Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
  • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
  • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
  • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
  • G11C11/409—Read-write [R-W] circuits 
  • G11C11/4094—Bit-line management or control circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
  • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
  • G11C11/409—Read-write [R-W] circuits 
  • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
  • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
  • G11C11/409—Read-write [R-W] circuits 
  • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines

Definitions

• the present invention is a memory device that uses semiconductor elements.
• DRAM Dynamic Random Access Memory
• SGT Square Gate Transistor
• Patent Document 1 and Non-Patent Document 1 a selection transistor and connects a capacitor
• PCM Phase Change Memory
• RRAM Resistive Random Access Memory
• Non-Patent Document 4 a resistive variable element
• MRAM Magnetic-resistive Random Access Memory
• DRAM memory cells (see Patent Document 2, Non-Patent Documents 6 to 10) that are composed of one MOS transistor without a capacitor.
• a DRAM memory cell composed of one MOS transistor for example, a group of holes and a group of electrons generated in a channel by the impact ionization phenomenon by a source-drain current of an N-channel MOS transistor are retained in the channel, and logical memory data "1" is written. Then, the group of holes is removed from the channel, and logical memory data "0" is written.
• the memory cell there are random memory cells with "1” written and memory cells with "0" written for a common selected word line.
• the floating body channel voltage of the selected memory cell connected to this selected word line fluctuates greatly due to the capacitive coupling between the gate electrode and the channel.
• the issues are to improve the decrease in operating margin due to the fluctuation in the floating body channel voltage, and to improve the decrease in data retention characteristics due to the removal of a part of the group of holes, which are the signal charges accumulated in the channel.
• Twin-Transistor MOS transistor memory element in which one memory cell is formed using two MOS transistors in an SOI layer (see, for example, Patent Documents 3 and 4, and Non-Patent Document 11).
• an N + layer which serves as a source or drain and separates the floating body channels of the two MOS transistors, is formed in contact with an insulating layer on the substrate side.
• This N + layer electrically separates the floating body channels of the two MOS transistors.
• a group of holes which is a signal charge, is stored only in the floating body channel of one MOS transistor.
• the other MOS transistor serves as a switch for reading out the group of holes of the signal stored in the other MOS transistor.
• the group of holes which is a signal charge
• the problem is to improve the decrease in the operating margin or to improve the decrease in data retention characteristics caused by removing part of the group of holes, which is the signal charge stored in the channel.
• FIG. 3 there is a dynamic flash memory (DFM) cell 111 shown in FIG. 3, which is composed of a MOS transistor without a capacitor (see Patent Document 5 and Non-Patent Document 12).
• DFM dynamic flash memory
• FIG. 3(a) there is a floating body semiconductor body 102 on a SiO 2 layer 101 of an SOI substrate. At both ends of the floating body semiconductor body 102, there is an N + layer 103 connected to a source line SL and an N + layer 104 connected to a bit line BL .
• first gate insulating layer 109a connected to the N + layer 103 and covering the floating body semiconductor body 102
• second gate insulating layer 109b connected to the first gate insulating layer 109a via the N + layer 104 and the slit insulating film 110 and covering the floating body semiconductor body 102.
• first gate conductor layer 105a covering the first gate insulating layer 109a and connected to the plate line PL
• second gate conductor layer 105b covering the second gate insulating layer 109b and connected to the word line WL.
• slit insulating layer 110 between the first gate conductor layer 105a and the second gate conductor layer 105b. This forms a memory cell 111 of the DFM. It is also possible to configure the source line SL to be connected to the N + layer 104, and the bit line BL to be connected to the N + layer 103.
• a zero voltage is applied to the N + layer 103, and a positive voltage is applied to the N + layer 104, so that the first N-channel MOS transistor region made of the floating body semiconductor body 102 covered with the first gate conductor layer 105a is operated in the saturation region, and the second N-channel MOS transistor region made of the floating body semiconductor body 102 covered with the second gate conductor layer 105b is operated in the linear region.
• no pinch-off point exists in the second N-channel MOS transistor region, and an inversion layer 107b is formed over the entire surface.
• the inversion layer 107b formed under the second gate conductor layer 105b connected to the word line WL acts as a substantial drain of the first N-channel MOS transistor region.
• the memory write operation is performed by removing the electrons from the electron-hole group generated by the impact ionization phenomenon from the floating body semiconductor body 102 and retaining some or all of the hole group 106 in the floating body semiconductor body 102. This state becomes logical storage data "1".
• a positive voltage is applied to the plate line PL
• a zero voltage is applied to the word line WL and the bit line BL
• a negative voltage is applied to the source line SL to remove the hole group 106 from the floating body semiconductor body 102 to perform an erase operation.
• This state becomes logical memory data "0".
• the voltage applied to the first gate conductor layer 105a connected to the plate line PL is set to be higher than the threshold voltage when the logical memory data is "1" and lower than the threshold voltage when the logical memory data is "0", thereby obtaining a characteristic in which no current flows even if the voltage of the word line WL is increased when reading logical memory data "0", as shown in FIG. 3(d).
• This characteristic allows a significant expansion of the operating margin compared to a DRAM memory cell composed of a single MOS transistor without a capacitor.
• the channels of the first and second N-channel MOS transistor regions whose gates are the first gate conductor layer 105a connected to the plate line PL and the second gate conductor layer 105b connected to the word line WL, are connected by the floating body semiconductor body 102, so that the voltage fluctuation of the floating body semiconductor body 102 when a selection pulse voltage is applied to the word line WL is greatly suppressed.
• a dynamic flash memory cell 8 having three gates and composed of a MOS transistor without a capacitor is known (see Patent Document 6 and Non-Patent Document 13).
• a silicon semiconductor pillar (Si pillar) 2 is provided on a substrate 1.
• the Si pillar 2 has an N+ layer 3a, a P layer 7, and an N+ layer 3b from below.
• the P layer 7 between the N+ layers 3a and 3b becomes a channel region 7a.
• Surrounding the Si pillar 2 from below are a first gate insulating layer 4a, a second gate insulating layer 4b, and a third gate insulating layer 4c.
• first gate conductor layer 5a Surrounding the first gate insulating layer 4a is a first gate conductor layer 5a, surrounding the second gate insulating layer 4b is a second gate conductor layer 5b, and surrounding the third gate insulating layer 4c is a third gate conductor layer 5c.
• the first gate conductor layer 5a and the second gate conductor layer 5b are separated by an insulating layer 6a, and the second gate conductor layer 5b and the third gate conductor layer 5c are separated by an insulating layer 6b.
• a feature of this structure is that the recombination of the holes stored in the channel region 7a between the N+ layers 3a and 3b is significantly suppressed in the N+ layers 3a and 3b by utilizing the electrical shielding between the first gate conductor layer 5a and the third gate conductor layer 5c. As a result, the retention characteristic of data "1" is significantly improved.
• the dynamic flash memory cells can be arranged horizontally on the substrate 1, and multiple memory cells can be stacked vertically to increase the degree of integration (see Patent Document 8).
• the first gate conductor layer 5a, the second gate conductor layer 5b, and the third gate conductor layer 5c can be divided (see, for example, Patent Document 9 and Non-Patent Document 18).
• Non-Patent Documents 14 and 15 a thyristor RAM memory with three gates and no capacitor has been announced (see Non-Patent Documents 14 and 15).
• This thyristor memory has the advantage that the equivalent memory cell size can be reduced by stacking multiple layers, but because it uses a thyristor as the read mechanism, there is a problem that the read current value increases or decreases significantly, resulting in high power consumption.
• Non-Patent Documents 16 and 17 a 1T1C DRAM cell with a stackable capacitor has been announced (see Non-Patent Documents 16 and 17).
• the aspect ratio of the capacitor in a DRAM memory cell is large at 50. Therefore, when a DRAM cell is placed horizontally, the area of this capacitor is very large, and in order to obtain an equivalent area to an economical memory cell like a current vertically placed DRAM cell, for example, 200 layers must be stacked.
• Critoloveanu “A Compact Capacitor-Less High-Speed DRAM Using F ield Effect-Controlled Charge Regeneration,” Electron Device Letters, Vol. 35, No.2, pp.179-181 (2012) T. Ohsawa, K. Fujita, T. Higashi, Y. Iwata, T. Kajiyama, Y. Asao, and K. Sunouchi: “Memory d esign using a one-transistor gain cell on SOI,” IEEE JSSC, vol.37, No.11, pp1510-1522 (2002). T. Shino, N. Kusunoki, T. Higashi, T. Ohsawa, K. Fujita, K. Hatsuda, N.
• a first aspect of the present invention provides a memory cell array including a plurality of semiconductor memory cells, each of which includes a first memory cell and a second memory cell, arranged in a matrix on a substrate;
• the first memory cell includes a first semiconductor body extending in a first direction parallel to the substrate, and the second memory cell includes a second semiconductor body separated from the first semiconductor body in a vertical or horizontal direction, and overlapping the first semiconductor body in a plan view when separated in the vertical direction, and overlapping the first semiconductor body in a cross-sectional view when separated in the horizontal direction; a first impurity region and a second impurity region connected to both ends of the first semiconductor body, a third impurity region and a fourth impurity region respectively connected to both ends of the second semiconductor body; a first gate insulating layer in contact with a side surface of the first semiconductor body that faces the second semiconductor body, and a second gate insulating layer in contact with a side surface of the second semiconductor body that faces the first semiconductor body; a
• a second invention of the present application is the transistor according to the first invention, further comprising: the first impurity region is connected to a first source line; the third impurity region is connected to a second source line; the second and fourth impurity regions are connected to bit lines; one of the first gate conductor layer and the second gate conductor layer is connected to a first select gate line; and the other is connected to a plate line; The data erase operation, the data write operation, and the data read operation are performed by controlling voltages applied to the first and second source lines, the bit line, the plate line, and the select gate line.
• the third invention of the present application is the second invention described above, characterized in that, in the data write inhibit operation, the same voltage is applied to the first or second source line and the bit line.
• the fourth invention of the present application is the second invention described above, characterized in that the same voltage is applied to the first or second source line and the bit line during the data read operation.
• the sixth invention of the present application is characterized in that in the second invention, the bit line is perpendicular to the plate line and the select gate line in a vertical cross-sectional view relative to the substrate, and the first and second source lines are arranged perpendicularly in a plan view and parallel to the plate line and the select gate line.
• the seventh invention of the present application is characterized in that in the second invention described above, the first and second semiconductor bodies overlap when viewed from above, and the plate line and the select gate line are arranged perpendicular to and parallel to the substrate when viewed from a cross section.
• the eighth invention of the present application is characterized in that in the second invention, the bit line is perpendicular to the plate line and the select gate line in a plan view of the substrate, and the first and second source lines are arranged perpendicular to the plate line and the select gate line in a cross-sectional view.
• the ninth invention of the present application is characterized in that, in the second invention described above, the first select gate line is composed of a separated second select gate line and a third select gate line, one of the first gate conductor layer and the second gate conductor layer is divided into two, one of the divided gate conductor layers is connected to the second select gate line and the other is connected to the third select gate line, and the undivided first gate conductor layer or the second gate conductor layer is connected to the plate line, and the two gate conductor layers connected to the second select gate line and the third select gate line are arranged on both sides of the gate conductor layer connected to the plate line.
• the tenth invention of the present application is characterized in that in the ninth invention, the channel length of the gate conductor layer connected to the plate line is longer than the channel length of the gate conductor layer connected to the second select gate line and the third select gate line.
• the eleventh invention of the present application is characterized in that in the first invention described above, a plurality of semiconductor memory cells are arranged in a matrix on a substrate to form a memory block, and a plurality of the memory blocks are selected during at least one of the data write operation, the data erase operation, and the data read operation.
• dynamic flash memory The structure and driving method of a memory device using semiconductor elements (hereafter referred to as dynamic flash memory) according to the present invention will be explained below with reference to the drawings.
• FIG. 1G A structure in which a bit line 18 (BL) is disposed vertically with respect to a substrate 10, and first and second select gate lines 11 (SG1), 13 (SG2), and a plate line 12 (PL) are disposed horizontally will be described with reference to Figure 1A and 1B.
• a structure in which a bit line 18a (BL) is disposed horizontally with respect to a substrate, and first and second select gate lines 11a (SG1), 13a (SG2), and a plate line 12a (PL) are disposed vertically will be described with reference to Figure 1G.
• FIG. 1 An equivalent circuit diagram of a dynamic flash memory cell according to the first embodiment of the present invention, in which four layers are stacked on a substrate 10 in a plan view or cross-sectional view, and data write operation, data write inhibit operation, and data read operation will be described with reference to Figures 2A to 2C.
• FIG. 1A shows a bird's-eye view of the dynamic flash memory cell structure according to the first embodiment of the present invention.
• FIG. 1B(a) shows a plan view of the dynamic flash memory cell structure according to the first embodiment of the present invention
• FIG. 1B(b) and FIG. 1B(c) show a cross-sectional view along the X-X' line direction and a cross-sectional view along the Y-Y' line direction shown in FIG. 1B(a), respectively.
• Patent Document 8 is a document relating to a structure in which a dynamic flash memory cell is provided in a horizontal direction relative to a substrate 10.
• N + layer 15 an example of the "first impurity region” in the claims
• N + layer 16 an example of the "second impurity region” in the claims.
• a second semiconductor body 19 an example of the "second semiconductor body” in the claims) of a P layer, an N + layer 20 (an example of the “third impurity region” in the claims), and an N + layer 21 (an example of the "fourth impurity region” in the claims) are provided on the upper layer side of the first semiconductor body 14.
• the first gate conductor layer 11 (an example of the "first gate conductor layer” in the claims), the second gate conductor layer 12 (an example of the “second gate conductor layer” in the claims), and the third gate conductor layer 13 (an example of the "third gate conductor layer” in the claims), which are separated from each other, are in contact with the first side (an example of the "first side” in the claims) and the second side (an example of the "second side” in the claims) of the first gate insulating layer 23 and the second gate insulating layer 24, respectively.
• three gate conductor layers, the first to third gate conductor layers are shown in Figures 1A to 1C, Figures 1F and 1G, and Figures 2A and 2B, two gate conductor layers may be used.
• either the first gate conductor layer 11 or the third gate conductor layer 13 may be omitted as shown in Figures 1D and 1E, respectively.
• the first impurity region 15 and the third impurity region 20 are connected to SL0, which is the first source line 17 (an example of the "first source line” in the claims), and SL1, which is the second source line 22 (an example of the "second source line” in the claims), respectively, and the second impurity region 16 and the fourth impurity region 21 are connected to BL, which is the bit line 18 (an example of the "bit line” in the claims).
• the five terminals of the first memory cell are composed of a second select gate line SG1, a plate line PL, a third select gate line SG2, a first source line SL0, and a bit line BL
• the five terminals of the second memory cell are composed of a second select gate line SG1, a plate line PL, a third select gate line SG2, a second source line SL1, and a bit line BL.
• the first source line SL0 applies the ground voltage Vss, applies a positive voltage to the bit line BL, and controls the voltages applied to the plate line PL, the second select gate line SG1, and the third select gate line SG2 to perform a data write operation (an example of a "data write operation” in the claims) or a data read operation (an example of a "data read operation” in the claims) for the first memory cell.
• the second source line SL1 applies the same voltage as the bit line BL.
• the second memory cell is in a data write inhibit operation (an example of a "data write inhibit operation" in the claims).
• the second memory cell does not perform a data read operation.
• the voltages applied to the first source line SL0, the second source line SL1, the bit line BL, the plate line PL, the second select gate line SG1, and the third select gate line SG2 are controlled to perform a data erase operation (an example of a "data erase operation" in the claims) on the first memory cell and the second memory cell.
• the first to third gate conductor layers 11, 12, 13 form a common gate conductor layer for two dynamic flash memory cells having channels in the first semiconductor body 14 and the second semiconductor body 19.
• the first gate insulating film 23 may be provided at least between the first to third gate conductor layers 11, 12, 13 and the first semiconductor body 14.
• the second gate insulating film 24 may be provided at least between the first to third gate conductor layers 11, 12, 13 and the second semiconductor body 19.
• the channel length of the plate line PL (length in the X-X' direction) is shown to be the same as the lengths of the select gate lines SG1 and SG2.
• the channel length of the plate line PL (length in the X-X' direction) may be longer than the select gate lines SG1 and SG2. This provides better control over the plate line voltage for the floating body of the memory cell. Also, depending on the channel length (gate length) of the plate line, more holes can be held in the floating body in the "1" write state.
• Figure 1D shows an example in which the second select gate line SG1 adjacent to the first source line SL0 and the second source line SL1 is eliminated. That is, the structure is made up of the third select gate line SG2, which is the first select gate line that is not divided (an example of the "first select gate line” in the claims), and the plate line PL.
• Figure 1E shows an example in which the third select gate line SG2 adjacent to the bit lines BL0 and BL1 is eliminated. That is, the structure is made up of the second select gate line SG1, which is the first select gate line that is not divided, and the plate line PL. This allows the cell size of the dynamic flash memory cell to be further miniaturized. Also, the cell current can be increased, making it possible to achieve higher speeds.
• FIG. 1F shows an example of stacking three dynamic flash memory cells.
• a third semiconductor body 28 is above the second semiconductor body 19. Between the second semiconductor body 19 and the third semiconductor body 28, there are a first gate conductor layer 25 connected to a select gate line SG11, a second gate conductor layer 26 connected to a plate line PL1, and a third gate conductor layer 27 connected to a select gate line SG21.
• N + layers 29 and 30 are located on both ends of the third semiconductor body 28.
• the N + layer 29 is connected to a source line 31 (SL3), and the N + layer 30 is connected to a bit line 18 (BL).
• the first source line 17 (SL0), the second source line 22 (SL1), and the third source line 31 (SL2) are each selected by a decoder circuit (not shown).
• Figure 1G shows an example in which the second select gate line SG1, plate line PL, third select gate line SG2, and source line SL are arranged vertically with respect to the substrate 10, and the bit line BL is arranged horizontally.
• the dynamic flash memory cell shown in Figures 1A to 1F rotated 90 degrees toward the back of the drawing with respect to the substrate 10.
• Either one can be selected depending on the application, but the main features of the dynamic flash memory cell in Figure 1G are the same as those of the dynamic flash memory cell shown in Figures 1A to 1F.
• FIG. 2A shows an equivalent circuit diagram of a dynamic flash memory cell according to the first embodiment of the present invention, in which four memory cells Cell0 to Cell3 are stacked on a substrate in plan view or cross-sectional view.
• FIG. 2B shows the operation waveforms of the data write operation, data write inhibit operation, and data read operation of the four memory cells Cell0 to Cell3.
• the bit line BL, the second select gate line SG11, the plate line PL1, the third select gate line SG21, and the second source line SL2 are respectively changed from the ground voltage Vss to the first voltage V1, the second voltage V2, the third voltage V3, the fourth voltage V4, and the first voltage V1, and the second source line SL1 is set to the ground voltage Vss, the second memory cell Cell1 is selected, and the data write operation or data read operation is performed in the second memory cell Cell1.
• the third memory cell Cell2 when the third source line SL2 is applied with the first voltage V1, which is the same voltage as the bit line BL, the third memory cell Cell2 is prohibited from writing data while the second memory cell Cell1 is performing a data write operation. Furthermore, while the second memory cell Cell1 is performing a data read operation, the third memory cell Cell2 is not permitted to read data. In other words, multiple selection of the second memory cell Cell1 and the third memory cell Cell2 is prohibited.
• FIG. 2C shows a bird's-eye view of the equivalent circuit diagram of FIG. 2B, with the bit line array increased in the depth direction to BLn.
• bit line array is 1024 lines.
• a data write operation is simultaneously performed from a sense amplifier circuit (not shown) to this bit line array, or a data read operation is simultaneously performed to the sense amplifier circuit.
• dynamic flash memory cells shown in Figures 1A to 1G and 2A to 2C have been described using components with a rectangular vertical cross section, these vertical cross sections may be other shapes, such as a trapezoidal shape. Furthermore, the vertical cross sections of each component may be different. This is the same for the other embodiments.
• Dynamic flash memory operation can also be performed in a structure in which the conductivity of the semiconductor body of the N + layers 15, 16, 20, 21 and the P layers 14, 19 of the dynamic flash memory cell shown in Figures 1A and 1B is reversed.
• the N-type semiconductor body the majority carriers become electrons. Therefore, a group of electrons generated by impact ionization is stored in the floating body, and the "1" state is set.
• dynamic flash memory cells using a P-type semiconductor body and an N-type semiconductor body may be formed on the same substrate. This is the same in other embodiments.
• the dynamic flash memory cell shown in Figures 1A and 1B may have a junctionless structure in which the conductivity of the semiconductor body of the N + layers 15, 16, 20, and 21 and the P layers 14 and 19 are made the same. This is the same for the other embodiments.
• dynamic flash memory cells shown in Figures 1A to 1G and 2A to 2C may be arranged in a matrix on a substrate to form memory blocks, and multiple memory blocks may be selected during at least one of the data write, data erase, and data read operations.
• the number of memory cells selected in multiple memory blocks increases, making it possible to write data, erase data, and read data faster per cell.
• the second select gate line SG1, the plate line PL, and the third select gate line SG2 of the two stacked memory cells are shared, so that the aspect ratio of the stacked memory cells is reduced, and therefore a larger number of memory cells can be stacked, and cost reduction can be achieved. This is also true for the memory cells shown in Figures 1C to 2C. Then, by independently operating the first source line SL0 and the second source line SL1 of the two stacked memory cells Cell0 and Cell1, while one memory cell is performing a data write operation, the other memory cell is in a data write inhibit operation. Also, while one memory cell is performing a data read operation, the other memory cell is not performing a data read operation.
• the gate conductor layer connected to the plate line may be a single layer or a combination of multiple conductor material layers.
• the gate conductor layer connected to the second and third select gate lines may be a single layer or a combination of multiple conductor material layers.
• the outside of the gate conductor layer may be connected to a wiring metal layer such as W. This also applies to other embodiments of the present invention.
• the voltage applied to the plate line PL in the description of the embodiment may be a fixed voltage of, for example, 0 V, regardless of the operating mode.
• the voltage applied to the plate line PL may be a fixed voltage or a voltage that changes over time, as long as the voltage satisfies the conditions for dynamic flash memory operation.
• an N-type or P-type impurity region may be present between the first impurity region N + layer 15 and/or the second impurity region N + layer 16 and the first semiconductor body P layer 14. This also applies to other embodiments of the present invention.
• the memory device using semiconductor elements according to the present invention provides a high-density, high-performance dynamic flash memory.

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• 2023
  • 2023-10-06 WO PCT/JP2023/036523 patent/WO2025074607A1/ja active Pending
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