WO2025074578A1 - プリント配線板 - Google Patents

プリント配線板 Download PDF

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Publication number
WO2025074578A1
WO2025074578A1 PCT/JP2023/036389 JP2023036389W WO2025074578A1 WO 2025074578 A1 WO2025074578 A1 WO 2025074578A1 JP 2023036389 W JP2023036389 W JP 2023036389W WO 2025074578 A1 WO2025074578 A1 WO 2025074578A1
Authority
WO
WIPO (PCT)
Prior art keywords
thermal expansion
conductor
printed wiring
wiring board
low thermal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/JP2023/036389
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
洋平 伊藤
謙二郎 高西
竜也 坂本
等 新井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2024514459A priority Critical patent/JP7493695B1/ja
Priority to PCT/JP2023/036389 priority patent/WO2025074578A1/ja
Publication of WO2025074578A1 publication Critical patent/WO2025074578A1/ja
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Definitions

  • This disclosure relates to printed wiring boards.
  • Printed wiring boards with cores are known as a conventional technology for reducing the thermal expansion difference between a printed wiring board and mounted components.
  • Patent Document 1 discloses a package substrate.
  • a low-thermal expansion metal is used as a core
  • build-up wiring layers are laminated on both sides of the core
  • a semiconductor chip is flip-chip connected to the package substrate, with multiple through holes (or slits) formed in the core.
  • the purpose of this disclosure is to make it possible to control the thermal expansion coefficient of a printed wiring board to match the thermal expansion coefficient of each component to be mounted.
  • the printed wiring board of the present disclosure is a printed wiring board having multiple layers, Two surface conductor layers formed on the upper and lower surfaces of the printed wiring board; One or more internal conductor layers formed inside the printed wiring board; a plurality of insulating layers electrically insulating the two surface conductor layers from the one or more internal conductor layers; having the one or more internal conductor layers include one or more low thermal expansion conductor layers having conductor portions formed of conductors having a thermal expansion coefficient lower than that of the conductors of the two surface conductor layers; At least one of the one or more low thermal expansion conductor layers has two or more regions in the conductor portion where a plurality of through holes are provided, The two or more regions have different hole densities from one another.
  • two or more regions with different hole densities are provided in the low thermal expansion conductor layer of the printed wiring board, making it possible to control the thermal expansion coefficient of the printed wiring board to match the thermal expansion coefficient of each component to be mounted.
  • FIG. 1 is a partial cross-sectional view of a printed wiring board 100 according to a first embodiment.
  • 1 is a partial cross-sectional view of a printed wiring board 100 according to a first embodiment.
  • FIG. 4 is a partial plan view of a low thermal expansion conductor layer 112a according to the first embodiment.
  • FIG. 4 is a partial plan view of a low thermal expansion conductor layer 112b in the first embodiment.
  • FIG. 2 is a partial plan view of a low thermal expansion conductor layer 112 in the first embodiment.
  • FIG. 2 is a partial plan view of a low thermal expansion conductor layer 112 in the first embodiment.
  • FIG. 1 is a partial cross-sectional view of a printed wiring board 100 according to an embodiment.
  • FIG. 1 is a partial cross-sectional view of a printed wiring board 100 according to an embodiment.
  • FIG. 1 is a partial cross-sectional view of a printed wiring board 100 according to an embodiment.
  • FIG. 1 is a partial cross-sectional view of a printed wiring board 100 according to an embodiment.
  • FIG. 1 is a partial cross-sectional view of a printed wiring board 100 according to an embodiment.
  • FIG. 1 is a partial cross-sectional view of a printed wiring board 100 according to an embodiment.
  • FIG. 1 is a partial cross-sectional view of a printed wiring board 100 according to an embodiment.
  • FIG. 4 is a partial plan view of a low thermal expansion conductor layer 112 in the embodiment.
  • FIG. 4 is a partial plan view of a low thermal expansion conductor layer 112b in the embodiment.
  • FIG. 4 is a partial plan view of a low thermal expansion conductor layer 112 in the embodiment.
  • Embodiment 1 The printed wiring board 100 will be described with reference to FIGS.
  • the configuration of a printed wiring board 100 will be described with reference to FIGS.
  • the printed wiring board 100 is a printed wiring board having multiple layers (a multi-layer printed wiring board).
  • the printed wiring board 100 has two surface conductor layers 111 .
  • a printed wiring board 100 has a surface conductor layer 111a and a surface conductor layer 111b.
  • the surface conductor layers 111 are conductor layers formed on the top and bottom surfaces of the printed wiring board 100 .
  • the conductor layer is a layer having a portion formed of a conductor (conductor portion).
  • the conductor of the surface conductor layer 111 is referred to as the wiring conductor 101.
  • the printed wiring board 100 has one or more internal conductor layers.
  • the internal conductor layer is a conductor layer formed inside the printed wiring board 100 .
  • the low thermal expansion conductor layer 112 and the same type conductor layer 113 are each an internal conductor layer.
  • the conductor of the low thermal expansion conductor layer 112 has a thermal expansion coefficient lower than that of the wiring conductor 101.
  • the conductor of the low thermal expansion conductor layer 112 is referred to as a low thermal expansion conductor 102.
  • the conductor of the same type conductor layer 113 is the same type of conductor as the conductor of the surface conductor layer 111 .
  • a printed wiring board 100 has two low thermal expansion conductor layers 112 and two conductor layers 113 of the same type.
  • Each of the low thermal expansion conductor layers 112a and 112b is composed of a low thermal expansion conductor 102 and an insulating material 103.
  • the portion of the low thermal expansion conductor layer 112 shown in Fig. 1 is a conductor portion, the portion formed of the insulating material 103 (insulating portion) is not shown in the low thermal expansion conductor layer 112 in Fig. 1.
  • Each of the same-type conductor layers 113 a and 113 b is composed of a wiring conductor 101 and an insulating material 103 .
  • At least one of the same type conductor layers 113 is disposed between two low thermal expansion conductor layers 112 .
  • the same type conductor layer 113a and the same type conductor layer 113b are disposed between the low thermal expansion conductor layer 112a and the low thermal expansion conductor layer 112b.
  • the printed wiring board 100 has a plurality of insulating layers 114 .
  • the multiple insulating layers 114 electrically insulate the two surface conductor layers 111 from the one or more internal conductor layers.
  • the insulating layer 114 is a layer formed from the insulating material 103 inside the printed wiring board 100 .
  • the printed wiring board 100 has five insulating layers 114 .
  • the insulating layer 114a is disposed on the inner surface of the surface conductor layer 111a.
  • the low thermal expansion conductor layer 112a is disposed on the inner surface of the insulating layer 114a.
  • the insulating layer 114a insulates the surface conductor layer 111a from the low thermal expansion conductor layer 112a.
  • the insulating layer 114b is disposed on the inner surface of the low thermal expansion conductor layer 112a.
  • the same type conductor layer 113a is disposed on the inner surface of the insulating layer 114b.
  • the insulating layer 114b insulates the low thermal expansion conductor layer 112a from the same type conductor layer 113a.
  • the insulating layer 114c is disposed on the inner surfaces of the same-type conductor layers 113a and 113b, and insulates the same-type conductor layers 113a and 113b from each other.
  • the insulating layer 114d is disposed on the inner surface of the low thermal expansion conductor layer 112d.
  • the same type conductor layer 113b is disposed on the inner surface of the insulating layer 114d.
  • the insulating layer 114d insulates the same type conductor layer 113b from the low thermal expansion conductor layer 112b.
  • the insulating layer 114e is disposed on the inner surface of the surface conductor layer 111b.
  • the low thermal expansion conductor layer 112b is disposed on the inner surface of the insulating layer 114e.
  • the insulating layer 114e insulates the low thermal expansion conductor layer 112b from the surface conductor layer 111b.
  • the through holes 119 are formed of the same type of conductor as the conductor of the surface conductor layers 111, and electrically connect the two surface conductor layers 111 to at least one of the internal conductor layers.
  • the wiring conductor 101 of the through hole 119 electrically connects the wiring conductors 101 of the two surface conductor layers 111 to the low thermal expansion conductor 102 of at least one of the low thermal expansion conductor layers 112 .
  • the wiring conductors 101 of the through holes 119 are electrically connected to the wiring conductors 101 of the respective surface conductor layers 111, the low thermal expansion conductors 102 of the respective low thermal expansion conductor layers 112, and the wiring conductors 101 of the respective same type conductor layers 113.
  • the thickness of a portion of the low thermal expansion conductor layer 112 is different from the thickness of the other portion.
  • a portion of each of the low thermal expansion conductor layers 112a and 112b is thinner than the other portion.
  • At least one of the low thermal expansion conductor layers 112 has one or more regions 120 in its conductor portion.
  • the regions 120 are regions in which a plurality of through holes 121 are provided.
  • the low thermal expansion conductor layer 112a has a region 120a and a region 120b in the conductor portion.
  • a plurality of through holes 121 are provided in each of the regions 120a and 120b.
  • the region 120 is located at the same position in the planar direction as either of the component mounting regions of the two surface conductor layers 111.
  • the component mounting region is a region where components are mounted. 3
  • a region 120a is a region immediately below the component mounting region a of the surface conductor layer 111a
  • a region 120b is a region immediately below the component mounting region b of the surface conductor layer 111a.
  • At least one of the low thermal expansion conductor layers 112 has two or more regions 120 in its conductor portion.
  • the two or more regions 120 have different hole densities.
  • the hole density is also called porosity.
  • the hole density of region 120a is different from the hole density of region 120b.
  • the printed wiring board 100 has two or more low thermal expansion conductor layers 112 each having a region 120 in a conductor portion, the positions of the regions being different from each other in the planar direction. 4, the low thermal expansion conductor layer 112b has in its conductor portion a region 120c in which a plurality of through holes 121 are provided.
  • the region 120c is a region immediately above the component mounting region c of the surface conductor layer 111b.
  • the region 120c of the low thermal expansion conductor layer 112b is located at a different position in the planar direction from the regions (120a, 120b) of the low thermal expansion conductor layer 112a.
  • a plurality of through holes 129 are provided in the conductor portion around at least one of the regions 120, the hole density of which gradually changes with increasing distance from the region 120.
  • the low thermal expansion conductor layer 112 has a region 120d in the conductor portion where a plurality of through holes 121 are provided.
  • a plurality of through holes 129 are provided around the region 120d in the conductor portion. The diameter of the through holes 129 becomes smaller with increasing distance from the region 120d. As a result, the hole density around the region 120d gradually decreases with increasing distance from the region 120d. In FIG. 5, the diameter of the through hole 129 becomes smaller with increasing distance from the region 120d, but the diameter of the through hole 129 may become larger with increasing distance from the region 120d.
  • At least any one of the regions 120 has two or more compartments 122.
  • the compartments 122 are compartments in which a plurality of through holes 121 are provided.
  • the two or more compartments 122 have different hole densities from one another.
  • the low thermal expansion conductor layer 112 has a region 120e in the conductor portion.
  • the region 120e has a section 122a and a section 122b.
  • Each of the sections 122a and 122b is provided with a plurality of through holes 121.
  • the hole density of the section 122a and the hole density of the section 122b are different from each other.
  • the first embodiment provides a method for controlling the thermal expansion coefficient of a substrate to match the thermal expansion coefficient of a mounted component.
  • Two or more regions with different through-hole densities (void ratios) are provided in the conductor portion of the low thermal expansion conductor layer 112 of the printed wiring board 100. This makes it possible to adjust the thermal expansion coefficient of the printed wiring board 100 for each region where a component is mounted, and to reduce the difference in thermal expansion coefficient between the component and the printed wiring board 100. This makes it possible to keep the difference in thermal expansion coefficient below a predetermined value and to keep the strain generated in the solder joint of the component mounting portion below a certain level.
  • a through hole 121 is formed in a region 120 of the conductor portion of the low thermal expansion conductor layer 112 .
  • By changing the coefficient of thermal expansion it is possible to control the difference in the coefficient of thermal expansion between the region 120 and the mounted components.
  • by changing the porosity for each region 120 it is possible to change the apparent thermal expansion coefficient for each region 120, and to make the difference in thermal expansion coefficient between the region 120 and the mounted components corresponding to the region 120 the same for two or more regions 120. Therefore, it is possible to change the coefficient of thermal expansion directly below each mounted component, and to keep the difference in thermal expansion between the components and printed wiring board 100 constant over the entire substrate.
  • by keeping the difference in the thermal expansion coefficient between each mounted component and the printed circuit board directly below it at a specified value or less it is possible to keep the distortion occurring in the solder joints where the components are mounted at a constant level or less.
  • through holes 121 are formed in each region 120 of the two or more low thermal expansion conductor layers 112 to match the thermal expansion coefficient of the components to be mounted on each surface conductor layer 111. This makes it possible to adjust (match) the thermal expansion coefficient.
  • the positions of the through holes 121 of the two or more low thermal expansion conductor layers 112 do not have to match in the plate thickness direction.
  • the coefficient of thermal expansion differs within the component.
  • a component in which a plurality of chips are arranged in one package (for example, a multi-chip module)
  • the coefficient of thermal expansion differs within the component.
  • a component is mounted on the surface conductor layer 111, a plurality of sections 122 are provided in the region 120 corresponding to the component. This makes it possible to deal with the difference in thermal expansion coefficient within the component.
  • the first embodiment provides the following advantages.
  • In the printed wiring board 100 on which a plurality of different components are mounted it is possible to control the difference in thermal expansion coefficient between the mounted components and the substrate to a constant value.
  • In printed wiring board 100 on which a plurality of different components are mounted it is possible to control the strain occurring in the solder joints of the component mounting portion to a constant level.
  • By disposing the low thermal expansion conductor layer 112 near the surface the effect of controlling the thermal expansion coefficient by the low thermal expansion conductor 102 can be enhanced.
  • By electrically connecting the low thermal expansion conductor 102 to the wiring conductor 101 by the through hole 119 it is possible to prevent the low thermal expansion conductor 102 from having a floating potential.
  • the low thermal expansion conductor 102 it becomes possible to use the low thermal expansion conductor 102 as a heat path. Since the diameter of the through-hole 119 is constant within the same through-hole 119, it becomes possible to manufacture a multi-layer printed wiring board.
  • the positions of the regions 120 in two or more low thermal expansion conductor layers 112 differ in the planar direction, making it possible to control the thermal expansion coefficient in accordance with the components on both sides.
  • the thermal expansion coefficient can be gradually changed toward the region 120 for adjusting thermal expansion, thereby alleviating stress concentration.
  • the number of low thermal expansion conductor layers 112 may be one, or three or more.
  • the number of same-type conductor layers 113 is not limited to two.
  • the homogeneous conductor layer 113 may be disposed outside the low thermal expansion conductor layer 112 . However, it is desirable that there be little other material between the mounted component and the low thermal expansion conductor layer 112 when the component is mounted on the surface conductor layer 111. For this reason, it is desirable to dispose the low thermal expansion conductor layer 112 in a layer close to the surface conductor layer 111.
  • the layer structure of the printed wiring board 100 may be asymmetric in the thickness direction.
  • the low thermal expansion conductor layer 112, the same type conductor layer 113, and the insulating layer 114 have different coefficients of thermal expansion and elasticity. Therefore, when a temperature change occurs, different thermal stresses are generated inside the printed wiring board 100. If the layer structure of the printed wiring board 100 is asymmetric in the thickness direction, the entire board is likely to warp. Therefore, it is desirable that the layer structure of the printed wiring board 100 is symmetric in the thickness direction. In other words, it is desirable that the low thermal expansion conductor layer 112 and the same type conductor layer 113 are arranged symmetrically.
  • the conductor layer is often made of copper, but may also be made of silver paste, i.e., silver.
  • the printed wiring board 100 is a laminate of multiple materials. The overall thermal expansion coefficient of a laminate of n types of materials is calculated by calculating formula (1).
  • ⁇ denotes the coefficient of thermal expansion.
  • the subscript s refers to the entire substrate.
  • Vf indicates the volume fraction.
  • E denotes Young's modulus.
  • i indicates one of n types of materials.
  • the overall thermal expansion coefficient of the laminate is strongly influenced by the material (layer) with a high elastic modulus. Also, the overall thermal expansion coefficient of the laminate is strongly influenced by the material (layer) with a high volume fraction.
  • Copper composite materials are preferred materials for the low thermal expansion conductor layer 112 from the viewpoint of heat dissipation.
  • the above-mentioned copper composite materials are preferred materials for the low thermal expansion conductor layer 112 because they have high compatibility with the manufacturing process of the board that uses copper as the main conductor.
  • desirable materials include low thermal expansion alloys, negative thermal expansion materials, or composites of these.
  • An example of a low thermal expansion alloy is Invar alloy.
  • negative thermal expansion materials are bismuth nickel iron oxide and zirconium tungstate.
  • the thickness of the region 120 of the low thermal expansion conductor layer 112 may be varied in order to adjust the coefficient of thermal expansion of the conductor portion of the low thermal expansion conductor layer 112 . Additionally, the thickness around the periphery of region 120 may be gradually changed as one moves away from region 120 .
  • the through hole 119 does not need to be provided in the hole provided in the conductor portion.
  • no through-hole 119 is provided in the holes (areas surrounded by dashed lines) in the conductor portions of the low thermal expansion conductor layer 112a and the low thermal expansion conductor layer 112b.
  • At least one of the low thermal expansion conductor layers 112 may not have holes in the conductor portions. 13, holes are provided in the conductor portion of the low thermal expansion conductor layer 112a, whereas no holes are provided in the conductor portion of the low thermal expansion conductor layer 112b.
  • the hole in the conductor portion of the low thermal expansion conductor layer 112 is temporarily filled with the resin that constitutes the insulating material 103 during the manufacturing process of the printed wiring board 100.
  • the inside of the through hole or the hole becomes a cavity. It is also possible to fill the inside of the hole thereafter with a resin, a mixture of a functional filler and a resin, or a metal.
  • the functional filler include inorganic fillers such as alumina and conductive fillers such as silver-coated copper powder.
  • the hole density of the through holes may be adjusted by the size of the through holes, by the number of the through holes, or by both the size and the number.
  • the area 120 in which a plurality of through holes 121 are formed and located directly below the mounted component may be located in the low thermal expansion conductor layer 112b, which is far from the surface conductor layer 111a, rather than in the low thermal expansion conductor layer 112a, which is closer to the surface conductor layer 111a.
  • the through holes 121 may be provided in the entire low thermal expansion conductor layer 112, and the hole density in the region 120 may be lower than the hole density in the entire low thermal expansion conductor layer 112. Furthermore, at least some of the regions 120 may not have the through holes 121. 14, through holes 121 are provided throughout the entire low thermal expansion conductor layer 112. The hole density in region 120f is lower than the hole density throughout the entire low thermal expansion conductor layer 112. Furthermore, no through holes 121 are provided in region 120g. In this manner, the thermal expansion coefficient may be changed by lowering the hole density.
  • the regions 120 in the planar direction are different in two or more low thermal expansion conductor layers 112
  • at least a portion of the regions 120 may overlap each other in the planar direction.
  • the region 120 of one low thermal expansion conductor layer 112 may be included in the region 120 of the other low thermal expansion conductor layer 112 in the planar direction, and the entire region 120 of one low thermal expansion conductor layer 112 may overlap a portion of the region 120 of the other low thermal expansion conductor layer 112 in the planar direction.
  • a portion of the region 120h of the low thermal expansion conductor layer 112b overlaps with the region 120b of the low thermal expansion conductor layer 112a.
  • the shape of the through holes 121 may be any of a circle, an ellipse, a rectangle, or other shapes.
  • the shape of at least any of the through holes 121 may be different from the shape of the other through holes 121 in the same region 120.
  • the shape of the through holes 121 in at least any of the regions 120 may be different from the shape of the through holes 121 in the other regions 120.
  • the through holes 121 may have different lengths in the vertical and horizontal directions.
  • the longitudinal directions of the multiple through holes 121 may be aligned in one direction, or may be irregular in two or more directions.
  • the shape of the through holes 121 in the region 120 is a rectangle, not a circle.
  • the length and width of the through holes 121 are different.
  • the longitudinal directions of the eight through holes 121 in the region 120 are aligned in one direction (the vertical direction).
  • anisotropy occurs in the thermal expansion coefficient of the region 120. Since the hole density is low in the horizontal direction of the region 120 and high in the vertical direction of the region 120, the thermal expansion coefficient in the horizontal direction of the region 120 is higher than the thermal expansion coefficient in the vertical direction.
  • the thermal expansion coefficient of the mounted component is anisotropic, it is possible to adjust the thermal expansion coefficient of the printed wiring board 100 to match the thermal expansion coefficient of the mounted component by changing the aspect ratio of the through hole 121 .
  • the first embodiment is an example of a preferred embodiment and is not intended to limit the technical scope of the present disclosure.
  • the first embodiment may be implemented partially, may be implemented in combination with at least one of the embodiments, or may be implemented in combination with other embodiments or other embodiments.
  • 100 printed wiring board 101 wiring conductor, 102 low thermal expansion conductor, 103 insulating material, 111 surface conductor layer, 112 low thermal expansion conductor layer, 113 homogeneous conductor layer, 114 insulating layer, 119 through hole, 120 area, 121 through hole, 122 partition, 129 through hole.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
PCT/JP2023/036389 2023-10-05 2023-10-05 プリント配線板 Pending WO2025074578A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2024514459A JP7493695B1 (ja) 2023-10-05 2023-10-05 プリント配線板
PCT/JP2023/036389 WO2025074578A1 (ja) 2023-10-05 2023-10-05 プリント配線板

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Application Number Priority Date Filing Date Title
PCT/JP2023/036389 WO2025074578A1 (ja) 2023-10-05 2023-10-05 プリント配線板

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0653684A (ja) * 1992-07-29 1994-02-25 Hitachi Ltd 薄膜多層配線基板とそれを用いたモジュール
JPH0750484A (ja) * 1993-08-06 1995-02-21 Mitsubishi Electric Corp 多層プリント配線板
JP2000124612A (ja) * 1998-01-19 2000-04-28 Toshiba Corp 配線基板とその製造方法、その配線基板を具える電気機器
JP2004253738A (ja) 2003-02-21 2004-09-09 Toshiba Corp パッケージ基板及びフリップチップ型半導体装置
JP2008091552A (ja) * 2006-09-29 2008-04-17 Fujitsu Ltd プリント配線板およびプリント基板ユニット並びに電子機器
JP2011071454A (ja) * 2009-09-23 2011-04-07 Samsung Electro-Mechanics Co Ltd パッケージ基板

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7558683B2 (ja) * 2019-06-03 2024-10-01 三菱電機株式会社 プリント配線板装置およびその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0653684A (ja) * 1992-07-29 1994-02-25 Hitachi Ltd 薄膜多層配線基板とそれを用いたモジュール
JPH0750484A (ja) * 1993-08-06 1995-02-21 Mitsubishi Electric Corp 多層プリント配線板
JP2000124612A (ja) * 1998-01-19 2000-04-28 Toshiba Corp 配線基板とその製造方法、その配線基板を具える電気機器
JP2004253738A (ja) 2003-02-21 2004-09-09 Toshiba Corp パッケージ基板及びフリップチップ型半導体装置
JP2008091552A (ja) * 2006-09-29 2008-04-17 Fujitsu Ltd プリント配線板およびプリント基板ユニット並びに電子機器
JP2011071454A (ja) * 2009-09-23 2011-04-07 Samsung Electro-Mechanics Co Ltd パッケージ基板

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