CN112582370A - 覆晶封装基板及其制作方法 - Google Patents
覆晶封装基板及其制作方法 Download PDFInfo
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- CN112582370A CN112582370A CN202010928505.XA CN202010928505A CN112582370A CN 112582370 A CN112582370 A CN 112582370A CN 202010928505 A CN202010928505 A CN 202010928505A CN 112582370 A CN112582370 A CN 112582370A
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- core structure
- flip chip
- layer
- conductive
- insulating
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Abstract
一种覆晶封装基板及其制作方法,该覆晶封装基板包括于中间层的相对两侧上分别叠设绝缘层,以形成复合式核心结构,从而增加该覆晶封装基板的刚性强度,促使本发明的核心结构能朝薄型化设计,且其中导电结构的端面尺寸又可依需求朝微小化设计,因而能增加单位面积内电性连接点的数量,以及制作出细线路间距及高布线密度的线路结构,进而能满足高集成芯片/大尺寸基板的封装需求,以及还可避免电子封装件发生弯翘。
Description
技术领域
本发明有关一种封装基板,特别涉及一种半导体覆晶封装工艺用的覆晶封装基板及其制作方法。
背景技术
随着产业应用的发展,近年来逐渐朝向5G高频通信、AR、VR等发展,因此更需要研发高阶半导体的封装技术,以应用于如人工智能(AI)芯片、高阶芯片、多芯片等的半导体覆晶封装或多芯片封装,而在此封装需求之下,封装尺寸势必越来越大,叠层数也越来越高,导致线路设计更是朝高密度、细线路间距、高电性连接点数等方向设计,借以满足上述芯片的封装需求。
目前在高阶芯片封装及应用的缺点是现有的覆晶封装基板,因为要配合高集成尺寸芯片(如AI芯片等)的封装,为了满足更多的电性连接点数量、大量且复杂的线路需求,以及避免板翘现象的发生,所以势必要加厚核心结构尺寸,但也因而造成其穿孔(Throughhole)的断面尺寸变大,致使其电性连接点的间距也变大,故导致在单位面积内的电性连接点数量变少、线路密度变低、线路间距变大,而为了满足上述需求,只好将覆晶封装基板的尺寸变得更大、更厚,因而造成封装作业变得更加的困难。
因此,现有业界是使用大尺寸的覆晶封装基板,如45x45mm2、70x70mm2或80x80mm2等大尺寸覆晶封装基板结构,以承载如人工智能(AI)芯片、高阶芯片或多芯片等高集成尺寸芯片来进行封装。如图1A所示,该电子装置1包括:一电路板18、一设于该电路板18上的大尺寸版面覆晶封装基板1a、以及一结合于该覆晶封装基板1a上的高集成尺寸半导体芯片19。具体地,如图1B所示,该覆晶封装基板1a包括一核心结构10、设于该核心结构10上、下两侧面上的增层(Build up)结构11、及设于该增层结构11上的防焊层12,其中,该核心结构10具有导电通孔100以电性连接该增层结构11的线路层110,且该增层结构11还包含至少一包覆该线路层110的介电层111,并令该防焊层12外露出该增层结构11最外侧的线路层110,以供作为电性连接点112,以借由焊锡材料13结合该电路板18及该半导体芯片19。
现有核心结构10的制作中,采用玻纤配合环氧树脂所组成的基材,如BT(Bismaleimide Triazine,双马来酰亚胺三嗪)或FR5等,再于其上进行导电通孔100工艺,如机械钻孔、激光钻孔或双锥状盲孔等成孔步骤,再于孔中电镀导电层或再填入填充材料。
然而,现有应用于高集成/大尺寸的覆晶封装基板1a会产生明显缺点,例如:该核心结构10采用玻纤配合环氧树脂所组成的基材,因该覆晶封装基板1a于各层间材料的热膨胀系数(Coefficient of thermal expansion,简称CTE)不一致,因而于封装时易产生板翘,致使其与该半导体芯片19之间连接不良(如图1A所示的上方焊锡材料13’未接合或断裂)、或于焊接时,其与该电路板18之间会发生连接不良(如图1A所示的下方焊锡材料13”未接合或断裂),更严重的是可能因为应力关系,会造成该半导体芯片19本身的破裂、或该半导体芯片19的电性失效。
因此,业界遂有将该核心结构10的厚度h加厚,如厚度h从原本0.8毫米(mm)搭配0.1mm的孔径w,增加厚度h至1.2mm(或1.6mm)而搭配0.2mm以上的孔径w,以增加该覆晶封装基板1a的刚性强度,以改善板翘问题,但却因而产生更多的缺点,如下:
第一、加厚该核心结构10的方式,不符合朝薄型化或微小化的封装设计的需求。
第二、单位面积内的电性连接点112的数量无法增加。具体地,加厚该核心结构10的结果,造成在传统技术之下势必让该多个导电通孔100的端面尺寸变大(即该孔径w变大),进而造成该多个导电通孔100的间距必须变大,故导致单位面积内电性连接点112的数量变少。
第三、线路间距变大及线路密度变低。具体地,加厚该核心结构10的结果,造成在传统技术之下势必让该多个导电通孔100的端面尺寸变大而占用布线面积,导致其上方线路层110的线路布线面积缩减,进而难以制作细线路间距或高密度线路的线路层110。
第四、该导电通孔100内更难完成电镀及顺利填入填充材料。具体地,加厚该核心结构10的结果,将导致该多个导电通孔100变深,因而更难以在变深的导电通孔100内完成电镀甚至会产生包孔现象,也难以将填充材料顺利地填入变深的导电通孔100内。
第五、该导电通孔100的加工成本与难度随着该核心结构10加厚而变高。具体地,兹因现有核心结构10是采用含玻纤布的介电材料来加厚该核心结构10以改善板翘的问题,但是于该材质上以激光或机械钻孔进行较深的导电通孔100加工时,不但难以制造出细小端面尺寸的导电通孔100,更因而致使制作成本居高不下。
第六、导电阻值变高,且电性变差。具体地,由于增加该核心结构10的厚度h,使该覆晶封装基板1a的整体厚度变厚,势必使导电路径(如该导电通孔100)变长而使电阻值变高,导致电性变差。
第七、散热性变差。具体地,增加核心结构10的厚度,促使整个覆晶封装基板1a变厚,势必增加该覆晶封装基板1a的散热难度,导致散热性变差而影响整体效能与寿命。
因此,如何克服现有技术中的种种问题,实已成为目前亟欲解决的课题。
发明内容
鉴于上述现有技术的缺失,本发明提供一种覆晶封装基板及其制作方法,能满足高集成芯片/大尺寸基板的封装需求。
本发明的覆晶封装基板,包括:核心结构,其具有相对的第一侧与第二侧,其中,该核心结构包含一中间层及分别结合于该中间层相对两侧的绝缘层,且形成该中间层的材质不同于形成该绝缘层的材质;多个导电结构,其贯通该中间层与该绝缘层,且各导电结构外露于该核心结构的第一侧与第二侧;以及线路结构,其以双边增层线路形式形成于该核心结构的第一侧及第二侧上且电性连接该导电结构。
本发明还提供一种覆晶封装基板的制作方法,包括:提供一中间层;于该中间层的相对两侧上分别结合一绝缘层,以令该中间层与绝缘层作为核心结构,且该核心结构具有相对的第一侧与第二侧,其中,形成该中间层的材质不同于形成该绝缘层的材质;形成多个导电结构于该核心结构中,使该导电结构贯通该中间层与该绝缘层,且各该导电结构外露于该核心结构的第一侧与第二侧;以及以双边增层线路形式形成线路结构于该核心结构的第一侧及第二侧上,且令该线路结构电性连接该导电结构。
前述的覆晶封装基板及其制作方法中,该核心结构的中间层由含玻纤的高刚性硬度的BT(Bismaleimide Triazine)或FR-5的绝缘材料所形成。
前述的覆晶封装基板及其制作方法中,该核心结构的绝缘层由环氧模压树脂或ABF(Ajinomoto Build-up Film,Ajinomoto积聚膜)的具有高刚性硬度的介电材料所形成。
前述的覆晶封装基板及其制作方法中,还包括形成强化结构于该核心结构的第一侧及/或第二侧上的线路结构上。例如,该强化结构包含刚性部、及将该刚性部结合于该线路结构上的绝缘部。
由上可知,本发明的覆晶封装基板及其制作方法,主要借由将该绝缘层设于该中间层的相对两侧上,以形成复合式核心结构,因而增加该覆晶封装基板的刚性强度,所以相较于现有技术,本发明的覆晶封装基板不仅能避免于半导体封装工艺中发生板翘,且该导电结构的端面尺寸又可依需求朝微小化设计,因而能增加单位面积内电性连接点的数量,以及制作出细线路间距及高布线密度的线路结构,进而能满足高集成芯片的封装需求。
附图说明
图1A为现有电子装置的剖视示意图。
图1B为现有覆晶封装基板的剖视示意图。
图2A至图2E为本发明的覆晶封装基板的制作方法的第一实施例的剖视示意图,其中,图2C’为图2C的另一实施方式的局部剖视图。
图2F为图2E的应用的剖视示意图。
图3A为本发明的覆晶封装基板的制作方法的第二实施例的剖视示意图。
图3B为图3A的应用的剖视示意图。
图4A为本发明的覆晶封装基板的制作方法的第三实施例的剖视示意图。
图4B为图4A的应用的剖视示意图。
图5A至图5H为本发明的覆晶封装基板的核心结构的不同实施方式的剖视示意图。
符号说明
1 电子装置 1a 覆晶封装基板
10 核心结构 100 导电通孔
11 增层结构 110,261,25a,25b 线路层
111,260 介电层 112 电性连接点
12 防焊层 13,13’,13” 焊锡材料
18 电路板 19 半导体芯片
2a,2b,3,4 覆晶封装基板 20 核心结构
20a 第一侧 20b 第二侧
200 通孔 21 中间层
22,23 绝缘层 24,24’,54a~54h 导电结构
24a,24b 端面 240,540 柱体
240a 导电材料 240b 填充材料
26a,26b 线路结构 262,263 电性接触垫
27 绝缘保护层 28,29 导电元件
3a,4a 强化结构 33 刚性部
330 开孔 35 绝缘部
350 结合层 351 保护层
9,9’,9” 电子封装件 90 电子元件
91 底胶 H,h,D,t 厚度
L 端面交界处 w 孔径。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式,本领域技术人员可由本说明书所公开的内容轻易地了解本发明的其他优点及技术效果。
须知,本说明书附图所示出的结构、比例、大小等,均仅用以配合说明书所公开的内容,以供本领域技术人员的了解与阅读,并非用以限定本发明可实施的限定条件,故不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本发明所能产生的技术效果及所能实现的目的下,均应仍落在本发明所公开的技术内容得能涵盖的范围内。同时,本说明书中所引用的如“上”、“第一”、“第二”及“一”等的用语,也仅为便于叙述的明了,而非用以限定本发明可实施的范围,其相对关系的改变或调整,在无实质变更技术内容下,当也视为本发明可实施的范围。
图2A至图2E为本发明的覆晶封装基板2a,2b的制作方法的第一实施例的剖视示意图。
如图2A所示,提供一核心结构20,其具有相对的第一侧20a与第二侧20b。
于本实施例中,该核心结构20的制作于一中间层21的相对两侧上分别压合一绝缘层22,23,以令该中间层21与该绝缘层22,23作为该核心结构20,且该绝缘层22,23的表面定义为该第一侧20a与第二侧20b的表面。
此外,形成该中间层21的材质为如介电材料的绝缘材料,该介电材料可为不包含玻纤的有机树脂材料或含有填充材料(如SiO2或玻纤粉等)的有机树脂,具体地,该有机介电材料的种类还包含铸模化合物(Molding Compound)、环氧模压树脂(Epoxy MoldingCompound,简称EMC)或底层涂料(Primer);该介电材料或者也可为绝缘无机材料(如绝缘氧化物、氮化物、铝化物或陶瓷类等)。优选地,形成该中间层21的材质为含玻纤的高刚性硬度的BT(Bismaleimide Triazine)或FR-5。
另外,该绝缘层22,23的材质可例如高刚性的陶瓷材料(如Al2O3或AlN)、塑钢、碳纤维,有机介电材料或其它适当材质,且该有机介电材料例如为有机粘着材料。具体地,该有机介电材料的种类还包含铸模化合物(Molding Compound)、环氧模压树脂(Epoxy MoldingCompound,简称EMC)、底层涂料(Primer)或高比例充填材料(SiO2-75%以上)。优选地,形成该绝缘层22,23的材质为EMC或ABF等具有高刚性硬度的介电材料。因此,有关该绝缘层22,23的材质可依需求设计,并不限于上述。
因此,该中间层21的绝缘材料可不同于该绝缘层22,23的材质,且于该绝缘层22,23的材质选择中,该铸模化合物或底层涂料具抗翘曲的技术效果。
另外,该中间层21的厚度H为0.2~0.6mm,且该绝缘层的厚度D为0.1~0.3mm。
如图2B所示,借由图案化工艺,于该核心结构20上形成多个连通该第一侧20a与第二侧20b的通孔200。
于本实施例中,该通孔200的工艺为采用如机械钻孔、激光钻孔或其它成孔方式。
如图2C所示,于该多个通孔200中以电镀、沉积或填充导电材料(如锡膏、导电胶等)等方式形成多个导电结构24,且于该核心结构20的第一侧20a及第二侧20b上同时或分次各电镀形成一线路层25a,25b,且该线路层25a,25b电性连接该多个导电结构24。
于本实施例中,该导电结构24由单一柱体构成,其周身未延伸有线路,且各导电结构24的相对两端面24a,24b外露于该核心结构20的第一侧20a与第二侧20b,以令其端面24a,24b连接该线路层25a,25b。具体地,该导电结构24的工艺于该通孔200中电镀填满导电材料以形成一体成形的柱体(如图2C所示);或者,可先将导电材料240a形成于该通孔200的孔壁上,再填入绝缘填充材料240b(如图5A所示的导电结构54a)。
此外,如图2C’所示,该导电结构24’也可由多个相互继续堆叠的柱体240所组成,也就是该通孔200由该中间层21的开孔与该绝缘层22,23的开孔所叠成,例如,各该柱体240的端面尺寸为相同。或者,各该柱体540的端面尺寸可不相同(如图5B至图5D所示的导电结构54b,54c,54d),致使各柱体540的端面交界处L呈凹凸状(如图5B及图5C所示)或呈阶梯状(如图5D所示),因而该导电结构的周身为非连续面。应可理解地,该柱体的继续堆叠层数或周身形式均可依需求设计,如该中间层21、绝缘层22,23内的各柱体240可包含由多个柱体继续堆叠而成的阶级柱,但并不限于上述。
另外,该导电结构的周身可依需求为连续面(如平斜面、如图2C及图2C’所示的导电结构24,24’的平直面、如图5E及图5F所示的导电结构54e,54f的双锥面、或如图5G及图5H所示的导电结构54g,54h的弧面)。因此,有关该导电结构的轮廓形状并无特别限制。
如图2D所示,于该线路层25a,25b上以双边增层线路形式形成线路结构26a,26b于该核心结构20的第一侧20a及第二侧20b上,即依需求设计布设线路的层数,且令该线路结构26a,26b电性连接该导电结构24。具体地,于该核心结构20的第一侧20a及第二侧20b上同时或分次各形成增层线路形式的线路结构26a,26b,其包括至少一介电层260及结合该介电层260的线路层261。具体地,该介电层260可为环氧树脂,如ABF(Ajinomoto Build-upFilm)、预浸材料或环氧模压树脂(EMC)。
如图2E所示,该线路结构26a,26b上可形成一绝缘保护层27,以令该绝缘保护层27外露出最外侧线路层261,以供作为电性接触垫262,263。
于本实施例中,该绝缘保护层27可为防焊材料,如感光型油墨、ABF或非感光型介电材料(如EMC)等。
此外,于后续工艺中,如图2F所示,可于该覆晶封装基板2a,2b的其中一侧的电性接触垫262上借由导电元件28接置至少一电子元件90,以形成一电子封装件9。另一方面,于该覆晶封装基板2b的另一侧的电性接触垫263上接置如焊球的导电元件29,以供外接一电路板(图略)。
所述的导电元件28可包含焊锡材料及/或金属凸块(如铜凸块)。
所述的电子元件90为主动元件、被动元件或其二者组合,其中,该主动元件例如为半导体芯片,而该被动元件例如为电阻、电容及电感。例如,该电子元件以覆晶方式电性连接线路部。具体地,该电子元件90借由该多个导电元件28设于该覆晶封装基板2a,2b上,再以底胶91包覆该多个导电元件28;或以封装层(图略)包覆该电子元件90,其中,该封装层可为压合工艺用的薄膜、模压工艺用的封装胶体或印刷工艺用的胶材等,且形成该封装层的材质为聚酰亚胺(PI)、干膜(dry film)、环氧树脂(epoxy)或封装材料,并无特别限制。
图3A至图3B为本发明的覆晶封装基板3的制作方法的第二实施例的剖视示意图。本实施例与第一实施例的主要差异在于增设强化结构,其它工艺大致相同,故以下不再赘述相同处。
如图3A所示,继续图2D所示的工艺,将一强化结构3a设于该核心结构20的第二侧20b的线路结构26b上,且于该核心结构20的第一侧20a的线路结构26a上形成该绝缘保护层27。
于本实施例中,该强化结构3a包含一刚性部33,且形成该刚性部33的材质为高刚性片材或板材。例如,该刚性部33的材质可为如铝、铝合金、不锈钢、铜、铜合金、镍铁合金或其它金属材料。或者,该刚性部33的材质可为如高刚性的陶瓷材料(如Al2O3或AlN)、塑胶、碳纤或其它的绝缘材料。因此,有关该刚性部33的材质可依需求设计,并不限于上述。
此外,该强化结构3a包含一绝缘部35,其包覆该刚性部33,以令该刚性部33借由该绝缘部35结合于该线路结构26b上。例如,该绝缘部35包含一用以结合该线路结构26b的结合层350与一用以包覆该刚性部33的保护层351,其中,该绝缘部35(或该保护层351)的材料可为有机介电材料(如防焊材料)或无机介电材料(如绝缘氧化物)。具体地,该有机介电材料的种类还包含ABF、预浸材料、铸模化合物、环氧模压树脂(EMC)或底层涂料。另一方面,该结合层350的材质与该保护层351的材质可相同或不相同。
另外,于该强化结构3a上形成多个开孔330,以令该多个电性接触垫263外露于该多个开孔330,以供设置该导电元件29。应可理解地,有关该强化结构3a的工艺的种类繁多,并无特别限制。例如,可先以该绝缘部35(或结合层350)将该刚性部33贴合于该第二侧20b的线路结构26b上,再于该绝缘部25上形成多个开孔330以外露出该电性接触垫263,之后形成该保护层351于该刚性部33上及该开孔330的孔壁中。
另外,于后续工艺中,如图3B所示的电子封装件9’的结构中,可于该覆晶封装基板3的另一侧的电性接触垫262上借由导电元件28接置至少一电子元件90,而于该强化结构3a的开孔330中的电性接触垫263上接置如焊球的导电元件29,以供外接一电路板(图略)。
因此,该电子封装件9’可借由该绝缘部35隔绝金属材料的刚性部33与该导电元件29两者之间的电性导通,以防止短路。
图4A至图4B为本发明的覆晶封装基板4的制作方法的第三实施例的剖视示意图。本实施例与第二实施例的主要差异在于强化结构的布设,其它工艺大致相同,故以下不再赘述相同处。
如图4A所示,继续图2D所示的工艺,将一强化结构3a设于该核心结构20的第二侧20b的线路结构26b上,且于该核心结构20的第一侧20a的线路结构26a上形成该绝缘保护层27,并于该绝缘保护层27上设置另一强化结构4a。
于本实施例中,该强化结构4a为框体,其由高刚性材质制作,以外露该多个电性接触垫262或该导电元件28。例如,该强化结构4a的材质可为如铝、铝合金、不锈钢、铜、铜合金、镍铁合金或其它金属材料。或者,该强化结构4a的材质可为如高刚性的陶瓷材料(如Al2O3或AlN)、塑胶、碳纤或其它的绝缘材料。因此,有关该强化结构4a的材质可依需求设计,并不限于上述。
另外,于后续工艺中,如图4B所示的电子封装件9”的结构中,可于该强化结构4a的框体内的电性接触垫262上借由导电元件28接置至少一电子元件90,而于该强化结构3a的开孔330中的电性接触垫263上接置如焊球的导电元件29,以供外接一电路板(图略)。
因此,该强化结构4a可平衡该核心结构20的第一侧20a与第二侧20b的应力分布,以防止该覆晶封装基板4翘曲。
本发明的制作方法借由将该绝缘层22,23分别设于该中间层21的相对两侧而形成该复合强化型核心结构20,以增加该覆晶封装基板2a,2b,3,4的刚性强度,故相较于现有技术,当本发明的覆晶封装基板2a,2b,3,4应用于半导体的高集成/大尺寸封装工艺时,其良好的刚性特质,因而能确保本发明的薄型化且于封装高温工艺时又不会发生板翘,进而能避免其与半导体芯片或电路板之间发生连接不良的问题。
因此,利用该复合强化型核心结构20的设计以提高该覆晶封装基板2a,2b,3,4的刚性,因而可避免半导体封装工艺的板翘问题,故相较于现有技术,本发明的制作方法更利于该覆晶封装基板2a,2b,3,4朝薄化设计。
此外,由于该覆晶封装基板2a,2b,3,4的刚性强度够强,因而无需增厚该核心结构20,故该导电结构24的端面24a,24b可依需求朝微小化设计,因而能增加其上方线路结构26a,26b的线路布线面积,进而能增加该电性接触垫262,263的数量。
本发明还提供一种覆晶封装基板2a,2b,3,4,包括:一核心结构20、多个导电结构24以及多个线路结构26a,26b。
所述的核心结构20具有相对的第一侧20a与第二侧20b,其中,该核心结构20包含一中间层21及分别接触结合于该中间层21相对两侧的绝缘层22,23,且形成该中间层21的材质不同于形成该绝缘层22,23的材质。
所述的导电结构24贯通该中间层21与该绝缘层22,23,且各该导电结构24外露于该核心结构20的第一侧20a与第二侧20b。
所述的线路结构26a,26b以双边增层线路形式形成于该核心结构20的第一侧20a及第二侧20b上且电性连接该导电结构24。
于一实施例中,该核心结构20的中间层21由绝缘材料所形成,如不包含玻纤布的有机树脂、含有填充材料(如SiO2或玻纤粉等)的有机树脂、或绝缘的无机材料(如绝缘氧化物、氮化物、铝化物或陶瓷类等)。
于一实施例中,该导电结构24,54a,5e~5h由单一柱体构成。
于一实施例中,该导电结构24’,54b~54d由多个柱体240,540继续堆叠而形成,且彼此继续堆叠的该多个柱体240,540的端面尺寸相同或不相同。
于一实施例中,所述的覆晶封装基板3,4还包括一设于该线路结构26a,26b上的强化结构3a,4a。例如,该强化结构3a包含刚性部33,其为导电材料或绝缘材料所形成,且该强化结构还包含包覆该刚性部33的绝缘部35,其用以结合于该线路结构26b上。或者,该强化结构4a为框体。
综上所述,本发明的覆晶封装基板及其制作方法,借由复合强化型核心结构的设计,以增加该覆晶封装基板的刚性强度,故当本发明的覆晶封装基板应用于高集成/大尺寸半导体封装工艺时,可避免封装件发生板翘的问题。
因此,兹将本发明上述特征所产生的技术效果说明如下:
第一、因本发明的覆晶封装基板2a,2b,3,4具有强化的高刚性核心结构20的支撑作用,促使该覆晶封装基板2a,2b,3,4于进行电子封装件9,9’,9”的高集成/大尺寸封装作业时,即使是各层间材料的热膨胀系数(Coefficient of thermal expansion,简称CTE)不一致,也不会因而发生弯翘(warpage)、或与电子元件90(现有半导体芯片19)间的连接不良(如导电元件28或焊锡材料未接合)、或与电路板间的连接不良(如导电元件29或焊锡材料未接合)、或因为热应力关系而造成该电子元件90(现有半导体芯片19)本身的破裂或电性失效。
第二、因本发明的覆晶封装基板2a,2b,3,4具有强化的高刚性核心结构20的支撑作用,促使该覆晶封装基板2a,2b,3,4及借其完成的电子封装件9,9’,9”可以进行高集成/大尺寸的封装作业及朝薄型化设计。
第三、因本发明的核心结构20能维持薄型化设计,故本发明的导电结构24的端面24a,24b可依需求朝微小化设计,因而达到该导电结构24细间距化的目的。
第四、因本发明的导电结构24能细间距化设计,故能降低该线路结构26a,26b的线路布线限制,进而易于制作高密度的线路配置。
第五、因本发明的核心结构20能维持薄型化设计,故不会增加该导电结构24的高度,因而能降低导电阻值,进而提升电性技术效果。
第六、因本发明的核心结构20能维持薄型化设计,故能大幅降低该核心结构20内的通孔200的加工难度与成本。
第七、因本发明的覆晶封装基板2a,2b,3,4具有强化的高刚性核心结构20的支撑作用,促使该覆晶封装基板2a,2b,3,4及借其完成的电子封装件9,9’,9”可以朝薄型化设计,所以可有效提升该电子封装件9,9’,9”的散热性,因而能确保应用端的效能稳定性。
另一方面,本发明的覆晶封装基板3,4进一步借由将该强化结构3a设于该核心结构20的第二侧20b的线路结构26b上,以增加该覆晶封装基板3,4的刚性强度,故相较于现有技术,当该覆晶封装基板3,4用于大封装尺寸时,即使薄化该覆晶封装基板3,4,该覆晶封装基板3,4仍具有高的刚性,因而于后续封装高温工艺时或于产品使用时,能避免该电子封装件9,9’,9”发生弯翘,进而能避免其与电子元件90或电路板之间发生连接不良的问题。
此外,由于该覆晶封装基板3,4用于大封装尺寸(如55*55、70*70、80*80mm2等)时,该线路结构26a,26b的层数可依需求设计,故该线路结构26a,26b可能产生各种程度的翘曲变化,因而可借由该强化结构3a的厚度t(如图3B所示)或利用该强化结构3a及构成材质,以控制该覆晶封装基板3,4的刚性,因而无需增加该核心结构20的厚度,甚至可降低该核心结构20的厚度,即能避免该覆晶封装基板3,4弯翘的问题。借此,该导电结构24的端面24a,24b可依需求朝微小化设计,因而能降低该线路层261的线路布线限制,进而易于制作细线路及细间距的线路层261,达到高密度封装的技术效果。
另外,因无需增加该核心结构20的厚度,甚至能降低该核心结构20的厚度,该导电结构24采用金属导电柱可降低导电阻值,以提升电性,进而可提供良好的散热。
另外,因该核心结构20得以变薄,故该导电结构24的加工难度降低,因而电子封装件9’,9”及其覆晶封装基板3,4的整体制作成本可大幅降低。
因此,兹将本发明因该强化结构3a特征而产生的技术效果说明如下:
第一、因本发明的覆晶封装基板3,4具有高刚性强化结构3a的支撑作用,促使该覆晶封装基板3,4及借其完成的电子封装件9’,9”可以进行大尺寸的封装作业及朝薄型化设计。
第二、因本发明的核心结构20能维持薄型化设计,故不会增加该导电结构24的直径与该核心结构20的厚度二者间的纵深比,因而易于填塞该通孔200或电镀该导电结构24,以有效均匀填入材质,故能大幅降低该导电结构24的加工难度与成本。
第三、因本发明的核心结构20能维持薄型化设计,故不会增加该导电结构24的高度,因而能降低导电阻值,进而提升电性技术效果。
第四、因本发明的强化结构3a的厚刚性部33及薄化核心结构20的特征,可有效提升该电子封装件9’,9”的散热性,因而能配合封装过程的高温而不会翘曲变形,也能确保应用端于运行发热时的效能稳定性。进一步,该强化结构3a为金属材料时,还可以提供良好的电性接地功能,降低使用中的噪声。
上述实施例仅用以例示性说明本发明的原理及其技术效果,而非用于限制本发明。任何本领域技术人员均可在不违背本发明的构思及范围下,对上述实施例进行修改。因此本发明的权利保护范围,应如权利要求书所列。
Claims (10)
1.一种覆晶封装基板,其特征在于,包括:
核心结构,其具有相对的第一侧与第二侧,并包含一中间层及分别结合于该中间层相对两侧的绝缘层,且形成该中间层的材质不同于形成该绝缘层的绝缘材质;
多个导电结构,其贯通该中间层与该绝缘层,且各导电结构外露于该核心结构的第一侧与第二侧;以及
线路结构,其以双边增层线路形式形成于该核心结构的第一侧及第二侧上且电性连接该导电结构。
2.根据权利要求1所述的覆晶封装基板,其特征在于,该核心结构的中间层由含玻纤的高刚性硬度的BT或FR-5的绝缘材料所形成。
3.根据权利要求1所述的覆晶封装基板,其特征在于,该核心结构的绝缘层由环氧模压树脂或ABF的具有高刚性硬度的介电材料所形成。
4.根据权利要求1所述的覆晶封装基板,其特征在于,该覆晶封装基板还包括强化结构,其设于该核心结构的第一侧及/或第二侧上的线路结构上。
5.根据权利要求4所述的覆晶封装基板,其特征在于,该强化结构包含刚性部、及将该刚性部结合于该线路结构上的绝缘部。
6.一种覆晶封装基板的制作方法,其特征在于,该制作方法包括:
提供一中间层;
于该中间层的相对两侧上分别结合一绝缘层,以令该中间层与绝缘层作为核心结构,且该核心结构具有相对的第一侧与第二侧,其中,形成该中间层的材质不同于形成该绝缘层的材质;
形成多个导电结构于该核心结构中,使该导电结构贯通该中间层与该绝缘层,且各导电结构外露于该核心结构的第一侧与第二侧;以及
以双边增层线路形式形成线路结构于该核心结构的第一侧及第二侧上,且令该线路结构电性连接该导电结构。
7.根据权利要求6所述的覆晶封装基板的制作方法,其中,该核心结构的中间层由含玻纤的高刚性硬度的BT或FR-5的绝缘材料所形成。
8.根据权利要求6所述的覆晶封装基板的制作方法,其中,该核心结构的绝缘层由环氧模压树脂或ABF的具有高刚性硬度的介电材料所形成。
9.根据权利要求6所述的覆晶封装基板的制作方法,还包括形成强化结构于该核心结构的第一侧及/或第二侧上的线路结构上。
10.根据权利要求9所述的覆晶封装基板的制作方法,其中,该强化结构包含刚性部、及将该刚性部结合于该线路结构上的绝缘部。
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JP2003007897A (ja) * | 2001-06-27 | 2003-01-10 | Toppan Printing Co Ltd | 半導体装置用基板 |
JP2004172304A (ja) * | 2002-11-19 | 2004-06-17 | Kyocera Corp | 配線基板およびその製造方法 |
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