TWI794034B - 基板結構 - Google Patents
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- 239000000758 substrate Substances 0.000 title claims abstract description 37
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Abstract
一種基板結構,係以絕緣體包覆呈單一實心柱體之導電柱,且於該絕緣體上配置至少一電性連接該導電柱之佈線層,以藉由該導電柱係為單一實心柱體之設計,滿足細線路、細間距及高密度接點等需求。
Description
本發明係有關一種半導體封裝製程,尤指一種可滿足細線路需求之基板結構。
隨著電子產業的蓬勃發展,許多高階電子產品都逐漸朝往輕、薄、短、小等高集積度方向發展,且隨著封裝技術之演進,半導體晶片的封裝技術也越來越多樣化,封裝基板之尺寸或體積亦隨之不斷縮小,藉以使該半導體封裝件達到輕薄短小之目的。
圖1係為習知封裝基板1之剖面示意圖。如圖1所示,該封裝基板1係包括一核心層10、設於該核心層10兩側上之線路結構11、及設於該線路結構11上之防焊層12,其中,該核心層10具有貫穿之導電柱體100以電性連接該線路結構11之線路層110,且該線路結構11復包含至少一包覆該些線路層110之介電層111,並令該防焊層12外露出該線路結構11最外側之線路層110,俾供作為接點(即I/O)112,以接置半導體晶片。
於習知核心層10之製作中,係採用玻纖配合環氧樹酯所組成之基材,如BT(Bismaleimide Triazine)或FR5等介電材,再於其上進行
如機械鑽孔或其它方式之成孔步驟以形成通孔,之後於該通孔中電鍍銅材100a,再填入絕緣膠材100b,以形成導電柱體100。另外,該介電層111係採用不含玻纖之材質。
惟,習知封裝基板1中,因採用鑽孔方式製作該導電柱體100,而在傳統機械鑽孔之技術下,必使通孔之孔徑w較大,導致該導電柱體100的端面尺寸較大,因而造成各該導電柱體100之間的距離較大,致使該封裝基板1之單位面積內之接點112的數量較少或難以增加。
再者,在傳統機械鑽孔之技術下,該導電柱體100的端面尺寸必定較大,因而佔用佈線面積,導致其兩側端面上之線路層110之線路佈線面積大幅縮減,致使該封裝基板1難以形成細線路間距或高密度線路之線路層110,故該封裝基板1之線路間距極大且線路密度極低。
又,傳統機械鑽孔所形成之通孔需具備一定比例之深寬比,致使該通孔具備一定深度h,故於後續製作該導電柱體100時,不易均勻電鍍銅材100a,且難以順利填滿該絕緣膠材100b,因而容易產生氣孔(void)現象。
另外,習知核心層10係採用含玻纖之介電材製作,使傳統機械鑽孔受限於此種材質而需形成一定孔徑w大小之通孔,因而難以製造出細小端面尺寸之導電柱體100,且該封裝基板1之製作成本難以下降。
因此,如何克服上述習知技術的問題,實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失,本發明係提供一種基板結構,係包括:導電柱,係為單一實心柱體,其具有相對之第一端面與第二端面;絕緣體,係包覆該導電柱,且該絕緣體具有相對之第一表面與第二表面,以令該導電柱之第一端面齊平該絕緣體之第一表面,而該導電柱之第二端面未連通至該第二表面;以及佈線層,係形成於該絕緣體之第一表面及/或第二表面上以電性連接該導電柱。
前述之基板結構中,該絕緣體係為不含玻纖之介電體。
前述之基板結構中,該佈線層係設於該絕緣體之第一表面上,且包含至少一設於該第一表面上之線路部、設於該線路部上之導電體、及包覆該線路部與該導電體之包覆部。例如,該包覆部係為含玻纖之介電體。或者,該導電體係為柱狀。亦或,該線路部係局部結合該導電柱之第一端面。
前述之基板結構中,該佈線層係設於該絕緣體之第二表面上,且包含至少一設於該第二表面上之導電體、設於該導電體上之線路部、及包覆該線路部與該導電體之包覆部。例如,該包覆部係為含玻纖之介電體。或者,該導電體係為柱狀。亦或,該線路部係局部嵌埋於該絕緣體之第二表面中,以結合該導電柱之第二端面。
由上可知,本發明之基板結構中,主要藉由該導電柱係為單一實心柱體之設計,以利於滿足細線路、細間距及高密度接點等需求,而克服習知技術之種種缺失。
1:封裝基板
10:核心層
100:導電柱體
100a:銅材
100b:絕緣膠材
11:線路結構
110:線路層
111:介電層
112,220,250:接點
12,28,29:防焊層
2:基板結構
2a:第一佈線層
2b:第二佈線層
20:絕緣體
20a:第一表面
20b:第二表面
21:導電柱
21a:第一端面
21b:第二端面
22:第一線路部
22a,25a:導電跡線
23:第一導電體
24:第一包覆部
25:第二線路部
26:第二導電體
27:第二包覆部
d:寬度
h:深度
L:高度
w:孔徑
圖1係為習知基板結構之剖視示意圖。
圖2係為本發明之基板結構之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如「上」、「第一」、「第二」及「一」等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
圖2係為本發明之基板結構2的剖視示意圖。如圖2所示,所述之基板結構2係包括一絕緣體20、至少一導電柱21、以及形成於該絕緣體20上以電性連接該導電柱21之第一佈線層2a與第二佈線層2b。
所述之絕緣體20係具有相對之第一表面20a與第二表面20b且包覆該導電柱21。
於本實施例中,該絕緣體20係採用不含玻纖之介電材製作,且該介電材可為環氧樹脂(Epoxy)。進一步,該環氧樹脂之種類更包含ABF(Ajinomoto Build-up Film)、鑄模化合物(Molding Compound)或底層塗料(Primer),如環氧模壓樹脂(Epoxy Molding Compound,簡稱EMC)。
所述之導電柱21係為單一實心柱體,其具有相對之第一端面21a與第二端面21b,且該第一端面21a係齊平該絕緣體20之第一表面20a,而該第二端面21b並未連通至該第二表面20b。
所述之第一佈線層2a係設於該絕緣體20之第一表面20a上,且包含至少一設於該第一表面20a上之第一線路部22、設於該第一線路部22上之第一導電體23、及包覆該第一線路部22與該第一導電體23之第一包覆部24。
於本實施例中,該第一包覆部24係採用含玻纖之介電材製作,如預浸材(prepreg,簡稱PP)。
再者,該第一導電體23係為柱狀,且部分該第一線路部22係結合該導電柱21之第一端面21a以電性連接該導電柱21。
又,該第一佈線層2a可於其最外側上形成一防焊層28,以令該防焊層28外露出該第一佈線層2a最外側之第一線路部22,俾供作為接點(即I/O)220,以接置電路板。
所述之第二佈線層2b係設於該絕緣體20之第二表面20b上,且包含至少一設於該第二表面20b上之第二導電體26、設於該第二導電體26上之第二線路部25、及包覆該第二線路部25與該第二導電體26之第二包覆部27。
於本實施例中,該第二包覆部27係採用含玻纖之介電材製作,如預浸材。
再者,該第二導電體26係為柱狀,且部分該第二線路部25係嵌埋於該絕緣體20之第二表面20b中且與第二表面20b齊平,以供於該第二線路部25上電鍍形成導電柱21,而該導電柱21之第二端面21b係結合該第二線路部25以電性連接該第二線路部25。具言之,可於一基底
上形成第二線路部25後,再採用電鍍實心柱方式製作該導電柱21,例如形成外露部分該第二線路部25之圖案化阻層,在該圖案化阻層(圖略)中電鍍形成導電柱21,之後移除圖案化阻層,再以絕緣體20包覆該第二線路部25及導電柱21,藉此,如圖2所示,該導電柱21之第二端面21b低於且並未連通至該絕緣體20之第二表面20b。
又,該第二佈線層2b亦可於其最外側上形成一防焊層29,以令該防焊層29外露出該第二佈線層2b最外側之第二線路部25,俾供作為接點(即I/O)250,以接置半導體晶片。
因此,本發明之基板結構2中,因採用電鍍實心柱方式製作該導電柱21,故可依需求調整該導電柱21的端面尺寸(該第一端面21a或該第二端面21b之寬度d),使各該導電柱21之間的距離能有效縮減,以利於增加該基板結構2之單位面積內之接點的數量。
再者,在電鍍實心柱之技術下,該導電柱21的端面尺寸可有效縮小,以減少佔用該第一表面20a或第二表面20b之佈線面積,因而能增加第一與第二端面21a,21b上之第一與第二線路部22,25之線路佈線面積(如該第一與第二線路部22,25之導電跡線22a,25a),故相較於習知技術,本發明之基板結構2能輕易形成細線路間距或高密度線路之線路部,使該第一與第二線路部22,25之線路間距能大幅縮小且線路密度大幅提高。
又,採用電鍍實心柱方式所形成之導電柱21不受高寬比之限制,因而能依需求形成所需之高度L,並能均勻電鍍銅材,且無需填充任何絕緣膠材於該導電柱21中,因而可避免發生氣孔(void)現象。
另外,由於該絕緣體20係以不含玻纖之介電材包覆該導電柱21,因而無需製作孔洞,使該導電柱21之製作不會受限於該絕緣體20之
材質,因而有利於製造出細小端面尺寸之導電柱21,且有利於降低該基板結構2之製作成本。
綜上所述,本發明之基板結構係藉由單一實心柱之設計方式製作該導電柱,以滿足細線路、細間距及高密度接點等需求。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
2:基板結構
2a:第一佈線層
2b:第二佈線層
20:絕緣體
20a:第一表面
20b:第二表面
21:導電柱
21a:第一端面
21b:第二端面
22:第一線路部
22a,25a:導電跡線
220,250:接點
23:第一導電體
24:第一包覆部
25:第二線路部
26:第二導電體
27:第二包覆部
28,29:防焊層
d:寬度
L:高度
Claims (9)
- 一種基板結構,係包括:導電柱,係為單一實心柱體,其具有相對之第一端面與第二端面;絕緣體,係包覆該導電柱,且該絕緣體具有相對之第一表面與第二表面,以令該導電柱之第一端面齊平該絕緣體之第一表面,而該導電柱之第二端面未連通至該第二表面,其中,該絕緣體係為不含玻纖之介電體;以及佈線層,係形成於該絕緣體之第一表面及/或第二表面上以電性連接該導電柱。
- 如請求項1所述之基板結構,其中,該佈線層係設於該絕緣體之第一表面上,且包含至少一設於該第一表面上之線路部、設於該線路部上之導電體、及包覆該線路部與該導電體之包覆部。
- 如請求項2所述之基板結構,其中,該包覆部係為含玻纖之介電體。
- 如請求項2所述之基板結構,其中,該導電體係為柱狀。
- 如請求項2所述之基板結構,其中,該線路部係局部結合該導電柱之第一端面。
- 如請求項1所述之基板結構,其中,該佈線層係設於該絕緣體之第二表面上,且包含至少一設於該第二表面上之導電體、設於該導電體上之線路部、及包覆該線路部與該導電體之包覆部。
- 如請求項6所述之基板結構,其中,該包覆部係為含玻纖之介電體。
- 如請求項6所述之基板結構,其中,該導電體係為柱狀。
- 如請求項6所述之基板結構,其中,該線路部係局部嵌埋於該絕緣體之第二表面中,以結合該導電柱之第二端面。
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TW201606964A (zh) * | 2014-08-12 | 2016-02-16 | 臻鼎科技股份有限公司 | 晶片封裝基板、晶片封裝結構及二者之製作方法 |
TW202114000A (zh) * | 2019-09-27 | 2021-04-01 | 恆勁科技股份有限公司 | 覆晶封裝基板及其製法 |
TW202139395A (zh) * | 2018-08-30 | 2021-10-16 | 恆勁科技股份有限公司 | 覆晶封裝基板之核心結構及其製法 |
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TW201606964A (zh) * | 2014-08-12 | 2016-02-16 | 臻鼎科技股份有限公司 | 晶片封裝基板、晶片封裝結構及二者之製作方法 |
TW202139395A (zh) * | 2018-08-30 | 2021-10-16 | 恆勁科技股份有限公司 | 覆晶封裝基板之核心結構及其製法 |
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