WO2025065286A1 - 一种像素驱动电路、显示面板及驱动方法 - Google Patents

一种像素驱动电路、显示面板及驱动方法 Download PDF

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Publication number
WO2025065286A1
WO2025065286A1 PCT/CN2023/121752 CN2023121752W WO2025065286A1 WO 2025065286 A1 WO2025065286 A1 WO 2025065286A1 CN 2023121752 W CN2023121752 W CN 2023121752W WO 2025065286 A1 WO2025065286 A1 WO 2025065286A1
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WIPO (PCT)
Prior art keywords
transistor
signal
terminal
coupled
compensation capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/CN2023/121752
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English (en)
French (fr)
Inventor
方飞
王铸
石领
周伟峰
杨明坤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to PCT/CN2023/121752 priority Critical patent/WO2025065286A1/zh
Priority to CN202380010895.4A priority patent/CN120112973A/zh
Priority to US18/837,814 priority patent/US20260196158A1/en
Publication of WO2025065286A1 publication Critical patent/WO2025065286A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0435—Change or adaptation of the frame rate of the video stream

Definitions

  • the present disclosure relates to the field of display technology and provides a pixel driving circuit, a display panel and a driving method.
  • the threshold voltage compensation of the driving transistor is synchronously completed when the data voltage is written into the gate of the driving transistor.
  • the compensation period per unit time is greatly reduced, which will lead to insufficient compensation of the threshold voltage of the driving transistor, and thus poor display effect of the display.
  • the embodiments of the present disclosure provide a pixel driving circuit, a display panel and a driving method, which are used to perform threshold voltage compensation and data voltage writing in different time periods, so as to improve the threshold voltage compensation effect under high refresh rate.
  • an embodiment of the present disclosure provides a pixel driving circuit, including: a driving transistor, a light-emitting device, a compensation capacitor, a threshold compensation subcircuit, a data writing subcircuit, a conduction control subcircuit and a light-emitting control subcircuit;
  • the threshold compensation sub-circuit is coupled to the gate of the driving transistor and the first end of the compensation capacitor, and is configured to provide the threshold voltage of the driving transistor to the first end of the compensation capacitor in response to a signal at the compensation signal end;
  • the data writing sub-circuit is coupled to the second end of the compensation capacitor and is configured to provide a data voltage of the data signal end to the second end of the compensation capacitor in response to a signal of the scan signal end;
  • a compensation capacitor configured to stabilize the voltage at the first terminal and the second terminal
  • the conduction control subcircuit is coupled to the second end of the compensation capacitor and the power signal end, and is configured to conduct the power signal end and the second end of the compensation capacitor in response to a signal at the conduction control end;
  • the light emitting control subcircuit is coupled to the driving transistor and the light emitting device, and is configured to provide the driving current generated by the driving transistor to the light emitting device in response to a signal at the light emitting control signal terminal.
  • the conduction control subcircuit includes: a first transistor
  • the control end of the first transistor is coupled to the conduction control end, the first end of the first transistor is coupled to the second end of the compensation capacitor, and the second end of the first transistor is coupled to the power signal end.
  • the data writing sub-circuit provides a data voltage at the data signal terminal to the second terminal of the compensation capacitor in response to a first effective level of a signal at the scan signal terminal;
  • the threshold compensation subcircuit provides the threshold voltage of the driving transistor to the first terminal of the compensation capacitor in response to the second effective level of the signal at the compensation signal terminal;
  • the first effective level is within a time period of the second effective level.
  • a high level duration of the first effective level is shorter than a low level duration of the second effective level.
  • the threshold compensation subcircuit includes: a second transistor
  • the control terminal of the second transistor is coupled to the compensation signal terminal, the first terminal of the second transistor is coupled to the first terminal of the compensation capacitor, and the second terminal of the second transistor is coupled to the second terminal of the driving transistor.
  • the data writing sub-circuit includes: a third transistor
  • the control end of the third transistor is coupled to the scan signal end, the first end of the third transistor is coupled to the data signal end, and the second end of the third transistor is coupled to the second end of the compensation capacitor.
  • the light emitting control subcircuit includes: a fourth transistor and a fifth transistor;
  • the control end of the fourth transistor is coupled to the light emitting control signal end, the first end of the fourth transistor is coupled to the power signal end, and the second end of the fourth transistor is coupled to the first end of the driving transistor;
  • the control terminal of the fifth transistor is coupled to the conduction control terminal, the first terminal of the fifth transistor is coupled to the second terminal of the driving transistor, and the second terminal of the fifth transistor is coupled to the anode of the light emitting device.
  • a first initialization subcircuit is further included, which is coupled to the first end of the driving transistor and is configured to provide a signal from the first initialization signal end to the first end of the driving transistor in response to a signal from the first reset signal end.
  • the first initialization sub-circuit includes: a sixth transistor
  • the control terminal of the sixth transistor is coupled to the first reset signal terminal, the first terminal of the sixth transistor is coupled to the first terminal of the driving transistor, and the second terminal of the sixth transistor is coupled to the first initialization signal terminal.
  • a second initialization subcircuit is further included, which is coupled to the anode of the light-emitting device and is configured to provide a signal from the second initialization signal terminal to the anode of the light-emitting device in response to a signal from the second reset signal terminal.
  • the second initialization sub-circuit includes: a seventh transistor
  • the control terminal of the seventh transistor is coupled to the second reset signal terminal, the first terminal of the seventh transistor is coupled to the anode of the light emitting device, and the second terminal of the seventh transistor is coupled to the second initialization signal terminal.
  • a third initialization subcircuit is further included, which is coupled to the first end of the compensation capacitor and is configured to provide a signal from the third initialization signal end to the first end of the compensation capacitor in response to a signal from the third reset signal end.
  • the third initialization sub-circuit includes: an eighth transistor;
  • the control terminal of the eighth transistor is coupled to the third reset signal terminal, the first terminal of the eighth transistor is coupled to the first terminal of the compensation capacitor, and the second terminal of the eighth transistor is coupled to the third initialization signal terminal.
  • an embodiment of the present disclosure further provides a display panel, including:
  • a substrate comprising a plurality of sub-pixels, wherein the sub-pixels include any one of the above pixel driving circuits;
  • the pixel driving circuit comprises: a driving transistor, a first transistor, a third transistor and a compensation capacitor, wherein a first end of the first transistor is coupled to a second end of the compensation capacitor, a second end of the third transistor is coupled to a second end of the compensation capacitor, and a gate of the driving transistor is coupled to the first end of the compensation capacitor;
  • the orthographic projection of the active layer of the third transistor on the substrate is located between the orthographic projection of the active layer of the driving transistor on the substrate and the orthographic projection of the active layer of the first transistor on the substrate.
  • the display panel includes: a first semiconductor layer, a first conductive layer, a second conductive layer, and a second semiconductor layer;
  • a first semiconductor layer is located on the substrate, and the first semiconductor layer includes an active layer of the first transistor and an active layer of the driving transistor;
  • the first conductive layer is located on a side of the substrate away from the first semiconductor layer, and the first conductive layer includes including a gate of the first transistor, a gate of the driving transistor, and a first signal line;
  • a second conductive layer is located on a side of the substrate away from the first conductive layer, and the second conductive layer includes a second end of the compensation capacitor, a gate of the third transistor and a fifth signal line;
  • the second semiconductor layer is located on a side of the substrate away from the second conductive layer, and the second semiconductor layer includes an active layer of a third transistor.
  • an orthographic projection of the first signal line on the substrate and an orthographic projection of the active layer of the first transistor on the substrate have an overlapping area, and the first signal line in the overlapping area is a gate of the first transistor.
  • the active layer of the first transistor includes a first active portion and a second active portion, the first active portion extends along a first direction, the second active portion extends along a second direction, and an orthographic projection of the first signal line on the substrate overlaps with an orthographic projection of the first active portion on the substrate.
  • a third conductive layer is further included, the third conductive layer is located on a side of the substrate away from the second semiconductor layer, the third conductive layer includes a power signal line connected to the power signal terminal, and the power signal line covers the overlapping area.
  • the third conductive layer includes a first connecting portion
  • the second conductive layer includes a second connecting portion
  • a first insulating layer is provided between the third conductive layer and the second conductive layer
  • a second insulating layer is provided between the second conductive layer and the first conductive layer
  • the power signal line is connected to the second connection portion through a first via hole penetrating the first insulating layer;
  • the second connection portion is connected to the active layer of the first transistor through a second via hole penetrating the second insulating layer.
  • an embodiment of the present disclosure further provides a driving method of any of the above pixel driving circuits, including:
  • the threshold compensation subcircuit provides the threshold voltage of the driving transistor to the first terminal of the compensation capacitor in response to the signal at the compensation signal terminal;
  • the data writing sub-circuit provides the data voltage of the data signal terminal to the second terminal of the compensation capacitor in response to the signal of the scanning signal terminal;
  • the compensation capacitor stabilizes the voltage between the first terminal and the second terminal
  • the conduction control subcircuit responds to the signal of the conduction control terminal and connects the power signal terminal to the compensation capacitor.
  • the second terminal is conducting;
  • the light emitting control subcircuit provides the driving current generated by the driving transistor to the light emitting device in response to the signal at the light emitting control signal terminal.
  • the pixel driving circuit includes: a driving transistor, a light-emitting device, a compensation capacitor, a threshold compensation sub-circuit, a data writing sub-circuit, a conduction control sub-circuit and a light-emitting control sub-circuit.
  • the threshold compensation sub-circuit responds to a signal at the compensation signal end to provide the threshold voltage of the driving transistor to the first end of the compensation capacitor.
  • the data writing sub-circuit responds to a signal at the scanning signal end to provide a data voltage at the data signal end to the second end of the compensation capacitor.
  • the conduction control sub-circuit responds to a signal at the conduction control end to conduct the power signal end with the second end of the compensation capacitor.
  • the light-emitting control sub-circuit responds to a signal at the light-emitting control signal end to provide the driving current generated by the driving transistor to the light-emitting device.
  • the setting of the compensation capacitor realizes the time-sharing of threshold compensation and data writing, which satisfies the display of the light-emitting device and achieves high-frequency refresh at the same time.
  • FIG1 is a connection diagram of a pixel driving circuit in the related art
  • FIG2 is a connection diagram of a pixel driving circuit in an embodiment of the present disclosure
  • FIG3 is a circuit connection diagram of a pixel driving circuit in an embodiment of the present disclosure.
  • FIG4 is a connection diagram of another pixel driving circuit in an embodiment of the present disclosure.
  • FIG5 is a circuit connection diagram of another pixel driving circuit in an embodiment of the present disclosure.
  • FIG6 is a timing diagram of a pixel driving circuit in an embodiment of the present disclosure.
  • FIG7 is a schematic diagram of a layout structure of a display panel in an embodiment of the present disclosure.
  • FIG8 is a schematic diagram of the layout structure of a first semiconductor layer in a display panel in an embodiment of the present disclosure
  • FIG9 is a schematic diagram of the layout structure of a first conductive layer in a display panel in an embodiment of the present disclosure
  • FIG10 is a schematic diagram of the layout structure of a second conductive layer in a display panel in an embodiment of the present disclosure
  • FIG11 is a schematic diagram of the layout structure of a second semiconductor layer in a display panel in an embodiment of the present disclosure
  • FIG12 is a schematic diagram of the layout structure of a third conductive layer in a display panel in an embodiment of the present disclosure.
  • FIG13 is a schematic diagram of the layout structure of a film layer where a power signal terminal is located in a display panel in an embodiment of the present disclosure
  • FIG14 is a schematic diagram of the layout structure of a film layer where each connection line in a display panel according to an embodiment of the present disclosure is located;
  • FIG15 is a schematic diagram of the layout structure of a film layer where each connection line is located in another display panel in an embodiment of the present disclosure
  • FIG. 16 is a flow chart of a driving method of a pixel driving circuit in an embodiment of the present disclosure.
  • the threshold voltage of the driving transistor is compensated synchronously when the data voltage is written into the gate of the driving transistor.
  • the compensation period per unit time is greatly reduced, which will lead to insufficient compensation of the threshold voltage of the driving transistor, and thus poor display effect of the display.
  • the transistor M3 in FIG. 1 is a driving transistor.
  • the threshold voltage of the driving transistor M3 is written into the gate of the driving transistor via the turned-on transistor M2.
  • the data voltage is also written into the gate of the driving transistor via the turned-on transistor T4.
  • a pixel driving circuit proposed in an embodiment of the present application includes: a driving transistor DTFT, a light-emitting device L1, a compensation capacitor C1, a threshold compensation subcircuit 200, a data writing subcircuit 300, a conduction control subcircuit 100 and a light-emitting control subcircuit 400.
  • the conduction control subcircuit 100 is coupled to the second terminal of the compensation capacitor C1 and the power signal terminal ELVDD, and is configured to conduct the power signal terminal ELVDD with the second terminal of the compensation capacitor C1 in response to the signal of the conduction control terminal S4.
  • the conduction control subcircuit 100 includes: a first transistor T1 .
  • connection relationship between the first transistor T1 and other components in Figure 3 is: the control end of the first transistor T1 is coupled to the conduction control end S4, the first end of the first transistor T1 is coupled to the second end of the compensation capacitor C1, and the second end of the first transistor T1 is coupled to the power signal end ELVDD.
  • the control terminal S4 of the first transistor T1 when the signal at the conduction control terminal S4 is at a low level, the control terminal S4 of the first transistor T1 is The control terminal is turned on, and the level of the power signal terminal ELVDD is provided to the second terminal of the compensation capacitor C1 through the turned-on first transistor T1.
  • the threshold compensation subcircuit 200 is coupled to the gate of the driving transistor DTFT and the first end of the compensation capacitor C1, and is configured to provide the threshold voltage of the driving transistor DTFT to the first end of the compensation capacitor C1 in response to the signal of the compensation signal terminal S1.
  • the threshold compensation sub-circuit 200 includes: a second transistor T2 .
  • connection relationship between the second transistor T2 and other components in Figure 3 is: the control end of the second transistor T2 is coupled to the compensation signal end S1, the first end of the second transistor T2 is coupled to the first end of the compensation capacitor C1, and the second end of the second transistor T2 is coupled to the second end of the driving transistor DTFT.
  • the second transistor T2 since the second transistor T2 is directly connected to the first end of the compensation capacitor C1, i.e., the gate of the driving transistor DTFT, during the implementation process, the second transistor T2 can be replaced with an IGZO tube, which can ensure that the potential of the gate of the driving transistor DTFT will not change due to leakage of the second transistor T2.
  • the control terminal of the second transistor T2 is at a low level, the second transistor T2 is turned on, and the threshold voltage of the driving transistor DTFT is provided to the first terminal of the compensation capacitor C1 via the turned-on second transistor T2.
  • the data writing sub-circuit 300 is coupled to the second end of the compensation capacitor C1 and is configured to provide a data voltage of the data signal terminal Data to the second end of the compensation capacitor C1 in response to a signal of the scan signal terminal S3 .
  • the data writing sub-circuit 300 includes: a third transistor T3 .
  • connection relationship between the third transistor T3 and other components in Figure 3 is: the control end of the third transistor T3 is coupled to the scan signal end S3, the first end of the third transistor T3 is coupled to the data signal end Data, and the second end of the third transistor T3 is coupled to the second end of the compensation capacitor C1.
  • the third transistor T3 is an N-type transistor, and the material of the active layer of the third transistor is a metal oxide semiconductor material, such as IGZO.
  • the third transistor T3 is an N-type transistor
  • the other transistors are P-type transistors, and the material of the active layer of the other transistors can also be low temperature polysilicon (LTPS), etc., which is not mentioned here. Make specific restrictions.
  • the control terminal of the third transistor T3 is at a high level, the third transistor T3 is turned on, and the data voltage of the data signal terminal Data is provided to the second terminal of the compensation capacitor C1 through the turned-on third transistor T3.
  • the effective time period for writing the data into the effective level of the sub-circuit 300 and the threshold compensation sub-circuit 200 is set as follows:
  • the data writing sub-circuit 300 provides the data voltage of the data signal terminal Data to the second terminal of the compensation capacitor C1 in response to the first effective level of the signal at the scan signal terminal S3.
  • the duration for which the data voltage is written into the second end of the compensation capacitor C1 is the duration corresponding to the first effective level.
  • the threshold compensation sub-circuit 200 provides the threshold voltage of the driving transistor DTFT to the first terminal of the compensation capacitor C1 in response to the second effective level of the signal at the compensation signal terminal S1.
  • the duration for which the threshold voltage is written into the first end of the compensation capacitor C1 is the duration corresponding to the second effective level.
  • the first effective level may be a high level, and correspondingly, the second effective level may be a low level. In other embodiments, the first effective level may be a low level, and correspondingly, the second effective level may be a high level.
  • the first effective level is within the time period of the second effective level.
  • the time period corresponding to the first effective level is set shorter than the time period corresponding to the second effective level, thereby ensuring that the time period of the threshold voltage writing circuit is longer than the time period of the data voltage writing circuit.
  • a high level duration of the first effective level is shorter than a low level duration of the second effective level.
  • the first effective level is high level effective and the second effective level is low level effective.
  • the high level time of the first effective level is shorter than The low level duration of the second effective level.
  • the compensation capacitor C1 is configured to stabilize the voltage at the first end and the second end.
  • the first transistor T1 is turned on under the control of the turn-on control terminal S4, and the voltage at the first end of the compensation capacitor C1 jumps from the data voltage to the voltage of the power signal terminal ELVDD.
  • the bootstrap effect of the compensation capacitor C1 couples the jump amount of the voltage at the first end to the second end of the compensation capacitor C1.
  • the driving transistor DTFT generates a driving current according to the threshold voltage and the data voltage.
  • the light emitting control subcircuit is coupled to the driving transistor DTFT and the light emitting device L1 , and is configured to provide the driving current generated by the driving transistor DTFT to the light emitting device L1 in response to the signal of the light emitting control signal terminal S4 .
  • the light emitting control subcircuit includes a fourth transistor T4 and a fifth transistor T5 .
  • connection relationship between the fourth transistor T4 and other components in Figure 3 is: the control end of the fourth transistor T4 is coupled to the light control signal end S4, the first end of the fourth transistor T4 is coupled to the power signal end ELVDD, and the second end of the fourth transistor T4 is coupled to the first end of the driving transistor DTFT.
  • the fourth transistor T4 when the light emitting control signal terminal S4 is at a low level, the fourth transistor T4 is turned on, and the signal in the power signal terminal ELVDD is provided to the driving transistor DTFT via the turned-on fourth transistor T4.
  • connection relationship between the fifth transistor T5 and other components in Figure 3 is: the control end of the fifth transistor T5 is coupled to the conduction control end S4, the first end of the fifth transistor T5 is coupled to the second end of the driving transistor DTFT, and the second end of the fifth transistor T5 is coupled to the anode of the light-emitting device L1.
  • the fifth transistor T5 when the signal at the conduction control terminal S4 is at a low level, the fifth transistor T5 is turned on, and the driving current generated by the driving transistor DTFT is provided to the anode of the light emitting device L1 via the turned-on fifth transistor T5, so that the light emitting device L1 emits light.
  • the pixel driving circuit further includes a first initialization sub-circuit 500, which is coupled to the first end of the driving transistor DTFT and is configured to respond to a signal from the first reset signal terminal S5 and provide a signal from the first initialization signal terminal Vinit1 to the first end of the driving transistor DTFT.
  • a first initialization sub-circuit 500 which is coupled to the first end of the driving transistor DTFT and is configured to respond to a signal from the first reset signal terminal S5 and provide a signal from the first initialization signal terminal Vinit1 to the first end of the driving transistor DTFT.
  • the first initialization sub-circuit 500 includes: a sixth transistor T6 .
  • connection relationship between the sixth transistor T6 and other components in Figure 5 is: the control end of the sixth transistor T6 is coupled to the first reset signal end S5, the first end of the sixth transistor T6 is coupled to the first end of the driving transistor DTFT, and the second end of the sixth transistor T6 is coupled to the first initialization signal end Vinit1.
  • the sixth transistor T6 when the signal at the first reset signal terminal S5 is at a low level, the sixth transistor T6 is turned on, and the first initialization signal at the first initialization signal terminal Vinit1 is provided to the first terminal of the driving transistor DTFT via the turned-on sixth transistor T6 to reset the first terminal of the driving transistor DTFT.
  • the above-mentioned pixel driving circuit also includes a second initialization subcircuit 600, which is coupled to the anode of the light-emitting device L1 and is configured to provide the signal of the second initialization signal terminal Vinit2 to the anode of the light-emitting device L1 in response to the signal of the second reset signal terminal S5.
  • a second initialization subcircuit 600 which is coupled to the anode of the light-emitting device L1 and is configured to provide the signal of the second initialization signal terminal Vinit2 to the anode of the light-emitting device L1 in response to the signal of the second reset signal terminal S5.
  • the second initialization sub-circuit 600 includes a seventh transistor T7 .
  • connection relationship between the seventh transistor T7 and other components in Figure 5 is: the control end of the seventh transistor T7 is coupled to the second reset signal end S5, the first end of the seventh transistor T7 is coupled to the anode of the light-emitting device L1, and the second end of the seventh transistor T7 is coupled to the second initialization signal end Vinit2.
  • the seventh transistor T7 is turned on, and the second initialization signal at the second initialization signal terminal Vinit2 is provided to the anode of the light emitting device L1 via the turned-on seventh transistor T7 to reset the anode of the light emitting device L1.
  • the above-mentioned pixel driving circuit also includes a third initialization sub-circuit 700, which is coupled to the first end of the compensation capacitor C1 and is configured to respond to the signal of the third reset signal terminal S6 and provide the signal of the third initialization signal terminal Vinit3 to the first end of the compensation capacitor C1.
  • a third initialization sub-circuit 700 which is coupled to the first end of the compensation capacitor C1 and is configured to respond to the signal of the third reset signal terminal S6 and provide the signal of the third initialization signal terminal Vinit3 to the first end of the compensation capacitor C1.
  • the third initialization sub-circuit 700 includes: an eighth transistor T8 .
  • the connection relationship between the eighth transistor T8 and other components in FIG. 5 is as follows: the eighth transistor T8 The control end of the eighth transistor T8 is coupled to the third reset signal end S6, the first end of the eighth transistor T8 is coupled to the first end of the compensation capacitor C1, and the second end of the eighth transistor T8 is coupled to the third initialization signal end Vinit3.
  • the eighth transistor T8 when the signal at the third reset signal terminal S6 is at a low level, the eighth transistor T8 is turned on, and the third initialization signal at the third initialization signal terminal Vinit3 is provided to the first end of the compensation capacitor C1 via the turned-on eighth transistor T8 to reset the first end of the compensation capacitor C1.
  • the cathode of the above-mentioned light-emitting device is coupled to the cathode power supply terminal ELVSS, and the voltage of the above-mentioned cathode power supply terminal ELVSS is lower than the voltage of the above-mentioned power signal terminal ELVDD.
  • the first transistor T1 When S1 is a low level signal, the first transistor T1 is turned on, and the signal of the power signal terminal ELVDD is provided to the fifth node N5, and the fifth node N5 is coupled to the second end of the compensation capacitor C1. At the same time, when S1 is a low level signal, the fifth transistor T5 is turned on. When S5 is a low level signal, the sixth transistor T6 is turned on, and the signal of the first initialization signal terminal Vinit1 is provided to the second node N2, and the second node N2 is coupled to the first end of the sixth transistor.
  • the seventh transistor T7 is turned on, and the signal of the second initialization signal terminal Vinit2 is provided to the N4 node, and the signal of the second initialization signal terminal Vinit2 is provided to the third node N3 via the fourth node N4 and the turned-on fifth transistor T5, and the fourth node N4 is coupled to the anode of the light emitting device, and the third node N3 is coupled to the second end of the driving transistor.
  • the second transistor T2 is turned on, and the signal of the second initialization signal terminal Vinit2 is provided to the first node N1 via the third node N3 and the turned-on second transistor T2, and the first node N1 is coupled to the gate of the driving transistor.
  • S2 is a low level signal
  • the second transistor T2 is turned on, and the signal of the first initialization signal terminal Vinit1 is provided to the second node N2.
  • the second transistor T2 When S2 is a low level signal, the second transistor T2 is turned on, and the driving transistor DTFT is in the first The node N1 is turned on by the signal of the second initialization signal terminal Vinit2.
  • S4 When S4 is a low level signal, the fourth transistor T4 is turned on, and the signal of the power signal terminal ELVDD is provided to the driving transistor DTFT through the turned-on fourth transistor T4, so that the voltage of the gate of the driving transistor DTFT changes to Vth+VELVDD, wherein Vth is the threshold voltage of the driving transistor DTFT, and VELVDD is the voltage of the power signal terminal ELVDD, that is, the first end of the compensation capacitor C1.
  • the third transistor T3 Since the first effective level of the data writing sub-circuit 300 is in the time period of the second effective level of the threshold compensation sub-circuit 200, that is, the starting time of the low level of S3 is later than the starting time of the low level of S2 and S4, that is, when the above compensation is about to end, S3 is a low level signal, the third transistor T3 is turned on, and the data voltage of the data signal terminal Data is provided to the N5 node, that is, the second end of the compensation capacitor C1, through the turned-on third transistor T3.
  • the first transistor T1 When S1 is a low level signal, the first transistor T1 is turned on, and the signal of the power signal terminal ELVDD is written into the second end of the compensation capacitor C1 through the turned-on first transistor T1 and the N5 node.
  • the voltage at the second end of the compensation capacitor C1 jumps from the data voltage of the data signal terminal Data to VELVDD, and the voltage change is ELVDD-Data.
  • the voltage change is coupled to the first end of the compensation capacitor C1.
  • the voltage change at the first end of the compensation capacitor C1 is Vth+VELVDD+VELVDD-Data, that is, Vth-Data, so that the data voltage of the data signal terminal Data is written into the first node N1, that is, the gate of the driving transistor DTFT.
  • the fifth transistor T5 When S1 is a low level signal, the fifth transistor T5 is turned on. When S4 is a low level signal, the fourth transistor T4 is turned on.
  • the driving current is input into the light emitting device L1, thereby driving the light emitting device L1 to emit light.
  • an embodiment of the present disclosure provides a display panel, including a substrate, the substrate including a plurality of sub-pixels, the sub-pixels including any of the above-mentioned pixel driving circuits; the pixel driving circuit including: a driving transistor, a first transistor, a third transistor and a compensation capacitor, the first end of the first transistor being coupled to the second end of the compensation capacitor, the third transistor The second end of the transistor is coupled to the second end of the compensation capacitor, the gate of the driving transistor is coupled to the first end of the compensation capacitor, and the positive projection of the active layer of the third transistor on the substrate substrate is located between the positive projection of the active layer of the driving transistor on the substrate substrate and the positive projection of the active layer of the first transistor on the substrate substrate. That is, the active layer of the first transistor newly added in the present application and the active layer of the third transistor coupled to the second end of the compensation capacitor are in the same layer.
  • FIG7 is a schematic diagram of the layout structure of the pixel driving circuit provided in some embodiments of the present disclosure.
  • FIG8 to FIG15 are schematic diagrams of each layer of the pixel driving circuit provided in some embodiments of the present disclosure.
  • the examples shown in FIG7 to FIG15 take the pixel driving circuit of a sub-pixel as an example.
  • FIG7 to FIG15 also show a first signal line S1, a fifth signal line S5 and a power signal line electrically connected to the pixel driving circuit.
  • the power signal line is configured to input a voltage VELVDD to the power signal terminal ELVDD.
  • a plurality of signal lines can be arranged along a first direction F1.
  • the first semiconductor layer of the pixel driving circuit is shown.
  • the first semiconductor layer can be formed by patterning amorphous silicon or low temperature polycrystalline silicon (LTPS) material.
  • the first semiconductor layer can be used to make the active layer of the first transistor T1, the active layer of the second transistor T2, the active layer of the third transistor T3, the active layer of the fifth transistor T5, the active layer of the sixth transistor T6, the active layer of the seventh transistor T7 and the active layer of the driving transistor DTFT.
  • each active layer may include a first region, a second region and a first channel region located between the first region and the second region.
  • first region and the second region may be regions doped with n-type impurities or p-type impurities in the first semiconductor layer to form a conductor region, so that the first region and the second region can be used as the source region and the drain region of the active layer for electrical connection.
  • the active layer of the fifth transistor T5 can be extended roughly in a straight line along the second direction F2.
  • the extension direction of the active layer of the fifth transistor T5 is roughly parallel to the second direction F2.
  • the extension direction of the active layer of the fifth transistor T5 is not completely parallel to the second direction, and there may be some deviations. Therefore, as long as the extension direction of the active layer of the fifth transistor T5 and the second direction roughly meet the parallel condition, they all belong to the protection scope of the present invention.
  • the above-mentioned sameness can be parallelism allowed within the allowable error range.
  • an insulating layer is formed on the above-mentioned first semiconductor layer to protect the above-mentioned first semiconductor layer.
  • the first conductive layer of the pixel driving circuit is shown.
  • the first conductive layer is arranged on the side of the substrate away from the first semiconductor layer, so as to be insulated from the first semiconductor layer.
  • the first conductive layer may include: a gate of the first transistor T1, a gate of the second transistor T2, a gate of the third transistor T3, a gate of the fifth transistor T5, a gate of the sixth transistor T6, a gate of the seventh transistor T7, a gate of the driving transistor DTFT, a first signal line S1, a second signal line S2, a third signal line S3 and a fifth signal line S5.
  • the gate of the first transistor T1 may be the portion where the first signal line S1 overlaps with the first semiconductor layer.
  • the gate of the driving transistor DTFT may be the portion where the first end of the compensation capacitor C1 overlaps with the first semiconductor layer.
  • the second conductive layer of the pixel driving circuit is shown, and the second conductive layer is arranged on the side of the substrate away from the first conductive layer, and an insulating layer is arranged between the first conductive layer and the second conductive layer.
  • the second conductive layer may include: the second end of the compensation capacitor C1, the gate of the third transistor and the fifth signal line S5.
  • the gate of the third transistor T3 may be the portion where the fifth signal line S5 overlaps with the first semiconductor layer.
  • the second semiconductor layer of the pixel driving circuit is shown.
  • the second semiconductor layer is arranged on the side of the substrate away from the second conductive layer.
  • the second semiconductor layer can be made of metal oxide semiconductor material.
  • the second semiconductor layer can be used to make the active layer of the third transistor T3.
  • the orthographic projection of the first signal line S1 on the substrate and the orthographic projection of the active layer of the first transistor T1 on the substrate have an overlapping area, that is, the gate of the first transistor T1 can be the overlapping portion of the first signal line S1 and the first semiconductor layer, and the gate T7-G of the second reset transistor T7 can be the overlapping portion of the fourth scan line GA4 and the first semiconductor layer.
  • the active layer of the first transistor T1 includes a first active portion 11 and a second active portion 12.
  • the first active portion 11 extends along a first direction F1
  • the second active portion 12 extends along a second direction F2.
  • the orthographic projection of the first signal line S1 on the substrate and the orthographic projection of the first active portion 11 on the substrate overlap. That is, the first active portion 11 and the second active portion 12 of the first transistor have an intersection, and the first active portion 11 and the second active portion 12 are arranged in two different directions.
  • the first active portion 11 of the active layer of the first transistor T1 can be the first signal line S1. The portion where the line S1 overlaps with the first semiconductor layer.
  • the substrate further includes a third conductive layer, in which the power signal line ELVDD, the fourth signal line S4, and the fifth signal line (Vinit2 and Vinit1 in FIG12) extend along the first direction F1. Furthermore, as shown in FIG13, the power signal line ELVDD is also arranged along the second direction F2. In the same sub-pixel, the power signal line ELVDD is a mesh connection structure.
  • the above-mentioned setting method can be designed and determined according to the needs of actual applications and is not limited here.
  • the third conductive layer includes a first connection portion 13
  • the second conductive layer includes a second connection portion 14
  • a first insulating layer is provided between the third conductive layer and the second conductive layer
  • a second insulating layer is provided between the second conductive layer and the first conductive layer, that is, in order to ensure the normal operation of each conductive layer, insulating layers are provided between the first conductive layer, the second conductive layer and the third conductive layer, respectively.
  • the power signal line is connected to the second connection portion 14 through a first via hole penetrating the first insulating layer, and the second connection portion is connected to the active layer of the first transistor T2 through a second via hole penetrating the second insulating layer, that is, the conduction of the power signal line between different conductive layers is realized.
  • the power signal line ELVDD and the first signal line S1 extend along the second direction F2.
  • a first portion of the third signal line S3 extends along the second direction F2, and a second portion of the third signal line S3 extends in a direction that is 45 degrees to the lower left of the second direction F2.
  • a portion of the fourth signal line S4 extends in the second direction F2, and another portion of the fourth signal line S4 extends in a direction that is 45 degrees to the upper left of the second direction F2.
  • the signal line connected to the anode of the light-emitting device extends in the direction of the second direction F2, and the signal line of the data signal terminal Data extends approximately in the direction of the second direction F2.
  • an embodiment of the present disclosure provides a driving method for a pixel driving circuit, as shown in FIG16 , including:
  • Step 201 the threshold compensation sub-circuit provides the threshold voltage of the driving transistor to the first terminal of the compensation capacitor in response to the signal at the compensation signal terminal.
  • the second transistor when the signal at the compensation signal end is at a low level, the second transistor is turned on, and the threshold voltage of the driving transistor is written into the first end of the compensation capacitor.
  • Step 202 The data writing sub-circuit responds to the signal at the scanning signal terminal and writes the data at the data signal terminal to the data signal terminal.
  • the data voltage is provided to the second terminal of the compensation capacitor.
  • the third transistor when the signal at the scan signal end is at a low level, the third transistor is turned on, and the data voltage at the data signal end is written into the second end of the compensation capacitor.
  • Step 203 The compensation capacitor stabilizes the voltages at the first terminal and the second terminal.
  • the compensation capacitor is mainly used to stabilize the voltages at its first and second terminals. Due to the voltage stabilization effect of the compensation capacitor, the threshold voltage of the driving transistor and the data voltage at the data signal terminal are written into the gate of the driving transistor.
  • Step 204 the conduction control subcircuit conducts the power signal terminal with the second terminal of the compensation capacitor in response to the signal at the conduction control terminal.
  • the loop connected to the light-emitting device is turned on, that is, the power signal terminal is turned on with the second end of the compensation capacitor, and the driving transistor generates a driving current according to the threshold voltage and the data voltage.
  • Step 205 the light emitting control sub-circuit provides the driving current generated by the driving transistor to the light emitting device in response to the signal at the light emitting control signal terminal.
  • the light emitting control subcircuit when the signal at the light emitting control signal terminal is at a low level, the light emitting control subcircuit is turned on, that is, the driving current generated by the driving transistor DTFT is provided to the anode of the light emitting device L1, so that the light emitting device L1 emits light.
  • the third transistor in the pixel driving circuit of the embodiment of the present application is an N-type transistor, and the other transistors are P-type transistors. In other embodiments, the third transistor is a P-type transistor, and the corresponding other transistors are N-type transistors.
  • a pixel driving circuit in the embodiments of the present disclosure, includes: a driving transistor, a light-emitting device, a compensation capacitor, a threshold compensation subcircuit, a data writing subcircuit, a conduction control subcircuit and a light-emitting control subcircuit.
  • the threshold compensation subcircuit provides the threshold voltage of the driving transistor to the first end of the compensation capacitor in response to a signal at the compensation signal end.
  • the data writing subcircuit provides the data voltage at the data signal end to the second end of the compensation capacitor in response to a signal at the scan signal end.
  • the conduction control subcircuit conducts the power signal end with the second end of the compensation capacitor in response to a signal at the conduction control end.
  • the light-emitting control subcircuit conducts the power signal end with the second end of the compensation capacitor in response to a signal at the conduction control end.
  • the signal at the signal end provides the driving current generated by the driving transistor to the light-emitting device.
  • the setting of the compensation capacitor realizes the time-sharing of threshold compensation and data writing, which satisfies the display of the light-emitting device and realizes high-frequency refresh at the same time.
  • the embodiments of the present disclosure may be provided as methods, systems, or computer program product systems. Therefore, the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present disclosure may take the form of a computer program product system implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.
  • a computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.
  • These computer program instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

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Abstract

一种像素驱动电路、显示面板及驱动方法，该像素驱动电路包括：驱动晶体管（DTFT）、发光器件（L1）、补偿电容（C1）、阈值补偿子电路（200）、数据写入子电路（300）、导通控制子电路（100）和发光控制子电路（400），阈值补偿子电路（200）响应于补偿信号端（S1）的信号，将驱动晶体管（DTFT）的阈值电压提供给补偿电容（C1）的第一端，数据写入子电路（300）响应于扫描信号端（S3）的信号，将数据信号端（Data）的数据电压提供给补偿电容（C1）的第二端，导通控制子电路（100）响应于导通控制端（S4）的信号，将电源信号端（ELVDD）与补偿电容（C1）的第二端导通，发光控制子电路（400）响应于发光控制信号端（S4）的信号，将驱动晶体管（DTFT）产生的驱动电流提供给发光器件（L1），补偿电容（C1）的设置实现了阈值补偿和数据写入的分时进行，满足发光器件（L1）显示的同时实现了高频率刷新。

Description

一种像素驱动电路、显示面板及驱动方法 技术领域
本公开涉及显示技术领域，提供了一种像素驱动电路、显示面板及驱动方法。
背景技术
相关技术中的像素驱动电路的驱动过程中，在数据电压写入驱动晶体管的栅极的阶段，会同步完成驱动晶体管的阈值电压的补偿。但由于上述阈值电压补偿所需的时间较长，随着显示屏刷新率的提高，单位时间的补偿时段大大减小，这样就会导致驱动晶体管的阈值电压的补偿不够充分，进而使显示屏的显示效果较差。
发明内容
本公开实施例提供一种像素驱动电路、显示面板及驱动方法，用以将阈值电压补偿和数据电压的写入分时段进行，以提升高刷新率下阈值电压的补偿效果。
本公开提供的具体技术方案如下：
第一方面，本公开实施例提供了一种像素驱动电路，包括：驱动晶体管、发光器件、补偿电容、阈值补偿子电路、数据写入子电路、导通控制子电路和发光控制子电路；
阈值补偿子电路与驱动晶体管的栅极以及补偿电容的第一端相互耦接，被配置为响应于补偿信号端的信号，将驱动晶体管的阈值电压提供给补偿电容的第一端；
数据写入子电路与补偿电容的第二端耦接，被配置为响应于扫描信号端的信号，将数据信号端的数据电压提供给补偿电容的第二端；
补偿电容，被配置为稳定第一端和第二端的电压；
导通控制子电路与补偿电容的第二端以及电源信号端耦接，被配置为响应于导通控制端的信号，将电源信号端与补偿电容的第二端导通；
发光控制子电路与驱动晶体管以及发光器件耦接，被配置为响应于发光控制信号端的信号，将驱动晶体管产生的驱动电流提供给发光器件。
可选地，导通控制子电路包括：第一晶体管；
第一晶体管的控制端与导通控制端耦接，第一晶体管的第一端与补偿电容的第二端耦接，第一晶体管的第二端与电源信号端耦接。
可选地，数据写入子电路响应于扫描信号端的信号的第一有效电平，将数据信号端的数据电压提供给补偿电容的第二端；
阈值补偿子电路响应于补偿信号端的信号的第二有效电平，将驱动晶体管的阈值电压提供给补偿电容的第一端；
其中，第一有效电平处于第二有效电平的时间段内。
可选地，第一有效电平的高电平时长小于第二有效电平的低电平时长。
可选地，阈值补偿子电路包括：第二晶体管；
第二晶体管的控制端与补偿信号端耦接，第二晶体管的第一端与补偿电容的第一端耦接，第二晶体管的第二端与驱动晶体管的第二端耦接。
可选地，数据写入子电路包括：第三晶体管；
第三晶体管的控制端与扫描信号端耦接，第三晶体管的第一端与数据信号端耦接，第三晶体管的第二端与补偿电容的第二端耦接。
可选地，发光控制子电路包括：第四晶体管和第五晶体管；
第四晶体管的控制端与发光控制信号端耦接，第四晶体管的第一端与电源信号端耦接，第四晶体管的第二端与驱动晶体管的第一端耦接；
第五晶体管的控制端与导通控制端耦接，第五晶体管的第一端与驱动晶体管的第二端耦接，第五晶体管的第二端与发光器件的阳极耦接。
可选地，还包括第一初始化子电路，第一初始化子电路与驱动晶体管的第一端耦接，被配置为响应于第一复位信号端的信号，将第一初始化信号端的信号提供给驱动晶体管的第一端。
可选地，第一初始化子电路包括：第六晶体管；
第六晶体管的控制端与第一复位信号端耦接，第六晶体管的第一端与驱动晶体管的第一端耦接，第六晶体管的第二端与第一初始化信号端耦接。
可选地，还包括第二初始化子电路，第二初始化子电路与发光器件的阳极耦接，被配置为响应于第二复位信号端的信号，将第二初始化信号端的信号提供给发光器件的阳极。
可选地，第二初始化子电路包括：第七晶体管；
第七晶体管的控制端与第二复位信号端耦接，第七晶体管的第一端与发光器件的阳极耦接，第七晶体管的第二端与第二初始化信号端耦接。
可选地，还包括第三初始化子电路，第三初始化子电路与补偿电容的第一端耦接，被配置为响应于第三复位信号端的信号，将第三初始化信号端的信号提供给补偿电容的第一端。
可选地，第三初始化子电路包括：第八晶体管；
第八晶体管的控制端与第三复位信号端耦接，第八晶体管的第一端与补偿电容的第一端耦接，第八晶体管的第二端与第三初始化信号端耦接。
第二方面，本公开实施例还提供了一种显示面板，包括：
衬底基板，包括多个子像素，子像素包括上述任一项的像素驱动电路；
像素驱动电路包括：驱动晶体管、第一晶体管、第三晶体管以及补偿电容，第一晶体管的第一端与补偿电容的第二端耦接，第三晶体管的第二端与补偿电容的第二端耦接，驱动晶体管的栅极与补偿电容的第一端耦接；
第三晶体管的有源层在衬底基板的正投影位于驱动晶体管的有源层在衬底基板的正投影和第一晶体管的有源层在衬底基板的正投影之间。
可选地，显示面板包括：第一半导体层、第一导电层、第二导电层、第二半导体层；
第一半导体层，位于衬底基板上，且第一半导体层包括第一晶体管的有源层和驱动晶体管的有源层；
第一导电层，位于衬底基板背离第一半导体层的一侧，且第一导电层包 括第一晶体管的栅极、驱动晶体管的栅极、第一信号线；
第二导电层，位于衬底基板背离第一导电层的一侧，且第二导电层包括补偿电容的第二端、第三晶体管的栅极和第五信号线；
第二半导体层，位于衬底基板背离第二导电层的一侧，且第二半导体层包括第三晶体管的有源层。
可选地，第一信号线在衬底基板上的正投影与第一晶体管的有源层在衬底基板上的正投影具有交叠区域，交叠区域中的第一信号线为第一晶体管的栅极。
可选地，第一晶体管的有源层包括第一有源部和第二有源部，第一有源部沿第一方向延伸，第二有源部沿第二方向延伸，第一信号线在衬底基板上的正投影与第一有源部在衬底基板上的正投影存在交叠区域。
可选地，还包括第三导电层，第三导电层位于衬底基板背离第二半导体层的一侧，第三导电层包括与电源信号端连接的电源信号线，电源信号线覆盖交叠区域。
可选地，第三导电层包括第一连接部，第二导电层包括第二连接部，第三导电层与第二导电层之间具有第一绝缘层，第二导电层与第一导电层之间具有第二绝缘层；
电源信号线通过贯穿第一绝缘层的第一过孔与第二连接部连接；
第二连接部通过贯穿第二绝缘层的第二过孔与第一晶体管的有源层连接。
第三方面，本公开实施例还提供了一种上述任一项的像素驱动电路的驱动方法，包括：
阈值补偿子电路响应于补偿信号端的信号，将驱动晶体管的阈值电压提供给补偿电容的第一端；
数据写入子电路响应于扫描信号端的信号，将数据信号端的数据电压提供给补偿电容的第二端；
补偿电容稳定第一端和第二端的电压；
导通控制子电路响应于导通控制端的信号，将电源信号端与补偿电容的 第二端导通；
发光控制子电路响应于发光控制信号端的信号，将驱动晶体管产生的驱动电流提供给发光器件。
本公开有益效果如下：
综上所述，本公开实施例中提供了一种像素驱动电路、显示面板及驱动方法，该像素驱动电路包括：驱动晶体管、发光器件、补偿电容、阈值补偿子电路、数据写入子电路、导通控制子电路和发光控制子电路，阈值补偿子电路响应于补偿信号端的信号，将驱动晶体管的阈值电压提供给补偿电容的第一端，数据写入子电路响应于扫描信号端的信号，将数据信号端的数据电压提供给补偿电容的第二端，导通控制子电路响应于导通控制端的信号，将电源信号端与补偿电容的第二端导通，发光控制子电路响应于发光控制信号端的信号，将驱动晶体管产生的驱动电流提供给发光器件，补偿电容的设置实现了阈值补偿和数据写入的分时进行，满足发光器件显示的同时实现了高频率刷新。
本公开的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本公开而了解。本公开的目的和其他优点可通过在所写的说明书、权利要求书、以及附图中所特别指出的结构来实现和获得。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为相关技术中的像素驱动电路的连接示意图；
图2为本公开实施例中一种像素驱动电路的连接示意图；
图3为本公开实施例中一种像素驱动电路的电路连接图；
图4为本公开实施例中另一种像素驱动电路的连接示意图；
图5为本公开实施例中另一种像素驱动电路的电路连接图；
图6为本公开实施例中一种像素驱动电路的时序图；
图7为本公开实施例中的一种显示面板的布局结构示意图；
图8为本公开实施例中的一种显示面板中的第一半导体层的布局结构示意图；
图9为本公开实施例中的一种显示面板中的第一导电层的布局结构示意图；
图10为本公开实施例中的一种显示面板中的第二导电层的布局结构示意图；
图11为本公开实施例中的一种显示面板中的第二半导体层的布局结构示意图；
图12为本公开实施例中的一种显示面板中的第三导电层的布局结构示意图；
图13为本公开实施例中的一种显示面板中的电源信号端所在的膜层的布局结构示意图；
图14为本公开实施例中的一种显示面板中的各连接线所在的膜层的布局结构示意图；
图15为本公开实施例中的另一种显示面板中的各连接线所在的膜层的布局结构示意图；
图16为本公开实施例中一种像素驱动电路的驱动方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开技术方案的一部分实施例，而不是全部的实施例。基于本公开文件中记载的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开技术方案保护的范围。
本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本发明的实施例能够使用除了在这里图示或描述的那些以外的顺序实施。
相关技术中，像素驱动电路的驱动过程中，在数据电压写入驱动晶体管的栅极的阶段，会同步完成驱动晶体管的阈值电压的补偿。但由于上述阈值电压补偿所需的时间较长，随着显示屏刷新率的提高，单位时间的补偿时段大大减小，这样就会导致驱动晶体管的阈值电压的补偿不够充分，进而使显示屏的显示效果较差。
参阅图1所示，以图1所示的像素驱动电路来进行详细说明，图1中的晶体管M3为驱动晶体管，在驱动晶体管的工作过程中，驱动晶体管M3的阈值电压经导通的晶体管M2写入驱动晶体管的栅极，与此同时，数据电压经导通的晶体管T4也写入驱动晶体管的栅极，当上述驱动晶体管所在的显示屏的刷新率较高时，常常会出现补偿时段结束时，阈值电压的补偿仍不充分，从而影响显示屏的显示效果。
下面结合附图对本公开优选的实施方式进行详细说明。
参阅图2所示，本申请实施例中提出的一种像素驱动电路，包括：驱动晶体管DTFT、发光器件L1、补偿电容C1、阈值补偿子电路200、数据写入子电路300、导通控制子电路100和发光控制子电路400。
实施过程中，上述导通控制子电路100与补偿电容C1的第二端以及电源信号端ELVDD耦接，被配置为响应于导通控制端S4的信号，将电源信号端ELVDD与补偿电容C1的第二端导通
参阅图3所示，上述导通控制子电路100包括：第一晶体管T1。
第一晶体管T1与图3中其他元器件之间的连接关系为：第一晶体管T1的控制端与导通控制端S4耦接，第一晶体管T1的第一端与补偿电容C1的第二端耦接，第一晶体管T1的第二端与电源信号端ELVDD耦接。
实施过程中，当导通控制端S4的信号为低电平时，第一晶体管T1的控 制端导通，电源信号端ELVDD的电平经导通的第一晶体管T1提供给补偿电容C1的第二端。
实施过程中，上述阈值补偿子电路200与驱动晶体管DTFT的栅极以及补偿电容C1的第一端相互耦接，被配置为响应于补偿信号端S1的信号，将驱动晶体管DTFT的阈值电压提供给补偿电容C1的第一端。
参阅图3所示，上述阈值补偿子电路200包括：第二晶体管T2。
第二晶体管T2与图3中其他元器件之间的连接关系为：第二晶体管T2的控制端与补偿信号端S1耦接，第二晶体管T2的第一端与补偿电容C1的第一端耦接，第二晶体管T2的第二端与驱动晶体管DTFT的第二端耦接。
需要说明的是，由于，第二晶体管T2直接与补偿电容C1的第一端即驱动晶体管DTFT的栅极相连，因此，实施过程中，可将上述第二晶体管T2更换成IGZO管，这样能够保证不会因为第二晶体管T2的漏电造成驱动晶体管DTFT的栅极的电位发生变化。
实施过程中，当补偿信号端S1的信号为低电平时，第二晶体管T2的控制端为低电平，第二晶体管T2导通，驱动晶体管DTFT的阈值电压经导通的第二晶体管T2提供给补偿电容C1的第一端。
上述数据写入子电路300与补偿电容C1的第二端耦接，被配置为响应于扫描信号端S3的信号，将数据信号端Data的数据电压提供给补偿电容C1的第二端。
参阅图3所示，数据写入子电路300包括：第三晶体管T3。
第三晶体管T3与图3中其他元器件之间的连接关系为：第三晶体管T3的控制端与扫描信号端S3耦接，第三晶体管T3的第一端与数据信号端Data耦接，第三晶体管T3的第二端与补偿电容C1的第二端耦接。
示例性的，本申请实施例中，上述第三晶体管T3为N型晶体管，第三晶体管的有源层的材料为金属氧化物半导体材料，例如IGZO。当第三晶体管T3为N型晶体管时，其他的晶体管为P型晶体管，其他的晶体管的有源层的材料还可以是低温多晶硅(Low Temperature Poly-Silicon，LTPS)等，这里不 做具体的限定。
实施过程中，当扫描信号端S3为高电平时，第三晶体管T3的控制端为高电平，第三晶体管T3导通，数据信号端Data的数据电压经导通的第三晶体管T3提供给补偿电容C1的第二端。
需要补充说明的是，本申请实施例中，为了将阈值补偿和数据写入的过程分别设置在不同的时段进行，将数据写入子电路300和阈值补偿子电路200的有效电平的有效时段进行了如下设置：
具体实施过程中，数据写入子电路300响应于扫描信号端S3的信号的第一有效电平，将数据信号端Data的数据电压提供给补偿电容C1的第二端。
即数据电压写入补偿电容C1的第二端的时长为上述第一有效电平对应的时长。
相应的，阈值补偿子电路200响应于补偿信号端S1的信号的第二有效电平，将驱动晶体管DTFT的阈值电压提供给补偿电容C1的第一端。
即阈值电压写入补偿电容C1的第一端的时长为上述第二有效电平对应的时长。
由于，第三晶体管的类型与其他的晶体管的类型不一样，在一些实施例中，上述第一有效电平可以为高电平，相应的，上述第二有效电平为低电平。在另一些实施例中，上述第一有效电平可以为低电平，相应的，上述第二有效电平为高电平。
需要注意的是，上述第一有效电平处于第二有效电平的时间段内。
即实施过程中，将第一有效电平对应的时间段设置的时长短于第二有效电平对应的时间段设置的时长，从而保证了阈值电压写入电路的时长大于数据电压写入电路的时长。
进一步的，第一有效电平的高电平时长小于第二有效电平的低电平时长。
参阅图3所示，第二晶体管T2为N型晶体管，第三晶体管T3为P型晶体管时，上述第一有效电平为高电平有效，上述第二有效电平为低电平有效，为了保证阈值电压写入的时长足够充分，上述第一有效电平的高电平时长小 于第二有效电平的低电平时长。
上述补偿电容C1，被配置为稳定第一端和第二端的电压。
参阅图3所示，实施过程中，在将驱动晶体管DTFT的阈值电压经导通的第二晶体管T2提供给补偿电容C1的第一端之后，数据电压经导通的第三晶体管T3写入到补偿电容C1的第二端后，第一晶体管T1在导通控制端S4的控制下导通，补偿电容C1的第一端的电压由数据电压跳变为电源信号端ELVDD的电压，为了维持上述补偿电容C1的第一端和第二端的电压的平衡，补偿电容C1的自举作用将上述第一端的电压的跳变量耦合至补偿电容C1的第二端。
实施过程中，驱动晶体管DTFT根据上述阈值电压和数据电压生成驱动电流。
上述发光控制子电路与驱动晶体管DTFT以及发光器件L1耦接，被配置为响应于发光控制信号端S4的信号，将驱动晶体管DTFT产生的驱动电流提供给发光器件L1。
参阅图3所示，发光控制子电路包括：第四晶体管T4和第五晶体管T5。
第四晶体管T4与图3中其他元器件之间的连接关系为：第四晶体管T4的控制端与发光控制信号端S4耦接，第四晶体管T4的第一端与电源信号端ELVDD耦接，第四晶体管T4的第二端与驱动晶体管DTFT的第一端耦接。
实施过程中，当发光控制信号端S4为低电平时，第四晶体管T4导通，电源信号端ELVDD中的信号经导通的第四晶体管T4提供给驱动晶体管DTFT。
第五晶体管T5与图3中其他元器件之间的连接关系为：第五晶体管T5的控制端与导通控制端S4耦接，第五晶体管T5的第一端与驱动晶体管DTFT的第二端耦接，第五晶体管T5的第二端与发光器件L1的阳极耦接。
实施过程中，当导通控制端S4的信号为低电平时，第五晶体管T5导通，驱动晶体管DTFT产生的驱动电流经导通的第五晶体管T5提供给发光器件L1的阳极，以使发光器件L1发光。
此外，参阅图4所示，上述像素驱动电路还包括第一初始化子电路500，上述第一初始化子电路500与驱动晶体管DTFT的第一端耦接，被配置为响应于第一复位信号端S5的信号，将第一初始化信号端Vinit1的信号提供给驱动晶体管DTFT的第一端。
参阅图5所示，上述第一初始化子电路500包括：第六晶体管T6。
第六晶体管T6与图5中其他元器件之间的连接关系为：第六晶体管T6的控制端与第一复位信号端S5耦接，第六晶体管T6的第一端与驱动晶体管DTFT的第一端耦接，第六晶体管T6的第二端与第一初始化信号端Vinit1耦接。
实施过程中，当第一复位信号端S5的信号为低电平时，第六晶体管T6导通，第一初始化信号端Vinit1的第一初始化信号经导通的第六晶体管T6提供给驱动晶体管DTFT的第一端，以对驱动晶体管DTFT的第一端进行复位。
此外，上述像素驱动电路还包括第二初始化子电路600，第二初始化子电路600与发光器件L1的阳极耦接，被配置为响应于第二复位信号端S5的信号，将第二初始化信号端Vinit2的信号提供给发光器件L1的阳极。
参阅图5所示，上述第二初始化子电路600包括：第七晶体管T7。
第七晶体管T7与图5中其他元器件之间的连接关系为：第七晶体管T7的控制端与第二复位信号端S5耦接，第七晶体管T7的第一端与发光器件L1的阳极耦接，第七晶体管T7的第二端与第二初始化信号端Vinit2耦接。
实施过程中，当第二复位信号端S5的信号为低电平时，第七晶体管T7导通，第二初始化信号端Vinit2的第二初始化信号经导通的第七晶体管T7提供给发光器件L1的阳极，以对发光器件L1的阳极进行复位。
此外，上述像素驱动电路还包括第三初始化子电路700，第三初始化子电路700与补偿电容C1的第一端耦接，被配置为响应于第三复位信号端S6的信号，将第三初始化信号端Vinit3的信号提供给补偿电容C1的第一端。
参阅图5所示，上述第三初始化子电路700包括：第八晶体管T8。
第八晶体管T8与图5中其他元器件之间的连接关系为：第八晶体管T8 的控制端与第三复位信号端S6耦接，第八晶体管T8的第一端与补偿电容C1的第一端耦接，第八晶体管T8的第二端与第三初始化信号端Vinit3耦接。
实施过程中，当第三复位信号端S6的信号为低电平时，第八晶体管T8导通，第三初始化信号端Vinit3的第三初始化信号经导通的第八晶体管T8提供给补偿电容C1的第一端，以对补偿电容C1的第一端进行复位。
需要补充说明的是，上述发光器件的阴极与阴极电源端ELVSS耦接，上述阴极电源端ELVSS的电压小于上述电源信号端ELVDD的电压，通过阴极电源端ELVSS和电源信号端ELVDD的设置，能够保障发光器件L1以及外围电路的正常工作。
下面结合时序图6和图3对本申请实施例中的像素驱动电路的工作过程进行详细描述。
时序T1复位阶段：S3＝1，S1＝0，S4＝1，S5＝0，S2＝0
当S1为低电平信号时，第一晶体管T1导通，电源信号端ELVDD的信号提供给第五节点N5，上述第五节点N5与补偿电容C1的第二端耦接，同时，当S1为低电平信号时，第五晶体管T5导通。当S5为低电平信号时，第六晶体管T6导通，第一初始化信号端Vinit1的信号提供给第二节点N2，上述第二节点N2与第六晶体管的第一端耦接，同时，当S5为低电平信号时，第七晶体管T7导通，第二初始化信号端Vinit2的信号提供给N4节点，并且，该第二初始化信号端Vinit2的信号经第四节点N4和导通的第五晶体管T5提供给第三节点N3，上述第四节点N4与发光器件的阳极耦接，上述第三节点N3与驱动晶体管的第二端耦接，由于，当S2为低电平信号时，第二晶体管T2导通，第二初始化信号端Vinit2的信号经第三节点N3和导通的第二晶体管T2提供给第一节点N1，上述第一节点N1与驱动晶体管的栅极耦接。当S2为低电平信号时，第二晶体管T2导通，第一初始化信号端Vinit1的信号提供给第二节点N2。
时序T2补偿阶段：S3＝0，S1＝1，S4＝0，S5＝1，S2＝0
当S2为低电平信号时，第二晶体管T2导通，驱动晶体管DTFT在第一 节点N1的第二初始化信号端Vinit2的信号的作用下导通。当S4为低电平信号时，第四晶体管T4导通，电源信号端ELVDD的信号经导通的第四晶体管T4提供给驱动晶体管DTFT，使驱动晶体管DTFT的栅极的电压变化为Vth+VELVDD，其中，Vth为驱动晶体管DTFT的阈值电压，VELVDD为电源信号端ELVDD的电压，也就是补偿电容C1的第一端。由于，数据写入子电路300的第一有效电平处于阈值补偿子电路200的第二有效电平的时间段内，即S3的低电平的起始时间晚于S2和S4的低电平的起始时间，即上述补偿快要结束时，S3为低电平信号，第三晶体管T3导通，数据信号端Data的数据电压经导通的第三晶体管T3提供给N5节点，也就是补偿电容C1的第二端。
时序T3写入阶段：S3＝1，S1＝0，S4＝0，S5＝1，S2＝1
当S1为低电平信号时，第一晶体管T1导通，电源信号端ELVDD的信号经导通的第一晶体管T1和N5节点写入补偿电容C1的第二端，补偿电容C1的第二端的电压从数据信号端Data的数据电压跳变到VELVDD，电压的变化量为ELVDD-Data，通过上述补偿电容C1的自举作用，将电压的变化量耦合到补偿电容C1的第一端，补偿电容C1的第一端的电压的变化量为Vth+VELVDD+VELVDD-Data，即Vth-Data，从而将数据信号端Data的数据电压写入第一节点N1，也就是驱动晶体管DTFT的栅极。
时序T4发光阶段：S3＝1，S1＝0，S4＝0，S5＝1，S2＝1
当S1为低电平信号时，第五晶体管T5导通，当S4为低电平信号时，第四晶体管T4导通，驱动晶体管DTFT产生驱动电流，示例性的，驱动电流Id＝K*(VELVDD-Data)2，K为常数，驱动电流输入发光器件L1，进而驱动发光器件L1发光。
参阅图7所示，基于同一发明构思，本公开实施例中提供了一种显示面板，包括衬底基板，上述衬底基板包括多个子像素，子像素包括上述任一项的像素驱动电路；像素驱动电路包括：驱动晶体管、第一晶体管、第三晶体管以及补偿电容，第一晶体管的第一端与补偿电容的第二端耦接，第三晶体 管的第二端与补偿电容的第二端耦接，驱动晶体管的栅极与补偿电容的第一端耦接，第三晶体管的有源层在衬底基板的正投影位于驱动晶体管的有源层在衬底基板的正投影和第一晶体管的有源层在衬底基板的正投影之间。即本申请新加入的第一晶体管的有源层和与补偿电容的第二端相耦接的第三晶体管的有源层在同一层中。
图7为本公开一些实施例提供的像素驱动电路的布局(Layout)结构示意图。图8至图15为本公开一些实施例提供的像素驱动电路的各层的示意图。其中，图7至图15所示的示例以一个子像素的像素驱动电路为例。其中，图7至图15还示出了电连接到像素驱动电路的第一信号线S1、第五信号线S5和电源信号线。其中，电源信号线被配置为向电源信号端ELVDD输入电压VELVDD。示例性地，可以使多条信号线沿第一方向F1排列。
示例性地，如图7至图8所示，示出了该像素驱动电路的第一半导体层。第一半导体层可采用非晶硅、低温多晶硅(Low Temperature Poly-Silicon，LTPS)材料图案化形成。第一半导体层可用于制作上述的第一晶体管T1的有源层、第二晶体管T2的有源层、第三晶体管T3的有源层、第五晶体管T5的有源层、第六晶体管T6的有源层、第七晶体管T7的有源层和驱动晶体管DTFT的有源层。并且，各有源层可包括第一区、第二区以及位于第一区和第二区之间的第一沟道区。需要说明的是，上述的第一区和第二区可为第一半导体层中掺杂有n型杂质或p型杂质的区域，以形成的导体化区，从而可以使第一区和第二区作为有源层的源极区和漏极区，以进行电连接。
示例性地，如图7与图8所示，可以使第五晶体管T5的有源层沿第二方向F2大致延伸呈一条直线。例如，第五晶体管T5的有源层的延伸方向与第二方向F2大致平行。需要说明的是，在实际工艺中，由于工艺条件的限制或其他因素，第五晶体管T5的有源层的延伸方向与第二方向并不能完全平行，可能会有一些偏差，因此上述第五晶体管T5的有源层的延伸方向与第二方向只要大致满足平行条件即可，均属于本发明的保护范围。例如，上述相同可以是在误差允许范围之内所允许的平行。
示例性地，在上述的第一半导体层上形成有绝缘层，用于保护上述的第一半导体层。如图9和图10所示，示出了该像素驱动电路的第一导电层。第一导电层设置在衬底基板背离第一半导体层的一侧，从而与第一半导体层绝缘。第一导电层可以包括：第一晶体管T1的栅极、第二晶体管T2的栅极、第三晶体管T3的栅极、第五晶体管T5的栅极、第六晶体管T6的栅极、第七晶体管T7的栅极、驱动晶体管DTFT的栅极、第一信号线S1、第二信号线S2、第三信号线S3和第五信号线S5。示例性的，第一晶体管T1的栅极可以为第一信号线S1与第一半导体层交叠的部分。驱动晶体管DTFT的栅极可以为补偿电容C1的第一端与第一半导体层交叠的部分。
如图10所示，示出了该像素驱动电路的第二导电层，第二导电层设置在衬底基板背离第一导电层的一侧，并且，第一导电层与第二导电层之间设置有绝缘层。上述第二导电层可以包括：补偿电容C1的第二端、第三晶体管的栅极和第五信号线S5。示例性的，第三晶体管T3的栅极可以为第五信号线S5与第一半导体层交叠的部分。
如图11所示，示出了该像素驱动电路的第二半导体层，第二半导体层设置于衬底基板背离第二导电层的一侧，第二半导体层可采用金属氧化物半导体材料。第二半导体层可用于制作上述的第三晶体管T3的有源层。
并且，第一信号线S1在衬底基板的正投影与第一晶体管T1的有源层在衬底基板上的正投影具有交叠区域，即第一晶体管T1的栅极可以为第一信号线S1与第一半导体层交叠的部分，第二复位晶体管T7的栅极T7-G可以为第四扫描线GA4与第一半导体层交叠的部分。
参阅图11所示，上述第一晶体管T1的有源层包括第一有源部11和第二有源部12，第一有源部11沿第一方向F1延伸，第二有源部12沿第二方向F2延伸，第一信号线S1在衬底基板上的正投影与第一有源部11在衬底基板上的正投影存在交叠区域。即上述第一晶体管的第一有源部11和第二有源部12存在交点，并且，上述第一有源部11和第二有源部12分别沿两个不同的方向排列。并且，第一晶体管T1的有源层的第一有源部11可以为第一信号 线S1与第一半导体层交叠的部分。
示例性地，如图12所示，衬底基板还包括第三导电层，在第三导电层中，电源信号线ELVDD、第四信号线S4以及第五信号线(图12中的Vinit2和Vinit1)沿第一方向F1延伸。并且，如图13所示，电源信号线ELVDD还会沿第二方向F2排列。其中，同一子像素中，电源信号线ELVDD为网状连接结构。上述设置方式可以根据实际应用的需求进行设计确定，在此不作限定。
示例性地，第三导电层包括第一连接部13，第二导电层包括第二连接部14，第三导电层与第二导电层之间具有第一绝缘层，第二导电层与第一导电层之间具有第二绝缘层，即为了保证各个导电层的正常工作，上述第一导电层、第二导电层和第三导电层之间分别设置有绝缘层。这样，电源信号线通过贯穿第一绝缘层的第一过孔与第二连接部14连接，第二连接部通过贯穿第二绝缘层的第二过孔与第一晶体管T2的有源层连接，即实现了电源信号线在不同导电层之间的传导。
示例性地，如图14所示，电源信号线ELVDD和第一信号线S1沿第二方向F2延伸。第三信号线S3的第一部分沿第二方向F2延伸，第三信号线S3的第二部分沿与第二方向F2向左下呈45度角的方向延伸。第四信号线S4的一部分沿第二方向F2延伸，第四信号线S4的另一部分沿与第二方向F2向左上呈45度角的方向延伸。示例性地，如图15所示，与发光器件的阳极相连接的信号线沿第二方向F2的方向延伸，数据信号端Data的信号线大致沿第二方向F2的方向延伸。
基于同一发明构思，本公开实施例中提供了一种像素驱动电路的驱动方法，参阅图16所示，包括：
步骤201：阈值补偿子电路响应于补偿信号端的信号，将驱动晶体管的阈值电压提供给补偿电容的第一端。
实施过程中，在补偿信号端的信号为低电平时，第二晶体管导通，上述驱动晶体管的阈值电压被写入补偿电容的第一端。
步骤202：数据写入子电路响应于扫描信号端的信号，将数据信号端的数 据电压提供给补偿电容的第二端。
实施过程中，当扫描信号端的信号为低电平时，第三晶体管导通，数据信号端的数据电压被写入补偿电容的第二端。
步骤203：补偿电容稳定第一端和第二端的电压。
实施过程中，上述补偿电容主要用来稳定其第一端和第二端的电压，由于，补偿电容的稳压作用，进而将上述驱动晶体管的阈值电压和数据信号端的数据电压写入驱动晶体管的栅极。
步骤204：导通控制子电路响应于导通控制端的信号，将电源信号端与补偿电容的第二端导通。
实施过程中，当导通控制端的信号为低电平时，与发光器件相连接的回路导通，即电源信号端与补偿电容的第二端导通，驱动晶体管根据上述阈值电压和数据电压生成驱动电流。
步骤205：发光控制子电路响应于发光控制信号端的信号，将驱动晶体管产生的驱动电流提供给发光器件。
实施过程中，当发光控制信号端的信号为低电平时，发光控制子电路导通，即驱动晶体管DTFT产生的驱动电流提供给发光器件L1的阳极，以使发光器件L1发光。
需要补充说明的是，本申请实施例像素驱动电路中的第三晶体管为N型晶体管，其他晶体管为P型晶体管，在另一些实施例中，上述第三晶体管为P型晶体管，相应的其他晶体管为N型晶体管。
综上所述，本公开实施例中，提供的一种像素驱动电路、显示面板及驱动方法，该像素驱动电路包括：驱动晶体管、发光器件、补偿电容、阈值补偿子电路、数据写入子电路、导通控制子电路和发光控制子电路，阈值补偿子电路响应于补偿信号端的信号，将驱动晶体管的阈值电压提供给补偿电容的第一端，数据写入子电路响应于扫描信号端的信号，将数据信号端的数据电压提供给补偿电容的第二端，导通控制子电路响应于导通控制端的信号，将电源信号端与补偿电容的第二端导通，发光控制子电路响应于发光控制信 号端的信号，将驱动晶体管产生的驱动电流提供给发光器件，补偿电容的设置实现了阈值补偿和数据写入的分时进行，满足发光器件显示的同时实现了高频率刷新。
本领域内的技术人员应明白，本公开的实施例可提供为方法、系统、或计算机程序产品系统。因此，本公开可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本公开可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品系统的形式。
本公开是参照根据本公开的方法、设备(系统)、和计算机程序产品系统的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要 求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (20)

  1. 一种像素驱动电路，其中，包括：驱动晶体管、发光器件、补偿电容、阈值补偿子电路、数据写入子电路、导通控制子电路和发光控制子电路；
    所述阈值补偿子电路与所述驱动晶体管的栅极以及补偿电容的第一端相互耦接，被配置为响应于补偿信号端的信号，将所述驱动晶体管的阈值电压提供给所述补偿电容的第一端；
    所述数据写入子电路与所述补偿电容的第二端耦接，被配置为响应于扫描信号端的信号，将数据信号端的数据电压提供给所述补偿电容的第二端；
    所述补偿电容，被配置为稳定所述第一端和所述第二端的电压；
    所述导通控制子电路与所述补偿电容的第二端以及电源信号端耦接，被配置为响应于导通控制端的信号，将电源信号端与所述补偿电容的第二端导通；
    所述发光控制子电路与所述驱动晶体管以及发光器件耦接，被配置为响应于发光控制信号端的信号，将所述驱动晶体管产生的驱动电流提供给所述发光器件。
  2. 如权利要求1所述的像素驱动电路，其中，所述导通控制子电路包括：第一晶体管；
    所述第一晶体管的控制端与所述导通控制端耦接，所述第一晶体管的第一端与所述补偿电容的第二端耦接，所述第一晶体管的第二端与电源信号端耦接。
  3. 如权利要求1所述的像素驱动电路，其中，所述数据写入子电路响应于扫描信号端的信号的第一有效电平，将数据信号端的数据电压提供给所述补偿电容的第二端；
    所述阈值补偿子电路响应于补偿信号端的信号的第二有效电平，将所述驱动晶体管的阈值电压提供给所述补偿电容的第一端；
    其中，所述第一有效电平处于第二有效电平的时间段内。
  4. 如权利要求3所述的像素驱动电路，其中，所述第一有效电平的高电平时长小于所述第二有效电平的低电平时长。
  5. 如权利要求1～4任一项所述的像素驱动电路，其中，所述阈值补偿子电路包括：第二晶体管；
    所述第二晶体管的控制端与补偿信号端耦接，所述第二晶体管的第一端与所述补偿电容的第一端耦接，所述第二晶体管的第二端与驱动晶体管的第二端耦接。
  6. 如权利要求1～5任一项所述的像素驱动电路，其中，所述数据写入子电路包括：第三晶体管；
    所述第三晶体管的控制端与所述扫描信号端耦接，所述第三晶体管的第一端与所述数据信号端耦接，所述第三晶体管的第二端与所述补偿电容的第二端耦接。
  7. 如权利要求1～6任一项所述的像素驱动电路，其中，所述发光控制子电路包括：第四晶体管和第五晶体管；
    所述第四晶体管的控制端与发光控制信号端耦接，所述第四晶体管的第一端与电源信号端耦接，所述第四晶体管的第二端与驱动晶体管的第一端耦接；
    所述第五晶体管的控制端与导通控制端耦接，所述第五晶体管的第一端与驱动晶体管的第二端耦接，所述第五晶体管的第二端与所述发光器件的阳极耦接。
  8. 如权利要求1～7任一项所述的像素驱动电路，其中，还包括第一初始化子电路，所述第一初始化子电路与所述驱动晶体管的第一端耦接，被配置为响应于第一复位信号端的信号，将第一初始化信号端的信号提供给所述驱动晶体管的第一端。
  9. 如权利要求8所述的像素驱动电路，其中，所述第一初始化子电路包括：第六晶体管；
    所述第六晶体管的控制端与第一复位信号端耦接，所述第六晶体管的第 一端与驱动晶体管的第一端耦接，所述第六晶体管的第二端与所述第一初始化信号端耦接。
  10. 如权利要求1～9任一项所述的像素驱动电路，其中，还包括第二初始化子电路，所述第二初始化子电路与所述发光器件的阳极耦接，被配置为响应于第二复位信号端的信号，将第二初始化信号端的信号提供给所述发光器件的阳极。
  11. 如权利要求10所述的像素驱动电路，其中，所述第二初始化子电路包括：第七晶体管；
    所述第七晶体管的控制端与第二复位信号端耦接，所述第七晶体管的第一端与所述发光器件的阳极耦接，所述第七晶体管的第二端与所述第二初始化信号端耦接。
  12. 如权利要求1～11任一项所述的像素驱动电路，其中，还包括第三初始化子电路，所述第三初始化子电路与所述补偿电容的第一端耦接，被配置为响应于第三复位信号端的信号，将第三初始化信号端的信号提供给所述补偿电容的第一端。
  13. 如权利要求12所述的像素驱动电路，其中，所述第三初始化子电路包括：第八晶体管；
    所述第八晶体管的控制端与第三复位信号端耦接，所述第八晶体管的第一端与所述补偿电容的第一端耦接，所述第八晶体管的第二端与所述第三初始化信号端耦接。
  14. 一种显示面板，其中，包括：
    衬底基板，包括多个子像素，所述子像素包括如权利要求1-13任一项所述的像素驱动电路；
    所述像素驱动电路包括：驱动晶体管、第一晶体管、第三晶体管以及补偿电容，所述第一晶体管的第一端与所述补偿电容的第二端耦接，所述第三晶体管的第二端与所述补偿电容的第二端耦接，所述驱动晶体管的栅极与所述补偿电容的第一端耦接；
    所述第三晶体管的有源层在所述衬底基板的正投影位于所述驱动晶体管的有源层在所述衬底基板的正投影和所述第一晶体管的有源层在所述衬底基板的正投影之间。
  15. 如权利要求14所述的显示面板，其中，所述显示面板包括：第一半导体层、第一导电层、第二导电层、第二半导体层；
    所述第一半导体层，位于所述衬底基板上，且所述第一半导体层包括第一晶体管的有源层和驱动晶体管的有源层；
    所述第一导电层，位于衬底基板背离所述第一半导体层的一侧，且所述第一导电层包括第一晶体管的栅极、驱动晶体管的栅极、第一信号线；
    所述第二导电层，位于所述衬底基板背离所述第一导电层的一侧，且所述第二导电层包括补偿电容的第二端、第三晶体管的栅极和第五信号线；
    所述第二半导体层，位于所述衬底基板背离所述第二导电层的一侧，且所述第二半导体层包括第三晶体管的有源层。
  16. 如权利要求14所述的显示面板，其中，所述第一信号线在所述衬底基板上的正投影与第一晶体管的有源层在所述衬底基板上的正投影具有交叠区域，所述交叠区域中的第一信号线为第一晶体管的栅极。
  17. 如权利要求16所述的显示面板，其中，所述第一晶体管的有源层包括第一有源部和第二有源部，所述第一有源部沿第一方向延伸，所述第二有源部沿第二方向延伸，所述第一信号线在所述衬底基板上的正投影与所述第一有源部在所述衬底基板上的正投影存在所述交叠区域。
  18. 如权利要求14所述的显示面板，其中，还包括第三导电层，所述第三导电层位于所述衬底基板背离所述第二半导体层的一侧，所述第三导电层包括与电源信号端连接的电源信号线，所述电源信号线覆盖所述交叠区域。
  19. 如权利要求14所述的显示面板，其中，所述第三导电层包括第一连接部，所述第二导电层包括第二连接部，所述第三导电层与所述第二导电层之间具有第一绝缘层，所述第二导电层与所述第一导电层之间具有第二绝缘层；
    所述电源信号线通过贯穿第一绝缘层的第一过孔与所述第二连接部连接；
    所述第二连接部通过贯穿第二绝缘层的第二过孔与所述第一晶体管的有源层连接。
  20. 一种如权利要求1-13任一项所述的像素驱动电路的驱动方法，其中，包括：
    阈值补偿子电路响应于补偿信号端的信号，将所述驱动晶体管的阈值电压提供给所述补偿电容的第一端；
    数据写入子电路响应于扫描信号端的信号，将数据信号端的数据电压提供给所述补偿电容的第二端；
    补偿电容稳定所述第一端和所述第二端的电压；
    导通控制子电路响应于导通控制端的信号，将电源信号端与所述补偿电容的第二端导通；
    发光控制子电路响应于发光控制信号端的信号，将所述驱动晶体管产生的驱动电流提供给所述发光器件。
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