Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
  • H01G4/00—Fixed capacitors; Processes of their manufacture
  • H01G4/30—Stacked capacitors

Definitions

• This disclosure relates to multilayer ceramic capacitors with retrofitted side margins, particularly small multilayer ceramic capacitors.
• Patent Document 1 A conventional multilayer ceramic capacitor is described, for example, in Patent Document 1.
• the multilayer ceramic capacitor of the present disclosure is a substantially rectangular parallelepiped laminate including a plurality of internal electrodes and a plurality of dielectric layers that are alternately laminated, and having a first surface and a second surface that face each other in a lamination direction, a laminate having a first side surface, a second side surface, a third side surface, and a fourth side surface around an axis along the stacking direction, and further having a first ridge portion located between the first side surface and the second side surface, a second ridge portion located between the second side surface and the third side surface, a third ridge portion located between the third side surface and the fourth side surface, and a fourth ridge portion located between the fourth side surface and the first side surface; a protective layer that covers an area of the first side surface, the second side surface, the third side surface, and the fourth side surface excluding a predetermined edge portion among the first edge portion, the second edge portion, the third edge portion, and the fourth edge portion;
• the semiconductor device includes a plurality of internal electrodes
• FIG. 1 is a perspective view showing a multilayer ceramic capacitor according to a first embodiment and a second embodiment
• 1 is a perspective view showing a laminate of a multilayer ceramic capacitor in accordance with a first embodiment.
• FIG. 2 is a perspective view showing a protective layer of the multilayer ceramic capacitor in accordance with the first embodiment.
• 1 is a perspective view showing an element part of a multilayer ceramic capacitor in accordance with a first embodiment; 1 is a plan view showing an element part of a multilayer ceramic capacitor in accordance with a first embodiment.
• FIG. FIG. 6 is a perspective view showing a laminate of a multilayer ceramic capacitor in accordance with a second embodiment.
• FIG. 11 is a perspective view showing a protective layer of the multilayer ceramic capacitor in accordance with a second embodiment.
• FIG. 11 is a perspective view showing an element part of a multilayer ceramic capacitor in accordance with a second embodiment.
• FIG. 11 is a plan view showing an element part of a multilayer ceramic capacitor in accordance with a second embodiment.
• FIG. 11 is a perspective view showing an example of a multilayer ceramic capacitor in accordance with a third embodiment.
• FIG. 11 is a perspective view showing another example of the multilayer ceramic capacitor in accordance with the third embodiment.
• FIG. 11 is a perspective view showing an example of a laminate of the multilayer ceramic capacitor in accordance with a third embodiment.
• FIG. 11 is a perspective view showing a protective layer of the multilayer ceramic capacitor in accordance with a third embodiment.
• FIG. 11 is a perspective view showing an element part of a multilayer ceramic capacitor in accordance with a third embodiment.
• FIG. 11 is a perspective view showing another example of the laminate of the multilayer ceramic capacitor in accordance with the third embodiment.
• FIG. 11 is a plan view showing an element part of a multilayer ceramic capacitor in accordance with a third embodiment.
• FIG. 11 is a plan view showing a multilayer ceramic capacitor in accordance with a third embodiment.
• FIG. 11 is a plan view showing a multilayer ceramic capacitor that does not have the features of the multilayer ceramic capacitor in accordance with the third embodiment.
• FIG. 2 is a plan view showing a ceramic green sheet on which an internal electrode pattern is printed.
• FIG. 2 is a plan view showing a ceramic green sheet on which an internal electrode pattern is printed.
• FIG. 1 is a plan view showing a ceramic green sheet on which an internal electrode pattern is printed.
• FIG. 2 is a perspective view illustrating an example of a process for producing a base laminate.
• FIG. 2 is a plan view showing a ceramic green sheet on which a dummy electrode pattern is printed.
• FIG. 11 is a perspective view illustrating another example of the process for producing the base laminate.
• FIG. 2 is a perspective view showing an example of a base laminate.
• FIG. 15 is a perspective view showing a plurality of laminate precursors obtained by cutting the base laminate of FIG. 14 .
• FIG. 2 is a perspective view showing a plurality of laminate precursors aligned on a support sheet.
• FIG. 4 is a perspective view showing a step of attaching a ceramic green sheet for a protective layer to a side surface of the laminate precursor.
• FIG. 4 is a perspective view showing a step of attaching a ceramic green sheet for a protective layer to a side surface of the laminate precursor.
• FIG. 4 is a perspective view showing a step of attaching a ceramic green sheet for a protective layer to a side surface of the laminate precursor.
• FIG. 2 is a perspective view showing an element part precursor;
• FIG. 2 is a perspective view showing an element part on which a first layer of an external electrode is formed.
• a multilayer ceramic capacitor includes a laminate in which multiple ceramic dielectric layers and multiple internal electrode layers are alternately stacked in a predetermined direction (stacking direction).
• a multilayer ceramic capacitor can have a large capacitance, for example, by increasing the overlap area (effective area) between adjacent internal electrode layers in the stacking direction.
• Patent Document 1 discloses a technology for increasing the effective area by exposing multiple internal electrode layers to the side of an unfired laminate, adding a slurry of the ceramic material that constitutes the ceramic dielectric layer to the side to form an unfired side margin portion, and simultaneously firing the laminate and the side margin portion.
• any direction may be considered to be up or down, but in this specification, for convenience, a Cartesian coordinate system XYZ is defined in some drawings.
• the positive side in the Z-axis direction is considered to be up, and terms such as upper surface and lower surface may be used.
• the X-axis direction is also referred to as the first direction or length direction.
• the Y-axis direction is also referred to as the second direction or width direction.
• the Z-axis direction is also referred to as the third direction, height direction, or stacking direction.
• the plan view area means the area of the part or member of interest when viewed along the stacking direction (Z-axis direction).
• the plan view shape means the shape of the part or member of interest when viewed along the stacking direction (Z-axis direction).
• FIG. 1 is a perspective view showing a laminated ceramic capacitor according to the first and second embodiments.
• FIG. 2A is a perspective view showing a laminate of the laminated ceramic capacitor according to the first embodiment
• FIG. 2B is a perspective view showing a protective layer of the laminated ceramic capacitor according to the first embodiment
• FIG. 2C is a perspective view showing a base component of the laminated ceramic capacitor according to the first embodiment
• FIG. 3 is a plan view showing a base component of the laminated ceramic capacitor according to the first embodiment.
• FIG. 4A is a perspective view showing a laminate of the laminated ceramic capacitor according to the second embodiment
• FIG. 4B is a perspective view showing a protective layer of the laminated ceramic capacitor according to the second embodiment
• FIG. 4C is a perspective view showing a base component of the laminated ceramic capacitor according to the second embodiment
• FIG. 5 is a plan view showing a base component of the laminated ceramic capacitor according to the second embodiment. Note that FIGS. 2A, 2B, 4A, and 4B show the laminate or protective layer before polishing, and FIGS. 2C, 3, 4C, and 5 show the base component after polishing.
• the multilayer ceramic capacitor 1 of this embodiment includes a base component 2 and an external electrode 3.
• the base component 2 includes a laminate 4 and a protective layer 5.
• the laminate 4 is constructed by alternately stacking multiple internal electrodes 6 and multiple dielectric layers 7.
• the multiple internal electrodes 6 and multiple dielectric layers 7 are stacked in the stacking direction (Z-axis direction).
• the laminate 4 is substantially rectangular.
• the laminate 4 has a first surface 8a and a second surface 8b that face each other in the stacking direction (Z-axis direction).
• the first surface 8a and the second surface 8b may be perpendicular to the stacking direction.
• the first surface 8a and the second surface 8b may be collectively referred to as the main surfaces 8a and 8b.
• the laminate 4 may be substantially square in plan view. In other words, the main surfaces 8a and 8b may be substantially square in plan view.
• the laminate 4 has a first side 9a, a second side 9b, a third side 9c, and a fourth side 9d around an axis perpendicular to the main surfaces 8a and 8b.
• the first side 9a, the second side 9b, the third side 9c, and the fourth side 9d may be parallel to the stacking direction.
• the laminate 4 also has a first ridge portion 10a located between the first side 9a and the second side 9b, a second ridge portion 10b located between the second side 9b and the third side 9c, a third ridge portion 10c located between the third side 9c and the fourth side 9d, and a fourth ridge portion 10d located between the fourth side 9d and the first side 9a.
• the first ridge portion 10a refers to a portion extending from a region of the first side surface 9a close to the first ridge portion 11a to a region of the second side surface 9b close to the first ridge portion 11a via the first ridge portion 11a, when the ridge formed by the intersection of the first side surface 9a and the second side surface 9b is defined as the first ridge portion 11a.
• the corner portion of the laminate 4 extending from the first side surface 9a to the second side surface 9b may be chamfered, and in this case, the edge extending in the third direction in the chamfered portion may be defined as the first ridge portion 11a.
• first side surface 9a, the second side surface 9b, the third side surface 9c, and the fourth side surface 9d may be collectively referred to as the side surfaces 9a to 9d.
• first edge portion 10a, the second edge portion 10b, the third edge portion 10c, and the fourth edge portion 10d may be collectively referred to as edge portions 10a to 10d.
• the internal electrode 6 is made of a conductive material.
• the internal electrode 6 may be made of a metal material mainly composed of metals such as Ni (nickel), Cu (copper), Sn (tin), Pt (platinum), Pd (palladium), Ag (silver), Au (gold), etc., or alloys thereof.
• the term "main component” refers to the component that is contained in the highest proportion in the material or member of interest.
• the internal electrode 6 may have a thickness of, for example, 1.5 ⁇ m or less. In this case, internal defects caused by internal stress when the laminate 4 is fired or when a voltage is applied to the internal electrode 6 can be reduced, and the reliability of the multilayer ceramic capacitor 1 can be improved.
• the dielectric layer 7 is made of a dielectric material.
• the dielectric layer 7 may be made of a ceramic material mainly composed of BaTiO 3 (barium titanate), CaTiO 3 (calcium titanate), SrTiO 3 (strontium titanate), BaZrO 3 (barium zirconate), etc.
• the ceramic material constituting the dielectric layer 7 may contain Mn (manganese) compounds, Mg (magnesium) compounds, Si (silicon) compounds, Co (cobalt) compounds, Ni compounds, rare earth compounds, etc. as subcomponents whose content is lower than that of the main component.
• the dielectric layer 7 may have a thickness of, for example, 0.1 ⁇ m or more and 10 ⁇ m or less.
• the multiple internal electrodes 6 include at least one first internal electrode 6a and at least one second internal electrode 6b.
• the first internal electrode 6a and the second internal electrode 6b have polarities different from each other, and when the first internal electrode 6a has a first polarity, the second internal electrode 6b has a second polarity different from the first polarity.
• the first internal electrode 6a and the second internal electrode 6b are arranged alternately in the stacking direction with the dielectric layer 7 sandwiched therebetween.
• the first internal electrode 6a is exposed in a region of the side surfaces 9a to 9d of the laminate 4 excluding at least one of the ridge portions 10a to 10d.
• the second internal electrode 6b is exposed in a region of the side surfaces 9a to 9d of the laminate 4 excluding at least one of the ridge portions 10a to 10d.
• the first internal electrode 6a is exposed in a region of the side surfaces 9a to 9d excluding the second ridge portion 10b
• the second internal electrode 6b is exposed in a region of the side surfaces 9a to 9d excluding the first ridge portion 10a.
• the ridge portion (second ridge portion 10b) where the first internal electrode 6a is not exposed is different from the ridge portion (first ridge portion 10a) where the second internal electrode 6b is not exposed.
• the number of edges where the first internal electrode 6a is not exposed may be the same as the number of edges where the second internal electrode 6b is not exposed. In this case, it is easy to ensure the characteristics of the multilayer ceramic capacitor.
• the first internal electrode 6a has a notch 12b in a substantially right-angled triangular shape with its apex (right-angled apex) located on the second edge 11b in a plan view.
• the first internal electrode 6a has the same shape in a plan view as the laminate 4, except for the notch 12b.
• the second internal electrode 6b has a notch 12a in a substantially right-angled triangular shape with its apex (right-angled apex) located on the first edge 11a in a plan view.
• the second internal electrode 6b has the same shape in a plan view as the laminate 4, except for the notch 12a.
• the effective area contributing to the capacitance is reduced by the area of the notches 12a and 12b compared to the plan view area of the laminate 4. Therefore, from the viewpoint of increasing the capacitance of the multilayer ceramic capacitor 1, the smaller the area of the notches 12a and 12b (the sum of the areas of the notches 12a and 12b), the better.
• the planar shape of the notch 12b of the first internal electrode 6a may be an approximately right-angled isosceles triangle.
• the planar shape of the notch 12b is not limited to an approximately right-angled triangle.
• the planar shape of the notch 12b may be a rectangle with one vertex located on the second edge 11b, a sector (quadrants) with its center located on the second edge 11b, or the like.
• the notch may be a right-angled triangle with a vertex located on the edge of the edge, or a right-angled triangle with a right-angled hypotenuse bulging in an arc shape.
• planar shape of the notch 12b is an approximately right-angled isosceles triangle, it becomes easier to print the internal electrode pattern having a hole that becomes the notch 12b (the square-shaped hole in the internal electrode pattern shown in Figures 9A and 9B) in the manufacturing process of the multilayer ceramic capacitor 1. The same applies to the notch 12a of the second internal electrode 6b.
• the protective layer 5 is located on the side surfaces 9a to 9d of the laminate 4 and forms a side margin.
• the protective layer 5 covers the areas of the side surfaces 9a to 9d excluding predetermined ridges among the ridges 10a to 10d.
• the predetermined ridges that are not covered by the protective layer 5 are ridges where one of the first internal electrode 6a and the second internal electrode 6b is exposed and the other is not exposed.
• the protective layer 5 covers the areas of the side surfaces 9a to 9d excluding the first ridge portion 10a and the second ridge portion 10b. In other words, the protective layer 5 covers at least the areas where the first internal electrode 6a and the second internal electrode 6b overlap and are exposed when the side surfaces 9a to 9d are viewed in the stacking direction.
• the protective layer 5 is made of a dielectric material.
• the protective layer 5 may be made of a ceramic material mainly composed of, for example, BaTiO 3 , CaTiO 3 , SrTiO 3 , BaZrO 3 , etc.
• the ceramic material constituting the protective layer 5 may contain, as a subcomponent, a Mn compound, a Mg compound, a Si compound, a Co compound, a Ni compound, a rare earth compound, etc.
• the protective layer 5 may be made of a ceramic material mainly composed of the same material as the ceramic material constituting the dielectric layer 7.
• the protective layer 5 electrically insulates the external electrode 3 and the internal electrode 6 of different polarities from each other.
• the protective layer 5 also electrically insulates the ends of the internal electrodes 6 of different polarities exposed on the side surfaces 9a to 9d from each other, and also physically protects the ends of the internal electrodes 6 exposed on the side surfaces 9a to 9d.
• the distance between the ends of the protective layer 5 is longer than the distance between the two ends of the internal electrodes 6 exposed on the side surfaces. This reduces the possibility of a short circuit caused by the internal electrodes being exposed from the protective layer.
• the effective area of the internal electrodes 6 is increased and the distance between the two ends of the internal electrodes 6 exposed on the side surfaces is increased, the distance between the ends of the protective layer 5 is increased, thereby reducing the possibility of the internal electrodes 6 being exposed from the protective layer 5 and reducing the possibility of a short circuit with the external electrode 3.
• This increases the ratio of the effective area to the planar area of the element component 2, making it possible to reduce the size of the multilayer ceramic capacitor 1 while increasing its capacitance.
• the effective area refers to the overlapping area in the stacking direction between adjacent internal electrodes 6.
• the protective layer 5 may have a thickness of, for example, 30 ⁇ m or less.
• the protective layer 5 may be located in the first region R1 and the second region R2 within a range that does not reach the ridges of the predetermined ridge portions.
• the external electrodes 3 and internal electrodes 6 of the same polarity can be connected to each other, while the external electrodes 3 and internal electrodes 6 of different polarities can be electrically insulated from each other.
• the external electrode 3 is made of a conductive material.
• the external electrode 3 includes a first external electrode 3a and a second external electrode 3b.
• the first external electrode 3a and the second external electrode 3b are electrically insulated from each other.
• the first external electrode 3a is located from the first side surface 9a to at least one of the second side surface 9b, the fourth side surface 9d, and the first surface 8a and the second surface 8b.
• the first external electrode 3a covers the first ridge portion 10a and is connected to the first internal electrode 6a exposed at the first ridge portion 10a.
• the first external electrode 3a may be located from the first side surface 9a to at least one of the first surface 8a and the second surface 8b.
• the second external electrode 3b is located from the third side surface 9c to at least one of the second side surface 9b, the fourth side surface 9d, and the first surface 8a and the second surface 8b.
• the second external electrode 3b covers the second ridge portion 10b and is connected to the second internal electrode 6b exposed at the second ridge portion 10b.
• the second external electrode 3b may be located from the third side surface 9c to at least one of the first surface 8a and the second surface 8b.
• the second external electrode 3b When the first external electrode 3a is located on the first surface 8a, the second external electrode 3b may also be located on the first surface 8a, and when the first external electrode 3a is located on the second surface 8b, the second external electrode 3b may also be located on the second surface 8b.
• the first surface 8a or the second surface 8b on which the first external electrode 3a and the second external electrode 3b are located is mounted facing the mounting surface of the substrate, so that the multilayer ceramic capacitor 1 can be easily mounted on the substrate.
• the second external electrode 3b When the first external electrode 3a is located on the first surface 8a and the second surface 8b, the second external electrode 3b may also be located on the first surface 8a and the second surface 8b. In this case, when mounting the multilayer ceramic capacitor 1 on a substrate, either the first surface 8a or the second surface 8b may be opposed to the mounting surface, so that the mounting process can be simplified.
• the multilayer ceramic capacitor 1 has a minimum distance between the external electrode 3 of a first polarity and the internal electrode 6 of a second polarity that is equal to or greater than a predetermined insulation distance H.
• the insulation distance H may be, for example, approximately the thickness of the protective layer 5.
• the external electrode 3 may be configured to include a first layer in contact with the element component 2 and a second layer covering the first layer.
• the first layer may be a sintered metal layer.
• the first layer may be formed by baking a conductive paste containing a metal material such as Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc., onto the surface of the element component 2.
• the first layer may be formed by baking a conductive paste containing the material by sputtering onto the surface of the element component 2.
• the first layer may also be a vapor-deposited metal film.
• a metal film of Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. may be formed by sputtering.
• the first layer may also be a conductive resin.
• the second layer may be an epoxy resin or a phenolic resin containing a metal powder such as Ag.
• the second layer may be a plating layer.
• the second layer may be formed by a plating method such as an electroless plating method or an electrolytic plating method.
• the second layer may be configured to include, for example, a Ni plating layer and a Sn plating layer covering the Ni plating layer.
• the second layer may include, for example, a Sn plating layer, a Cu plating layer, an Au plating layer, etc.
• the second layer may also be configured by stacking multiple plating layers.
• the external electrode 3 may be composed of only a plating layer. In this case, the thickness of the external electrode 3 can be made thin, allowing the multilayer ceramic capacitor 1 to be made smaller.
• the external electrode 3 may be composed of a conductive resin paste. In this case, the stress generated when mounting the multilayer ceramic capacitor 1 on a substrate can be alleviated, reducing the risk of cracks occurring in the element component 2, thereby improving the reliability of the mounting structure formed by mounting the multilayer ceramic capacitor 1 on a substrate. In addition, when the multilayer ceramic capacitor 1 is mounted on a substrate for use, it is possible to reduce noise from the substrate due to electrostriction when voltage is applied.
• the first internal electrode 6a has a rectangular cutout with its long side located on the third side surface 9c
• the second internal electrode 6b has a rectangular cutout with its long side located on the first side surface 9a
• the length of the short side of the rectangular cutout needs to be approximately the insulation distance H, which may result in a lower ratio of the effective area to the plan view area of the base component 2.
• the cutouts 12a, 12b are located only at the corners including the first ridge 10a and the second ridge 10b of the laminate 4, so that the area of the cutouts 12a, 12b can be reduced and the ratio of the effective area to the planar area of the base component 2 can be increased. Therefore, according to the first embodiment, a multilayer ceramic capacitor 1 that is small and has a large capacitance can be provided.
• the cutouts 12a, 12b are located at the corners including the first ridge 10a and the second ridge 10b of the laminate 4, but the same function and effect can be achieved even if they are located at the corners including the first ridge 10a and the third ridge 10c.
• the multilayer ceramic capacitor 1A of this embodiment differs from the multilayer ceramic capacitor 1 of the above embodiment in the configuration of the internal electrodes 6 and protective layer 5, but has a similar configuration in other respects. Therefore, the same reference characters as those in the multilayer ceramic capacitor 1 are used for the similar configuration, and detailed description will be omitted.
• the multilayer ceramic capacitor 1A includes an element component 2 and an external electrode 3, as shown in FIG. 1.
• the element component 2 includes a laminate 4 and a protective layer 5, as shown in FIGS. 4A, 4B, and 4C.
• the laminate 4 is formed by alternately stacking a plurality of internal electrodes 6 and a plurality of dielectric layers 7.
• the plurality of internal electrodes 6 include at least one first internal electrode 6a and at least one second internal electrode 6b.
• the first internal electrode 6a and the second internal electrode 6b have mutually opposite polarities.
• the laminate 4 may be substantially square in plan view. In other words, the main surfaces 8a, 8b may be substantially square in plan view.
• the first internal electrode 6a is exposed in the area of the side surfaces 9a to 9d of the laminate 4 excluding the second edge portion 10b and the third edge portion 10c.
• the first internal electrode 6a has a right-angled triangular cutout portion 12b whose apex (right-angled apex) is located on the second edge 11b, and a right-angled triangular cutout portion 12c whose apex (right-angled apex) is located on the third edge 11c.
• the first internal electrode 6a has the same shape in a plan view as the laminate 4, except for the cutout portions 12b and 12c.
• the second internal electrode 6b is exposed in the area of the side surfaces 9a to 9d of the laminate 4 excluding the fourth edge portion 10d and the first edge portion 10a.
• the second internal electrode 6b has a right-angled triangular cutout portion 12d whose apex (right-angled apex) is located on the fourth edge 11d, and a right-angled triangular cutout portion 12a whose apex (right-angled apex) is located on the first edge 11a.
• the second internal electrode 6b has the same shape in a plan view as the laminate 4, except for the cutout portions 12d and 12a.
• the protective layer 5 covers the areas of the sides 9a to 9d except for the first edge portion 10a, the second edge portion 10b, the third edge portion 10c, and the fourth edge portion 10d.
• the first external electrode 3a is located from the first side surface 9a to at least one of the second side surface 9b, the fourth side surface 9d, and the first surface 8a and the second surface 8b.
• the first external electrode 3a covers the fourth ridge portion 10d and the first ridge portion 10a, and is connected to the first internal electrode 6a exposed at the fourth ridge portion 10d and the first ridge portion 10a.
• the first external electrode 3a may be located from the first side surface 9a to at least one of the first surface 8a and the second surface 8b.
• the second external electrode 3b is located from the third side surface 9c to at least one of the second side surface 9b, the fourth side surface 9d, and the first surface 8a and the second surface 8b.
• the second external electrode 3b covers the second ridge portion 10b and the third ridge portion 10c, and is connected to the second internal electrode 6b exposed at the second ridge portion 10b and the third ridge portion 10c.
• the second external electrode 3b may be located from the third side surface 9c to at least one of the first surface 8a and the second surface 8b.
• the multilayer ceramic capacitor 1A has a slightly lower capacitance than the multilayer ceramic capacitor 1 because the first internal electrode 6a has the notches 12d, 12a and the second internal electrode 6b has the notches 12b, 12c, and therefore the ratio of the effective area to the planar area of the element component 2 is slightly lower than that of the multilayer ceramic capacitor 1.
• the multilayer ceramic capacitor 1A has a lower equivalent series resistance (ESR) than the multilayer ceramic capacitor 1 because the first external electrode 3a is connected to the first internal electrode 6a at the fourth ridge 10d and the first ridge 10a, and the second external electrode 3b is connected to the second internal electrode 6b at the second ridge 10b and the third ridge 10c.
• ESR equivalent series resistance
• the multilayer ceramic capacitor 1 and the multilayer ceramic capacitor 1A may be used appropriately according to the required characteristics of the electronic circuit in which the multilayer ceramic capacitors 1 and 1A are used.
• FIG. 6A is a perspective view showing an example of the multilayer ceramic capacitor according to the third embodiment
• FIG. 6B is a perspective view showing another example of the multilayer ceramic capacitor according to the third embodiment
• FIG. 7A is a perspective view showing an example of a laminate of the multilayer ceramic capacitor according to the third embodiment
• FIG. 7B is a perspective view showing a protective layer of the multilayer ceramic capacitor according to the third embodiment
• FIG. 7C is a perspective view showing an element part of the multilayer ceramic capacitor according to the third embodiment
• FIG. 7D is a perspective view showing another example of the laminate of the multilayer ceramic capacitor according to the third embodiment.
• FIG. 7A is a perspective view showing an example of a laminate of the multilayer ceramic capacitor according to the third embodiment
• FIG. 7B is a perspective view showing a protective layer of the multilayer ceramic capacitor according to the third embodiment
• FIG. 7C is a perspective view showing an element part of the multilayer ceramic capacitor according to the third embodiment
• FIG. 7D is a perspective view showing another
• FIG. 8 is a plan view showing an element part of the multilayer ceramic capacitor according to the third embodiment.
• FIG. 9A is a plan view showing the multilayer ceramic capacitor according to the third embodiment
• FIG. 9B is a plan view showing a multilayer ceramic capacitor that does not have the characteristics of the multilayer ceramic capacitor according to the third embodiment.
• FIGS. 7A, 7B, and 7D show the laminate or protective layer before polishing
• FIGS. 7C and 8 show the element part after polishing.
• the multilayer ceramic capacitor 1B of this embodiment differs from the multilayer ceramic capacitor 1 of the above embodiment in the configuration of the internal electrode 6, protective layer 5, and external electrode 3, but is otherwise similar in configuration, so the same reference characters as in the multilayer ceramic capacitor 1 are used for the similar configuration and detailed description is omitted.
• the multilayer ceramic capacitor 1B includes a base component 2 and an external electrode 3.
• the base component 2 includes a laminate 4 and a protective layer 5.
• the laminate 4 is formed by alternately stacking a plurality of internal electrodes 6 and a plurality of dielectric layers 7.
• the multiple internal electrodes 6 include at least one first internal electrode 6a and at least one second internal electrode 6b.
• the first internal electrode 6a and the second internal electrode 6b have polarities opposite to each other.
• the laminate 4 may be substantially square in plan view.
• the main surfaces 8a and 8b may be substantially square in plan view.
• the first internal electrode 6a is exposed in the area of the side surfaces 9a to 9d of the laminate 4 excluding the second edge portion 10b and the fourth edge portion 10d.
• the first internal electrode 6a has a right-angled triangular cutout portion 12b whose apex (right-angled apex) is located on the second edge 11b, and a right-angled triangular cutout portion 12d whose apex (right-angled apex) is located on the fourth edge 11d.
• the first internal electrode 6a has the same shape in a plan view as the laminate 4, except for the cutout portions 12b and 12d.
• the second internal electrode 6b is exposed in the area of the side surfaces 9a to 9d of the laminate 4 excluding the first edge portion 10a and the third edge portion 10c.
• the second internal electrode 6b has a right-angled triangular cutout portion 12a whose apex (right-angled apex) is located on the first edge 11a, and a right-angled triangular cutout portion 12c whose apex (right-angled apex) is located on the third edge 11c.
• the second internal electrode 6b has the same shape in a plan view as the laminate 4, except for the cutout portions 12a and 12c.
• the protective layer 5 covers the areas of the sides 9a to 9d except for the first edge portion 10a, the second edge portion 10b, the third edge portion 10c, and the fourth edge portion 10d.
• the external electrodes 3 include a first external electrode 3a, a second external electrode 3b, a third external electrode 3c, and a fourth external electrode 3d.
• the first external electrode 3a and the third external electrode 3c are electrically insulated from the second external electrode 3b and the fourth external electrode 3d.
• the first external electrode 3a is located from the first side surface 9a to the second side surface 9b and at least one of the first surface 8a and the second surface 8b.
• the first external electrode 3a covers the first ridge portion 10a and is connected to the first internal electrode 6a exposed at the first ridge portion 10a.
• the first external electrode 3a may be located from the first side surface 9a to at least one of the first surface 8a and the second surface 8b.
• the second external electrode 3b is located from the second side surface 9b to the third side surface 9c and at least one of the first surface 8a and the second surface 8b.
• the second external electrode 3b covers the second ridge portion 10b and is connected to the second internal electrode 6b exposed at the second ridge portion 10b.
• the second external electrode 3b may be located from the second side surface 9b to at least one of the first surface 8a and the second surface 8b.
• the third external electrode 3c is located from the third side surface 9c to the fourth side surface 9d and at least one of the first surface 8a and the second surface 8b.
• the third external electrode 3c covers the third ridge portion 10c and is connected to the first internal electrode 6a exposed at the third ridge portion 10c.
• the third external electrode 3c may be located from the third side surface 9c to at least one of the first surface 8a and the second surface 8b.
• the fourth external electrode 3d is located from the fourth side surface 9d to at least one of the first side surface 9a, and the first surface 8a and the second surface 8b.
• the fourth external electrode 3d covers the fourth ridge portion 10d and is connected to the second internal electrode 6b exposed at the fourth ridge portion 10d.
• the fourth external electrode 3d may be located from the fourth side surface 9d to at least one of the first surface 8a and the second surface 8b.
• the external electrode 3 may be substantially rectangular when viewed in a direction perpendicular to the side surfaces 9a to 9d.
• the contact area between the element component 2 and each of the first external electrode 3a, the second external electrode 3b, the third external electrode 3c, and the fourth external electrode 3d can be increased.
• the adhesion between the external electrode 3 and the element component 2 can be increased, improving the reliability of the multilayer ceramic capacitor 1B.
• the first internal electrode 6a has the notches 12b, 12d
• the second internal electrode 6b has the notches 12a, 12c, so that the ratio of the effective area to the planar area of the element component 2 is slightly lower than that of the multilayer ceramic capacitor 1, resulting in a slightly lower capacitance.
• the external electrode 3 is connected to the internal electrode 6 at the four edges 10a to 10d, so that the multilayer ceramic capacitor 1B has a lower equivalent series resistance (ESR) than the multilayer ceramic capacitor 1.
• ESR equivalent series resistance
• the multilayer ceramic capacitors 1, 1A, and 1B may be used appropriately depending on the required characteristics of the electronic circuit in which the multilayer ceramic capacitors 1, 1A, and 1B are used.
• the external electrode 3 may be U-shaped when viewed in a direction perpendicular to the side surfaces 9a to 9d.
• the external electrode 3 when mounting the multilayer ceramic capacitor 1B on a substrate, it is possible to reduce the creeping up of the solder paste and improve reliability against substrate deflection and temperature cycles. It is also possible to reduce the occurrence of short circuits between the first external electrode 3a and the third external electrode 3c and the second external electrode 3b and the fourth external electrode 3d due to migration. As a result, it is possible to improve the reliability of a mounting structure in which the multilayer ceramic capacitor 1B is mounted on a substrate.
• the multilayer ceramic capacitor 1B may be configured such that the first external electrode 3a, the second external electrode 3b, the third external electrode 3c, and the fourth external electrode 3d are all located on at least one of the first surface 8a and the second surface 8b.
• the first surface 8a or the second surface 8b on which the first external electrode 3a, the second external electrode 3b, the third external electrode 3c, and the fourth external electrode 3d are all located is mounted facing the mounting surface of the substrate, thereby making it possible to easily mount the multilayer ceramic capacitor 1B on the substrate.
• the multilayer ceramic capacitor 1B may be configured such that the first external electrode 3a, the second external electrode 3b, the third external electrode 3c, and the fourth external electrode 3d are all located on both the first surface 8a and the second surface 8b.
• first surface 8a or the second surface 8b may face the mounting surface, simplifying the mounting process.
• the multilayer ceramic capacitor 1B is configured so that its electrical characteristics do not change even if it is rotated 90° around an axis along the lamination direction (Z-axis direction) when mounted on a substrate. For this reason, multilayer ceramic capacitor 1B can simplify the mounting process.
• the laminate 4 includes a capacitance forming portion 40, and a first cover layer 41 and a second cover layer 42 located at both ends of the capacitance forming portion in the stacking direction (Z-axis direction).
• the capacitance forming portion 40 is configured by alternately stacking a plurality of internal electrodes 6 and a plurality of dielectric layers 7, and forms a capacitance.
• the first cover layer 41 and the second cover layer 42 protect the capacitance forming portion 40.
• the first cover layer 41 includes a dielectric 41a and a plurality of first dummy electrodes 41b.
• the plurality of first dummy electrodes 41b are exposed on the first surface 8a and the side surfaces 9a to 9d, and are connected to the external electrode 3.
• the plurality of first dummy electrodes 41b do not connect the first external electrode 3a, the second external electrode 3b, the third external electrode 3c, and the fourth external electrode 3d to one another.
• the second cover layer 42 includes a dielectric 42a and a plurality of second dummy electrodes 42b.
• the plurality of second dummy electrodes 42b are exposed on the second surface 8b and the side surfaces 9a to 9d, and are connected to the external electrode 3.
• the plurality of second dummy electrodes 42b do not connect the first external electrode 3a, the second external electrode 3b, the third external electrode 3c, and the fourth external electrode 3d to one another.
• the dielectrics 41a, 42a are made of a dielectric material.
• the dielectrics 41a, 42a may be made of a ceramic material having the same main component as the ceramic material that constitutes the dielectric layer 7.
• the first dummy electrode 41b and the second dummy electrode 42b are made of a conductive material.
• the first dummy electrode 41b and the second dummy electrode 42b may be made of a metallic material having the same main component as the metallic material that constitutes the internal electrode 6.
• the laminate 4 shown in FIG. 7D can increase the contact area between the base component 2 and each of the first external electrode 3a, the second external electrode 3b, the third external electrode 3c, and the fourth external electrode 3d. As a result, the adhesion between the external electrodes 3 and the base component 2 can be further improved, and the reliability of the laminated ceramic capacitor 1B can be further improved.
• the multiple first dummy electrodes 41b may be separated from each other in the stacking direction (Z-axis direction) with the dielectric 41a therebetween, or may be integrated. The same applies to the multiple second dummy electrodes 42b.
• Figure 9A shows the multilayer ceramic capacitor 1B of this embodiment
• Figure 9B shows a multilayer ceramic capacitor (hereinafter also referred to as multilayer ceramic capacitor C) that does not have the characteristics of the multilayer ceramic capacitor 1B.
• the multilayer ceramic capacitor C is a multilayer ceramic capacitor manufactured by a manufacturing method that does not add a side margin.
• the multilayer ceramic capacitor C has the same appearance as the multilayer ceramic capacitor 1B, but differs from the multilayer ceramic capacitor 1B in the configuration of the laminate 4, particularly the side margin and the internal electrode 6.
• the thickness of the side margin needs to be set relatively large in order to reduce the exposure of the internal electrode to the side surface of the laminate during the manufacture of the laminate.
• the area surrounded by a dashed line indicates the area that contributes to the formation of the capacitance in the internal electrode 6.
• the length L and width W were set to 0.6 mm
• the thickness SM of protective layer 5 was set to 0.032 mm
• the length b along the side of each edge was set to 0.08 mm
• the length L1 and width L1 of element component 2 were set to 0.57 mm.
• the length L and width W were set to 0.6 mm
• the thickness SM of the side margin was set to 0.57 mm.
• the length L1 and width L1 of element component of multilayer ceramic capacitor C were set to 0.57 mm.
• multilayer ceramic capacitor 1B is referred to as capacitor 1B
• multilayer ceramic capacitor C is referred to as capacitor C.
• the capacitance contribution area in Table 1 indicates the effective area of multilayer ceramic capacitor 1B and multilayer ceramic capacitor C.
• the area ratio in Table 1 indicates the ratio of the capacitance contribution area of multilayer ceramic capacitor 1B to the capacitance contribution area of multilayer ceramic capacitor C.
• Multilayer ceramic capacitor 1B has an area ratio of 1.1, which means that its effective area is increased by 10% compared to multilayer ceramic capacitor C. Since the capacitance of a multilayer ceramic capacitor is proportional to its effective area, it can be said that multilayer ceramic capacitor 1B has a capacitance increased by 10% compared to multilayer ceramic capacitor C.
• FIGS. 10A and 10B are plan views showing ceramic green sheets on which an internal electrode pattern is printed
• FIG. 11 is a perspective view illustrating an example of a process for producing a mother laminate
• FIG. 12 is a plan view showing a ceramic green sheet on which a dummy electrode pattern is printed
• FIG. 13 is a perspective view illustrating another example of a process for producing a mother laminate
• FIG. 14 is a perspective view showing an example of a mother laminate.
• FIG. 15 is a perspective view showing a plurality of laminate precursors obtained by cutting the mother laminate of FIG. 14,
• FIG. 16 is a perspective view showing a plurality of laminate precursors aligned on a support sheet, and FIGS.
• FIG. 17A, 17B, and 17C are perspective views showing a process for forming a protective layer precursor on the side of the laminate precursor.
• FIG. 18A is a perspective view showing a base part precursor
• FIG. 18B is a perspective view showing a base part
• FIG. 18C is a perspective view showing a base part on which a first layer of an external electrode is formed.
• the internal electrode patterns, dummy electrode patterns, and external electrode inks are shown hatched to facilitate illustration. Note that the internal electrode patterns are shown with grid-like cutting lines that do not actually exist to make it easier to understand the areas that are incorporated into the individual laminates.
• a raw material powder mainly composed of BaTiO 3 is prepared.
• an organic vehicle is mixed with the prepared raw material powder to prepare a ceramic slurry.
• the organic vehicle used to prepare the ceramic slurry may be, for example, a resin such as a butyral resin dissolved in a solvent mixed with ethyl alcohol and toluene.
• the prepared ceramic slurry is used to form a ceramic green sheet 13, which will become the dielectric layer 7, on a carrier film by a sheet forming method such as a die coater method, a doctor blade method, or a gravure coater method.
• the thickness of the ceramic green sheet 13 may be, for example, about 0.5 to 5 ⁇ m. The thinner the ceramic green sheet 13 is, the greater the capacitance of the multilayer ceramic capacitor can be.
• an organic vehicle is mixed with a powder mainly composed of a metal such as Ni, Cu, Sn, Pt, Pd, Ag, or Au, or an alloy thereof, to prepare a conductive paste.
• the organic vehicle used to prepare the conductive paste may be, for example, a resin such as ethyl cellulose dissolved in a solvent mixed with a dihydroterpineol-based solvent and butyl cellosolve.
• the dispersant may be, for example, oleic acid, polyethylene glycol, or the like.
• the prepared conductive paste is used to produce ceramic green sheets 13 having an internal electrode pattern that becomes the internal electrodes 6 printed on the main surfaces by a printing method such as screen printing or gravure printing.
• FIGS. 10A and 10B show an example in which a plurality of internal electrode patterns are printed in a row, the plurality of internal electrode patterns may be printed at a distance from each other.
• the ceramic green sheet 13 on which the internal electrode pattern that will become the first internal electrode 6a is printed may be referred to as the first pattern sheet 14.
• the ceramic green sheet 13 on which the internal electrode pattern that will become the second internal electrode 6b is printed may be referred to as the second pattern sheet 15.
• first pattern sheet 14 and the second pattern sheet 15 may be collectively referred to as the pattern sheets 14 and 15.
• the outer periphery of the first pattern sheet 14 and the second pattern sheet 15 may be a margin portion (i.e., a blank portion where no internal electrode pattern is printed).
• FIGS. 10A and 10B show an example in which the first pattern sheet 14 and the second pattern sheet 15 are produced separately, but this is not limiting.
• multiple first pattern sheets 14 may be produced, and when producing a temporary laminate (see FIG. 11), the multiple first pattern sheets 14 may be stacked while being offset by a predetermined distance.
• a predetermined number of pattern sheets 14 and 15 are laminated on top of a predetermined number of laminated ceramic green sheets (also called cover sheets) 13, and a predetermined number of cover sheets 13 are laminated on top of the pattern sheets 14 and 15 to produce a temporary laminate.
• the pattern sheets 14 and 15 may be laminated by alternating first pattern sheets 14 and second pattern sheets 15, or the first pattern sheet 14 may be laminated while shifting it by a predetermined distance.
• the temporary laminate is produced on a support sheet 16.
• the support sheet 16 may be an adhesive release sheet that can be adhered and released, such as a weak adhesive sheet or a foam release sheet.
• the support sheet 16 may be fixed to a base (also called a first base) 17.
• a ceramic green sheet 13 on which a dummy electrode pattern is printed to become dummy electrodes (first dummy electrode 41b and second dummy electrode 42b) that do not contribute to the capacitance of the laminated ceramic capacitor 1B may be used as the cover sheet 13 (see FIG. 12).
• the ceramic green sheet 13 on which the dummy electrode pattern is printed may be referred to as a dummy sheet 18.
• the dummy sheet 18 may have a margin portion (i.e., a blank portion on which the dummy electrode pattern is not printed) at its outer periphery.
• the laminate 13 shows an example of preparing a provisional laminate by stacking a predetermined number of pattern sheets 14 and 15 on a predetermined number of stacked dummy sheets 18, and stacking a predetermined number of dummy sheets 18 on the pattern sheets 14 and 15.
• the laminate 4 includes dummy electrodes, which facilitates the formation of the external electrodes 3 using a plating method.
• at least one ceramic green sheet 13 may be placed between the dummy sheet 18 and the pattern sheets 14 and 15.
• the top and bottom layers of the temporary laminate may be ceramic green sheets 13.
• the laminate precursor 21 obtained by cutting the base laminate 19 is peeled off from the support sheet 16, it is possible to reduce the possibility that a part of the dummy electrode pattern will remain on the support sheet 16 (electrode erosion). As a result, it is possible to reduce the occurrence of poor formation of the dummy electrodes due to electrode erosion, and ultimately improve the reliability of the multilayer ceramic capacitor 1B.
• the temporary laminate is pressed in the lamination direction to obtain the mother laminate 19 as shown in FIG. 14.
• the temporary laminate can be pressed using, for example, a hydrostatic press.
• FIG. 14 shows external electrode ink 22, which serves as a base for the external electrode 3, printed on the upper surface of the base laminate 19 obtained by pressing the temporary laminate shown in FIG. 13 in the stacking direction.
• the base may be formed on the upper and lower surfaces of the base laminate 19, in which case it is possible to further improve the adhesion between the external electrode 3 and the base component 2.
• the external electrode ink 22 may be a paste made by kneading powder of a metal material such as Cu, Ni, Ag, Pd, Ag-Pd alloy, or Au with a sintering aid such as glass powder, a binder resin, and a plasticizer together with a solvent.
• the external electrode ink 22 is fired together with the element component precursor 25 (see FIG. 18A) to form the base for the external electrode 3. It is also possible to use a resin paste as the external electrode ink 22.
• the external electrode ink 22 does not have to be printed on the base laminate 19.
• the external electrode ink 22 may be printed on the ceramic green sheet 13, and when the temporary laminate is produced, the ceramic green sheet 13 on which the external electrode ink 22 is printed may be used as the uppermost layer of the temporary laminate.
• the mother laminate 19 is cut along the planned cutting lines 20 to produce a plurality of laminate precursors 21.
• the mother laminate 19 may be cut while it is placed on the support sheet 16.
• the mother laminate 19 may be cut using, for example, a press cutter, a dicing saw device, or the like.
• each laminate precursor 21 is rotated 90° on the support sheet 16 so that the side on which the internal electrode pattern is exposed becomes the open surface (upper surface).
• multiple laminate precursors 21 may be aligned in a matrix on the support sheet 16. In this case, it becomes possible to efficiently attach the ceramic green sheet that will become the protective layer 5 to the side of the laminate precursor 21.
• a ceramic green sheet that will become protective layer 5 (also called a ceramic green sheet for protective layer) is attached to the side of the laminate precursor to produce a base component precursor.
• the ceramic green sheet that will become protective layer 5 may be referred to as a ceramic green sheet for protective layer 23.
• Figures 17A, 17B, and 17C show the process of attaching a ceramic green sheet for protective layer 23 to the side of laminate precursor 21.
• a strip-shaped ceramic green sheet 23 for protective layer is prepared, and the ceramic green sheet 23 for protective layer is placed on the upper surface of a base (also called a second base) 24.
• a plurality of laminate precursors 21 shown in FIG. 16 are placed so that the open surface of each laminate precursor 21 faces the upper surface of the second base 24.
• the plurality of laminate precursors 21 are held by a support sheet 16 fixed to a first base 17.
• the thickness of the ceramic green sheet 23 for protective layer may be 30 ⁇ m or less, or may be 25 ⁇ m to 10 ⁇ m.
• the width of the ceramic green sheet 23 for protective layer width in the left-right direction in FIG.
• 17A may be a dimension that completely covers the area on the side of the laminate precursor 21 where the internal electrode pattern that becomes the first internal electrode 6a and the internal electrode pattern that becomes the second internal electrode 6b overlap in the stacking direction and are exposed, and does not cover the area that becomes the edge portions 10a to 10d.
• the first seat 17 is moved toward the second seat 24, and the open surface of each laminate precursor 21 is pressed against the protective layer ceramic green sheet 23, thereby bonding the protective layer ceramic green sheet 23 to the open surface of each laminate precursor 21.
• the pressing force may be set appropriately.
• the protective layer ceramic green sheet 23 may also be bonded to the open surface of each laminate precursor 21 while at least one of the open surface of each laminate precursor 21 and the protective layer ceramic green sheet 23 is heated. In this case, the protective layer ceramic green sheet 23 can be bonded well to the open surface of each laminate precursor 21.
• the first pedestal 17 is moved away from the second pedestal 24 to produce a laminate precursor 21 having a protective layer ceramic green sheet 23 bonded to its open surface.
• a laminate precursor 21 having a protective layer ceramic green sheet 23 bonded to four side surfaces, i.e., a base part precursor 25, can be produced (see FIG. 18A).
• Figs. 17A, 17B, and 17C show an example in which protective layer ceramic green sheets 23 are pressed onto the side of laminate precursor 21 to produce bare part precursor 25, this is not limiting. Bare part precursor 25 may also be produced by applying protective layer ceramic slurry to the side of laminate precursor 21 and drying it.
• the firing temperature can be set appropriately depending on the metal material contained in the conductive paste that becomes the internal electrode 6, the ceramic material contained in the ceramic green sheet that becomes the dielectric layer 7, etc.
• the firing temperature may be, for example, about 1100 to 1250°C.
• a degreasing process may be performed on the element component precursor 25 before firing.
• the degreasing process may be performed in an air atmosphere, an inert gas atmosphere, or a reducing atmosphere.
• the degreasing process may be performed under atmospheric pressure or under reduced pressure.
• the element component 2 after firing may be subjected to a re-oxidation process in an oxidizing atmosphere.
• FIG. 18B shows the element component 2 after polishing.
• FIG. 18C shows an element part on which the first layer 31 of the external electrode 3 is formed.
• the first layer 31 of the external electrode 3 can be formed by repeating the process of immersing the edge portions 10a-10d on which the first layer 31 is to be formed in external electrode paste, then lifting them out of the external electrode paste, and baking the external electrode paste attached to the edge portions 10a-10d.
• the external electrode paste may be applied to the edge portions 10a-10d on which the first layer is to be formed by a printing method such as screen printing or gravure printing.
• a metal film of Ni or Cu may also be formed by a sputtering method or the like.
• the second layer is formed by a plating method such as electroless plating or electrolytic plating so as to cover the first layer 31, thereby manufacturing the multilayer ceramic capacitor 1B of FIG. 6B.
• This disclosure makes it possible to provide a small, high-capacity multilayer ceramic capacitor.
• This disclosure can be implemented in the following configurations (1) to (9).
• a multilayer ceramic capacitor comprising: a plurality of internal electrodes and external electrodes
• the external electrodes are a first external electrode located at least from the first side surface to the first surface and/or the second surface and connected to an internal electrode of a first polarity among the plurality of internal electrodes at the first edge portion;
• a multilayer ceramic capacitor as described in the above configuration (1) including a second external electrode located at least from the third side surface to the first surface and/or the second surface, and connected to an internal electrode of a second polarity among the plurality of internal electrodes at the second edge portion.
• the external electrodes are a first external electrode located at least from the first side surface to the first surface and/or the second surface, and connected to an internal electrode of a first polarity among the plurality of internal electrodes at the first edge portion and the fourth edge portion;
• a multilayer ceramic capacitor as described in the above configuration (1) including a second external electrode located at least from the third side surface to the first surface and/or the second surface, and connected to an internal electrode of a second polarity among the plurality of internal electrodes at the second edge portion and the third edge portion.
• the external electrodes are a first external electrode located at least from the first side surface to the first surface and/or the second surface and connected to an internal electrode of a first polarity among the plurality of internal electrodes at the first edge portion; a second external electrode located at least from the second side surface to the first surface and/or the second surface and connected to an internal electrode of a second polarity among the plurality of internal electrodes at the second edge portion; a third external electrode located at least from the third side surface to the first surface and/or the second surface, and connected to an internal electrode of a first polarity among the plurality of internal electrodes at the third edge portion;
• each of the multiple internal electrodes has a notch portion that, when viewed in the stacking direction, is in the shape of a right triangle whose apex is located on the edge of the predetermined edge portion, or in the shape of a right triangle whose hypotenuse bulges in an arc shape.
• the laminate includes a first cover layer including the first surface and a second cover layer including the second surface, the first cover layer includes a plurality of first dummy electrodes to which the external electrodes are connected;
• the multilayer ceramic capacitor according to any one of the above configurations (1) to (8), wherein the second cover layer includes a plurality of second dummy electrodes to which the external electrodes are connected.

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