WO2025010905A1 - 栅极驱动电路、显示面板 - Google Patents

栅极驱动电路、显示面板 Download PDF

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Publication number
WO2025010905A1
WO2025010905A1 PCT/CN2023/132974 CN2023132974W WO2025010905A1 WO 2025010905 A1 WO2025010905 A1 WO 2025010905A1 CN 2023132974 W CN2023132974 W CN 2023132974W WO 2025010905 A1 WO2025010905 A1 WO 2025010905A1
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Prior art keywords
transistor
electrically connected
node
terminal
output
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Ceased
Application number
PCT/CN2023/132974
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English (en)
French (fr)
Inventor
陶宝生
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Publication of WO2025010905A1 publication Critical patent/WO2025010905A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits

Definitions

  • the present application relates to the field of display technology, and in particular to a gate drive circuit and a display panel.
  • capacitor C3 is often used to maintain the gate potential of the pull-down output transistor To2.
  • the pull-down output transistor To2 is a P-type transistor, since the gate-source voltage difference must be less than the threshold voltage when the P-type transistor is turned on, there will be a problem of voltage loss when the existing gate drive circuit outputs the required gate control signal Scan.
  • the output potential of the source of the pull-down output transistor To2 (i.e., the signal output terminal OUT) is L+2
  • the embodiments of the present application provide a gate driving circuit and a display panel, which can maintain the potential of the second node and improve the problem of voltage loss in the gate control signal output by the gate driving circuit.
  • An embodiment of the present application provides a gate driving circuit, including a first node pull-down module, a second node pull-down module, a second node maintaining module and an output module.
  • the first node pull-down module is electrically connected to the first clock signal line, the second clock signal line, the first voltage terminal and the first node, and the first node pull-down module is configured to lower the potential of the first node according to the first clock signal transmitted by the first clock signal line, the second clock signal transmitted by the second clock signal line and the first voltage transmitted by the first voltage terminal.
  • the second node pull-down module is electrically connected to the first clock signal line, the pull-down control line and the second node, and the second node pull-down module is configured to pull down the potential of the second node according to the first clock signal and the pull-down control signal transmitted by the pull-down control line, so that the variable at the signal output end of the gate drive circuit is coupled to the second node.
  • the second node maintaining module is electrically connected to the first clock signal line, the second clock signal line, the pull-down control line and the second node, and the second node maintaining module is configured to maintain the potential of the second node according to the first clock signal, the second clock signal and the pull-down control signal.
  • the output module is electrically connected to the first node and the second node, and is configured to control the signal output terminal to output a gate control signal according to the potentials of the first node and the second node.
  • the present application also provides a display panel, comprising a plurality of any of the above-mentioned gate driving circuits; and a plurality of sub-pixels, wherein the plurality of sub-pixels are electrically connected to the plurality of gate driving circuits.
  • FIG1 is a schematic diagram of the structure of an existing gate drive circuit
  • FIG2 is a timing diagram corresponding to FIG1;
  • FIG3 is a schematic diagram of the structure of a gate driving circuit provided in an embodiment of the present application.
  • FIG4 is a timing diagram corresponding to the gate driving circuit shown in FIG3 provided in an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a display panel provided in an embodiment of the present application.
  • the output module includes a pull-up output transistor, a pull-down output transistor and a first capacitor.
  • the control end of the pull-up output transistor is electrically connected to the first node, the input end of the pull-up output transistor is electrically connected to the second voltage end, and the output end of the pull-up output transistor is electrically connected to the signal output end;
  • the control end of the pull-down output transistor is electrically connected to the second node, the input end of the pull-down output transistor is electrically connected to the first voltage end, and the output end of the pull-down output transistor is electrically connected to the signal output end;
  • the first capacitor is connected in series between the first node and the second voltage end.
  • the second node pull-down module includes a first transistor and a second transistor.
  • the control end of the first transistor is electrically connected to the first clock signal line, and the input end of the first transistor is electrically connected to the pull-down control line;
  • the control end of the second transistor is electrically connected to the first voltage end, the input end of the second transistor is electrically connected to the output end of the first transistor, and the output end of the second transistor is electrically connected to the second node.
  • the control end of the third transistor is electrically connected to the first clock signal line, and the input end of the third transistor is electrically connected to the pull-down control line;
  • the control end of the fourth transistor is electrically connected to the first voltage end, and the input end of the fourth transistor is electrically connected to the output end of the third transistor;
  • the control end of the fifth transistor is electrically connected to the output end of the fourth transistor, the input end of the fifth transistor is electrically connected to the control end of the fifth transistor, and the output end of the fifth transistor is electrically connected to the second node;
  • the control end of the sixth transistor is electrically connected to the control end of the fifth transistor, and the input end of the sixth transistor is electrically connected to the second clock signal line;
  • the control end and input end of the seventh transistor are electrically connected to the output end of the sixth transistor, and the output end of the seventh transistor is electrically connected to the control end of the fifth transistor.
  • the first node pull-down module includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a second capacitor.
  • the control terminal of the eighth transistor is electrically connected to the first clock signal line, and the input terminal of the eighth transistor is electrically connected to the first voltage terminal;
  • the control terminal of the ninth transistor is electrically connected to the first voltage terminal, and the input terminal of the ninth transistor is electrically connected to the output terminal of the eighth transistor;
  • the control terminal of the tenth transistor is electrically connected to the output terminal of the ninth transistor, and the input terminal of the tenth transistor is electrically connected to the second clock signal line;
  • the control terminal of the eleventh transistor is electrically connected to the second clock signal line, and the input terminal of the eleventh transistor is electrically connected to the output terminal of the tenth transistor, and the output terminal of the eleventh transistor is electrically connected to the first node;
  • the second capacitor is connected in series between the control terminal of the tenth transistor and the output terminal of the tenth transistor.
  • the second node maintaining module also includes a twelfth transistor, the control end of the twelfth transistor is electrically connected to the output end of the eighth transistor, the input end of the twelfth transistor is electrically connected to the second voltage end, and the output end of the twelfth transistor is electrically connected to the control end of the seventh transistor.
  • the gate drive circuit also includes a reset module, the reset module includes a reset transistor, the control end of the reset transistor is electrically connected to the reset control line, the input end of the reset transistor is electrically connected to the second voltage end, and the output end of the reset transistor is electrically connected to the output end of the first transistor.
  • the present application provides a gate driving circuit and a display panel, wherein the gate driving circuit includes a first node pull-down module, a second node pull-down module, a second node maintenance module and an output module.
  • the first node pull-down module pulls down the potential of the first node according to the first clock signal, the second clock signal and the first voltage;
  • the second node pull-down module pulls down the potential of the second node according to the first clock signal and the pull-down control signal, so that the variable at the signal output end of the gate driving circuit is coupled to the second node;
  • the second node maintenance module maintains the potential of the second node according to the first clock signal, the second clock signal and the pull-down control signal;
  • the output module outputs a gate control signal according to the potential control signal output end of the first node and the second node.
  • the gate driving circuit includes a second node pull-down module
  • the variable at the signal output end can be coupled to the second node, so that the potential of the second node is further pulled down, thereby reducing the voltage loss of the gate control signal output by the output module.
  • the second node maintenance module By setting the second node maintenance module, the potential of the second node can be maintained at a low potential after being pulled down.
  • the display panel includes a plurality of sub-pixels and a plurality of gate driving circuits.
  • FIG. 3 it is a structural diagram of the gate drive circuit provided in an embodiment of the present application; the embodiment of the present application provides a gate drive circuit, including a first node pull-down module 100, a second node pull-down module 200, a second node maintaining module 300 and an output module 400.
  • the first node pull-down module 100 is electrically connected to the first clock signal line CKL1, the second clock signal line CKL2, the first voltage terminal VGL and the first node N1, and the first node pull-down module 100 is configured to pull down the potential of the first node N1 according to the first clock signal CK transmitted by the first clock signal line CKL1, the second clock signal XCK transmitted by the second clock signal line CKL2 and the first voltage transmitted by the first voltage terminal VGL.
  • the second node pull-down module 200 is electrically connected to the first clock signal line CKL1, the pull-down control line InL and the second node N2.
  • the second node pull-down module 200 is configured to pull down the potential of the second node N2 according to the first clock signal CK and the pull-down control signal In transmitted by the pull-down control line InL, so that the variable at the signal output terminal Out of the gate drive circuit is coupled to the second node N2.
  • the second node maintaining module 300 is electrically connected to the first clock signal line CKL1, the second clock signal line CKL2, the pull-down control line InL and the second node N2, and the second node maintaining module 300 is configured to maintain the potential of the second node N2 according to the first clock signal CK, the second clock signal XCK and the pull-down control signal In.
  • the output module 400 is electrically connected to the first node N1 and the second node N2 , and is configured to control the signal output terminal Out to output a gate control signal Scan according to the potentials of the first node N1 and the second node N2 .
  • Vth is the threshold voltage of the pull-down output transistor To2 included in the output module 400.
  • the output module 400 includes a pull-up output transistor To1 , a pull-down output transistor To2 , and a first capacitor C1 .
  • the control end of the pull-up output transistor To1 is electrically connected to the first node N1, the input end of the pull-up output transistor To1 is electrically connected to the second voltage end VGH, and the output end of the pull-up output transistor To1 is electrically connected to the signal output end Out; the pull-up output transistor To1 transmits the second voltage output by the second voltage end VGH to the signal output end Out according to the potential of the first node N1.
  • the control end of the pull-down output transistor To2 is electrically connected to the second node N2, the input end of the pull-down output transistor To2 is electrically connected to the first voltage end VGL, and the output end of the pull-down output transistor To2 is electrically connected to the signal output end Out; the pull-down output transistor To2 transmits the first voltage output by the first voltage end VGL to the signal output end Out according to the potential of the second node N2.
  • the first capacitor C1 is connected in series between the first node N1 and the second voltage terminal VGH, and the first capacitor C1 is used to maintain the potential of the first node N1.
  • the first voltage is less than the second voltage, so that when the pull-down output transistor To2 is turned on, the gate control signal Scan output by the gate driving circuit is pulled down from the first voltage to the second voltage.
  • the second node pull-down module 200 includes a first transistor T1 and a second transistor T2 .
  • the control end of the first transistor T1 is electrically connected to the first clock signal line CKL1, the input end of the first transistor T1 is electrically connected to the pull-down control line InL, the output end of the first transistor T1 is electrically connected to the input end of the second transistor T2.
  • the first transistor T1 transmits the pull-down control signal In to the input end of the second transistor T2 according to the first clock signal CK.
  • the control end of the second transistor T2 is electrically connected to the first voltage end VGL, the output end of the second transistor T2 is electrically connected to the second node N2, and the second transistor T2 is used to make the potential of the second node N2 the sum of the first voltage and the threshold voltage of the second transistor T2 when the pull-down control signal In is transmitted to the input end of the second transistor T2.
  • the second node maintaining module 300 includes a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 and a seventh transistor T7 .
  • the control end of the third transistor T3 is electrically connected to the first clock signal line CKL1, the input end of the third transistor T3 is electrically connected to the pull-down control line InL, and the output end of the third transistor T3 is electrically connected to the input end of the fourth transistor T4; the third transistor T3 transmits the pull-down control signal In to the input end of the fourth transistor T4 according to the first clock signal CK.
  • the control end of the fourth transistor T4 is electrically connected to the first voltage end VGL, and the output end of the fourth transistor T4 is electrically connected to the control end of the fifth transistor T5; the fourth transistor T4 is used to transmit the pull-down control signal In to the control end of the fifth transistor T5 to control the conduction and cutoff of the fifth transistor T5.
  • the input end of the fifth transistor T5 is electrically connected to the control end of the fifth transistor T5, and the output end of the fifth transistor T5 is electrically connected to the second node N2; the fifth transistor T5 is used to make the potential of the second node N2 the sum of the first voltage and the threshold voltage of the fifth transistor T5 when the pull-down control signal In is transmitted to the input end of the fifth transistor T5.
  • the control end of the sixth transistor T6 is electrically connected to the control end of the fifth transistor T5, the input end of the sixth transistor T6 is electrically connected to the second clock signal line CKL2, the output end of the sixth transistor T6 is electrically connected to the control end and the input end of the seventh transistor T7, and the output end of the seventh transistor T7 is electrically connected to the control end of the fifth transistor T5; the sixth transistor T6 transmits the second clock signal XCK to the control ends of the seventh transistor T7 and the fifth transistor T5 according to the pull-down control signal In.
  • the first node pull-down module 100 includes an eighth transistor T8 , a ninth transistor T9 , a tenth transistor T10 , an eleventh transistor T11 and a second capacitor C2 .
  • the control end of the eighth transistor T8 is electrically connected to the first clock signal line CKL1 , the input end of the eighth transistor T8 is electrically connected to the first voltage end VGL, and the output end of the eighth transistor T8 is electrically connected to the input end of the ninth transistor T9 .
  • the control end of the ninth transistor T9 is electrically connected to the first voltage end VGL, and the output end of the ninth transistor T9 is electrically connected to the control end of the tenth transistor T10.
  • An input terminal of the tenth transistor T10 is electrically connected to the second clock signal line CKL2 , and an output terminal of the tenth transistor T10 is electrically connected to an input terminal of the eleventh transistor T11 .
  • a control end of the eleventh transistor T11 is electrically connected to the second clock signal line CKL2 , and an output end of the eleventh transistor T11 is electrically connected to the first node N1 .
  • the second capacitor C2 is connected in series between the control terminal of the tenth transistor T10 and the output terminal of the tenth transistor T10.
  • the fourteenth transistor T14 is a dual-gate transistor to reduce leakage current.
  • the gate driving circuit also includes a reset module 600
  • the reset module 600 includes a reset transistor Tin
  • the control end of the reset transistor Tin is electrically connected to the reset control line RL
  • the input end of the reset transistor Tin is electrically connected to the second voltage end VGH
  • the output end of the reset transistor Tin is electrically connected to the output end of the first transistor T1; the reset transistor Tin resets the potential of the output end of the first transistor T1 according to the reset control signal Rst transmitted by the reset control line RL.
  • the eleventh transistor T11 is turned on according to the second clock signal XCK, the control end of the tenth transistor T10 is turned on because it maintains the low level in the previous stage, and the input end of the tenth transistor T10 transmits the second clock signal XCK to the first node N1, so that the pull-up output transistor To1 is turned on, and the second voltage is output to the signal output end Out through the pull-up output transistor To1.
  • the second clock signal XCK is coupled to the control end of the twelfth transistor T12 through the second capacitor C2, so that the twelfth transistor T12 is turned on, and the second voltage is transmitted to the control end of the seventh transistor T7 through the twelfth transistor T12, so that the seventh transistor T7 is turned off.
  • the reset transistor Tin is turned off according to the reset control signal Rst, the first transistor T1, the third transistor T3 and the eighth transistor T8 are turned off according to the first clock signal CK, and the control ends of the fifth transistor T5, the sixth transistor T6, the thirteenth transistor T13, the fourteenth transistor T14 and the pull-down output transistor To2 are turned off because they maintain the high level in the previous stage.
  • the second stage t2 the pull-down control signal In is at a low level, and the first clock signal CK, the second clock signal XCK and the reset control signal Rst are at a high level.
  • the eleventh transistor T11 is turned off according to the second clock signal XCK, the first capacitor C1 maintains the pull-up output transistor To1 turned on, and the second voltage is output to the signal output terminal Out through the pull-up output transistor To1.
  • the reset transistor Tin is turned off according to the reset control signal Rst, the first transistor T1, the third transistor T3 and the eighth transistor T8 are turned off according to the first clock signal CK, and the fifth transistor T5, the sixth transistor T6, the double-gate seventh transistor T7, the thirteenth transistor T13, the fourteenth transistor T14 and the pull-down output transistor To2 remain turned off.
  • the third stage t3 the first clock signal CK and the pull-down control signal In are at a low level, and the second clock signal XCK and the reset control signal Rst are at a high level.
  • the first transistor T1, the third transistor T3 and the eighth transistor T8 are turned on, and the pull-down control signal In is transmitted to the control terminals of the pull-down output transistor To2, the thirteenth transistor T13 and the fourteenth transistor T14 through the first transistor T1, so that the potential of the control terminal of the pull-down output transistor To2 becomes the sum of the first voltage and the threshold voltage of the third transistor T3 (i.e., L+
  • the third transistor T3 is turned on so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the potential of the control terminal of the fifth transistor T5 becomes the sum of the first voltage and the threshold voltage of the fourth transistor T4.
  • the potential of the signal output terminal Out needs to be the sum of the first voltage and twice the threshold voltage of the third transistor T3 (i.e., L+2
  • the voltage change of the signal output terminal Out is coupled to the control terminal of the pull-down output transistor To2 through the parasitic capacitance between the gate and source of the pull-down output transistor To2, so that the potential of the control terminal of the pull-down output transistor To2 is pulled down from L+
  • the fourteenth transistor T14 and the eighth transistor T8 are turned on, so that the tenth transistor T10 and the twelfth transistor T12 are turned on.
  • the twelfth transistor T12 and the sixth transistor T6 are turned on, so that the seventh transistor T7 is turned off.
  • the thirteenth transistor T13 is turned on so that the second voltage is transmitted to the control terminal of the pull-up output transistor To1 to control the pull-up output transistor To1 to be turned off.
  • H represents the voltage value corresponding to the first voltage
  • L represents the voltage value corresponding to the second voltage
  • Vth_T3 represents the threshold voltage of the third transistor T3.
  • Fourth stage t4 the pull-down control signal In is at a low level, and the first clock signal CK, the second clock signal XCK and the reset control signal Rst are at a high level.
  • the first transistor T1, the third transistor T3 and the eighth transistor T8 are turned off according to the first clock signal CK, and the eleventh transistor T11 is turned off according to the second clock signal XCK.
  • the first capacitor C1 maintains the pull-up output transistor To1 to be turned off, the thirteenth transistor T13 and the pull-down output transistor To2 remain turned on, the first voltage is transmitted to the signal output terminal Out, the fifth transistor T5, the sixth transistor T6, the tenth transistor T10, and the fourteenth transistor T14 remain turned on, the first clock signal CK charges the second capacitor C2 to increase the potential of the control terminal of the tenth transistor T10 and the twelfth transistor T12, and the second clock signal XCK is transmitted to the control terminal of the seventh transistor T7 through the sixth transistor T6 to turn off the seventh transistor T7.
  • the reset transistor Tin is turned off according to the reset control signal Rst.
  • the fifth transistor T5 and the sixth transistor T6 remain turned on (i.e., the potential of the control end of the fifth transistor T5 and the sixth transistor T6 is the sum of the first voltage and the threshold voltage of the fourth transistor T4, L+
  • the control terminal and the input terminal of the fifth transistor are short-circuited, the control terminal and the input terminal of the fifth transistor T5 are at the same potential.
  • the potential of the control terminal of the pull-down output transistor To2 can be coupled through the gate-source parasitic capacitance and the gate-drain parasitic capacitance of the fifth transistor T5 itself, so that the potential of the control terminal of the pull-down output transistor To2 is further reduced, thereby ensuring that the signal output terminal Out can output a low level stably for a long time.
  • Figure 5 is a schematic diagram of a display panel provided by an embodiment of the present application.
  • the present application also provides a display panel, comprising a plurality of any of the above-mentioned gate driving circuits; and a plurality of sub-pixels, wherein the plurality of sub-pixels are electrically connected to the plurality of gate driving circuits.
  • a plurality of the gate driving circuits are cascaded, and a plurality of the sub-pixels are electrically connected to the plurality of the gate driving circuits via a plurality of gate control lines.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种栅极驱动电路及显示面板，通过第一节点下拉模块（100）拉低第一节点（N1）的电位，通过第二节点下拉模块（200）拉低第二节点（N2）的电位，以使栅极驱动电路的信号输出端（Out）具有的变量耦合至第二节点（N2）；通过第二节点维持模块（300）维持第二节点（N2）的电位，通过输出模块（400）输出栅极控制信号（Scan）。

Description

栅极驱动电路、显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种栅极驱动电路、显示面板。
 背景技术
现有的栅极驱动电路中（如图1所示），常利用电容C3维持下拉输出晶体管To2的栅极电位。但在下拉输出晶体管To2为P型晶体管时，因P型晶体管导通需满足栅源电压差小于阈值电压，因而，现有的栅极驱动电路输出所需的栅极控制信号Scan时，会存在电压损失的问题。即当下拉输出晶体管To2的栅极电位为L+|Vth|，漏极电位为低电位L时，下拉输出晶体管To2的源极（即信号输出端OUT）输出电位为L+2|Vth|才满足Vgs＜Vth的导通条件，使下拉输出晶体管To2导通，从而使得输出存在2|Vth|的电压损失而无法直接输出VGL所对应电压（即如图2所示，输出波形对应具有L+2|Vth|的拖尾，输出波形需在时钟信号XCK为低电位时才能输出VGL对应的电压）。
 发明概述
本申请实施例提供一种栅极驱动电路、显示面板，可以实现维持第二节点的电位，改善栅极驱动电路输出的栅极控制信号存在电压损失的问题。
本申请实施例提供一种栅极驱动电路，包括第一节点下拉模块、第二节点下拉模块、第二节点维持模块以及输出模块。
所述第一节点下拉模块与第一时钟信号线、第二时钟信号线、第一电压端及第一节点电性连接，所述第一节点下拉模块被配置为根据所述第一时钟信号线传输的第一时钟信号、所述第二时钟信号线传输的第二时钟信号及所述第一电压端传输的第一电压拉低所述第一节点的电位。
所述第二节点下拉模块与所述第一时钟信号线、下拉控制线及第二节点电性连接，所述第二节点下拉模块被配置为根据所述第一时钟信号及所述下拉控制线传输的下拉控制信号拉低所述第二节点的电位，以使所述栅极驱动电路的信号输出端具有的变量耦合至所述第二节点。
所述第二节点维持模块与所述第一时钟信号线、所述第二时钟信号线、所述下拉控制线及所述第二节点电性连接，所述第二节点维持模块被配置为根据所述第一时钟信号、所述第二时钟信号及所述下拉控制信号维持所述第二节点的电位。
所述输出模块与所述第一节点和第二节点电性连接，所述输出模块被配置为根据所述第一节点和所述第二节点的电位控制所述信号输出端输出栅极控制信号。
本申请还提供一种显示面板，包括多个任一上述的栅极驱动电路；以及多个子像素，多个所述子像素与多个所述栅极驱动电路电性连接。
 附图说明
图1是现有的栅极驱动电路的结构示意图；
图2是与图1对应的时序图；
图3是本申请实施例提供的栅极驱动电路的结构示意图；
图4是本申请实施例提供的与图3所示的栅极驱动电路对应的时序图；
图5是本申请实施例提供的显示面板的示意图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
可选地，在本申请的一些实施例中，所述输出模块包括上拉输出晶体管、下拉输出晶体管以及第一电容。所述上拉输出晶体管的控制端与所述第一节点电性连接，所述上拉输出晶体管的输入端与第二电压端电性连接，所述上拉输出晶体管的输出端与所述信号输出端电性连接；所述下拉输出晶体管的控制端与所述第二节点电性连接，所述下拉输出晶体管的输入端与所述第一电压端电性连接，所述下拉输出晶体管的输出端与所述信号输出端电性连接；所述第一电容串联于所述第一节点和所述第二电压端之间。
可选地，在本申请的一些实施例中，所述第二节点下拉模块包括第一晶体管以及第二晶体管。所述第一晶体管的控制端与所述第一时钟信号线电性连接，所述第一晶体管的输入端与所述下拉控制线电性连接；所述第二晶体管的控制端与所述第一电压端电性连接，所述第二晶体管的输入端与所述第一晶体管的输出端电性连接，所述第二晶体管的输出端与所述第二节点电性连接。
可选地，在本申请的一些实施例中，所述第二节点维持模块包括第三晶体管、第四晶体管、第五晶体管、第六晶体管以及第七晶体管。
所述第三晶体管的控制端与所述第一时钟信号线电性连接，所述第三晶体管的输入端与所述下拉控制线电性连接；所述第四晶体管的控制端与所述第一电压端电性连接，所述第四晶体管的输入端与所述第三晶体管的输出端电性连接；所述第五晶体管的控制端与所述第四晶体管的输出端电性连接，所述第五晶体管的输入端与所述第五晶体管的控制端电性连接，所述第五晶体管的输出端与所述第二节点电性连接；所述第六晶体管的控制端与所述第五晶体管的控制端电性连接，所述第六晶体管的输入端与所述第二时钟信号线电性连接；所述第七晶体管的控制端及输入端与所述第六晶体管的输出端电性连接，所述第七晶体管的输出端与所述第五晶体管的控制端电性连接。
可选地，在本申请的一些实施例中，所述第一节点下拉模块包括第八晶体管、第九晶体管、第十晶体管、第十一晶体管以及第二电容。所述第八晶体管的控制端与所述第一时钟信号线电性连接，所述第八晶体管的输入端与所述第一电压端电性连接；所述第九晶体管的控制端与所述第一电压端电性连接，所述第九晶体管的输入端与所述第八晶体管的输出端电性连接；所述第十晶体管的控制端与所述第九晶体管的输出端电性连接，所述第十晶体管的输入端与所述第二时钟信号线电性连接；所述第十一晶体管的控制端与所述第二时钟信号线电性连接，所述第十一晶体管的输入端与所述第十晶体管的输出端电性连接，所述第十一晶体管的输出端与所述第一节点电性连接；所述第二电容串联于所述第十晶体管的控制端与所述第十晶体管的输出端之间。
可选地，在本申请的一些实施例中，所述第二节点维持模块还包括第十二晶体管，所述第十二晶体管的控制端与所述第八晶体管的输出端电性连接，所述第十二晶体管的输入端与第二电压端电性连接，所述第十二晶体管的输出端与所述第七晶体管的控制端电性连接。
可选地，在本申请的一些实施例中，所述栅极驱动电路还包括第一节点上拉模块，所述第一节点上拉模块包括第十三晶体管，所述第十三晶体管的控制端与所述第一晶体管的输出端电性连接，所述第十三晶体管的输入端与第二电压端电性连接，所述第十三晶体管的输出端与所述第一节点电性连接。
可选地，在本申请的一些实施例中，所述第一节点下拉模块还包括第十四晶体管，所述第十四晶体管的控制端与所述第一晶体管的输出端电性连接，所述第十四晶体管的输入端与所述第一时钟信号线电性连接，所述第十四晶体管的输出端与所述第八晶体管的输出端电性连接。
可选地，在本申请的一些实施例中，所述栅极驱动电路还包括重置模块，所述重置模块包括重置晶体管，所述重置晶体管的控制端与重置控制线电性连接，所述重置晶体管的输入端与第二电压端电性连接，所述重置晶体管的输出端与所述第一晶体管的输出端电性连接。
本申请提供一种栅极驱动电路及显示面板，栅极驱动电路包括第一节点下拉模块、第二节点下拉模块、第二节点维持模块以及输出模块。第一节点下拉模块根据第一时钟信号、第二时钟信号及第一电压拉低第一节点的电位；第二节点下拉模块根据第一时钟信号及下拉控制信号拉低第二节点的电位，以使栅极驱动电路的信号输出端具有的变量耦合至第二节点；第二节点维持模块根据第一时钟信号、第二时钟信号及下拉控制信号维持第二节点的电位；输出模块根据第一节点和第二节点的电位控制信号输出端输出栅极控制信号。通过使栅极驱动电路包括第二节点下拉模块使得第二节点电位被下拉时，信号输出端所具有的变量可被耦合至第二节点，以使第二节点电位进一步下拉，从而使输出模块输出的栅极控制信号具有的电压损失得以降低。通过设置第二节点维持模块，可以使第二节点的电位在被下拉后维持在低电位。显示面板包括多个子像素和多个栅极驱动电路。
具体地，如图3是本申请实施例提供的栅极驱动电路的结构示意图；本申请实施例提供一种栅极驱动电路，包括第一节点下拉模块100、第二节点下拉模块200、第二节点维持模块300以及输出模块400。
所述第一节点下拉模块100与第一时钟信号线CKL1、第二时钟信号线CKL2、第一电压端VGL及第一节点N1电性连接，所述第一节点下拉模块100被配置为根据所述第一时钟信号线CKL1传输的第一时钟信号CK、所述第二时钟信号线CKL2传输的第二时钟信号XCK及所述第一电压端VGL传输的第一电压拉低所述第一节点N1的电位。
所述第二节点下拉模块200与所述第一时钟信号线CKL1、下拉控制线InL及第二节点N2电性连接，所述第二节点下拉模块200被配置为根据所述第一时钟信号CK及所述下拉控制线InL传输的下拉控制信号In拉低所述第二节点N2的电位，以使所述栅极驱动电路的信号输出端Out具有的变量耦合至所述第二节点N2。
所述第二节点维持模块300与所述第一时钟信号线CKL1、所述第二时钟信号线CKL2、所述下拉控制线InL及所述第二节点N2电性连接，所述第二节点维持模块300被配置为根据所述第一时钟信号CK、所述第二时钟信号XCK及所述下拉控制信号In维持所述第二节点N2的电位。
所述输出模块400与所述第一节点N1和第二节点N2电性连接，所述输出模块400被配置为根据所述第一节点N1和所述第二节点N2的电位控制所述信号输出端Out输出栅极控制信号Scan。
通过设置第二节点下拉模块200以在第二节点N2电位被拉低时，使信号输出端Out所具有的变量可耦合至第二节点N2，以进一步拉低第二节点N2的电位，从而使输出模块400可根据第二节点N2的电位快速的将第一电压传输至信号输出端Out，以缩短栅极控制信号Scan由高电平变化至低电平的时长，规避栅极控制信号Scan由高电平变化至低电平时所具有的2|Vth|的电压损失。其中，Vth为输出模块400所包括的下拉输出晶体管To2的阈值电压。
可选地，请继续参阅图3，所述输出模块400包括上拉输出晶体管To1、下拉输出晶体管To2以及第一电容C1。
所述上拉输出晶体管To1的控制端与所述第一节点N1电性连接，所述上拉输出晶体管To1的输入端与第二电压端VGH电性连接，所述上拉输出晶体管To1的输出端与所述信号输出端Out电性连接；所述上拉输出晶体管To1根据所述第一节点N1的电位将所述第二电压端VGH输出的第二电压传输至所述信号输出端Out。
所述下拉输出晶体管To2的控制端与所述第二节点N2电性连接，所述下拉输出晶体管To2的输入端与所述第一电压端VGL电性连接，所述下拉输出晶体管To2的输出端与所述信号输出端Out电性连接；所述下拉输出晶体管To2根据所述第二节点N2的电位将所述第一电压端VGL输出的第一电压传输至所述信号输出端Out。
所述第一电容C1串联于所述第一节点N1和所述第二电压端VGH之间，所述第一电容C1用于维持所述第一节点N1的电位。
可选地，所述第一电压小于所述第二电压，以使所述下拉输出晶体管To2导通时，所述栅极驱动电路输出的栅极控制信号Scan由所述第一电压下拉至所述第二电压。
可选地，请继续参阅图3，所述第二节点下拉模块200包括第一晶体管T1以及第二晶体管T2。
所述第一晶体管T1的控制端与所述第一时钟信号线CKL1电性连接，所述第一晶体管T1的输入端与所述下拉控制线InL电性连接，所述第一晶体管T1的输出端与所述第二晶体管T2的输入端电性连接。所述第一晶体管T1根据第一时钟信号CK将下拉控制信号In传输至所述第二晶体管T2的输入端。
所述第二晶体管T2的控制端与所述第一电压端VGL电性连接，所述第二晶体管T2的输出端与所述第二节点N2电性连接，所述第二晶体管T2用于在所述下拉控制信号In传输至所述第二晶体管T2的输入端时，使所述第二节点N2的电位为第一电压与所述第二晶体管T2的阈值电压之和。
可选地，请继续参阅图3，所述第二节点维持模块300包括第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6以及第七晶体管T7。
所述第三晶体管T3的控制端与所述第一时钟信号线CKL1电性连接，所述第三晶体管T3的输入端与所述下拉控制线InL电性连接，所述第三晶体管T3的输出端与所述第四晶体管T4的输入端电性连接；所述第三晶体管T3根据第一时钟信号CK将下拉控制信号In传输至所述第四晶体管T4的输入端。
所述第四晶体管T4的控制端与所述第一电压端VGL电性连接，所述第四晶体管T4的输出端与所述第五晶体管T5的控制端电性连接；所述第四晶体管T4用于将下拉控制信号In传输至所述第五晶体管T5的控制端，以控制所述第五晶体管T5的导通与截止。
所述第五晶体管T5的输入端与所述第五晶体管T5的控制端电性连接，所述第五晶体管T5的输出端与所述第二节点N2电性连接；所述第五晶体管T5用于在所述下拉控制信号In传输至所述第五晶体管T5的输入端时，使所述第二节点N2的电位为第一电压与所述第五晶体管T5的阈值电压之和。
所述第六晶体管T6的控制端与所述第五晶体管T5的控制端电性连接，所述第六晶体管T6的输入端与所述第二时钟信号线CKL2电性连接，所述第六晶体管T6的输出端与所述第七晶体管T7的控制端及输入端电性连接，所述第七晶体管T7的输出端与所述第五晶体管T5的控制端电性连接；所述第六晶体管T6根据下拉控制信号In将第二时钟信号XCK传输至第七晶体管T7及第五晶体管T5的控制端。
可选地，请继续参阅图3，所述第一节点下拉模块100包括第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11以及第二电容C2。
所述第八晶体管T8的控制端与所述第一时钟信号线CKL1电性连接，所述第八晶体管T8的输入端与所述第一电压端VGL电性连接，所述第八晶体管T8的输出端与所述第九晶体管T9的输入端电性连接。
所述第九晶体管T9的控制端与所述第一电压端VGL电性连接，所述第九晶体管T9的输出端与所述第十晶体管T10的控制端电性连接。
所述第十晶体管T10的输入端与所述第二时钟信号线CKL2电性连接，所述第十晶体管T10的输出端与所述第十一晶体管T11的输入端电性连接。
所述第十一晶体管T11的控制端与所述第二时钟信号线CKL2电性连接，所述第十一晶体管T11的输出端与所述第一节点N1电性连接。
所述第二电容C2串联于所述第十晶体管T10的控制端与所述第十晶体管T10的输出端之间。
可选地，请继续参阅图3，所述第二节点维持模块300还包括第十二晶体管T12，所述第十二晶体管T12的控制端与所述第八晶体管T8的输出端电性连接，所述第十二晶体管T12的输入端与第二电压端VGH电性连接，所述第十二晶体管T12的输出端与所述第七晶体管T7的控制端电性连接；所述第十二晶体管T12通过第二电压控制所述第七晶体管T7的导通或截止。
可选地，请继续参阅图3，所述栅极驱动电路还包括第一节点上拉模块500，所述第一节点上拉模块500包括第十三晶体管T13，所述第十三晶体管T13的控制端与所述第一晶体管T1的输出端电性连接，所述第十三晶体管T13的输入端与第二电压端VGH电性连接，所述第十三晶体管T13的输出端与所述第一节点N1电性连接；所述第十三晶体管T13通过第二电压上拉所述第一节点N1的电位。
可选地，请继续参阅图3，所述第一节点下拉模块100还包括第十四晶体管T14，所述第十四晶体管T14的控制端与所述第一晶体管T1的输出端电性连接，所述第十四晶体管T14的输入端与所述第一时钟信号线CKL1电性连接，所述第十四晶体管T14的输出端与所述第八晶体管T8的输出端电性连接。
可选地，所述第十四晶体管T14为双栅晶体管，以降低漏电流。
可选地，请继续参阅图3，所述栅极驱动电路还包括重置模块600，所述重置模块600包括重置晶体管Tin，所述重置晶体管Tin的控制端与重置控制线RL电性连接，所述重置晶体管Tin的输入端与第二电压端VGH电性连接，所述重置晶体管Tin的输出端与所述第一晶体管T1的输出端电性连接；所述重置晶体管Tin根据重置控制线RL传输的重置控制信号Rst对第一晶体管T1的输出端的电位进行重置。
图4是本申请实施例提供的与图3所示的栅极驱动电路对应的时序图，以所述栅极驱动电路所包括的晶体管均为P型晶体管为例，对所述栅极驱动电路的工作原理进行说明如下。
第一阶段t1：第二时钟信号XCK及下拉控制信号In为低电平，第一时钟信号CK及重置控制信号Rst为高电平。
第十一晶体管T11根据第二时钟信号XCK导通，第十晶体管T10的控制端因维持前一阶段为低电平而导通，第十晶体管T10的输入端将第二时钟信号XCK传输至第一节点N1，以使所述上拉输出晶体管To1导通，所述第二电压经所述上拉输出晶体管To1输出至所述信号输出端Out。所述第二时钟信号XCK经所述第二电容C2耦合至所述第十二晶体管T12的控制端，以使所述第十二晶体管T12导通，所述第二电压经所述第十二晶体管T12传输至所述第七晶体管T7的控制端，以使所述第七晶体管T7截止。所述重置晶体管Tin根据所述重置控制信号Rst而截止，所述第一晶体管T1、所述第三晶体管T3及所述第八晶体管T8根据所述第一时钟信号CK而截止，所述第五晶体管T5、所述第六晶体管T6、所述第十三晶体管T13、所述第十四晶体管T14及所述下拉输出晶体管To2的控制端因维持前一阶段的高电平而截止。
第二阶段t2：下拉控制信号In为低电平，第一时钟信号CK、第二时钟信号XCK及重置控制信号Rst为高电平。
第十一晶体管T11根据第二时钟信号XCK截止，第一电容C1维持所述上拉输出晶体管To1导通，所述第二电压经所述上拉输出晶体管To1输出至所述信号输出端Out。所述重置晶体管Tin根据所述重置控制信号Rst而截止，所述第一晶体管T1、所述第三晶体管T3及所述第八晶体管T8根据所述第一时钟信号CK而截止，所述第五晶体管T5、所述第六晶体管T6、双栅第七晶体管T7、所述第十三晶体管T13、所述第十四晶体管T14及所述下拉输出晶体管To2保持截止。
第三阶段t3：第一时钟信号CK及下拉控制信号In为低电平，第二时钟信号XCK及重置控制信号Rst为高电平。
所述第一晶体管T1、所述第三晶体管T3及所述第八晶体管T8导通，所述下拉控制信号In经所述第一晶体管T1传输至所述下拉输出晶体管To2、所述第十三晶体管T13及所述第十四晶体管T14的控制端，使得所述下拉输出晶体管To2的控制端的电位变为所述第一电压与所述第三晶体管T3的阈值电压之和（即L+|Vth_T3|）。所述第三晶体管T3导通使得所述第五晶体管T5、所述第六晶体管T6导通，所述第五晶体管T5的控制端的电位变为所述第一电压与所述第四晶体管T4的阈值电压之和。由于P型晶体管需满足栅源压差小于阈值电压而导通，因此，所述下拉输出晶体管To2的控制端的电位为所述第一电压与所述第三晶体管T3的阈值电压之和时，所述信号输出端Out的电位需为所述第一电压与所述第三晶体管T3的阈值电压的2倍之和（即L+2|Vth_T3|）才导通。因而所述信号输出端Out由所述第二阶段t2的第二电压变为所述第三阶段t3的L+2|Vth_T3|，使得所述信号输出端Out具有电压变化量为L+2|Vth_T3|-H。所述信号输出端Out具有的电压变化量经所述下拉输出晶体管To2的栅源之间的寄生电容耦合至所述下拉输出晶体管To2的控制端，使得所述下拉输出晶体管To2的控制端的电位被由L+|Vth_T3|下拉至更低的电位，从而使得所述下拉输出晶体管To2完全导通，所述第一电压可经所述下拉输出晶体管To2输出至所述信号输出端Out，使得栅极驱动电路所输出的栅极控制信号Scan在由第二电压转换为第一电压的输出时规避了2|Vth|的电压损失。所述第十四晶体管T14及所述第八晶体管T8导通，使得所述第十晶体管T10、所述第十二晶体管T12导通。所述第十二晶体管T12及所述第六晶体管T6导通使得所述第七晶体管T7截止。所述第十三晶体管T13导通使得所述第二电压被传输至所述上拉输出晶体管To1的控制端，以控制所述上拉输出晶体管To1截止。其中，H表示第一电压所对应的电压值，L表示第二电压所对应的电压值，Vth_T3表示第三晶体管T3的阈值电压。
第四阶段t4：下拉控制信号In为低电平，第一时钟信号CK、第二时钟信号XCK及重置控制信号Rst为高电平。
所述第一晶体管T1、所述第三晶体管T3及所述第八晶体管T8根据所述第一时钟信号CK而截止，第十一晶体管T11根据第二时钟信号XCK截止。第一电容C1维持所述上拉输出晶体管To1截止，所述第十三晶体管T13及所述下拉输出晶体管To2保持导通，所述第一电压被传输至所述信号输出端Out，所述第五晶体管T5、所述第六晶体管T6、所述第十晶体管T10、所述第十四晶体管T14保持导通，所述第一时钟信号CK对所述第二电容C2充电，以使所述第十晶体管T10和所述第十二晶体管T12的控制端的电位而升高，所述第二时钟信号XCK经所述第六晶体管T6传输至所述第七晶体管T7的控制端，以使所述第七晶体管T7截止。所述重置晶体管Tin根据所述重置控制信号Rst而截止。
第五阶段t5，所述第二时钟信号XCK及下拉控制信号In为低电平，第一时钟信号CK及重置控制信号Rst为高电平。
所述第五晶体管T5、所述第六晶体管T6保持导通（即所述第五晶体管T5、所述第六晶体管T6的控制端的电位为第一电压与所述第四晶体管T4的阈值电压之和L+|Vth_T4|），因而第二时钟信号XCK经所述第六晶体管T6使得所述第七晶体管T7的控制端的电位变为L+2|Vth_T4|，因此所述第七晶体管T7的控制端由所述第四阶段t4的高电平H1变为第五阶段t5的L+|Vth_T4|产生的电压变化量为L+2|Vth_T4|-H1。所述第七晶体管T7的控制端所具有的电压变化量经所述第七晶体管T7自身的栅源寄生电容和栅漏寄生电容耦合所述第五晶体管T5和所述第六晶体管T6的控制端的电位，使得所述第五晶体管T5及所述第六晶体管T6的控制端的电位由原来的L+|Vth_T4变成更低的电位，继而使得所述第七晶体管T7的控制端的电位由L+2|Vth_T4|进一步降低，之后再次通过所述第七晶体管T7自身的栅源寄生电容和栅漏寄生电容耦合所述第五晶体管T5和所述第六晶体管T6的控制端的电位，使得所述第五晶体管T5及所述第六晶体管T6的控制端的电位进一步降低。由于所述第五晶体的控制端和输入端短接，因此所述第五晶体管T5的控制端和输入端等电位，通过所述第五晶体管T5自身的栅源寄生电容和栅漏寄生电容可耦合所述下拉输出晶体管To2的控制端的电位，以使所述下拉输出晶体管To2的控制端的电位进一步降低，从而确保所述信号输出端Out可长时间稳定的输出低电平。
如图5是本申请实施例提供的显示面板的示意图。本申请还提供一种显示面板，包括多个任一上述的栅极驱动电路；以及多个子像素，多个所述子像素与多个所述栅极驱动电路电性连接。
可选地，多个所述栅极驱动电路级联设置，多个所述子像素通过多条栅极控制线与多个所述栅极驱动电路电性连接。
可以理解的，所述显示面板包括液晶显示面板、自发光显示面板（包括有机发光二极管、次毫米发光二极管、微型发光二极管等发光器件）等。
本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (15)

  1. 一种栅极驱动电路，其中，包括：
    第一节点下拉模块，与第一时钟信号线、第二时钟信号线、第一电压端及第一节点电性连接，被配置为根据所述第一时钟信号线传输的第一时钟信号、所述第二时钟信号线传输的第二时钟信号及所述第一电压端传输的第一电压拉低所述第一节点的电位；
    第二节点下拉模块，与所述第一时钟信号线、下拉控制线及第二节点电性连接，被配置为根据所述第一时钟信号及所述下拉控制线传输的下拉控制信号拉低所述第二节点的电位，以使所述栅极驱动电路的信号输出端具有的变量耦合至所述第二节点；
    第二节点维持模块，与所述第一时钟信号线、所述第二时钟信号线、所述下拉控制线及所述第二节点电性连接，被配置为根据所述第一时钟信号、所述第二时钟信号及所述下拉控制信号维持所述第二节点的电位；以及
    输出模块，与所述第一节点和第二节点电性连接，被配置为根据所述第一节点和所述第二节点的电位控制所述信号输出端输出栅极控制信号。
  2. 根据权利要求1所述的栅极驱动电路，其中，所述输出模块包括：
    上拉输出晶体管，所述上拉输出晶体管的控制端与所述第一节点电性连接，所述上拉输出晶体管的输入端与第二电压端电性连接，所述上拉输出晶体管的输出端与所述信号输出端电性连接；
    下拉输出晶体管，所述下拉输出晶体管的控制端与所述第二节点电性连接，所述下拉输出晶体管的输入端与所述第一电压端电性连接，所述下拉输出晶体管的输出端与所述信号输出端电性连接；以及
    第一电容，串联于所述第一节点和所述第二电压端之间。
  3. 根据权利要求1所述的栅极驱动电路，其中，所述第二节点下拉模块包括：
    第一晶体管，所述第一晶体管的控制端与所述第一时钟信号线电性连接，所述第一晶体管的输入端与所述下拉控制线电性连接；
    第二晶体管，所述第二晶体管的控制端与所述第一电压端电性连接，所述第二晶体管的输入端与所述第一晶体管的输出端电性连接，所述第二晶体管的输出端与所述第二节点电性连接。
  4. 根据权利要求3所述的栅极驱动电路，其中，所述第二节点维持模块包括：
    第三晶体管，所述第三晶体管的控制端与所述第一时钟信号线电性连接，所述第三晶体管的输入端与所述下拉控制线电性连接；
    第四晶体管，所述第四晶体管的控制端与所述第一电压端电性连接，所述第四晶体管的输入端与所述第三晶体管的输出端电性连接；
    第五晶体管，所述第五晶体管的控制端与所述第四晶体管的输出端电性连接，所述第五晶体管的输入端与所述第五晶体管的控制端电性连接，所述第五晶体管的输出端与所述第二节点电性连接；
    第六晶体管，所述第六晶体管的控制端与所述第五晶体管的控制端电性连接，所述第六晶体管的输入端与所述第二时钟信号线电性连接；
    第七晶体管，所述第七晶体管的控制端及输入端与所述第六晶体管的输出端电性连接，所述第七晶体管的输出端与所述第五晶体管的控制端电性连接。
  5. 根据权利要求4所述的栅极驱动电路，其中，所述第一节点下拉模块包括：
    第八晶体管，所述第八晶体管的控制端与所述第一时钟信号线电性连接，所述第八晶体管的输入端与所述第一电压端电性连接；
    第九晶体管，所述第九晶体管的控制端与所述第一电压端电性连接，所述第九晶体管的输入端与所述第八晶体管的输出端电性连接；
    第十晶体管，所述第十晶体管的控制端与所述第九晶体管的输出端电性连接，所述第十晶体管的输入端与所述第二时钟信号线电性连接；
    第十一晶体管，所述第十一晶体管的控制端与所述第二时钟信号线电性连接，所述第十一晶体管的输入端与所述第十晶体管的输出端电性连接，所述第十一晶体管的输出端与所述第一节点电性连接；以及
    第二电容，串联于所述第十晶体管的控制端与所述第十晶体管的输出端之间。
  6. 根据权利要求5所述的栅极驱动电路，其中，所述第二节点维持模块还包括：
    第十二晶体管，所述第十二晶体管的控制端与所述第八晶体管的输出端电性连接，所述第十二晶体管的输入端与第二电压端电性连接，所述第十二晶体管的输出端与所述第七晶体管的控制端电性连接。
  7. 根据权利要求5所述的栅极驱动电路，其中，所述栅极驱动电路还包括：
    第一节点上拉模块，包括第十三晶体管，所述第十三晶体管的控制端与所述第一晶体管的输出端电性连接，所述第十三晶体管的输入端与第二电压端电性连接，所述第十三晶体管的输出端与所述第一节点电性连接。
  8. 根据权利要求5所述的栅极驱动电路，其中，所述第一节点下拉模块还包括：
    第十四晶体管，所述第十四晶体管的控制端与所述第一晶体管的输出端电性连接，所述第十四晶体管的输入端与所述第一时钟信号线电性连接，所述第十四晶体管的输出端与所述第八晶体管的输出端电性连接。
  9. 根据权利要求8所述的栅极驱动电路，其中，所述第十四晶体管为双栅晶体管。
  10. 根据权利要求8所述的栅极驱动电路，其中，所述栅极驱动电路还包括：
    重置模块，包括重置晶体管，所述重置晶体管的控制端与重置控制线电性连接，所述重置晶体管的输入端与第二电压端电性连接，所述重置晶体管的输出端与所述第一晶体管的输出端电性连接。
  11. 一种显示面板，其中，包括：
    多个栅极驱动电路，至少一所述栅极驱动电路包括、第一节点下拉模块、第二节点下拉模块、第二节点维持模块及输出模块；所述第一节点下拉模块与第一时钟信号线、第二时钟信号线、第一电压端及第一节点电性连接，所述第一节点下拉模块被配置为根据所述第一时钟信号线传输的第一时钟信号、所述第二时钟信号线传输的第二时钟信号及所述第一电压端传输的第一电压拉低所述第一节点的电位；所述第二节点下拉模块与所述第一时钟信号线、下拉控制线及第二节点电性连接，所述第二节点下拉模块被配置为根据所述第一时钟信号及所述下拉控制线传输的下拉控制信号拉低所述第二节点的电位，以使所述栅极驱动电路的信号输出端具有的变量耦合至所述第二节点；所述第二节点维持模块与所述第一时钟信号线、所述第二时钟信号线、所述下拉控制线及所述第二节点电性连接，所述第二节点维持模块被配置为根据所述第一时钟信号、所述第二时钟信号及所述下拉控制信号维持所述第二节点的电位；所述输出模块与所述第一节点和第二节点电性连接，所述输出模块被配置为根据所述第一节点和所述第二节点的电位控制所述信号输出端输出栅极控制信号；以及
    多个子像素，与多个所述栅极驱动电路电性连接。
  12. 根据权利要求11所述的显示面板，其中，所述输出模块包括：
    上拉输出晶体管，所述上拉输出晶体管的控制端与所述第一节点电性连接，所述上拉输出晶体管的输入端与第二电压端电性连接，所述上拉输出晶体管的输出端与所述信号输出端电性连接；
    下拉输出晶体管，所述下拉输出晶体管的控制端与所述第二节点电性连接，所述下拉输出晶体管的输入端与所述第一电压端电性连接，所述下拉输出晶体管的输出端与所述信号输出端电性连接；以及
    第一电容，串联于所述第一节点和所述第二电压端之间。
  13. 根据权利要求11所述的显示面板，其中，所述第二节点下拉模块包括：
    第一晶体管，所述第一晶体管的控制端与所述第一时钟信号线电性连接，所述第一晶体管的输入端与所述下拉控制线电性连接；
    第二晶体管，所述第二晶体管的控制端与所述第一电压端电性连接，所述第二晶体管的输入端与所述第一晶体管的输出端电性连接，所述第二晶体管的输出端与所述第二节点电性连接。
  14. 根据权利要求13所述的显示面板，其中，所述第二节点维持模块包括：
    第三晶体管，所述第三晶体管的控制端与所述第一时钟信号线电性连接，所述第三晶体管的输入端与所述下拉控制线电性连接；
    第四晶体管，所述第四晶体管的控制端与所述第一电压端电性连接，所述第四晶体管的输入端与所述第三晶体管的输出端电性连接；
    第五晶体管，所述第五晶体管的控制端与所述第四晶体管的输出端电性连接，所述第五晶体管的输入端与所述第五晶体管的控制端电性连接，所述第五晶体管的输出端与所述第二节点电性连接；
    第六晶体管，所述第六晶体管的控制端与所述第五晶体管的控制端电性连接，所述第六晶体管的输入端与所述第二时钟信号线电性连接；
    第七晶体管，所述第七晶体管的控制端及输入端与所述第六晶体管的输出端电性连接，所述第七晶体管的输出端与所述第五晶体管的控制端电性连接。
  15. 根据权利要求14所述的显示面板，其中，所述第一节点下拉模块包括：
    第八晶体管，所述第八晶体管的控制端与所述第一时钟信号线电性连接，所述第八晶体管的输入端与所述第一电压端电性连接；
    第九晶体管，所述第九晶体管的控制端与所述第一电压端电性连接，所述第九晶体管的输入端与所述第八晶体管的输出端电性连接；
    第十晶体管，所述第十晶体管的控制端与所述第九晶体管的输出端电性连接，所述第十晶体管的输入端与所述第二时钟信号线电性连接；
    第十一晶体管，所述第十一晶体管的控制端与所述第二时钟信号线电性连接，所述第十一晶体管的输入端与所述第十晶体管的输出端电性连接，所述第十一晶体管的输出端与所述第一节点电性连接；以及
    第二电容，串联于所述第十晶体管的控制端与所述第十晶体管的输出端之间。
PCT/CN2023/132974 2023-07-07 2023-11-21 栅极驱动电路、显示面板 Ceased WO2025010905A1 (zh)

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