WO2025007407A1 - 晶体管的制备方法及电子设备 - Google Patents

晶体管的制备方法及电子设备 Download PDF

Info

Publication number
WO2025007407A1
WO2025007407A1 PCT/CN2023/116357 CN2023116357W WO2025007407A1 WO 2025007407 A1 WO2025007407 A1 WO 2025007407A1 CN 2023116357 W CN2023116357 W CN 2023116357W WO 2025007407 A1 WO2025007407 A1 WO 2025007407A1
Authority
WO
WIPO (PCT)
Prior art keywords
silicon
layer
silicon layer
etching
gate material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2023/116357
Other languages
English (en)
French (fr)
Other versions
WO2025007407A9 (zh
Inventor
董博闻
李辉辉
李庚霏
胡琪
王桂磊
赵超
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing Superstring Academy of Memory Technology
Original Assignee
Beijing Superstring Academy of Memory Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing Superstring Academy of Memory Technology filed Critical Beijing Superstring Academy of Memory Technology
Publication of WO2025007407A1 publication Critical patent/WO2025007407A1/zh
Publication of WO2025007407A9 publication Critical patent/WO2025007407A9/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass

Definitions

  • the embodiments of the present application relate to the field of semiconductor technology, and in particular to a method for manufacturing a transistor and an electronic device.
  • the vertical gate-all-around (VGAA) transistor is a new type of semiconductor device. Compared with the planar GAA transistor, the vertical GAA transistor (VGAA) has a small projected area and is not limited in channel length.
  • the exposed source/drain is easily contaminated with metal and is difficult to remove, which may cause a short circuit between the source/drain and the metal gate.
  • the embodiment of the present application provides a method for manufacturing a transistor and an electronic device, which effectively prevents the source/drain of the transistor from being contaminated by metal.
  • the technical solution is as follows:
  • a method for preparing a transistor comprising:
  • a first silicon layer 301, a silicon germanium layer 302 and a second silicon layer 303 are sequentially stacked on a silicon substrate 300, wherein the first silicon layer 301 is in contact with the silicon substrate 300;
  • first silicon layer 301 By etching the first silicon layer 301, the silicon germanium layer 302 and the second silicon layer 303, a plurality of first silicon pillars 304 are formed along a first direction;
  • a plurality of columns of second masks 305 are formed on the plurality of first silicon pillars 304 along a second direction, wherein the second masks 305 include sidewalls 305-1; the first silicon layer 301, the silicon germanium layer 302 and the second silicon layer 303 are etched according to the plurality of columns of second masks 305; on the basis of the grooves obtained by etching, the silicon germanium layer 302 is further etched to form lateral grooves; epitaxial silicon is laterally grown on the first silicon layer 301, the lateral grooves and the second silicon layer 303; a gate material is deposited on the first silicon layer 301; anisotropic etching of the gate material is performed according to the plurality of sidewalls 305-1 to remove the gate material outside the epitaxial silicon sidewalls of the second silicon layer 303; the gate material in the plurality of sidewalls 305-1 and the second silicon layer 303 is then removed to form a plurality of second silicon pillars 306, wherein the plurality of second silicon
  • a vertical all-around gate transistor is formed.
  • an electronic device wherein the electronic device includes a logic device, and the logic device is manufactured by the above transistor manufacturing method.
  • the electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal.
  • the gate material deposited outside the epitaxial silicon sidewall of the second silicon layer 303 is removed, and then the remaining gate material in the second silicon layer 303 is removed again, thereby avoiding a short circuit between the source/drain and the gate.
  • FIG. 1 is a schematic diagram of a VGAA transistor provided by one or more exemplary embodiments of the present application
  • FIG. 2 is a flow chart of a method for manufacturing a transistor provided by one or more exemplary embodiments of the present application;
  • FIG3 is a schematic diagram of relevant steps of a method for manufacturing a transistor provided by one or more exemplary embodiments of the present application;
  • FIG. 4 is a schematic diagram of relevant steps of a method for manufacturing a transistor provided by one or more exemplary embodiments of the present application;
  • FIG5 is a schematic diagram of relevant steps of a method for manufacturing a transistor provided by one or more exemplary embodiments of the present application.
  • FIG6 is a schematic diagram of relevant steps of a method for manufacturing a transistor provided by one or more exemplary embodiments of the present application.
  • FIG. 7 is a schematic diagram of relevant steps of a method for manufacturing a transistor provided by one or more exemplary embodiments of the present application.
  • FIG8 is a schematic diagram of relevant steps of a method for manufacturing a transistor provided by one or more exemplary embodiments of the present application.
  • FIG. 9 is a schematic diagram of relevant steps of a method for manufacturing a transistor provided by one or more exemplary embodiments of the present application.
  • FIG. 10 is a flow chart of a method for manufacturing a transistor provided by one or more exemplary embodiments of the present application.
  • FIG. 11 is a schematic diagram of relevant steps of a method for manufacturing a transistor provided by one or more exemplary embodiments of the present application.
  • FIG. 12 is a schematic diagram of relevant steps of a method for manufacturing a transistor provided by one or more exemplary embodiments of the present application.
  • FIG. 13 is a schematic diagram of relevant steps of a method for manufacturing a transistor provided by one or more exemplary embodiments of the present application.
  • FIG. 14 is a schematic diagram of relevant steps of a method for manufacturing a transistor provided by one or more exemplary embodiments of the present application.
  • FIG. 15 is a schematic diagram of relevant steps of a method for manufacturing a transistor provided by one or more exemplary embodiments of the present application.
  • FIG. 16 is a schematic diagram of relevant steps of a method for manufacturing a transistor provided by one or more exemplary embodiments of the present application.
  • FIG. 17 is a schematic diagram of a stacking structure provided by one or more exemplary embodiments of the present application.
  • FIG18 is a schematic diagram of a stacking structure provided by one or more exemplary embodiments of the present application.
  • FIG. 19 is a schematic diagram of a process for forming a stacked structure according to one or more exemplary embodiments of the present application.
  • FIG. 20 is a schematic diagram of a process for forming a stacked structure according to another one or more exemplary embodiments of the present application.
  • FIG. 21 is a schematic diagram of a process for forming a stacked structure according to another one or more exemplary embodiments of the present application.
  • FIG. 22 is a schematic diagram of a process of forming a stacked structure provided by one or more other exemplary embodiments of the present application.
  • a method for preparing a transistor is provided.
  • the method for preparing the transistor is mainly applied in a process for preparing a VGAA transistor.
  • each transistor unit includes a bit line (BL) 111, a word line (WL) 112, a source/drain 113, and a gate 114.
  • multiple transistor units in the same column of the transistor array 100 are connected by coupling with the extended bit line 111; multiple transistor units in the same row of the transistor array 100 are connected by coupling with the extended word line 112.
  • the word line 112 is connected to the gate 114 as a gate line to turn on the transistor unit, and the bit line 111 is connected to the source/drain 113 as a data signal writing line.
  • the word line 112 surrounds the gate 114.
  • FIG. 2 shows a flow chart of a method for manufacturing a transistor provided by an exemplary embodiment of the present application, the method comprising:
  • Step 201 stacking a first silicon layer, a silicon germanium layer, and a second silicon layer in sequence on a silicon substrate;
  • FIG. 3 shows that a first silicon layer 301 , a silicon germanium layer 302 , and a second silicon layer 303 are sequentially stacked on a silicon substrate 300 ; wherein the first silicon layer 301 is in contact with the silicon substrate 300 .
  • Step 202 forming a plurality of first silicon pillars along a first direction by etching the first silicon layer, the silicon germanium layer and the second silicon layer;
  • a plurality of columns of first masks are formed on the second silicon layer along a first direction; the first silicon layer, the silicon germanium layer and the second silicon layer are etched according to the plurality of columns of first masks to form a plurality of first silicon pillars along the first direction.
  • a plurality of columns of first masks are formed along a first direction on the second silicon layer 303.
  • the first direction is the direction of the bit line of the transistor finally generated.
  • the mask material includes a photoresist material, a photoresist, an anti-reflection material, and some hard mask materials. The plurality of columns of first masks extend along the first direction.
  • FIG. 4 shows a three-dimensional structure obtained by etching the silicon substrate 300, the first silicon layer 301, the silicon germanium layer 302 and the second silicon layer 303 according to multiple columns of the first mask.
  • FIG. 4 shows a plurality of first silicon pillars 304 along the first direction.
  • the silicon substrate 300, the first silicon layer 301, the silicon germanium layer 302 and the second silicon layer 303 are etched using a SADP (Self-Aligned Double Patterning) process.
  • SADP Self-Aligned Double Patterning
  • etching is performed using SADP according to the array period size or the critical size.
  • SAQP Self-aligned Quadruple Patterning
  • etching is performed using LELE (Litho-Etch-Lith-Etch) according to the array period size or the critical size.
  • etching is performed using a dry process.
  • Step 203 forming a plurality of columns of second masks along a second direction on the plurality of first silicon pillars, wherein the second masks include sidewalls;
  • Fig. 5 shows a plurality of columns of second masks 305.
  • the plurality of columns of second masks 305 extend along a second direction.
  • the second direction is the direction of a word line of a transistor finally generated.
  • Step 204 etching the first silicon layer, the silicon germanium layer and the second silicon layer according to the second mask of multiple columns; based on the grooves obtained by etching, continuing to etch the silicon germanium layer to form lateral grooves; and laterally epitaxially growing silicon on the first silicon layer, the lateral grooves and the second silicon layer;
  • part (A) of Fig. 6 shows a three-dimensional structure formed after performing a lateral epitaxial silicon operation.
  • Part (B) of Fig. 6 shows a two-dimensional plan view of the corresponding three-dimensional structure observed along the second direction.
  • Step 205 depositing a gate material on the first silicon layer; performing anisotropic etching of the gate material according to the plurality of sidewalls to remove the gate material outside the epitaxial silicon sidewalls of the second silicon layer; and then removing the plurality of sidewalls and the gate material in the second silicon layer to form a plurality of second silicon pillars;
  • the gate material includes at least one of a gate oxide layer, a high-K material and a gate metal layer.
  • the gate material includes dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, and other dielectric materials, and conductive materials such as polysilicon, tantalum, aluminum, and tungsten.
  • dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, and other dielectric materials
  • conductive materials such as polysilicon, tantalum, aluminum, and tungsten.
  • part (A) of FIG7 shows a three-dimensional structure obtained by depositing gate material in the gaps between the silicon germanium layer 302, the second silicon layer 303, and the plurality of sidewalls 305-1.
  • Part (B) of FIG7 shows a two-dimensional schematic diagram of the corresponding three-dimensional structure observed along the second direction. That is, FIG7 shows a three-dimensional structure obtained by filling the gate material above the first silicon layer 301.
  • part (A) of FIG8 shows a three-dimensional structure obtained by performing anisotropic etching of the gate material according to the multiple sidewalls 305-1 in the multiple columns of the second mask 305.
  • Part (B) of FIG8 shows a two-dimensional schematic diagram of the corresponding three-dimensional structure observed along the second direction.
  • the metal residues on the sidewalls of the multiple sidewalls 305-1 and the epitaxial silicon sidewalls of the second silicon layer 303 are also removed.
  • the sidewalls of the silicon germanium layer 302 are also aligned with the sidewalls of the multiple sidewalls 305-1.
  • part (A) of FIG9 shows a three-dimensional structural diagram of multiple second silicon pillars 306 formed by further removing multiple sidewalls 305-1 and gate materials in the second silicon layer 303.
  • Part (B) of FIG9 shows a two-dimensional schematic diagram of the corresponding three-dimensional structure observed along the second direction.
  • the multiple second silicon pillars 306 shown in FIG9 are distributed in an array along the first direction and the second direction.
  • Step 206 forming a vertical all-around gate transistor based on the plurality of second silicon pillars.
  • a vertical all-around gate transistor is formed based on the plurality of second silicon pillars 306 by adding contact pins.
  • the deposited The gate material outside the epitaxial silicon sidewall of the second silicon layer 303 is deposited, and then the remaining gate material in the second silicon layer 303 is removed again, thereby avoiding a short circuit between the source/drain and the gate.
  • FIG. 10 shows a flow chart of a method for manufacturing a transistor provided by an exemplary embodiment of the present application, the method comprising:
  • Step 1001 stacking a first silicon layer, a silicon germanium layer, and a second silicon layer in sequence on a silicon substrate;
  • part (A) of FIG. 11 shows that a first silicon layer 301 , a silicon germanium layer 302 , and a second silicon layer 303 are sequentially stacked on a silicon substrate 300 , wherein the first silicon layer 301 is in contact with the silicon substrate 300 .
  • Step 1002 forming a plurality of first silicon pillars along a first direction by etching the first silicon layer, the silicon germanium layer, and the second silicon layer.
  • a plurality of columns of first masks are formed along a first direction on the second silicon layer 301.
  • the first direction is the direction of the bit line of the transistor finally formed.
  • the mask material includes a photoresist material, a photoresist, an anti-reflection material, and some hard mask materials.
  • the first mask extends along the first direction.
  • part (B) of FIG11 shows that the first silicon layer 301, the silicon germanium layer 302, and the second silicon layer 303 are etched according to multiple columns of the first mask to form a three-dimensional structure of multiple first silicon pillars 304 along the first direction.
  • the partial volume of the first silicon layer 301, the silicon germanium layer 302, and the second silicon layer 303 that is not within the coverage of the first mask is etched away.
  • the etching is performed using a dry process.
  • etching is performed using SADP according to the array period size or the critical size. In one embodiment, etching is performed using SAQP (Self-aligned Quadruple Patterning) according to the array period size or the critical size. In one embodiment, etching is performed using LELE (Litho-Etch-Lith-Etch) according to the array period size or the critical size.
  • Step 1003 filling oxide between the plurality of first silicon pillars
  • part (C) of Fig. 11 shows a three-dimensional structure obtained by oxide between the plurality of first silicon pillars 304.
  • the oxide is silicon dioxide.
  • Step 1004 forming a plurality of columns of second masks along a second direction on the plurality of first silicon pillars, the second masks comprising sidewalls;
  • part (A) of FIG12 shows a three-dimensional structure obtained by forming a plurality of columns of second masks 305 along the second direction on a plurality of first silicon pillars 304.
  • the second masks 305 extend along the second direction.
  • Step 1005 etching the first silicon layer, the silicon germanium layer and the second silicon layer according to a plurality of columns of second masks to form a plurality of first grooves;
  • part (B) of FIG. 12 shows a three-dimensional structure obtained by etching the first silicon layer 301, the silicon germanium layer 302, and the second silicon layer 303 according to the multiple columns of second masks 305 to form multiple first grooves 307.
  • the first silicon layer 301, the silicon germanium layer 302, and the second silicon layer 303 that are not covered by the multiple columns of second masks 305 are etched away.
  • Part (B) of FIG. 12 also shows that any one of the multiple columns of second masks 305 includes three layers of sidewalls 305-1, mandrels 305-2, and sidewalls 305-1.
  • the etching is performed using a dry process.
  • Step 1006 performing a first lateral etching on the silicon germanium layer
  • portion ( C1 ) of FIG. 12 shows a three-dimensional structure obtained by performing a first lateral etching on the silicon germanium layer 302 .
  • Part (C2) of Figure 12 shows a two-dimensional plane view obtained by observing the corresponding three-dimensional structure in a second direction.
  • the second direction is the word line direction.
  • the second direction is the direction of the word line of the transistor finally generated.
  • the first lateral etching is performed using an ALE (Atomic Layer Etch) process.
  • Step 1007 performing a first lateral epitaxial silicon growth on the first silicon layer, the silicon germanium layer and the second silicon layer to form a first lateral groove; filling the first lateral groove with oxide and grinding it flat; filling the first groove with oxide and grinding it flat;
  • part (A1) of Figure 13 shows a three-dimensional structure obtained by performing a first lateral epitaxial silicon growth on the first silicon layer 301, the silicon germanium layer 302 and the second silicon layer 303 to form a first lateral groove 308.
  • Part (A2) of Figure 13 shows a two-dimensional plan view of the corresponding three-dimensional structure observed along the second direction.
  • Part (B1) of FIG. 13 shows a three-dimensional structure obtained by filling the first lateral groove 308 and the first groove 307 with oxide and grinding them flat.
  • Part (B2) of FIG. 13 shows a two-dimensional plane view of the corresponding three-dimensional structure observed along the second direction.
  • the grinding operation is performed by CMP (Chemical Mechanical Polishing).
  • Step 1008 etching the first silicon layer, the silicon germanium layer, and the second silicon layer according to the plurality of mandrels in the plurality of columns of the second mask to form a plurality of second grooves;
  • part (C1) of FIG13 shows a three-dimensional structure in which the first silicon layer 301, the silicon germanium layer 302, and the second silicon layer 303 are etched according to the plurality of mandrels 305-2 in the plurality of columns of the second mask 305 to form a plurality of second grooves 309.
  • Part (C2) of FIG13 shows a two-dimensional plan view of the corresponding three-dimensional structure observed along the second direction.
  • the first silicon layer 301, the silicon germanium layer 302 and the second silicon layer 303 are partially covered by the plurality of mandrels 305-2 and etched away. In one embodiment, the first silicon layer 301, the silicon germanium layer 302 and the second silicon layer 303 are partially covered by the plurality of spacers 305-1 and etched away.
  • a wet process or an ALE (Atomic Layer Etch) process is used to etch the first silicon layer 301, the silicon germanium layer 302 and the second silicon layer 303 to form a plurality of second grooves 309.
  • Step 1009 performing a second lateral etching on the silicon germanium layer
  • part (A1) of FIG14 shows a three-dimensional structure obtained by performing a second lateral etching on the silicon germanium layer 302.
  • Part (A2) of FIG14 shows a two-dimensional plan view of the corresponding three-dimensional structure observed along the second direction. Combined with the first lateral etching of the silicon germanium layer 302 in step 1007, the two lateral etchings enable the silicon germanium material of the silicon germanium layer 302 to be completely removed.
  • Step 1010 performing a second lateral epitaxial silicon growth on the first silicon layer, the silicon germanium layer and the second silicon layer to form a second lateral groove, filling the second lateral groove with oxide and grinding it flat; filling the second groove with oxide and grinding it flat;
  • part (B1) of FIG. 14 shows the first silicon layer 301, the silicon germanium layer 302 and The second silicon layer 303 is subjected to a second lateral epitaxial silicon growth to form a three-dimensional structure of a second lateral groove 310.
  • Part (B2) of Fig. 14 shows a two-dimensional plan view of the corresponding three-dimensional structure observed along the second direction.
  • Part (C1) of Figure 14 shows a three-dimensional structure obtained by filling the second lateral groove 310 with oxide and grinding it flat, and filling the second groove 309 with oxide and grinding it flat.
  • Part (C2) of Figure 14 shows a two-dimensional plan view of the corresponding three-dimensional structure.
  • the oxide is silicon dioxide.
  • the flattening operation is performed by CMP (Chemical Mechanical Polishing).
  • Step 1011 etching the oxide on the first silicon layer
  • part (A1) of FIG15 shows a three-dimensional structure after the oxide between the second silicon layer 303 and the plurality of sidewalls 305-1 is etched.
  • Part (A2) of FIG15 shows a two-dimensional plan view of the corresponding three-dimensional structure.
  • part (B1) of FIG15 shows a three-dimensional structure after the oxide of the further silicon germanium layer 302 is etched.
  • Part (B2) of FIG15 shows a two-dimensional plan view of the corresponding three-dimensional structure. That is, parts (A1), (A2), (B1), and (B2) of FIG15 show schematic diagrams after the oxide above the first silicon layer is etched.
  • the oxide on the silicon germanium layer 302 is etched by a dry process; and then the oxide on the silicon germanium layer 302 is etched by a wet process.
  • Step 1012 depositing a gate material in the gaps between the silicon germanium layer, the second silicon layer, and the plurality of spacers;
  • the gate material includes at least one of a gate oxide layer, a high-K material and a gate metal layer.
  • the gate material includes dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, and conductive materials such as polysilicon, tantalum, aluminum, and tungsten.
  • part (C1) of FIG15 shows a three-dimensional structure obtained by depositing gate material in the gaps between the silicon germanium layer 302, the second silicon layer 303, and the plurality of sidewalls 305-1.
  • Part (C2) of FIG15 shows a two-dimensional plan view of the corresponding three-dimensional structure. That is, parts (C1) and (C2) of FIG15 show schematic diagrams of a three-dimensional structure obtained by depositing gate material in the gap above the first silicon layer 301.
  • Step 1013 performing anisotropic etching of the gate material on the layer where the multiple sidewalls are located, etching to the sidewalls of the multiple sidewalls; and performing anisotropic etching of the gate material on the second silicon layer, etching to the epitaxial silicon sidewalls of the second silicon layer; and performing anisotropic etching of the gate material on the silicon germanium layer outside the coverage of the multiple sidewalls in the multiple columns of the second mask;
  • part (A1) of FIG16 shows a three-dimensional structure obtained by performing anisotropic etching of gate materials on the layer where the multiple sidewalls 305-1 are located, the second silicon layer 303 and the silicon germanium layer 302.
  • the metal anisotropic etching of the layer where the multiple sidewalls 305-1 are located will etch to the sidewalls of the multiple sidewalls
  • the metal anisotropic etching of the second silicon layer 303 will etch to the epitaxial silicon sidewalls
  • the metal anisotropic etching of the silicon germanium layer 302 will etch to the coverage boundary of the multiple sidewalls 305-1.
  • Part (A2) of FIG16 shows a two-dimensional plane view obtained by observing the corresponding three-dimensional structure along the second direction.
  • metal residues on the sidewalls of the plurality of spacers 305-1 and the epitaxial silicon sidewalls of the second silicon layer 303 are removed.
  • the sidewalls of the silicon germanium layer 302 are aligned with the sidewalls of the plurality of spacers 305-1.
  • Step 1014 filling oxide in the gaps between the silicon germanium layer, the second silicon layer, and the plurality of spacers;
  • part (B1) of FIG. 16 shows a three-dimensional structure obtained by filling oxide in the gaps between the silicon germanium layer 302, the second silicon layer 303, and the plurality of sidewalls 305-1.
  • Part (B2) of FIG. 16 shows a two-dimensional plane view obtained by observing the corresponding three-dimensional structure along the second direction. That is, parts (B1) and (B2) of FIG. 16 show a three-dimensional structure obtained by filling oxide above the first silicon layer 301.
  • the oxide is silicon dioxide.
  • Step 1015 removing a plurality of side walls
  • Step 1016 removing the remaining gate material in the second silicon layer to form a plurality of second silicon pillars
  • part (C1) of FIG16 shows a three-dimensional structure obtained by removing the plurality of sidewalls 305-1 and the remaining gate material in the second silicon layer 303.
  • Part (C2) of FIG16 shows a two-dimensional plane view of the corresponding three-dimensional structure observed along the second direction.
  • Parts (C1) and (C2) of FIG16 show the second silicon pillar 306.
  • Step 1017 forming a vertical all-around gate transistor based on the plurality of second silicon pillars.
  • a vertical all-around gate transistor is formed by adding contact pins based on the plurality of second silicon pillars 306.
  • the vertical all-around gate transistor is also called a metal ring gate transistor or a metal replaceable gate transistor.
  • the gate material deposited outside the epitaxial silicon sidewall of the second silicon layer 303 is removed, and then the remaining gate material in the second silicon layer 303 is removed again, thereby avoiding a short circuit between the source/drain and the gate.
  • step 202 or step 1002 includes: forming a plurality of first silicon pillars along a first direction by etching the silicon substrate, the first silicon layer, the silicon germanium layer, and the second silicon layer.
  • step 201 and step 1001 when executing step 201 and step 1001 , well isolation is also formed in the stack structure.
  • part (A1) of FIG17 shows a stacked structure after forming well isolation.
  • Part (A2) of FIG17 shows a two-dimensional plan view of the stacked structure.
  • the stacked structure after well isolation includes a silicon substrate 300, a first silicon layer 301, a silicon germanium layer 302, and a second silicon layer 303.
  • the silicon substrate 300 includes an upper silicon substrate 300-1 and a lower silicon substrate 300-2.
  • the lower silicon substrate 300-2 is doped to N type
  • the upper silicon substrate 300-1 is doped to P type
  • the first silicon layer 301 is doped to P type.
  • the lower silicon substrate 300-2 is doped to P type
  • the upper silicon substrate 300-1 is doped to N type
  • the first silicon layer 301 is doped to N type.
  • part (B1) of FIG. 17 shows the three-dimensional structure of the plurality of first silicon pillars 307 obtained after considering the well isolation.
  • Part (B2) of FIG. 17 shows the plane view corresponding to the three-dimensional structure.
  • the etching depth of the longitudinal etching of the first silicon pillars 307 only reaches the upper part of the silicon substrate 300-1, and the plurality of first silicon pillars 307 (i.e., the bit lines) are isolated from each other by the PN junction structure to prevent leakage between the first silicon pillars 307.
  • part (A1) of FIG. 18 shows a stacked structure after forming well isolation.
  • Part (A2) of FIG. 18 shows a two-dimensional plan view of the stacked structure.
  • the stacked structure after well isolation includes a silicon substrate 300, a first silicon layer 301, a silicon germanium layer 302, a second silicon layer 303, and a third silicon layer 304 located between the silicon substrate 300 and the first silicon layer.
  • the silicon substrate The first silicon layer 300 is doped to P type
  • the first silicon layer 301 and the third silicon layer 304 are doped to N type.
  • part (B1) of FIG. 18 shows the three-dimensional structure of the plurality of first silicon pillars 307 obtained after considering the well isolation.
  • Part (B2) of FIG. 18 shows the plane view corresponding to the three-dimensional structure.
  • the etching depth of the longitudinal etching of the first silicon pillars 307 only reaches the third silicon layer 304, and the plurality of first silicon pillars 307 (i.e., the bit lines) are isolated from each other by the PN junction structure to prevent leakage between the first silicon pillars 307.
  • step 201 and step 1001 are provided.
  • a first possible implementation method is to obtain a silicon substrate; dope the lower part of the silicon substrate into N-type and dope the upper part of the silicon substrate into P-type; sequentially stack a first silicon layer, a silicon germanium layer and a second silicon layer on the silicon substrate; dope the first silicon layer into P-type.
  • annealing is performed to restore the silicon substrate lattice.
  • FIG. 19 (A) shows a silicon substrate 300 ;
  • FIG. 19 (B) shows a lower silicon substrate 300-1 doped with N type and an upper silicon substrate 300-2 doped with P type.
  • FIG. 19 (C) shows a first silicon layer 301, a silicon germanium layer 302, and a second silicon layer 303 stacked, wherein the first silicon layer 301 is doped with P type.
  • a second possible implementation method is to obtain a silicon substrate; dope the lower part of the silicon substrate into P type, and dope the upper part of the silicon substrate into N type; sequentially stack a first silicon layer, a silicon germanium layer, and a second silicon layer on the silicon substrate; and dope the first silicon layer into N type.
  • an annealing operation is performed to restore the silicon substrate lattice.
  • FIG20 (A) shows a silicon substrate 300;
  • FIG20 (B) shows a lower silicon substrate 300-1 doped with P type and an upper silicon substrate 300-2 doped with N type.
  • FIG20 (C) shows a first silicon layer 301, a silicon germanium layer 302, and a second silicon layer 303 stacked, wherein the first silicon layer 301 is doped with N type.
  • a third possible implementation method is to obtain a silicon substrate; dope the silicon substrate into N-type; sequentially stack a third silicon layer, a first silicon layer, a silicon germanium layer, and a second silicon layer on the silicon substrate; and dope the third silicon layer and the first silicon layer into P-type.
  • FIG21 (A) shows a silicon substrate 300
  • FIG21 (B) shows a silicon substrate 300 doped to N type
  • FIG21 (C) shows a third silicon layer 304, a first silicon layer 301, a silicon germanium layer 302, and a second silicon layer 303 stacked together, wherein the third silicon layer 304 is doped to P type, and the first silicon layer 301 is doped to P type.
  • a fourth possible implementation method is to obtain a silicon substrate; dope the silicon substrate into P type; sequentially stack a third silicon layer, a first silicon layer, a silicon germanium layer, and a second silicon layer on the silicon substrate; and dope the third silicon layer and the first silicon layer into N type.
  • part (A) of FIG22 shows a silicon substrate 300
  • part (B) of FIG22 shows a silicon substrate 300 doped to a P type
  • Part (C) of FIG22 shows a third silicon layer 304, a first silicon layer 301, a silicon germanium layer 302, and a second silicon layer 303 obtained by stacking, wherein the third silicon layer 304 is doped to an N type, and the first silicon layer 301 is doped to an N type.
  • An embodiment of the present application provides an electronic device, wherein the electronic device includes a logic device, wherein the logic device includes a 3D NAND gate circuit as provided in the above embodiment.
  • the logic device can be applied to a logic operator and a memory, etc.
  • the electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal.
  • first and second are used for descriptive purposes only and should not be understood as indicating or implying relative importance.
  • the term “at least one” means one or more, and the term “plurality” means two or more, unless otherwise clearly defined.
  • a and/or B can represent: A exists alone, A and B exist at the same time, and B exists alone.
  • the character "/" in this article generally indicates that the associated objects before and after are in an "or" relationship.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本申请公开了一种晶体管的制备方法和电子设备，属于半导体技术领域。所述方法包括：通过对第一硅层(301)、硅锗层(302)和第二硅层(303)进行刻蚀，形成沿第一方向的多个第一硅柱(304)；按照多列第二掩模(305)刻蚀第一硅层(301)、硅锗层(302)和第二硅层(303)；对第一硅层(301)、侧向凹槽和第二硅层(303)侧向外延硅；在第一硅层(301)的上方沉积栅极材料；按照多个侧墙(305-1)执行栅极材料的各向异性刻蚀，以形成多个第二硅柱(306)；基于多个第二硅柱(306)，形成垂直全环绕栅极晶体管。上述方法防止了源/漏被金属沾污。

Description

晶体管的制备方法及电子设备
本申请要求于2023年07月06日提交的申请号为202310827205.6、发明名称为“晶体管的制备方法及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及半导体技术领域，特别涉及一种晶体管的制备方法及电子设备。
背景技术
垂直栅极全环绕(Vertical Gate-All-Around，VGAA)晶体管是一种新型半导体器件，相对平面GAA晶体管，垂直GAA晶体管(VGAA)投影面积小，且沟道长度不受限。
相关技术中，在沉积VGAA晶体管的金属栅极的过程中，暴露的源/漏容易产生金属沾污并且难以去除，有可能造成源/漏与金属栅极之间的短路。
发明内容
本申请实施例提供了一种晶体管的制备方法及电子设备，有效防止了晶体管的源/漏被金属沾污。所述技术方案如下：
一方面，提供了一种晶体管的制备方法，所述方法包括：
在硅衬底300上依次堆叠第一硅层301、硅锗层302和第二硅层303，所述第一硅层301与所述硅衬底300相接触；
通过对所述第一硅层301、所述硅锗层302和所述第二硅层303进行刻蚀，形成沿第一方向的多个第一硅柱304；
在所述多个第一硅柱304上沿第二方向形成多列第二掩模305，所述第二掩模305包括侧墙305-1；按照所述多列第二掩模305刻蚀所述第一硅层301、所述硅锗层302和所述第二硅层303；在刻蚀得到的凹槽的基础上，继续刻蚀所述硅锗层302，形成侧向凹槽；对所述第一硅层301、所述侧向凹槽和所述第二硅层303侧向外延硅；在所述第一硅层301的上方沉积栅极材料；按照多个侧墙305-1执行所述栅极材料的各向异性刻蚀，去除了所述第二硅层303的外延硅侧壁之外的栅极材料；再去除所述多个侧墙305-1、所述第二硅层303内的栅极材料，形成多个第二硅柱306，所述多个第二硅柱306沿所述第一方向和所述第二方向阵列分布；
基于所述多个第二硅柱306，形成垂直全环绕栅极晶体管。
另一方面，提供了一种电子设备，电子设备中包括逻辑器件，逻辑器件由上述晶体管的制备方法制作得到。电子设备包括智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或智能移动终端。
本申请实施例提供的技术方案带来的有益效果至少包括：
通过对第二硅层303执行栅极材料的各向异性刻蚀，去除了沉积在第二硅层303的外延硅侧壁之外的栅极材料，之后，再次去除了第二硅层303内剩余的栅极材料，进而避免了源/漏和栅极之间的短路。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请一个或多个示例性实施例提供的VGAA晶体管的示意图；
图2是本申请一个或多个示例性实施例提供的晶体管的制备方法的流程图；
图3是本申请一个或多个示例性实施例提供的晶体管的制备方法的相关步骤的示意图；
图4是本申请一个或多个示例性实施例提供的晶体管的制备方法的相关步骤的示意图；
图5是本申请一个或多个示例性实施例提供的晶体管的制备方法的相关步骤的示意图；
图6是本申请一个或多个示例性实施例提供的晶体管的制备方法的相关步骤的示意图；
图7是本申请一个或多个示例性实施例提供的晶体管的制备方法的相关步骤的示意图；
图8是本申请一个或多个示例性实施例提供的晶体管的制备方法的相关步骤的示意图；
图9是本申请一个或多个示例性实施例提供的晶体管的制备方法的相关步骤的示意图；
图10是本申请一个或多个示例性实施例提供的晶体管的制备方法的流程图；
图11是本申请一个或多个示例性实施例提供的晶体管的制备方法的相关步骤的示意图；
图12是本申请一个或多个示例性实施例提供的晶体管的制备方法的相关步骤的示意图；
图13是本申请一个或多个示例性实施例提供的晶体管的制备方法的相关步骤的示意图；
图14是本申请一个或多个示例性实施例提供的晶体管的制备方法的相关步骤的示意图；
图15是本申请一个或多个示例性实施例提供的晶体管的制备方法的相关步骤的示意图；
图16是本申请一个或多个示例性实施例提供的晶体管的制备方法的相关步骤的示意图；
图17是本申请一个或多个示例性实施例提供的堆叠结构的示意图；
图18是本申请一个或多个示例性实施例提供的堆叠结构的示意图；
图19是本申请一个或多个示例性实施例提供的堆叠结构的形成过程的示意图；
图20是本申请另一个或多个示例性实施例提供的堆叠结构的形成过程的示意图；
图21是本申请另一个或多个示例性实施例提供的堆叠结构的形成过程的示意图；
图22是本申请另一个或多个示例性实施例提供的堆叠结构的形成过程的示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
本申请实施例中，提供了一种晶体管的制备方法，可选地，该晶体管的制备方法主要应用于VGAA晶体管的制备过程中。
首先对VGAA晶体管的结构进行介绍，如图1所示，在晶体管阵列100中包括多个晶体管单元。每个晶体管单元中包括位线(Bit Line，BL)111、字线(Word Line，WL)112、源极/漏极113、栅极114。
其中，晶体管阵列100中在同一列的多个晶体管单元通过与延伸的位线111耦接，对同一列的多个晶体管单元进行连通；晶体管阵列100中在同一行的多个晶体管单元通过与延伸的字线112耦接，对同一行的多个晶体管单元进行连通。
其中，字线112连接栅极114，作为栅线开启晶体管单元；位线111连接源极/漏极113，作为数据信号写入线。字线112在栅极114外围环绕包裹。
图2示出了本申请一个示例性实施例提供的晶体管的制备方法的流程图，该方法包括：
步骤201，在硅衬底上依次堆叠第一硅层、硅锗层和第二硅层；
结合参考图3，图3示出了在硅衬底300上依次堆叠第一硅层301、硅锗层302和第二硅层303；其中，第一硅层301与硅衬底300相接触。
步骤202，通过对第一硅层、硅锗层和第二硅层进行刻蚀，形成沿第一方向的多个第一硅柱；
在一个实施例中，在第二硅层上沿第一方向形成多列第一掩模；按照多列第一掩模刻蚀第一硅层、硅锗层和第二硅层，形成沿第一方向的多个第一硅柱。
在第二硅层303上沿第一方向形成多列第一掩模。可选的，第一方向为最终生成的晶体管的位线的方向。可选的，掩模材料包括光阻材料、光刻胶、防反射材料以及一些硬掩膜材料等。多列第一掩模沿第一方向延伸。
结合参考图4，图4示出了按照多列第一掩模刻蚀硅衬底300、第一硅层301、硅锗层302和第二硅层303得到的立体结构。图4示出了沿第一方向的多个第一硅柱304。在一个实施例中，采用SADP(Self-Aligned Double Patterning，自对准双图形)工艺对硅衬底300、第一硅层301、硅锗层302和第二硅层303 进行刻蚀。在一个实施例中，根据阵列周期尺寸或关键尺寸使用SADP进行刻蚀。在一个实施例中，根据阵列周期尺寸或关键尺寸使用SAQP(Self-aligned Quadruple Patterning，自对准四重图形)进行刻蚀。在一个实施例中，根据阵列周期尺寸或关键尺寸使用LELE(Litho-Etch-Lith-Etch，光刻蚀刻光刻蚀刻)进行刻蚀。在一个实施例中，采用干法工艺进行刻蚀。
步骤203，在多个第一硅柱上沿第二方向形成多列第二掩模，第二掩模包括侧墙；
结合参考图5，图5示出了多列第二掩模305。多列第二掩模305沿第二方向延伸。可选的，第二方向为最终生成的晶体管的字线的方向。
步骤204，按照多列第二掩模刻蚀第一硅层、硅锗层和第二硅层；在刻蚀得到的凹槽的基础上，继续刻蚀硅锗层，形成侧向凹槽；对第一硅层、侧向凹槽和第二硅层侧向外延硅；
结合参考图6，图6的(A)部分示出了执行侧向外延硅操作之后形成的立体结构。图6的(B)部分示出了沿第二方向观察对应的立体结构的二维平面图。
步骤205，在第一硅层的上方沉积栅极材料；按照多个侧墙执行栅极材料的各向异性刻蚀，去除了第二硅层的外延硅侧壁之外的栅极材料；再去除多个侧墙、第二硅层内的栅极材料，形成多个第二硅柱；
可选的，栅极材料包括栅氧化层，高K材料和栅极金属层中的至少一种。
可选的，栅极材料包括氧化硅、氮化硅、氮氧化硅、氧化铝、氧化铪、氧化锆等介质材料，以及多晶硅，钽、铝、钨等导电材料。
结合参考图7，图7的(A)部分示出了在硅锗层302、第二硅层303、多个侧墙305-1的空隙内沉积栅极材料得到的立体结构。图7的(B)部分示出了沿第二方向观察对应的立体结构的二维示意图。即，图7示出了在第一硅层301的上方填充栅极材料得到的立体结构。
结合参考图8，图8的(A)部分示出了按照多列第二掩模305中的多个侧墙305-1执行栅极材料的各向异性刻蚀得到的立体结构。图8的(B)部分示出了沿第二方向观察对应的立体结构的二维示意图。在一个实施例中，执行栅极材料的各向异性刻蚀之后，还清除多个侧墙305-1的侧壁、第二硅层303的外延硅侧壁上的金属残留。在一个实施例中，执行栅极材料的各向异性刻蚀之后，还将硅锗层302的侧壁与多个侧墙305-1的侧壁对齐。
结合参考图9，图9的(A)部分示出了进一步去除多个侧墙305-1、第二硅层303内的栅极材料，形成的多个第二硅柱306的立体结构图。图9的(B)部分示出了沿第二方向观察对应的立体结构的二维示意图。图9示出的多个第二硅柱306沿第一方向和第二方向阵列分布。
步骤206，基于多个第二硅柱，形成垂直全环绕栅极晶体管。
在一个实施例中，基于多个第二硅柱306，通过添加接触引脚，形成垂直全环绕栅极晶体管。
综上所述，通过对第二硅层303执行栅极材料的各向异性刻蚀，去除了沉 积在第二硅层303的外延硅侧壁之外的栅极材料，之后，再次去除了第二硅层303内剩余的栅极材料，进而避免了源/漏和栅极之间的短路。
图10示出了本申请一个示例性实施例提供的晶体管的制备方法的流程图，该方法包括：
步骤1001，在硅衬底上依次堆叠第一硅层、硅锗层和第二硅层；
结合参考图11，图11的(A)部分示出了在硅衬底300上依次堆叠第一硅层301、硅锗层302和第二硅层303，其中，第一硅层301与硅衬底300相接触。
步骤1002，通过对第一硅层、硅锗层和第二硅层进行刻蚀，形成沿第一方向的多个第一硅柱。
在一个实施例中，在第二硅层上沿第一方向形成多列第一掩模；按照多列第一掩模刻蚀第一硅层、硅锗层和第二硅层，形成沿第一方向的多个第一硅柱。
在第二硅层301上沿第一方向形成多列第一掩模。可选的，第一方向为最终形成的晶体管的位线的方向。掩膜材料包括光阻材料、光刻胶、防反射材料以及一些硬掩膜材料等。可选的，第一掩模沿第一方向延伸。
结合参考图11，图11的(B)部分示出了按照多列第一掩模刻蚀第一硅层301、硅锗层302和第二硅层303，形成沿第一方向的多个第一硅柱304的立体结构。在一个实施例中，刻蚀掉第一硅层301、硅锗层302和第二硅层303中未处于第一掩模的覆盖范围的部分体积。在一个实施例中，采用干法工艺进行刻蚀。
在一个实施例中，根据阵列周期尺寸或关键尺寸使用SADP进行刻蚀。在一个实施例中，根据阵列周期尺寸或关键尺寸使用SAQP(Self-aligned Quadruple Patterning，自对准四重图形)进行刻蚀。在一个实施例中，根据阵列周期尺寸或关键尺寸使用LELE(Litho-Etch-Lith-Etch，光刻蚀刻光刻蚀刻)进行刻蚀。
步骤1003，在多个第一硅柱之间填充氧化物；
结合参考图11，图11的(C)部分示出了在多个第一硅柱304之间氧化物得到的立体结构。可选的，氧化物为二氧化硅。
步骤1004，在多个第一硅柱上沿第二方向形成多列第二掩模，第二掩模包括侧墙；
结合参考图12，图12的(A)部分示出了在多个第一硅柱304上沿第二方向形成多列第二掩模305得到的立体结构。第二掩模305沿第二方向延伸。
步骤1005，按照多列第二掩模刻蚀第一硅层、硅锗层和第二硅层，形成多个第一凹槽；
结合参考图12，图12的(B)部分示出了按照多列第二掩模305刻蚀第一硅层301、硅锗层302和第二硅层303，形成多个第一凹槽307得到的立体结构。在一个实施例中，刻蚀掉第一硅层301、硅锗层302和第二硅层303中未被多列第二掩模305覆盖的部分体积。图12的(B)部分还示出了多列第二掩模305中的任意一个第二掩模305，包括侧墙305-1、芯轴305-2和侧墙305-1的三层 结构。在一个实施例中，采用干法工艺进行刻蚀。
步骤1006，对硅锗层执行第一次侧向刻蚀；
结合参考图12，图12的(C1)部分示出了对硅锗层302执行第一次侧向刻蚀得到的立体结构。
图12的(C2)部分示出了以第二方向观察对应的立体结构得到的二维平面图。在一个实施例中，第二方向为字线方向。第二方向为最终生成的晶体管的字线的方向。
在一个实施例中，采用ALE(Atomic Layer Etch，原子层刻蚀)工艺执行第一次侧向刻蚀。
步骤1007，对第一硅层、硅锗层和第二硅层执行第一次侧向外延硅，形成第一侧向凹槽；对第一侧向凹槽填充氧化物并磨平；对第一凹槽填充氧化物并磨平；
结合参考图13，图13的(A1)部分示出了第一硅层301、硅锗层302和第二硅层303执行第一次侧向外延硅，形成第一侧向凹槽308得到的立体结构。图13的(A2)部分示出了沿第二方向观察对应的立体结构的二维平面图。
图13的(B1)部分示出了对第一侧向凹槽308和第一凹槽307填充氧化物并磨平得到的立体结构。图13的(B2)部分示出了沿第二方向观察对应的立体结构的二维平面图。在一个实施例中，通过CMP(Chemical Mechanical Polishing，化学机械抛光)执行磨平操作。
步骤1008，按照多列第二掩模中的多个芯轴刻蚀第一硅层、硅锗层和第二硅层，形成多个第二凹槽；
结合参考图13，图13的(C1)部分示出了按照多列第二掩模305中的多个芯轴305-2刻蚀第一硅层301、硅锗层302和第二硅层303，形成多个第二凹槽309的立体结构。图13的(C2)部分示出了沿第二方向观察对应的立体结构的二维平面图。
在一个实施例中，刻蚀掉第一硅层301、硅锗层302和第二硅层303中被多个芯轴305-2覆盖的部分体积。在一个实施例中，刻蚀掉第一硅层301、硅锗层302和第二硅层303中未被多个侧墙305-1覆盖的部分体积。
在一个实施例中，采用湿法工艺或ALE(Atomic Layer Etch，原子层刻蚀)工艺刻蚀第一硅层301、硅锗层302和第二硅层303，形成多个第二凹槽309。
步骤1009，对硅锗层执行第二次侧向刻蚀；
结合参考图14，图14的(A1)部分示出了对硅锗层302执行第二次侧向刻蚀得到的立体结构。图14的(A2)部分示出了沿第二方向观察到的对应的立体结构的二维平面图。结合步骤1007对硅锗层302的第一次侧向刻蚀，两次侧向刻蚀使得硅锗层302的硅锗材料被全部去除。
步骤1010，对第一硅层、硅锗层和第二硅层执行第二次侧向外延硅，形成第二侧向凹槽，对第二侧向凹槽填充氧化物并磨平；对第二凹槽填充氧化物并磨平；
结合参考图14，图14的(B1)部分示出了对第一硅层301、硅锗层302和 第二硅层303执行第二次侧向外延硅，形成第二侧向凹槽310的立体结构。图14的(B2)部分示出了沿第二方向观察到的对应的立体结构的二维平面图。
图14的(C1)部分示出了对第二侧向凹槽310填充氧化物并磨平以及对第二凹槽309填充氧化物并磨平得到的立体结构。图14的(C2)部分示出了对应的立体结构的二维平面图。可选的，氧化物为二氧化硅。
在一个实施例中，通过CMP(Chemical Mechanical Polishing，化学机械抛光)执行磨平操作。
步骤1011，刻蚀第一硅层上方的氧化物；
结合参考图15，图15的(A1)部分示出了第二硅层303、多个侧墙305-1之间的氧化物被刻蚀之后的立体结构。图15的(A2)部分示出了对应的立体结构的二维平面图。结合参考图15，图15的(B1)部分示出了进一步的硅锗层302的氧化物被刻蚀之后的立体结构。图15的(B2)部分示出了对应的立体结构的二维平面图。即，图15的(A1)、(A2)、(B1)、(B2)部分示出了第一硅层上方的氧化物被刻蚀之后的示意图。
在一个实施例中，通过干法工艺刻蚀硅锗层302上方的氧化物；再通过湿法工艺刻蚀硅锗层302的氧化物。
步骤1012，在硅锗层、第二硅层和多个侧墙的空隙内沉积栅极材料；
可选的，栅极材料包括栅氧化层，高K材料和栅极金属层中的至少一种。可选的，栅极材料包括氧化硅、氮化硅、氮氧化硅、氧化铝、氧化铪、氧化锆等介质材料，以及多晶硅，钽、铝、钨等导电材料。
结合参考图15，图15的(C1)部分示出了在硅锗层302、第二硅层303和多个侧墙305-1的空隙内沉积栅极材料得到的立体结构。图15的(C2)部分示出了对应的立体结构的二维平面图。即，图15的(C1)(C2)部分示出了在第一硅层301的上方空隙内沉积栅极材料得到的立体结构的示意图。
步骤1013，对多个侧墙的所在层，执行栅极材料的各向异性刻蚀，刻蚀至多个侧墙的侧壁；以及，对第二硅层执行栅极材料的各向异性刻蚀，刻蚀至第二硅层的外延硅侧壁；以及，在多列第二掩模中的多个侧墙的覆盖范围之外，在硅锗层执行栅极材料的各向异性刻蚀；
结合参考图16，图16的(A1)部分示出了对多个侧墙305-1的所在层、第二硅层303和硅锗层302执行栅极材料的各向异性刻得到的立体结构。其中，多个侧墙305-1的所在层的金属各向异性刻蚀将刻蚀至多个侧墙的侧壁，第二硅层303的金属各向异性刻蚀将刻蚀至外延硅侧壁，硅锗层302的金属各向异性刻蚀将刻蚀至多个侧墙305-1的覆盖范围边界。图16的(A2)部分示出了沿第二方向观察对应的立体结构得到的二维平面图。
在一个实施例中，执行栅极材料的各向异性刻蚀之后，还清除多个侧墙305-1的侧壁、第二硅层303的外延硅侧壁上的金属残留。在一个实施例中，执行栅极材料的各向异性刻蚀之后，还将硅锗层302的侧壁与多个侧墙305-1的侧壁对齐。
步骤1014，在硅锗层、第二硅层、多个侧墙之间的空隙内填充氧化物；
结合参考图16，图16的(B1)部分示出了在硅锗层302、第二硅层303、多个侧墙305-1之间的空隙内填充氧化物得到的立体结构。图16的(B2)部分示出了沿第二方向观察对应的立体结构得到的二维平面图。即，图16的(B1)部分和(B2)部分示出了在第一硅层301的上方填充氧化物得到的立体结构。可选的，氧化物为二氧化硅。
步骤1015，去除多个侧墙；
步骤1016，去除第二硅层内剩余的栅极材料，形成多个第二硅柱；
结合参考图16，图16的(C1)部分示出了去除多个侧墙305-1、第二硅层303内剩余的栅极材料得到的立体结构。图16的(C2)部分示出了沿第二方向观察对应的立体结构得到的二维平面图。图16的(C1)和(C2)部分示出了第二硅柱306。
步骤1017，基于多个第二硅柱，形成垂直全环绕栅极晶体管。
在一个实施例中，对基于多个第二硅柱306，通过添加接触引脚，形成垂直全环绕栅极晶体管。在本实施例中，垂直全环绕栅极晶体管也被称为金属环栅晶体管、金属可替代栅晶体管。
综上所述，通过对第二硅层303执行栅极材料的各向异性刻蚀，去除了沉积在第二硅层303的外延硅侧壁之外的栅极材料，之后，再次去除了第二硅层303内剩余的栅极材料，进而避免了源/漏和栅极之间的短路。
在一个实施例中，步骤202或步骤1002包括：通过对硅衬底、第一硅层、硅锗层和第二硅层进行刻蚀，形成沿第一方向的多个第一硅柱。
基于图2和图10所示的方法实施例，在执行步骤201和步骤1001时，还在堆叠结构中形成阱隔离。
在一个实施例中，结合参考图17，图17的(A1)部分示出了形成阱隔离之后的堆叠结构。图17的(A2)部分示出了堆叠结构的二维平面图。考虑阱隔离之后的堆叠结构包括硅衬底300、第一硅层301、硅锗层302和第二硅层303。进一步的，硅衬底300包括上部分硅衬底300-1和下部分硅衬底300-2。可选的，下部分硅衬底300-2被掺杂为N型，上部分硅衬底300-1被掺杂为P型，第一硅层301被掺杂为P型。可选的，下部分硅衬底300-2被掺杂为P型，上部分硅衬底300-1被掺杂为N型，第一硅层301被掺杂为N型。
可以注意到的是，图17的(B1)部分示出了考虑阱隔离之后得到的多个第一硅柱307的立体结构。图17的(B2)部分示出了立体结构对应的平面图。此时，执行第一硅柱307的纵向刻蚀的刻蚀深度仅达到上部分硅衬底300-1，多个第一硅柱307(即位线)彼此之间通过PN结结构相互隔离，防止第一硅柱307之间发生漏电。
在一个实施例中，结合参考图18，图18的(A1)部分示出了形成阱隔离之后的堆叠结构。图18的(A2)部分示出了堆叠结构的二维平面图。考虑阱隔离之后的堆叠结构包括硅衬底300、第一硅层301、硅锗层302、第二硅层303，以及位于硅衬底300和第一硅层中间的第三硅层304。可选的，硅衬底 300被掺杂为P型，第一硅层301和第三硅层304被掺杂为N型。
可以注意到的是，图18的(B1)部分示出了考虑阱隔离之后得到的多个第一硅柱307的立体结构。图18的(B2)部分示出了立体结构对应的平面图。此时，执行第一硅柱307的纵向刻蚀的刻蚀深度仅达到第三硅层304，多个第一硅柱307(即位线)彼此之间通过PN结结构相互隔离，防止第一硅柱307之间发生漏电。
示意性的，提供了步骤201和步骤1001如下四种可能的实现方式。
第一种可能的实现方式：获取硅衬底；将硅衬底中的下部分硅衬底掺杂为N型，将硅衬底中的上部分硅衬底掺杂为P型；在硅衬底上依次堆叠第一硅层、硅锗层和第二硅层；将第一硅层掺杂为P型。可选的，对硅衬底进行掺杂之后通过退火操作恢复硅衬底晶格。
结合参考图19，图19的(A)部分示出了硅衬底300；图19的(B)部分示出了掺杂为N型的下部分硅衬底300-1和掺杂为P型的上部分硅衬底300-2。图19的(C)部分示出了堆叠得到的第一硅层301、硅锗层302和第二硅层303，第一硅层301被掺杂为P型。
第二种可能的实现方式：获取硅衬底；将硅衬底中的下部分硅衬底掺杂为P型，将硅衬底中的上部分硅衬底掺杂为N型；在硅衬底上依次堆叠第一硅层、硅锗层和第二硅层；将第一硅层掺杂为N型。可选的，对硅衬底进行掺杂之后通过退火操作恢复硅衬底晶格。
结合参考图20，图20的(A)部分示出了硅衬底300；图20的(B)部分示出了掺杂为P型的下部分硅衬底300-1和掺杂为N型的上部分硅衬底300-2。图20的(C)部分示出了堆叠得到的第一硅层301、硅锗层302和第二硅层303，第一硅层301被掺杂为N型。
第三种可能的实现方式：获取硅衬底；将硅衬底掺杂为N型；在硅衬底上依次堆叠第三硅层、第一硅层、硅锗层和第二硅层；将第三硅层和第一硅层掺杂为P型。
结合参考图21，图21的(A)部分示出了硅衬底300；图21的(B)部分示出了掺杂为N型的硅衬底300。图21的(C)部分示出了堆叠得到的第三硅层304、第一硅层301、硅锗层302和第二硅层303，第三硅层304被掺杂为P型，第一硅层301被掺杂为P型。
第四种可能的实现方式：获取硅衬底；将硅衬底掺杂为P型；在硅衬底上依次堆叠第三硅层、第一硅层、硅锗层和第二硅层；将第三硅层和第一硅层掺杂为N型。
结合参考图22，图22的(A)部分示出了硅衬底300；图22的(B)部分示出了掺杂为P型的硅衬底300。图22的(C)部分示出了堆叠得到的第三硅层304、第一硅层301、硅锗层302和第二硅层303，第三硅层304被掺杂为N型，第一硅层301被掺杂为N型。
本申请实施例提供了一种电子设备，该电子设备中包括逻辑器件，逻辑器件中包括如上述实施例中所提供的3D与非门电路。该逻辑器件可以应用于逻辑运算器和存储器等。
可选地，该电子设备包括智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或智能移动终端。
在本申请中，术语“第一”和“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。术语“至少一个”是指一个或多个，术语“多个”指两个或两个以上，除非另有明确的限定。
本申请中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
以上所述仅为本申请的示例性实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (10)

  1. 一种晶体管的制备方法，其特征在于，所述方法包括：
    在硅衬底(300)上依次堆叠第一硅层(301)、硅锗层(302)和第二硅层(303)，所述第一硅层(301)与所述硅衬底(300)相接触；
    通过对所述第一硅层(301)、所述硅锗层(302)和所述第二硅层(303)进行刻蚀，形成沿第一方向的多个第一硅柱(304)；
    在所述多个第一硅柱(304)上沿第二方向形成多列第二掩模(305)，所述第二掩模(305)包括侧墙(305-1)；按照所述多列第二掩模(305)刻蚀所述第一硅层(301)、所述硅锗层(302)和所述第二硅层(303)；在刻蚀得到的凹槽的基础上，继续刻蚀所述硅锗层(302)，形成侧向凹槽；对所述第一硅层(301)、所述侧向凹槽和所述第二硅层(303)侧向外延硅；在所述第一硅层(301)的上方沉积栅极材料；按照多个侧墙(305-1)执行所述栅极材料的各向异性刻蚀，去除了所述第二硅层(303)的外延硅侧壁之外的栅极材料；再去除所述多个侧墙(305-1)、所述第二硅层(303)内的栅极材料，形成多个第二硅柱(306)，所述多个第二硅柱(306)沿所述第一方向和所述第二方向阵列分布；
    基于所述多个第二硅柱(306)，形成垂直全环绕栅极晶体管。
  2. 根据权利要求1所述的方法，其特征在于，所述按照多个侧墙(305-1)执行所述栅极材料的各向异性刻蚀，包括：
    对所述多个侧墙(305-1)的所在层，执行栅极材料的各向异性刻蚀，刻蚀至所述多个侧墙(305-1)的侧壁；以及，对所述第二硅层(303)执行栅极材料的各向异性刻蚀，刻蚀至所述第二硅层(303)的外延硅侧壁；以及，在所述多个侧墙(305-1)的覆盖范围之外，在所述硅锗层(302)执行栅极材料的各向异性刻蚀。
  3. 根据权利要求1或2所述的方法，其特征在于，所述按照所述多列第二掩模(305)刻蚀所述第一硅层(301)、所述硅锗层(302)和所述第二硅层(303)；在刻蚀得到的凹槽的基础上，继续刻蚀所述硅锗层(302)，形成侧向凹槽；在所述第一硅层(301)、所述侧向凹槽和所述第二硅层(303)侧向外延硅，包括：
    按照所述多列第二掩模(305)刻蚀所述第一硅层(301)、所述硅锗层(302)和所述第二硅层(303)，形成多个第一凹槽(307)；对所述硅锗层(302)执行第一次侧向刻蚀，之后，对所述第一硅层(301)、所述硅锗层(302)和所述第二硅层(303)执行第一次侧向外延硅，形成第一侧向凹槽(308)；
    按照所述多列第二掩模(305)中的多个芯轴(305-2)刻蚀所述第一硅层(301)、所述硅锗层(302)和所述第二硅层(303)，形成多个第二凹槽 (309)；对所述硅锗层(302)执行第二次侧向刻蚀，之后，对所述第一硅层(301)、所述硅锗层(302)和所述第二硅层(303)执行第二次侧向外延硅，形成第二侧向凹槽(310)，两次侧向刻蚀使得所述硅锗层(302)的硅锗材料被全部去除。
  4. 根据权利要求3所述的方法，其特征在于，所述形成第一侧向凹槽(308)之后，还包括：对所述第一侧向凹槽(308)填充氧化物并磨平；对所述第一凹槽(307)填充氧化物并磨平；
    所述形成第二侧向凹槽(310)之后，还包括：对所述第二侧向凹槽(310)填充氧化物并磨平；对所述第二凹槽(309)填充氧化物并磨平。
  5. 根据权利要求4所述的方法，其特征在于，所述在所述第一硅层(301)的上方沉积栅极材料，包括：
    刻蚀第一硅层(301)上方的氧化物；
    在所述硅锗层(302)、所述第二硅层(303)和所述多个侧墙(305-1)的空隙内沉积所述栅极材料。
  6. 根据权利要求5所述的方法，其特征在于，所述刻蚀第一硅层301上方的氧化物，包括：
    通过干法工艺刻蚀所述硅锗层(302)上方的氧化物；
    再通过湿法工艺刻蚀所述硅锗层(302)的氧化物。
  7. 根据权利要求5所述的方法，其特征在于，所述再去除所述多个侧墙(305-1)、所述第二硅层(303)内的栅极材料，形成多个第二硅柱(306)，包括：
    在所述硅锗层(302)、所述第二硅层(303)、所述多个侧墙(305-1)之间的空隙内填充氧化物；
    去除所述多个侧墙(305-1)；
    去除所述第二硅层(303)内剩余的栅极材料，形成所述多个第二硅柱(306)。
  8. 根据权利要求1或2所述的方法，其特征在于，所述多列第二掩模(305)中的任意一个第二掩模(305)包括侧墙(305-1)、芯轴(305-2)和侧墙(305-1)的三层结构。
  9. 一种电子设备，其特征在于，所述电子设备中包括逻辑器件，所述逻辑器件中包括按照如权利要求1至8任一所述的晶体管的制备方法制备的晶体管。
  10. 根据权利要求9所述的电子设备，其特征在于，所述电子设备包括智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或智能移动终端。
PCT/CN2023/116357 2023-07-06 2023-08-31 晶体管的制备方法及电子设备 Ceased WO2025007407A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202310827205.6 2023-07-06
CN202310827205.6A CN119300381A (zh) 2023-07-06 2023-07-06 晶体管的制备方法及电子设备

Publications (2)

Publication Number Publication Date
WO2025007407A1 true WO2025007407A1 (zh) 2025-01-09
WO2025007407A9 WO2025007407A9 (zh) 2025-03-06

Family

ID=94160188

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/116357 Ceased WO2025007407A1 (zh) 2023-07-06 2023-08-31 晶体管的制备方法及电子设备

Country Status (2)

Country Link
CN (1) CN119300381A (zh)
WO (1) WO2025007407A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013122975A (ja) * 2011-12-09 2013-06-20 Takehide Shirato 半導体装置及びその製造方法
CN114078701A (zh) * 2020-08-14 2022-02-22 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US20230066811A1 (en) * 2021-08-30 2023-03-02 Changxin Memory Technologies, Inc. Semiconductor structure and manufacturing method thereof
WO2023108885A1 (zh) * 2021-12-13 2023-06-22 中国科学院微电子研究所 具有晶体侧墙的纳米线/片器件及制造方法及电子设备

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013122975A (ja) * 2011-12-09 2013-06-20 Takehide Shirato 半導体装置及びその製造方法
CN114078701A (zh) * 2020-08-14 2022-02-22 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US20230066811A1 (en) * 2021-08-30 2023-03-02 Changxin Memory Technologies, Inc. Semiconductor structure and manufacturing method thereof
WO2023108885A1 (zh) * 2021-12-13 2023-06-22 中国科学院微电子研究所 具有晶体侧墙的纳米线/片器件及制造方法及电子设备

Also Published As

Publication number Publication date
CN119300381A (zh) 2025-01-10
WO2025007407A9 (zh) 2025-03-06

Similar Documents

Publication Publication Date Title
CN104425388B (zh) 一种半浮栅器件的制造方法及器件
US9397108B2 (en) 3-D non-volatile memory device and method of manufacturing the same
US12315565B2 (en) Three-dimensional memory structure fabricated using repeated active stack sections
US9711657B2 (en) Silicide process using OD spacers
CN106992182B (zh) 存储器件及其制造方法及包括该存储器件的电子设备
CN103579126A (zh) 一种u型结构的半浮栅器件及其制造方法
CN116171043B (zh) 半导体结构及其制备方法
CN110600473A (zh) 三维存储结构及其制作方法
CN112071838A (zh) 存储器及其形成方法
TWI856511B (zh) Nor型記憶體件及其製造方法及包括記憶體件的電子設備
CN107068686B (zh) 存储器件及其制造方法及包括该存储器件的电子设备
CN111863826A (zh) 图形化掩膜的制作方法及三维nand存储器的制作方法
CN101800190A (zh) 隔离层的形成方法及非易失性存储装置的制造方法
CN113257920B (zh) 带支撑部的纳米线/片器件及其制造方法及电子设备
CN104124248B (zh) 一种抬升共源区的nor型闪存单元及其制备方法
WO2023102951A1 (zh) 一种垂直mosfet器件及其制造方法、应用
WO2025007407A1 (zh) 晶体管的制备方法及电子设备
CN209785940U (zh) 存储器
US20250031444A1 (en) 3d-stacked semiconductor device manufactured using channel spacer
CN107634061B (zh) 一种半导体器件的制造方法
CN112038341A (zh) 存储结构及其形成方法
WO2025007409A1 (zh) 晶体管的制备方法及电子设备
TW202410419A (zh) 記憶體件及其製造方法及包括記憶體件的電子設備
CN117939873A (zh) 半导体结构的制备方法、半导体结构和半导体存储器
CN102842536A (zh) 半导体装置的单元接触和位元线的制作方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23944132

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE