WO2024259879A1 - 存储单元、存储器及其制备方法 - Google Patents

存储单元、存储器及其制备方法 Download PDF

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Publication number
WO2024259879A1
WO2024259879A1 PCT/CN2023/131305 CN2023131305W WO2024259879A1 WO 2024259879 A1 WO2024259879 A1 WO 2024259879A1 CN 2023131305 W CN2023131305 W CN 2023131305W WO 2024259879 A1 WO2024259879 A1 WO 2024259879A1
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Prior art keywords
gate
layer
sacrificial layer
bit line
extending along
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English (en)
French (fr)
Inventor
唐怡
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Definitions

  • the present disclosure relates to the field of storage technology, and in particular to a storage unit, a memory and a preparation method thereof.
  • DRAM Dynamic Random Access Memory
  • the memory cell can adopt a 1T1C architecture, that is, it includes a transistor and a capacitor.
  • memory cells are beginning to be arranged in three-dimensional space.
  • 1T1C architecture memory cells due to the scalability problem of 1T1C architecture memory cells and the complexity of their process, the electrical performance of the memory cells is easily degraded when the size of the memory cells is further reduced, making it difficult to further reduce the size of the memory cells while ensuring the electrical performance of the memory cells.
  • the present disclosure provides a storage unit, a memory and a method for manufacturing the same.
  • the present disclosure provides a memory cell including a transistor and a capacitor.
  • the transistor includes: a semiconductor layer, a first gate and a second gate; wherein the semiconductor layer includes a first part extending along a first direction, and a second part and a third part respectively connected to two ends of the first part and extending along a second direction; the second direction intersects with the first direction, and a side of the second part away from the third part is electrically connected to a bit line; the first gate and the second gate are respectively located on opposite sides of the first part in the second direction.
  • the capacitor is located on a side of the third portion away from the second portion and is electrically connected to the third portion.
  • one of the first gate and the second gate includes a first sub-gate and a second sub-gate which are stacked in a direction away from the first portion and have different materials.
  • the first sub-gate is a polysilicon gate
  • the second sub-gate and the other of the first gate and the second gate are metal gates.
  • the second portion and the third portion are located on the same side of the first portion.
  • the first gate is located in a space surrounded by the first portion, the second portion and the third portion, and is electrically connected to the first word line.
  • the second gate is located on a side of the first portion away from the second portion and the third portion along the second direction, and includes a first sub-gate and a second sub-gate. The second sub-gate is electrically connected to the second word line.
  • the memory cell further comprises: a first gate dielectric layer and a second gate dielectric layer.
  • the first gate dielectric layer is located between the first gate and the first portion.
  • the second gate dielectric layer is located between the first sub-gate and the first portion. Wherein, along the second direction, the thickness of the second gate dielectric layer is greater than the thickness of the first gate dielectric layer.
  • the bit line extends along the second direction.
  • the capacitor protrudes from the third portion along the second direction toward the side where the second gate is located.
  • the memory cell also includes: a first isolation structure, a second isolation structure, and a third isolation structure.
  • the first isolation structure is located between the first gate and the second portion, and between the first gate and the third portion.
  • the second isolation structure is located between the second gate and the bit line, and between the second gate and the capacitor.
  • the third isolation structure is located on the same side of the first gate, the third portion, the capacitor, and the first isolation structure between the first gate and the third portion, and is in contact with and connected to the first isolation structure between the first gate and the second portion.
  • a length of the second portion is greater than a length of the third portion.
  • a memory comprises: at least one memory cell as described in any of the above embodiments, at least one bit line, at least one first word line and at least one second word line.
  • the bit line extends along the second direction and is electrically connected to the second portion of the memory cell.
  • the first word line extends along the third direction and is electrically connected to the first gate of the memory cell.
  • the second word line extends along the third direction and is electrically connected to the second gate of the memory cell.
  • the third direction intersects with the first direction and the second direction in pairs.
  • the two storage units are mirror-symmetrical to each other, and the second parts of the two storage units are opposite and connected to form an integral structure.
  • the memory cell includes: a first isolation structure located between the first gate and the second portion and between the first gate and the third portion; a third isolation structure located on the same side of the first gate, the third portion, the capacitor, and the first isolation structure between the first gate and the third portion, and in contact with and connected to the first isolation structure between the first gate and the second portion.
  • the first isolation structures located between the first gate and the second portion of the two memory cells are opposite and connected as an integral structure;
  • the third isolation structures of the two memory cells are located on the same side of the first gate, the third portion, the capacitor, and the first isolation structure between the first gate and the third portion.
  • the three isolation structures are opposite to each other and connected to form an integrated structure.
  • a method for preparing a memory includes the following steps.
  • a stack structure is formed, wherein the stack structure includes a plurality of first sacrificial layers and a plurality of second sacrificial layers that are alternately stacked.
  • the stack structure is etched along the stacking direction of the first sacrificial layer and the second sacrificial layer to form a first receiving hole.
  • a semiconductor layer is formed on the inner side wall of the second sacrificial layer in the first receiving hole; the semiconductor layer includes a first portion extending along a first direction, and a second portion and a third portion respectively connected to both ends of the first portion and extending along a second direction; the second direction intersects the first direction.
  • a first gate is formed on a side of the first portion away from the inner sidewall of the second sacrificial layer.
  • the stacked structure at a side of the first portion away from the first gate is etched, and a second gate is formed at a side of the first portion away from the first gate.
  • the second sacrificial layer located on a side of the second portion away from the third portion is removed to form a bit line accommodating groove.
  • a bit line is formed in the bit line receiving groove, and the bit line is electrically connected to the second part.
  • the second sacrificial layer located on a side of the third portion facing away from the second portion is removed to form a capacitor accommodating groove.
  • a capacitor is formed in the capacitor receiving groove, and the capacitor is electrically connected to the third part.
  • forming a semiconductor layer on the inner sidewall of the second sacrificial layer in the first receiving hole includes the following steps.
  • a semiconductor material layer is formed on the hole wall of the first containing hole.
  • the outer sidewall of the first sacrificial layer extending along the second direction is etched until the semiconductor material layer is exposed.
  • the semiconductor material layer is etched based on the removal area of the first sacrificial layer extending along the second direction to remove the semiconductor material layer extending along the second direction between adjacent second sacrificial layers to form an initial semiconductor layer.
  • the outer sidewall of the first sacrificial layer extending along the first direction is etched until the initial semiconductor layer is exposed.
  • the initial semiconductor layer is etched based on the removal area of the first sacrificial layer extending along the first direction to remove the initial semiconductor layer extending along the first direction between adjacent second sacrificial layers to form semiconductor layers respectively located on the inner sidewalls of each second sacrificial layer.
  • the method for preparing the memory further includes the following steps.
  • a first dielectric material layer is formed on the hole wall of the first receiving hole; wherein the semiconductor material layer is formed on the surface of the first dielectric material layer away from the hole wall of the first receiving hole.
  • the first dielectric material layer is etched to form a second gate dielectric layer between the inner side wall of the second sacrificial layer and the semiconductor layer.
  • the method before the outer sidewall of the first sacrificial layer extending along the second direction is etched until the semiconductor material layer is exposed, the method further includes the following steps.
  • a second dielectric material layer is formed to cover the semiconductor material layer and fill the first receiving hole.
  • the second dielectric material layer and the stacked structure and semiconductor material layer located on one side of the second dielectric material layer are etched along the stacking direction of the first sacrificial layer and the second sacrificial layer to form a first isolation groove extending along the first direction, and the remaining second dielectric material layer constitutes an initial first isolation structure.
  • a third isolation structure is formed in the first isolation trench.
  • forming the first gate on a side of the first portion away from the inner sidewall of the second sacrificial layer includes the following steps.
  • the initial first isolation structure is etched along the stacking direction of the first sacrificial layer and the second sacrificial layer to form a second accommodating hole and a first isolation structure located on opposite sides of the second accommodating hole in the first direction, and the semiconductor material layer and the third isolation structure located on opposite sides of the second accommodating hole in the second direction are exposed.
  • a first gate dielectric layer is conformally formed on the hole wall of the second receiving hole.
  • a first gate covering the first gate dielectric layer and filling the second receiving hole and a first word line correspondingly connected to the first gate are formed.
  • the method for preparing the memory further includes the following steps.
  • the first insulating material is backfilled in the removed area of the first sacrificial layer extending along the second direction and the etched area of the semiconductor material layer.
  • the removed area of the first sacrificial layer extending along the first direction and the etched area of the initial semiconductor layer are backfilled with a second insulating material.
  • the etching of the stacked structure on a side of the first portion away from the first gate and forming the second gate on a side of the first portion away from the first gate also includes the following steps.
  • the second sacrificial layer and the second insulating material of the first part away from the first gate are etched to form a second isolation groove extending along the second direction and spaced apart in the first direction, and the outer side wall of the corresponding end of the first part and a part of the first insulating material are exposed in the second isolation groove.
  • a second isolation structure is formed in the second isolation trench.
  • the second sacrificial layer in the interval between the adjacent second isolation grooves in the first direction is etched.
  • the sacrificial layer and the second insulating material form a third accommodating hole and expose the second isolation structures on two opposite sides of the third accommodating hole in the first direction, while retaining a portion of the second sacrificial layer in the interval between adjacent second isolation grooves to form a first sub-gate.
  • a second sub-gate covering the first sub-gate and a second word line correspondingly connected to the second sub-gate are formed in the third receiving hole; wherein the second gate includes the first sub-gate and the second sub-gate.
  • the removal of the second sacrificial layer located on the side of the second part away from the third part to form a bit line accommodating groove also includes: on the side of the second part away from the third part, etching the outer wall of the second sacrificial layer extending along the second direction until the second isolation structure and the outer wall of the second part are exposed to form the bit line accommodating groove.
  • the step of forming the bit line in the bit line receiving groove further includes: filling the bit line receiving groove with metal material to form the bit line.
  • FIG1 is a schematic diagram of the structure of a storage unit provided in some embodiments.
  • FIG2 is an electrical property curve diagram of a transistor in the memory cell shown in FIG1 ;
  • FIG3 is a schematic diagram of the structure of another storage unit provided in some embodiments.
  • FIG4 is a schematic diagram of the three-dimensional structure of the storage unit shown in FIG3 ;
  • FIG5 is a schematic diagram of the structure of a memory provided in some embodiments.
  • FIG6 is a schematic top view of another memory provided in some embodiments in the X-Y plane;
  • FIG7 is a schematic flow chart of a method for preparing a memory provided in some embodiments.
  • FIG8 is a schematic flow chart of a step S300 in the method for preparing the memory shown in FIG7 ;
  • FIG9 is a schematic flow chart of another step S300 in the method for preparing the memory shown in FIG7 ;
  • FIG10 is a schematic flow chart of a step S400 in the method for preparing the memory shown in FIG7 ;
  • FIG. 11 is a schematic flow chart of a step S500 in the method for preparing the memory shown in FIG. 7 ;
  • FIG12 is a schematic diagram of a structure obtained after forming a stacked structure provided in some embodiments.
  • FIG13 is a schematic structural diagram of a structure obtained after forming a first receiving hole provided in some embodiments.
  • FIG14 is a schematic structural diagram of a structure obtained after forming a first dielectric material layer provided in some embodiments.
  • FIG15 is a schematic structural diagram of a structure obtained after forming a semiconductor material layer provided in some embodiments.
  • FIG16 is a schematic structural diagram of a structure obtained after forming a second dielectric material layer provided in some embodiments.
  • FIG17 is a schematic structural diagram of a structure obtained after forming a first isolation trench provided in some embodiments.
  • FIG18 is a schematic structural diagram of a structure obtained after forming a third isolation structure provided in some embodiments.
  • FIG. 19 is a schematic structural diagram of a structure obtained after forming a second receiving hole and a first isolation structure provided in some embodiments;
  • FIG20 is a schematic structural diagram of a structure obtained after forming a first gate dielectric layer provided in some embodiments.
  • FIG21 is a schematic structural diagram of a structure obtained after forming a first gate and a first word line provided in some embodiments;
  • FIG22 is a schematic structural diagram of a structure obtained by etching the outer sidewall of the first sacrificial layer extending along the second direction until the semiconductor material layer is exposed, provided in some embodiments;
  • FIG23 is a schematic structural diagram of a structure obtained after forming an initial semiconductor layer provided in some embodiments.
  • FIG24 is a schematic structural diagram of a structure obtained after backfilling the first insulating material provided in some embodiments.
  • FIG25 is a schematic structural diagram of a structure obtained by etching the outer sidewall of the first sacrificial layer extending along the first direction until the initial semiconductor layer is exposed, provided in some embodiments;
  • FIG26 is a schematic diagram of a structure obtained after forming a semiconductor layer provided in some embodiments.
  • FIG27 is a schematic structural diagram of a structure obtained after backfilling with a second insulating material provided in some embodiments;
  • FIG28 is a schematic structural diagram of a structure obtained after forming a second isolation trench provided in some embodiments.
  • FIG29 is a schematic structural diagram of a structure obtained after forming a second isolation structure provided in some embodiments.
  • FIG30 is a schematic structural diagram of a structure obtained after forming a third receiving hole provided in some embodiments.
  • FIG31 is a schematic structural diagram of a structure obtained after forming a second gate and a second word line provided in some embodiments;
  • FIG32 is a schematic diagram of a structure obtained after forming a bit line accommodating groove provided in some embodiments.
  • FIG33 is a schematic structural diagram of a structure obtained after forming a bit line provided in some embodiments.
  • FIG34 is a schematic diagram of another structure obtained after forming a bit line in some embodiments.
  • FIG35 is a schematic structural diagram of a structure obtained after forming a capacitor receiving groove provided in some embodiments.
  • FIG36 is a schematic diagram of a structure obtained after forming a capacitor provided in some embodiments.
  • Figure 37 is a schematic diagram of the cross-sectional structure of a capacitor in the X-Z plane provided in some embodiments.
  • first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and/or portions, these elements, components, regions, layers, doping types, and/or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.
  • Embodiments of the invention are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and/or tolerances are anticipated.
  • Embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present disclosure.
  • FIG. 1 illustrates a three-dimensional structure of a memory cell
  • FIG. 1 is a top view of the memory cell shown in (a) of FIG. 1 .
  • the memory cell adopts a 1T1C architecture, that is, includes a transistor 1 and a capacitor 2.
  • the transistor 1 includes a gate 01 integrally connected to the word line WL, and a gate oxide layer 02 and a semiconductor layer 11 sequentially surrounding the gate 01; wherein two opposite outer side walls of the semiconductor layer 11 in a first direction (e.g., X direction) are respectively connected to the bit line BL and the capacitor 2, and the word line WL extends in a vertical direction (e.g., Z direction).
  • a first direction e.g., X direction
  • the portion of the semiconductor layer 11 connected to the bit line BL is a source
  • the portion connected to the capacitor 2 is a drain.
  • the electrical curve of the transistor 1 can be obtained as shown in FIG2 .
  • the transistor 1 adopts the above structure and there will be a gate induced drain leakage (GIDL) effect; that is, when the gate voltage (Gate Voltage) is zero or a negative voltage, if the drain voltage is a positive voltage, leakage current is easily formed.
  • GIDL gate induced drain leakage
  • the current curve I 11 is the drain current curve of the transistor 1 in the off state when the drain voltage is 1V
  • the current curve I 12 is the drain current curve of the transistor 1 in the off state when the drain voltage is 0.05V
  • the current curve I 21 is the drain current curve of the transistor 1 in the on state when the drain voltage is 1V
  • the current curve I 12 is the drain current curve of the transistor 1 in the on state when the drain voltage is 0.05V.
  • the embodiments of the present disclosure provide a storage unit and a memory, which are beneficial to reducing the planar occupied area of the storage unit to improve the storage density and storage capacity of the memory, and are also beneficial to ensuring that the storage unit has better electrical performance and reliability to improve the electrical performance and reliability of the memory.
  • some embodiments of the present disclosure provide a storage unit that can be applied to a memory, especially a DRAM.
  • the memory cell U includes a transistor 1 and a capacitor 2.
  • the transistor 1 includes a semiconductor layer 11, a first gate 12, and a second gate 13.
  • the semiconductor layer 11 includes a first portion 111 extending along a first direction (e.g., X direction), and a second portion 112 and a third portion 113 respectively connected to both ends of the first portion 111 and extending along a second direction (e.g., Y direction).
  • the second direction (e.g., Y direction) and the first direction (e.g., X direction) intersect, for example, are orthogonal.
  • the side of the second portion 112 away from the third portion 113 is electrically connected to the bit line BL.
  • the first gate 12 and the second gate 13 are respectively located on opposite sides of the first portion 111 in the second direction (e.g., Y direction).
  • the capacitor 2 is located on a side of the third portion 113 away from the second portion 112 and is electrically connected to the third portion 113.
  • the first portion 111 in the semiconductor layer 11 can be used as a channel region of the transistor 1 to form a channel current under the control of the gate voltages of the first gate 12 and the second gate 13.
  • the second portion 112 in the semiconductor layer 11 is connected to the bit line BL, and the second portion 112 can be, for example, a source.
  • the third portion 113 in the semiconductor layer 11 is connected to the capacitor 2, and the third portion 113 can be, for example, a drain.
  • the semiconductor layer 11 of the transistor 1 is configured to include a first portion 111 extending in a first direction (e.g., X direction), and a second portion 112 and a third portion 113 respectively connected to both ends of the first portion 111 and extending in a second direction (e.g., Y direction), and the second portion 112 is electrically connected to the bit line BL on one side away from the third portion 113, and the third portion 113 is electrically connected to the capacitor 2 on one side away from the second portion 112, and the first portion 111 is provided with a first gate 12 and a second gate 13 on two opposite sides in the second direction (e.g., Y direction).
  • a first direction e.g., X direction
  • a second portion 112 and a third portion 113 respectively connected to both ends of the first portion 111 and extending in a second direction (e.g., Y direction)
  • the second portion 112 is electrically connected to the bit line BL on one side away from the third portion 113
  • the transistor 1 adopts the aforementioned structure, which is not only conducive to improving the space utilization rate of the region where the transistor 1 is located, so as to effectively reduce the plane area of a single memory cell U, but also conducive to increasing the contact area between the transistor 1 (e.g., source) and the bit line BL through the extension length of the second portion 112 in the semiconductor layer 11, and increasing the contact area between the transistor 1 (e.g., drain) and the capacitor 2 through the extension length of the third portion 113 in the semiconductor layer 11, so as to effectively reduce the contact resistance.
  • a first gate 12 and a second gate 13 are respectively provided on opposite sides of the first portion 111 of the semiconductor layer 11 in a second direction (for example, the Y direction), which is also beneficial to increase the thickness of the semiconductor layer 11, especially the first portion 111, to avoid leakage of the transistor 1, thereby improving the reliability of the transistor 1.
  • the storage unit U provided in the embodiment of the present disclosure can not only occupy a smaller plane area to improve the storage density and storage capacity of the memory, but also ensure that the storage unit U has better electrical performance and reliability, thereby improving the electrical performance and reliability of the memory.
  • the semiconductor layer 11 includes but is not limited to an indium gallium zinc oxide film layer (i.e., Indium Gallium Zinc Oxide, referred to as IGZO film layer).
  • IGZO film layer Indium Gallium Zinc Oxide
  • the anti-leakage characteristics of the transistor 1 can be improved accordingly, and it is beneficial to reduce the production cost of the memory unit U, simplify the process of the memory unit U to improve production efficiency, etc.
  • the second portion 112 and the third portion 113 of the semiconductor layer 11 are located on the same side of the first portion 111. In this way, the second portion 112 and the third portion 113 of the semiconductor layer 11 can form a continuous three-sided space with the first portion 111 at both ends of the first portion 111. Accordingly, the first gate 12 is located in the space surrounded by the first portion 111, the second portion 112 and the third portion 113 of the semiconductor layer 11, and is electrically connected to the first word line WL1.
  • the second gate 13 is located on one side of the first portion 111 away from the second portion 112 and the third portion 113 along the second direction (e.g., the Y direction), and includes a first sub-gate 131 and a second sub-gate 132.
  • the second sub-gate 132 is electrically connected to the second word line WL2.
  • the first word line WL1 may extend along a third direction (e.g., Z direction), and the third direction (e.g., Z direction) is perpendicular to the intersection plane of the first direction and the second direction.
  • the first gate 12 and the first word line WL1 are an integral structure.
  • the second word line WL2 may also extend along the third direction (e.g., Z direction), and the second sub-gate 132 of the second gate 13 and the second word line WL2 are an integral structure.
  • the bit line BL extends along the second direction (eg, direction Y). Accordingly, along the second direction (eg, direction Y), the length of the second portion 112 of the semiconductor layer 11 is greater than the length of the third portion 113 .
  • the second portion 112 of the semiconductor layer 11 is electrically connected to the bit line BL, and the length of the second portion 112 is greater than the length of the third portion 113, which helps to ensure that the second portion 112 can have a larger contact area with the bit line BL along the extension direction of the bit line BL, so as to further reduce the contact resistance between the transistor 1 (for example, the source) and the bit line BL.
  • the bit line BL is formed of a conductive material, and the material of the bit line BL includes but is not limited to a silicon-based material, a metal-based material, or a combination thereof.
  • the material of the bit line BL includes polysilicon, metal, metal nitride, metal silicide, or a combination thereof.
  • the bit line BL may be a single-layer structure of tungsten, titanium nitride, or polysilicon, or may be a stacked-layer structure of titanium nitride, tungsten, or the like.
  • one of the first gate 12 and the second gate 13 includes a first sub-gate 131 and a second sub-gate 132 which are stacked in a direction away from the first portion 111 and are made of different materials.
  • FIG3 illustrates an example in which the second gate 13 includes the first sub-gate 131 and the second sub-gate 132, but is not limited thereto.
  • the first sub-gate 131 is a polysilicon gate.
  • the other one is a metal gate.
  • the second gate 13 includes a first sub-gate 131 and a second sub-gate 132.
  • the first gate 12 and the second sub-gate 132 are metal gates.
  • the metal gate includes but is not limited to a single structure with excellent conductivity such as tungsten or copper, and may also include a stacked structure of metal and metal, or metal and metal compound.
  • the metal gate includes a stacked structure of titanium nitride and tungsten.
  • the memory unit U further includes: a first gate dielectric layer 14 and a second gate dielectric layer 15.
  • the first gate dielectric layer 14 is located between the first gate 12 and the first portion 111 of the semiconductor layer 11.
  • the second gate dielectric layer 15 is located between the first sub-gate 131 of the second gate 13 and the first portion 111 of the semiconductor layer 11.
  • the thickness of the second gate dielectric layer 15 is greater than the thickness of the first gate dielectric layer 14.
  • the thickness values of the second gate dielectric layer 15 and the first gate dielectric layer 14 can be set to match each other according to requirements, but the thickness of the second gate dielectric layer 15 needs to be greater than the thickness of the first gate dielectric layer 14 as a limiting condition.
  • the first gate dielectric layer 14 is coated on the sidewalls of the first gate 12 along the circumference of the first gate 12; that is, the first gate dielectric layer 14 can coat the sidewalls of the first gate 12 extending along the first direction (e.g., X direction) and the second direction (e.g., Y direction), respectively.
  • first direction e.g., X direction
  • second direction e.g., Y direction
  • the second gate dielectric layer 15 is arranged parallel to the second gate 13, and the second gate dielectric layer 15 and the second gate 13 may have the same length dimension in the first direction (e.g., the X direction).
  • the orthographic projection of the second gate dielectric layer 15 along the second direction substantially coincides with the orthographic projection of the first sub-gate 131 in the second gate 13 in the second direction (e.g., the Y direction).
  • the materials of the first gate dielectric layer 14 and the second gate dielectric layer 15 may be the same or different.
  • the material of the first gate dielectric layer 14 and/or the second gate dielectric layer 15 includes, but is not limited to, silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-K dielectric material, ferroelectric material, antiferroelectric material, or a combination thereof.
  • K is a dielectric constant
  • the dielectric constant of the high-K dielectric material is, for example, greater than or equal to 3.9, and may be, for example, 20.
  • the high-K dielectric material may include hafnium oxide ( HfO2 ), zirconium oxide ( ZrO2 ) , aluminum oxide ( Al2O3), lanthanum oxide (La2O3 ) , titanium oxide ( TiO2 ) , tantalum oxide ( Ta2O5 ), niobium oxide ( Nb2O5 ), or strontium titanium oxide ( SrTiO3 ).
  • the material of the first gate dielectric layer 14 and/or the second gate dielectric layer 15 may be silicon oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), zinc oxide (ZnO), zirconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ), or the like.
  • the material of the second gate dielectric layer 15 is polysilicon oxide.
  • the second gate dielectric layer 15 is located between the first sub-gate 131 of the second gate 13 and the first portion 111 of the semiconductor layer 11. Compared with the first gate dielectric layer 14, the second gate dielectric layer 15 has a larger thickness, which can compensate for the oxygen vacancies in the first portion 111 (for example, the channel region) of the semiconductor layer 11 to a certain extent, especially in the embodiment where the second gate dielectric layer 15 is formed of polysilicon oxide, thereby facilitating improving the reliability of the transistor 1.
  • the bit line BL extends along the second direction (e.g., the Y direction).
  • the capacitor 2 protrudes from the third portion 113 of the semiconductor layer 11 along the second direction (e.g., the Y direction) toward the side where the second gate 13 is located.
  • the memory cell U further includes: a first isolation structure 3, a second isolation structure 4, and a third isolation structure 5.
  • the first isolation structure 3 is located between the first gate 12 and the second portion 112 of the semiconductor layer 11, and between the first gate 12 and the third portion 113 of the semiconductor layer 11.
  • the portion of the first isolation structure 3 located between the first gate 12 and the second portion 112 of the semiconductor layer 11, and the portion of the first isolation structure 3 located between the first gate 12 and the third portion 113 of the semiconductor layer 11, both extend along the second direction (e.g., the Y direction), and cover the sidewall of the corresponding first gate dielectric layer 14 along the second direction (e.g., the Y direction).
  • the second isolation structure 4 is located between the second gate 13 and the bit line BL, and between the second gate 13 and the capacitor 2.
  • the portion of the second isolation structure 4 located between the second gate 13 and the bit line BL, and the portion of the second isolation structure 4 located between the second gate 13 and the capacitor 2 both extend along the second direction (e.g., the Y direction), and cover the sidewalls of the corresponding second gate dielectric layer 15 along the second direction (e.g., the Y direction).
  • the third isolation structure 5 is located on the same side of the first gate 12, the third portion 113 of the semiconductor layer 11, the capacitor 2, and the first isolation structure 3 between the first gate 12 and the third portion 113, and is in contact with and connected to the first isolation structure 3 between the first gate 12 and the second portion 112 of the semiconductor layer 11.
  • the third isolation structure 5 extends along a first direction (e.g., X direction), and covers the corresponding sidewalls of the first isolation structure 3 between the first gate 12 and the second portion 112 of the semiconductor layer 11 along the second direction (e.g., Y direction), the corresponding sidewalls of the first gate dielectric layer 14 along the first direction (e.g., X direction), the corresponding sidewalls of the first isolation structure 3 between the first gate 12 and the third portion 113 along the first direction (e.g., X direction), the corresponding sidewalls of the third portion 113 of the semiconductor layer 11 along the first direction (e.g., X direction), and the corresponding sidewalls of the capacitor 2 along the first direction (e.g., X direction).
  • a first direction e.g., X direction
  • X direction covers the corresponding sidewalls of the first isolation structure 3 between the first gate 12 and the second portion 112 of the semiconductor layer 11 along the second direction (e.g., Y direction)
  • the first isolation structure 3 , the second isolation structure 4 and the third isolation structure 5 described above are used to effectively eliminate the GIDL effect of the transistor 1 , so as to improve the electrical performance and reliability of the transistor 1 .
  • first isolation structure 3, the second isolation structure 4 and the third isolation structure 5 are formed of insulating materials and can be a single-layer structure or a stacked structure.
  • the insulating materials used in the first isolation structure 3, the second isolation structure 4 and the third isolation structure 5 can be the same or different.
  • the aforementioned insulating material can include at least one of silicon oxide, silicon nitride or silicon oxynitride.
  • the capacitor 2 may have a structure in which a first electrode, a dielectric layer, and a second electrode are stacked in sequence.
  • the capacitor 2 is a metal-insulator-metal (MIM) capacitor; that is, the first electrode and the second electrode are both formed of metal materials.
  • the dielectric layer (insulator) may be formed of silicon oxide, silicon nitride, a high-K dielectric material, or a combination thereof.
  • the first electrode of the capacitor 2 is electrically connected to the third portion 113 of the semiconductor layer 11.
  • Some embodiments of the present disclosure also provide a memory as an application device of the memory unit in some of the above embodiments.
  • the memory also has the technical advantages of the above memory unit. Please refer to Figures 5 and 6, the memory includes: at least one memory unit U as in any of the above embodiments, at least one bit line BL, at least one first word line WL1 and at least one second word line WL2.
  • the bit line BL extends along the second direction (e.g., the Y direction) and is electrically connected to the second portion 112 of the semiconductor layer 11 in the memory cell U.
  • the first word line WL1 extends along the third direction (e.g., the Z direction) and is electrically connected to the first gate 12 in the memory cell U.
  • the second word line WL2 extends along the third direction (e.g., the Z direction) and is electrically connected to the second gate 13 in the memory cell U.
  • the third direction (e.g., the Z direction) intersects with the first direction (e.g., the X direction) and the second direction (e.g., the Y direction).
  • the third direction (eg, Z direction) is orthogonal to the first direction (eg, X direction) and the second direction (eg, Y direction).
  • the number of memory units U may be multiple, and two memory units U arranged adjacent to each other in the second direction (e.g., the Y direction) may constitute a repeating unit M.
  • the two memory units U are mirror-symmetrical to each other, and the second portions 112 of the semiconductor layers 11 in the two memory units U are opposite and may be connected to form an integral structure.
  • the center line O-O’ of the two storage units U in the same repeating unit M that are mirror-symmetric extends along the first direction (e.g., the X direction), and may, for example, pass through the geometric center of the third isolation structure 5.
  • the first isolation structures 3 between the first gate 12 and the second portion 112 of the two memory cells U are opposite and connected as an integral structure
  • the third isolation structures 5 of the two memory cells U are opposite and connected as an integral structure. In this way, the two memory cells U in the same repeating unit M can be regarded as sharing the same third isolation structure 5.
  • the number of repeating units M is multiple, and the multiple repeating units M can be arranged in rows along a first direction (for example, the X direction) and arranged in columns along a second direction (for example, the Y direction); wherein the storage units U in two adjacent columns of repeating units M can share the same bit line BL, and the two adjacent columns of repeating units M are symmetrically distributed with the bit line BL as the center.
  • a plurality of repeating units M may be stacked along a third direction (e.g., Z direction) to achieve three-dimensional stacking of memory cells U.
  • the first word line WL1 and the second word line WL2 may be connected to corresponding gates of the memory cells U in their extending directions, respectively.
  • Some embodiments of the present disclosure also provide a method for preparing a memory, which is used to prepare the memory in some of the above embodiments.
  • the preparation method also possesses the technical advantages of the above-mentioned memory.
  • the preparation method of the memory provided by the embodiments of the present disclosure reduces the difficulty of the process, is easy to implement, and is also conducive to improving the production efficiency and production yield of the memory.
  • the method for preparing a memory includes the following steps S100 - S900 .
  • the stack structure includes a plurality of first sacrificial layers and a plurality of second sacrificial layers that are alternately stacked.
  • the semiconductor layer includes a first portion extending along a first direction, and a second portion and a third portion respectively connected to two ends of the first portion and extending along a second direction; the second direction intersects with the first direction.
  • step S300 of forming a semiconductor layer on the inner sidewall of the second sacrificial layer in the first receiving hole includes the following steps S310 - S350 .
  • the method for preparing the memory further includes the following steps S301 and S351 .
  • step S301 before forming a semiconductor material layer on the hole wall of the first receiving hole in step S310 , forming a first dielectric material layer on the hole wall of the first receiving hole.
  • step S310 a semiconductor material layer is formed on a surface of the first dielectric material layer away from the wall of the first receiving hole.
  • the second gate dielectric layer formed in step S351 may be an initial second gate dielectric layer; and after etching to form a second isolation trench in the subsequent step S510 , a second gate dielectric layer of a final structure may be obtained.
  • the method further includes the following steps S311 to S313 .
  • the step S400 of forming a first gate on a side of the first portion away from the inner sidewall of the second sacrificial layer includes the following steps S410 - S430 .
  • the method for preparing the memory further includes the following steps S331 and S352 .
  • step S330 after etching the semiconductor material layer based on the removed area of the first sacrificial layer extending along the second direction to form an initial semiconductor layer, the first insulating material is backfilled in the removed area of the first sacrificial layer extending along the second direction and the etched area of the semiconductor material layer.
  • step S350 the initial semiconductor layer is etched based on the removed area of the first sacrificial layer extending along the first direction, and after the semiconductor layer is formed, the removed area of the first sacrificial layer extending along the first direction and the etched area of the initial semiconductor layer are backfilled with a second insulating material.
  • step S500 the stacked structure on the side of the first portion away from the first gate is etched, and the second gate is formed on the side of the first portion away from the first gate, and the following steps S510 to S540 are also included.
  • the second sacrificial layer and the second insulating material of the first part away from the first gate are etched to form second isolation grooves extending along the second direction and spaced apart in the first direction, and the outer side wall of the corresponding end of the first part and a part of the first insulating material are exposed in the second isolation grooves.
  • step S600 removes the second sacrificial layer located on the side of the second part away from the third part to form a bit line accommodating groove, and also includes: on the side of the second part away from the third part, etching the outer wall of the second sacrificial layer extending along the second direction until the second isolation structure and the outer wall of the second part are exposed to form a bit line accommodating groove.
  • the step S700 of forming the bit line in the bit line receiving groove further includes: filling the bit line receiving groove with a metal material to form the bit line.
  • the second sacrificial layer located on the side of the second part away from the third part is removed in step S600 to form a bit line accommodating groove
  • the step further includes: etching the outer side wall of the second sacrificial layer located on the same side of the second gate and extending along the first direction until the second sacrificial layer between the corresponding second isolation structures and the second sacrificial layer between the corresponding second parts in adjacent columns of memory cells are removed to form a bit line accommodating groove.
  • the step S700 to form a bit line in the bit line accommodating groove also includes: filling a metal material in the bit line accommodating groove to form a bit line shared by adjacent columns of memory cells.
  • step S800 removes the second sacrificial layer located on the side of the third part away from the second part to form a capacitor accommodating groove, and also includes: on the side of the third part away from the second part, etching the outer wall of the second sacrificial layer extending along the second direction until the second isolation structure and the outer wall of the third part are exposed to form a capacitor accommodating groove.
  • the capacitor receiving groove also exposes the third isolation structure.
  • the step S900 of forming a capacitor in the capacitor receiving groove includes the following steps.
  • a stack structure N is formed.
  • the stack structure N includes a plurality of first sacrificial layers L1 and a plurality of second sacrificial layers L2 that are alternately stacked.
  • FIG. 12 only illustrates one stacking structure N as an example.
  • multiple first sacrificial material layers and multiple second sacrificial material layers can be alternately stacked on the substrate (not shown in FIG. 12), and then the multiple first sacrificial material layers and the multiple second sacrificial material layers can be patterned to form a plurality of stacking structures N arranged in an array, so as to prepare corresponding storage units U based on each stacking structure N.
  • the number of stacking layers of the first sacrificial layer L1 and the second sacrificial layer L2 in the stacking structure N can match the storage requirement setting of the storage unit U in the third direction (for example, the Z direction).
  • the alternating stacking of the first sacrificial layer L1 and the second sacrificial layer L2 in the stacking structure N may start with the first sacrificial layer L1 and end with the second sacrificial layer L2.
  • the first sacrificial layer L1 includes, but is not limited to, a silicon oxide layer.
  • the second sacrificial layer L2 includes, but is not limited to, a polysilicon layer.
  • the second sacrificial layer L2 is a heavily doped polysilicon layer, for example, a P-type heavily doped polysilicon layer.
  • the doping concentration of the P-type doping element in the second sacrificial layer L2 may be 1E20/cm 3 to 1E21/cm 3 .
  • the P-type doping element includes, for example, group III elements, such as boron.
  • the second sacrificial layer L2 is a heavily doped polysilicon layer, which is beneficial for increasing the threshold voltage of the transistor 1 after the first sub-gate 131 of the second gate 13 is subsequently formed based on the second sacrificial layer L2.
  • the stack structure N may further include a protective layer L3 covering the top second sacrificial layer L2.
  • the protective layer L3 is, for example, a hard mask layer, including but not limited to a silicon nitride layer.
  • step S200 referring to FIG. 13 , the stack structure N is etched along the stacking direction (ie, the third direction, such as the Z direction) of the first sacrificial layer L1 and the second sacrificial layer L2 to form a first receiving hole H1 .
  • the stacking direction ie, the third direction, such as the Z direction
  • the first receiving hole H1 is used to define the formation position of the semiconductor layer 11 in the memory unit U.
  • the first receiving hole H1 can be used to directly define the formation position of the semiconductor layer 11 in the repeating unit M.
  • the cross-sectional shape of the first receiving hole H1 includes but is not limited to a rectangle.
  • the cross-sectional shape of the first receiving hole H1 refers to the cross-sectional shape of the first receiving hole H1 in the X-Y plane.
  • a semiconductor layer 11 is formed on the inner sidewall of the second sacrificial layer L2 in the first receiving hole H1; the semiconductor layer 11 includes a first portion 111 extending along a first direction (eg, X direction) and a first portion 111 extending along a first direction (eg, X direction).
  • the second part 112 and the third part 113 are respectively connected at both ends and extend along the second direction (for example, the Y direction).
  • the second direction (for example, the Y direction) and the first direction (for example, the X direction) intersect, for example, are orthogonal.
  • step S300 may include steps S301 to S352.
  • step S301 before forming a semiconductor material layer on the hole wall of the first receiving hole H1 in step S310 , a first dielectric material layer 150 is formed on the hole wall of the first receiving hole H1 .
  • the first dielectric material layer 150 includes, but is not limited to, silicon oxide.
  • the first dielectric material layer 150 can be formed only on the sidewall (ie, inner sidewall) of the second sacrificial layer L2 located in the first receiving hole H1.
  • a thermal oxidation process is performed on the inner sidewall of the second sacrificial layer L2 in the first receiving hole H1.
  • the second sacrificial layer L2 is a polysilicon layer
  • the first dielectric material layer 150 can be a polysilicon oxide layer.
  • the first dielectric material layer 150 may be formed by a deposition process to cover the hole wall of the first receiving hole H1.
  • the first dielectric material layer 150 may be formed by materials such as aluminum oxide (Al2O3), zinc oxide (ZnO), zirconium oxide (ZrO2) or hafnium oxide (HfO2).
  • step S310 referring to FIG. 15 , a semiconductor material layer 110 is formed on the hole wall of the first receiving hole H1 .
  • the semiconductor material layer 110 is formed on the surface of the first dielectric material layer 150 away from the hole wall of the first receiving hole H1 .
  • the semiconductor material layer 110 includes, but is not limited to, an IGZO layer.
  • step S311 referring to FIG. 16 , a second dielectric material layer 30 is formed to cover the semiconductor material layer 110 and fill the first receiving hole H1 .
  • the second dielectric material layer 30 includes, but is not limited to, a silicon oxide layer.
  • the top surface of the second dielectric material layer 30 is flush with the top surface of the protection layer L3 in the stacked structure N.
  • step S312 referring to FIG. 17 , the second dielectric material layer 30 and the stacking structure N and the semiconductor material layer 110 located on one side of the second dielectric material layer 30 are etched along the stacking direction of the first sacrificial layer L1 and the second sacrificial layer L2 (i.e., the third direction, such as the Z direction) to form a first isolation groove G1 extending along the first direction (e.g., the X direction), and the remaining second dielectric material layer 30 constitutes an initial first isolation structure 3A.
  • the third direction such as the Z direction
  • the first isolation trench G1 may be used to define a formation position of the third isolation structure 5 between adjacent transistors 1 in the same repeating unit M.
  • step S313 referring to FIG. 18 , a third isolation structure 5 is formed in the first isolation trench G1 .
  • the third isolation structure 5 and the second dielectric material layer 30 are made of different materials.
  • the third isolation structure 5 is formed of silicon nitride material.
  • step S400 may include steps S410 to S430.
  • step S410 please refer to Figure 19, the initial first isolation structure 3A is etched along the stacking direction of the first sacrificial layer L1 and the second sacrificial layer L2 (i.e., the third direction, such as the Z direction) to form the second accommodating hole H2 and the first isolation structure 3 located on the opposite sides of the second accommodating hole H2 in the first direction (e.g., the X direction), and the semiconductor material layer 110 and the third isolation structure 5 located on the opposite sides of the second accommodating hole H2 in the second direction (e.g., the Y direction) are exposed.
  • the third direction such as the Z direction
  • the second receiving hole H2 is used to define the formation positions of the first gate 12 and the first word line WL1 .
  • the cross-sectional shape of the second receiving hole H2 includes but is not limited to a rectangle, a circle or an ellipse, etc.
  • the cross-sectional shape of the second receiving hole H2 refers to the cross-sectional shape of the second receiving hole H2 in the X-Y plane.
  • step S420 referring to FIG. 20 , a first gate dielectric layer 14 is conformally formed on the hole wall of the second receiving hole H2 .
  • the first gate dielectric layer 14 is formed by a deposition process, which includes but is not limited to an atomic layer deposition process.
  • the material of the first gate dielectric layer 14 includes, but is not limited to, silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-K dielectric material, ferroelectric material, antiferroelectric material or a combination thereof.
  • step S430 referring to FIG. 21 , a first gate 12 covering the first gate dielectric layer 14 and filling the second receiving hole H2 and a first word line WL1 correspondingly connected to the first gate 12 are formed.
  • the first gate 12 and the first word line WL1 are formed of a metal material and are an integrated structure.
  • the metal material includes, for example, tungsten or copper.
  • the first gate 12 and the first word line WL1 may also be a stacked structure of metal and metal, or metal and metal compound.
  • the first gate 12 and the first word line WL1 are a stacked structure of titanium nitride and tungsten.
  • step S320 referring to FIG. 22 , the outer sidewall of the first sacrificial layer L1 extending along the second direction (eg, the Y direction) is etched until the semiconductor material layer 110 is exposed.
  • the first sacrificial layer L1 may be etched using a lateral etching process.
  • step S330 referring to FIG. 23, the semiconductor material layer 110 is etched based on the removal area extending along the second direction (e.g., the Y direction) of the first sacrificial layer L1 to remove the semiconductor material layer 110 extending along the second direction (e.g., the Y direction) between adjacent second sacrificial layers L2 to form an initial semiconductor layer 11A.
  • the second direction e.g., the Y direction
  • the semiconductor material layer 110 is etched based on the removal area extending along the second direction (e.g., the Y direction) of the first sacrificial layer L1 to remove the semiconductor material layer 110 extending along the second direction (e.g., the Y direction) between adjacent second sacrificial layers L2 to form an initial semiconductor layer 11A.
  • the first gate dielectric layer 14 extending along the second direction (eg, the Y direction) between adjacent second sacrificial layers L2 may serve as an etching stop layer for the semiconductor material layer 110 .
  • step S331 referring to FIG. 24 , the first insulating material 61 is backfilled in the removed area of the first sacrificial layer L1 extending along the second direction (eg, the Y direction) and the etched area of the semiconductor material layer 110 .
  • the first insulating material 61 is different from the material of the first sacrificial layer L1 .
  • the first insulating material 61 includes, but is not limited to, silicon nitride material.
  • step S340 referring to FIG. 25 , the outer sidewall of the first sacrificial layer L1 extending along the first direction (eg, the X direction) is etched until the initial semiconductor layer 11A is exposed.
  • the first sacrificial layer L1 may be etched using a lateral etching process.
  • each first sacrificial layer L1 in the stacked structure N has been effectively removed without any residue.
  • step S350 referring to FIG. 26 , the initial semiconductor layer 11A is etched based on the removal area extending along the first direction (e.g., the X direction) of the first sacrificial layer L1 to remove the initial semiconductor layer 11A extending along the first direction (e.g., the X direction) between adjacent second sacrificial layers L2, thereby forming semiconductor layers 11 respectively located on the inner side walls of each second sacrificial layer L2.
  • the first direction e.g., the X direction
  • the semiconductor layer 11 of each memory cell in the embodiment of the present disclosure has been prepared.
  • the relevant structure of the semiconductor layer 11 can refer to the relevant records in some of the aforementioned embodiments, and will not be described in detail here.
  • the first dielectric material layer 150 also covers the inner sidewall of the first sacrificial layer L1 in the first receiving hole H1. Accordingly, in step S351, please continue to refer to FIG. 26, while forming the semiconductor layer 11 on the inner sidewall of the second sacrificial layer L2, the first dielectric material layer 150 is etched to form a second gate dielectric layer 15 between the inner sidewall of the second sacrificial layer L2 and the semiconductor layer 11.
  • the etching of the first dielectric material layer 150 on the inner sidewall of the first sacrificial layer L1 can be performed twice to match the etching of the semiconductor material layer 110 and the etching of the initial semiconductor layer 11A.
  • the etching of the first dielectric material layer 150 on the inner sidewall of the first sacrificial layer L1 is performed before the etching of the corresponding regions of the semiconductor material layer 110 and the initial semiconductor layer 11A to expose the semiconductor material layer 110 and the initial semiconductor layer 11A in the corresponding regions.
  • the second gate dielectric layer 15 formed in step S351 may be an initial second gate dielectric layer; and after etching to form a second isolation trench in the subsequent step S510 , a second gate dielectric layer 15 of a final structure may be obtained.
  • step S352 referring to FIG. 27 , the second insulating material 62 is backfilled in the removed area of the first sacrificial layer L1 extending along the first direction (eg, the X direction) and the etched area of the initial semiconductor layer 11A.
  • the second insulating material 62 and the first insulating material 61 are made of different materials.
  • the second insulating material 62 includes, but is not limited to, a silicon oxide material.
  • step S500 referring to FIGS. 28 to 30 , the stacked structure N on the side of the first portion 111 of the semiconductor layer 11 away from the first gate 12 is etched, and the second gate 13 is formed on the side of the first portion 111 away from the first gate 12 .
  • step S500 may include steps S510 to S540.
  • step S510 please refer to Figure 28, along the stacking direction of the first sacrificial layer L1 and the second sacrificial layer L2 (i.e., the third direction, such as the Z direction), the second sacrificial layer L2 and the second insulating material 62 of the first portion 111 in the semiconductor layer 11 away from the first gate 12 are etched to form second isolation grooves G2 extending along the second direction (e.g., the Y direction) and spaced apart in the first direction (e.g., the X direction), and the outer side wall of the corresponding end of the first portion 111 and a portion of the first insulating material 61 are exposed in the second isolation grooves G2.
  • the second direction e.g., the Y direction
  • the first direction e.g., the X direction
  • intervals between adjacent second isolation trenches G2 in the first direction are used to define the formation positions of the second gate 13 and the second word line WL2 .
  • step S520 referring to FIG. 29 , a second isolation structure 4 is formed in the second isolation trench G2 .
  • the material of the second isolation structure 4 is the same as the first insulating material 61 .
  • the material of the second isolation structure 4 includes, but is not limited to, silicon nitride material.
  • step S530 referring to FIG. 30 , the second sacrificial layer L2 and the second insulating material 62 in the interval between adjacent second isolation grooves G2 in the first direction (e.g., the X direction) are etched along the stacking direction of the first sacrificial layer L1 and the second sacrificial layer L2 (i.e., the third direction, such as the Z direction) to form a third accommodating hole H3, and the second isolation structure 4 on opposite sides of the third accommodating hole H3 in the first direction (e.g., the X direction) is exposed, while a portion of the second sacrificial layer L2 in the interval between adjacent second isolation grooves G2 is retained to form a first sub-gate 131.
  • the third direction such as the Z direction
  • the first sub-gate 131 is a polysilicon gate.
  • step S540 referring to FIG. 31, a second sub-grid 132 covering the first sub-grid 131 is formed in the third receiving hole H3, and The second word line WL2 is connected to the second sub-gate 132 .
  • the second gate 13 includes a first sub-gate 131 and a second sub-gate 132 .
  • the second sub-gate 132 and the second word line WL2 are formed of a metal material and are an integrated structure.
  • the metal material includes tungsten or copper, for example.
  • step S600 referring to FIG. 32 , the second sacrificial layer L2 located on a side of the second portion 112 of the semiconductor layer 11 away from the third portion 113 is removed to form a bit line receiving groove G3 .
  • bit line accommodating groove G3 can be formed by etching the outer wall of the second sacrificial layer L2 extending along the second direction (such as the Y direction) on the side of the second portion 112 of the semiconductor layer 11 away from the third portion 113 until the second isolation structure 4 and the outer wall of the second portion 112 are exposed.
  • the second sacrificial layer L2 may be etched using a lateral etching process.
  • step S700 referring to FIG. 33 , a bit line BL is formed in the bit line receiving groove G3 , and the bit line BL is electrically connected to the second portion 112 of the semiconductor layer 11 .
  • the material forming the bit line BL includes, but is not limited to, a silicon-based material, a metal-based material, or a combination thereof.
  • the material of the bit line BL includes polysilicon, metal, metal nitride, metal silicide, or a combination thereof.
  • the bit line BL may be a single-layer structure of tungsten, titanium nitride, or polysilicon, or may be a stacked-layer structure of titanium nitride, tungsten, or the like.
  • bit line BL is formed by filling a metal material, such as tungsten or copper, in the bit line receiving groove G4.
  • a plurality of memory cells U are arranged in a row along a second direction (e.g., the Y direction); wherein two rows of memory cells U may share the same bit line BL and be symmetrically distributed around the bit line BL. Accordingly, the stacking structure N may be as shown in FIG. 34 .
  • the outer wall of the second sacrificial layer L2 located on the same side of the second gate 13 and extending along the first direction (for example, the X direction) is etched until the second sacrificial layer L2 between the corresponding second isolation structures 4 in adjacent columns of storage cells U and the second sacrificial layer L2 between the corresponding second parts 112 are removed, thereby forming a bit line accommodating groove G3.
  • step S800 referring to FIG. 35 , the second sacrificial layer L2 located on the side of the third portion 113 of the semiconductor layer 11 away from the second portion 112 is removed to form a capacitor receiving groove G4 .
  • the capacitor accommodating groove G4 can be formed on the side of the third portion 113 of the semiconductor layer 11 away from the second portion 112 by etching the outer wall of the second sacrificial layer L2 extending along the second direction (such as the Y direction) until the second isolation structure 4 and the outer wall of the third portion 113 are exposed.
  • the second sacrificial layer L2 may be etched using a lateral etching process.
  • the capacitor receiving groove G5 also exposes the third isolation structure 5 .
  • step S900 referring to FIG. 36 , a capacitor 2 is formed in the capacitor receiving groove G4 , and the capacitor 2 is electrically connected to the third portion 113 of the semiconductor layer 11 .
  • the manufacturing process of the capacitor 2 may be different depending on the structure of the matching capacitor 2 .
  • step S900 may include the following steps S910 to S930 .
  • a first electrode 21 is formed to conformally cover the wall of the capacitor receiving groove G4 , so that the first electrode 21 can be in contact with and connected to the third portion 113 of the semiconductor layer 11 .
  • step S920 a dielectric layer 22 is formed to conformally cover the first electrode 21 .
  • the dielectric layer 22 may be formed of silicon oxide, silicon nitride, a high-K dielectric material, or a combination thereof.
  • step S930 a second electrode 23 filling the capacitor receiving groove G4 is formed on the surface of the dielectric layer 22 away from the first electrode 21 .
  • first electrode 21 and the second electrode 23 may be formed of metal materials, respectively. Furthermore, the materials of the first electrode 21 and the second electrode 23 may be the same or different.

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Abstract

本公开涉及一种存储单元、存储器及其制备方法，涉及存储技术领域。所述存储单元包括：晶体管和电容器。晶体管包括：半导体层、第一栅极和第二栅极。其中，半导体层包括沿第一方向延伸的第一部分，以及与第一部分的两端分别连接并沿第二方向延伸的第二部分和第三部分；第二方向和第一方向相交，第二部分背离第三部分的一侧与位线电性连接。第一栅极和第二栅极分别位于第一部分在第二方向上相对的两侧。电容器位于第三部分背离第二部分的一侧，并与第三部分电性连接。

Description

存储单元、存储器及其制备方法
相关申请的交叉引用
本公开要求于2023年06月21日提交中国专利局、申请号为202310750067.6、发明名称为“存储单元、存储器及其制备方法”的中国专利申请的优先权，所述专利申请的全部内容通过引用结合在本公开中。
技术领域
本公开涉及存储技术领域，特别是涉及一种存储单元、存储器及其制备方法。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，其由阵列排布的若干个存储单元所组成。存储单元例如可以采用1T1C架构，即包括一个晶体管和一个电容器。
目前，随着对存储器存储容量要求的不断增加，存储单元开始进行三维空间布置。然而，基于1T1C架构存储单元的可扩展性问题及其工艺复杂的问题，容易在进一步缩小存储单元的尺寸时使得存储单元的电学性能劣化，从而导致难以进一步缩小存储单元的尺寸同时确保存储单元的电学性能。
发明内容
根据一些实施例，本公开实施例提供了一种存储单元、存储器及其制备方法。
根据一些实施例，本公开提供的存储单元，包括：晶体管和电容器。
晶体管包括：半导体层、第一栅极和第二栅极；其中，半导体层包括沿第一方向延伸的第一部分，以及与第一部分的两端分别连接并沿第二方向延伸的第二部分和第三部分；第二方向和第一方向相交，第二部分背离第三部分的一侧与位线电性连接；第一栅极和第二栅极分别位于第一部分在第二方向上相对的两侧。
电容器位于第三部分背离第二部分的一侧，并与第三部分电性连接。
根据一些实施例，第一栅极和第二栅极中的一者包括沿远离第一部分的方向层叠且材料不同的第一子栅和第二子栅。
根据一些实施例，第一子栅为多晶硅栅极。第二子栅以及第一栅极和第二栅极中的另一者均为金属栅极。
根据一些实施例，第二部分和第三部分位于第一部分的同侧。第一栅极位于第一部分、第二部分和第三部分围成的空间内，并与第一字线电性连接。第二栅极位于第一部分沿第二方向背离第二部分和第三部分的一侧，且包括第一子栅和第二子栅。第二子栅与第二字线电性连接。
根据一些实施例，所述存储单元还包括：第一栅介质层和第二栅介质层。第一栅介质层位于第一栅极和第一部分之间。第二栅介质层位于第一子栅和第一部分之间。其中，沿第二方向，第二栅介质层的厚度大于第一栅介质层的厚度。
根据一些实施例，位线沿第二方向延伸。电容器沿第二方向向第二栅极所在一侧凸出于第三部分。存储单元还包括：第一隔离结构、第二隔离结构和第三隔离结构。第一隔离结构位于第一栅极和第二部分之间，以及第一栅极和第三部分之间。第二隔离结构位于第二栅极和位线之间，以及第二栅极和电容器之间。第三隔离结构位于第一栅极、第三部分、电容器以及第一栅极和第三部分之间第一隔离结构的同侧，并与第一栅极和第二部分之间的第一隔离结构接触连接。
根据一些实施例，沿第二方向，第二部分的长度大于第三部分的长度。
根据一些实施例，存储器，包括：至少一个如上任一些实施例所述的存储单元，至少一个位线，至少一个第一字线和至少一个第二字线。位线沿第二方向延伸，并与存储单元中的第二部分对应电性连接。第一字线沿第三方向延伸，并与存储单元中的第一栅极对应电性连接。第二字线沿第三方向延伸，并与存储单元中的第二栅极对应电性连接。其中，第三方向与第一方向、第二方向两两相交。
根据一些实施例，存储单元的数量为多个，且在第二方向上相邻排列的两个存储单元构成一个重复单元。在同一个重复单元中，两个存储单元互为镜像对称，且两个存储单元的第二部分相对且连接为一体结构。
根据一些实施例，存储单元包括：位于第一栅极和第二部分之间以及第一栅极和第三部分之间的第一隔离结构；位于第一栅极、第三部分、电容器以及第一栅极和第三部分之间第一隔离结构的同侧，并与第一栅极和第二部分之间的第一隔离结构接触连接的第三隔离结构。在同一个重复单元中，两个存储单元的位于第一栅极和第二部分之间的第一隔离结构相对且连接为一体结构；两个存储单元的第 三隔离结构相对且连接为一体结构。
根据一些实施例，存储器的制备方法包括如下步骤。
形成堆叠结构，堆叠结构包括交替层叠的多层第一牺牲层和多层第二牺牲层。
沿第一牺牲层和第二牺牲层的层叠方向刻蚀堆叠结构，形成第一容置孔。
于第一容置孔内第二牺牲层的内侧壁上形成半导体层；半导体层包括沿第一方向延伸的第一部分，以及与第一部分的两端分别连接并沿第二方向延伸的第二部分和第三部分；第二方向和第一方向相交。
于第一部分背离第二牺牲层内侧壁的一侧形成第一栅极。
刻蚀第一部分背离第一栅极一侧的堆叠结构，并于第一部分背离第一栅极的一侧形成第二栅极。
去除位于第二部分背离第三部分的一侧的第二牺牲层，形成位线容置槽。
于位线容置槽内形成位线，并使位线与第二部分电性连接。
去除位于第三部分背离第二部分的一侧的第二牺牲层，形成电容器容置槽。
于电容器容置槽内形成电容器，并使电容器与第三部分电性连接。
根据一些实施例，所述于第一容置孔内第二牺牲层的内侧壁上形成半导体层，包括如下步骤。
于第一容置孔的孔壁上形成半导体材料层。
对第一牺牲层沿第二方向延伸的外侧壁进行刻蚀至暴露出半导体材料层。
基于第一牺牲层沿第二方向延伸的去除区域刻蚀半导体材料层，以去除相邻第二牺牲层之间沿第二方向延伸的半导体材料层，形成初始半导体层。
对第一牺牲层沿第一方向延伸的外侧壁进行刻蚀至暴露出初始半导体层。
基于第一牺牲层沿第一方向延伸的去除区域刻蚀初始半导体层，以去除相邻第二牺牲层之间沿第一方向延伸的初始半导体层，形成分别位于各第二牺牲层内侧壁上的半导体层。
根据一些实施例，所述存储器的制备方法，还包括如下步骤。
在第一容置孔的孔壁上形成半导体材料层之前，于第一容置孔的孔壁上形成第一介质材料层；其中，半导体材料层形成于第一介质材料层背离第一容置孔孔壁的表面。
在第二牺牲层的内侧壁上形成半导体层的同时，刻蚀第一介质材料层，以于第二牺牲层的内侧壁和半导体层之间形成第二栅介质层。
根据一些实施例，所述对第一牺牲层沿第二方向延伸的外侧壁进行刻蚀至暴露出半导体材料层之前，所述方法还包括如下步骤。
形成覆盖半导体材料层并填充第一容置孔的第二介质材料层。
沿第一牺牲层和第二牺牲层的层叠方向，刻蚀第二介质材料层以及位于第二介质材料层一侧的堆叠结构和半导体材料层，形成沿第一方向延伸的第一隔离槽，并使剩余的第二介质材料层构成初始第一隔离结构。
于第一隔离槽内形成第三隔离结构。
相应地，所述于第一部分背离第二牺牲层内侧壁的一侧形成第一栅极，包括如下步骤。
沿第一牺牲层和第二牺牲层的层叠方向刻蚀初始第一隔离结构，形成第二容置孔及位于第二容置孔在第一方向上相对两侧的第一隔离结构，并暴露出位于第二容置孔在第二方向上相对两侧的半导体材料层和第三隔离结构。
于第二容置孔的孔壁上保形形成第一栅介质层。
形成覆盖第一栅介质层并填充第二容置孔的第一栅极及与第一栅极对应连接的第一字线。
根据一些实施例，所述存储器的制备方法，还包括如下步骤。
在基于第一牺牲层沿第二方向延伸的去除区域刻蚀半导体材料层，形成初始半导体层之后，于第一牺牲层沿第二方向延伸的去除区域和半导体材料层的刻蚀区域回填第一绝缘材料。
在基于第一牺牲层沿第一方向延伸的去除区域刻蚀初始半导体层，形成半导体层之后，于第一牺牲层沿第一方向延伸的去除区域和初始半导体层的刻蚀区域回填第二绝缘材料。
相应地，所述刻蚀第一部分背离第一栅极一侧的堆叠结构，并于第一部分背离第一栅极的一侧形成第二栅极，还包括如下步骤。
沿第一牺牲层和第二牺牲层的层叠方向，刻蚀第一部分背离第一栅极一侧的第二牺牲层和第二绝缘材料，形成沿第二方向延伸且在第一方向上间隔设置的第二隔离槽，并于第二隔离槽内暴露出第一部分对应端部的外侧壁及部分第一绝缘材料。
于第二隔离槽内形成第二隔离结构。
沿第一牺牲层和第二牺牲层的层叠方向，刻蚀在第一方向上相邻第二隔离槽之间间隔内的第二牺 牲层和第二绝缘材料，形成第三容置孔，并暴露出第三容置孔在第一方向上相对两侧的第二隔离结构，同时保留相邻第二隔离槽之间间隔内的部分第二牺牲层构成第一子栅。
于第三容置孔内形成覆盖第一子栅的第二子栅，以及与第二子栅对应连接的第二字线；其中，第二栅极包括第一子栅和第二子栅。
根据一些实施例，所述去除位于第二部分背离第三部分的一侧的第二牺牲层，形成位线容置槽，还包括：于第二部分背离第三部分的一侧，对第二牺牲层沿第二方向延伸的外侧壁进行刻蚀至暴露出第二隔离结构及第二部分的外侧壁，形成位线容置槽。
相应地，所述于位线容置槽内形成位线，还包括：于位线容置槽内填充金属材料，形成位线。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一些实施例中提供的一种存储单元的结构示意图；
图2为图1所示存储单元中一种晶体管的电性曲线图；
图3为一些实施例中提供的另一种存储单元的结构示意图；
图4为图3所示存储单元的立体结构示意图；
图5为一些实施例中提供的一种存储器的结构示意图；
图6为一些实施例中提供的另一种存储器在X-Y平面内的俯视示意图；
图7为一些实施例中提供的一种存储器的制备方法的流程示意图；
图8为图7所示存储器的制备方法中一种步骤S300的流程示意图；
图9为图7所示存储器的制备方法中另一种步骤S300的流程示意图；
图10为图7所示存储器的制备方法中一种步骤S400的流程示意图；
图11为图7所示存储器的制备方法中一种步骤S500的流程示意图；
图12为一些实施例中提供的一种形成堆叠结构之后所得结构的结构示意图；
图13为一些实施例中提供的一种形成第一容置孔之后所得结构的结构示意图；
图14为一些实施例中提供的一种形成第一介质材料层之后所得结构的结构示意图；
图15为一些实施例中提供的一种形成半导体材料层之后所得结构的结构示意图；
图16为一些实施例中提供的一种形成第二介质材料层之后所得结构的结构示意图；
图17为一些实施例中提供的一种形成第一隔离槽之后所得结构的结构示意图；
图18为一些实施例中提供的一种形成第三隔离结构之后所得结构的结构示意图；
图19为一些实施例中提供的一种形成第二容置孔及第一隔离结构之后所得结构的结构示意图；
图20为一些实施例中提供的一种形成第一栅介质层之后所得结构的结构示意图；
图21为一些实施例中提供的一种形成第一栅极及第一字线之后所得结构的结构示意图；
图22为一些实施例中提供的一种对第一牺牲层沿第二方向延伸的外侧壁进行刻蚀至暴露出半导体材料层后所得结构的结构示意图；
图23为一些实施例中提供的一种形成初始半导体层之后所得结构的结构示意图；
图24为一些实施例中提供的一种回填第一绝缘材料之后所得结构的结构示意图；
图25为一些实施例中提供的一种对第一牺牲层沿第一方向延伸的外侧壁进行刻蚀至暴露出初始半导体层后所得结构的结构示意图；
图26为一些实施例中提供的一种形成半导体层之后所得结构的结构示意图；
图27为一些实施例中提供的一种回填第二绝缘材料之后所得结构的结构示意图；
图28为一些实施例中提供的一种形成第二隔离槽之后所得结构的结构示意图；
图29为一些实施例中提供的一种形成第二隔离结构之后所得结构的结构示意图；
图30为一些实施例中提供的一种形成第三容置孔之后所得结构的结构示意图；
图31为一些实施例中提供的一种形成第二栅极及第二字线之后所得结构的结构示意图；
图32为一些实施例中提供的一种形成位线容置槽之后所得结构的结构示意图；
图33为一些实施例中提供的一种形成位线之后所得结构的结构示意图；
图34为一些实施例中提供的另一种形成位线之后所得结构的结构示意图；
图35为一些实施例中提供的一种形成电容器容置槽之后所得结构的结构示意图；
图36为一些实施例中提供的一种形成电容器之后所得结构的结构示意图；
图37为一些实施例中提供的一种电容器在X-Z平面内的剖面结构示意图。
具体实施方式
为了便于理解本公开，下面将参照相关附图对本公开进行更全面的描述。附图中给出了本公开的首选实施例。但是，本公开可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本公开的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中在本公开的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本公开。
应当明白，当元件或层被称为“在…上”、“与…相邻”或“与…电性连接”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应明白，当术语“组成”和/或“包括”在该说明书中使用时，可以确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。同时，在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本公开的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例，这样可以预期由于例如制造技术和/或容差导致的所示形状的变化。本公开的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造技术导致的形状偏差。因此，图中显示的区实质上是示意性的，它们的形状并不表示器件的区的实际形状，且并不限定本公开的范围。
在目前的DRAM制造工艺中，多采用存储单元6F2排布且埋置字线(Buried Word line)的制造方法。由于在这种方法下进一步的缩小存储单元的尺寸会变得十分困难，因此随着对存储器存储容量要求的不断增加，存储单元开始进行三维空间布置。然而，基于DRAM中存储单元的可扩展性问题及其工艺复杂的问题，容易在进一步缩小存储单元的尺寸时使得存储单元的电学性能劣化，从而导致难以进一步缩小存储单元的尺寸同时确保存储单元的电学性能。
在一些实施例中，请参阅图1中的(a)图和(b)图，其中，图1中的(a)图示意了一种存储单元的立体结构，图1中的(b)图为图1中(a)图所示存储单元的俯视示意图。该存储单元采用了1T1C架构，即包括一个晶体管1和一个电容器2。
示例地，晶体管1包括与字线WL一体连接的栅极01以及依序环绕于栅极01周侧的栅氧层02和半导体层11；其中，半导体层11在第一方向(例如X方向)上相对的两个外侧壁分别与位线BL和电容器2对应连接，字线WL沿竖直方向(例如Z方向)延伸。并且，半导体层11中与位线BL连接的部分为源极，与电容器2连接的部分为漏极。
由上，随着晶体管1特征尺寸的减小，在对图1所示存储单元的晶体管1进行漏电测试之后，可以获取该晶体管1的电性曲线图如图2所示。如图2中所示，该晶体管1采用前述结构会存在有栅致漏极漏电(Gate Induced Drain Leakage，简称GIDL)效应；即：在栅极电压(Gate Voltage)为零或负电压时，若漏极电压为正电压，则容易形成漏电流。示例地，在图2中，电流曲线I11为漏极电压1V时晶体管1关态下的漏极电流曲线，电流曲线I12为漏极电压0.05V时晶体管1关态下的漏极电流曲线，电流曲线I21为漏极电压1V时晶体管1开态下的漏极电流曲线，电流曲线I12为漏极电压0.05V时晶体管1开态下的漏极电流曲线。对比电流曲线I11和电流曲线I12可知，在栅极电压为-0.5V时，漏极电压虽为0.05V但在晶体管1关态的情况下，该漏极电流却有明显增大，约接近于2×10-07A。
由上，本公开实施例提供了一种存储单元和存储器，利于减小存储单元的平面占用面积，以提升存储器的存储密度和存储容量，还利于确保存储单元具有较佳的电学性能及可靠性，以提升存储器的电学性能及可靠性。
请参阅图3和图4，本公开一些实施例提供了一种存储单元，可以应用于存储器，尤其是DRAM中。
如图3和图4中所示，存储单元U包括：晶体管1和电容器2。晶体管1包括：半导体层11、第一栅极12和第二栅极13。其中，半导体层11包括沿第一方向(例如X方向)延伸的第一部分111，以及与第一部分111的两端分别连接并沿第二方向(例如Y方向)延伸的第二部分112和第三部分113。第二方向(例如Y方向)和第一方向(例如X方向)相交，例如正交。并且，第二部分112背离第三部分113的一侧与位线BL电性连接。第一栅极12和第二栅极13分别位于第一部分111在第二方向(例如Y方向)上相对的两侧。电容器2位于第三部分113背离第二部分112的一侧，并与第三部分113电性连接。
此处，半导体层11中的第一部分111能够作为晶体管1的沟道区，以在第一栅极12和第二栅极13的栅极电压控制下形成沟道电流。半导体层11中的第二部分112与位线BL相连接，该第二部分112例如可以为源极。半导体层11中的第三部分113与电容器2相连接，该第三部分113例如可以为漏极。
在本公开实施例中，将晶体管1的半导体层11设置为沿第一方向(例如X方向)延伸的第一部分111，以及与第一部分111的两端分别连接并沿第二方向(例如Y方向)延伸的第二部分112和第三部分113，并使得第二部分112背离第三部分113的一侧与位线BL电性连接，第三部分113背离第二部分112的一侧与电容器2电性连接，第一部分111在第二方向(例如Y方向)上相对的两侧分别设置有第一栅极12和第二栅极13。如此，该晶体管1采用前述结构，不仅利于提高晶体管1所在区域的空间利用率，以有效减小单个存储单元U的平面面积，还有利于通过半导体层11中第二部分112的延伸长度增加晶体管1(例如源极)和位线BL的接触面积，通过半导体层11中第三部分113的延伸长度增加晶体管1(例如漏极)和电容器2的接触面积，以有效降低接触电阻。
并且，本公开实施例中，半导体层11的第一部分111在第二方向(例如Y方向)上相对的两侧分别设置第一栅极12和第二栅极13，还有利于增加半导体层11尤其是第一部分111的厚度，以避免晶体管1漏电，从而提升晶体管1的可靠性。
由上，本公开实施例提供的存储单元U不仅可以占用较小的平面面积，以提升存储器的存储密度和存储容量，还可以确保存储单元U具有较佳的电学性能及可靠性，从而提升存储器的电学性能及可靠性。
可以理解，上述半导体层11中第一部分111、第二部分112和第三部分113可以为一体结构，以同步形成。并且，在一些实施例中，该半导体层11包括但不限于铟镓锌氧化膜层(即Indium Gallium Zinc Oxide，简称IGZO膜层)。如此，基于IGZO膜层绝佳的抗漏电特性、低成本和简单工艺制程，可以相应提高晶体管1的抗漏电特性，以及利于降低存储单元U的生产成本、简化存储单元U的工艺制程以提升生产效率等。
在一些实施例中，请参阅图3和图4，半导体层11的第二部分112和第三部分113位于第一部分111的同侧。如此，半导体层11的第二部分112和第三部分113可以在第一部分111的两端与第一部分111形成连续三边被围的空间。相应地，第一栅极12位于半导体层11的第一部分111、第二部分112和第三部分113围成的空间内，并与第一字线WL1电性连接。第二栅极13位于第一部分111沿第二方向(例如Y方向)背离第二部分112和第三部分113的一侧，且包括第一子栅131和第二子栅132。第二子栅132与第二字线WL2电性连接。
示例地，第一字线WL1可以沿第三方向(例如Z方向)延伸，第三方向(例如Z方向)垂直于第一方向和第二方向的相交平面。第一栅极12和第一字线WL1为一体结构。同理，第二字线WL2也可以沿第三方向(例如Z方向)延伸，且第二栅极13的第二子栅132和第二字线WL2为一体结构。
在一些实施例中，请继续参阅图3和图4，位线BL沿第二方向(例如Y方向)延伸。相应地，沿第二方向(例如Y方向)，半导体层11的第二部分112的长度大于第三部分113的长度。
本公开实施例中，半导体层11的第二部分112与位线BL电性连接，该第二部分112的长度大于第三部分113的长度，利于确保第二部分112可以沿位线BL的延伸方向和位线BL具有更大的接触面积，以进一步降低晶体管1(例如源极)和位线BL之间的接触电阻。
在一些实施例中，位线BL采用导电材料形成，位线BL的材料包括但不限于硅基材料、金属基材料或其组合。例如，位线BL的材料包括多晶硅、金属、金属氮化物、金属硅化物或其组合。例如，位线BL可以为钨或氮化钛或多晶硅的单层结构，或者也可以为氮化钛及钨等的叠层结构。
需要补充的是，在一些实施例中，请参阅图3，第一栅极12和第二栅极13中的一者包括沿远离第一部分111的方向层叠且材料不同的第一子栅131和第二子栅132。图3中以第二栅极13包括第一子栅131和第二子栅132为例进行了示意，但并不仅限于此。
在一些实施例中，第一子栅131为多晶硅栅极。第二子栅132以及第一栅极12和第二栅极13中 的另一者均为金属栅极。
在一些示例中，如图3中所示，第二栅极13包括第一子栅131和第二子栅132。第一栅极12和第二子栅132为金属栅极。
示例地，金属栅极包括但不限于钨或铜等具有优良导电性的单体结构，还可以包括金属与金属、或金属与金属化合物的叠层结构。例如，金属栅极包括氮化钛和钨的叠层结构。
请继续参阅图3和图4，在一些实施例中，存储单元U还包括：第一栅介质层14和第二栅介质层15。第一栅介质层14位于第一栅极12和半导体层11的第一部分111之间。第二栅介质层15位于第二栅极13的第一子栅131和半导体层11的第一部分111之间。其中，沿第二方向(例如Y方向)，第二栅介质层15的厚度大于第一栅介质层14的厚度。
此处，第二栅介质层15和第一栅介质层14的厚度数值可以根据需求匹配设置，但需要以第二栅介质层15的厚度大于第一栅介质层14的厚度为限制条件。
示例地，如图3中所示，第一栅介质层14沿第一栅极12的周向包覆于第一栅极12的侧壁上；也即，第一栅介质层14可以包覆第一栅极12沿第一方向(例如X方向)和第二方向(例如Y方向)分别延伸的各侧壁。
示例地，第二栅介质层15平行于第二栅极13设置，第二栅介质层15与第二栅极13在第一方向(例如X方向)上可以具有相同的长度尺寸。进一步示例地，第二栅介质层15沿第二方向(例如Y方向)的正投影与第二栅极13中的第一子栅131在第二方向(例如Y方向)的正投影基本重合。
示例地，第一栅介质层14和第二栅介质层15的材料相同或不同，均可。
在一些示例中，第一栅介质层14和/或第二栅介质层15的材料包括但不限于氧化硅、氮化硅、金属氧化物、金属氮氧化物、金属硅酸盐、高K介电材料、铁电材料、反铁电材料或其组合。K为介电常数，高K介电材料的介电常数例如大于或等于3.9，例如可以为20。
在一些示例中，高K介电材料可以包括氧化铪(HfO2)、氧化锆(ZrO2)、氧化铝(Al2O3)、氧化镧(La2O3)、氧化钛(TiO2)、氧化钽(Ta2O5)、氧化铌(Nb2O5)或氧化锶钛(SrTiO3)。
示例地，第一栅介质层14和/或第二栅介质层15的材料可以为氧化硅(SiO2)、氧化铝(Al2O3)、氧化锌(ZnO)、氧化锆(ZrO2)或氧化铪(HfO2)等。
示例地，第二栅介质层15的材料为多晶硅氧化物。
上述一些实施例中，第二栅介质层15位于第二栅极13的第一子栅131和半导体层11的第一部分111之间，相较于第一栅介质层14，第二栅介质层15采用较大厚度，可以在一定程度上弥补半导体层11中第一部分111(例如沟道区)的氧空位，尤其是在第二栅介质层15采用多晶硅氧化物形成的实施例中，从而有利于提升晶体管1的可靠性。
在一些实施例中，请继续参阅图3和图4，位线BL沿第二方向(例如Y方向)延伸。电容器2沿第二方向(例如Y方向)向第二栅极13所在一侧凸出于半导体层11的第三部分113。存储单元U还包括：第一隔离结构3、第二隔离结构4和第三隔离结构5。
第一隔离结构3位于第一栅极12和半导体层11的第二部分112之间，以及第一栅极12和半导体层11的第三部分113之间。例如，第一隔离结构3位于第一栅极12和半导体层11的第二部分112之间的部分，以及第一隔离结构3位于第一栅极12和半导体层11的第三部分113之间的部分，均沿第二方向(例如Y方向)延伸，并覆盖对应第一栅介质层14沿第二方向(例如Y方向)的侧壁。
第二隔离结构4位于第二栅极13和位线BL之间，以及第二栅极13和电容器2之间。例如，第二隔离结构4位于第二栅极13和位线BL之间的部分，以及第二隔离结构4位于第二栅极13和电容器2之间的部分，均沿第二方向(例如Y方向)延伸，并覆盖对应第二栅介质层15沿第二方向(例如Y方向)的侧壁。
第三隔离结构5位于第一栅极12、半导体层11的第三部分113、电容器2以及第一栅极12和第三部分113之间第一隔离结构3的同侧，并与第一栅极12和半导体层11的第二部分112之间的第一隔离结构3接触连接。例如，第三隔离结构5沿第一方向(例如X方向)延伸，并覆盖第一栅极12和半导体层11的第二部分112之间第一隔离结构3沿第二方向(例如Y方向)的对应侧壁、第一栅介质层14沿第一方向(例如X方向)的对应侧壁、第一栅极12和第三部分113之间第一隔离结构3沿第一方向(例如X方向)的对应侧壁、半导体层11的第三部分113沿第一方向(例如X方向)的对应侧壁、以及电容器2沿第一方向(例如X方向)的对应侧壁。
本公开实施例中，采用前述的第一隔离结构3、第二隔离结构4和第三隔离结构5，可以有效消除晶体管1的GIDL效应，以提升晶体管1的电学性能及可靠性。
需要补充的是，上述第一隔离结构3、第二隔离结构4和第三隔离结构5，采用绝缘材料形成，可以为单层结构或叠层结构。并且，第一隔离结构3、第二隔离结构4和第三隔离结构5所采用的绝缘材料相同或不同，均可。示例地，前述的绝缘材料可以包括氧化硅、氮化硅或氮氧化硅中的至少一种。
在一些实施例中，电容器2可以采用第一电极、介电层和第二电极依序层叠的结构。例如，电容器2为金属-绝缘体-金属(MIM)电容器；即：第一电极和第二电极均采用金属材料形成。介电层(绝缘体)可以采用氧化硅、氮化硅、高K介电材料或其组合形成。其中，电容器2的第一电极与半导体层11的第三部分113电性连接。
本公开一些实施例还提供了一种存储器，作为上述一些实施例中存储单元的一种应用器件。前述存储单元所具有的技术优势，该存储器也均具备。请参阅图5和图6，该存储器包括：至少一个如上任一些实施例的存储单元U，至少一个位线BL，至少一个第一字线WL1和至少一个第二字线WL2。
如图5和图6中所示，位线BL沿第二方向(例如Y方向)延伸，并与存储单元U中的半导体层11的第二部分112对应电性连接。第一字线WL1沿第三方向(例如Z方向)延伸，并与存储单元U中的第一栅极12对应电性连接。第二字线WL2沿第三方向(例如Z方向)延伸，并与存储单元U中的第二栅极13对应电性连接。其中，第三方向(例如Z方向)与第一方向(例如X方向)、第二方向(例如Y方向)两两相交。
示例地，第三方向(例如Z方向)与第一方向(例如X方向)、第二方向(例如Y方向)两两正交。
在一些实施例中，请继续参阅图5和图6，存储单元U的数量可以为多个，且在第二方向(例如Y方向)上相邻排列的两个存储单元U可以构成一个重复单元M。在同一个重复单元M中，两个存储单元U互为镜像对称，且两个存储单元U中半导体层11的第二部分112相对且可以连接为一体结构。
此处，如图6中所示，同一个重复单元M中两个存储单元U镜像对称的中心线O-O’沿第一方向(例如X方向)延伸，例如可以贯穿第三隔离结构5的几何中心。
在一些实施例中，请继续参阅图5和图6，在同一个重复单元M中，两个存储单元U的位于第一栅极12和第二部分112之间的第一隔离结构3相对且连接为一体结构，两个存储单元U的第三隔离结构5相对且连接为一体结构。如此，同一个重复单元M中的两个存储单元U可以视为共用同一个第三隔离结构5。
在一些实施例中，请参阅图6，重复单元M的数量为多个，且多个重复单元M可以沿第一方向(例如X方向)排布呈行，沿第二方向(例如Y方向)排布呈列；其中，相邻两列重复单元M中的各存储单元U可以共用同一个位线BL，且相邻两列重复单元M以位线BL为中心对称分布。
此外，请参阅图5，在一些实施例中，多个重复单元M还可以沿第三方向(例如Z方向堆叠)，以实现存储单元U的三维堆叠。如此，第一字线WL1和第二字线WL2可以分别连接位于其延伸方向上存储单元U的对应栅极。
本公开一些实施例还提供了一种存储器的制备方法，用于制备上述一些实施例中的存储器。前述存储器所具有的技术优势，该制备方法也均具备。并且，本公开实施例提供的存储器的制备方法降低了工艺制程的难度，易于实施，还利于提升存储器的生产效率及生产良率。
请参阅图7，存储器的制备方法包括如下步骤S100～S900。
S100，形成堆叠结构，堆叠结构包括交替层叠的多层第一牺牲层和多层第二牺牲层。
S200，沿第一牺牲层和第二牺牲层的层叠方向刻蚀堆叠结构，形成第一容置孔。
S300，于第一容置孔内第二牺牲层的内侧壁上形成半导体层；半导体层包括沿第一方向延伸的第一部分，以及与第一部分的两端分别连接并沿第二方向延伸的第二部分和第三部分；第二方向和第一方向相交。
S400，于第一部分背离第二牺牲层内侧壁的一侧形成第一栅极。
S500，刻蚀第一部分背离第一栅极一侧的堆叠结构，并于第一部分背离第一栅极的一侧形成第二栅极。
S600，去除位于第二部分背离第三部分的一侧的第二牺牲层，形成位线容置槽。
S700，于位线容置槽内形成位线，并使位线与第二部分电性连接。
S800，去除位于第三部分背离第二部分的一侧的第二牺牲层，形成电容器容置槽。
S900，于电容器容置槽内形成电容器，并使电容器与第三部分电性连接。
在一些实施例中，请参阅图8，步骤S300中于第一容置孔内第二牺牲层的内侧壁上形成半导体层，包括如下步骤S310～S350。
S310，于第一容置孔的孔壁上形成半导体材料层。
S320，对第一牺牲层沿第二方向延伸的外侧壁进行刻蚀至暴露出半导体材料层。
S330，基于第一牺牲层沿第二方向延伸的去除区域刻蚀半导体材料层，以去除相邻第二牺牲层之间沿第二方向延伸的半导体材料层，形成初始半导体层。
S340，对第一牺牲层沿第一方向延伸的外侧壁进行刻蚀至暴露出初始半导体层。
S350，基于第一牺牲层沿第一方向延伸的去除区域刻蚀初始半导体层，以去除相邻第二牺牲层之间沿第一方向延伸的初始半导体层，形成分别位于各第二牺牲层内侧壁上的半导体层。
在一些实施例中，请参阅图9，所述存储器的制备方法，还包括如下步骤S301和S351。
S301，在步骤S310于第一容置孔的孔壁上形成半导体材料层之前，于第一容置孔的孔壁上形成第一介质材料层。
相应地，步骤S310中，半导体材料层形成于第一介质材料层背离第一容置孔孔壁的表面。
S351，在第二牺牲层的内侧壁上形成半导体层的同时，刻蚀第一介质材料层，以于第二牺牲层的内侧壁和半导体层之间形成第二栅介质层。
在一些示例中，步骤S351中形成的第二栅介质层可以为初始第二栅介质层；并且，在后续步骤S510中刻蚀形成第二隔离槽之后，可以获得最终结构的第二栅介质层。
在一些实施例中，请继续参阅图9，在执行步骤S320对第一牺牲层沿第二方向延伸的外侧壁进行刻蚀至暴露出半导体材料层之前，所述方法还包括如下步骤S311～S313。
S311，形成覆盖半导体材料层并填充第一容置孔的第二介质材料层。
S312，沿第一牺牲层和第二牺牲层的层叠方向，刻蚀第二介质材料层以及位于第二介质材料层一侧的堆叠结构和半导体材料层，形成沿第一方向延伸的第一隔离槽，并使剩余的第二介质材料层构成初始第一隔离结构。
S313，于第一隔离槽内形成第三隔离结构。
相应地，请参阅图10，步骤S400中于第一部分背离第二牺牲层内侧壁的一侧形成第一栅极，包括如下步骤S410～S430。
S410，沿第一牺牲层和第二牺牲层的层叠方向刻蚀初始第一隔离结构，形成第二容置孔及位于第二容置孔在第一方向上相对两侧的第一隔离结构，并暴露出位于第二容置孔在第二方向上相对两侧的半导体材料层和第三隔离结构。
S420，于第二容置孔的孔壁上保形形成第一栅介质层。
S430，形成覆盖第一栅介质层并填充第二容置孔的第一栅极及与第一栅极对应连接的第一字线。
在一些实施例中，请继续参阅图9，所述存储器的制备方法，还包括如下步骤S331和S352。
S331，在步骤S330基于第一牺牲层沿第二方向延伸的去除区域刻蚀半导体材料层，形成初始半导体层之后，于第一牺牲层沿第二方向延伸的去除区域和半导体材料层的刻蚀区域回填第一绝缘材料。
S352，在步骤S350基于第一牺牲层沿第一方向延伸的去除区域刻蚀初始半导体层，形成半导体层之后，于第一牺牲层沿第一方向延伸的去除区域和初始半导体层的刻蚀区域回填第二绝缘材料。
相应地，请参阅图11，步骤S500中刻蚀第一部分背离第一栅极一侧的堆叠结构，并于第一部分背离第一栅极的一侧形成第二栅极，还包括如下步骤S510～S540。
S510，沿第一牺牲层和第二牺牲层的层叠方向，刻蚀第一部分背离第一栅极一侧的第二牺牲层和第二绝缘材料，形成沿第二方向延伸且在第一方向上间隔设置的第二隔离槽，并于第二隔离槽内暴露出第一部分对应端部的外侧壁及部分第一绝缘材料。
S520，于第二隔离槽内形成第二隔离结构。
S530，沿第一牺牲层和第二牺牲层的层叠方向，刻蚀在第一方向上相邻第二隔离槽之间间隔内的第二牺牲层和第二绝缘材料，形成第三容置孔，并暴露出第三容置孔在第一方向上相对两侧的第二隔离结构，同时保留相邻第二隔离槽之间间隔内的部分第二牺牲层构成第一子栅。
S540，于第三容置孔内形成覆盖第一子栅的第二子栅，以及与第二子栅对应连接的第二字线；其中，第二栅极包括第一子栅和第二子栅。
在一些实施例中，步骤S600中去除位于第二部分背离第三部分的一侧的第二牺牲层，形成位线容置槽，还包括：于第二部分背离第三部分的一侧，对第二牺牲层沿第二方向延伸的外侧壁进行刻蚀至暴露出第二隔离结构及第二部分的外侧壁，形成位线容置槽。
相应地，步骤S700中于位线容置槽内形成位线，还包括：于位线容置槽内填充金属材料，形成位线。
进一步地，在一些实施例，步骤S600中去除位于第二部分背离第三部分的一侧的第二牺牲层，形成位线容置槽，还包括：对该第二牺牲层位于第二栅极同侧并沿第一方向延伸的外侧壁进行刻蚀，直至相邻列存储单元中对应第二隔离结构之间的第二牺牲层和对应第二部分之间的第二牺牲层均被去除，形成位线容置槽。相应地，步骤S700中于位线容置槽内形成位线，还包括：于位线容置槽内填充金属材料，形成相邻列存储单元共用的位线。
在一些实施例中，步骤S800中去除位于第三部分背离第二部分的一侧的第二牺牲层，形成电容器容置槽，还包括：于第三部分背离第二部分的一侧，刻蚀第二牺牲层沿第二方向延伸的外侧壁直至暴露出第二隔离结构及第三部分的外侧壁，形成电容器容置槽。
此处，在形成有第三隔离结构的实施例中，电容器容置槽还暴露出第三隔离结构。
示例地，步骤S900中于电容器容置槽内形成电容器，包括如下步骤。
S910，形成保形覆盖电容器容置槽槽壁的第一电极。
S920，形成保形覆盖第一电极的介电层。
S930，于介电层背离第一电极的表面形成填充电容器容置槽的第二电极。
应该理解的是，虽然上述图7～图11的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图7～图11中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
为了更清楚的说明上述一些实施例中存储器的制备方法，以下请结合图12至图37理解本公开的一些实施例。
在步骤S100中，请参阅图12，形成堆叠结构N，堆叠结构N包括交替层叠的多层第一牺牲层L1和多层第二牺牲层L2。
此处，可以理解，图12中仅以一个堆叠结构N为例进行了示意。该堆叠结构N在形成时，可以先于衬底(图12中未示出)上交替层叠的多层第一牺牲材料层和多层第二牺牲材料层，然后将多层第一牺牲材料层和多层第二牺牲材料层图案化，以形成呈阵列排布的多个堆叠结构N，以基于各堆叠结构N分别制备获得对应的存储单元U。并且，堆叠结构N中第一牺牲层L1和第二牺牲层L2的堆叠层数，可以匹配存储单元U在第三方向(例如Z方向)上的存储需求设置。
示例地，堆叠结构N中第一牺牲层L1和第二牺牲层L2的交替层叠，可以以第一牺牲层L1开始，以第二牺牲层L2结束。但也并不仅限于此，例如以第二牺牲层L2开始，以第一牺牲层L1结束；或者，以第一牺牲层L1开始，以第一牺牲层L1结束等；均是允许地。
在一些示例中，第一牺牲层L1包括但不限于氧化硅层。
在一些示例中，第二牺牲层L2包括但不限于多晶硅层。
进一步示例地，第二牺牲层L2为重掺杂多晶硅层，例如为P型重掺杂多晶硅层。第二牺牲层L2中P型掺杂元素的掺杂浓度可以为1E20/cm3～1E21/cm3。P型掺杂元素例如包括III族元素，比如硼元素。
此处，第二牺牲层L2采用重掺杂多晶硅层，有利于后续在基于第二牺牲层L2形成第二栅极13的第一子栅131之后，提升晶体管1的阈值电压。
在一些示例中，以堆叠结构N中第一牺牲层L1为开始层，第二牺牲层L2为结束层为例，堆叠结构N还可以包括覆盖顶层第二牺牲层L2的保护层L3。保护层L3例如为硬掩膜层，包括但不限于氮化硅层。
在步骤S200中，请参阅图13，沿第一牺牲层L1和第二牺牲层L2的层叠方向(即第三方向，例如Z方向)刻蚀堆叠结构N，形成第一容置孔H1。
此处，第一容置孔H1用于定义存储单元U中半导体层11的形成位置。在同一重复单元M中半导体层11的第二部分112相对且为一体结构的示例中，第一容置孔H1可以用于直接定义重复单元M中半导体层11的形成位置。
示例地，第一容置孔H1的横截面形状包括但不限于矩形。第一容置孔H1的横截面是指第一容置孔H1在X-Y平面内的截面。
在步骤S300中，请参阅图3及图14～图27，于第一容置孔H1内第二牺牲层L2的内侧壁上形成半导体层11；半导体层11包括沿第一方向(例如X方向)延伸的第一部分111，以及与第一部分111 的两端分别连接并沿第二方向(例如Y方向)延伸的第二部分112和第三部分113。其中，第二方向(例如Y方向)和第一方向(例如X方向)相交，例如正交。
在一些示例中，步骤S300可以包括步骤S301～S352。
在步骤S301中，请参阅图14，在步骤S310于第一容置孔H1的孔壁上形成半导体材料层之前，于第一容置孔H的孔壁上形成第一介质材料层150。
示例地，第一介质材料层150包括但不限于氧化硅。
此处，可以理解，在第一牺牲层L1为氧化硅层的实施例中，第一介质材料层150可以仅形成于第二牺牲层L2位于第一容置孔H1内的侧壁(即内侧壁)上。
示例地，对第一容置孔H1内第二牺牲层L2的内侧壁执行热氧化工艺。第二牺牲层L2为多晶硅层，该第一介质材料层150对应可以为多晶硅氧化物层。
在另一些示例中，第一介质材料层150可以采用沉积工艺形成，以覆盖第一容置孔H1的孔壁。第一介质材料层150可以采用氧化铝(Al2O3)、氧化锌(ZnO)、氧化锆(ZrO2)或氧化铪(HfO2)等材料形成。
在步骤S310中，请参阅图15，于第一容置孔H1的孔壁上形成半导体材料层110。
在前述于第一容置孔H1的孔壁上形成第一介质材料层150之后，半导体材料层110形成于第一介质材料层150背离第一容置孔H1孔壁的表面。
示例地，半导体材料层110包括但不限于IGZO层。
在步骤S311中，请参阅图16，形成覆盖半导体材料层110并填充第一容置孔H1的第二介质材料层30。
示例地，第二介质材料层30包括但不限于氧化硅层。
示例地，第二介质材料层30的顶面与堆叠结构N中保护层L3的顶面平齐。
在步骤S312中，请参阅图17，沿第一牺牲层L1和第二牺牲层L2的层叠方向(即第三方向，例如Z方向)，刻蚀第二介质材料层30以及位于第二介质材料层30一侧的堆叠结构N和半导体材料层110，形成沿第一方向(例如X方向)延伸的第一隔离槽G1，并使剩余的第二介质材料层30构成初始第一隔离结构3A。
此处，第一隔离槽G1可以用于定义同一重复单元M中相邻晶体管1之间第三隔离结构5的形成位置。
在步骤S313中，请参阅图18，于第一隔离槽G1内形成第三隔离结构5。
示例地，第三隔离结构5和第二介质材料层30的材料不同。
示例地，第三隔离结构5采用氮化硅材料形成。
在步骤S400中，请参阅图19～图21，步骤S400可以包括步骤S410～S430。
在步骤S410中，请参阅图19，沿第一牺牲层L1和第二牺牲层L2的层叠方向(即第三方向，例如Z方向)刻蚀初始第一隔离结构3A，形成第二容置孔H2及位于第二容置孔H2在第一方向(例如X方向)上相对两侧的第一隔离结构3，并暴露出位于第二容置孔H2在第二方向(例如Y方向)上相对两侧的半导体材料层110和第三隔离结构5。
此处，第二容置孔H2用于定义第一栅极12及第一字线WL1的形成位置。
示例地，第二容置孔H2的横截面形状包括但不限于矩形、圆形或椭圆形等。第二容置孔H2的横截面是指第二容置孔H2在X-Y平面内的截面。
在步骤S420中，请参阅图20，于第二容置孔H2的孔壁上保形形成第一栅介质层14。
示例地，第一栅介质层14采用沉积工艺形成，该沉积工艺包括但不限于原子层沉积工艺。
示例地，第一栅介质层14的材料包括但不限于氧化硅、氮化硅、金属氧化物、金属氮氧化物、金属硅酸盐、高K介电材料、铁电材料、反铁电材料或其组合。
在步骤S430中，请参阅图21，形成覆盖第一栅介质层14并填充第二容置孔H2的第一栅极12及与第一栅极12对应连接的第一字线WL1。
示例地，第一栅极12及第一字线WL1采用金属材料形成，并为一体结构。该金属材料例如包括钨或铜。
示例地，第一栅极12及第一字线WL1还可以为金属与金属、或金属与金属化合物的叠层结构。例如，第一栅极12及第一字线WL1采用了氮化钛和钨的叠层结构。
在步骤S320中，请参阅图22，对第一牺牲层L1沿第二方向(例如Y方向)延伸的外侧壁进行刻蚀至暴露出半导体材料层110。
示例地，第一牺牲层L1可以采用横向刻蚀工艺进行刻蚀。
在步骤S330中，请参阅图23，基于第一牺牲层L1沿第二方向(例如Y方向)延伸的去除区域刻蚀半导体材料层110，以去除相邻第二牺牲层L2之间沿第二方向(例如Y方向)延伸的半导体材料层110，形成初始半导体层11A。
此处，相邻第二牺牲层L2之间沿第二方向(例如Y方向)延伸的第一栅介质层14可以作为半导体材料层110的刻蚀阻挡层。
在步骤S331中，请参阅图24，于第一牺牲层L1沿第二方向(例如Y方向)延伸的去除区域和半导体材料层110的刻蚀区域回填第一绝缘材料61。
示例地，第一绝缘材料61与第一牺牲层L1的材料不同。
示例地，第一绝缘材料61包括但不限于氮化硅材料。
在步骤S340中，请参阅图25，对第一牺牲层L1沿第一方向(例如X方向)延伸的外侧壁进行刻蚀至暴露出初始半导体层11A。
示例地，第一牺牲层L1可以采用横向刻蚀工艺进行刻蚀。
可以理解，在执行步骤S340之后，堆叠结构N中的各第一牺牲层L1均已被有效去除，而无残留。
在步骤S350中，请参阅图26，基于第一牺牲层L1沿第一方向(例如X方向)延伸的去除区域刻蚀初始半导体层11A，以去除相邻第二牺牲层L2之间沿第一方向(例如X方向)延伸的初始半导体层11A，形成分别位于各第二牺牲层L2内侧壁上的半导体层11。
至此，本公开实施例中各存储单元的半导体层11已制备完成，该半导体层11的相关结构可参见前述一些实施例中的相关记载，此处不再详述。
在一些实施例中，第一介质材料层150还覆盖于第一容置孔H1内第一牺牲层L1的内侧壁。相应的，在步骤S351中，请继续参阅图26，在第二牺牲层L2的内侧壁上形成半导体层11的同时，刻蚀第一介质材料层150，以于第二牺牲层L2的内侧壁和半导体层11之间形成第二栅介质层15。
此处，对第一牺牲层L1内侧壁上第一介质材料层150的刻蚀，可以匹配半导体材料层110的刻蚀及初始半导体层11A的刻蚀分两次进行。并且，对第一牺牲层L1内侧壁上第一介质材料层150的刻蚀，先于半导体材料层110及初始半导体层11A对应区域刻蚀进行，以暴露出对应区域的半导体材料层110及初始半导体层11A。
在一些示例中，步骤S351中形成的第二栅介质层15可以为初始第二栅介质层；并且，在后续步骤S510中刻蚀形成第二隔离槽之后，可以获得最终结构的第二栅介质层15。
在步骤S352中，请参阅图27，于第一牺牲层L1沿第一方向(例如X方向)延伸的去除区域和初始半导体层11A的刻蚀区域回填第二绝缘材料62。
示例地，第二绝缘材料62和第一绝缘材料61的材料不同。
示例地，第二绝缘材料62包括但不限于氧化硅材料。
在步骤S500中，请参阅图28～图30，刻蚀半导体层11中第一部分111背离第一栅极12一侧的堆叠结构N，并于该第一部分111背离第一栅极12的一侧形成第二栅极13。
在一些示例中，步骤S500可以包括步骤S510～S540。
在步骤S510中，请参阅图28，沿第一牺牲层L1和第二牺牲层L2的层叠方向(即第三方向，例如Z方向)，刻蚀半导体层11中第一部分111背离第一栅极12一侧的第二牺牲层L2和第二绝缘材料62，形成沿第二方向(例如Y方向)延伸且在第一方向(例如X方向)上间隔设置的第二隔离槽G2，并于第二隔离槽G2内暴露出第一部分111对应端部的外侧壁及部分第一绝缘材料61。
此处，在第一方向(例如X方向)上相邻第二隔离槽G2之间的间隔用于定义第二栅极13及第二字线WL2的形成位置。
在步骤S520中，请参阅图29，于第二隔离槽G2内形成第二隔离结构4。
示例地，第二隔离结构4的材料与第一绝缘材料61相同。
示例地，第二隔离结构4的材料包括但不限于氮化硅材料。
在步骤S530中，请参阅图30，沿第一牺牲层L1和第二牺牲层L2的层叠方向(即第三方向，例如Z方向)，刻蚀在第一方向(例如X方向)上相邻第二隔离槽G2之间间隔内的第二牺牲层L2和第二绝缘材料62，形成第三容置孔H3，并暴露出第三容置孔H3在第一方向(例如X方向)上相对两侧的第二隔离结构4，同时保留相邻第二隔离槽G2之间间隔内的部分第二牺牲层L2构成第一子栅131。
示例地，第一子栅131为多晶硅栅极。
在步骤S540中，请参阅图31，于第三容置孔H3内形成覆盖第一子栅131的第二子栅132，以及 与第二子栅132对应连接的第二字线WL2。
如此，第二栅极13包括第一子栅131和第二子栅132。
示例地，第二子栅132及第二字线WL2采用金属材料形成，并为一体结构。该金属材料例如包括钨或铜。
在步骤S600中，请参阅图32，去除位于半导体层11的第二部分112背离第三部分113的一侧的第二牺牲层L2，形成位线容置槽G3。
此处，位线容置槽G3可以于半导体层11的第二部分112背离第三部分113的一侧，对第二牺牲层L2沿第二方向(例如Y方向)延伸的外侧壁进行刻蚀至暴露出第二隔离结构4及第二部分112的外侧壁而形成。
示例地，第二牺牲层L2可以采用横向刻蚀工艺进行刻蚀。
在步骤S700中，请参阅图33，于位线容置槽G3内形成位线BL，并使位线BL与半导体层11的第二部分112电性连接。
示例地，位线BL的形成材料包括但不限于硅基材料、金属基材料或其组合。例如，位线BL的材料包括多晶硅、金属、金属氮化物、金属硅化物或其组合。例如，位线BL可以为钨或氮化钛或多晶硅的单层结构，或者也可以为氮化钛及钨等的叠层结构。
示例地，位线BL于位线容置槽G4内填充金属材料形成，例如钨或铜。
值得一提的是，在一些实施例中，请参阅图6及图34，多个存储单元U沿第二方向(例如Y方向)排布呈列；其中，两列存储单元U可以共用同一个位线BL，并以位线BL为中心对称分布。相应地，堆叠结构N可以如图34中所示。
基于此，前述步骤S600在具体执行时，可以采用如下方式：对第二牺牲层L2位于第二栅极13同侧并沿第一方向(例如X方向)延伸的外侧壁进行刻蚀，直至相邻列存储单元U中对应第二隔离结构4之间的第二牺牲层L2和对应第二部分112之间的第二牺牲层L2均被去除，从而形成位线容置槽G3。
在步骤S800中，请参阅图35，去除位于半导体层11的第三部分113背离第二部分112一侧的第二牺牲层L2，形成电容器容置槽G4。
此处，电容器容置槽G4可以于半导体层11的第三部分113背离第二部分112的一侧，刻蚀第二牺牲层L2沿第二方向(例如Y方向)延伸的外侧壁直至暴露出第二隔离结构4及第三部分113的外侧壁形成。
示例地，第二牺牲层L2可以采用横向刻蚀工艺进行刻蚀。
此外，在形成有第三隔离结构5的实施例中，电容器容置槽G5还暴露出第三隔离结构5。
在步骤S900中，请参阅图36，于电容器容置槽G4内形成电容器2，并使电容器2与半导体层11的第三部分113电性连接。
可以理解，匹配电容器2结构的不同，电容器2的制备工艺可以不同。
在一些实施例中，电容器2的结构如图37所示，包括层叠设置的第一电极21、介电层22和第二电极23。相应地，步骤S900可以包括如下步骤S910～S930。
在步骤S910中，形成保形覆盖电容器容置槽G4槽壁的第一电极21，以使得第一电极21可以与半导体层11的第三部分113接触连接。
在步骤S920中，形成保形覆盖第一电极21的介电层22。
示例地，介电层22可以采用氧化硅、氮化硅、高K介电材料或其组合形成。
在步骤S930中，于介电层22背离第一电极21的表面形成填充电容器容置槽G4的第二电极23。
示例地，上述第一电极21和第二电极23可以分别采用金属材料形成。并且，第一电极21和第二电极23的材料相同或不同，均可。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上实施例仅表达了本公开的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本公开构思的前提下，还可以做出若干变形和改进，这些都属于本公开的保护范围。因此，本公开专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种存储单元，包括：
    晶体管(1)，包括：半导体层(11)、第一栅极(12)和第二栅极(13)；所述半导体层(11)包括沿第一方向延伸的第一部分(111)，以及与所述第一部分(111)的两端分别连接并沿第二方向延伸的第二部分(112)和第三部分(113)；所述第二方向和所述第一方向相交，所述第二部分(112)背离所述第三部分(113)的一侧与位线(BL)电性连接；所述第一栅极(12)和所述第二栅极(13)分别位于所述第一部分(111)在所述第二方向上相对的两侧；
    电容器(2)，位于所述第三部分(113)背离所述第二部分(112)的一侧，并与所述第三部分(113)电性连接；
    其中，所述第一栅极(12)和所述第二栅极(13)中的一者包括沿远离所述第一部分(111)的方向层叠且材料不同的第一子栅(131)和第二子栅(132)。
  2. 根据权利要求1所述的存储单元，其中，所述第一子栅(131)为多晶硅栅极；
    所述第二子栅(132)以及所述第一栅极(12)和所述第二栅极(13)中的另一者均为金属栅极。
  3. 根据权利要求1或2所述的存储单元，其中，
    所述第二部分(112)和所述第三部分(113)位于所述第一部分(111)的同侧；
    所述第一栅极(12)位于所述第一部分(111)、所述第二部分(112)和所述第三部分(113)围成的空间内，并与第一字线(WL1)电性连接；
    所述第二栅极(13)位于所述第一部分(111)沿所述第二方向背离所述第二部分(112)和所述第三部分(113)的一侧，且包括所述第一子栅(131)和所述第二子栅(132)；所述第二子栅(131)与第二字线(WL2)电性连接。
  4. 根据权利要求3所述的存储单元，其中，还包括：
    第一栅介质层(14)，位于所述第一栅极(12)和所述第一部分(111)之间；
    第二栅介质层(15)，位于所述第一子栅(131)和所述第一部分(111)之间；
    其中，沿所述第二方向，所述第二栅介质层(15)的厚度大于所述第一栅介质层(14)的厚度。
  5. 根据权利要求3所述的存储单元，其中，所述位线(BL)沿所述第二方向延伸；所述电容器(2)沿所述第二方向向所述第二栅极(13)所在一侧凸出于所述第三部分(113)；
    所述存储单元还包括：
    第一隔离结构(3)，位于所述第一栅极(12)和所述第二部分(112)之间，以及所述第一栅极(12)和所述第三部分(113)之间；
    第二隔离结构(4)，位于所述第二栅极(13)和所述位线(BL)之间，以及所述第二栅极(13)和所述电容器(2)之间；
    第三隔离结构(5)，位于所述第一栅极(12)、所述第三部分(113)、所述电容器(2)以及所述第一栅极(12)和所述第三部分(113)之间所述第一隔离结构(3)的同侧，并与所述第一栅极(12)和所述第二部分(112)之间的所述第一隔离结构(3)接触连接。
  6. 根据权利要求1所述的存储单元，其中，沿所述第二方向，所述第二部分(112)的长度大于所述第三部分(113)的长度。
  7. 一种存储器，包括：
    至少一个如权利要求1～6中任一项所述的存储单元；
    至少一个位线(BL)；所述位线(BL)沿所述第二方向延伸，并与所述存储单元中的所述第二部分(112)对应电性连接；
    至少一个第一字线(WL1)；所述第一字线(WL1)沿第三方向延伸，并与所述存储单元中的所述第一栅极(12)对应电性连接；
    至少一个第二字线(WL2)；所述第二字线(WL2)沿所述第三方向延伸，并与所述存储单元中的所述第二栅极(13)对应电性连接；
    其中，所述第三方向与所述第一方向、所述第二方向两两相交。
  8. 根据权利要求7所述的存储器，其中，所述存储单元的数量为多个，且在所述第二方向上相邻排列的两个所述存储单元构成一个重复单元(M)；
    在同一个所述重复单元(M)中，两个所述存储单元互为镜像对称，且两个所述存储单元的所述第二部分(112)相对且连接为一体结构。
  9. 根据权利要求8所述的存储器，其中，所述存储单元包括：位于所述第一栅极(12)和所述第二 部分(112)之间以及所述第一栅极(12)和所述第三部分(113)之间的第一隔离结构(3)；位于所述第一栅极(12)、所述第三部分(113)、所述电容器(2)以及所述第一栅极(12)和所述第三部分(113)之间所述第一隔离结构(3)的同侧，并与所述第一栅极(12)和所述第二部分(112)之间的所述第一隔离结构(3)接触连接的第三隔离结构(5)；
    在同一个所述重复单元(M)中，两个所述存储单元的位于所述第一栅极(12)和所述第二部分(112)之间的所述第一隔离结构(3)相对且连接为一体结构；两个所述存储单元的所述第三隔离结构(5)相对且连接为一体结构。
  10. 一种存储器的制备方法，包括：
    形成堆叠结构(N)，所述堆叠结构(N)包括交替层叠的多层第一牺牲层(L1)和多层第二牺牲层(L2)；
    沿所述第一牺牲层(L1)和所述第二牺牲层(L2)的层叠方向刻蚀所述堆叠结构(N)，形成第一容置孔(H1)；
    于所述第一容置孔(H1)内所述第二牺牲层(L2)的内侧壁上形成半导体层(11)；所述半导体层(11)包括沿第一方向延伸的第一部分(111)，以及与所述第一部分(111)的两端分别连接并沿第二方向延伸的第二部分(112)和第三部分(113)；所述第二方向和所述第一方向相交；
    于所述第一部分(111)背离所述第二牺牲层(L2)内侧壁的一侧形成第一栅极(12)；
    刻蚀所述第一部分(111)背离所述第一栅极(12)一侧的所述堆叠结构(N)，并于所述第一部分(111)背离所述第一栅极(12)的一侧形成第二栅极(13)；
    去除位于所述第二部分(112)背离所述第三部分(113)的一侧的所述第二牺牲层(L2)，形成位线容置槽(G3)；
    于所述位线容置槽(G3)内形成位线(BL)，并使所述位线(BL)与所述第二部分(112)电性连接；
    去除位于所述第三部分(113)背离所述第二部分(112)的一侧的所述第二牺牲层(L2)，形成电容器容置槽(G4)；
    于所述电容器容置槽(G4)内形成电容器(2)，并使所述电容器(2)与所述第三部分(113)电性连接。
  11. 根据权利要求10所述的存储器的制备方法，其中，所述于所述第一容置孔(H1)内所述第二牺牲层(L2)的内侧壁上形成半导体层(11)，包括：
    于所述第一容置孔(H1)的孔壁上形成半导体材料层(110)；
    对所述第一牺牲层(L1)沿所述第二方向延伸的外侧壁进行刻蚀至暴露出所述半导体材料层(110)；
    基于所述第一牺牲层(L1)沿所述第二方向延伸的去除区域刻蚀所述半导体材料层(110)，以去除相邻所述第二牺牲层(L2)之间沿所述第二方向延伸的所述半导体材料层(110)，形成初始半导体层(11A)；
    对所述第一牺牲层(L1)沿所述第一方向延伸的外侧壁进行刻蚀至暴露出所述初始半导体层(11A)；
    基于所述第一牺牲层(L1)沿所述第一方向延伸的去除区域刻蚀所述初始半导体层(21A)，以去除相邻所述第二牺牲层(L2)之间沿所述第一方向延伸的所述初始半导体层(21A)，形成分别位于各所述第二牺牲层(L2)内侧壁上的所述半导体层(11)。
  12. 根据权利要求11所述的存储器的制备方法，其中，还包括：
    在所述第一容置孔(H1)的孔壁上形成所述半导体材料层(110)之前，于所述第一容置孔(H1)的孔壁上形成第一介质材料层(150)；其中，所述半导体材料层(110)形成于所述第一介质材料层(150)背离所述第一容置孔(H1)孔壁的表面；
    在所述第二牺牲层(L2)的内侧壁上形成所述半导体层(11)的同时，刻蚀所述第一介质材料层(150)，以于所述第二牺牲层(L2)的内侧壁和所述半导体层(11)之间形成第二栅介质层(15)。
  13. 根据权利要求11所述的存储器的制备方法，其中，所述对所述第一牺牲层(L1)沿所述第二方向延伸的外侧壁进行刻蚀至暴露出所述半导体材料层(110)之前，所述方法还包括：
    形成覆盖所述半导体材料层(110)并填充所述第一容置孔(H1)的第二介质材料层(30)；
    沿所述第一牺牲层(L1)和所述第二牺牲层(L2)的层叠方向，刻蚀所述第二介质材料层(30)以及位于所述第二介质材料层(30)一侧的所述堆叠结构(N)和所述半导体材料层(110)，形成沿所述第一方向延伸的第一隔离槽(G1)，并使剩余的所述第二介质材料层(30)构成初始第一隔离结构 (3A)；
    于所述第一隔离槽(G1)内形成第三隔离结构(5)；
    其中，所述于所述第一部分(111)背离所述第二牺牲层(L2)内侧壁的一侧形成第一栅极(12)，包括：
    沿所述第一牺牲层(L1)和所述第二牺牲层(L2)的层叠方向刻蚀所述初始第一隔离结构(3A)，形成第二容置孔(H2)及位于所述第二容置孔(H2)在所述第一方向上相对两侧的第一隔离结构(3)，并暴露出位于所述第二容置孔(H2)在所述第二方向上相对两侧的所述半导体材料层(110)和所述第三隔离结构(5)；
    于所述第二容置孔(H2)的孔壁上保形形成第一栅介质层(14)；
    形成覆盖所述第一栅介质层(14)并填充所述第二容置孔(H2)的所述第一栅极(12)及与所述第一栅极(12)对应连接的第一字线(WL1)。
  14. 根据权利要求11～13中任一项所述的存储器的制备方法，其中，还包括：
    在基于所述第一牺牲层(L1)沿所述第二方向延伸的去除区域刻蚀所述半导体材料层(110)，形成所述初始半导体层(11A)之后，于所述第一牺牲层(L1)沿所述第二方向延伸的去除区域和所述半导体材料层(110)的刻蚀区域回填第一绝缘材料(61)；
    在基于所述第一牺牲层(L1)沿所述第一方向延伸的去除区域刻蚀所述初始半导体层(11A)，形成所述半导体层(11)之后，于所述第一牺牲层(L1)沿所述第一方向延伸的去除区域和所述初始半导体层(11A)的刻蚀区域回填第二绝缘材料(62)；
    其中，所述刻蚀所述第一部分(111)背离所述第一栅极(12)一侧的所述堆叠结构(N)，并于所述第一部分(111)背离所述第一栅极(12)的一侧形成第二栅极(13)，还包括：
    沿所述第一牺牲层(L1)和所述第二牺牲层(L2)的层叠方向，刻蚀所述第一部分(111)背离所述第一栅极(12)一侧的所述第二牺牲层(L2)和所述第二绝缘材料(61)，形成沿所述第二方向延伸且在所述第一方向上间隔设置的第二隔离槽(G2)，并于所述第二隔离槽(G2)内暴露出所述第一部分(111)对应端部的外侧壁及部分所述第一绝缘材料(61)；
    于所述第二隔离槽(G2)内形成第二隔离结构(4)；
    沿所述第一牺牲层(L1)和所述第二牺牲层(L2)的层叠方向，刻蚀在所述第一方向上相邻所述第二隔离槽(G2)之间间隔内的所述第二牺牲层(L2)和所述第二绝缘材料(62)，形成第三容置孔(H3)，并暴露出所述第三容置孔(H3)在所述第一方向上相对两侧的所述第二隔离结构(4)，同时保留相邻所述第二隔离槽(G2)之间间隔内的部分所述第二牺牲层(L2)构成第一子栅(131)；
    于所述第三容置孔(H3)内形成覆盖所述第一子栅(131)的第二子栅(132)，以及与所述第二子栅(132)对应连接的第二字线(WL2)；其中，所述第二栅极(13)包括所述第一子栅(131)和所述第二子栅(132)。
  15. 根据权利要求14所述的存储器的制备方法，其中，
    所述去除位于所述第二部分(112)背离所述第三部分(113)的一侧的所述第二牺牲层(L2)，形成位线容置槽(G3)，还包括：于所述第二部分(112)背离所述第三部分(113)的一侧，对所述第二牺牲层(L2)沿所述第二方向延伸的外侧壁进行刻蚀至暴露出所述第二隔离结构(4)及所述第二部分(112)的外侧壁，形成所述位线容置槽(G3)；
    所述于所述位线容置槽(G3)内形成位线(BL)，还包括：于所述位线容置槽(G3)内填充金属材料，形成所述位线(BL)。
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