WO2024254942A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2024254942A1
WO2024254942A1 PCT/CN2023/108493 CN2023108493W WO2024254942A1 WO 2024254942 A1 WO2024254942 A1 WO 2024254942A1 CN 2023108493 W CN2023108493 W CN 2023108493W WO 2024254942 A1 WO2024254942 A1 WO 2024254942A1
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WIPO (PCT)
Prior art keywords
groove
substrate
display area
layer
organic insulating
Prior art date
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Ceased
Application number
PCT/CN2023/108493
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English (en)
French (fr)
Inventor
杨国强
龚丽亮
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US18/279,228 priority Critical patent/US20250089473A1/en
Publication of WO2024254942A1 publication Critical patent/WO2024254942A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K59/8792—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. black layers

Definitions

  • the present application relates to the field of display technology, and in particular to a display panel and a display device.
  • the imaging component is set to correspond to the transparent display area of the display panel.
  • the pixel density of the transparent display area is set too high, the light transmittance of the screen will be reduced, affecting the imaging effect. Reducing the pixel density of the transparent display area will affect the display effect of the screen. Therefore, when the transparent display area and the main display area are designed with the same pixel density, the low light transmittance of the transparent display area becomes an obstacle to the development of full-screen technology.
  • the embodiments of the present application provide a display panel and a display device, which can improve the problem of low light transmittance of the light-transmitting display area when the light-transmitting display area and the main display area are designed with the same pixel density.
  • An embodiment of the present application provides a display panel, the display panel comprising a light-transmitting display area and a main display area adjacent to the light-transmitting display area, the light transmittance of the light-transmitting display area being greater than the light transmittance of the main display area.
  • the display panel comprises a substrate, a pixel driving circuit layer, an organic insulating layer and a light-emitting layer.
  • the pixel driving circuit layer is located on the substrate, and the pixel driving circuit layer comprises a plurality of inorganic insulating layers stacked and a plurality of pixel driving circuits arranged in the main display area.
  • the organic insulating layer is located on the pixel driving circuit layer, and the organic insulating layer comprises a first organic insulating sublayer and a second organic insulating sublayer located on the first organic insulating sublayer.
  • the light-emitting layer is located on the organic insulating layer, and the light-emitting layer comprises a plurality of first pixels located in the main display area and a plurality of second pixels located in the light-transmitting display area, and the first pixels and the second pixels are electrically connected to the corresponding pixel driving circuits.
  • the pixel driving circuit layer includes a plurality of first grooves arranged in the light-transmitting display area and located between the second pixels, the first grooves adjacent to different second pixels are connected to each other, the first organic insulating sublayer fills the first grooves, and a first distance from the surface of the first organic insulating sublayer located at the first groove to the substrate away from the substrate is smaller than a second distance from the surface of the first organic insulating sublayer located in the main display area to the substrate away from the substrate.
  • the pixel driving circuit layer further comprises a plurality of protrusions arranged in the light-transmissive display area and corresponding to the second pixels, and the first groove is arranged around the protrusions.
  • a third distance from the first organic insulating sublayer located on the protrusions to the surface of the substrate away from the substrate is greater than the first distance from the first organic insulating sublayer located on the first groove to the surface of the substrate away from the substrate, and is less than the second distance from the first organic insulating sublayer located in the main display area to the surface of the substrate away from the substrate.
  • the pixel driving circuit layer further includes a plurality of second grooves arranged in the light-transmitting display area and corresponding to the second pixels, and the second grooves are connected to adjacent first grooves.
  • a fourth distance from the surface of the substrate to the first organic insulating sublayer located at the second groove is equal to the first distance from the surface of the substrate to the first organic insulating sublayer located at the first groove.
  • the depth of the first groove is equal to the depth of the second groove.
  • the first organic insulating sublayer includes a third groove disposed in the light-transmitting display area and corresponding to the first groove, wherein a width of the third groove is less than or equal to a width of the first groove.
  • a projection width of a sidewall of the third groove on the substrate is less than or equal to a projection width of a sidewall of the first groove on the substrate.
  • the first groove includes a plurality of sub-grooves that are stacked and interconnected, wherein the width of the sub-groove away from the substrate is greater than the width of the sub-groove close to the substrate.
  • the plurality of sub-grooves include a first sub-groove and a second sub-groove.
  • the pixel driving circuit layer includes a buffer layer, a first gate insulating layer, a second gate insulating layer, and an interlayer dielectric layer.
  • the buffer layer is located on the substrate, the first gate insulating layer is located on the buffer layer, the second gate insulating layer is located on the first gate insulating layer, and the interlayer dielectric layer is located on the second gate insulating layer.
  • the buffer layer and the first gate insulating layer include the first sub-groove
  • the second gate insulating layer and the interlayer dielectric layer include the second sub-groove
  • the width of the first sub-groove is less than the width of the second sub-groove.
  • an angle between the bottom surface of the second sub-groove and the sidewall of the second sub-groove is less than or equal to 115°.
  • the display panel further includes a light-shielding layer, the light-shielding layer is located under the pixel driving circuit layer, the light-shielding layer is provided with an opening corresponding to the first groove, and the width of the opening is greater than or equal to the width of the first sub-groove.
  • the substrate includes a base and a barrier layer located on the base.
  • the present application also provides a display device, comprising any of the above-mentioned display panels.
  • the display panel and display device provided by the present application make the plurality of second pixels included in the light-transmitting display area electrically connected to the pixel driving circuit located in the main display area, so that there is no pixel driving circuit design in the entire light-transmitting display area.
  • the pixel driving circuit layer is provided with a plurality of first grooves between the second pixels corresponding to the light-transmitting display area, and the first grooves adjacent to different second pixels are interconnected.
  • the first organic insulating sublayer included in the organic insulating layer fills the first groove, so that the first distance from the surface of the first organic insulating sublayer located at the first groove to the substrate away from the substrate is less than the second distance from the surface of the first organic insulating sublayer located in the main display area to the substrate away from the substrate, so as to reduce the interface reflection, interference and other effects in the portion of the pixel driving circuit layer corresponding to the light-transmitting display area, which is conducive to improving the transmittance of the light-transmitting display area and improving the problem of low transmittance of the light-transmitting display area when the light-transmitting display area and the main display area are designed with the same pixel density.
  • FIG1 is a schematic diagram of the structure of a main display area and a light-transmitting display area provided in an embodiment of the present application;
  • FIGS. 2A to 2D are schematic diagrams of the structure of a display panel provided in an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of the boundary of the opening and the boundary of the groove provided in an embodiment of the present application.
  • Figure 1 is a structural schematic diagram of the main display area and the translucent display area provided in an embodiment of the present application; an embodiment of the present application provides a display panel, the display panel includes a translucent display area 100a and a main display area 100b adjacent to the translucent display area 100a, and the transmittance of the translucent display area 100a is greater than the transmittance of the main display area 100b.
  • the main display area 100b is located outside the light-transmitting display area 100a.
  • the main display area 100b is configured to realize the display function of the display panel
  • the light-transmitting display area 100a is configured to realize the sensing function while realizing the display function of the display panel.
  • the light-transmitting display area 100a realizes the sensing function including sensing light to realize imaging, fingerprint recognition and other functions.
  • the display panel includes a light sensing device arranged corresponding to the light-transmitting display area 100a.
  • the light sensing device includes a camera, a light sensor, etc.
  • the main display area 100b includes a transitional display area 100c, and the transitional display area 100c is located outside the light-transmitting display area 100a.
  • the transitional display area 100c is configured to realize the display function of the display panel.
  • FIGS. 2A to 2D are schematic diagrams of the structure of a display panel provided in an embodiment of the present application.
  • the display panel includes a substrate 100 , a pixel driving circuit layer 200 , an organic insulating layer 300 and a light emitting layer 400 .
  • the substrate 100 includes a base 101 and a barrier layer 102 located on the base 101 .
  • the preparation material of the substrate 101 includes a flexible substrate and a rigid substrate.
  • the substrate 101 can be formed as a single layer or repeatedly stacked to form a multilayer by processes such as coating and curing.
  • the flexible substrate includes polyimide, etc.
  • the substrate 101 can be a flexible substrate formed by coating a polymeric material (such as polyimide) on a supporting substrate and curing the polymeric material.
  • the supporting substrate includes glass, metal, ceramic, etc., and the polymeric material can be coated on the supporting substrate by coating processes such as spin coating, slit coating, inkjet coating, etc. The supporting substrate can be removed in a subsequent process.
  • the rigid substrate includes glass, ceramic, etc.
  • the barrier layer 102 may be made of various insulating materials (such as silicon oxide or silicon nitride).
  • the barrier layer 102 may be a single layer or a multilayer structure.
  • the barrier layer 102 may be configured to block or prevent impurities and moisture from penetrating from the substrate 101 into the light emitting layer 400.
  • the barrier layer 102 includes a first barrier layer and a second barrier layer, wherein the second barrier layer is located between the first barrier layer and the substrate.
  • the first barrier layer may be formed of SiOx or SiON
  • the second barrier layer may be formed of SiNx or SiON.
  • the pixel driving circuit layer 200 is located on the substrate 100 and includes a plurality of stacked inorganic insulating layers and a plurality of pixel driving circuits PDE disposed in the main display area 100 b.
  • the pixel driving circuit PDE that drives the second pixel Pix located in the translucent display area 100a to emit light may be located in the transition display area 100c, and the pixel driving circuit PDE that drives the first pixel located in the main display area 100b to emit light is correspondingly located in the main display area 100b, so as to reduce the interference of the pixel driving circuit PDE on the transmittance of the translucent display area 100a.
  • the pixel driving circuit layer 200 includes a plurality of first grooves H1 disposed in the light-transmitting display area 100 a and located between the second pixels Pix, and the first grooves H1 adjacent to different second pixels Pix are connected to each other.
  • the first groove H1 exposes the barrier layer 102 , so as to block or prevent impurities and moisture from penetrating from the substrate 101 into the light emitting layer 400 through the barrier layer 102 .
  • the pixel driving circuit layer 200 includes a buffer layer 201 , a first gate insulating layer 202 and an interlayer dielectric layer 203 .
  • the buffer layer 201 is located on the substrate 100, and the buffer layer 201 can block or prevent impurities and moisture from penetrating from the substrate 100 into the light-emitting layer 400.
  • the buffer layer 201 can be a single-layer or multi-layer structure, and the buffer layer 201 is made of materials such as silicon oxide or silicon nitride.
  • the first gate insulating layer 202 is located on the buffer layer 201 .
  • the first gate insulating layer 202 may be a single-layer or multi-layer structure.
  • the material of the first gate insulating layer 202 includes at least one of silicon nitride, silicon oxide and the like.
  • the interlayer dielectric layer 203 is located on the first gate insulating layer 202 .
  • the interlayer dielectric layer 203 may be a single-layer or multi-layer structure.
  • the preparation material of the interlayer dielectric layer 203 includes at least one of silicon nitride, silicon oxide, and the like.
  • the buffer layer 201 , the first gate insulating layer 202 , and the interlayer dielectric layer 203 are provided with the first grooves H1 that are interconnected at least in a portion that does not correspond to the second pixel Pix.
  • the pixel driving circuit layer 200 further includes a second gate insulating layer 204, the second gate insulating layer 204 is located on the first gate insulating layer 202, and the interlayer dielectric layer 203 is located on the second gate insulating layer 204.
  • the second gate insulating layer 204 may be a single-layer or multi-layer structure, and the preparation material of the second gate insulating layer 204 includes at least one of silicon nitride, silicon oxide, etc.
  • the buffer layer 201 , the first gate insulating layer 202 , the second gate insulating layer 204 and the interlayer dielectric layer 203 are provided with a plurality of first grooves H1 .
  • the pixel driving circuit layer 200 further includes an active layer 205 , a first gate layer 206 and a source-drain layer 207 .
  • the active layer 205 is located between the buffer layer 201 and the first gate insulating layer 202.
  • the active layer 205 includes a silicon semiconductor material, an oxide semiconductor material, etc.
  • the silicon semiconductor material includes a polysilicon material.
  • the first gate layer 206 is located between the first gate insulating layer 202 and the second gate insulating layer 204, and the first gate layer 206 includes a gate arranged corresponding to the channel region of the active layer 205.
  • the first gate layer 206 may be a single-layer or multi-layer structure, and the material for preparing the first gate layer 206 includes Al, Ti, Mo, Cu, Ni, or alloys thereof, or materials with high corrosion resistance, etc.
  • the source-drain electrode layer 207 is located on the interlayer dielectric layer 203, and the source-drain electrode layer 207 includes a source electrode and a drain electrode electrically connected to the source region and the drain region of the active layer 205, respectively.
  • the source-drain electrode layer 207 may be a single-layer or multi-layer structure, and the material of the source-drain electrode layer 207 includes at least one of Al, Ti, Mo, Cu, Ni, or alloys thereof, or materials with high corrosion resistance.
  • the gate, the source, and the drain respectively form a control electrode, an input electrode, and an output electrode of a transistor.
  • the gate, the source, the drain, and the active layer 205 form a transistor in the pixel driving circuit PDE.
  • the first gate layer 206 further includes a scan line, etc.
  • the source-drain layer 207 further includes a data line, etc.
  • the scan line and the data line are electrically connected to the pixel driving circuit PDE, so that the pixel driving circuit PDE drives the corresponding light-emitting device to emit light according to the scan signal transmitted by the scan line and the data signal transmitted by the data line.
  • the light-emitting device is the first pixel or the second pixel.
  • the display panel further includes a second gate layer 208 and a signal connection layer 310 .
  • the second gate layer 208 is located between the second gate insulating layer 204 and the interlayer dielectric layer 203, and the second gate layer 208 includes a plate portion corresponding to the gate, so that the gate and the plate portion form two electrodes of a capacitor.
  • the second gate layer 208 can be a single-layer or multi-layer structure, and the preparation material of the second gate layer 208 includes at least one of Al, Ti, Mo, Cu, Ni, or alloys thereof, or materials with high corrosion resistance.
  • the signal connection layer 310 is located on the source-drain electrode layer 207, and the signal connection layer 310 includes a plurality of signal connection parts, and the plurality of signal connection parts are electrically connected to corresponding transistors.
  • the signal connection layer 310 is made of at least one material selected from Al, Ti, Mo, Cu, Ni, or alloys thereof, or materials with high corrosion resistance.
  • the signal connection layer 310 is made of a transparent conductive material to reduce the effect of the signal connection layer 310 on the transmittance of the light-transmitting display area 100a.
  • the organic insulating layer 300 is located on the pixel driving circuit layer 200, and the organic insulating layer 300 includes a first organic insulating sublayer 301 and a second organic insulating sublayer 302 located on the first organic insulating sublayer 301.
  • the first organic insulating sublayer 301 fills the first groove H1.
  • a first distance L1 from the surface of the substrate 100 to the first organic insulating sublayer 301 located at the first groove H1 is less than a second distance L2 from the surface of the substrate 100 to the substrate 100 located in the main display area 100b (i.e., L1 ⁇ L2), so that the top surface of the portion of the first organic insulating sublayer 301 corresponding to the first groove H1 is lower than the top surface of the portion of the first organic insulating sublayer 301 corresponding to the main display area 100b.
  • the top surface of the portion of the second organic insulating sublayer 302 corresponding to the first groove H1 is flush with the top surface of the portion of the second organic insulating sublayer 302 corresponding to the main display area 100b, so as to provide a better flatness foundation for the second pixel Pix included in the light-emitting layer 400.
  • the light emitting layer 400 is located on the organic insulating layer 300, and the light emitting layer 400 includes a plurality of first pixels located in the main display area 100b and a plurality of second pixels Pix located in the light-transmitting display area 100a, and the first pixels and the second pixels Pix are electrically connected to the corresponding pixel driving circuit PDE.
  • the inorganic insulating layer i.e., the buffer layer 201, the first gate insulating layer 202, the second gate insulating layer 204, and the interlayer dielectric layer 203 corresponding to the entire light-transmitting display area 100a can be removed to form a first groove H1.
  • the interface reflection, interference and other effects of the buffer layer 201, the gate insulating layer and the interlayer dielectric layer 203 included in the pixel driving circuit layer 200 corresponding to the transparent display area 100a are reduced, which is beneficial to improving the transmittance of the transparent display area 100a and improving the problem of low transmittance of the transparent display area 100a when the transparent display area 100a and the main display area 100b are designed with the same pixel density.
  • the refractive index of the first organic insulating sublayer 301 may be less than or equal to 1.6, and the extinction coefficient may be approximately 0.
  • the refractive index of the first organic insulating sublayer 301 may be equal to 1.6, 1.5, 1.4, 1.3, 1.2, 1.1, 1, etc.
  • the density of the second pixels Pix located in the light-transmitting display area 100 a and the density of the first pixels located in the main display area 100 b are the same.
  • the second pixel Pix and the first pixel include an organic light emitting diode, a sub-millimeter light emitting diode, a micro light emitting diode, etc.
  • the light emitting layer 400 is electrically connected to the corresponding pixel driving circuit PDE through the signal connection layer 310 .
  • the signal connection layer 310 includes a first connection layer 311, the first connection layer 311 is located on the first organic insulating sublayer 301, the first connection layer 311 includes a plurality of first connection parts, and each of the first connection parts is electrically connected to the corresponding pixel driving circuit PDE through a via hole penetrating the first organic insulating sublayer 301.
  • the signal connection layer 310 further includes a second connection layer 312 , and the second connection layer 312 is electrically connected between the second pixel Pix or the first pixel and the first connection layer 311 .
  • the first connecting layer 311 is located between the first organic insulating sublayer 301 and the second organic insulating sublayer 302
  • the second connecting layer 312 is located on the second organic insulating sublayer 302
  • the second connecting layer 312 includes a plurality of second connecting portions, each of the second connecting portions being electrically connected to the corresponding first connecting portion through a via hole penetrating the second organic insulating sublayer 302.
  • the second organic insulating sublayer 302 is prepared by a double coating process to reduce the probability of the wiring on the second organic insulating sublayer 302 being broken or short-circuited, and provide better flatness for the first electrode layer 401 in the light-emitting layer 400.
  • the first electrode layer 401 can be an anode layer or a cathode layer.
  • the signal connection layer 310 further includes a third connection layer 313 , and the third connection layer 313 is electrically connected to the second pixel Pix or between the first pixel and the second connection layer 312 .
  • the organic insulating layer 300 also includes a third organic insulating sublayer 303, the third organic insulating sublayer 303 is located on the second organic insulating sublayer 302, the second connecting layer 312 is located between the second organic insulating sublayer 302 and the third organic insulating sublayer 303, the third connecting layer 313 is located on the third organic insulating sublayer 303, and the third connecting layer 313 includes a plurality of third connecting portions, each of the third connecting portions is electrically connected to the corresponding third connecting portion through a via hole penetrating the third organic insulating sublayer 303.
  • the preparation material of the third organic insulating sublayer 303 includes silicon oxide to prevent the gas in the second organic insulating sublayer 302 , the first organic insulating sublayer 301 , the blocking layer 102 and the substrate 101 under the third organic insulating sublayer 303 from being released into the light-emitting layer 400 .
  • multiple first connection portions are located in the transition display area 100c to avoid problems such as breakage of multiple first connection portions due to the step difference of the first organic insulating sublayer 301 corresponding to the first groove H1, thereby reducing the probability of electrical connection failure between the second pixel Pix located in the transparent display area 100a and the corresponding pixel driving circuit PDE, which in turn causes display failure of the display panel.
  • multiple second connection portions are located in the transition display area 100c, or multiple second connection portions extend from the transition display area 100c to the transparent display area 100a, so as to achieve electrical connection between the second pixel Pix located in the transparent display area 100a and the corresponding pixel driving circuit PDE.
  • multiple third connection portions are located in the transparent display area 100a, or multiple third connection portions extend from the transition display area 100c to the transparent display area 100a, so as to achieve electrical connection between the second pixel Pix located in the transparent display area 100a and the corresponding pixel driving circuit PDE.
  • the organic insulating layer 300 further includes a fourth organic insulating sublayer 304, and the fourth organic insulating sublayer 304 is located on the third organic insulating sublayer 303 and the third connecting layer 313.
  • the first electrode layer 401 of the light-emitting layer 400 includes a plurality of first electrodes, and each of the first electrodes is electrically connected to a corresponding signal connection portion through a via hole penetrating the fourth organic insulating sublayer 304.
  • the first electrode is an anode or cathode of the second pixel Pix or the first pixel.
  • the first electrode layer 401 is an anode layer, and the first electrode is an anode.
  • the pixel driving circuit layer 200 further includes a plurality of second grooves H2 disposed in the light-transmissive display area 100 a and corresponding to the second pixels Pix, and the second grooves H2 are connected to the adjacent first grooves H1 .
  • a fourth distance from the first organic insulating sublayer 301 located at the second groove H2 to the surface of the substrate 100 is equal to the first distance L1 from the first organic insulating sublayer 301 located at the first groove H1 to the surface of the substrate 100, so that a portion of the first organic insulating sublayer 301 corresponding to the second pixel Pix is flush with a portion between the corresponding second pixels Pix.
  • the depth of the first groove H1 is equal to the depth of the second groove H2, so that the first groove H1 and the second groove H2 are prepared synchronously.
  • the light-transmitting display area 100a includes multiple display sub-areas 1001a and light-transmitting sub-areas 1001b located between the multiple display sub-areas 1001a.
  • Multiple second pixels Pix are located correspondingly in the multiple display sub-areas 1001a, and the first groove H1 is set correspondingly to the light-transmitting sub-areas 1001b.
  • the pixel driving circuit layer 200 further includes a plurality of protrusions BP disposed in the light-transmissive display area 100a and corresponding to the second pixel Pix, and the first groove H1 is disposed around the protrusions BP.
  • the third distance L3 from the first organic insulating sublayer 301 located on the protrusions BP to the substrate 100 away from the surface of the substrate 100 is greater than the first distance L1 from the first organic insulating sublayer 301 located on the first groove H1 to the substrate 100 away from the surface of the substrate 100, and is less than or equal to the second distance L2 from the first organic insulating sublayer 301 located in the main display area 100b to the substrate 100 away from the surface of the substrate 100 (i.e., L1 ⁇ L3 ⁇ L2).
  • the convex portion BP includes a first sub-convex portion and a second sub-convex portion.
  • the buffer layer 201 and the first gate insulating layer 202 are provided with the first sub-convex portion corresponding to the display sub-area 1001a
  • the second gate insulating layer 204 and the interlayer dielectric layer 203 are provided with the second sub-convex portion corresponding to the display sub-area 1001a.
  • the orthographic projection of the first sub-convex portion on the substrate 100 has an eighth boundary (such as d6 in FIG. 2C to FIG. 2D is the size defined by the eighth boundary)
  • the orthographic projection of the second sub-convex portion on the substrate 100 has a ninth boundary (such as d7 in FIG. 2C to FIG. 2D is the size defined by the ninth boundary), and the ninth boundary is located within the eighth boundary, so as to provide better support and flatness performance for the second pixel Pix through the convex portion BP.
  • each of the second pixels Pix includes a first electrode located on the organic insulating layer 300.
  • the orthographic projection of the first electrode on the substrate 100 has a tenth boundary (such as d8 in FIG. 2C to FIG. 2D is the size defined by the tenth boundary), and the orthographic projection of the protrusion BP on the substrate 100 is located within the orthographic projection of the first electrode on the substrate 100, so as to reduce the influence of the pixel driving circuit layer 200 on the transmittance of the light-transmitting display area 100a.
  • the orthographic projection of the protrusion BP on the substrate 100 is located within the orthographic projection of the first electrode on the substrate 100, including that the tenth boundary overlaps with the eighth boundary, or the tenth boundary is located outside the eighth boundary.
  • the pixel driving circuit layer 200 is only provided with the first groove H1 corresponding to the light-transmitting sub-area 1001b, so that the size of the first groove H1 is smaller.
  • the step difference between the top surface of the first organic insulating sublayer 301 corresponding to the first groove H1 and the top surface of the first organic insulating sublayer 301 corresponding to the main display area 100b and the transition display area 100c is smaller (as shown by d5 in FIGS.
  • the first organic insulating sublayer 301 includes a third groove H3 disposed in the light-transmitting display area 100a and corresponding to the first groove H1.
  • the width of the third groove H3 is less than or equal to the width of the first groove H1, so that after the first organic insulating sublayer 301 fills the first groove H1, the organic insulating sublayer located on the first organic insulating sublayer 301 has better flatness (i.e., by increasing the number of film layers to be filled (such as the first flat layer 201 including the third groove H3 also needs to be filled), a relatively flat surface is obtained after multiple fillings).
  • FIG3 is a schematic diagram of the structure of the boundary of the first groove and the boundary of the third groove provided in an embodiment of the present application.
  • the projection width of the side wall of the third groove H3 on the substrate 100 is less than or equal to the projection width of the side wall of the first groove H1 on the substrate 100.
  • the projection width of the side wall of the third groove H3 on the substrate 100 is equal to the projection width of the side wall of the first groove H1 on the substrate 100, so as to reduce the probability of light dispersion problems at the staggered positions of the third groove H3 and the first groove H1.
  • the orthographic projection of the side wall of the third groove H3 on the substrate 100 has a first boundary B1
  • the orthographic projection of the side wall of the first groove H1 on the substrate 100 has a second boundary B2
  • the first boundary B1 overlaps with the second boundary B2 to reduce the probability of dispersion problems occurring in light at the staggered positions of the third groove H3 and the first groove H1.
  • the overlap of the first boundary B1 and the second boundary B2 referred to in this application should also include the situation where there is a spacing error between the first boundary B1 and the second boundary B2 due to the influence of factors such as process accuracy and process technology.
  • the first groove H1 includes a plurality of sub-grooves that are stacked and interconnected.
  • the more the number of the sub-grooves the more favorable it is for the first organic insulating sublayer 301 to obtain a relatively flat surface.
  • the more the number of the sub-grooves the more the number of step surfaces formed between the sub-grooves will increase. The more the number of step surfaces, the greater the probability of light scattering on the step surfaces.
  • the number of step surfaces Sm between at least two adjacent sub-grooves is less than or equal to 2, so that the display panel takes into account both flatness and optical performance.
  • the number of the step surfaces Sm may be 0, 1 or 2.
  • the sizes of the plurality of sub-grooves may gradually increase or remain unchanged.
  • the buffer layer 201 and the first gate insulating layer 202 are provided with a first sub-groove H11 corresponding to the light-transmitting display area 100a (that is, the side walls of the buffer layer 201 and the side walls of the first gate insulating layer 202 corresponding to the light-transmitting display area 100a are surrounded to form the first sub-groove H11), and the second gate insulating layer 204 and the interlayer dielectric layer 203 are provided with a second sub-groove H12 corresponding to the light-transmitting display area 100a (that is, the side walls of the second gate insulating layer 204 and the side walls of the interlayer dielectric layer 203 corresponding to the light-transmitting display area 100a are surrounded to form the second sub-groove H12), and the width of the first sub-groove H11 is smaller than the width of the second sub-groove H12, so that the orthographic projection of the first sub-
  • the plurality of first grooves H1 and the plurality of second grooves H2 may have a common boundary (as shown by Bc in FIG. 3 ).
  • each first groove H1 may have a first boundary B1 . Accordingly, each first groove H1 may include the first sub-groove H11 and the second sub-groove H12 .
  • the orthographic projection of the second sub-groove H12 on the substrate 100 has the second boundary B2 and the third boundary B3
  • the orthographic projection of the bottom surface of the third groove H3 on the substrate 100 has the fourth boundary B4
  • the orthographic projection of the first sub-groove H11 on the substrate 100 has the fifth boundary B5 and the sixth boundary B6.
  • the fourth boundary B4 is located within the boundary Bc
  • the third boundary B3 is located within the boundary Bc
  • the fifth boundary B5 is located within the boundary Bc
  • the sixth boundary B6 is located within the fifth boundary B5, and the fourth boundary B4 and the sixth boundary B6 overlap, so as to reduce the probability of light scattering problems occurring at the intersection of the first sub-groove H11, the second sub-groove H12 and the third groove H3.
  • the fourth boundary B4 is located within the first boundary B1
  • the third boundary B3 is located within the second boundary B2
  • the fifth boundary B5 is located within the second boundary B2
  • the sixth boundary B6 is located within the fifth boundary B5.
  • the fourth boundary B4 and the sixth boundary B6 overlap to reduce the probability of light scattering problems occurring at the intersection of the first sub-groove H11, the second sub-groove H12 and the third groove H3.
  • first spacing d1 between the second boundary B2 or boundary Bc and the third boundary B3
  • second spacing d2 between the third boundary B3 and the fifth boundary B5
  • third spacing d3 between the fifth boundary B5 and the sixth boundary B6.
  • the second spacing d2 is less than or equal to 0.3 micrometers
  • the third spacing d3 is less than or equal to 0.8 micrometers, so as to reduce scattering of light at the side of the first sub-groove H11 and the side of the second sub-groove H12.
  • the second spacing d2 is equal to 0.3 micrometers, 0.25 micrometers, 0.21 micrometers, 0.2 micrometers, 0.18 micrometers, 0.15 micrometers, 0.1 micrometers, 0.05 micrometers or 0 micrometers.
  • the third spacing d3 is equal to 0.8 micrometers, 0.75 micrometers, 0.7 micrometers, 0.65 micrometers, 0.6 micrometers, 0.55 micrometers, 0.5 micrometers, 0.45 micrometers, 0.4 micrometers, 0.35 micrometers, 0.3 micrometers, 0.25 micrometers, 0.2 micrometers, 0.15 micrometers, 0.1 micrometers or 0 micrometers.
  • the fourth boundary B4 and the sixth boundary B6 may not be guaranteed to be completely overlapped during preparation. Therefore, the overlap of the fourth boundary B4 and the sixth boundary B6 referred to in this application should also include the situation where there is a spacing error between the fourth boundary B4 and the sixth boundary B6 due to the influence of process accuracy, process technology and other factors.
  • the fifth boundary B5 may coincide with the boundary of the light-transmitting display area 100a, or the sixth boundary B6 may coincide with the boundary of the light-transmitting display area 100a, so as to ensure that the transmittance of the entire light-transmitting display area 100a is improved.
  • the first boundary B1, the boundary Bc and the third boundary B3 are located in the transitional display area 100c, so as to reduce the influence of the first boundary B1, the boundary Bc and the third boundary B3 on the transmittance of the light-transmitting display area 100a.
  • the angle ⁇ between the bottom surface of the second sub-recess H12 and the side wall of the second sub-recess is less than or equal to 115° (that is, the step surface Sm is provided between the first sub-recess H11 and the second sub-recess H12, and the step surface Sm and the side wall of the second sub-first recess H12 have an angle ⁇ , and the supplementary angle of the angle ⁇ is greater than or equal to 65°, so that the side length of the second sub-recess H12 is shorter, thereby reducing the scattering of light at the side of the second sub-recess H12.
  • the complementary angle of the angle ⁇ is equal to 65°, 66°, 67°, 68°, 69°, 70°, 71°, 72°, 73°, 74°, 75°, 76°, 77°, 78°, 79°, 80°, 81°, 82°, 83°, 84°, 85°, 86°, 87°, 88°, 89°, or 90°.
  • the angle between the bottom surface of the first sub-groove H11 and the side wall of the first sub-groove H11 is less than or equal to 115°, so that the side length of the first sub-groove H11 is smaller, thereby reducing scattering of light at the side of the first sub-groove H11.
  • the display panel further includes a light shielding layer 103, and the light shielding layer 103 is located under the pixel driving circuit layer 200.
  • the light shielding layer 103 is provided with an opening corresponding to the first groove H1, and the width of the opening is greater than or equal to the width of the first sub-groove H11.
  • the orthographic projection of the opening on the substrate 100 has a seventh boundary, and the seventh boundary is located between the sixth boundary B6 and the fifth boundary B5, so as to protect the active layer 205 from being irradiated by light while ensuring that the transmittance of the light-transmitting display area 100a is not affected by the shading layer.
  • the light-emitting layer 400 further includes a light-emitting material layer 402 and a second electrode layer 403.
  • the display panel includes a pixel definition layer 404 and an encapsulation layer 500, etc.
  • the pixel definition layer 404 is located on the first electrode layer 401, and the pixel definition layer 404 has a pixel definition area corresponding to the first electrode, the light-emitting material layer 402 is located in the pixel definition area, the second electrode layer 403 is located on the light-emitting material layer 402, and the encapsulation layer 500 is located on the second electrode layer 403.
  • the inventor of the present application provided the first groove H1 in the pixel driving circuit layer 200 corresponding to the light-transmitting display area 100a, and after filling the first groove H1 with a high-transmittance organic material, verified that the transmittance of the display panel can be increased by about 15% (that is, the transmittance of the display panel is increased from the original 63% to 78%).
  • the verification was carried out using a camera as a light sensing element, and the verification results showed that in a dark environment, the camera set corresponding to the light-transmitting display area 100a can take clearer photos with richer details. Therefore, the present application can improve the transmittance of the light-transmitting display area 100a and optimize the imaging effect.
  • the present application also provides a display device, including any of the above-mentioned display panels.
  • the display device includes a mobile display device (such as a laptop computer, a mobile phone, etc.), a fixed terminal (such as a desktop computer, a television, etc.), a measuring device (such as a sports bracelet, a thermometer, etc.), etc.

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Abstract

本申请提供一种显示面板及显示装置，多个第二像素与位于主显示区的像素驱动电路电性连接，像素驱动电路层对应透光显示区的第二像素之间设有多个第一凹槽，临近不同第二像素的第一凹槽相互连通，位于第一凹槽处的第一有机绝缘子层远离衬底的表面距衬底的距离小于位于主显示区的第一有机绝缘子层远离衬底的表面距衬底的距离。

Description

显示面板及显示装置 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板及一种显示装置。
 背景技术
为实现全面屏设计，成像组件对应显示面板的透光显示区设置。但透光显示区设置过高的像素密度，会降低屏体透光率，影响成像效果。而降低透光显示区的像素密度又会影响屏幕的显示效果。因此，透光显示区和主显示区采用相同的像素密度设计时，透光显示区的透光率较低成为全面屏技术发展的阻碍。
 发明概述
本申请实施例提供一种显示面板及一种显示装置，可以改善透光显示区和主显示区采用相同的像素密度设计时，透光显示区的透光率较低的问题。
本申请的实施例提供一种显示面板，所述显示面板包括透光显示区和与所述透光显示区相邻的主显示区，所述透光显示区的透光率大于所述主显示区的透光率。所述显示面板包括衬底、像素驱动电路层、有机绝缘层以及发光层。所述像素驱动电路层位于所述衬底上，所述像素驱动电路层包括多个层叠设置的无机绝缘层和多个设置在所述主显示区的像素驱动电路。所述有机绝缘层位于所述像素驱动电路层上，所述有机绝缘层包括第一有机绝缘子层和位于所述第一有机绝缘子层上的第二有机绝缘子层。所述发光层位于所述有机绝缘层上，所述发光层包括位于所述主显示区内的多个第一像素和位于所述透光显示区内的多个第二像素，所述第一像素和所述第二像素与对应的所述像素驱动电路电性连接。其中，所述像素驱动电路层包括设置在所述透光显示区且位于所述第二像素之间的多个第一凹槽，临近不同所述第二像素的所述第一凹槽相互连通，所述第一有机绝缘子层填充所述第一凹槽，位于所述第一凹槽处的所述第一有机绝缘子层远离所述衬底的表面到衬底的第一距离小于位于所述主显示区的所述第一有机绝缘子层远离所述衬底的表面到衬底的第二距离。
可选地，在本申请的一些实施例中，所述像素驱动电路层还包括多个设置在所述透光显示区且与所述第二像素对应设置的凸起部，所述第一凹槽环绕所述凸起部设置。其中，位于所述凸起部上的第一有机绝缘子层远离所述衬底的表面到所述衬底的第三距离，大于位于所述第一凹槽上的所述第一有机绝缘子层远离所述衬底的表面到所述衬底的所述第一距离，且小于位于所述主显示区的所述第一有机绝缘子层远离所述衬底的表面到所述衬底的所述第二距离。
可选地，在本申请的一些实施例中，所述像素驱动电路层还包括多个设置在所述透光显示区且与所述第二像素对应设置的第二凹槽，所述第二凹槽与相邻的所述第一凹槽连通设置。
可选地，在本申请的一些实施例中，位于所述第二凹槽处的第一有机绝缘子层远离所述衬底的表面到所述衬底的第四距离，等于位于所述第一凹槽处的所述第一有机绝缘子层远离所述衬底的表面到所述衬底的所述第一距离。
可选地，在本申请的一些实施例中，所述第一凹槽的深度等于所述第二凹槽的深度。
可选地，在本申请的一些实施例中，所述第一有机绝缘子层包括设置在所述透光显示区且与所述第一凹槽对应的第三凹槽。其中，所述第三凹槽的宽度小于或等于所述第一凹槽的宽度。
可选地，在本申请的一些实施例中，所述第三凹槽的侧壁在所述衬底上的投影宽度，小于或等于，所述第一凹槽的侧壁在所述衬底上的投影宽度。
可选地，在本申请的一些实施例中，所述第一凹槽包括多个层叠设置且相互连通的子凹槽。其中，远离所述衬底的所述子凹槽的宽度大于靠近所述衬底的所述子凹槽的宽度。
可选地，在本申请的一些实施例中，多个所述子凹槽包括第一子凹槽和第二子凹槽。所述像素驱动电路层包括缓冲层、第一栅绝缘层、第二栅绝缘层以及层间介电层。所述缓冲层位于所述衬底上，所述第一栅绝缘层位于所述缓冲层上，所述第二栅绝缘层位于所述第一栅绝缘层上，所述层间介电层位于所述第二栅绝缘层上。其中，所述缓冲层和所述第一栅绝缘层包括所述第一子凹槽，所述第二栅绝缘层和所述层间介电层包括所述第二子凹槽，所述第一子凹槽的宽度小于所述第二子凹槽的宽度。
可选地，在本申请的一些实施例中，所述第二子凹槽的底面与所述第二子凹槽的侧壁之间所具有的夹角小于或等于115°。
可选地，在本申请的一些实施例中，所述显示面板还包括遮光层，所述遮光层位于所述像素驱动电路层下，所述遮光层对应所述第一凹槽设有开孔，所述开孔的宽度大于或等于所述第一子凹槽的宽度。
可选地，在本申请的一些实施例中，所述衬底包括基底和位于所述基底上的阻挡层。
本申请还提供一种显示装置，包括任一上述的显示面板。
有益效果
相较于现有技术，本申请提供的显示面板及显示装置，通过使发光层包括的位于透光显示区内的多个第二像素对应与位于主显示区的像素驱动电路电性连接，以使整个透光显示区内无像素驱动电路设计。像素驱动电路层在对应透光显示区的第二像素之间设有多个第一凹槽，临近不同第二像素的第一凹槽相互连通，有机绝缘层包括的第一有机绝缘子层填充第一凹槽，使得位于第一凹槽处的第一有机绝缘子层远离衬底的表面到衬底的第一距离小于位于主显示区的第一有机绝缘子层远离衬底的表面到衬底的第二距离，以降低像素驱动电路层对应透光显示区的部分出现界面反射、干涉等作用，有利于提高透光显示区的透光率，改善透光显示区和主显示区采用相同的像素密度设计时，透光显示区的透光率较低的问题。通过在第一有机绝缘子层上设置第二有机绝缘子层，以为第二像素提供较佳的平坦性基础。
 附图说明
图1是本申请实施例提供的主显示区和透光显示区的结构示意图；
图2A~图2D是本申请实施例提供的显示面板的结构示意图；
图3是本申请实施例提供的开口的边界与凹槽的边界的结构示意图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
具体地，具体地，图1是本申请实施例提供的主显示区和透光显示区的结构示意图；本申请的实施例提供一种显示面板，所述显示面板包括透光显示区100a及与所述透光显示区100a相邻的主显示区100b，所述透光显示区100a的透光率大于所述主显示区100b的透光率。
可选地，所述主显示区100b位于所述透光显示区100a外围。可选地，所述主显示区100b被配置为实现所述显示面板的显示功能，所述透光显示区100a被配置为在实现所述显示面板的显示功能的同时，还被配置为用于实现感测功能。可选地，所述透光显示区100a实现感测功能包括感测光线而实现成像、指纹识别等功能。
可选地，所述显示面板包括对应所述透光显示区100a设置的光感测器件。可选地，所述光感测器件包括摄像头、光传感器等。
可选地，所述主显示区100b包括过渡显示区100c，过渡显示区100c位于所述透光显示区100a外围。可选地，所述过渡显示区100c被配置为实现所述显示面板的显示功能。
图2A~图2D是本申请实施例提供的显示面板的结构示意图。
所述显示面板包括衬底100、像素驱动电路层200、有机绝缘层300以及发光层400。
可选地，所述衬底100包括基底101和位于所述基底101上的阻挡层102。
可选地，所述基底101的制备材料包括柔性基底和刚性基底。可选地，所述基底101可形成为单层或通过涂布和固化等工艺而重复地堆叠形成为多层。可选地，所述柔性基底包括聚酰亚胺等。可选地，所述基底101可通过将聚合材料（如聚酰亚胺）涂布在支承基底上并使聚合材料固化而形成的柔性基底。可选地，支承基底包括玻璃、金属、陶瓷等，聚合材料可通过诸如旋涂、狭缝涂覆、喷墨涂覆等涂布工艺而涂布在支承基底上。支撑基底在后续工艺中可以被移除。可选地，所述刚性基底包括玻璃、陶瓷等。
可选地，所述阻挡层102的制备材料包括各种绝缘材料（例如氧化硅或氮化硅等）。可选地，所述阻挡层102可为单层或多层结构。所述阻挡层102可被配置为阻止或防止杂质和湿气从所述基底101渗入到发光层400中。
可选地，所述阻挡层102包括第一阻挡层和第二阻挡层，所述第二阻挡层位于所述第一阻挡层和所述基底之间。所述第一阻挡层可由SiOx或SiON形成，所述第二阻挡层可由SiNx或SiON形成。
所述像素驱动电路层200位于所述衬底100上，包括多个层叠设置的无机绝缘层和多个设置在所述主显示区100b的像素驱动电路PDE。
可选地，驱动位于所述透光显示区100a的第二像素Pix发光的像素驱动电路PDE可位于所述过渡显示区100c，驱动位于所述主显示区100b的第一像素发光的像素驱动电路PDE对应位于所述主显示区100b内，以降低像素驱动电路PDE对所述透光显示区100a的透光率的干扰。
其中，所述像素驱动电路层200包括设置在所述透光显示区100a且位于所述第二像素Pix之间的多个第一凹槽H1，临近不同所述第二像素Pix的所述第一凹槽H1相互连通。
可选地，所述第一凹槽H1暴露出所述阻挡层102，以通过所述阻挡层102阻止或防止杂质和湿气从所述基底101渗入到发光层400中。
可选地，所述像素驱动电路层200包括缓冲层201、第一栅绝缘层202以及层间介电层203。
所述缓冲层201位于所述衬底100上，所述缓冲层201可阻止或防止杂质和湿气从所述衬底100渗入到所述发光层400中。可选地，所述缓冲层201可为单层或多层结构，所述缓冲层201的制备材料包括氧化硅或氮化硅等材料。
所述第一栅绝缘层202位于所述缓冲层201上，所述第一栅绝缘层202可为单层或多层结构，所述第一栅绝缘层202的制备材料包括硅氮化物、硅氧化物等中的至少一种。
所述层间介电层203位于所述第一栅绝缘层202上，所述层间介电层203可为单层或多层结构，所述层间介电层203的制备材料包括硅氮化物、硅氧化物等中的至少一种。
可选地，所述缓冲层201、所述第一栅绝缘层202以及所述层间介电层203至少在对应非所述第二像素Pix的部分设有相互连通的所述第一凹槽H1。
可选地，所述像素驱动电路层200还包括第二栅绝缘层204，所述第二栅绝缘层204位于所述第一栅绝缘层202上，所述层间介电层203位于所述第二栅绝缘层204上。所述第二栅绝缘层204可为单层或多层结构，所述第二栅绝缘层204的制备材料包括硅氮化物、硅氧化物等中的至少一种。
可选地，所述缓冲层201、所述第一栅绝缘层202、所述第二栅绝缘层204以及所述层间介电层203设有多个所述第一凹槽H1。
可选地，所述像素驱动电路层200还包括有源层205、第一栅极层206以及源漏极层207。
所述有源层205位于所述缓冲层201和所述第一栅绝缘层202之间。可选地，所述有源层205包括硅半导体材料、氧化物半导体材料等。可选地，所述硅半导体材料包括多晶硅材料。
所述第一栅极层206位于所述第一栅绝缘层202和所述第二栅绝缘层204之间，所述第一栅极层206包括对应所述有源层205的沟道区设置的栅极。可选地，所述第一栅极层206可为单层或多层结构，所述第一栅极层206的制备材料包括Al、Ti、Mo、Cu、Ni、或其合金，或具有高防腐性能的材料等。
所述源漏极层207位于所述层间介电层203上，所述源漏极层207包括分别与所述有源层205的源极区和漏极区电性连接的源极和漏极。可选地，所述源漏极层207可为单层或多层结构，所述源漏极层207的制备材料包括Al、Ti、Mo、Cu、Ni、或其合金，或具有高防腐性能的材料等中的至少一种。
所述栅极、所述源极以及所述漏极分别形成晶体管的控制电极、输入电极以及输出电极，所述栅极、所述源极以及所述漏极与所述有源层205形成所述像素驱动电路PDE中的晶体管。
可选地，所述第一栅极层206还包括扫描线等，所述源漏极层207还包括数据线等。所述扫描线、所述数据线与所述像素驱动电路PDE电性连接，以使所述像素驱动电路PDE根据所述扫描线传输的扫描信号和所述数据线传输的数据信号驱动对应的发光器件进行发光。其中，所述发光器件为第一像素或第二像素。
可选地，所述显示面板还包括第二栅极层208及信号连接层310。
所述第二栅极层208位于所述第二栅绝缘层204和所述层间介电层203之间，所述第二栅极层208包括对应所述栅极设置的极板部，以使所述栅极与所述极板部形成电容的两电极。可选地，所述第二栅极层208可为单层或多层结构，所述第二栅极层208的制备材料包括Al、Ti、Mo、Cu、Ni、或其合金，或具有高防腐性能的材料等中的至少一种。
所述信号连接层310位于所述源漏极层207上，所述信号连接层310包括多个信号连接部，多个信号连接部与对应的晶体管电性连接。可选地，所述信号连接层310的制备材料包括Al、Ti、Mo、Cu、Ni、或其合金，或具有高防腐性能的材料等中的至少一种。可选地，所述信号连接层310的制备材料包括透明导电材料，以降低信号连接层310对所述透光显示区100a透光率的影响。
请继续参阅图2A~图2D，所述有机绝缘层300位于所述像素驱动电路层200上，所述有机绝缘层300包括第一有机绝缘子层301和位于所述第一有机绝缘子层301上的第二有机绝缘子层302。其中，所述第一有机绝缘子层301填充所述第一凹槽H1。
可选地，位于所述第一凹槽H1处的所述第一有机绝缘子层301远离所述衬底100的表面到所述衬底100的第一距离L1小于位于所述主显示区100b的所述第一有机绝缘子层301远离所述衬底100的表面到衬底100的第二距离L2（即L1<L2），以使所述第一有机绝缘子层301对应位于所述第一凹槽H1内的部分的顶面低于所述第一有机绝缘子层301对应位于所述主显示区100b内的部分的顶面。可选地，所述第二有机绝缘子层302对应所述第一凹槽H1的部分的顶面与所述第二有机绝缘子层302对应位于所述主显示区100b内的部分的顶面平齐，以为发光层400包括的第二像素Pix提供较佳的平坦性基础。
请继续参阅图2A~图2D，所述发光层400位于所述有机绝缘层300上，所述发光层400包括位于所述主显示区100b内的多个第一像素和位于所述透光显示区100a内的多个第二像素Pix，所述第一像素和所述第二像素Pix与对应的所述像素驱动电路PDE电性连接。通过使多个第二像素Pix与位于主显示区100b内的像素驱动电路PDE电性连接，以使整个透光显示区100a内无像素驱动电路PDE设计，从而在提升透光显示区100a的透光率时，对应整个透光显示区100a的无机绝缘层（即缓冲层201、第一栅绝缘层202、第二栅绝缘层204和层间介电层203）可被去除，以形成第一凹槽H1。通过在第一凹槽H1内设置有机绝缘层300，以降低像素驱动电路层200包括的缓冲层201、栅绝缘层及层间介电层203对应透光显示区100a的部分出现界面反射、干涉等作用，有利于提高透光显示区100a的透光率，改善透光显示区100a和主显示区100b采用相同的像素密度设计时，透光显示区100a的透光率较低的问题。
可选地，为使所述第一有机绝缘子层301具有较好的光透过率，所述第一有机绝缘子层301的折射率可小于或等于1.6，消光系数约为0。可选地，所述第一有机绝缘子层301的折射率可等于1.6、1.5、1.4、1.3、1.2、1.1、1等。
可选地，单位面积内，位于所述透光显示区100a的第二像素Pix和位于所述主显示区100b的第一像素的密度相同。
可选地，所述第二像素Pix和所述第一像素包括有机发光二极管、次毫米发光二极管及微型发光二极管等。
可选地，所述发光层400通过所述信号连接层310与对应的所述像素驱动电路PDE电性连接。
可选地，所述信号连接层310包括第一连接层311，所述第一连接层311位于所述第一有机绝缘子层301上，所述第一连接层311包括多个第一连接部，每一所述第一连接部通过贯穿所述第一有机绝缘子层301的过孔与对应的所述像素驱动电路PDE电性连接。
可选地，所述信号连接层310还包括第二连接层312，所述第二连接层312电性连接于所述第二像素Pix或所述第一像素与所述第一连接层311之间。
可选地，所述第一连接层311位于所述第一有机绝缘子层301和所述第二有机绝缘子层302之间，所述第二连接层312位于所述第二有机绝缘子层302上，所述第二连接层312包括多个第二连接部，每一所述第二连接部通过贯穿所述第二有机绝缘子层302的过孔与对应的所述第一连接部电性连接。
可选地，为降低所述第二有机绝缘子层302表面的段差，使所述第二有机绝缘子层302表面具有较好的平坦性，所述第二有机绝缘子层302采用两次涂布工艺制备，以降低位于所述第二有机绝缘子层302上的走线的出现断裂或短路的几率，并为发光层400中的第一电极层401提供较好的平坦性。其中，所述第一电极层401可为阳极层或阴极层。
可选地，所述信号连接层310还包括第三连接层313，所述第三连接层313电性连接于所述第二像素Pix或所述第一像素与所述第二连接层312之间。
可选地，所述有机绝缘层300还包括第三有机绝缘子层303，所述第三有机绝缘子层303位于所述第二有机绝缘子层302上，所述第二连接层312位于所述第二有机绝缘子层302和所述第三有机绝缘子层303之间，所述第三连接层313位于所述第三有机绝缘子层303上，所述第三连接层313包括多个第三连接部，每一所述第三连接部通过贯穿所述第三有机绝缘子层303的过孔与对应的所述第三连接部电性连接。
可选地，所述第三有机绝缘子层303的制备材料包括氧化硅，以阻隔位于所述第三有机绝缘子层303下的所述第二有机绝缘子层302、所述第一有机绝缘子层301、所述阻挡层102及所述基底101中的气体释放至所述发光层400。
可选地，多个第一连接部位于所述过渡显示区100c内，以避免因所述第一有机绝缘子层301在对应所述第一凹槽H1处具有段差而导致多个所述第一连接部出现断裂等问题，从而降低位于透光显示区100a的第二像素Pix与所对应的像素驱动电路PDE之间出现电性连接故障，继而导致显示面板出现显示故障的几率。
可选地，多个第二连接部位于所述过渡显示区100c内，或多个所述第二连接部自所述过渡显示区100c延伸至所述透光显示区100a内，以使位于透光显示区100a的第二像素Pix与所对应的像素驱动电路PDE之间实现电性连接。
可选地，多个第三连接部位于所述透光显示区100a内，或多个所述第三连接部自所述过渡显示区100c延伸至所述透光显示区100a内，以使位于透光显示区100a的第二像素Pix与所对应的像素驱动电路PDE之间实现电性连接。
可选地，所述有机绝缘层300还包括第四有机绝缘子层304，所述第四有机绝缘子层304位于所述第三有机绝缘子层303和所述第三连接层313上，所述发光层400的第一电极层401包括多个第一电极，每一所述第一电极通过贯穿所述第四有机绝缘子层304的过孔与对应的信号连接部电性连接。其中，所述第一电极为第二像素Pix或第一像素的阳极或阴极。
可选地，所述第一电极层401为阳极层，所述第一电极为阳极。
请继续参阅图2A~图2B，所述像素驱动电路层200还包括多个设置在所述透光显示区100a且与所述第二像素Pix对应设置的第二凹槽H2，所述第二凹槽H2与相邻的所述第一凹槽H1连通设置。
可选地，位于所述第二凹槽H2处的第一有机绝缘子层301远离所述衬底100的表面到所述衬底100的第四距离，等于位于所述第一凹槽H1处的所述第一有机绝缘子层301远离所述衬底100的表面到所述衬底100的所述第一距离L1，以使第一有机绝缘子层301对应第二像素Pix的部分与对应第二像素Pix之间的部分平齐。
可选地，所述第一凹槽H1的深度等于所述第二凹槽H2的深度，以便同步制备所述第一凹槽H1和所述第二凹槽H2。
可选地，请继续参阅图2C~图2D，所述透光显示区100a包括多个显示子区1001a和位于多个显示子区1001a之间的透光子区1001b。多个所述第二像素Pix对应位于多个所述显示子区1001a，所述第一凹槽H1对应所述透光子区1001b设置。
所述像素驱动电路层200还包括多个设置在所述透光显示区100a且与所述第二像素Pix对应设置的凸起部BP，所述第一凹槽H1环绕所述凸起部BP设置。其中，位于所述凸起部BP上的第一有机绝缘子层301远离所述衬底100的表面到所述衬底100的第三距离L3，大于位于所述第一凹槽H1上的所述第一有机绝缘子层301远离所述衬底100的表面到所述衬底100的所述第一距离L1，且小于或等于位于所述主显示区100b的所述第一有机绝缘子层301远离所述衬底100的表面到所述衬底100的所述第二距离L2（即L1<L3≤L2）。
可选地，所述凸起部BP包括第一子凸起部和第二子凸起部。所述缓冲层201和所述第一栅绝缘层202对应所述显示子区1001a设有所述第一子凸起部，所述第二栅绝缘层204和所述层间介电层203对应所述显示子区1001a设有所述第二子凸起部。其中，所述第一子凸起部在所述衬底100上的正投影具有第八边界（如图2C~图2D中的d6即为第八边界限定的尺寸），所述第二子凸起部在所述衬底100上的正投影具有第九边界（如图2C~图2D中的d7即为第九边界限定的尺寸），所述第九边界位于所述第八边界内，以通过所述凸起部BP为所述第二像素Pix提供较好的支撑及平坦性能。
可选地，每一所述第二像素Pix包括位于所述有机绝缘层300上的第一电极。其中，所述第一电极在所述衬底100上的正投影具有第十边界（如图2C~图2D中的d8即为第十边界限定的尺寸），所述凸起部BP在所述衬底100上的正投影位于所述第一电极在所述衬底100上的正投影内，以降低所述像素驱动电路层200对所述透光显示区100a的透光率的影响。其中，所述凸起部BP在所述衬底100上的正投影位于所述第一电极在所述衬底100上的正投影内包括所述第十边界与所述第八边界重叠，或所述第十边界位于所述第八边界外。
相对于图2A~图2B的设计，所述像素驱动电路层200仅在对应所述透光子区1001b设有所述第一凹槽H1的设计，使得所述第一凹槽H1的尺寸更小，在所述第一有机绝缘子层301填充所述第一凹槽H1时，所述第一有机绝缘子层301对应所述第一凹槽H1处的顶面与所述第一有机绝缘子层301对应所述主显示区100b、所述过渡显示区100c的顶面之间的段差更小（如图2C~图2D中的d5所示），有利于提高所述第二有机绝缘子层302表面的平坦性，从而能够更大限度的减小所述信号连接层310内出现断线的几率，有利于提高位于所述透光显示区100a内的所述第一电极的平坦度。
请继续参阅图2A~图2D，由于第一距离L1小于第二距离L2，因而，所述第一有机绝缘子层301包括设置在所述透光显示区100a且与所述第一凹槽H1对应的第三凹槽H3。可选地，所述第三凹槽H3的的宽度小于或等于所述第一凹槽H1的宽度，以在所述第一有机绝缘子层301填充所述第一凹槽H1后，使位于所述第一有机绝缘子层301上的有机绝缘子层具有较好的平坦性（即通过增加需填平膜层的数量（如第一平坦层201包括所述第三凹槽H3也需被填平），以在多次填平后获取较平坦的表面）。
可选地，如图3是本申请实施例提供的第一凹槽的边界与第三凹槽的边界的结构示意图。所述第三凹槽H3的侧壁在所述衬底100上的投影宽度，小于或等于，所述第一凹槽H1的侧壁在所述衬底100上的投影宽度。可选地，所述第三凹槽H3的侧壁在所述衬底100上的投影宽度等于所述第一凹槽H1的侧壁在所述衬底100上的投影宽度，以降低光线在所述第三凹槽H3及所述第一凹槽H1的交错位置出现色散问题的几率。
可选地，所述第三凹槽H3的侧壁在所述衬底100上的正投影具有第一边界B1，所述第一凹槽H1的侧壁在所述衬底100上的正投影具有第二边界B2，所述第一边界B1与所述第二边界B2重叠，以降低光线在所述第三凹槽H3及所述第一凹槽H1的交错位置出现色散问题的几率。
其中，可以理解的是，在现有制备方法中，受限于制程精度、制程工艺等因素的限制，所述第一边界B1与所述第二边界B2制备时可能并不能保证完全重叠。因而，本申请所指的所述第一边界B1与所述第二边界B2重叠也应包括因制程精度、制程工艺等因素的影响，而使得所述第一边界B1与所述第二边界B2之间存在间距误差的情况。
可选地，请继续参阅图2A~图2D，在所述显示面板的厚度方向上，所述第一凹槽H1包括多个层叠设置且相互连通的子凹槽。所述子凹槽数量越多，越有利于使第一有机绝缘子层301获得较平坦的表面，但所述子凹槽数量越多，子凹槽与子凹槽之间形成的台阶面的数量也会随之增加，而台阶面的数量越多，光线在台阶面出现光线散射的几率就越大。因而，为兼顾平坦性及光学性能，在所述显示面板的厚度方向上，使至少两相邻的所述子凹槽之间所具有的台阶面Sm的数量小于或等于2，以便使所述显示面板兼顾平坦性及光学性能。
可选地，所述台阶面Sm的数量可以为0个、1个或2个。
可选地，所述台阶面Sm的数量为0个时，在所述缓冲层201至所述层间介电层203的方向上，多个所述子凹槽的尺寸可以逐渐增大，也可以保持不变。
可选地，请继续参阅图2A~图2D，所述缓冲层201和所述第一栅绝缘层202对应所述透光显示区100a设有第一子凹槽H11（即对应所述透光显示区100a的所述缓冲层201的侧壁和所述第一栅绝缘层202的侧壁包围形成所述第一子凹槽H11），所述第二栅绝缘层204和所述层间介电层203对应所述透光显示区100a设有第二子凹槽H12（即对应所述透光显示区100a的所述第二栅绝缘层204的侧壁和所述层间介电层203的侧壁包围形成所述第二子凹槽H12），所述第一子凹槽H11的宽度小于所述第二子凹槽H12的宽度，从而使所述第一子凹槽H11在所述衬底100上的正投影位于所述第二子凹槽H12在所述衬底100上的正投影内，以使所述台阶面Sm数量为1个或0个，从而兼顾平坦性和光学性能。
可选地，在图2A~图2B所示的显示面板中，多个所述第一凹槽H1和多个所述第二凹槽H2的顶面平齐时，多个所述第一凹槽H1和多个所述第二凹槽H2可具有的一个共同的边界（如图3中的Bc所示）。
可选地，在图2C~图2D所示的显示面板中，显示面板不包括第二凹槽H2时，每一第一凹槽H1对应具有第一边界B1。相应地，每一第一凹槽H1可对应包括所述第一子凹槽H11及所述第二子凹槽H12。
可选地，请继续参阅图3，所述第二子凹槽H12在所述衬底100上的正投影具有所述第二边界B2和第三边界B3，所述第三凹槽H3的底面在所述衬底100上的正投影具有第四边界B4，所述第一子凹槽H11在所述衬底100上的正投影具有第五边界B5和第六边界B6。其中，在图2A~图2B所示的显示面板中，所述第四边界B4位于边界Bc内，所述第三边界B3位于所述边界Bc内，所述第五边界B5位于所述边界Bc内，所述第六边界B6位于所述第五边界B5内，所述第四边界B4和所述第六边界B6重叠，以降低光线在所述第一子凹槽H11、所述第二子凹槽H12及所述第三凹槽H3的交错处所出现的光线散射问题的几率。在图2C~图2D所示的显示面板中，所述第四边界B4位于所述第一边界B1内，所述第三边界B3位于所述第二边界B2内，所述第五边界B5位于所述第二边界B2内，所述第六边界B6位于所述第五边界B5内，所述第四边界B4和所述第六边界B6重叠，以降低光线在所述第一子凹槽H11、所述第二子凹槽H12及所述第三凹槽H3的交错处所出现的光线散射问题的几率。
可选地，所述第二边界B2或边界Bc与所述第三边界B3之间具有第一间距d1，所述第三边界B3与所述第五边界B5之间具有第二间距d2，所述第五边界B5与所述第六边界B6之间具有第三间距d3。所述第一边界B1与所述第四边界B4的间距d4等于所述第一间距d1与所述第二间距d2、所述第三间距d3之和（即d4=d1+d2+d3）。
可选地，所述第二间距d2小于或等于0.3微米，所述第三间距d3小于或等于0.8微米，以减小光线在所述第一子凹槽H11侧面及所述第二子凹槽H12侧面处的散射。
可选地，所述第二间距d2等于0.3微米、0.25微米、0.21微米、0.2微米、0.18微米、0.15微米、0.1微米、0.05微米或0微米。可选地，所述第三间距d3等于0.8微米、0.75微米、0.7微米、0.65微米、0.6微米、0.55微米、0.5微米、0.45微米、0.4微米、0.35微米、0.3微米、0.25微米、0.2微米、0.15微米、0.1微米或0微米。
其中，可以理解的是，在现有制备方法中，受限于制程精度、制程工艺等因素的限制，所述第四边界B4和所述第六边界B6制备时可能并不能保证完全重叠。因而，本申请所指的所述第四边界B4和所述第六边界B6重叠也应包括因制程精度、制程工艺等因素的影响，而使得所述第四边界B4和所述第六边界B6之间存在间距误差的情况。
可选地，在图2A~图2B所示的显示面板中，所述第五边界B5可与所述透光显示区100a的边界重合，或所述第六边界B6可与所述透光显示区100a的边界重合，以确保整个所述透光显示区100a的透光率均得到改善。可选地，所述第一边界B1、边界Bc及所述第三边界B3位于所述过渡显示区100c内，以降低所述第一边界B1、边界Bc及所述第三边界B3对所述透光显示区100a的透光率的影响。
可选地，请继续参阅图2A~图2D，所述第二子凹槽H12的底面与所述第二子凹槽的侧壁之间所具有的夹角α小于或等于115°（即所述第一子凹槽H11和所述第二子凹槽H12之间具有所述台阶面Sm，所述台阶面Sm与所述第二子第一凹槽H12的侧壁之间具有夹角α，所述夹角α的补角大于或等于65°，以使所述第二子凹槽H12的侧面长度较小，从而减小光线在所述第二子凹槽H12侧面处的散射。
可选地，所述夹角α的补角等于65°、66°、67°、68°、69°、70°、71°、72°、73°、74°、75°、76°、77°、78°、79°、80°、81°、82°、83°、84°、85°、86°、87°、88°、89°、或90°。
可选地，所述第一子凹槽H11的底面与所述第一子凹槽H11的侧壁之间的夹角小于或等于115°，以使所述第一子凹槽H11的侧面长度较小，从而减小光线在所述第一子凹槽H11侧面处的散射。
可选地，请继续参阅图2B和图2D，所述显示面板还包括遮光层103，所述遮光层103位于所述像素驱动电路层200下。其中，所述遮光层103对应所述第一凹槽H1设有开孔，所述开孔的宽度大于或等于所述第一子凹槽H11的宽度。
可选地，所述开孔在所述衬底100上的正投影具有第七边界，所述第七边界位于所述第六边界B6和所述第五边界B5之间，以在保护有源层205不被光线照射的同时，使所述透光显示区100a的透光率不被所述遮光层影响。
可选地，请继续参阅图2A~图2D，所述发光层400还包括发光材料层402及第二电极层403。所述显示面板包括像素定义层404及封装层500等。所述像素定义层404位于所述第一电极层401上，所述像素定义层404对应所述第一电极设有像素定义区，所述发光材料层402位于所述像素定义区内，所述第二电极层403位于所述发光材料层402上，所述封装层500位于所述第二电极层403上。
本申请发明人将所述像素驱动电路层200对应所述透光显示区100a设有所述第一凹槽H1，并在所述第一凹槽H1内填充高透有机材料后，验证所述显示面板的透光率可提升约15%（即显示面板的透光率由原来的63%提升至78%）。采用摄像头作为光感测元件进行验证，验证结果表明在暗态环境下，对应透光显示区100a设置的摄像头拍照更清晰，细节更丰富。因此，本申请可提高透光显示区100a的透光率，优化成像效果。
本申请还提供一种显示装置，包括任一上述的显示面板。可以理解地，所述显示装置包括可移动显示装置（如笔记本电脑、手机等）、固定终端（如台式电脑、电视等）、测量装置（如运动手环、测温仪等）等。
本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示面板，其中，包括透光显示区和与所述透光显示区相邻的主显示区，所述透光显示区的透光率大于所述主显示区的透光率，所述显示面板包括：
    衬底；
    像素驱动电路层，位于所述衬底上，包括多个层叠设置的无机绝缘层和多个设置在所述主显示区的像素驱动电路；
    有机绝缘层，位于所述像素驱动电路层上，包括第一有机绝缘子层和位于所述第一有机绝缘子层上的第二有机绝缘子层；以及
    发光层，位于所述有机绝缘层上，包括：位于所述主显示区内的多个第一像素和位于所述透光显示区内的多个第二像素，所述第一像素和所述第二像素与对应的所述像素驱动电路电性连接；
    其中，所述像素驱动电路层包括：设置在所述透光显示区且位于所述第二像素之间的多个第一凹槽，临近不同所述第二像素的所述第一凹槽相互连通，所述第一有机绝缘子层填充所述第一凹槽，位于所述第一凹槽处的所述第一有机绝缘子层远离所述衬底的表面到所述衬底的第一距离小于位于所述主显示区的所述第一有机绝缘子层远离所述衬底的表面到所述衬底的第二距离。
  2. 根据权利要求1所述的显示面板，其中，所述像素驱动电路层还包括：
    多个设置在所述透光显示区且与所述第二像素对应设置的凸起部，所述第一凹槽环绕所述凸起部设置，位于所述凸起部上的第一有机绝缘子层远离所述衬底的表面到所述衬底的第三距离，大于位于所述第一凹槽上的所述第一有机绝缘子层远离所述衬底的表面到所述衬底的所述第一距离，且小于位于所述主显示区的所述第一有机绝缘子层远离所述衬底的表面到所述衬底的所述第二距离。
  3. 根据权利要求1所述的显示面板，其中，所述像素驱动电路层还包括：
    多个设置在所述透光显示区且与所述第二像素对应设置的第二凹槽，所述第二凹槽与相邻的所述第一凹槽连通设置。
  4. 根据权利要求3所述的显示面板，其中，
    位于所述第二凹槽处的第一有机绝缘子层远离所述衬底的表面到所述衬底的第四距离，等于位于所述第一凹槽处的所述第一有机绝缘子层远离所述衬底的表面到所述衬底的所述第一距离。
  5. 根据权利要求3所述的显示面板，其中，所述第一凹槽的深度等于所述第二凹槽的深度。
  6. 根据权利要求1所述的显示面板，其中，所述第一有机绝缘子层包括设置在所述透光显示区且与所述第一凹槽对应的第三凹槽；
    其中，所述第三凹槽的宽度小于或等于所述第一凹槽的宽度。
  7. 根据权利要求6所述的显示面板，其中，所述第三凹槽的侧壁在所述衬底上的投影宽度，小于或等于，所述第一凹槽的侧壁在所述衬底上的投影宽度。
  8. 根据权利要求1所述的显示面板，其中，所述第一凹槽包括多个层叠设置且相互连通的子凹槽；
    其中，远离所述衬底的所述子凹槽的宽度大于靠近所述衬底的所述子凹槽的宽度。
  9. 根据权利要求8所述的显示面板，其中，多个所述子凹槽包括第一子凹槽和第二子凹槽；所述像素驱动电路层包括：
    缓冲层，位于所述衬底上；
    第一栅绝缘层，位于所述缓冲层上；
    第二栅绝缘层，位于所述第一栅绝缘层上；以及
    层间介电层，位于所述第二栅绝缘层上；
    其中，所述缓冲层和所述第一栅绝缘层包括所述第一子凹槽，所述第二栅绝缘层和所述层间介电层包括所述第二子凹槽，所述第一子凹槽的宽度小于所述第二子凹槽的宽度。
  10. 根据权利要求9所述的显示面板，其中，所述第二子凹槽的底面与所述第二子凹槽的侧壁之间所具有的夹角小于或等于115°。
  11. 根据权利要求9所述的显示面板，其中，还包括：
    遮光层，位于所述像素驱动电路层下，所述遮光层对应所述第一凹槽设有开孔，所述开孔的宽度大于或等于所述第一子凹槽的宽度。
  12. 根据权利要求1所述的显示面板，其中，所述衬底包括基底和位于所述基底上的阻挡层。
  13. 一种显示装置，其中，包括显示面板，所述显示面板包括透光显示区和与所述透光显示区相邻的主显示区，所述透光显示区的透光率大于所述主显示区的透光率，所述显示面板包括：
    衬底；
    像素驱动电路层，位于所述衬底上，包括多个层叠设置的无机绝缘层和多个设置在所述主显示区的像素驱动电路；
    有机绝缘层，位于所述像素驱动电路层上，包括第一有机绝缘子层和位于所述第一有机绝缘子层上的第二有机绝缘子层；以及
    发光层，位于所述有机绝缘层上，包括：位于所述主显示区内的多个第一像素和位于所述透光显示区内的多个第二像素，所述第一像素和所述第二像素与对应的所述像素驱动电路电性连接；
    其中，所述像素驱动电路层包括：设置在所述透光显示区且位于所述第二像素之间的多个第一凹槽，临近不同所述第二像素的所述第一凹槽相互连通，所述第一有机绝缘子层填充所述第一凹槽，位于所述第一凹槽处的所述第一有机绝缘子层远离所述衬底的表面到所述衬底的第一距离小于位于所述主显示区的所述第一有机绝缘子层远离所述衬底的表面到所述衬底的第二距离。
  14. 根据权利要求13所述的显示装置，其特征在于，所述像素驱动电路层还包括：
    多个设置在所述透光显示区且与所述第二像素对应设置的凸起部，所述第一凹槽环绕所述凸起部设置，位于所述凸起部上的第一有机绝缘子层远离所述衬底的表面到所述衬底的第三距离，大于位于所述第一凹槽上的所述第一有机绝缘子层远离所述衬底的表面到所述衬底的所述第一距离，且小于位于所述主显示区的所述第一有机绝缘子层远离所述衬底的表面到所述衬底的所述第二距离。
  15. 根据权利要求13所述的显示装置，其中，所述像素驱动电路层还包括：
    多个设置在所述透光显示区且与所述第二像素对应设置的第二凹槽，所述第二凹槽与相邻的所述第一凹槽连通设置。
  16. 根据权利要求15所述的显示装置，其中，
    位于所述第二凹槽处的第一有机绝缘子层远离所述衬底的表面到所述衬底的第四距离，等于位于所述第一凹槽处的所述第一有机绝缘子层远离所述衬底的表面到所述衬底的所述第一距离。
  17. 根据权利要求13所述的显示装置，其中，所述第一有机绝缘子层包括设置在所述透光显示区且与所述第一凹槽对应的第三凹槽；
    其中，所述第三凹槽的宽度小于或等于所述第一凹槽的宽度。
  18. 根据权利要求17所述的显示装置，其中，所述第三凹槽的侧壁在所述衬底上的投影宽度，小于或等于，所述第一凹槽的侧壁在所述衬底上的投影宽度。
  19. 根据权利要求13所述的显示装置，其中，所述第一凹槽包括多个层叠设置且相互连通的子凹槽；
    其中，远离所述衬底的所述子凹槽的宽度大于靠近所述衬底的所述子凹槽的宽度。
  20. 根据权利要求19所述的显示装置，其中，多个所述子凹槽包括第一子凹槽和第二子凹槽，所述第一子凹槽的宽度小于所述第二子凹槽的宽度，所述第二子凹槽的底面与所述第二子凹槽的侧壁之间所具有的夹角小于或等于115°。
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