WO2024219249A1 - プリント配線板用基板の信頼性試験方法 - Google Patents

プリント配線板用基板の信頼性試験方法 Download PDF

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Publication number
WO2024219249A1
WO2024219249A1 PCT/JP2024/014015 JP2024014015W WO2024219249A1 WO 2024219249 A1 WO2024219249 A1 WO 2024219249A1 JP 2024014015 W JP2024014015 W JP 2024014015W WO 2024219249 A1 WO2024219249 A1 WO 2024219249A1
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WO
WIPO (PCT)
Prior art keywords
substrate
printed wiring
test
indenter
load
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2024/014015
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English (en)
French (fr)
Japanese (ja)
Inventor
正樹 高橋
俊亮 大竹
裕一 乃万
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Resonac Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Resonac Corp filed Critical Resonac Corp
Priority to KR1020257034537A priority Critical patent/KR20250174619A/ko
Priority to JP2025515160A priority patent/JPWO2024219249A1/ja
Priority to CN202480002352.2A priority patent/CN119173752A/zh
Priority to US18/859,872 priority patent/US20250283793A1/en
Priority to EP24792524.1A priority patent/EP4700359A1/en
Publication of WO2024219249A1 publication Critical patent/WO2024219249A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N3/00—Investigating strength properties of solid materials by application of mechanical stress
    • G01N3/08—Investigating strength properties of solid materials by application of mechanical stress by applying steady tensile or compressive forces
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N19/00—Investigating materials by mechanical methods
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N3/00—Investigating strength properties of solid materials by application of mechanical stress
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N3/00—Investigating strength properties of solid materials by application of mechanical stress
    • G01N3/02—Details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N3/00—Investigating strength properties of solid materials by application of mechanical stress
    • G01N3/40—Investigating hardness or rebound hardness
    • G01N3/42—Investigating hardness or rebound hardness by performing impressions under a steady load by indentors, e.g. sphere, pyramid
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N2203/00—Investigating strength properties of solid materials by application of mechanical stress
    • G01N2203/0058—Kind of property studied
    • G01N2203/006—Crack, flaws, fracture or rupture
    • G01N2203/0062—Crack or flaws
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N2203/00—Investigating strength properties of solid materials by application of mechanical stress
    • G01N2203/0058—Kind of property studied
    • G01N2203/0076—Hardness, compressibility or resistance to crushing
    • G01N2203/0078—Hardness, compressibility or resistance to crushing using indentation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/162—Testing a finished product, e.g. heat cycle testing of solder joints

Definitions

  • This embodiment relates to a reliability test method for substrates for printed wiring boards.
  • Substrates used for printed wiring boards contain a resin component as an insulating material, but due to the difference in the thermal expansion coefficient between the resin component and inorganic components such as the conductor layer and semiconductor chip, stress occurs when the temperature changes, and cracks may occur in the substrate for printed wiring boards.
  • the stress caused by the difference in the thermal expansion coefficient is becoming larger, and the problem of cracks occurring due to temperature changes has become apparent.
  • the temperature cycle test is generally used as a reliability test method for substrates for printed wiring boards (see, for example, Patent Document 1).
  • Temperature cycle testing is an effective method for checking the long-term reliability of a test subject against temperature changes by repeatedly heating and cooling it. However, because temperature cycle testing requires several weeks to several months to obtain test results, a simpler reliability evaluation method is desired.
  • the objective of this embodiment is to provide a method for testing the reliability of substrates for printed wiring boards that can be easily implemented.
  • a method for testing the reliability of a substrate for a printed wiring board comprising: A reliability test method for a substrate for printed wiring boards, comprising measuring a load at which a crack occurs in the substrate for printed wiring boards using a nanoindenter.
  • This embodiment provides a method for testing the reliability of substrates for printed wiring boards that can be easily implemented.
  • FIG. 1 is a graph for explaining a load-displacement curve. 1 is a graph for explaining a load-contact stiffness curve.
  • FIG. 1 is a schematic diagram for explaining an observation position by an optical microscope in a liquid bath temperature cycle test.
  • FIG. 2 is a schematic diagram for explaining the positions from which test pieces were taken and the test areas for a destructive test using a nanoindenter.
  • FIG. 13 is a diagram for explaining a method of analyzing a load-contact stiffness curve.
  • 1 is a graph showing the correlation between the crack generation load W1 and the crack generation rate after a temperature cycle test (1,000 cycles), created from the results of the examples.
  • the reliability test method for a substrate for printed wiring boards according to the present embodiment is a reliability test method for a substrate for printed wiring boards, which uses a nanoindenter to measure the load at which a crack occurs in the substrate for printed wiring boards. According to the reliability test method of the present embodiment, the test does not require a long period of time as in the temperature cycle test, and therefore the reliability of a substrate for a printed wiring board can be easily evaluated.
  • the nanoindenter used in the reliability testing method of this embodiment is a microhardness tester that can press a tiny indenter into the surface of a sample to a depth of several nm to several tens of ⁇ m and measure the relationship between the displacement and load at that time.
  • the substrate for printed wiring boards that is the test subject of the reliability test method of this embodiment is not particularly limited, and any known substrate for printed wiring boards can be used as the test subject.
  • the insulating layer of the substrate for printed wiring board may be a layer containing a resin and not containing glass cloth, or may be a layer containing a resin and glass cloth.
  • a layer containing a cured resin and glass cloth is preferable.
  • the term "cured resin” means a cured product containing at least a resin and not containing glass cloth, and is preferably a cured product of a thermosetting resin composition containing a thermosetting resin.
  • the thermosetting resin composition may contain, as necessary, a curing agent, a curing accelerator, an inorganic filler, and the like as components other than the thermosetting resin.
  • the insulating layer of the substrate for printed wiring board may be a single layer or multiple layers.
  • a specific example of a test subject for the reliability test method of this embodiment is a substrate for printed wiring boards having two or more layers containing a cured resin and a glass cloth.
  • the substrate for printed wiring boards may have a member other than the insulating layer that a substrate for printed wiring boards may generally have, such as a conductor layer formed on the surface of the substrate, a conductor layer formed between insulating layers, a semiconductor chip mounted on the surface of the substrate, etc.
  • the content of the cured resin in the layer containing the cured resin and the glass cloth is not particularly limited, and may be, for example, 25 to 75 mass %, 30 to 70 mass %, or 35 to 65 mass %.
  • the thickness of each layer containing the cured resin and the glass cloth is not particularly limited and may be, for example, 200 to 1,900 ⁇ m, 500 to 1,800 ⁇ m, or 800 to 1,700 ⁇ m.
  • the number of layers containing a cured resin and a glass cloth is not particularly limited, and may be, for example, 2 to 19 layers, 5 to 18 layers, or 8 to 17 layers.
  • the position of the substrate for printed wiring boards where the destructive test is performed using the nanoindenter is not particularly limited, but it is preferable to select a location where cracks are likely to occur in a temperature cycle test, for example.
  • the location where cracks are likely to occur in a temperature cycle test is a location where stress is likely to occur in the substrate for printed wiring boards, so that the crack occurrence load can be easily obtained within the range of the destructive test using the nanoindenter.
  • an example of a place where a destructive test is performed is preferably the end of the substrate for printed wiring boards, from the viewpoint of facilitating acquisition of the crack initiation load.
  • the indenter of the nanoindenter is pressed into the cross section of the substrate for printed wiring boards.
  • the substrate for printed wiring boards is obtained by cutting and processing the outer shape in a plan view into a desired shape, so the end face of the substrate for printed wiring boards corresponds to the cross section.
  • an example of a location where the destructive test is performed is approximately the center in the thickness direction of the substrate for printed wiring boards. That is, the location where the destructive test is performed is preferably a cross section of an end portion of the substrate for printed wiring boards in a plan view, and also approximately the center of the substrate for printed wiring boards in a cross-sectional view.
  • the substrate for printed wiring board it is preferable to process the substrate for printed wiring board by cutting or the like so as to form a test piece including an area for carrying out the destructive test, in order to mount it on a nanoindenter. From the viewpoint of suppressing the occurrence of variations in test results due to surface irregularities, it is preferable to smooth the surface of the test piece into which the indenter of the nanoindenter is pressed by polishing before or after the test piece is taken.
  • the polishing method is not particularly limited, but mechanical polishing or chemical mechanical polishing is preferable.
  • test specimens taken from the substrate for printed wiring boards may be pretreated before the destructive test.
  • pretreatment is heating and cooling. By performing heating and cooling as pretreatment, internal stress accumulates in the test specimen, making it easier to obtain the crack initiation load within the range of destructive testing using a nanoindenter.
  • the type of the indenter of the nanoindenter is not particularly limited, but from the viewpoint of versatility, a Berkovich indenter is preferred.
  • the Berkovich indenter is an indenter in which the shape of the surface on the side that presses into the test piece is a triangular pyramid (edge spacing 115°).
  • the type and edge spacing of the indenter are not particularly limited, and a Berkovich indenter (edge spacing 100°), a Rockwell indenter, a Vickers indenter, a Knoop indenter, or a Shore indenter may be used.
  • the indenter of a nanoindenter is very small, when testing a substrate containing multiple materials, such as a layer containing a cured resin and glass cloth, the load-displacement curve obtained may change depending on the position where the indenter is pressed.
  • the measurement subject is a substrate having a layer containing a cured resin and glass cloth
  • the position where the indenter is pressed is the glass cloth or the cured resin close to the glass cloth
  • cracks are likely to occur in the glass cloth
  • the cured resin is located a certain distance away from the glass cloth
  • cracks are likely to occur at the interface between the glass cloth and the cured resin and in the cured resin
  • the cured resin is located even further away from the glass cloth, only cracks are likely to occur in the cured resin.
  • the shortest distance between the glass cloth and the center position on the cured resin product where the indenter is pressed may be, for example, 1 to 10 ⁇ m, 2 to 8 ⁇ m, or 3 to 7 ⁇ m.
  • the position at which the indenter is pressed can be adjusted using the optical microscope and micrometer attached to the nanoindenter.
  • the pressing speed of the indenter is not particularly limited, but may be, for example, 15 to 55 mN/s, 25 to 50 mN/s, or 35 to 45 mN/s.
  • the temperature at which the destructive test is carried out is not particularly limited, but may be 5 to 50°C, 10 to 40°C, or 20 to 30°C from the viewpoint of workability.
  • the atmosphere in which the destructive test is carried out is not particularly limited, but from the viewpoint of workability, it is preferable to carry out the test in air.
  • FIG. 1 An example of a load-displacement curve is shown in FIG.
  • the load tends to increase overall as the depth to which the indenter is pressed into the test piece, i.e., the displacement, increases.
  • region A in FIG. 1 A curve (hereinafter also referred to as a "load-contact stiffness curve") obtained by plotting the contact stiffness calculated as the slope of the load-displacement curve shown in Figure 1 on the vertical axis and the load on the horizontal axis is shown in Figure 2.
  • region A in Figure 1 appears as a downward peak where the contact stiffness decreases.
  • this peak is referred to as the "crack generation peak.”
  • the load at which the crack generation peak appears correlates with the crack generation rate in a temperature cycle test. Therefore, the reliability of a printed wiring board substrate can be evaluated by measuring the load at which the crack generation peak appears (hereinafter also referred to as the "crack generation load"). For example, by understanding in advance the correlation between the crack generation load and the crack generation rate in a temperature cycle test, it is possible to predict the crack generation rate in a temperature cycle test from the crack generation load.
  • a threshold value may be set for the magnitude of the crack occurrence peaks, and a crack occurrence peak having a predetermined magnitude or more may be used as an index for reliability evaluation.
  • the threshold value for the magnitude of the crack occurrence peaks may be, for example, the contact stiffness reduction rate (%) calculated by the following formula (1).
  • Contact stiffness reduction rate (%) (S1-S2) x 100/S1 (1)
  • S1 means the contact stiffness when the contact stiffness starts to decrease at the crack generation peak
  • S2 means the contact stiffness at the peak top of the crack generation peak.
  • the "contact stiffness when the contact stiffness starts to decrease" can be determined by, for example, the method described in the Examples.
  • the “peak top” refers to the apex of the crack generation peak (the point showing the minimum value of the contact stiffness at the peak).
  • the load that gives the peak top of the crack initiation peak may be used for reliability evaluation.
  • the crack generation peak that is appropriate as an indicator of reliability can vary depending on the position where the indenter is pressed. Therefore, it is preferable to determine the position where the indenter is pressed, and perform temperature cycle tests and destructive tests using a nanoindenter in advance on multiple types of test objects under conditions where the indenter is pressed into that position, and to identify, among the crack generation peaks that appear, those that have a high correlation with the temperature cycle test.
  • the core layers of the obtained substrates 1 to 6 for printed wiring boards are different from each other.
  • a silicon semiconductor chip (rectangular with external dimensions of 20 mm x 20 mm in plan view and a thickness of 0.775 mm) was placed in the center of one side of the printed wiring board substrate obtained above, with the circuit side facing down, and the gap between the semiconductor chip and the substrate was sealed with a liquid sealant (Resonac Corporation, product name "CEL-C-3730 series”) to obtain semiconductor chip-mounted substrates 1 to 6 for liquid bath temperature cycle testing.
  • a liquid sealant Resonac Corporation, product name "CEL-C-3730 series
  • the observation range was an area of 1,500 ⁇ m x 1,500 ⁇ m per position.
  • the above eight locations were observed for each of the five substrates, and the ratio of locations where cracks were observed out of a total of 40 locations [number of locations where cracks were observed x 100/40 locations] (unit: %) was defined as the crack occurrence rate in the liquid bath temperature cycle test.
  • FIG. 4 shows a transparent perspective view for explaining the positions where the test pieces were taken and the positions where the destructive tests were performed on the test pieces.
  • the printed wiring board substrates 1 to 6 obtained in Production Examples 1 to 6 were cut, and test pieces having dimensions of 1.5 mm (cutting width W) ⁇ 60 mm (substrate length L) ⁇ 1.7 to 2.0 mm (substrate thickness T), as shown in portion 20 in FIG. 4, were taken.
  • the test area of the collected test piece where the destructive test is performed is the area shown by area 30 in Fig. 4.
  • Area 30 is a cross section of an end portion of substrate 1 for printed wiring boards, and is approximately the center of substrate 1 for printed wiring boards in a cross-sectional view. Area 30 is located at a distance of about 10 mm from a corner of substrate 1 for printed wiring boards (distance B in Fig. 4).
  • the cross section of the printed wiring board substrate including the region 30 was mechanically polished in advance using abrasive paper of No. 4000.
  • the obtained test piece was heat-treated at 260° C. for 6 hours in an air atmosphere, and cooled to room temperature, and was used as the object of measurement with the nanoindenter.
  • an approximation line of the load-contact stiffness curve is found by the least squares method, and this is called "approximation line 1."
  • the absolute value D of the difference between the contact stiffness S2 and the contact stiffness of approximate line 1 at W2 is calculated, and the load that gives a contact stiffness of S2 + 0.7D is defined as W2A , and the load that gives a contact stiffness of S2 + 0.5D is defined as W2B .
  • an approximate line of the load-contact stiffness curve is found using the least squares method, and this is defined as "approximate line 2.”
  • the contact stiffness at the intersection of the approximated lines 1 and 2 obtained above was defined as S1.
  • FIG. 6 shows a graph in which the crack generation load W1 obtained above is plotted on the horizontal axis and the crack generation rate after the liquid bath temperature cycle test (1,000 cycles) is plotted on the vertical axis, and a linear approximation line obtained by the least squares method of the above plot is shown.
  • the reliability test method of this embodiment is useful as a reliability test method for substrates for printed wiring boards.
  • Substrate for printed wiring board 10 Observation area 20 Part of test piece taken 30 Test area W Width L Length T Thickness B Distance S1, S2 Contact stiffness W 1A , W 1B , W 2A , W 2B , W S2 Load A Area

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  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Investigating Strength Of Materials By Application Of Mechanical Stress (AREA)
  • Measuring Or Testing Involving Enzymes Or Micro-Organisms (AREA)
PCT/JP2024/014015 2023-04-19 2024-04-05 プリント配線板用基板の信頼性試験方法 Ceased WO2024219249A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020257034537A KR20250174619A (ko) 2023-04-19 2024-04-05 프린트 배선판용 기판의 신뢰성 시험 방법
JP2025515160A JPWO2024219249A1 (https=) 2023-04-19 2024-04-05
CN202480002352.2A CN119173752A (zh) 2023-04-19 2024-04-05 印刷线路板用基板的可靠性试验方法
US18/859,872 US20250283793A1 (en) 2023-04-19 2024-04-05 Reliability test method for printed wiring board substrate
EP24792524.1A EP4700359A1 (en) 2023-04-19 2024-04-05 Printed circuit board substrate reliability testing method

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JP2023-068328 2023-04-19
JP2023068328 2023-04-19

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CN119437897B (zh) * 2025-01-07 2025-03-21 高邮鑫润龙印刷科技有限公司 一种印刷材料检测机构及具有该检测机构的印刷机

Citations (8)

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Publication number Priority date Publication date Assignee Title
JPH07260658A (ja) * 1994-12-13 1995-10-13 Shimadzu Corp 薄膜の剥離荷重測定方法
JPH07325029A (ja) * 1994-05-31 1995-12-12 Nec Corp 薄膜物性評価装置
JP2001108586A (ja) * 1999-10-13 2001-04-20 Masaki Shiratori 材料試験機
US6339958B1 (en) * 1998-12-10 2002-01-22 Advanced Micro Devices, Inc. Adhesion strength testing using a depth-sensing indentation technique
JP2002151848A (ja) * 2000-11-10 2002-05-24 Mitsubishi Plastics Ind Ltd ビルドアップ多層プリント配線基板用コア基板
JP2004170160A (ja) * 2002-11-19 2004-06-17 National Institute Of Advanced Industrial & Technology 無機質膜の剥離力測定方法及び測定装置
JP2006093618A (ja) 2004-09-27 2006-04-06 Ibiden Co Ltd 多層プリント配線板
JP2012146990A (ja) * 2012-02-22 2012-08-02 Sumitomo Bakelite Co Ltd 多層回路基板、多層回路基板の製造方法および半導体装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07325029A (ja) * 1994-05-31 1995-12-12 Nec Corp 薄膜物性評価装置
JPH07260658A (ja) * 1994-12-13 1995-10-13 Shimadzu Corp 薄膜の剥離荷重測定方法
US6339958B1 (en) * 1998-12-10 2002-01-22 Advanced Micro Devices, Inc. Adhesion strength testing using a depth-sensing indentation technique
JP2001108586A (ja) * 1999-10-13 2001-04-20 Masaki Shiratori 材料試験機
JP2002151848A (ja) * 2000-11-10 2002-05-24 Mitsubishi Plastics Ind Ltd ビルドアップ多層プリント配線基板用コア基板
JP2004170160A (ja) * 2002-11-19 2004-06-17 National Institute Of Advanced Industrial & Technology 無機質膜の剥離力測定方法及び測定装置
JP2006093618A (ja) 2004-09-27 2006-04-06 Ibiden Co Ltd 多層プリント配線板
JP2012146990A (ja) * 2012-02-22 2012-08-02 Sumitomo Bakelite Co Ltd 多層回路基板、多層回路基板の製造方法および半導体装置

Non-Patent Citations (1)

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Title
See also references of EP4700359A1

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CN119173752A (zh) 2024-12-20
JPWO2024219249A1 (https=) 2024-10-24
KR20250174619A (ko) 2025-12-12
US20250283793A1 (en) 2025-09-11
EP4700359A1 (en) 2026-02-25
TW202446174A (zh) 2024-11-16

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