WO2024176726A1 - 積層セラミックコンデンサ - Google Patents

積層セラミックコンデンサ Download PDF

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Publication number
WO2024176726A1
WO2024176726A1 PCT/JP2024/002438 JP2024002438W WO2024176726A1 WO 2024176726 A1 WO2024176726 A1 WO 2024176726A1 JP 2024002438 W JP2024002438 W JP 2024002438W WO 2024176726 A1 WO2024176726 A1 WO 2024176726A1
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Prior art keywords
multilayer ceramic
internal electrode
ceramic capacitor
electrode layer
regions
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English (en)
French (fr)
Japanese (ja)
Inventor
和博 西林
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Priority to JP2025502197A priority Critical patent/JPWO2024176726A1/ja
Priority to CN202480009783.1A priority patent/CN120548580A/zh
Publication of WO2024176726A1 publication Critical patent/WO2024176726A1/ja
Priority to US19/263,957 priority patent/US20250336603A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/008—Selection of materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/012—Form of non-self-supporting electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H01G4/1209—Ceramic dielectrics characterised by the ceramic dielectric material
    • H01G4/1218—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates
    • H01G4/1227—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates based on alkaline earth titanates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H01G4/2325—Terminals electrically connecting two or more layers of a stacked or rolled capacitor characterised by the material of the terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/248—Terminals the terminals embracing or surrounding the capacitive element, e.g. caps

Definitions

  • the present invention relates to a multilayer ceramic capacitor.
  • Patent Document 1 describes a technology for thinning the external electrodes by providing a Ni layer and a Sn plating layer provided on the Ni layer, and specifying the thickness of the Ni layer and the Si content relative to the Ni content in the Ni layer.
  • the objective of the present invention is to provide a multilayer ceramic capacitor that can achieve both thin external electrodes and improved moisture resistance.
  • the inventors discovered that by forming a diffusion region at the boundary between the opposing portions and the lead-out portions of the internal electrode layers that constitute a multilayer ceramic capacitor, where both the metal components contained in the opposing portions and the metal components contained in the lead-out portions are detectable, the moisture resistance of the multilayer ceramic capacitor can be improved, leading to the completion of the present invention.
  • the present invention provides a multilayer ceramic capacitor having a laminate in which a plurality of internal electrode layers and dielectric layers are laminated, and external electrodes that are arranged in a length direction intersecting with the lamination direction of the laminate and connect to the internal electrode layers,
  • the internal electrode layer includes two regions in the longitudinal direction, the two regions having at least a part of a metal component different from each other,
  • a diffusion region is formed at the boundary between the two regions, where metal components contained in both regions can be detected.
  • the present invention makes it possible to provide a multilayer ceramic capacitor that achieves both thin external electrodes and improved moisture resistance.
  • FIG. 1 is a diagram showing the appearance of a multilayer ceramic capacitor according to the present invention
  • 2 is a cross-sectional view of the multilayer ceramic capacitor of the present invention (first embodiment) taken along line II-II in FIG.
  • 3 is a cross-sectional view of the multilayer ceramic capacitor of the present invention (first embodiment) taken along line III-III in FIG. 2.
  • FIG. 2 is an exploded schematic view showing the structure of the inner layer portion.
  • 2 is a cross-sectional view of the multilayer ceramic capacitor of the present invention (second embodiment) taken along line II-II in FIG. 1.
  • 6 is a cross-sectional view of the multilayer ceramic capacitor of the present invention (second embodiment) taken along line VI-VI in FIG. 5.
  • FIG. 1 is an external view of the multilayer ceramic capacitor 1.
  • FIG. 2 is a cross-sectional view (LT cross-sectional view) of the multilayer ceramic capacitor 1 cut along line II-II at the center of the width direction W shown in FIG. 1.
  • FIG. 3 is a cross-sectional view (LW cross-sectional view) of the multilayer ceramic capacitor 1 cut along line III-III shown in FIG. 2.
  • FIG. 4 is a schematic diagram showing the structure of an inner layer portion 3.
  • the structure of the multilayer ceramic capacitor 1 will be described using the direction in which the dielectric layers and the internal electrode layers are stacked as a stacking direction T, a length direction L perpendicular to the stacking direction T, and a width direction W perpendicular to the stacking direction T and the length direction L.
  • the stacking direction T, the length direction L, and the width direction W are perpendicular to each other, but they are not necessarily perpendicular to each other and may intersect each other.
  • the multilayer ceramic capacitor 1 includes a laminate 2 having a rectangular parallelepiped shape.
  • the laminate 2 includes an inner layer portion 3, and has a pair of first and second main surfaces A1 and A2 that face each other in the stacking direction T, a pair of first and second end surfaces C1 and C2 that face each other in a length direction L that is perpendicular to the stacking direction T, and a pair of first and second side surfaces B1 and B2 that face each other in a width direction W that is perpendicular to both the stacking direction T and the length direction L.
  • the multilayer ceramic capacitor 1 of the embodiment is often used with the second main surface A2 side facing in the mounting direction and the first main surface A1 facing up.
  • first main surface A1 and the second main surface A2 they will be collectively referred to as the main surface A. If there is no need to distinguish between the first side surface B1 and the second side surface B2, they will be collectively referred to as the side surface B. If there is no need to distinguish between the first end surface C1 and the second end surface C2, they will be collectively referred to as the end surface C.
  • the dimensions of the multilayer ceramic capacitor 1 are not particularly limited, but for example, the dimension in the stacking direction T can be approximately 0.1 mm to 2.5 mm, the dimension in the length direction L can be approximately 0.1 mm to 3.2 mm, and the dimension in the width direction W can be approximately 0.1 mm to 2.5 mm.
  • the inner layer 3 is made up of a plurality of dielectric layers 5 and a plurality of internal electrode layers 6 stacked together.
  • the internal electrode layers 6 are made up of a first internal electrode layer 6a and a second internal electrode layer 6b.
  • the first internal electrode layer 6a and the second internal electrode layer 6b are disposed on top of the dielectric layers 5a and 5b, respectively.
  • the internal electrode layer 6 extends in the length direction L and has a rectangular shape when viewed in a plan view from the stacking direction T.
  • the internal electrode layers 6 have opposing portions OP where adjacent internal electrode layers 6 face each other in the stacking direction T to form a capacitance, and lead-out portions DP that extend from the opposing portions OP to the end face C and connect to one of the external electrodes 4.
  • the first internal electrode layer 6a is connected to the first external electrode 4a and is separated from the second external electrode 4b.
  • the second internal electrode layer 6b is connected to the second external electrode 4b and is separated from the first external electrode 4a.
  • the internal electrode layer 6 can be formed using metals such as Ni, Cu, Ag, Pd, and Au, Ag-Pd alloys, or compounds containing these metal elements or alloys with other metals, but the metal components contained in the facing portion OP and the metal components contained in the lead-out portion DP are all or partly different. Also, a specific metal component may be contained in only one of the facing portion OP and the lead-out portion DP.
  • the metal components contained in the opposing portion OP and the draw-out portion DP can be appropriately selected, but for example, if one of the opposing portion OP and the draw-out portion DP contains Cu and the other contains Ni instead of Cu, a diffusion region SR can be formed at the boundary between the opposing portion OP and the draw-out portion DP where the metal components Cu and Ni diffuse into each other or from one to the other. Also, if one of the opposing portion OP and the draw-out portion DP contains Cu and the other contains Ag instead of Cu, a diffusion region SR can be formed at the boundary between the opposing portion OP and the draw-out portion DP where the metal components Cu and Ni diffuse into each other or from one to the other.
  • the diffusion region SR is formed by diffusing the metal components contained in the opposing portion OP and the metal components contained in the pull-out portion DP into each other or from one to the other to an extent that both can be detected, and the metal components do not necessarily have to be distributed uniformly. Therefore, the concentration of the metal components in the diffusion region SR may vary depending on the position.
  • the diffusion region SR volume expansion occurs due to the diffusion of the metal components, and the thickness in the stacking direction T increases, so that gaps that may exist at the interface between the internal electrode layer 6 and the dielectric layer 5 can be filled. As a result, it is possible to prevent moisture from penetrating into the laminate 2 from the end face C, and the moisture resistance of the multilayer ceramic capacitor is improved.
  • the thickness of the diffusion region SR in the stacking direction T is usually greater than the thicknesses of the opposing portion OP and the lead portion DP in the stacking direction, but since the diffusion region SR expands in volume depending on the size of the gap at the interface between the internal electrode layer 6 and the dielectric layer 5, depending on the size of the gap at the interface between the internal electrode layer 6 and the dielectric layer 5, the thickness of the diffusion region SR in the stacking direction T is not necessarily greater than the thicknesses of the opposing portion OP and the lead portion DP in the stacking direction T.
  • a diffusion region SR is formed at the boundary between the opposing portion OP and the lead-out portion DP, but the present invention is not limited to this.
  • Two regions containing at least some of the metal components different from each other may be provided at any position in the longitudinal direction L of the internal electrode layer 6, and a diffusion region SR in which the metal components contained in both regions are detected may be formed at the boundary between the two regions.
  • a diffusion region SR does not necessarily need to be formed in all of the multiple internal electrode layers constituting the laminate 2, and may be formed only in some of the multiple internal electrode layers. For example, when a diffusion region SR is provided in the internal electrode layer 6 that contacts the outer layer portion 7, the effect of improving moisture resistance is significant, so the diffusion region SR may be formed only in this internal electrode layer 6.
  • the dielectric layer 5 is made of a dielectric material.
  • a dielectric ceramic containing a component such as BaTiO 3 , CaTiO 3 , SrTiO 3 , or CaZrO 3 can be used as the dielectric material.
  • the dielectric material may also be one in which a subcomponent such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound is added to the main component.
  • the thickness of the dielectric layer 5 is not particularly limited, but can be, for example, about 0.3 ⁇ m to 2.0 ⁇ m in the effective capacitance formation area formed by the first internal electrode layer 6a and the second internal electrode layer 6b.
  • the number of dielectric layers 5 is not particularly limited, but can be, for example, 1 to 6,000 layers in the effective capacitance formation area formed by the first internal electrode layer 6a and the second internal electrode layer 6b.
  • an outer layer 7 which is composed only of a dielectric layer and does not have an internal electrode layer 6 formed thereon.
  • the thickness of the outer layer 7 is not limited, but can be, for example, 15 ⁇ m to 150 ⁇ m.
  • the thickness of the dielectric layer in the outer layer 7 may be greater than the thickness of the dielectric layer in the effective region of capacitance formation where the internal electrode layer 6 is formed.
  • the material of the dielectric layer in the outer layer may be different from the material of the dielectric layer in the inner layer.
  • Figure 4 shows the inner layer 3 broken down into individual dielectric layers 5 in the stacking direction T.
  • the internal electrode layers 6 and the dielectric layers 5 are alternately stacked to form the inner layer portion 3.
  • the internal electrode layers 6 are composed of a first internal electrode layer 6a and a second internal electrode layer 6b, and the first internal electrode layer 6a and the second internal electrode layer 6b are disposed on the dielectric layers 5a and 5b, respectively.
  • the internal electrode layer 6 has an opposing portion OP where adjacent internal electrode layers 6 face each other in the stacking direction T to form a capacitance, and a lead-out portion DP that extends from the opposing portion OP to the end face C and connects to one of the external electrodes 4.
  • a diffusion region SR is formed where both the metal components contained in the opposing portion OP and the metal components contained in the lead-out portion DP are detected.
  • a conductive paste for forming the opposing portion OP and a conductive paste for forming the lead-out portion DP are prepared during manufacturing.
  • the conductive paste contains a metal powder that serves as a conductor, an organic solvent, a binder, and a dispersant, and is sintered on the dielectric layer 5 to form the internal electrode layer 6, but the conductive paste for forming the opposing portion OP and the conductive paste for forming the lead-out portion DP contain different metal components.
  • a conductive paste for forming the facing portion OP is printed on the ceramic green sheet that will become the dielectric layer 5 in a predetermined shape to form the facing portion OP, and then a conductive paste for forming the lead portion DP is printed in a predetermined shape to form the lead portion DP.
  • the printing order is not limited to this. Also, the printing method may be a screen printing method, a jet printer method, or the like.
  • the multiple material sheets thus formed are stacked together with the sheet that forms the outer layer portion 7 and cut to a predetermined shape, and then fired to form the inner layer portion 3 in which the dielectric layers 5 and the internal electrode layers 6 are stacked, and a diffusion region SR is formed at the boundary between the opposing portion OP and the lead-out portion DP, where the metal components of the opposing portion OP and the lead-out portion DP diffuse into both portions or from one portion to the other.
  • FIG. 5 shows a state in which two boundaries between two regions having different metal components are provided in two locations in the length direction L of the lead portion DP to form two diffusion regions SR 1 and SR 2.
  • the left and right regions centered on the diffusion region SR 1 contain different metal components
  • the left and right regions centered on the diffusion region SR 2 contain different metal components
  • the region to the right of the diffusion region SR 1 and the region to the left of the diffusion region SR 2 do not necessarily contain different metal components, and may be the same.
  • Fig. 6 is an LW cross-sectional view taken along line VI-VI shown in Fig. 5, showing the first internal electrode layer 6a as viewed from the stacking direction T.
  • Fig. 6 shows the diffusion regions SR 1 and SR 2 extending perpendicular to the length direction L and arranged parallel to each other in strips, but they do not necessarily have to be perpendicular to the length direction L, and they do not necessarily have to be continuous strips.
  • the thickness of the internal electrode layer 6 is not particularly limited, but can be, for example, about 0.3 ⁇ m to 1.5 ⁇ m.
  • ⁇ Moisture resistance load test> (a) A conventional multilayer ceramic capacitor without a diffusion region, (b) a multilayer ceramic capacitor with a diffusion region SR at the boundary between the opposing portion OP and the lead portion DP of the internal electrode layer 6 (the number of diffusion regions is one), and (c) a multilayer ceramic capacitor with a diffusion region at the boundary between the opposing portion OP and the lead portion DP of the internal electrode layer 6 and at the boundary provided in the lead portion (the number of diffusion regions is two) were used as samples, and a humidity load test was performed using 72 test pieces for each of the three types of multilayer ceramic capacitors (a), (b), and (c).
  • the humidity load test was performed by measuring the insulation resistance IR ( ⁇ ) after 100 hours under conditions of a temperature of 85° C., a humidity of 85% RH, and an applied voltage of 6.3 V, and a sample with LogIR ⁇ 7.5 was judged to be defective.
  • the evaluation of each of the multilayer ceramic capacitors (a), (b), and (c) was judged as ⁇ : excellent, ⁇ : good, and ⁇ : defective based on the number of samples judged to be defective and the logarithmic value LogIR of the insulation resistance.
  • the number of defective samples was 4 out of 72 samples of the multilayer ceramic capacitor of (a). Although there were no defective samples in either the multilayer ceramic capacitor (b) or the multilayer ceramic capacitor (c), the multilayer ceramic capacitor (c) had a higher average LogIR than the multilayer ceramic capacitor (b), and it was confirmed that the multilayer ceramic capacitor maintained better insulation resistance.
  • the average LogIR value after testing of the multilayer ceramic capacitor (b) was 7.9, and the average LogIR value after testing of the multilayer ceramic capacitor (c) was 8.2.
  • a first external electrode 4a and a second external electrode 4b are formed on the first end face C1 and the second end face C2 of the laminate 2, respectively.
  • the end of the lead-out portion DP of the first internal electrode layer 6a is exposed to the first end face C1 and is electrically connected to the first external electrode 4a.
  • the end of the lead-out portion DP of the second internal electrode layer 6b is exposed to the second end face C2 and is electrically connected to the second external electrode 4b.
  • the first external electrode 4a has a first base electrode layer 41a and a first plating layer 42a arranged on the first base electrode layer 41a
  • the second external electrode 4b has a second base electrode layer 41b and a second plating layer 42b arranged on the second base electrode layer 41b.
  • the first external electrode 4a and the second external electrode 4b do not necessarily have to have such a two-layer structure.
  • the first base electrode layer 41a of the first external electrode 4a is disposed on the first end face C1.
  • the first base electrode layer 41a is connected to the first internal electrode layer 6a.
  • the first base electrode layer 41a is formed to extend from the first end face C1 to a portion of the first main surface A1 and a portion of the second main surface A2, as well as a portion of the first side surface B1 and a portion of the second side surface B2.
  • the second base electrode layer 41b of the second external electrode 4b is disposed on the second end face C2.
  • the second base electrode layer 41b is connected to the second internal electrode layer 6b.
  • the second base electrode layer 41b is formed to extend from the second end face C2 to a portion of the first main surface A1 and a portion of the second main surface A2, as well as a portion of the first side surface B1 and a portion of the second side surface B2.
  • the first internal electrode layer 6a and the second internal electrode layer 6b can be formed using, for example, metals such as Ni, Cu, Ag, Pd, Au, Ag-Pd alloys, or compounds containing these metal elements or alloys with other metals.
  • the first base electrode layer 41a and the second base electrode layer 41b constituting the first external electrode 4a and the second external electrode 4b, respectively, can be formed using, for example, any of Cu, Ni, Ag, Pd, Ag-Pd alloys, Au, etc.
  • the metal components contained in the first internal electrode layer 6a and the first base electrode layer 41a can be appropriately selected, but the metal components contained in the lead portion DP of the first internal electrode layer 6a and the metal components contained in the first base electrode layer 41a are all or partly different. Also, a specific metal component may be contained in only one of the lead portion DP of the first internal electrode layer 6a and the first base electrode layer 41a. For example, if either the lead portion DP of the first internal electrode layer 6a or the first base electrode layer 41a contains Cu and the other contains Ni instead of Cu, a diffusion region SRc is formed at the boundary between the lead portion DP of the first internal electrode layer 6a and the first base electrode layer 41a, where the metal components Cu and Ni diffuse into each other or from one to the other.
  • a diffusion region SRc is formed at the boundary between the lead portion DP of the first internal electrode layer 6a and the first base electrode layer 41a, where the metal components Cu and Ni diffuse into each other or from one to the other.
  • the metal components contained in the second internal electrode layer 6b and the second base electrode layer 41b can be appropriately selected, but the metal components contained in the lead portion DP of the second internal electrode layer 6b and the metal components contained in the second base electrode layer 41b are all or partly different. Also, a specific metal component may be contained in only one of the lead portion DP of the second internal electrode layer 6b and the second base electrode layer 41b.
  • a diffusion region SRc is formed at the boundary between the lead portion DP of the second internal electrode layer 6b and the second base electrode layer 41b, where the metal components Cu and Ni diffuse into each other or from one to the other.
  • a diffusion region SRc is formed at the boundary between the lead portion DP of the second internal electrode layer 6b and the second base electrode layer 41b, where the metal components Cu and Ni diffuse into each other or from one to the other.
  • the first base electrode layer 41a and the second base electrode layer 41b are each formed of a Ni layer containing Ni and a ceramic material. Such a Ni layer can be formed by firing together with the first internal electrode layer 6a and the second internal electrode layer 6b.
  • the Ni layer is preferably disposed directly on the laminate 2.
  • the diffusion region SRc is formed by mutual diffusion or diffusion from one to the other to a degree that allows detection of both the metal components contained in the lead portion DP of the first internal electrode layer 6a and the metal components contained in the first base electrode layer 41a, or both the metal components contained in the lead portion DP of the second internal electrode layer 6b and the metal components contained in the second base electrode layer 41b, and the metal components do not necessarily have to be distributed uniformly. Therefore, the concentration of the metal components in the diffusion region SR may vary depending on the position.
  • the thickness of the diffusion region SRc in the stacking direction T is usually larger than the thickness of the lead portion DP in the stacking direction T, but the diffusion region SRc expands in volume depending on the size of the gap at the interface between the lead portion DP of the internal electrode layer 6 and the dielectric layer 5. Therefore, depending on the size of the gap at the interface between the internal electrode layer 6 and the dielectric layer 5, the thickness of the diffusion region SRc in the stacking direction T is not necessarily larger than the thickness of the lead portion DP in the stacking direction T. In addition, such a diffusion region SRc does not necessarily need to be formed in all of the multiple internal electrode layers 6 constituting the laminate 2, and may be formed only in some of the multiple internal electrode layers 6.
  • the diffusion region SRc when the diffusion region SRc is provided at the boundary between the lead portion DP of the internal electrode layer 6 that contacts the outer layer portion 7 and the base electrode layer, the effect of improving moisture resistance is large, so the diffusion region SRc may be formed only in this part.
  • the first plating layer 42a and the second plating layer 42b are arranged to cover the first base electrode layer 41a and the second base electrode layer 41b, respectively.
  • the first plating layer 42a and the second plating layer 42b may contain, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, an Ag-Pd alloy, Au, etc.
  • the first plating layer 42a and the second plating layer 42b may each be formed of multiple layers.
  • the first plating layer 42a and the second plating layer 42b preferably have a two-layer structure in which a Sn plating layer is formed on a Ni plating layer.
  • the Ni plating layer prevents the first base electrode layer 41a and the second base electrode layer 41b from being eroded by solder when mounting the multilayer ceramic capacitor 1.
  • the Sn plating layer also improves the wettability of the solder when mounting the multilayer ceramic capacitor 1. This makes it easier to mount the multilayer ceramic capacitor 1.
  • the boundary between the extension portion DP of the first internal electrode layer 6a and the first base electrode layer 41a, or the boundary between the extension portion DP of the second internal electrode layer 6b and the second base electrode layer 41b, corresponds to the boundary between the extension portion DP and the external electrode 4 of the present invention.
  • the metal component contained in the region in contact with the boundary of the first base electrode layer 41a or the second base electrode layer 41b corresponds to the metal component contained in the region in contact with the boundary of the external electrode of the present invention.
  • a multilayer ceramic capacitor having a two-layer structure of an external electrode 4 consisting of a base electrode layer and a plating layer has been described.
  • the present invention is not limited to such an external electrode structure and can be applied to multilayer ceramic capacitors having external electrodes of any shape.
  • a diffusion region SRc at the boundary between the lead portion DP and the external electrode 4, in which both the metal component contained in the region adjacent to the boundary of the lead portion DP and the metal component contained in the region adjacent to the boundary of the external electrode 4 are detected, the moisture resistance of the multilayer ceramic capacitor can be improved.
  • the multilayer ceramic capacitor 1 of the present invention is provided with the diffusion regions SR, SR 1 , SR 2 , and SRc, thereby filling gaps that may exist at the interfaces between the internal electrode layers 6 and the dielectric layers 5. This makes it possible to prevent moisture from penetrating into the laminate 2 from the end faces C, thereby making it possible to thin the external electrodes 4 and increase the volume of the laminate 2.
  • the thickness in the longitudinal direction L of the external electrodes 4 of the multilayer ceramic capacitor 1 is 1.0 to 50.0 ⁇ m.
  • a two-terminal multilayer ceramic capacitor 1 has been described, but the present invention is not limited to two-terminal multilayer ceramic capacitors, and can also be applied to multi-terminal multilayer ceramic capacitors with three or more terminals.
  • the above describes an embodiment of the present invention, but the present invention is not limited to the embodiment, and can be embodied in various forms without departing from the gist of the present invention.
  • the present invention includes the following combinations.
  • a multilayer ceramic capacitor comprising: a laminate in which a plurality of internal electrode layers and dielectric layers are laminated; and external electrodes arranged in a length direction intersecting a lamination direction of the laminate and connected to the internal electrode layers,
  • the internal electrode layer includes two regions in the longitudinal direction, the two regions having at least a part of a metal component different from each other,
  • a multilayer ceramic capacitor in which a diffusion region is formed at the boundary between the two regions, where metal components contained in both regions can be detected.
  • the internal electrode layers each have an opposing portion where adjacent internal electrode layers in the stacking direction face each other, and an extension portion extending from the opposing portion to the external electrode,
  • the opposing portion and the drawn-out portion have at least a part of different metal components
  • the multilayer ceramic capacitor according to ⁇ 1> wherein a diffusion region is formed at a boundary between the facing portion and the extended portion, in which both a metal component contained in the facing portion and a metal component contained in the extended portion are detected.
  • the lead portion has two regions in the longitudinal direction, the regions having different metal components
  • the multilayer ceramic capacitor according to ⁇ 2> wherein a diffusion region is formed at a boundary between the two regions, in which metal components contained in both regions can be detected.
  • ⁇ 4> The multilayer ceramic capacitor according to ⁇ 3>, wherein a plurality of diffusion regions are formed in the lead portion.
  • ⁇ 5> The multilayer ceramic capacitor according to any one of ⁇ 2> to ⁇ 4>, wherein a thickness of the diffusion region in the stacking direction is greater than a thickness of the facing portion and the lead-out portion in the stacking direction.
  • ⁇ 6> The multilayer ceramic capacitor according to any one of ⁇ 2> to ⁇ 5>, wherein a diffusion region is formed at a boundary between the extension and the external electrode, in which both a metal component contained in a region of the extension in contact with the boundary and a metal component contained in a region of the external electrode in contact with the boundary are detected.
  • ⁇ 7> The multilayer ceramic capacitor according to ⁇ 6>, wherein a thickness of the diffusion region in the lamination direction is greater than a thickness of the lead portion in the lamination direction.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Materials Engineering (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Ceramic Capacitors (AREA)
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10135065A (ja) * 1996-10-31 1998-05-22 Kyocera Corp 積層セラミックコンデンサ
WO2013047281A1 (ja) * 2011-09-27 2013-04-04 株式会社村田製作所 積層セラミック電子部品およびその製造方法
JP2021044317A (ja) * 2019-09-09 2021-03-18 株式会社村田製作所 積層セラミック電子部品
JP2022077451A (ja) * 2020-11-11 2022-05-23 株式会社村田製作所 積層セラミックコンデンサ

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10135065A (ja) * 1996-10-31 1998-05-22 Kyocera Corp 積層セラミックコンデンサ
WO2013047281A1 (ja) * 2011-09-27 2013-04-04 株式会社村田製作所 積層セラミック電子部品およびその製造方法
JP2021044317A (ja) * 2019-09-09 2021-03-18 株式会社村田製作所 積層セラミック電子部品
JP2022077451A (ja) * 2020-11-11 2022-05-23 株式会社村田製作所 積層セラミックコンデンサ

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