WO2024152283A1 - 像素电路、像素驱动方法和显示装置 - Google Patents

像素电路、像素驱动方法和显示装置 Download PDF

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Publication number
WO2024152283A1
WO2024152283A1 PCT/CN2023/073062 CN2023073062W WO2024152283A1 WO 2024152283 A1 WO2024152283 A1 WO 2024152283A1 CN 2023073062 W CN2023073062 W CN 2023073062W WO 2024152283 A1 WO2024152283 A1 WO 2024152283A1
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Prior art keywords
circuit
control
electrically connected
transistor
light
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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PCT/CN2023/073062
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English (en)
French (fr)
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WO2024152283A9 (zh
Inventor
李健
田雪松
侯帅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN202380008135.XA priority Critical patent/CN118765412A/zh
Priority to PCT/CN2023/073062 priority patent/WO2024152283A1/zh
Priority to US18/556,897 priority patent/US20260120632A1/en
Publication of WO2024152283A1 publication Critical patent/WO2024152283A1/zh
Publication of WO2024152283A9 publication Critical patent/WO2024152283A9/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0245—Clearing or presetting the whole screen independently of waveforms, e.g. on power-on
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel circuit, a pixel driving method and a display device.
  • VRR frequency switching difference
  • an embodiment of the present disclosure provides a pixel circuit including a driving circuit, a first initialization circuit, and a second initialization circuit;
  • the control end of the driving circuit is electrically connected to the first node, the first end of the driving circuit is electrically connected to the second node, the second end of the driving circuit is electrically connected to the third node, and the driving circuit is used to generate a current flowing from the second node to the third node under the control of the potential of the first node;
  • the first initialization circuit is electrically connected to the first control terminal, the first initial voltage line and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage line into the first node under the control of the first control signal provided by the first control terminal;
  • the second initialization circuit is electrically connected to the first scan end, the second initial voltage line and the third node respectively, and is used to write the second initial voltage provided by the second initial voltage line into the third node under the control of the first scan signal provided by the first scan end.
  • the driving transistor included in the driving circuit is a p-type transistor, and the difference between the voltage value of the first initial voltage and the voltage value of the second initial voltage is smaller than the threshold voltage of the driving transistor; or,
  • the driving transistor included in the driving circuit is an n-type transistor, and the voltage of the first initial voltage is The difference between the voltage value of the first voltage and the voltage value of the second initial voltage is greater than the threshold voltage of the driving transistor.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a data writing circuit, a compensation control circuit and an energy storage circuit;
  • the data writing circuit is electrically connected to the second scanning end, the data line and the second node respectively, and is used to write the data voltage on the data line into the second node under the control of the second scanning signal provided by the second scanning end;
  • the compensation control circuit is electrically connected to the second control terminal, the first node and the third node respectively, and is used to control the connection or disconnection between the first node and the third node under the control of the second control signal provided by the second control terminal;
  • the first end of the energy storage circuit is electrically connected to the first node, the second end of the energy storage circuit is electrically connected to the first voltage end, and the energy storage circuit is used to store electrical energy.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a data writing circuit and an energy storage circuit;
  • the data writing circuit is electrically connected to the second scanning end, the data line and the first node respectively, and is used to write the data voltage on the data line into the first node under the control of the second scanning signal provided by the second scanning end;
  • the first end of the energy storage circuit is electrically connected to the first node, the second end of the energy storage circuit is electrically connected to the first voltage end, and the energy storage circuit is used to store electrical energy.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a first energy storage circuit, a second energy storage circuit, a data writing circuit and a compensation control circuit;
  • the first end of the first energy tank circuit is electrically connected to the first node, the second end of the first energy tank circuit is electrically connected to the first end of the second energy tank circuit, and the second end of the second energy tank circuit is electrically connected to the first voltage end; the first energy tank circuit and the second energy tank circuit are used to store electrical energy;
  • the data writing circuit is electrically connected to the second scanning end, the data line and the second end of the first energy storage circuit respectively, and is used to write the data voltage on the data line into the second end of the first energy storage circuit under the control of the second scanning signal provided by the second scanning end;
  • the compensation control circuit is electrically connected to the second control terminal, the first node and the third node respectively, and is used to control the first node under the control of the second control signal provided by the second control terminal.
  • the node is connected or disconnected from the third node.
  • the compensation control circuit includes a first transistor, a gate of the first transistor is electrically connected to the second control terminal, a first electrode of the first transistor is electrically connected to the first node, and a second electrode of the first transistor is electrically connected to the third node; the first transistor is a dual-gate transistor.
  • the compensation control circuit includes a first compensation control transistor and a second compensation control transistor; the gate of the first compensation control transistor is electrically connected to the second control terminal, the first electrode of the first compensation control transistor is electrically connected to the first node, and the second electrode of the first compensation control transistor is electrically connected to the intermediate node; the gate of the second compensation control transistor is electrically connected to the second control terminal, the first electrode of the second compensation control transistor is electrically connected to the intermediate node, and the second electrode of the second compensation control transistor is electrically connected to the third node; the pixel circuit also includes a third initialization circuit;
  • the third initialization circuit is electrically connected to the light emitting control terminal, the third initial voltage line and the intermediate node respectively, and is used to write the third initial voltage provided by the third initial voltage line into the intermediate node under the control of the light emitting control signal provided by the light emitting control terminal.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a light-emitting element, a first light-emitting control circuit, and a second light-emitting control circuit;
  • the first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the power supply voltage terminal and the first terminal of the driving circuit respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the first light-emitting control signal provided by the first light-emitting control terminal;
  • the second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the second terminal of the driving circuit and the first electrode of the light-emitting element respectively, and is used to control the connection or disconnection between the second terminal of the driving circuit and the first electrode of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal;
  • the second electrode of the light emitting element is electrically connected to the second voltage terminal.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a fourth initialization circuit
  • the fourth initialization circuit is electrically connected to the first scanning end, the fourth initial voltage line and the first pole of the light-emitting element respectively, and is used to write the fourth initial voltage provided by the fourth initial voltage line into the first pole of the light-emitting element under the control of the first scanning signal provided by the first scanning end.
  • the driving circuit includes a driving transistor, the first initialization circuit includes a second transistor, and the second initialization circuit includes a third transistor;
  • the gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node;
  • the gate of the second transistor is electrically connected to the first control terminal, the first electrode of the second transistor is electrically connected to the first initial voltage line, and the second electrode of the second transistor is electrically connected to the first node;
  • a gate of the third transistor is electrically connected to the first scanning end, a first electrode of the third transistor is electrically connected to the second initial voltage line, and a second electrode of the third transistor is electrically connected to the third node.
  • the data writing circuit includes a fourth transistor
  • the gate of the fourth transistor is electrically connected to the second scanning end, the first electrode of the fourth transistor is electrically connected to the data line, and the second electrode of the fourth transistor is electrically connected to the second node;
  • the energy storage circuit includes a storage capacitor
  • the first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the power supply voltage end.
  • the data writing circuit includes a fourth transistor
  • the gate of the fourth transistor is electrically connected to the second scanning end, the first electrode of the fourth transistor is electrically connected to the data line, and the second electrode of the fourth transistor is electrically connected to the first node;
  • the energy storage circuit includes a storage capacitor
  • the first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the first voltage end.
  • the data writing circuit includes a fourth transistor
  • the gate of the fourth transistor is electrically connected to the second scanning end, the first electrode of the fourth transistor is electrically connected to the data line, and the second electrode of the fourth transistor is electrically connected to the second end of the first energy storage circuit;
  • the first energy storage circuit includes a first storage capacitor, and the second energy storage circuit includes a second storage capacitor;
  • the first end of the first storage capacitor is electrically connected to the first node
  • the second end of the first storage capacitor is electrically connected to the first end of the second storage capacitor
  • the second end of the second storage capacitor is electrically connected to the first node.
  • a voltage terminal is electrically connected.
  • the first light emitting control circuit includes a fifth transistor, and the second light emitting control circuit includes a sixth transistor;
  • the gate of the fifth transistor is electrically connected to the first light emitting control terminal, the first electrode of the fifth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the fifth transistor is electrically connected to the first terminal of the driving circuit;
  • the gate of the sixth transistor is electrically connected to the second light emitting control terminal, the first electrode of the sixth transistor is electrically connected to the second terminal of the driving circuit, and the second electrode of the sixth transistor is electrically connected to the first electrode of the light emitting element.
  • the fourth initialization circuit includes a seventh transistor
  • a gate of the seventh transistor is electrically connected to the first scanning end, a first electrode of the seventh transistor is electrically connected to the fourth initial voltage line, and a second electrode of the seventh transistor is electrically connected to a first electrode of the light emitting element.
  • the third initialization circuit includes an eighth transistor
  • a gate of the eighth transistor is electrically connected to the light emitting control terminal, a first electrode of the eighth transistor is electrically connected to the third initial voltage line, and a second electrode of the eighth transistor is electrically connected to the intermediate node.
  • an embodiment of the present disclosure provides a pixel driving method, which is applied to the above-mentioned pixel circuit, wherein a display period includes a hold frame, and the hold frame includes a hold bias phase; the pixel driving method includes:
  • the first initialization circuit writes a first initial voltage to the first node under the control of the first control signal; the second initialization circuit writes a second initial voltage to the third node under the control of the first scan signal, so that the driving transistor included in the driving circuit is in an on-bias state.
  • the pixel circuit further includes a first light emitting control circuit, a second light emitting control circuit and a light emitting element;
  • the bias holding stage includes a plurality of bias holding time periods; the holding frame also includes a plurality of light holding time periods; the bias holding time periods and the light holding time periods are alternately arranged, and the pixel driving method includes:
  • the first initialization circuit writes a first initial voltage to the first node under the control of the first control signal;
  • the second initialization circuit writes a second initial voltage to the third node under the control of the first scan signal, so that the driving transistor included in the driving circuit is in an on-state bias state;
  • the first light-emitting control circuit controls the connection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the first light-emitting control signal
  • the second light-emitting control circuit controls the connection between the second terminal of the driving circuit and the first pole of the light-emitting element under the control of the second light-emitting control signal
  • the driving circuit drives the light-emitting element
  • the display cycle further includes a refresh frame arranged between the hold frames;
  • the refresh frame includes a pre-write bias phase arranged before the data write phase;
  • the pixel driving method includes:
  • the first initialization circuit writes a first initial voltage to the first node under the control of the first control signal; the second initialization circuit writes a second initial voltage to the third node under the control of the first scan signal, so that the driving transistor included in the driving circuit is in an on-state bias state.
  • the display cycle further includes a refresh frame arranged between the hold frames; the refresh frame further includes a post-write bias phase arranged after the data write phase; the pixel driving method includes:
  • the first initialization circuit writes a first initial voltage to the first node under the control of the first control signal; the second initialization circuit writes a second initial voltage to the third node under the control of the first scan signal, so that the driving transistor included in the driving circuit is in an on-state bias state.
  • the pixel circuit includes a data writing circuit; and the pixel driving method further includes:
  • the data writing circuit controls the data voltage on the data line to be written into the second node under the control of the second scanning signal provided by the second scanning terminal.
  • the pixel circuit further includes a compensation control circuit; the refresh frame further includes a compensation phase; the data writing phase is included in the compensation phase, and the data writing phase is arranged before the post-writing bias phase; the pixel driving method includes:
  • the compensation control circuit is controlled by the second control signal provided by the second control terminal. Controlling the communication between the first node and the third node.
  • the pixel circuit further includes a light emitting element, a first light emitting control circuit and a second light emitting control circuit;
  • the refresh frame further includes a refresh light emitting phase arranged after the post-write bias phase;
  • the hold frame includes a hold light emitting phase;
  • the pixel driving method further comprises:
  • the first light-emitting control circuit controls the connection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the first light-emitting control signal
  • the second light-emitting control circuit controls the connection between the second terminal of the driving circuit and the first pole of the light-emitting element under the control of the second light-emitting control signal
  • the driving circuit drives the light-emitting element
  • the pixel circuit further includes a light emitting element, a first light emitting control circuit and a second light emitting control circuit;
  • the refresh frame further includes a light emitting refresh phase;
  • the post-write bias phase includes a plurality of refresh bias time periods, and the refresh light-emitting phase includes a plurality of refresh light-emitting time periods; the refresh bias time periods and the refresh light-emitting time periods are alternately arranged;
  • the pixel driving method comprises:
  • the first initialization circuit writes a first initial voltage to the first node under the control of the first control signal;
  • the second initialization circuit writes a second initial voltage to the third node under the control of the first scan signal, so that the driving transistor included in the driving circuit is in an on-state bias state;
  • the first light-emitting control circuit controls the connection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the first light-emitting control signal
  • the second light-emitting control circuit controls the connection between the second terminal of the driving circuit and the first pole of the light-emitting element under the control of the second light-emitting control signal
  • the driving circuit drives the light-emitting element
  • the compensation control circuit includes a first compensation control transistor and a second compensation control transistor, and the pixel circuit further includes a third initialization circuit; and the pixel driving method further includes:
  • the third initialization circuit writes the third initialization voltage into the middle node under the control of the light emitting control signal.
  • an embodiment of the present disclosure provides a display device, comprising the above-mentioned pixel circuit.
  • FIG1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG8 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG9 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG8 ;
  • FIG10 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG8 ;
  • FIG11 is a timing diagram of the operation of each GOA (Gate On Array, a gate driving circuit disposed on an array substrate) circuit for generating at least one embodiment of the pixel circuit shown in FIG8 ;
  • GOA Gate On Array, a gate driving circuit disposed on an array substrate
  • FIG12 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG8 ;
  • FIG13 is a timing diagram of the operation of each GOA circuit of at least one embodiment of the pixel circuit shown in FIG8;
  • FIG15 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG8 ;
  • FIG16 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG8 ;
  • FIG18 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 19 is a schematic diagram of an orthographic projection of each initial voltage line on a substrate.
  • the transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • one of the electrodes is called the first electrode and the other is called the second electrode.
  • the first electrode when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
  • the pixel circuit includes a driving circuit 10 , a first initialization circuit 11 , and a second initialization circuit 12 ;
  • the control end of the driving circuit 10 is electrically connected to the first node N1, the first end of the driving circuit 10 is electrically connected to the second node N2, and the second end of the driving circuit 10 is electrically connected to the third node N3.
  • the driving circuit 10 is used to generate a current flowing from the second node N2 to the third node N3 under the control of the potential of the first node N1;
  • the first initialization circuit 11 is electrically connected to the first control terminal EM21, the first initial voltage line I1 and the first node N1 respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage line I1 into the first node N1 under the control of the first control signal provided by the first control terminal EM21;
  • the second initialization circuit 12 is electrically connected to the first scan terminal G1, the second initial voltage line I2 and the third node N3 respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage line I2 into the third node N3 under the control of the first scan signal provided by the first scan terminal G1.
  • At least one embodiment of the pixel circuit shown in Figure 1 of the present disclosure is provided with a first initialization circuit 11 and a second initialization circuit 12; the first initialization circuit 11 writes a first initial voltage Vinit1 to the first node N1 under the control of a first control signal; the second initialization circuit 12 writes a second initial voltage Vinit2 to the third node N3 under the control of a first scanning signal to control the driving transistor included in the driving circuit 10 to be in an on-state biased state.
  • the transistor included in the driving circuit 10 can be in an on-state bias state.
  • a display cycle when in operation, may include a hold frame; the hold frame may include a hold bias phase set before the hold light emission phase. part;
  • the first initialization circuit 11 writes the first initial voltage Vinit1 into the first node N1 under the control of the first control signal; the second initialization circuit 12 writes the second initial voltage Vinit2 into the third node N3 under the control of the first scan signal, so that the driving transistor included in the driving circuit 10 is in an on-state bias state to pull down Vth.
  • the driving transistor is controlled to be in an on-state bias state to lower Vth, thereby improving VRR (frequency switching difference).
  • VRR frequency switching difference
  • Vth will be negatively biased, and in the maintenance frame, Vth will return to stability.
  • Vth will be negatively biased in each frame; and when the display frequency is 30Hz, Vth will be negatively biased in the refresh frame, and Vth will be restored in the maintenance frame. Therefore, when the display frequency is switched, due to the difference in Vth, a brightness difference will occur, which is easily captured by the human eye.
  • At least one embodiment of the present disclosure controls the driving transistor to be in an on-state bias state in the maintenance frame, before maintaining the light-emitting stage, and in the maintenance bias stage, Vth is pulled down, and the Vth difference between the refresh frame and the maintenance frame is reduced, so as to improve VRR.
  • the absolute value of the difference between the Vth in the refresh frame and the Vth in the hold frame may be less than or equal to 0.2 V, but is not limited thereto. In specific implementation, the absolute value of the difference may be selected according to actual conditions.
  • the voltage value of Vinit1 may be greater than or equal to -5V and less than or equal to -3V, and the voltage value of Vinit2 may be greater than or equal to 5V and less than or equal to 7V, but the present invention is not limited thereto.
  • T0 as a p-type transistor as an example
  • Vinit1 is connected to the first node N1
  • Vinit3 is written to the third node N3
  • T0 is turned on
  • Vinit2 is written to the second node N2
  • the gate-source voltage Vgs of T0 is less than the threshold voltage Vth of T0.
  • the absolute value of the gate-source voltage Vgs of T0 is large, which will capture more holes at the switch of T0, making Vth negatively biased.
  • a display cycle when in operation, includes a refresh frame, wherein the refresh frame includes a pre-write bias phase arranged before a data write phase;
  • the first initialization circuit In the pre-write bias phase, the first initialization circuit, under the control of the first control signal, sets the first An initial voltage is written into the first node; and under the control of the first scanning signal, the second initialization circuit writes a second initial voltage into the third node, so that the driving transistor included in the driving circuit is in an on-state bias state.
  • At least one embodiment of the pixel circuit shown in FIG. 1 of the present disclosure is in operation.
  • the driving transistor included in the control driving circuit is in an on-state bias state, and the threshold voltage Vth of the driving transistor is pulled down without being affected by the data voltage of the previous frame, thereby solving the FFR (first frame response rate) problem.
  • FFR has a great relationship with the threshold voltage of the driving transistor; when displaying a black screen, the voltage value of the data voltage Vdata is large, and the threshold voltage Vth is more negatively biased; when displaying a white screen, the voltage value of the data voltage Vdata is small, and the threshold voltage Vth is less negatively biased.
  • This Vth difference causes Vth to be still in the black screen state at the moment when the black screen switches to the white screen, and the white screen data voltage must first make up for part of Vth, resulting in low brightness of the first frame in the switched screen.
  • at least one embodiment of the present disclosure controls the driving transistor to be in an on-state bias state before charging with the data voltage during the refresh frame to pull down Vth to solve the FFR problem.
  • low-frequency technology has been widely used in small and medium-sized display panels, but most of them are OLED (organic light-emitting diode) display panels using LTPO (low-temperature polycrystalline oxide) materials. Due to the complexity of LTPO panel technology and high cost, many panel manufacturers pursue LTPS (Low Temperature Poly-Silicon) low-frequency display, and also pursue higher frequency display compatible with low-frequency display, such as 144Hz or 165Hz, and low frequency such as 40Hz or 30Hz. The related pixel circuit has poor FFR at high frequency and poor VRR at low frequency.
  • LTPS Low Temperature Poly-Silicon
  • the pixel circuit described in at least one embodiment of the present disclosure can improve VRR and FFR, and can achieve high-frequency display and low-frequency display at the same time.
  • the driving transistor included in the driving circuit is a p-type transistor, and the difference between the voltage value of the first initial voltage and the voltage value of the second initial voltage is smaller than the threshold voltage of the driving transistor; or,
  • the driving transistor included in the driving circuit is an n-type transistor, and the difference between the voltage value of the first initial voltage and the voltage value of the second initial voltage is greater than the threshold voltage of the driving transistor.
  • the voltage value of the first initial voltage and the voltage value of the second initial voltage can be set.
  • the voltage value is used to control the driving transistor to be in an on-state bias state.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a data writing circuit, a compensation control circuit and an energy storage circuit;
  • the data writing circuit is electrically connected to the second scanning end, the data line and the second node respectively, and is used to write the data voltage on the data line into the second node under the control of the second scanning signal provided by the second scanning end;
  • the compensation control circuit is electrically connected to the second control terminal, the first node and the third node respectively, and is used to control the connection or disconnection between the first node and the third node under the control of the second control signal provided by the second control terminal;
  • the first end of the energy storage circuit is electrically connected to the first node, the second end of the energy storage circuit is electrically connected to the first voltage end, and the energy storage circuit is used to store electrical energy.
  • the pixel circuit described in at least one embodiment of the present disclosure may also include a data writing circuit and a compensation control circuit, wherein the data writing circuit writes the data voltage to the second node under the control of a second scanning signal; and the compensation control circuit controls the connection or disconnection between the first node and the second node under the control of a second control signal to perform threshold voltage compensation.
  • the first voltage terminal may be a power supply voltage terminal or a reference voltage terminal; in actual operation, the first voltage terminal may be a DC voltage terminal, but is not limited thereto.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a data writing circuit 21 , a compensation control circuit 22 and an energy storage circuit 23 ;
  • the data writing circuit 21 is electrically connected to the second scanning terminal G2, the data line Da and the second node N2 respectively, and is used to write the data voltage Vdata on the data line Da into the second node N2 under the control of the second scanning signal provided by the second scanning terminal G2;
  • the compensation control circuit 22 is electrically connected to the second control terminal EM2, the first node N1 and the third node N3 respectively, and is used to control the connection or disconnection between the first node N1 and the third node N3 under the control of the second control signal provided by the second control terminal EM2;
  • a first end of the energy storage circuit 23 is electrically connected to the first node N1 , a second end of the energy storage circuit 23 is electrically connected to the power supply voltage terminal VDD, and the energy storage circuit 23 is used to store electrical energy.
  • At least one embodiment of the driving circuit shown in FIG. 2 of the present disclosure is in operation, and the refresh frame also includes
  • the data writing phase includes a compensation phase, the data writing phase is included in the compensation phase, and the data writing phase is arranged before the post-write bias phase;
  • the data writing circuit 21 controls the data voltage Vdata on the data line Da to be written into the second node N2 under the control of the second scanning signal provided by the second scanning terminal G2.
  • the compensation control circuit 22 controls the connection between the first node N1 and the third node N3 under the control of the second control signal provided by the second control terminal EM2.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a data writing circuit 21 and an energy storage circuit 23 ;
  • the data writing circuit 21 is electrically connected to the second scanning terminal G2, the data line Da and the first node N1 respectively, and is used to write the data voltage Vdata on the data line Da into the first node N1 under the control of the second scanning signal provided by the second scanning terminal G2;
  • a first end of the energy storage circuit 23 is electrically connected to the first node N1 , a second end of the energy storage circuit 23 is electrically connected to the power supply voltage terminal VDD, and the energy storage circuit 23 is used to store electrical energy.
  • the data writing circuit 21 writes the data voltage Vdata on the data line Da into the first node N1 under the control of the second scanning signal to perform data voltage writing.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a first energy storage circuit 231 , a second energy storage circuit 232 , a data writing circuit 21 , and a compensation control circuit 22 ;
  • the first end of the first energy storage circuit 231 is electrically connected to the first node N1, the second end of the first energy storage circuit 231 is electrically connected to the first end of the second energy storage circuit 232, and the second end of the second energy storage circuit 232 is electrically connected to the power supply voltage terminal VDD; the first energy storage circuit 231 and the second energy storage circuit 232 are used to store electrical energy;
  • the data writing circuit 21 is electrically connected to the second scanning terminal G2, the data line Da and the second end of the first energy storage circuit 231 respectively, and is used to write the data voltage Vdata on the data line Da into the second end of the first energy storage circuit 231 under the control of the second scanning signal provided by the second scanning terminal G2;
  • the compensation control circuit 22 is electrically connected to the second control terminal EM2, the first node N1 and the third node N3 respectively, and is used to control the second control signal provided by the second control terminal EM2. Under control, the first node N1 and the third node N3 are controlled to be connected or disconnected.
  • the compensation control circuit includes a first transistor, which is a dual-gate transistor, wherein the gate of the first transistor is electrically connected to the second control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the third node.
  • the first transistor included in the compensation control circuit may be a dual-gate transistor.
  • the dual-gate transistor has a small leakage current so as to better maintain the potential of the first node.
  • the compensation control circuit includes a first compensation control transistor and a second compensation control transistor; the gate of the first compensation control transistor is electrically connected to the second control terminal, the first electrode of the first compensation control transistor is electrically connected to the first node, and the second electrode of the first compensation control transistor is electrically connected to the intermediate node; the gate of the second compensation control transistor is electrically connected to the second control terminal, the first electrode of the second compensation control transistor is electrically connected to the intermediate node, and the second electrode of the second compensation control transistor is electrically connected to the third node; the pixel circuit also includes a third initialization circuit;
  • the third initialization circuit is electrically connected to the light emitting control terminal, the third initial voltage line and the middle node of the first transistor respectively, and is used to write the third initial voltage provided by the third initial voltage line into the middle node under the control of the light emitting control signal provided by the light emitting control terminal.
  • the compensation control circuit may include a first compensation control transistor and a second compensation control transistor, and the pixel circuit may also include a third initialization circuit.
  • the third initialization circuit writes a third initial voltage into the intermediate node to control the intermediate stage to access the third initial voltage during the light-emitting stage, so as to reduce the leakage of the first node N1 and help maintain the potential of the first node N1.
  • the compensation control circuit includes a first compensation control transistor T11 and a second compensation control transistor T12 , and the pixel circuit further includes a third initialization circuit 31 ;
  • the gate of the first compensation control transistor T11 is electrically connected to the second control terminal EM2, the source of the first compensation control transistor T11 is electrically connected to the first node N1, and the drain of the first compensation control transistor T11 is electrically connected to the intermediate node;
  • the gate of the second compensation control transistor T12 is electrically connected to the second control terminal EM2.
  • the source of the second compensation control transistor T12 is electrically connected to the intermediate node, and the drain of the second compensation control transistor T12 is electrically connected to the third node N3;
  • the third initialization circuit 31 is electrically connected to the light emitting control terminal EM1, the third initial voltage line I3 and the intermediate node respectively, and is used to write the third initial voltage Vinit3 provided by the third initial voltage line I3 into the intermediate node under the control of the light emitting control signal provided by the light emitting control terminal EM1.
  • the third initialization circuit 31 writes the third initial voltage Vinit3 into the intermediate node under the control of the light-emitting control signal, and the voltage value of the third initial voltage Vinit3 is not much different from the potential of the first node N1, so as to reduce the leakage of the first node N1 and help maintain the potential of the first node N1.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a light-emitting element, a first light-emitting control circuit and a second light-emitting control circuit;
  • the first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the power supply voltage terminal and the first terminal of the driving circuit respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the first light-emitting control signal provided by the first light-emitting control terminal;
  • the second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the second terminal of the driving circuit and the first electrode of the light-emitting element respectively, and is used to control the connection or disconnection between the second terminal of the driving circuit and the first electrode of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal;
  • the second electrode of the light emitting element is electrically connected to the second voltage terminal.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a light-emitting element, a first light-emitting control circuit and a second light-emitting control circuit, and the first light-emitting control circuit and the second light-emitting control circuit can perform light-emitting control.
  • the first light-emitting control end and the second light-emitting control end may both be light-emitting control ends, but are not limited thereto; in actual operation, the first light-emitting control end and the second light-emitting control end may also be different.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a light emitting element 40 , a first light emitting control circuit 41 and a second light emitting control circuit 42 ;
  • the first light emitting control circuit 41 is electrically connected to the light emitting control terminal EM1, the power supply voltage terminal VDD and the first terminal of the driving circuit 10 respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the first terminal of the driving circuit 10 under the control of the light emitting control signal provided by the light emitting control terminal EM1;
  • the second light emitting control circuit 42 is electrically connected to the light emitting control terminal EM1, the second terminal of the driving circuit 10 and the first electrode of the light emitting element 40 respectively, and is used to control the connection or disconnection between the second terminal of the driving circuit 10 and the first electrode of the light emitting element 40 under the control of the light emitting control signal;
  • the second electrode of the light emitting element 40 is electrically connected to the second voltage terminal V2.
  • the first light-emitting control terminal and the second light-emitting control terminal are both light-emitting control terminals EM1 , but the present invention is not limited thereto. In actual operation, the first light-emitting control terminal and the second light-emitting control terminal may also be different control terminals.
  • the light emitting element may be an organic light emitting diode
  • the first electrode of the light emitting element may be an anode
  • the second electrode of the light emitting element may be a cathode
  • the second voltage terminal V2 may be a low voltage terminal
  • the fourth initialization circuit is electrically connected to the first scanning end, the fourth initial voltage line and the first pole of the light-emitting element respectively, and is used to write the fourth initial voltage provided by the fourth initial voltage line into the first pole of the light-emitting element under the control of the first scanning signal provided by the first scanning end.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a fourth initialization circuit; under the control of the first scanning signal, the fourth initialization circuit writes the fourth initial voltage provided by the fourth initial voltage line into the first pole of the light-emitting element to reset the potential of the first pole of the light-emitting element, clear the residual charge in the first pole of the light-emitting element, and control the light-emitting element not to emit light.
  • the fourth initialization circuit under the control of the first scanning signal, the fourth initialization circuit writes the fourth initial voltage provided by the fourth initial voltage line into the first pole of the light-emitting element to reset the potential of the first pole of the light-emitting element, clear the residual charge in the first pole of the light-emitting element, and control the light-emitting element not to emit light.
  • a difference between a voltage value of the fourth initial voltage and a voltage value of the second voltage signal provided by the second voltage terminal V2 may be smaller than a start-up voltage of the light-emitting element.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a fourth initialization circuit 51 ;
  • the fourth initialization circuit 51 is electrically connected to the first scanning terminal G1, the fourth initial voltage line I4 and the first electrode of the light-emitting element, respectively, and is used to write the fourth initial voltage Vinit4 of the fourth initial voltage line I4 into the first electrode of the light-emitting element 40 under the control of the first scanning signal of the first scanning terminal G1.
  • the driving circuit includes a driving transistor, the first initialization circuit includes a second transistor, and the second initialization circuit includes a third transistor;
  • the gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node;
  • the gate of the second transistor is electrically connected to the first control terminal, the first electrode of the second transistor is electrically connected to the first initial voltage line, and the second electrode of the second transistor is electrically connected to the first node;
  • a gate of the third transistor is electrically connected to the first scanning end, a first electrode of the third transistor is electrically connected to the second initial voltage line, and a second electrode of the third transistor is electrically connected to the third node.
  • the data writing circuit includes a fourth transistor
  • the gate of the fourth transistor is electrically connected to the second scanning end, the first electrode of the fourth transistor is electrically connected to the data line, and the second electrode of the fourth transistor is electrically connected to the second node;
  • the energy storage circuit includes a storage capacitor
  • the first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the power supply voltage end.
  • the data writing circuit includes a fourth transistor
  • the gate of the fourth transistor is electrically connected to the second scanning end, the first electrode of the fourth transistor is electrically connected to the data line, and the second electrode of the fourth transistor is electrically connected to the first node;
  • the energy storage circuit includes a storage capacitor
  • the first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the first voltage end.
  • the data writing circuit includes a fourth transistor
  • the gate of the fourth transistor is electrically connected to the second scanning end, the first electrode of the fourth transistor is electrically connected to the data line, and the second electrode of the fourth transistor is electrically connected to the second end of the first energy storage circuit;
  • the first energy storage circuit includes a first storage capacitor, and the second energy storage circuit includes a second storage capacitor;
  • the first end of the first storage capacitor is electrically connected to the first node
  • the second end of the first storage capacitor is electrically connected to the first end of the second storage capacitor
  • the second end of the second storage capacitor is electrically connected to the first voltage end.
  • the first light emitting control circuit includes a fifth transistor, and the second light emitting control circuit includes a sixth transistor;
  • the gate of the fifth transistor is electrically connected to the first light emitting control terminal, the first electrode of the fifth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the fifth transistor is electrically connected to the first terminal of the driving circuit;
  • the gate of the sixth transistor is electrically connected to the second light emitting control terminal, the first electrode of the sixth transistor is electrically connected to the second terminal of the driving circuit, and the second electrode of the sixth transistor is electrically connected to the first electrode of the light emitting element.
  • the fourth initialization circuit includes a seventh transistor
  • a gate of the seventh transistor is electrically connected to the first scanning end, a first electrode of the seventh transistor is electrically connected to the fourth initial voltage line, and a second electrode of the seventh transistor is electrically connected to a first electrode of the light emitting element.
  • the third initialization circuit includes an eighth transistor
  • a gate of the eighth transistor is electrically connected to the light emitting control terminal, a first electrode of the eighth transistor is electrically connected to the third initial voltage line, and a second electrode of the eighth transistor is electrically connected to the intermediate node.
  • the driving circuit includes a driving transistor T0
  • the first initialization circuit includes a second transistor T2
  • the second initialization circuit includes a third transistor T3
  • the light emitting element is an organic light emitting diode O1 ;
  • the gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the second node N2, and the drain of the driving transistor T0 is electrically connected to the third node N2.
  • Node N3 is electrically connected;
  • the gate of the second transistor T2 is electrically connected to the first control terminal EM21, the source of the second transistor T2 is electrically connected to the first initial voltage line I1, and the drain of the second transistor T2 is electrically connected to the first node N1; the first initial voltage line I1 is used to provide a first initial voltage Vinit1;
  • the gate of the third transistor T3 is electrically connected to the first scanning terminal G1, the source of the third transistor T3 is electrically connected to the second initial voltage line I2, and the drain of the third transistor T3 is electrically connected to the third node N3; the second initial voltage line I2 is used to provide a second initial voltage Vinit2;
  • the data writing circuit includes a fourth transistor T4; the energy storage circuit includes a storage capacitor Cst;
  • the gate of the fourth transistor T4 is electrically connected to the second scanning terminal G2, the source of the fourth transistor T4 is electrically connected to the data line Da, and the drain of the fourth transistor T4 is electrically connected to the second node N2;
  • the first end of the storage capacitor Cst is electrically connected to the first node N1, and the second end of the storage capacitor Cst is electrically connected to the power supply voltage terminal VDD.
  • the first light emitting control circuit includes a fifth transistor T5, and the second light emitting control circuit includes a sixth transistor T6;
  • the gate of the fifth transistor T5 is electrically connected to the light emitting control terminal EM1, the source of the fifth transistor T5 is electrically connected to the power supply voltage terminal VDD, and the drain of the fifth transistor T5 is electrically connected to the source of the driving transistor T0;
  • the gate of the sixth transistor T6 is electrically connected to the light emitting control terminal EM1, the source of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0, the drain of the sixth transistor T6 is electrically connected to the anode of the organic light emitting diode O1; the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal VSS;
  • the fourth initialization circuit includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the first scanning terminal G1, the source of the seventh transistor T7 is electrically connected to the fourth initial voltage line I4, and the drain of the seventh transistor T7 is electrically connected to the anode of the organic light emitting diode O1; the fourth initial voltage line I4 is used to provide a fourth initial voltage Vinit4;
  • the third initialization circuit includes an eighth transistor T8;
  • the gate of the eighth transistor T8 is electrically connected to the light emitting control terminal EM, the source of the eighth transistor T8 is electrically connected to the third initial voltage line I3, and the drain of the eighth transistor T8 is electrically connected to the middle node; the third initial voltage line I3 is used to provide a third initial voltage Vinit3.
  • all transistors are p-type transistors, but the present invention is not limited thereto.
  • the first voltage terminal is a power voltage terminal
  • the second voltage terminal is a low voltage terminal
  • the first light-emitting control terminal and the second light-emitting control terminal are both light-emitting control terminals, but the present invention is not limited thereto.
  • the voltage value of Vinit1 can be greater than or equal to -5V and less than or equal to -3V
  • the voltage value of Vinit2 can be greater than or equal to 5V and less than or equal to 7V
  • the voltage value of Vinit3 can be greater than or equal to 0V and less than or equal to 3V
  • the voltage value of Vinit4 can be greater than or equal to -4V and less than or equal to -2V.
  • the driving transistor T0 is in an on-state bias state
  • Vinit3 is written into the middle node, so that the potential of the middle node is not much different from the potential of the first node, thereby reducing the leakage of the first node N1;
  • the organic light emitting diode O1 does not emit light.
  • the display cycle may include a refresh frame, wherein the refresh frame includes a pre-write bias stage S11, a compensation stage S12, a post-write bias stage S13, and a refresh light-emitting stage S14 that are successively arranged, and the data writing stage S120 is included in the compensation stage S12;
  • EM1 provides a high voltage signal
  • G1 and EM21 both provide low voltage signals
  • EM2 provides a high voltage signal
  • G2 provides a high voltage signal
  • T3 is turned on to write Vinit2 into the third node N3
  • T0 is turned on to write Vinit2 into the second node N2
  • T2 is turned on to write Vinit1 into the first node N1, so that T0 is in an on-state bias state.
  • N1 and N2 there is a large voltage difference between N1 and N2, the absolute value of the gate-source voltage Vgs of T0 is large, and the threshold voltage Vth of T0 is negatively biased, which can eliminate the influence of different data voltages Vdata on Vth and improve the FFR phenomenon;
  • G1 provides a low voltage signal and T7 is turned on to write Vinit4 to the anode of O1 and clear the residual charge on the anode of O1;
  • EM2 provides a low voltage signal, T11 and T12 are turned on to control the connection between N1 and N3;
  • G2 provides a low voltage signal, T4 is turned on, and Da provides a data voltage Vdata to the second node N2 ;
  • T0 is turned on, and Vdata charges Cst through T4, T0, and T2 to increase the potential of N1 until Vgs of T0 becomes Vth, and T0 is turned off.
  • the gate potential of T0 is Vdata+Vth;
  • EM1 provides a high voltage signal
  • G1 provides a low voltage signal
  • EM21, EM2 and G2 all provide high voltage signals
  • T3 is turned on to write Vinit2 into N3
  • T0 is turned on to write Vinit2 into the second node N2
  • T0 is controlled to be in an on-state bias state
  • T7 is turned on to write Vinit4 into the anode of O1 to clear the residual charge of the anode of O1;
  • EM1 provides a low voltage signal
  • T5 and T6 are turned on, and T0 drives O1 to emit light.
  • the potential of N1 is Vdata+Vth
  • the gate-source voltage of T0 is Vdata+Vth-VDD
  • the driving current of T0 is independent of Vth, so that threshold voltage compensation can be performed
  • T8 is turned on to write Vinit3 to the middle node, and the potential of Vinit3 is not much different from that of N1, so as to reduce the leakage current of N1 and maintain the potential of N1.
  • EM2 is used to control the on and off of T11 and T12.
  • the second control signal provided by EM2 can be provided by an EM GOA circuit (the EM GOA circuit is a light emitting control signal generating circuit arranged on the array substrate), which can achieve reduced leakage and high-frequency display.
  • the time period during which G1 provides a low voltage signal partially overlaps with the time period during which EM21 provides a low voltage signal, and the time period during which G2 provides a low voltage signal is included in the time period during which EM2 provides a low voltage signal.
  • N1 and N2 are reset at the same time. If the reset time is too long, VRR may deteriorate. The reason is that the gate-source voltage Vgs of T0 is too large, which will make Vth more negatively biased. When actually writing data, in the refresh frame, Vth can no longer be negatively biased, and there is no problem with continuous refresh. However, when the data voltage is not written in the hold frame, Vth will gradually recover, which will form The difference between the refresh frame and the hold frame Vth is too large, and the VRR deteriorates. Based on this, at least one embodiment of the present disclosure can improve the VRR by controlling the duration of the pre-write bias phase and controlling T0 to be in an on-state bias state during the hold bias phase included in the hold frame.
  • EM21 provides a low voltage signal at least 3 rows earlier than EM2 provides a low voltage signal.
  • the Nth row GOA circuit provides a low voltage signal to EM21
  • the N-3th row GOA circuit or the N-7th row GOA circuit provides a low voltage signal to EM21.
  • the display cycle may include a hold frame, and the hold frame includes a hold bias stage S21 and a hold light emitting stage S22 that are successively set;
  • EM1 provides a high voltage signal
  • G1 provides a low voltage signal
  • T3 is turned on to write Vinit2 into N3, and T0 is controlled to be in an on bias state
  • EM1 provides a low voltage signal
  • G1 provides a high voltage signal
  • T5 and T6 are turned on
  • T0 drives O1 to emit light.
  • EM21, EM2 and G2 all provide high voltage signals.
  • the first scanning signal provided by G1 can be provided by a first GOA (Gate On Array, a gate driving circuit arranged on an array substrate) circuit
  • the second scanning signal provided by G2 can be provided by a second GOA circuit
  • the light emitting control signal provided by EM1 can be provided by the first EM GOA circuit
  • the first control signal provided by EM21 and the second control signal provided by EM2 can be provided by the second EM GOA circuit
  • the structure of the first EM GOA circuit can be the same as that of the second EM GOA circuit.
  • FIG. 11 is a timing diagram of the operation of each GOA circuit for generating at least one embodiment of the pixel circuit shown in FIG. 8 .
  • GSTV2 is the second starting voltage
  • GCB2 is the second second clock signal
  • GCK2 is the second first clock signal
  • G2 is the second control terminal
  • GSTV1 is the first starting voltage
  • GCB1 is the first second clock signal
  • GCK1 is the first first clock signal
  • G1 is the first control terminal
  • ESTV2 is the second light-emitting control starting voltage
  • ECK2 is the second third clock signal
  • ECB2 is the second fourth clock signal
  • EM21 is the first control terminal
  • EM2 is the second control terminal
  • Da is the data line
  • ESTV1 is the first light-emitting control starting voltage
  • ECK1 is the first third clock signal
  • ECB1 is the first fourth clock signal
  • EM1 is the light-emitting control terminal.
  • the display cycle may include a refresh frame, the refresh frame includes a compensation stage S12, a post-write bias stage S13, and a refresh light-emitting stage S14 that are successively arranged, and the data writing stage S120 is included in the compensation stage S12;
  • EM2 provides the lowest voltage signal, T11 and T12 are turned on to control the connection between N1 and N3;
  • G2 provides a low voltage signal, T4 is turned on, and Da provides a data voltage Vdata to the second node N2 ;
  • T0 is turned on, and Vdata charges Cst through T4, T0, and T2 to increase the potential of N1 until Vgs of T0 becomes Vth, and T0 is turned off.
  • the gate potential of T0 is Vdata+Vth;
  • EM1 provides a high voltage signal
  • G1 provides a low voltage signal
  • EM21, EM2 and G2 all provide high voltage signals
  • T3 is turned on to write Vinit2 into N3
  • T0 is turned on to write Vinit2 into the second node N2
  • T0 is controlled to be in an on-state bias state
  • T7 is turned on to write Vinit4 into the anode of O1 to clear the residual charge of the anode of O1;
  • FIG. 13 is a timing diagram of the operation of each GOA circuit for generating at least one embodiment of the pixel circuit shown in FIG. 8 .
  • GSTV2 is the second starting voltage
  • GCB2 is the second second clock signal
  • GCK2 is the second first clock signal
  • G2 is the second control terminal
  • GSTV1 is the first starting voltage
  • GCB1 is the first second clock signal
  • GCK1 is the first first clock signal
  • G1 is the first control terminal
  • ESTV2 is the second light-emitting control starting voltage
  • ECK2 is the second
  • the first third clock signal is labeled ECB2
  • the second fourth clock signal is labeled EM21
  • the first control terminal is labeled EM2
  • the second control terminal is labeled Da
  • the data line is labeled ESTV1
  • the first light-emitting control starting voltage is labeled ECK1
  • the first third clock signal is labeled ECB1
  • the first fourth clock signal is labeled EM1
  • the light-emitting control terminal is labeled EM1.
  • Figure 14 is a circuit diagram of a first-level light
  • At least one embodiment of the light emitting control signal generating unit includes a first control transistor M1, a second control transistor M2, a third control transistor M3, a fourth control transistor M4, a fifth control transistor M5, a sixth control transistor M6, a seventh control transistor M7, an eighth control transistor M8, a ninth control transistor M9, a tenth control transistor M10, an eleventh control transistor M11, a twelfth control transistor M12, a first capacitor C1, a second capacitor C2, and a third capacitor C3;
  • the gate of M1 is connected to the third clock signal ECK, the source of M2 is electrically connected to the low level terminal VGL, and the drain of M1 is electrically connected to the source of M11;
  • the gate of M11 is electrically connected to the low level terminal VGL, and the drain of M11 is electrically connected to the gate of M6;
  • the gate of M2 is connected to the third clock signal ECK, the source of M2 is connected to the light emission control start voltage ESMV, and the drain of M2 is electrically connected to the gate of M3;
  • the source of M3 is connected to the third clock signal ECK, and the drain of M3 is electrically connected to the drain of M1;
  • the gate of M4 is electrically connected to the gate of M6, the source of M4 is electrically connected to the high level terminal VGH, and the drain of M4 is electrically connected to the source of M5;
  • the gate of M5 is connected to the fourth clock signal ECB, and the drain of M5 is electrically connected to the gate of M3;
  • the source of M6 is connected to the fourth clock signal ECB, and the drain of M6 is electrically connected to the source of M7;
  • the gate of M7 is connected to the fourth clock signal ECB, and the drain of M7 is electrically connected to the gate of M9;
  • the gate of M8 is electrically connected to the gate of M3, the source of M8 is electrically connected to the high level terminal VGH, and the drain of M8 is electrically connected to the gate of M9;
  • the source of M9 is electrically connected to the high level terminal VGH, and the drain of M9 is electrically connected to the light emitting control signal output terminal EO;
  • the gate of M10 is electrically connected to the drain of M12, the source of M10 is electrically connected to the low level terminal VGL, and the drain of M10 is electrically connected to the light emitting control signal output terminal EO;
  • the gate of M12 is electrically connected to the low level terminal VGL, and the source of M12 is electrically connected to the gate of M8;
  • a first end of C1 is electrically connected to the gate of M6, and a second end of C2 is electrically connected to the drain of M6;
  • the first end of C2 is connected to the fourth clock signal ECB, and the second end of C2 is electrically connected to the gate of M10;
  • a first end of C3 is electrically connected to the gate of M9 , and a second end of C3 is electrically connected to the high level end VGH.
  • each transistor may be a p-type transistor, but is not limited thereto.
  • the refresh frame includes a refresh light-emitting stage
  • the hold frame includes a hold light-emitting stage.
  • the refresh light-emitting stage includes a plurality of mutually independent refresh light-emitting time periods
  • the hold light-emitting stage includes a plurality of mutually independent hold light-emitting time periods.
  • the potential of N3 is reset in the corresponding refresh bias time period, and before the hold light-emitting time period, the potential of N3 is reset in the corresponding hold bias time period, so that in the hold frame, the driving transistor can be controlled to be in an on-state bias state multiple times, and Vth can be pulled down multiple times, which can effectively prevent Vth from recovering and improve the VRR phenomenon at low frequency.
  • the refresh frame includes a compensation stage S12, a refresh bias stage, and a refresh light-emitting stage; the data writing stage S120 is included in the compensation stage S12; the compensation stage S12 is arranged before the refresh bias stage and the refresh light-emitting stage;
  • EM1 provides a high voltage signal
  • EM2 provides a low voltage signal
  • EM21 provides a high voltage signal
  • G1 provides a high voltage signal
  • T11 and T12 are turned on, and N1 and N3 are connected;
  • G2 provides a low voltage signal, T4 is turned on, and Da writes the data voltage Vdata into N2;
  • T0 is turned on, and Vdata charges Cst through T4, T0, T11, and T12 until T0 is turned off, at which time the gate-source voltage of T0 is Vth, and the gate voltage of T0 is Vdata+Vth;
  • the refresh bias phase may include a plurality of mutually independent refresh bias time periods, the refresh light emission phase may include a plurality of mutually independent refresh light emission time periods, and the refresh bias time periods may be arranged before the corresponding refresh light emission time periods;
  • the first refresh bias period is labeled S31, and the first refresh bias period is labeled S41.
  • refresh light-emitting time period the one labeled S32 is the second refresh bias time period
  • the one labeled S42 is the second refresh light-emitting time period
  • the one labeled S33 is the third refresh bias time period
  • the one labeled S43 is the third refresh light-emitting time period
  • the one labeled S34 is the fourth refresh bias time period
  • the one labeled S44 is the fourth refresh light-emitting time period
  • the one labeled S35 is the fifth refresh bias time period
  • the one labeled S45 is the fifth refresh light-emitting time period
  • the one labeled S36 is the sixth refresh bias time period
  • the one labeled S46 is the sixth refresh light-emitting time period
  • G1 provides a low voltage signal
  • T3 is turned on to write Vinit2 into N3
  • T0 is turned on to reset the potential of N3 and the potential of N2, and T0 is controlled to be in an on-state bias state
  • G1 provides a high voltage signal
  • EM1 provides a low voltage signal
  • T5 and T6 are turned on
  • T0 drives O1 to emit light.
  • EM21 provides a high voltage signal.
  • the holding frame when at least one embodiment of the pixel circuit shown in FIG. 8 of the present disclosure is in operation, the holding frame includes a holding bias phase and a holding light emission phase;
  • the bias holding stage may include a plurality of mutually independent bias holding time periods, the light holding stage may include a plurality of mutually independent light holding time periods, and the bias holding time periods may be arranged before the corresponding light holding time periods;
  • the first bias holding time period is labeled S51
  • the first light holding time period is labeled S61
  • the second bias holding time period is labeled S52
  • the second light holding time period is labeled S62
  • the third bias holding time period is labeled S53
  • the third light holding time period is labeled S63
  • the fourth bias holding time period is labeled S54
  • the fourth light holding time period is labeled S64
  • the fifth bias holding time period is labeled S55
  • the fifth light holding time period is labeled S65
  • the sixth bias holding time period is labeled S56
  • the sixth light holding time period is labeled S66;
  • G1 provides a low voltage signal
  • T3 is turned on to write Vinit2 into N3
  • T0 is turned on to reset the potential of N3 and the potential of N2, and T0 is controlled to be in an on-state bias state
  • G1 provides a high voltage signal
  • EM1 provides a low voltage signal
  • T5 and T6 are turned on
  • T0 drives O1 to emit light.
  • EM21, EM2 and G2 all provide high voltage signals.
  • the pixel circuit described in at least one embodiment of the present disclosure improves FFR and VRR, can achieve high-frequency display and low-frequency display, and can be appropriately selected for application according to different needs, which is sufficient to meet the first frame response speed and frequency switching flicker specifications.
  • the difference between at least one embodiment of the pixel circuit shown in FIG. 17 of the present disclosure and the pixel circuit shown in FIG. 8 of the present disclosure is that T11, T12 and T8 are not provided, and the drain of T4 is electrically connected to the first node N1.
  • At least one embodiment of the pixel circuit shown in FIG. 17 of the present disclosure cannot perform threshold voltage compensation. Based on this, at least one embodiment of the pixel circuit shown in FIG. 8 of the present disclosure sets the drain of T4 to be electrically connected to the second node N2, and adds T11, T12 and T8.
  • At least one embodiment of the pixel circuit shown in FIG. 18 of the present disclosure differs from the pixel circuit shown in FIG. 8 of the present disclosure in that: it does not include a storage capacitor Cst, but includes a first energy storage circuit and a second energy storage circuit;
  • the first energy storage circuit includes a first storage capacitor Cst1, and the second energy storage circuit includes a second storage capacitor Cst2;
  • the drain of T4 is electrically connected to the second end of Cst1;
  • a first end of Cst1 is electrically connected to the first node N1 , a second end of Cst1 is electrically connected to a first end of Cst2 , and a second end of Cst2 is electrically connected to the power supply voltage terminal VDD.
  • the capacitance value of Cst1 may be greater than the capacitance value of Cst2 , so as to ensure the stability of the potential of the first node N1 .
  • the first initial voltage may be a negative voltage
  • the second initial voltage may be a positive voltage
  • the third initial voltage may be a positive voltage
  • the fourth initial voltage may be a negative voltage
  • a first initial voltage line for providing a first initial voltage Vinit1 and a second initial voltage line for providing a second initial voltage Vinit2 may be formed in different metal layers, and the first initial voltage line and the second initial voltage line may be parallel to each other to avoid the voltage line providing a positive voltage and the voltage line providing a negative voltage from overlapping, thereby affecting voltage stability;
  • the first initial voltage line can be formed in the second gate metal layer, and the first initial voltage line can be arranged in the same layer as the gate of the driving transistor included in the pixel circuit;
  • the second initial voltage line can be formed in the first source-drain metal layer, and the second initial voltage line can be arranged in the same layer as the source and drain of the driving transistor;
  • the drain is arranged in the same layer;
  • the line width of the second initial voltage line can be greater than the line width of the first initial voltage line, which is beneficial to the stability of the positive voltage and reduces the voltage drop.
  • the first initial voltage line and the fourth initial voltage line may be formed in the first metal layer, and the second initial voltage line and the third initial voltage line may be formed in the second metal layer;
  • the first metal layer may be a second gate metal layer, and the second metal layer may be a first source/drain metal layer, but the sequence is not limited thereto.
  • the first initial voltage line, the second initial voltage line, the third initial voltage line and the fourth initial voltage line can extend laterally, and the first initial voltage line, the second initial voltage line, the third initial voltage line and the fourth initial voltage line are arranged on the base substrate, and the orthographic projections of each initial voltage line on the base substrate can be arranged in sequence in the longitudinal direction.
  • initial voltage lines providing positive voltages and initial voltage lines providing negative voltages may be arranged alternately to ensure charge neutralization on the substrate and avoid the influence of residual charges on the display screen.
  • the orthographic projection of the first initial voltage line I1 on the substrate is labeled I11
  • the orthographic projection of the second initial voltage line I2 on the substrate is labeled I21
  • the orthographic projection of the third initial voltage line I3 on the substrate is labeled I31
  • the orthographic projection of the fourth initial voltage line I4 on the substrate is labeled I41;
  • I21, I11, I31 and I41 are arranged in sequence along the vertical direction; I21, I11, I31 and I41 are parallel to each other.
  • the line width of I2 and the line width of I3 are relatively wide.
  • the first initial voltage line and the fourth initial voltage line may be formed in the second gate metal layer, and the second initial voltage line and the third initial voltage line may be formed in the first source-drain metal layer, but the present invention is not limited thereto.
  • the pixel driving method described in the embodiment of the present disclosure is applied to the above-mentioned pixel circuit, the display period includes a holding frame, and the holding frame includes a holding bias phase; the pixel driving method includes:
  • the first initialization circuit writes a first initial voltage to the first node under the control of the first control signal; the second initialization circuit writes a second initial voltage to the third node under the control of the first scan signal, so that the driving transistor included in the driving circuit is in an on-bias state.
  • the driving transistor is controlled to be in an on-state bias state to lower Vth, so as to improve VRR (frequency switching difference).
  • the pixel circuit further includes a first light emitting control circuit, a second light emitting control circuit and a light emitting element;
  • the bias holding stage includes a plurality of bias holding time periods; the holding frame also includes a plurality of light holding time periods; the bias holding time periods and the light holding time periods are alternately arranged, and the pixel driving method includes:
  • the first initialization circuit writes a first initial voltage to the first node under the control of the first control signal;
  • the second initialization circuit writes a second initial voltage to the third node under the control of the first scan signal, so that the driving transistor included in the driving circuit is in an on-state bias state;
  • the first light-emitting control circuit controls the connection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the first light-emitting control signal
  • the second light-emitting control circuit controls the connection between the second terminal of the driving circuit and the first pole of the light-emitting element under the control of the second light-emitting control signal
  • the driving circuit drives the light-emitting element
  • the display cycle further includes a refresh frame arranged between the hold frames;
  • the refresh frame includes a pre-write bias phase arranged before the data write phase;
  • the pixel driving method includes:
  • the first initialization circuit writes a first initial voltage to the first node under the control of the first control signal; the second initialization circuit writes a second initial voltage to the third node under the control of the first scan signal, so that the driving transistor included in the driving circuit is in an on-state bias state.
  • the driving transistor included in the control driving circuit in an on-state bias state, and the Vth of the driving transistor is pulled down without being affected by the data voltage of the previous frame, thereby improving FFR.
  • the display cycle further includes a refresh frame arranged between the hold frames; the refresh frame further includes a post-write bias phase arranged after the data write phase; the pixel driving method includes:
  • the first initialization circuit writes a first initial voltage to the first node under the control of the first control signal; the second initialization circuit writes a second initial voltage to the third node under the control of the first scan signal, so that the driving transistor included in the driving circuit is in an on-state bias state.
  • the pixel circuit includes a data writing circuit; and the pixel driving method further includes:
  • the data writing circuit controls the data voltage on the data line to be written into the second node under the control of the second scanning signal provided by the second scanning terminal.
  • the pixel circuit further includes a compensation control circuit; the refresh frame further includes a compensation phase; the data writing phase is included in the compensation phase, and the data writing phase is arranged before the post-write bias phase; the pixel driving method includes:
  • the compensation control circuit controls the connection between the first node and the third node under the control of the second control signal provided by the second control terminal.
  • the pixel circuit further includes a light emitting element, a first light emitting control circuit and a second light emitting control circuit;
  • the refresh frame further includes a refresh light emitting phase arranged after the post-write bias phase;
  • the hold frame includes a hold light emitting phase;
  • the pixel driving method further comprises:
  • the first light-emitting control circuit controls the connection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the first light-emitting control signal
  • the second light-emitting control circuit controls the connection between the second terminal of the driving circuit and the first pole of the light-emitting element under the control of the second light-emitting control signal
  • the driving circuit drives the light-emitting element
  • the pixel circuit further includes a light emitting element, a first light emitting control circuit and a second light emitting control circuit;
  • the refresh frame further includes a refresh light emitting phase;
  • the post-write bias phase includes a plurality of refresh bias time periods, and the refresh light-emitting phase includes a plurality of refresh light-emitting time periods; the refresh bias time periods and the refresh light-emitting time periods are alternately arranged;
  • the pixel driving method comprises:
  • the first initialization circuit writes a first initial voltage to the first node under the control of the first control signal;
  • the second initialization circuit writes a second initial voltage to the third node under the control of the first scan signal, so that the driving transistor included in the driving circuit is in an on-state bias state;
  • the first light-emitting control circuit controls the connection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the first light-emitting control signal
  • the second light-emitting control circuit controls the connection between the second terminal of the driving circuit and the first pole of the light-emitting element under the control of the second light-emitting control signal
  • the driving circuit drives the light-emitting element
  • the compensation control circuit includes a first compensation control transistor and a second compensation control transistor, and the pixel circuit further includes a third initialization circuit; and the pixel driving method further includes:
  • the third initialization circuit writes the third initialization voltage into the middle node under the control of the light emitting control signal.
  • the display device described in the embodiment of the present disclosure includes the above-mentioned pixel circuit.

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Abstract

一种像素电路、像素驱动方法和显示装置。像素电路包括驱动电路（10）、第一初始化电路（11）和第二初始化电路（12）；驱动电路（10）用于在第一节点（N1）的电位的控制下，产生由第二节点（N2）流向第三节点（N3）的电流；第一初始化电路（11）在第一控制信号的控制下，将第一初始电压（Vinit1）写入第一节点（N1）；第二初始化电路（12）在第一扫描信号的控制下，将第二初始电压（Vinit2）写入第三节点（N3），能够改善频率切换差异。

Description

像素电路、像素驱动方法和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路、像素驱动方法和显示装置。
背景技术
在相关技术中，关于VRR(频率切换差异)，表现为频率切换前后亮度和色坐标存在差异。在显示频率切换时，由于像素电路中的驱动晶体管的阈值电压存在差异，会发生亮度差异，很容易被人眼捕捉。
发明内容
在一个方面中，本公开实施例提供一种像素电路包括驱动电路、第一初始化电路和第二初始化电路；
所述驱动电路的控制端与第一节点电连接，所述驱动电路的第一端与第二节点电连接，所述驱动电路的第二端与第三节点电连接，所述驱动电路用于在所述第一节点的电位的控制下，产生由所述第二节点流向所述第三节点的电流；
所述第一初始化电路分别与第一控制端、第一初始电压线和第一节点电连接，用于在所述第一控制端提供的第一控制信号的控制下，将第一初始电压线提供的第一初始电压写入第一节点；
所述第二初始化电路分别与第一扫描端、第二初始电压线和所述第三节点电连接，用于在所述第一扫描端提供的第一扫描信号的控制下，将第二初始电压线提供的第二初始电压写入所述第三节点。
可选的，所述驱动电路包括的驱动晶体管为p型晶体管，所述第一初始电压的电压值与所述第二初始电压的电压值之间的差值小于所述驱动晶体管的阈值电压；或者，
所述驱动电路包括的驱动晶体管为n型晶体管，所述第一初始电压的电 压值与所述第二初始电压的电压值之间的差值大于所述驱动晶体管的阈值电压。
可选的，本公开至少一实施例所述的像素电路还包括数据写入电路、补偿控制电路和储能电路；
所述数据写入电路分别与第二扫描端、数据线和所述第二节点电连接，用于在所述第二扫描端提供的第二扫描信号的控制下，将所述数据线上的数据电压写入所述第二节点；
所述补偿控制电路分别与第二控制端、所述第一节点和所述第三节点电连接，用于在所述第二控制端提供的第二控制信号的控制下，控制所述第一节点与所述第三节点之间连通或断开；
所述储能电路的第一端与第一节点电连接，所述储能电路的第二端与第一电压端电连接，所述储能电路用于储存电能。
可选的，本公开至少一实施例所述的像素电路还包括数据写入电路和储能电路；
所述数据写入电路分别与第二扫描端、数据线和所述第一节点电连接，用于在所述第二扫描端提供的第二扫描信号的控制下，将所述数据线上的数据电压写入所述第一节点；
所述储能电路的第一端与第一节点电连接，所述储能电路的第二端与第一电压端电连接，所述储能电路用于储存电能。
可选的，本公开至少一实施例所述的像素电路还包括第一储能电路、第二储能电路、数据写入电路和补偿控制电路；
所述第一储能电路的第一端与第一节点电连接，所述第一储能电路的第二端与所述第二储能电路的第一端电连接，所述第二储能电路的第二端与第一电压端电连接；所述第一储能电路和所述第二储能电路用于储存电能；
所述数据写入电路分别与第二扫描端、数据线和所述第一储能电路的第二端电连接，用于在所述第二扫描端提供的第二扫描信号的控制下，将所述数据线上的数据电压写入所述第一储能电路的第二端；
所述补偿控制电路分别与第二控制端、所述第一节点和所述第三节点电连接，用于在所述第二控制端提供的第二控制信号的控制下，控制所述第一 节点与所述第三节点之间连通或断开。
可选的，所述补偿控制电路包括第一晶体管，所述第一晶体管的栅极与所述第二控制端电连接，所述第一晶体管的第一极与所述第一节点电连接，所述第一晶体管的第二极与所述第三节点电连接；所述第一晶体管为双栅晶体管。
可选的，所述补偿控制电路包括第一补偿控制晶体管和第二补偿控制晶体管；所述第一补偿控制晶体管的栅极与所述第二控制端电连接，所述第一补偿控制晶体管的第一极与第一节点电连接，所述第一补偿控制晶体管的第二极与中间节点电连接；所述第二补偿控制晶体管的栅极与所述第二控制端电连接，所述第二补偿控制晶体管的第一极与中间节点电连接，所述第二补偿控制晶体管的第二极与所述第三节点电连接；所述像素电路还包括第三初始化电路；
所述第三初始化电路分别与发光控制端、第三初始电压线和所述中间节点电连接，用于在所述发光控制端提供的发光控制信号的控制下，将所述第三初始电压线提供的第三初始电压写入所述中间节点。
可选的，本公开至少一实施例所述的像素电路还包括发光元件、第一发光控制电路和第二发光控制电路；
所述第一发光控制电路分别与第一发光控制端、电源电压端和所述驱动电路的第一端电连接，用于在所述第一发光控制端提供的第一发光控制信号的控制下，控制所述电源电压端与所述驱动电路的第一端之间连通或断开；
所述第二发光控制电路分别与第二发光控制端、所述驱动电路的第二端和所述发光元件的第一极电连接，用于在所述第二发光控制端提供的第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通或断开；
所述发光元件的第二极与第二电压端电连接。
可选的，本公开至少一实施例所述的像素电路还包括第四初始化电路；
所述第四初始化电路分别与第一扫描端、第四初始电压线和所述发光元件的第一极电连接，用于在所述第一扫描端提供的第一扫描信号的控制下，将所述第四初始电压线提供的第四初始电压写入所述发光元件的第一极。
可选的，所述驱动电路包括驱动晶体管，所述第一初始化电路包括第二晶体管，所述第二初始化电路包括第三晶体管；
所述驱动晶体管的栅极与所述第一节点电连接，所述驱动晶体管的第一极与所述第二节点电连接，所述驱动晶体管的第二极与所述第三节点电连接；
所述第二晶体管的栅极与所述第一控制端电连接，所述第二晶体管的第一极与所述第一初始电压线电连接，所述第二晶体管的第二极与所述第一节点电连接；
所述第三晶体管的栅极与第一扫描端电连接，所述第三晶体管的第一极与第二初始电压线电连接，所述第三晶体管的第二极与第三节点电连接。
可选的，所述数据写入电路包括第四晶体管；
所述第四晶体管的栅极与所述第二扫描端电连接，所述第四晶体管的第一极与所述数据线电连接，所述第四晶体管的第二极与所述第二节点电连接；
所述储能电路包括存储电容；
所述存储电容的第一端与第一节点电连接，所述存储电容的第二端与电源电压端电连接。
可选的，所述数据写入电路包括第四晶体管；
所述第四晶体管的栅极与所述第二扫描端电连接，所述第四晶体管的第一极与所述数据线电连接，所述第四晶体管的第二极与所述第一节点电连接；
所述储能电路包括存储电容；
所述存储电容的第一端与第一节点电连接，所述存储电容的第二端与第一电压端电连接。
可选的，所述数据写入电路包括第四晶体管；
所述第四晶体管的栅极与所述第二扫描端电连接，所述第四晶体管的第一极与所述数据线电连接，所述第四晶体管的第二极与所述第一储能电路的第二端电连接；
所述第一储能电路包括第一存储电容，所述第二储能电路包括第二存储电容；
所述第一存储电容的第一端与第一节点电连接，所述第一存储电容的第二端与所述第二存储电容的第一端电连接，所述第二存储电容的第二端与第 一电压端电连接。
可选的，所述第一发光控制电路包括第五晶体管，所述第二发光控制电路包括第六晶体管；
所述第五晶体管的栅极与所述第一发光控制端电连接，所述第五晶体管的第一极与所述电源电压端电连接，所述第五晶体管的第二极与所述驱动电路的第一端电连接；
所述第六晶体管的栅极与所述第二发光控制端电连接，所述第六晶体管的第一极与所述驱动电路的第二端电连接，所述第六晶体管的第二极与所述发光元件的第一极电连接。
可选的，所述第四初始化电路包括第七晶体管；
所述第七晶体管的栅极与所述第一扫描端电连接，所述第七晶体管的第一极与所述第四初始电压线电连接，所述第七晶体管的第二极与所述发光元件的第一极电连接。
可选的，所述第三初始化电路包括第八晶体管；
所述第八晶体管的栅极与所述发光控制端电连接，所述第八晶体管的第一极与所述第三初始电压线电连接，所述第八晶体管的第二极与所述中间节点电连接。
在第三个方面中，本公开实施例提供一种像素驱动方法，应用于上述的像素电路，显示周期包括保持帧，所述保持帧包括保持偏置阶段；所述像素驱动方法包括：
在所述保持偏置阶段，第一初始化电路在第一控制信号的控制下，将第一初始电压写入第一节点；第二初始化电路在第一扫描信号的控制下，将第二初始电压写入第三节点，以使得驱动电路包括的驱动晶体管处于开态偏置状态。
可选的，所述像素电路还包括第一发光控制电路、第二发光控制电路和发光元件；
所述保持偏置阶段包括多个保持偏置时间段；所述保持帧还包括多个保持发光时间段；所述保持偏置时间段和所述保持发光时间段交替设置，所述像素驱动方法包括：
在所述保持偏置时间段，第一初始化电路在第一控制信号的控制下，将第一初始电压写入第一节点；第二初始化电路在第一扫描信号的控制下，将第二初始电压写入第三节点，以使得驱动电路包括的驱动晶体管处于开态偏置状态；
在所述保持发光时间段，第一发光控制电路在第一发光控制信号的控制下，控制电源电压端与驱动电路的第一端之间连通，第二发光控制电路在所述第二发光控制信号的控制下，控制所述驱动电路的第二端与发光元件的第一极之间连通，驱动电路驱动发光元件。
可选的，所述显示周期还包括设置于所述保持帧之间的刷新帧；所述刷新帧包括设置于数据写入阶段之前的写入前偏置阶段；所述像素驱动方法包括：
在所述写入前偏置阶段，第一初始化电路在第一控制信号的控制下，将第一初始电压写入第一节点；第二初始化电路在第一扫描信号的控制下，将第二初始电压写入第三节点，以使得驱动电路包括的驱动晶体管处于开态偏置状态。
可选的，所述显示周期还包括设置于所述保持帧之间的刷新帧；所述刷新帧还包括设置于数据写入阶段之后的写入后偏置阶段；所述像素驱动方法包括：
在写入后偏置阶段，第一初始化电路在第一控制信号的控制下，将第一初始电压写入第一节点；第二初始化电路在第一扫描信号的控制下，将第二初始电压写入第三节点，以使得驱动电路包括的驱动晶体管处于开态偏置状态。
可选的，所述像素电路包括数据写入电路；所述像素驱动方法还包括：
在所述数据写入阶段，数据写入电路在第二扫描端提供的第二扫描信号的控制下，控制将数据线上的数据电压写入第二节点。
可选的，所述像素电路还包括补偿控制电路；所述刷新帧还包括补偿阶段；所述数据写入阶段包含于所述补偿阶段，所述数据写入阶段设置于所述写入后偏置阶段之前；所述像素驱动方法包括：
在补偿阶段，补偿控制电路在第二控制端提供的第二控制信号的控制下， 控制所述第一节点与所述第三节点之间连通。
可选的，所述像素电路还包括发光元件、第一发光控制电路和第二发光控制电路；所述刷新帧还包括设置于所述写入后偏置阶段之后的刷新发光阶段；所述保持帧包括保持发光阶段；
所述像素驱动方法还包括：
在刷新发光阶段和保持发光阶段，第一发光控制电路在第一发光控制信号的控制下，控制电源电压端与驱动电路的第一端之间连通，第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与发光元件的第一极之间连通，驱动电路驱动发光元件。
可选的，所述像素电路还包括发光元件、第一发光控制电路和第二发光控制电路；所述刷新帧还包括刷新发光阶段；
所述写入后偏置阶段包括多个刷新偏置时间段，所述刷新发光阶段包括多个刷新发光时间段；所述刷新偏置时间段和所述刷新发光时间段交替设置；
所述像素驱动方法包括：
在所述刷新偏置时间段，第一初始化电路在第一控制信号的控制下，将第一初始电压写入第一节点；第二初始化电路在第一扫描信号的控制下，将第二初始电压写入第三节点，以使得驱动电路包括的驱动晶体管处于开态偏置状态；
在所述刷新发光时间段，第一发光控制电路在第一发光控制信号的控制下，控制电源电压端与驱动电路的第一端之间连通，第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与发光元件的第一极之间连通，驱动电路驱动发光元件。
可选的，所述补偿控制电路包括第一补偿控制晶体管和第二补偿控制晶体管，所述像素电路还包括第三初始化电路；所述像素驱动方法还包括：
在刷新发光阶段和保持发光阶段，所述第三初始化电路在发光控制信号的控制下，将第三初始电压写入中间节点。
在第三个方面中，本公开实施例提供一种显示装置，包括上述的像素电路。
附图说明
图1是本公开至少一实施例所述的像素电路的结构图；
图2是本公开至少一实施例所述的像素电路的结构图；
图3是本公开至少一实施例所述的像素电路的结构图；
图4是本公开至少一实施例所述的像素电路的结构图；
图5是本公开至少一实施例所述的像素电路的结构图；
图6是本公开至少一实施例所述的像素电路的结构图；
图7是本公开至少一实施例所述的像素电路的结构图；
图8是本公开至少一实施例所述的像素电路的电路图；
图9是图8所示的像素电路的至少一实施例的工作时序图；
图10是图8所示的像素电路的至少一实施例的工作时序图；
图11是生成图8所示的像素电路的至少一实施例的各GOA(Gate On Array，设置于阵列基板上的栅极驱动电路)电路的工作时序图；
图12是图8所示的像素电路的至少一实施例的工作时序图；
图13是生成图8所示的像素电路的至少一实施例的各GOA电路的工作时序图；
图14是发光控制信号生成电路包括的一级发光控制信号生成单元的电路图；
图15是图8所示的像素电路的至少一实施例的工作时序图；
图16是图8所示的像素电路的至少一实施例的工作时序图；
图17是本公开至少一实施例所述的像素电路的电路图；
图18是本公开至少一实施例所述的像素电路的电路图；
图19是各初始电压线在衬底基板上的正投影的示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一电极，另一极称为第二电极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一电极可以为漏极，所述第二电极可以为源极；或者，所述第一电极可以为源极，所述第二电极可以为漏极。
如图1所示，本公开至少一实施例所述的像素电路包括驱动电路10、第一初始化电路11和第二初始化电路12；
所述驱动电路10的控制端与第一节点N1电连接，所述驱动电路10的第一端与第二节点N2电连接，所述驱动电路10的第二端与第三节点N3电连接，所述驱动电路10用于在所述第一节点N1的电位的控制下，产生由所述第二节点N2流向所述第三节点N3的电流；
所述第一初始化电路11分别与第一控制端EM21、第一初始电压线I1和第一节点N1电连接，用于在所述第一控制端EM21提供的第一控制信号的控制下，将第一初始电压线I1提供的第一初始电压Vinit1写入第一节点N1；
所述第二初始化电路12分别与第一扫描端G1、第二初始电压线I2和所述第三节点N3电连接，用于在所述第一扫描端G1提供的第一扫描信号的控制下，将第二初始电压线I2提供的第二初始电压Vinit2写入所述第三节点N3。
本公开图1所示的像素电路的至少一实施例设置了第一初始化电路11和第二初始化电路12；所述第一初始化电路11在第一控制信号的控制下，将第一初始电压Vinit1写入第一节点N1；第二初始化电路12在第一扫描信号的控制下，将第二初始电压Vinit2写入所述第三节点N3，以控制对所述驱动电路10包括的驱动晶体管处于开态偏置状态。
在本公开至少一实施例中，当第一节点N1的电位为Vinit1，第三节点N3的电位为Vinit2时，能够使得所述驱动电路10包括的晶体管处于开态偏置状态。
本公开图1所示的像素电路的至少一实施例在工作时，显示周期可以包括保持帧；所述保持帧可以包括设置于所述保持发光阶段之前的保持偏置阶 段；
在所述保持偏置阶段，第一初始化电路11在第一控制信号的控制下，将第一初始电压Vinit1写入第一节点N1；第二初始化电路12在第一扫描信号的控制下，将第二初始电压Vinit2写入第三节点N3，以使得驱动电路10包括的驱动晶体管处于开态偏置状态，以将Vth拉低。
本公开图1所示的像素电路的至少一实施例在工作时，在保持帧包括的保持偏置阶段，控制驱动晶体管处于开态偏置状态，以将Vth拉低，以能够改善VRR(频率切换差异)。
在相关技术中，关于VRR(频率切换差异)，表现为频率切换前后亮度和色坐标存在差异。以显示频率由120Hz切换到30Hz为例，当显示频率为120Hz时，每帧都在刷新，当显示频率为30Hz时，则刷新一帧保持三帧。在刷新帧，Vth会负偏，在保持帧，Vth恢复稳定。当显示频率为120Hz时，在每一帧Vth都会进行负偏；而当显示频率为30Hz时，在刷新帧Vth负偏，而在保持帧Vth恢复。因此在显示频率切换时，由于Vth存在差异，会发生亮度差异，很容易被人眼捕捉。基于此，本公开至少一实施例在保持帧，在保持发光阶段之前，在保持偏置阶段，控制驱动晶体管处于开态偏置状态，将Vth拉低，减小刷新帧与保持帧之间的Vth差异，以便能改善VRR。
在本公开至少一实施例中，在刷新帧的Vth与在保持帧的Vth之间的差值的绝对值可以小于等于0.2V，但不以此为限。在具体实施时，该差值的绝对值可以根据实际情况选定。
可选的，Vinit1的电压值可以大于等于-5V而小于等于-3V，Vinit2的电压值可以大于等于5V而小于等于7V，但不以此为限。
在具体实施时，以T0为p型晶体管为例说明，在各偏置阶段，将Vinit1接入第一节点N1，将Vinit3写入第三节点N3，T0导通，将Vinit2写入第二节点N2，T0的栅源电压Vgs小于T0的阈值电压Vth，T0的栅源电压Vgs的绝对值较大，会在T0的开关处捕获较多空穴，使得Vth负偏。
本公开图1所示的像素电路的至少一实施例在工作时，显示周期包括刷新帧，所述刷新帧包括设置于数据写入阶段之前的写入前偏置阶段；
在写入前偏置阶段，第一初始化电路在第一控制信号的控制下，将第一 初始电压写入第一节点；第二初始化电路在第一扫描信号的控制下，将第二初始电压写入第三节点，以使得驱动电路包括的驱动晶体管处于开态偏置状态。
本公开图1所示的像素电路的至少一实施例在工作时，
在刷新帧，在数据写入充电之前，控制驱动电路包括的驱动晶体管处于开态偏置状态，将驱动晶体管的阈值电压Vth拉低，而不受上一帧的数据电压的影响，则可以解决FFR(首帧响应速率)问题。
在相关技术中，通过机理分析发现FFR与驱动晶体管的阈值电压有较大关系；在显示黑画面时，数据电压Vdata的电压值较大，阈值电压Vth负偏较多；在显示白画面时，数据电压Vdata的电压值较小，阈值电压Vth负偏较少。这种Vth差异造成在黑画面切换为白画面的瞬间，Vth还处于黑画面状态，则白画面数据电压首先要弥补部分Vth，造成切换画面中首帧亮度低，基于此，本公开至少一实施例在刷新帧，在通过数据电压充电之前，通过控制驱动晶体管处于开态偏置状态，将Vth拉低，以解决FFR问题。
在相关技术中，低频技术已经广泛应用于中小显示面板上，但多数为采用LTPO(低温多晶氧化物)材料的OLED(有机发光二极管)显示面板。由于LTPO面板技术复杂，成本较高。为此许多面板厂家追求LTPS(Low Temperature Poly-Silicon，低温多晶硅)低频显示，并也追求更高频率显示与低频显示进行兼容，高频如144Hz或165Hz，低频如40Hz或30Hz。相关的像素电路在高频下FFR较差，在低频下VRR较差。
综上，本公开至少一实施例所述的像素电路能够改善VRR和FFR，可以同时实现高频显示和低频显示。
可选的，所述驱动电路包括的驱动晶体管为p型晶体管，所述第一初始电压的电压值与所述第二初始电压的电压值之间的差值小于所述驱动晶体管的阈值电压；或者，
所述驱动电路包括的驱动晶体管为n型晶体管，所述第一初始电压的电压值与所述第二初始电压的电压值之间的差值大于所述驱动晶体管的阈值电压。
在具体实施时，可以通过设置第一初始电压的电压值与第二初始电压的 电压值，以控制所述驱动晶体管能够处于开态偏置状态。
本公开至少一实施例所述的像素电路还包括数据写入电路、补偿控制电路和储能电路；
所述数据写入电路分别与第二扫描端、数据线和所述第二节点电连接，用于在所述第二扫描端提供的第二扫描信号的控制下，将所述数据线上的数据电压写入所述第二节点；
所述补偿控制电路分别与第二控制端、所述第一节点和所述第三节点电连接，用于在所述第二控制端提供的第二控制信号的控制下，控制所述第一节点与所述第三节点之间连通或断开；
所述储能电路的第一端与第一节点电连接，所述储能电路的第二端与第一电压端电连接，所述储能电路用于储存电能。
在具体实施时，本公开至少一实施例所述的像素电路还可以包括数据写入电路和补偿控制电路，所述数据写入电路在第二扫描信号的控制下，将数据电压写入第二节点；所述补偿控制电路在第二控制信号的控制下，控制所述第一节点与所述第二节点之间连通或断开，以进行阈值电压补偿。
可选的，所述第一电压端可以为电源电压端或参考电压端；在实际操作时，所述第一电压端可以为直流电压端，但不以此为限。
如图2所示，在图1所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括数据写入电路21、补偿控制电路22和储能电路23；
所述数据写入电路21分别与第二扫描端G2、数据线Da和所述第二节点N2电连接，用于在所述第二扫描端G2提供的第二扫描信号的控制下，将所述数据线Da上的数据电压Vdata写入所述第二节点N2；
所述补偿控制电路22分别与第二控制端EM2、所述第一节点N1和所述第三节点N3电连接，用于在所述第二控制端EM2提供的第二控制信号的控制下，控制所述第一节点N1与所述第三节点N3之间连通或断开；
所述储能电路23的第一端与第一节点N1电连接，所述储能电路23的第二端与电源电压端VDD电连接，所述储能电路23用于储存电能。
本公开图2所示的驱动电路的至少一实施例在工作时，所述刷新帧还包 括补偿阶段，所述数据写入阶段包含于所述补偿阶段，所述数据写入阶段设置于所述写入后偏置阶段之前；
在所述数据写入阶段，数据写入电路21在第二扫描端G2提供的第二扫描信号的控制下，控制将数据线Da上的数据电压Vdata写入第二节点N2。
在补偿阶段，补偿控制电路22在第二控制端EM2提供的第二控制信号的控制下，控制所述第一节点N1与所述第三节点N3之间连通。
如图3所示，在图1所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括数据写入电路21和储能电路23；
所述数据写入电路21分别与第二扫描端G2、数据线Da和所述第一节点N1电连接，用于在所述第二扫描端G2提供的第二扫描信号的控制下，将所述数据线Da上的数据电压Vdata写入所述第一节点N1；
所述储能电路23的第一端与第一节点N1电连接，所述储能电路23的第二端与电源电压端VDD电连接，所述储能电路23用于储存电能。
本公开图3所示的像素电路的至少一实施例在工作时，在数据写入阶段，所述数据写入电路21在第二扫描信号的控制下，将所述数据线Da上的数据电压Vdata写入所述第一节点N1，以进行数据电压写入。
如图4所示，在图1所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括第一储能电路231、第二储能电路232、数据写入电路21和补偿控制电路22；
所述第一储能电路231的第一端与第一节点N1电连接，所述第一储能电路231的第二端与所述第二储能电路232的第一端电连接，所述第二储能电路232的第二端与电源电压端VDD电连接；所述第一储能电路231和所述第二储能电路232用于储存电能；
所述数据写入电路21分别与第二扫描端G2、数据线Da和所述第一储能电路231的第二端电连接，用于在所述第二扫描端G2提供的第二扫描信号的控制下，将所述数据线Da上的数据电压Vdata写入所述第一储能电路231的第二端；
所述补偿控制电路22分别与第二控制端EM2、所述第一节点N1和所述第三节点N3电连接，用于在所述第二控制端EM2提供的第二控制信号的控 制下，控制所述第一节点N1与所述第三节点N3之间连通或断开。
可选的，所述补偿控制电路包括第一晶体管，所述第一晶体管为双栅晶体管，所述第一晶体管的栅极与所述第二控制端电连接，所述第一晶体管的第一极与所述第一节点电连接，所述第一晶体管的第二极与所述第三节点电连接。
在本公开至少一实施例中，所述补偿控制电路包括的第一晶体管可以为双栅晶体管，双栅晶体管的漏电流较小，以能够较好的维持第一节点的电位。
在本公开至少一实施例中，所述补偿控制电路包括第一补偿控制晶体管和第二补偿控制晶体管；所述第一补偿控制晶体管的栅极与所述第二控制端电连接，所述第一补偿控制晶体管的第一极与第一节点电连接，所述第一补偿控制晶体管的第二极与中间节点电连接；所述第二补偿控制晶体管的栅极与所述第二控制端电连接，所述第二补偿控制晶体管的第一极与中间节点电连接，所述第二补偿控制晶体管的第二极与所述第三节点电连接；所述像素电路还包括第三初始化电路；
所述第三初始化电路分别与发光控制端、第三初始电压线和所述第一晶体管的中间节点电连接，用于在所述发光控制端提供的发光控制信号的控制下，将所述第三初始电压线提供的第三初始电压写入所述中间节点。
在具体实施时，所述补偿控制电路可以包括第一补偿控制晶体管和第二补偿控制晶体管，所述像素电路还可以包括第三初始化电路，所述第三初始化电路在发光控制信号的控制下，将第三初始电压写入中间节点，以在发光阶段，控制所述中间阶段接入第三初始电压，以减小第一节点N1的漏电，利于保持第一节点N1的电位。
如图5所示，在图2所示的像素电路的至少一实施例的基础上，所述补偿控制电路包括第一补偿控制晶体管T11和第二补偿控制晶体管T12，所述像素电路还包括第三初始化电路31；
所述第一补偿控制晶体管T11的栅极与所述第二控制端EM2电连接，所述第一补偿控制晶体管T11的源极与第一节点N1电连接，所述第一补偿控制晶体管T11的漏极与中间节点电连接；
所述第二补偿控制晶体管T12的栅极与所述第二控制端EM2电连接，所 述第二补偿控制晶体管T12的源极与中间节点电连接，所述第二补偿控制晶体管T12的漏极与所述第三节点N3电连接；
所述第三初始化电路31分别与发光控制端EM1、第三初始电压线I3和所述中间节点电连接，用于在所述发光控制端EM1提供的发光控制信号的控制下，将所述第三初始电压线I3提供的第三初始电压Vinit3写入所述中间节点。
本公开如图5所示的像素电路的至少一实施例在工作时，在刷新发光阶段和保持发光阶段，第三初始化电路31在发光控制信号的控制下，将第三初始电压Vinit3写入中间节点，第三初始电压Vinit3的电压值与第一节点N1的电位相差不大，以减小第一节点N1的漏电，利于维持第一节点N1的电位。
本公开至少一实施例所述的像素电路还包括发光元件、第一发光控制电路和第二发光控制电路；
所述第一发光控制电路分别与第一发光控制端、电源电压端和所述驱动电路的第一端电连接，用于在所述第一发光控制端提供的第一发光控制信号的控制下，控制所述电源电压端与所述驱动电路的第一端之间连通或断开；
所述第二发光控制电路分别与第二发光控制端、所述驱动电路的第二端和所述发光元件的第一极电连接，用于在所述第二发光控制端提供的第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通或断开；
所述发光元件的第二极与第二电压端电连接。
在具体实施时，本公开至少一实施例所述的像素电路还可以包括发光元件、第一发光控制电路和第二发光控制电路，第一发光控制电路和第二发光控制电路能够进行发光控制。
在本公开至少一实施例中，所述第一发光控制端和所述第二发光控制端可以都为发光控制端，但不以此为限；在实际操作时，所述第一发光控制端和所述第二发光控制端也可以不同。
如图6所示，在图5所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括发光元件40、第一发光控制电路41和第二发光控制电路42；
所述第一发光控制电路41分别与发光控制端EM1、电源电压端VDD和所述驱动电路10的第一端电连接，用于在所述发光控制端EM1提供的发光控制信号的控制下，控制所述电源电压端VDD与所述驱动电路10的第一端之间连通或断开；
所述第二发光控制电路42分别与所述发光控制端EM1、所述驱动电路10的第二端和所述发光元件40的第一极电连接，用于在所述发光控制信号的控制下，控制所述驱动电路10的第二端与所述发光元件40的第一极之间连通或断开；
所述发光元件40的第二极与第二电压端V2电连接。
在图6所示的至少一实施例中，第一发光控制端和第二发光控制端都为发光控制端EM1，但不以此为限。在实际操作时，所述第一发光控制端和所述第二发光控制端也可以为不同的控制端。
可选的，所述发光元件可以为有机发光二极管，发光元件的第一极可以为阳极，发光元件的第二极可以为阴极，所述第二电压端V2可以为低电压端。
本公开至少一实施例所述的像素电路还可以包括第四初始化电路；
所述第四初始化电路分别与第一扫描端、第四初始电压线和所述发光元件的第一极电连接，用于在所述第一扫描端提供的第一扫描信号的控制下，将所述第四初始电压线提供的第四初始电压写入所述发光元件的第一极。
在具体实施时，本公开至少一实施例所述的像素电路还可以包括第四初始化电路；所述第四初始化电路在第一扫描信号的控制下，将所述第四初始电压线提供的第四初始电压写入所述发光元件的第一极，以对所述发光元件的第一极的电位进行复位，清除所述发光元件的第一极残留的电荷，并控制所述发光元件不发光。
在本公开至少一实施例中，所述第四初始电压的电压值与所述第二电压端V2提供的第二电压信号的电压值之间的差值可以小于所述发光元件的启亮电压。
可选的，所述第四初始电压的电压值与所述第二电压端V2提供的第二电压信号的电压值之间的差值的绝对值可以小于电压差值阈值；例如，所述 电压差值阈值可以为1V，但不以此为限。
如图7所示，在图6所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括第四初始化电路51；
所述第四初始化电路51分别与第一扫描端G1、第四初始电压线I4和所述发光元件的第一极电连接，用于在所述第一扫描端G1的第一扫描信号的控制下，将所述第四初始电压线I4的第四初始电压Vinit4写入所述发光元件40的第一极。
可选的，所述驱动电路包括驱动晶体管，所述第一初始化电路包括第二晶体管，所述第二初始化电路包括第三晶体管；
所述驱动晶体管的栅极与所述第一节点电连接，所述驱动晶体管的第一极与所述第二节点电连接，所述驱动晶体管的第二极与所述第三节点电连接；
所述第二晶体管的栅极与所述第一控制端电连接，所述第二晶体管的第一极与所述第一初始电压线电连接，所述第二晶体管的第二极与所述第一节点电连接；
所述第三晶体管的栅极与第一扫描端电连接，所述第三晶体管的第一极与第二初始电压线电连接，所述第三晶体管的第二极与第三节点电连接。
可选的，所述数据写入电路包括第四晶体管；
所述第四晶体管的栅极与所述第二扫描端电连接，所述第四晶体管的第一极与所述数据线电连接，所述第四晶体管的第二极与所述第二节点电连接；
所述储能电路包括存储电容；
所述存储电容的第一端与第一节点电连接，所述存储电容的第二端与电源电压端电连接。
可选的，所述数据写入电路包括第四晶体管；
所述第四晶体管的栅极与所述第二扫描端电连接，所述第四晶体管的第一极与所述数据线电连接，所述第四晶体管的第二极与所述第一节点电连接；
所述储能电路包括存储电容；
所述存储电容的第一端与第一节点电连接，所述存储电容的第二端与第一电压端电连接。
可选的，所述数据写入电路包括第四晶体管；
所述第四晶体管的栅极与所述第二扫描端电连接，所述第四晶体管的第一极与所述数据线电连接，所述第四晶体管的第二极与所述第一储能电路的第二端电连接；
所述第一储能电路包括第一存储电容，所述第二储能电路包括第二存储电容；
所述第一存储电容的第一端与第一节点电连接，所述第一存储电容的第二端与所述第二存储电容的第一端电连接，所述第二存储电容的第二端与第一电压端电连接。
可选的，所述第一发光控制电路包括第五晶体管，所述第二发光控制电路包括第六晶体管；
所述第五晶体管的栅极与所述第一发光控制端电连接，所述第五晶体管的第一极与所述电源电压端电连接，所述第五晶体管的第二极与所述驱动电路的第一端电连接；
所述第六晶体管的栅极与所述第二发光控制端电连接，所述第六晶体管的第一极与所述驱动电路的第二端电连接，所述第六晶体管的第二极与所述发光元件的第一极电连接。
可选的，所述第四初始化电路包括第七晶体管；
所述第七晶体管的栅极与所述第一扫描端电连接，所述第七晶体管的第一极与所述第四初始电压线电连接，所述第七晶体管的第二极与所述发光元件的第一极电连接。
可选的，所述第三初始化电路包括第八晶体管；
所述第八晶体管的栅极与所述发光控制端电连接，所述第八晶体管的第一极与所述第三初始电压线电连接，所述第八晶体管的第二极与所述中间节点电连接。
如图8所示，在图7所示的像素电路的至少一实施例的基础上，所述驱动电路包括驱动晶体管T0，所述第一初始化电路包括第二晶体管T2，所述第二初始化电路包括第三晶体管T3；所述发光元件为有机发光二极管O1；
所述驱动晶体管T0的栅极与所述第一节点N1电连接，所述驱动晶体管T0的源极与所述第二节点N2电连接，所述驱动晶体管T0的漏极与所述第三 节点N3电连接；
所述第二晶体管T2的栅极与所述第一控制端EM21电连接，所述第二晶体管T2的源极与所述第一初始电压线I1电连接，所述第二晶体管T2的漏极与所述第一节点N1电连接；所述第一初始电压线I1用于提供第一初始电压Vinit1；
所述第三晶体管T3的栅极与第一扫描端G1电连接，所述第三晶体管T3的源极与第二初始电压线I2电连接，所述第三晶体管T3的漏极与第三节点N3电连接；所述第二初始电压线I2用于提供第二初始电压Vinit2；
所述数据写入电路包括第四晶体管T4；所述储能电路包括存储电容Cst；
所述第四晶体管T4的栅极与所述第二扫描端G2电连接，所述第四晶体管T4的源极与所述数据线Da电连接，所述第四晶体管T4的漏极与所述第二节点N2电连接；
所述存储电容Cst的第一端与第一节点N1电连接，所述存储电容Cst的第二端与电源电压端VDD电连接
所述第一发光控制电路包括第五晶体管T5，所述第二发光控制电路包括第六晶体管T6；
所述第五晶体管T5的栅极与所述发光控制端EM1电连接，所述第五晶体管T5的源极与所述电源电压端VDD电连接，所述第五晶体管T5的漏极与所述驱动晶体管T0的源极电连接；
所述第六晶体管T6的栅极与所述发光控制端EM1电连接，所述第六晶体管T6的源极与所述驱动晶体管T0的漏极电连接，所述第六晶体管T6的漏极与所述有机发光二极管O1的阳极电连接；所述有机发光二极管O1的阴极与低电压端VSS电连接；
所述第四初始化电路包括第七晶体管T7；
所述第七晶体管T7的栅极与所述第一扫描端G1电连接，所述第七晶体管T7的源极与所述第四初始电压线I4电连接，所述第七晶体管T7的漏极与所述有机发光二极管O1的阳极电连接；所述第四初始电压线I4用于提供第四初始电压Vinit4；
所述第三初始化电路包括第八晶体管T8；
所述第八晶体管T8的栅极与所述发光控制端EM电连接，所述第八晶体管T8的源极与所述第三初始电压线I3电连接，所述第八晶体管T8的漏极与中间节点电连接；所述第三初始电压线I3用于提供第三初始电压Vinit3。
在图8所示的像素电路的至少一实施例中，所有晶体管都为p型晶体管，但不以此为限。
在图8所示的像素电路的至少一实施例中，第一电压端为电源电压端，第二电压端为低电压端，第一发光控制端和第二发光控制端都为发光控制端，但不以此为限。
在图8所示的像素电路的至少一实施例中，Vinit1的电压值可以大于等于-5V而小于等于-3V，Vinit2的电压值可以大于等于5V而小于等于7V，Vinit3的电压值可以大于等于0V而小于等于3V，Vinit4的电压值可以大于等于-4V而小于等于-2V。
在图8所示的像素电路的至少一实施例中，通过将Vinit1设置为负电压，将Vinit2设置为正电压，以使得当将Vinit1写入第一节点N1，将Vinit2写入第三节点N3时，驱动晶体管T0处于开态偏置状态；
并通过设置Vinit3，以使得在刷新发光阶段和保持发光阶段，将Vinit3写入中间节点，使得所述中间节点的电位与第一节点的电位相差不大，从而减小第一节点N1的漏电；
并通过设置Vinit4，以使得有机发光二极管O1不发光。
如图9所示，本公开如图8所示的像素电路的至少一实施例在工作时，显示周期可以包括刷新帧，所述刷新帧包括先后设置的写入前偏置阶段S11、补偿阶段S12、写入后偏置阶段S13和刷新发光阶段S14，数据写入阶段S120包含于补偿阶段S12；
在写入前偏置阶段S11，EM1提供高电压信号，G1和EM21都提供低电压信号，EM2提供高电压信号，G2提供高电压信号，T3打开，以将Vinit2写入第三节点N3，T0导通，以将Vinit2写入第二节点N2，T2打开，将Vinit1写入第一节点N1，以使得T0处于开态偏置状态，此时N1和N2之间存在较大压差，T0的栅源电压Vgs的绝对值较大，T0的阈值电压Vth负偏，可消除不同数据电压Vdata对Vth的影响，改善FFR现象；
在写入前偏置阶段S11，G1提供低电压信号，T7打开，以将Vinit4写入O1的阳极，清除O1的阳极残留的电荷；
在补偿阶段S12，EM2提供低电压信号，T11和T12打开，以控制N1与N3之间连通；
在数据写入阶段S120，G2提供低电压信号，T4打开，Da提供数据电压Vdata至第二节点N2；
在数据写入阶段S120开始时，T0导通，Vdata通过T4、T0和T2为Cst充电，以提升N1的电位，直至T0的Vgs变为Vth，T0关断，此时T0的栅极电位为Vdata+Vth；
在写入后偏置阶段S13，EM1提供高电压信号，G1提供低电压信号，EM21、EM2和G2都提供高电压信号，T3打开，以将Vinit2写入N3，T0导通，以将Vinit2写入第二节点N2，控制T0处于开态偏置状态，T7打开，以将Vinit4写入O1的阳极，清除O1的阳极残留的电荷；
在刷新发光阶段S14，EM1提供低电压信号，T5和T6打开，T0驱动O1发光，此时，N1的电位为Vdata+Vth，T0的栅源电压为Vdata+Vth-VDD，T0的驱动电流与Vth无关，以能进行阈值电压补偿；T8打开，以将Vinit3写入中间节点，Vinit3与N1的电位相差不大，以能够减少N1的漏电流，利于维持N1的电位。
在本公开如图8所示的像素电路的至少一实施例中，采用EM2以控制T11和T12的通断，EM2提供的第二控制信号可以由EM GOA电路(EM GOA电路为设置于阵列基板上的发光控制信号生成电路)提供，可以实现降低漏电和高频率显示。
如图9所示，G1提供低电压信号的时间段与EM21提供低电压信号的时间段部分交叠，G2提供低电压信号的时间段包含于EM2提供低电压信号的时间段。
在具体实施时，在写入前偏置阶段，对N1和N2同时复位，如果复位时间过程，可能会造成VRR变差，原因是T0的栅源电压Vgs过大，会将Vth负偏更厉害，在真实写入数据时，在刷新帧，Vth已经不能再进行负偏，持续刷新不存在问题。但是在保持帧不写入数据电压，Vth会逐渐恢复，会形 成刷新帧和保持帧Vth差异过大，VRR变差。基于此，本公开至少一实施例可以通过控制写入前偏置阶段持续的时间，并控制在保持帧包括的保持偏置阶段控制T0处于开态偏置状态，以改善VRR。
可选地，EM21提供低电压信号的时间比EM2提供低电压信号提前至少3行。例如：第N行GOA电路向EM21提供低电压信号，第N-3行GOA电路或第N-7行GOA电路为EM21提供低电压信号，如此设计有利于对N1节点尽早进行复位，其中，N为正整数。如图10所示，本公开如图8所示的像素电路的至少一实施例在工作时，显示周期可以包括保持帧，所述保持帧包括先后设置的保持偏置阶段S21和保持发光阶段S22；
在保持偏置阶段S21，EM1提供高电压信号，G1提供低电压信号，T3打开，以将Vinit2写入N3，控制T0处于开态偏置状态；
在保持发光阶段S22，EM1提供低电压信号，G1提供高电压信号，T5和T6打开，T0驱动O1发光。
在所述保持帧，EM21、EM2和G2都提供高电压信号。
在图8所示的像素电路的至少一实施例中，G1提供的第一扫描信号可以由第一GOA(Gate On Array，设置于阵列基板上的栅极驱动电路)电路提供，G2提供的第二扫描信号可以由第二GOA电路提供，EM1提供的发光控制信号可以由第一EM GOA电路提供，EM21提供的第一控制信号和EM2提供的第二控制信号可以由第二EM GOA电路提供，第一EM GOA电路的结构可以与第二EM GOA电路的结构相同。
图11是生成图8所示的像素电路的至少一实施例的各GOA电路的工作时序图。
在图11中，标号为GSTV2的为第二起始电压，标号为GCB2的为第二个第二时钟信号，标号为GCK2的为第二个第一时钟信号，标号为G2的为第二控制端，标号为GSTV1的为第一起始电压，标号为GCB1的为第一个第二时钟信号，标号为GCK1的为第一个第一时钟信号，标号为G1的为第一控制端，标号为ESTV2的为第二发光控制起始电压，标号为ECK2的为第二个第三时钟信号，标号为ECB2的为第二个第四时钟信号，标号为EM21的为第一控制端，标号为EM2的为第二控制端，标号为Da的为数据线，标号 为ESTV1的为第一发光控制起始电压，标号为ECK1的为第一个第三时钟信号，标号为ECB1的为第一个第四时钟信号，标号为EM1的为发光控制端。
如图12所示，本公开如图8所示的像素电路的至少一实施例在工作时，显示周期可以包括刷新帧，所述刷新帧包括先后设置的补偿阶段S12、写入后偏置阶段S13和刷新发光阶段S14，数据写入阶段S120包含于补偿阶段S12；
在补偿阶段S12，EM2提供第低电压信号，T11和T12打开，以控制N1与N3之间连通；
在数据写入阶段S120，G2提供低电压信号，T4打开，Da提供数据电压Vdata至第二节点N2；
在数据写入阶段S120开始时，T0导通，Vdata通过T4、T0和T2为Cst充电，以提升N1的电位，直至T0的Vgs变为Vth，T0关断，此时T0的栅极电位为Vdata+Vth；
在写入后偏置阶段S13，EM1提供高电压信号，G1提供低电压信号，EM21、EM2和G2都提供高电压信号，T3打开，以将Vinit2写入N3，T0导通，以将Vinit2写入第二节点N2，控制T0处于开态偏置状态，T7打开，以将Vinit4写入O1的阳极，清除O1的阳极残留的电荷；
在刷新发光阶段S14，EM1提供低电压信号，T5和T6打开，T0驱动O1发光，此时，N1的电位为Vdata+Vth，T0的栅源电压为Vdata+Vth-VDD，T0的驱动电流与Vth无关，以能进行阈值电压补偿；T8打开，以将Vinit3写入中间节点，Vinit3与N1的电位相差不大，以能够减少N1的漏电流，利于维持N1的电位。
图13是生成图8所示的像素电路的至少一实施例的各GOA电路的工作时序图。
在图13中，标号为GSTV2的为第二起始电压，标号为GCB2的为第二个第二时钟信号，标号为GCK2的为第二个第一时钟信号，标号为G2的为第二控制端，标号为GSTV1的为第一起始电压，标号为GCB1的为第一个第二时钟信号，标号为GCK1的为第一个第一时钟信号，标号为G1的为第一控制端，标号为ESTV2的为第二发光控制起始电压，标号为ECK2的为第二 个第三时钟信号，标号为ECB2的为第二个第四时钟信号，标号为EM21的为第一控制端，标号为EM2的为第二控制端，标号为Da的为数据线，标号为ESTV1的为第一发光控制起始电压，标号为ECK1的为第一个第三时钟信号，标号为ECB1的为第一个第四时钟信号，标号为EM1的为发光控制端。图14是发光控制信号生成电路包括的一级发光控制信号生成单元的电路图。
如图14所示，所述发光控制信号生成单元的至少一实施例包括第一控制晶体管M1、第二控制晶体管M2、第三控制晶体管M3、第四控制晶体管M4、第五控制晶体管M5、第六控制晶体管M6、第七控制晶体管M7、第八控制晶体管M8、第九控制晶体管M9、第十控制晶体管M10、第十一控制晶体管M11、第十二控制晶体管M12、第一电容C1、第二电容C2和第三电容C3；
M1的栅极接入第三时钟信号ECK，M2的源极与低电平端VGL电连接，M1的漏极与M11的源极电连接；
M11的栅极与低电平端VGL电连接，M11的漏极与M6的栅极电连接；
M2的栅极接入第三时钟信号ECK，M2的源极接入发光控制起始电压ESMV，M2的漏极与M3的栅极电连接；
M3的源极接入第三时钟信号ECK，M3的漏极与M1的漏极电连接；
M4的栅极与M6的栅极电连接，M4的源极与高电平端VGH电连接，M4的漏极与M5的源极电连接；
M5的栅极接入第四时钟信号ECB，M5的漏极与M3的栅极电连接；
M6的源极接入第四时钟信号ECB，M6的漏极与M7的源极电连接；
M7的栅极接入第四时钟信号ECB，M7的漏极与M9的栅极电连接；
M8的栅极与M3的栅极电连接，M8的源极与高电平端VGH电连接，M8的漏极与M9的栅极电连接；
M9的源极与高电平端VGH电连接，M9的漏极与发光控制信号输出端EO电连接；
M10的栅极与M12的漏极电连接，M10的源极与低电平端VGL电连接，M10的漏极与发光控制信号输出端EO电连接；
M12的栅极与低电平端VGL电连接，M12的源极与M8的栅极电连接；
C1的第一端与M6的栅极电连接，C2的第二端与M6的漏极电连接；
C2的第一端接入第四时钟信号ECB，C2的第二端与M10的栅极电连接；
C3的第一端与M9的栅极电连接，C3的第二端与高电平端VGH电连接。
在图14所示的至少一实施例中，各晶体管可以都为p型晶体管，但不以此为限。
当图8所示的像素电路的至少一实施例不在超高频率下使用，且最高频率为120Hz时，在保证IC(集成电路)支持的情况下，在数据写入阶段之前，可以不对N3的电位进行复位，只需要在数据写入阶段之后，对N3的电位进行复位。并且，刷新帧包括刷新发光阶段，保持帧包括保持发光阶段，所述刷新发光阶段包括多个相互独立的刷新发光时间段，所述保持发光阶段包括多个相互独立的保持发光时间段，在所述刷新发光时间段之前，在相应的刷新偏置时间段，对N3的电位进行复位，在所述保持发光时间段之前，在相应的保持偏置时间段，对N3的电位进行复位，以在保持帧，可以通过多次控制驱动晶体管处于开态偏置状态，多次拉低Vth，可有效防止Vth恢复，能改善低频下VRR现象。
如图15所示，本公开图8所示的像素电路的至少一实施例在工作时，刷新帧包括补偿阶段S12、刷新偏置阶段和刷新发光阶段；数据写入阶段S120包含于补偿阶段S12；所述补偿阶段S12设置于刷新偏置阶段和刷新发光阶段之前；
在补偿阶段S12，EM1提供高电压信号，EM2提供低电压信号，EM21提供高电压信号，G1提供高电压信号，T11和T12导通，N1和N3之间连通；
在数据写入阶段S120，G2提供低电压信号，T4打开，Da将数据电压Vdata写入N2；
在数据写入阶段S120开始时，T0导通，Vdata通过T4、T0、T11和T12为Cst充电，直至T0关断，此时T0的栅源电压为Vth，此时T0的栅极电压为Vdata+Vth；
所述刷新偏置阶段可以包括多个相互独立的刷新偏置时间段，所述刷新发光阶段包括多个相互独立的刷新发光时间段，所述刷新偏置时间段设置于相应的刷新发光时间段之前；
在图15中，标号为S31的为第一刷新偏置时间段，标号为S41的为第一 刷新发光时间段，标号为S32的为第二刷新偏置时间段，标号为S42的为第二刷新发光时间段，标号为S33的为第三刷新偏置时间段，标号为S43的为第三刷新发光时间段，标号为S34的为第四刷新偏置时间段，标号为S44的为第四刷新发光时间段，标号为S35的为第五刷新偏置时间段，标号为S45的为第五刷新发光时间段，标号为S36的为第六刷新偏置时间段，标号为S46的为第六刷新发光时间段；
在各刷新偏置时间段，G1提供低电压信号，T3打开，以将Vinit2写入N3，T0打开，对N3的电位和N2的电位进行复位，控制T0处于开态偏置状态；
在各刷新发光时间段，G1提供高电压信号，EM1提供低电压信号，T5和T6打开，T0驱动O1发光。
如图15所示，在刷新帧，EM21提供高电压信号。
如图16所示，本公开图8所示的像素电路的至少一实施例在工作时，保持帧包括保持偏置阶段和保持发光阶段；
所述保持偏置阶段可以包括多个相互独立的保持偏置时间段，所述保持发光阶段包括多个相互独立的保持发光时间段，所述保持偏置时间段设置于相应的保持发光时间段之前；
在图16中，标号为S51的为第一保持偏置时间段，标号为S61的为第一保持发光时间段，标号为S52的为第二保持偏置时间段，标号为S62的为第二保持发光时间段，标号为S53的为第三保持偏置时间段，标号为S63的为第三保持发光时间段，标号为S54的为第四保持偏置时间段，标号为S64的为第四保持发光时间段，标号为S55的为第五保持偏置时间段，标号为S65的为第五保持发光时间段，标号为S56的为第六保持偏置时间段，标号为S66的为第六保持发光时间段；
在各保持偏置时间段，G1提供低电压信号，T3打开，以将Vinit2写入N3，T0打开，对N3的电位和N2的电位进行复位，控制T0处于开态偏置状态；
在各保持发光时间段，G1提供高电压信号，EM1提供低电压信号，T5和T6打开，T0驱动O1发光。
在保持帧，EM21、EM2和G2都提供高电压信号。
本公开至少一实施例所述的像素电路改善FFR和VRR，可以实现高频显示和低频显示，可以根据不同需求适当选取应用，足以满足第一帧响应速度和切频闪烁规格。
本公开图17所示的像素电路的至少一实施例与本公开图8所示的像素电路的区别在于：不设置有T11、T12和T8，并T4的漏极与第一节点N1电连接。
本公开图17所示的像素电路的至少一实施例不能进行阈值电压补偿，基于此，本公开图8所示的像素电路的至少一实施例将T4的漏极设置为与第二节点N2电连接，并增设T11、T12和T8。
本公开图18所示的像素电路的至少一实施例与本公开图8所示的像素电路的区别在于：不包含存储电容Cst，包含第一储能电路和第二储能电路；
第一储能电路包括第一存储电容Cst1，第二储能电路包括第二存储电容Cst2；
T4的漏极与Cst1的第二端电连接；
Cst1的第一端与第一节点N1电连接，Cst1的第二端与Cst2的第一端电连接，Cst2的第二端与电源电压端VDD电连接。
在图18所示的像素电路的至少一实施例中，Cst1的电容值可以大于Cst2的电容值，以能够保证第一节点N1的电位的稳定性。
在本公开至少一实施例中，第一初始电压可以为负电压，第二初始电压可以为正电压，第三初始电压可以为正电压，第四初始电压可以为负电压。
在本公开至少一实施例中，用于提供第一初始电压Vinit1的第一初始电压线与用于提供第二初始电压Vinit2的第二初始电压线可以形成于不同的金属层，且第一初始电压线与第二初始电压线可以相互平行，避免提供正电压的电压线与提供负电压的电压线交叠，影响电压稳定性；
例如，所述第一初始电压线可以形成于第二栅金属层，所述第一初始电压线可以与像素电路包括的驱动晶体管的栅极同层设置；所述第二初始电压线可以形成于第一源漏金属层，第二初始电压线可以与驱动晶体管的源极和 漏极同层设置；另外，第二初始电压线的线宽可以大于第一初始电压线的线宽，有利于正电压的稳定，减少压降。
可选的，第一初始电压线与第四初始电压线可以形成于第一金属层，第二初始电压线和第三初始电压线可以形成于第二金属层；
例如，所述第一金属层可以为第二栅金属层，第二金属层可以为第一源漏金属层，但不依次为限。
可选的，第一初始电压线、第二初始电压线、第三初始电压线和第四初始电压线可以横向延伸，并第一初始电压线、第二初始电压线、第三初始电压线和第四初始电压线设置于衬底基板上，各初始电压线在所述衬底基板上的正投影可以在纵向上依次排列。
在本公开至少一实施例中，提供正电压的初始电压线和提供负电压的初始电压线可以交替排布，以保证衬底基板上的电荷中和，避免残留电荷对显示画面的影响。
如图19所示，标号为I11的为第一初始电压线I1在衬底基板上的正投影，标号为I21的为第二初始电压线I2在衬底基板上的正投影，标号为I31的为第三初始电压线I3在衬底基板上的正投影，标号为I41的为第四初始电压线I4在衬底基板上的正投影；
I21、I11、I31和I41沿着竖直方向依次排列；I21、I11、I31和I41相互平行。
在图19所示的至少一实施例中，I2的线宽和I3的线宽较宽。
在图19所示的至少一实施例中，所述第一初始电压线和第四初始电压线可以形成于第二栅金属层，第二初始电压线和第三初始电压线可以形成于第一源漏金属层，但不以此为限。
本公开实施例所述的像素驱动方法，应用于上述的像素电路，显示周期包括保持帧，所述保持帧包括保持偏置阶段；所述像素驱动方法包括：
在所述保持偏置阶段，第一初始化电路在第一控制信号的控制下，将第一初始电压写入第一节点；第二初始化电路在第一扫描信号的控制下，将第二初始电压写入第三节点，以使得驱动电路包括的驱动晶体管处于开态偏置状态。
在本公开至少一实施例所述的保持偏置阶段中，在保持帧包括的保持偏置阶段，控制驱动晶体管处于开态偏置状态，以将Vth拉低，以能够改善VRR(频率切换差异)。
可选的，所述像素电路还包括第一发光控制电路、第二发光控制电路和发光元件；
所述保持偏置阶段包括多个保持偏置时间段；所述保持帧还包括多个保持发光时间段；所述保持偏置时间段和所述保持发光时间段交替设置，所述像素驱动方法包括：
在所述保持偏置时间段，第一初始化电路在第一控制信号的控制下，将第一初始电压写入第一节点；第二初始化电路在第一扫描信号的控制下，将第二初始电压写入第三节点，以使得驱动电路包括的驱动晶体管处于开态偏置状态；
在所述保持发光时间段，第一发光控制电路在第一发光控制信号的控制下，控制电源电压端与驱动电路的第一端之间连通，第二发光控制电路在所述第二发光控制信号的控制下，控制所述驱动电路的第二端与发光元件的第一极之间连通，驱动电路驱动发光元件。
在本公开至少一实施例中，所述显示周期还包括设置于所述保持帧之间的刷新帧；所述刷新帧包括设置于数据写入阶段之前的写入前偏置阶段；所述像素驱动方法包括：
在所述写入前偏置阶段，第一初始化电路在第一控制信号的控制下，将第一初始电压写入第一节点；第二初始化电路在第一扫描信号的控制下，将第二初始电压写入第三节点，以使得驱动电路包括的驱动晶体管处于开态偏置状态。
在本公开至少一实施例所述的像素驱动方法中，在刷新帧，在数据写入充电之前，控制驱动电路包括的驱动晶体管处于开态偏置状态，将驱动晶体管的Vth拉低，而不受上一帧的数据电压的影响，则可以改善FFR。
在本公开至少一实施例中，所述显示周期还包括设置于所述保持帧之间的刷新帧；所述刷新帧还包括设置于数据写入阶段之后的写入后偏置阶段；所述像素驱动方法包括：
在写入后偏置阶段，第一初始化电路在第一控制信号的控制下，将第一初始电压写入第一节点；第二初始化电路在第一扫描信号的控制下，将第二初始电压写入第三节点，以使得驱动电路包括的驱动晶体管处于开态偏置状态。
可选的，所述像素电路包括数据写入电路；所述像素驱动方法还包括：
在所述数据写入阶段，数据写入电路在第二扫描端提供的第二扫描信号的控制下，控制将数据线上的数据电压写入第二节点。
在本公开至少一实施例中，所述像素电路还包括补偿控制电路；所述刷新帧还包括补偿阶段；所述数据写入阶段包含于所述补偿阶段，所述数据写入阶段设置于所述写入后偏置阶段之前；所述像素驱动方法包括：
在补偿阶段，补偿控制电路在第二控制端提供的第二控制信号的控制下，控制所述第一节点与所述第三节点之间连通。
可选的，所述像素电路还包括发光元件、第一发光控制电路和第二发光控制电路；所述刷新帧还包括设置于所述写入后偏置阶段之后的刷新发光阶段；所述保持帧包括保持发光阶段；
所述像素驱动方法还包括：
在刷新发光阶段和保持发光阶段，第一发光控制电路在第一发光控制信号的控制下，控制电源电压端与驱动电路的第一端之间连通，第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与发光元件的第一极之间连通，驱动电路驱动发光元件。
在本公开至少一实施例中，所述像素电路还包括发光元件、第一发光控制电路和第二发光控制电路；所述刷新帧还包括刷新发光阶段；
所述写入后偏置阶段包括多个刷新偏置时间段，所述刷新发光阶段包括多个刷新发光时间段；所述刷新偏置时间段和所述刷新发光时间段交替设置；
所述像素驱动方法包括：
在所述刷新偏置时间段，第一初始化电路在第一控制信号的控制下，将第一初始电压写入第一节点；第二初始化电路在第一扫描信号的控制下，将第二初始电压写入第三节点，以使得驱动电路包括的驱动晶体管处于开态偏置状态；
在所述刷新发光时间段，第一发光控制电路在第一发光控制信号的控制下，控制电源电压端与驱动电路的第一端之间连通，第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与发光元件的第一极之间连通，驱动电路驱动发光元件。
可选的，所述补偿控制电路包括第一补偿控制晶体管和第二补偿控制晶体管，所述像素电路还包括第三初始化电路；所述像素驱动方法还包括：
在刷新发光阶段和保持发光阶段，所述第三初始化电路在发光控制信号的控制下，将第三初始电压写入中间节点。
本公开实施例所述的显示装置包括上述的像素电路。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (26)

  1. 一种像素电路，包括驱动电路、第一初始化电路和第二初始化电路；
    所述驱动电路的控制端与第一节点电连接，所述驱动电路的第一端与第二节点电连接，所述驱动电路的第二端与第三节点电连接，所述驱动电路用于在所述第一节点的电位的控制下，产生由所述第二节点流向所述第三节点的电流；
    所述第一初始化电路分别与第一控制端、第一初始电压线和第一节点电连接，用于在所述第一控制端提供的第一控制信号的控制下，将第一初始电压线提供的第一初始电压写入第一节点；
    所述第二初始化电路分别与第一扫描端、第二初始电压线和所述第三节点电连接，用于在所述第一扫描端提供的第一扫描信号的控制下，将第二初始电压线提供的第二初始电压写入所述第三节点。
  2. 如权利要求1所述的像素电路，其中，所述驱动电路包括的驱动晶体管为p型晶体管，所述第一初始电压的电压值与所述第二初始电压的电压值之间的差值小于所述驱动晶体管的阈值电压；或者，
    所述驱动电路包括的驱动晶体管为n型晶体管，所述第一初始电压的电压值与所述第二初始电压的电压值之间的差值大于所述驱动晶体管的阈值电压。
  3. 如权利要求1所述的像素电路，其中，还包括数据写入电路、补偿控制电路和储能电路；
    所述数据写入电路分别与第二扫描端、数据线和所述第二节点电连接，用于在所述第二扫描端提供的第二扫描信号的控制下，将所述数据线上的数据电压写入所述第二节点；
    所述补偿控制电路分别与第二控制端、所述第一节点和所述第三节点电连接，用于在所述第二控制端提供的第二控制信号的控制下，控制所述第一节点与所述第三节点之间连通或断开；
    所述储能电路的第一端与第一节点电连接，所述储能电路的第二端与第一电压端电连接，所述储能电路用于储存电能。
  4. 如权利要求1所述的像素电路，其中，还包括数据写入电路和储能电路；
    所述数据写入电路分别与第二扫描端、数据线和所述第一节点电连接，用于在所述第二扫描端提供的第二扫描信号的控制下，将所述数据线上的数据电压写入所述第一节点；
    所述储能电路的第一端与第一节点电连接，所述储能电路的第二端与第一电压端电连接，所述储能电路用于储存电能。
  5. 如权利要求1所述的像素电路，其中，还包括第一储能电路、第二储能电路、数据写入电路和补偿控制电路；
    所述第一储能电路的第一端与第一节点电连接，所述第一储能电路的第二端与所述第二储能电路的第一端电连接，所述第二储能电路的第二端与第一电压端电连接；所述第一储能电路和所述第二储能电路用于储存电能；
    所述数据写入电路分别与第二扫描端、数据线和所述第一储能电路的第二端电连接，用于在所述第二扫描端提供的第二扫描信号的控制下，将所述数据线上的数据电压写入所述第一储能电路的第二端；
    所述补偿控制电路分别与第二控制端、所述第一节点和所述第三节点电连接，用于在所述第二控制端提供的第二控制信号的控制下，控制所述第一节点与所述第三节点之间连通或断开。
  6. 如权利要求3或5所述的像素电路，其中，所述补偿控制电路包括第一晶体管，所述第一晶体管的栅极与所述第二控制端电连接，所述第一晶体管的第一极与所述第一节点电连接，所述第一晶体管的第二极与所述第三节点电连接；所述第一晶体管为双栅晶体管。
  7. 如权利要求3或5所述的像素电路，其中，所述补偿控制电路包括第一补偿控制晶体管和第二补偿控制晶体管；所述第一补偿控制晶体管的栅极与所述第二控制端电连接，所述第一补偿控制晶体管的第一极与第一节点电连接，所述第一补偿控制晶体管的第二极与中间节点电连接；所述第二补偿控制晶体管的栅极与所述第二控制端电连接，所述第二补偿控制晶体管的第一极与中间节点电连接，所述第二补偿控制晶体管的第二极与所述第三节点电连接；所述像素电路还包括第三初始化电路；
    所述第三初始化电路分别与发光控制端、第三初始电压线和所述中间节点电连接，用于在所述发光控制端提供的发光控制信号的控制下，将所述第三初始电压线提供的第三初始电压写入所述中间节点。
  8. 如权利要求1至5中任一权利要求所述的像素电路，其中，还包括发光元件、第一发光控制电路和第二发光控制电路；
    所述第一发光控制电路分别与第一发光控制端、电源电压端和所述驱动电路的第一端电连接，用于在所述第一发光控制端提供的第一发光控制信号的控制下，控制所述电源电压端与所述驱动电路的第一端之间连通或断开；
    所述第二发光控制电路分别与第二发光控制端、所述驱动电路的第二端和所述发光元件的第一极电连接，用于在所述第二发光控制端提供的第二发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通或断开；
    所述发光元件的第二极与第二电压端电连接。
  9. 如权利要求8所述的像素电路，其中，还包括第四初始化电路；
    所述第四初始化电路分别与第一扫描端、第四初始电压线和所述发光元件的第一极电连接，用于在所述第一扫描端提供的第一扫描信号的控制下，将所述第四初始电压线提供的第四初始电压写入所述发光元件的第一极。
  10. 如权利要求1至5中任一权利要求所述的像素电路，其中，所述驱动电路包括驱动晶体管，所述第一初始化电路包括第二晶体管，所述第二初始化电路包括第三晶体管；
    所述驱动晶体管的栅极与所述第一节点电连接，所述驱动晶体管的第一极与所述第二节点电连接，所述驱动晶体管的第二极与所述第三节点电连接；
    所述第二晶体管的栅极与所述第一控制端电连接，所述第二晶体管的第一极与所述第一初始电压线电连接，所述第二晶体管的第二极与所述第一节点电连接；
    所述第三晶体管的栅极与第一扫描端电连接，所述第三晶体管的第一极与第二初始电压线电连接，所述第三晶体管的第二极与第三节点电连接。
  11. 如权利要求3所述的像素电路，其中，所述数据写入电路包括第四晶体管；
    所述第四晶体管的栅极与所述第二扫描端电连接，所述第四晶体管的第一极与所述数据线电连接，所述第四晶体管的第二极与所述第二节点电连接；
    所述储能电路包括存储电容；
    所述存储电容的第一端与第一节点电连接，所述存储电容的第二端与电源电压端电连接。
  12. 如权利要求4所述的像素电路，其中，所述数据写入电路包括第四晶体管；
    所述第四晶体管的栅极与所述第二扫描端电连接，所述第四晶体管的第一极与所述数据线电连接，所述第四晶体管的第二极与所述第一节点电连接；
    所述储能电路包括存储电容；
    所述存储电容的第一端与第一节点电连接，所述存储电容的第二端与第一电压端电连接。
  13. 如权利要求5所述的像素电路，其中，所述数据写入电路包括第四晶体管；
    所述第四晶体管的栅极与所述第二扫描端电连接，所述第四晶体管的第一极与所述数据线电连接，所述第四晶体管的第二极与所述第一储能电路的第二端电连接；
    所述第一储能电路包括第一存储电容，所述第二储能电路包括第二存储电容；
    所述第一存储电容的第一端与第一节点电连接，所述第一存储电容的第二端与所述第二存储电容的第一端电连接，所述第二存储电容的第二端与第一电压端电连接。
  14. 如权利要求8所述的像素电路，其中，所述第一发光控制电路包括第五晶体管，所述第二发光控制电路包括第六晶体管；
    所述第五晶体管的栅极与所述第一发光控制端电连接，所述第五晶体管的第一极与所述电源电压端电连接，所述第五晶体管的第二极与所述驱动电路的第一端电连接；
    所述第六晶体管的栅极与所述第二发光控制端电连接，所述第六晶体管的第一极与所述驱动电路的第二端电连接，所述第六晶体管的第二极与所述 发光元件的第一极电连接。
  15. 如权利要求9所述的像素电路，其中，所述第四初始化电路包括第七晶体管；
    所述第七晶体管的栅极与所述第一扫描端电连接，所述第七晶体管的第一极与所述第四初始电压线电连接，所述第七晶体管的第二极与所述发光元件的第一极电连接。
  16. 如权利要求7所述的像素电路，其中，所述第三初始化电路包括第八晶体管；
    所述第八晶体管的栅极与所述发光控制端电连接，所述第八晶体管的第一极与所述第三初始电压线电连接，所述第八晶体管的第二极与所述中间节点电连接。
  17. 一种像素驱动方法，应用于如权利要求1至16中任一权利要求所述的像素电路，显示周期包括保持帧，所述保持帧包括保持偏置阶段；所述像素驱动方法包括：
    在所述保持偏置阶段，第一初始化电路在第一控制信号的控制下，将第一初始电压写入第一节点；第二初始化电路在第一扫描信号的控制下，将第二初始电压写入第三节点，以使得驱动电路包括的驱动晶体管处于开态偏置状态。
  18. 如权利要求17所述的像素驱动方法，其中，所述像素电路还包括第一发光控制电路、第二发光控制电路和发光元件；
    所述保持偏置阶段包括多个保持偏置时间段；所述保持帧还包括多个保持发光时间段；所述保持偏置时间段和所述保持发光时间段交替设置，所述像素驱动方法包括：
    在所述保持偏置时间段，第一初始化电路在第一控制信号的控制下，将第一初始电压写入第一节点；第二初始化电路在第一扫描信号的控制下，将第二初始电压写入第三节点，以使得驱动电路包括的驱动晶体管处于开态偏置状态；
    在所述保持发光时间段，第一发光控制电路在第一发光控制信号的控制下，控制电源电压端与驱动电路的第一端之间连通，第二发光控制电路在所 述第二发光控制信号的控制下，控制所述驱动电路的第二端与发光元件的第一极之间连通，驱动电路驱动发光元件。
  19. 如权利要求17所述的像素驱动方法，其中，所述显示周期还包括设置于所述保持帧之间的刷新帧；所述刷新帧包括设置于数据写入阶段之前的写入前偏置阶段；所述像素驱动方法包括：
    在所述写入前偏置阶段，第一初始化电路在第一控制信号的控制下，将第一初始电压写入第一节点；第二初始化电路在第一扫描信号的控制下，将第二初始电压写入第三节点，以使得驱动电路包括的驱动晶体管处于开态偏置状态。
  20. 如权利要求17至19中任一权利要求所述的像素驱动方法，其中，所述显示周期还包括设置于所述保持帧之间的刷新帧；所述刷新帧还包括设置于数据写入阶段之后的写入后偏置阶段；所述像素驱动方法包括：
    在写入后偏置阶段，第一初始化电路在第一控制信号的控制下，将第一初始电压写入第一节点；第二初始化电路在第一扫描信号的控制下，将第二初始电压写入第三节点，以使得驱动电路包括的驱动晶体管处于开态偏置状态。
  21. 如权利要求20所述的像素驱动方法，其中，所述像素电路包括数据写入电路；所述像素驱动方法还包括：
    在所述数据写入阶段，数据写入电路在第二扫描端提供的第二扫描信号的控制下，控制将数据线上的数据电压写入第二节点。
  22. 如权利要求21所述的像素驱动方法，其中，所述像素电路还包括补偿控制电路；所述刷新帧还包括补偿阶段；所述数据写入阶段包含于所述补偿阶段，所述数据写入阶段设置于所述写入后偏置阶段之前；所述像素驱动方法包括：
    在补偿阶段，补偿控制电路在第二控制端提供的第二控制信号的控制下，控制所述第一节点与所述第三节点之间连通。
  23. 如权利要求20所述的像素驱动方法，其中，所述像素电路还包括发光元件、第一发光控制电路和第二发光控制电路；所述刷新帧还包括设置于所述写入后偏置阶段之后的刷新发光阶段；所述保持帧包括保持发光阶段；
    所述像素驱动方法还包括：
    在刷新发光阶段和保持发光阶段，第一发光控制电路在第一发光控制信号的控制下，控制电源电压端与驱动电路的第一端之间连通，第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与发光元件的第一极之间连通，驱动电路驱动发光元件。
  24. 如权利要求20所述的像素驱动方法，其中，所述像素电路还包括发光元件、第一发光控制电路和第二发光控制电路；所述刷新帧还包括刷新发光阶段；
    所述写入后偏置阶段包括多个刷新偏置时间段，所述刷新发光阶段包括多个刷新发光时间段；所述刷新偏置时间段和所述刷新发光时间段交替设置；
    所述像素驱动方法包括：
    在所述刷新偏置时间段，第一初始化电路在第一控制信号的控制下，将第一初始电压写入第一节点；第二初始化电路在第一扫描信号的控制下，将第二初始电压写入第三节点，以使得驱动电路包括的驱动晶体管处于开态偏置状态；
    在所述刷新发光时间段，第一发光控制电路在第一发光控制信号的控制下，控制电源电压端与驱动电路的第一端之间连通，第二发光控制电路在第二发光控制信号的控制下，控制所述驱动电路的第二端与发光元件的第一极之间连通，驱动电路驱动发光元件。
  25. 如权利要求22所述的像素驱动方法，其中，所述补偿控制电路包括第一补偿控制晶体管和第二补偿控制晶体管，所述像素电路还包括第三初始化电路；所述像素驱动方法还包括：
    在刷新发光阶段和保持发光阶段，所述第三初始化电路在发光控制信号的控制下，将第三初始电压写入中间节点。
  26. 一种显示装置，包括如权利要求1至16任一权利要求所述的像素电路。
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CN113593475A (zh) * 2021-07-30 2021-11-02 京东方科技集团股份有限公司 像素电路、驱动方法和显示装置
CN114627807A (zh) * 2021-07-30 2022-06-14 京东方科技集团股份有限公司 像素电路、驱动方法和显示装置
CN114974130A (zh) * 2022-05-24 2022-08-30 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、阵列基板及显示装置
CN115273737A (zh) * 2022-08-25 2022-11-01 厦门天马显示科技有限公司 像素电路及其驱动方法、显示面板和显示装置
CN115482780A (zh) * 2022-09-28 2022-12-16 京东方科技集团股份有限公司 像素电路、像素驱动方法和显示装置
CN115547255A (zh) * 2022-10-25 2022-12-30 京东方科技集团股份有限公司 像素驱动电路、显示装置及显示画面的亮点修复方法

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