WO2024148797A1 - 半导体器件及其制备方法 - Google Patents

半导体器件及其制备方法 Download PDF

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Publication number
WO2024148797A1
WO2024148797A1 PCT/CN2023/111046 CN2023111046W WO2024148797A1 WO 2024148797 A1 WO2024148797 A1 WO 2024148797A1 CN 2023111046 W CN2023111046 W CN 2023111046W WO 2024148797 A1 WO2024148797 A1 WO 2024148797A1
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Prior art keywords
capacitor
region
layer
supporting
supporting layer
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PCT/CN2023/111046
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English (en)
French (fr)
Inventor
刘纪涛
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B12/00—Superconductive or hyperconductive conductors, cables, or transmission lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance

Definitions

  • the present disclosure relates to the technical field of integrated circuits, and in particular to a semiconductor device and a method for preparing the same.
  • the double-sided capacitor process can increase the facing area between the two electrodes of the capacitor, thereby increasing the capacitance value.
  • a support layer and a sacrificial layer can be formed first, and then a capacitor hole penetrating the support layer and the sacrificial layer is formed, and a capacitor-related structure (such as a first capacitor electrode) is formed in the capacitor hole.
  • the sacrificial layer can be removed by wet removal, and the retained support layer can support the structure formed in the capacitor hole.
  • semiconductor devices are usually formed only in the array area. Therefore, during the formation of semiconductor devices, the support layer located in the peripheral area is usually removed. At this time, during the wet removal of the sacrificial layer, the capacitor-related structure formed in the capacitor hole at the edge of the array area is prone to collapse due to problems such as wet etching rate, stress, and centrifugal force, thereby affecting the product yield and even causing the wafer to be scrapped.
  • a semiconductor device and a method for manufacturing the same are provided.
  • a method for preparing a semiconductor device comprising:
  • the substrate having an array region and a peripheral region, the array region including a first region and a second region, the first region being located between the peripheral region and the second region;
  • a capacitor is fabricated in the array region so that the bottom of the capacitor is formed in the first supporting layer.
  • the step of manufacturing a capacitor in the array region so that the bottom of the capacitor is formed in the first supporting layer includes:
  • the sacrificial material layer and the second supporting material layer in the peripheral area are removed to form a second supporting layer in the array area, and a second capacitor substructure is formed on the surface of the first capacitor substructure.
  • forming a first supporting layer on the substrate comprises:
  • the first supporting material layer located in the second region is thinned to form the first supporting layer.
  • forming a first supporting layer on the substrate includes:
  • a second supporting sublayer is formed on the first supporting sublayer located in the first region, and the second supporting sublayer and the first supporting sublayer constitute the first supporting layer.
  • a difference between a thickness of the first supporting layer in the first region and a thickness of the first supporting layer in the second region is 20 nm to 100 nm.
  • etching the second supporting material layer, the sacrificial material layer, and the first supporting layer to form array region capacitor holes in the first region and the second region includes:
  • a dummy capacitor hole is formed in the first region, and a storage capacitor hole is formed in the second region, wherein the dummy capacitor hole is used to form a dummy capacitor, and the storage capacitor hole is used to form a storage capacitor.
  • the depth of the dummy capacitor hole is less than the depth of the storage capacitor hole.
  • the peripheral region includes a third region and a fourth region, wherein the third region is located between the fourth region and the array region.
  • the etching of the second supporting material layer, the sacrificial material layer and the first supporting layer forms array region capacitor holes in the first region and the second region, and also forms peripheral region capacitor holes in the third region.
  • the thickness of the first supporting layer in the third region is greater than that in the second region, the array region capacitor hole includes a storage capacitor hole, and the peripheral region capacitor hole depth is less than the storage capacitor hole depth.
  • the first capacitor substructure includes a first capacitor electrode
  • the forming of a second capacitor substructure on the surface of the first capacitor substructure includes:
  • a second capacitor electrode is formed on the surface of the capacitor dielectric layer.
  • a semiconductor device including:
  • a substrate wherein the substrate has an array region and a peripheral region, the array region includes a first region and a second region, and the first region is located between the peripheral region and the second region;
  • a first supporting layer located on the substrate, wherein the thickness of the first supporting layer in the first region is greater than the thickness of the first supporting layer in the second region;
  • the capacitor is located in the array area, and the bottom of the capacitor is arranged in the first supporting layer.
  • the semiconductor device further comprises a second supporting layer, wherein the second supporting layer is located in the array region and is spaced apart from the first supporting layer;
  • the capacitor comprises a first capacitor substructure and a second capacitor substructure, wherein the first capacitor substructure extends from the second supporting layer into the first supporting layer, and the second capacitor substructure is located on a surface of the first capacitor substructure.
  • a difference between a thickness of the first supporting layer in the first region and a thickness of the first supporting layer in the second region is 20 nm to 100 nm.
  • the capacitor located in the first region is a dummy capacitor, and the capacitor located in the second region is a storage capacitor.
  • a first capacitor substructure depth of the dummy capacitor is less than a first capacitor substructure depth of the storage capacitor.
  • the peripheral region includes a third region and a fourth region, wherein the third region is located between the fourth region and the array region.
  • the first supporting layer of the third zone is provided with a peripheral supporting layer hole.
  • the peripheral support layer holes are blind holes.
  • the first capacitor substructure includes a first capacitor electrode
  • the second capacitor substructure includes a capacitor dielectric layer and a second capacitor electrode
  • the capacitor dielectric layer is located on the surface of the first capacitor electrode
  • the second capacitor electrode is located on the surface of the capacitor dielectric layer
  • FIG1 is a flow chart of a method for preparing a semiconductor device provided in one embodiment
  • FIGS. 2 to 11 are schematic cross-sectional views of structures obtained during the preparation of a semiconductor device provided in one embodiment
  • FIG. 12 is a schematic diagram of a cross-sectional structure of a semiconductor device formed in an embodiment.
  • the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.
  • spatially relative terms such as “under,” “beneath,” “below,” “under,” “above,” “above,” and the like, may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as “under other elements” or “under it” or “under it” will be oriented as being “above” the other elements or features. Thus, the exemplary terms “under” and “under” may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
  • a method for preparing a semiconductor device comprising the following steps:
  • Step S10 providing a substrate 100, the substrate 100 having an array region and a peripheral region, the array region including a first region and a second region, the first region being located between the peripheral region and the second region, please refer to FIG. 2;
  • Step S20 forming a first supporting layer 200 on the substrate 100, wherein the thickness of the first supporting layer 200 in the first region is greater than the thickness in the second region, see FIG. 4;
  • Step S30 manufacturing capacitors 500 in the array region, so that the bottom of the capacitors 500 is formed in the first supporting layer 200 , please refer to FIG. 11 .
  • the base 100 may include a semiconductor substrate.
  • the semiconductor substrate may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III/V semiconductor substrates or II/VI semiconductor substrates.
  • the semiconductor substrate may also include a substrate such as Si/SiGe, Si/SiC, silicon on insulator (SOI), or silicon germanium on insulator.
  • the substrate 100 may also include a transistor structure, a capacitor contact structure 110, and a first dielectric layer 120.
  • the transistor structure and the capacitor contact structure 110 may be formed in the array region.
  • the transistor structure may be formed based on a semiconductor substrate.
  • the capacitor contact structure 110 may be formed in the first dielectric layer 120, and may connect the transistor structure to the capacitor 500.
  • the substrate 100 has an array region and a peripheral region.
  • the array region is used to form a memory array.
  • the peripheral region is used to form a logic circuit.
  • the first region of the array region is located at the edge of the array region, which is closer to the peripheral region than the second region.
  • a first supporting layer 200 may be formed on the surface of the capacitor contact structure 110 and the first dielectric layer 120.
  • the material of the first supporting layer 200 may include but is not limited to silicon nitride or silicon oxynitride.
  • the first support layer 200 has different thicknesses in different areas of the array region, and its thickness in the first area located at the edge of the array region and close to the peripheral area is greater than its thickness in the second area of the array region.
  • the first support layer 200 can be a single-layer structure or a multi-layer structure, which is not limited here.
  • a capacitor 500 is fabricated in the array region.
  • the capacitor 500 can be used as a storage unit in the array region.
  • the bottom of the capacitor 500 is formed in the first supporting layer 200. Meanwhile, the capacitor 500 also includes a portion located above the first supporting layer 200.
  • including S30 may include:
  • Step S310 forming a sacrificial material layer 301 and a second supporting material layer 401 on the first supporting layer 200, please refer to FIG. 4;
  • Step S320 etching the second support material layer 401, the sacrificial material layer 301 and the first support layer 200 to form array region capacitor holes 10 in the first region and the second region, please refer to FIG. 5;
  • Step S330 forming a first capacitor substructure 510 in the array region capacitor hole 10, please refer to FIG. 6;
  • step S340 the sacrificial material layer 301 and the second supporting material layer 401 in the peripheral region are removed to form a second supporting layer 400 in the array region, and a second capacitor substructure 520 is formed on the surface of the first capacitor substructure 510 , see FIG. 11 .
  • the material of the sacrificial material layer 301 may include but is not limited to silicon oxide.
  • the material of the second supporting material layer 401 may include but is not limited to silicon nitride or silicon oxynitride, which may be the same as or different from the material of the first supporting layer 200.
  • a plurality of sets of sacrificial material layers 301 and second supporting material layers 401 may be formed on the first supporting layer 200.
  • the sacrificial material layers 301 and the second supporting material layers 401 may be alternately formed on the first supporting layer 200.
  • only one set of sacrificial material layers 301 and the second supporting material layers 401 may be formed on the first supporting layer 200.
  • a layer of sacrificial material layer 301 may be formed on the surface of the first supporting layer 200, and then a layer of second supporting material layer 401 may be formed on the surface of the sacrificial material layer 301.
  • the sacrificial material layer 301 and the second supporting material layer 401 may be formed by a deposition process.
  • the deposition process may include but is not limited to a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a high density plasma deposition (HDP) process, a plasma enhanced chemical vapor deposition (PECVD) process, a spin-on dielectric (SOD) process, or one or more of the above processes.
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • HDP high density plasma deposition
  • PECVD plasma enhanced chemical vapor deposition
  • SOD spin-on dielectric
  • a mask may be first formed on the surface of the second support material layer 401 located at the top layer.
  • Mask material layer 801 may be a single-layer structure or a multi-layer stacked structure.
  • a first photoresist may be coated on the mask material layer 801, and a series of steps such as exposure and development may be performed to form a first patterned photoresist layer 30.
  • the openings of the first patterned photoresist layer 30 define the position and shape of the capacitor holes 10 in the array region.
  • the first photoresist can be a positive photoresist or a negative photoresist.
  • the first photoresist is a negative photoresist, after a series of steps such as exposure and development, the portion of the first photoresist corresponding to the light-shielding area of the first exposure mask 50 is removed, while the portion corresponding to the light-transmitting area of the first exposure mask 50 is retained, so that the opening of the first patterned photoresist 30 layer is opposite to the light-shielding area of the first exposure mask 50.
  • the first photoresist is a positive photoresist
  • the portion of the first photoresist corresponding to the light-shielding area of the first exposure mask 50 is retained, while the portion corresponding to the light-transmitting area of the first exposure mask 50 is removed, so that the opening of the first patterned photoresist 30 layer is opposite to the light-transmitting area of the first exposure mask 50.
  • the mask material layer 801 can be etched based on the first patterned photoresist 30 to form a patterned mask layer. Then the first patterned photoresist 30 is removed. Then based on the patterned mask layer, the second support material layer 401, the sacrificial material layer 301 and the first support layer 200 are etched from top to bottom in sequence, thereby forming the array area capacitor hole 10 in the first area and the second area. At this time, the array area capacitor hole 10 extends from the surface of the second support material layer 401 located at the top layer into the first support layer 200, so that the first support layer 200 can support the first capacitor substructure 510 subsequently formed in the array area capacitor hole 10. Then remove the patterned mask layer.
  • the first capacitor substructure 510 is a partial structure of the capacitor 500.
  • the first capacitor substructure 510 is formed in the array region capacitor hole 10, so the first capacitor substructure also extends from the surface of the second supporting material layer 401 located at the top layer into the first supporting layer 200.
  • the first capacitor substructure 510 may include a first capacitor electrode.
  • the material of the first capacitor electrode may include but is not limited to titanium nitride.
  • the first capacitor electrode can fill the array region capacitor hole 10.
  • a lower electrode material layer can be first formed on the second support material layer 401 located on the top layer and in the array region capacitor hole 10, and then the lower electrode material layer located on the surface of the second support material layer 401 is removed by chemical mechanical polishing (CMP), and the electrode material layer remaining in the array region capacitor hole 10 forms the first capacitor electrode.
  • CMP chemical mechanical polishing
  • the first capacitor electrode may also form the sidewall and the bottom of the array region capacitor hole 10 .
  • the first capacitor substructure 510 may also include a plurality of (e.g., two) capacitor electrodes formed on the sidewalls and bottom of the array region capacitor hole 10 and a capacitor dielectric layer between the capacitor electrodes. At this time, after removing the sacrificial material layer 301 and part of the second support material layer 401 in step S340, other capacitor electrodes and capacitor dielectric layers may be formed on the basis of the first capacitor substructure 510.
  • the specific form of the first capacitor substructure 510 is not limited here.
  • the second support material layer 401 may be firstly dry-etched to remove the portion located in the peripheral region, and an opening may be formed in the second support material layer 401 in the array region, thereby exposing the sacrificial material layer 301 located below the second support material layer 401.
  • the sacrificial material layer 301 below the second support material layer 401 may then be removed by wet etching.
  • each group of sacrificial material layers 301 and second supporting material layers 401 can be processed in the above manner, so that all sacrificial material layers 301 are removed and the second supporting material layers 401 located in the peripheral area are removed to form a second supporting layer 400 located in the array area.
  • the second supporting material layer 401 located in the upper layer may be firstly dry-etched (see FIG. 7). Thereafter, the sacrificial material layer 301 located in the upper layer may be removed by wet etching (see FIG. 8). Then, the second supporting material layer 401 located in the lower layer may be dry-etched (see FIG. 9). Thereafter, the sacrificial material layer 301 located in the lower layer may be removed by wet etching (see FIG. 10).
  • a The first capacitor substructure 510 in the zone capacitor hole 10 is supported by the first supporting layer 200 and the second supporting layer 400 .
  • the second capacitor substructure 520 may be formed on the basis of the first capacitor substructure 510 , thereby completing the manufacture of the capacitor 500 . That is, the capacitor 500 includes the first capacitor substructure 510 and the second capacitor substructure 520 .
  • forming the second capacitor substructure 520 on the surface of the first capacitor substructure 510 may include first forming a capacitor dielectric layer on the surface of the first capacitor electrode; and then forming the second capacitor electrode on the surface of the capacitor dielectric layer.
  • the second capacitor substructure 520 includes a capacitor dielectric layer and a second capacitor electrode.
  • the material of the capacitor dielectric layer may include but is not limited to a high dielectric constant material, such as aluminum oxide.
  • the second capacitor electrode may include an electrode layer and a filling layer, the electrode layer may be located on the surface of the capacitor dielectric layer, and the filling layer may fill the array region capacitor hole 10.
  • the material of the electrode layer may include but is not limited to titanium nitride, and the material of the filling layer may include but is not limited to polysilicon or silicon germanium.
  • a first support layer 200 with different thicknesses in different regions (first region and second region) of the array region is formed on the substrate 100.
  • the thickness of the first support layer 200 in the first region close to the peripheral region is greater than its thickness in the second region far from the peripheral region, so that the supporting effect of the first support layer 200 in the first region close to the peripheral region can be made more solid.
  • the relevant structure of the capacitor can be effectively prevented from collapsing.
  • the first capacitor substructure 510 formed in the array region capacitor hole 10 at the edge of the array region can be effectively prevented from collapsing, so that the product yield can be effectively improved.
  • the thickness of the second region far from the peripheral region is less than the thickness of the first region, so that the side wall of the first capacitor substructure 510 formed in the array region capacitor hole 10 located in the second region can be exposed more.
  • the area directly opposite to the capacitor can be increased, thereby effectively ensuring that the capacitance of the capacitor 500 in the second region will not be affected by the thickness of the first support layer 200.
  • step S20 includes:
  • Step S211 forming a first supporting material layer 201 on the substrate 100, please refer to FIG. 2;
  • Step S212 thinning the first supporting material layer 201 located in the second area to form a first supporting layer 200 , please refer to FIG. 4 .
  • a first support material layer 201 with a relatively large thickness may be formed on the substrate 100 in the array region and the peripheral region by deposition or the like.
  • a second photoresist may be first formed on the surface of the first support material layer 201.
  • the second photoresist is then exposed through a second exposure mask.
  • the second photoresist is subjected to development and other treatments to form a second patterned photoresist 40.
  • the opening of the second patterned photoresist 40 may expose the second area of the array area.
  • the first support material layer 201 in the second region may be thinned by etching based on the second patterned photoresist 40, and the first support material layer 201 retained after etching may form the first support layer 200.
  • the second patterned photoresist 40 may then be removed.
  • the thickness of the first support layer 200 located in the first area and the peripheral area is greater than the thickness of the first support layer 200 in the second area, so that the first support layer 200 located in the peripheral area can assist the first support layer 200 located in the first area, and more effectively prevent the collapse of the first capacitor substructure 510 formed in the array area capacitor hole 10 located at the edge of the array area.
  • the first supporting layer 200 is obtained by thinning the first supporting material layer 201 .
  • the first supporting material layer 201 can be formed by a single deposition process, and thus a first supporting layer 200 with uniform film quality can be formed.
  • step S20 includes:
  • Step S222 forming a second supporting sublayer on the first supporting sublayer located in the first area, the second supporting sublayer and the first supporting sublayer forming the first supporting layer 200 .
  • a first supporting sublayer with a small thickness may be formed on the substrate 100 in the array region and the peripheral region by deposition or the like.
  • the second area of the array area may be covered by a mask, and then the first area of the array area may be covered by a mask. and the peripheral area forms a second supporting sublayer.
  • the material of the second supporting sublayer may be the same as or different from the material of the first supporting sublayer, which is not limited here.
  • the first supporting layer 200 can be obtained through two deposition processes, so that one photomask process can be omitted, thereby improving process efficiency.
  • the method of forming the first support layer 200 in step S20 is not limited to the above two methods.
  • a second support material sublayer of a material different from the first support sublayer may be formed on the first support sublayer.
  • the second support material sublayer in the second area is removed by photolithography, etching, etc., and the retained second support material sublayer forms a second support sublayer.
  • the second support sublayer and the first support sublayer constitute the first support layer 200. At this time, the thickness of the first support layer 200 in the second area can be effectively controlled.
  • the difference between the thickness of the first supporting layer 200 in the first region and the thickness of the first supporting layer 200 in the second region is 20 nm to 100 nm.
  • the difference between the thickness of the first supporting layer 200 in the first area and the thickness of the first supporting layer 200 in the second area is not too large, so as not to affect the uniformity of the thickness of the sacrificial material layer 301 formed on the surface of the first supporting layer 200.
  • the step of planarizing the sacrificial material layer 301 can be omitted.
  • the difference between the thickness of the first supporting layer 200 in the first region and the thickness in the second region may also be other values, which is not limited here.
  • step S320 includes:
  • Step S321 forming a dummy capacitor hole 11 in the first area and a storage capacitor hole 12 in the second area, wherein the dummy capacitor hole 11 is used to form a dummy capacitor and the storage capacitor hole 12 is used to form a storage capacitor.
  • the storage capacitor is a capacitor actually used for storage.
  • the dummy capacitor is a capacitor not actually used for storage.
  • the array region capacitor hole 10 includes a dummy capacitor hole 11 located in the first region and a storage capacitor hole 12 located in the second region.
  • the capacitor 500 includes a dummy capacitor and a storage capacitor, wherein the first capacitor substructure 510 of the dummy capacitor is located in the dummy capacitor hole 11, and the first capacitor substructure 510 of the storage capacitor is located in the storage capacitor hole 12.
  • a mask material layer 801 can be formed on the surface of the second supporting material layer 401 located at the top layer. Afterwards, a first patterned photoresist 30 layer can be formed on the mask material layer 801, and the opening of the first patterned photoresist 30 layer defines the position and shape of the array area capacitor hole 10 (dummy capacitor hole 11 and storage capacitor hole 12). Then, based on the first patterned photoresist 30, the mask material layer 801 is etched to form a patterned mask layer. Afterwards, the array area capacitor hole 10 (dummy capacitor hole 11 and storage capacitor hole 12) is formed based on the patterned mask layer.
  • the peripheral region does not need to form the capacitor 500. Therefore, the first patterned photoresist 30 layer has different opening densities in the array region and the peripheral region.
  • the openings of the photoresist near the peripheral region are in different environments from the openings in other regions, which may cause the openings near the peripheral region to deform, and then cause the patterned mask layer formed based on the first patterned photoresist 30 to be etched and deformed when near the peripheral region, and then cause the array region capacitor hole 10 formed near the peripheral region to deform.
  • a dummy capacitor hole 11 is set in the first area close to the peripheral area, so as to provide a transition condition for the storage capacitor hole 12 in the second area, so that the deformation of the array area capacitor hole 10 occurs in the dummy capacitor hole 11, so as to ensure that the storage capacitor hole 12 has a precise graphic shape.
  • the dummy capacitor formed based on the dummy capacitor hole 11 is not actually used for storage, so it will not affect the storage performance of the array area.
  • the area where the dummy capacitor hole 11 is set is used as the area of the first support layer 200 with a higher thickness (first area), and the area where the storage capacitor hole 12 is set is used as the area of the first support layer 200 with a lower thickness (second area), so that the thicker part of the first support layer 200 does not affect the capacitance of the storage capacitor.
  • the configuration of the first area and the second area is not limited to this.
  • a portion of the dummy capacitor holes 11 may be formed in the first area, and another portion of the dummy capacitor holes 11 and the storage capacitor holes 12 may be formed in the second area.
  • the dummy capacitor holes 11 and a small portion of the storage capacitor holes 12 may be formed in the first area, and the remaining portion of the storage capacitor holes 12 may be formed in the second area.
  • the depth of the dummy capacitor hole 11 is less than the depth of the storage capacitor hole 12.
  • the depth of the first capacitor substructure 510 of the dummy capacitor is less than the depth of the first capacitor substructure 510 of the storage capacitor.
  • the second support material layer 401, the sacrificial material layer 301 and the first support layer 200 are etched.
  • the thickness of the first support layer 200 in the first area is greater than its thickness in the second area. Therefore, after etching to the upper surface of the first support layer 200 located in the first area, the first support layer 200 is etched in the first area, and the remaining sacrificial material layer 301 needs to be etched in the second area.
  • the material of the first support layer 200 is different from that of the sacrificial material layer 301, and the etching rate of the sacrificial material layer 301 (such as a silicon oxide layer) is generally greater than the etching rate of the first support layer 200 (such as a silicon nitride layer).
  • the depth of the dummy capacitor hole 11 is set to be less than the depth of the storage capacitor hole 12, and the etching can be stopped after the first support layer 200 located in the second area is etched through, thereby effectively improving the etching efficiency.
  • the depth of the dummy capacitor hole 11 may be equal to the depth of the storage capacitor hole 12, and this is not limited here.
  • the peripheral region includes a third region and a fourth region (not shown), and the third region is located between the fourth region and the array region.
  • step S320 forms array region capacitor holes 10 in the first region and the second region and also forms peripheral region capacitor holes 20 in the third region.
  • peripheral region capacitor holes 20 may be formed in the third region.
  • the array area can be provided with a dummy capacitor hole 11 in the first area close to the peripheral area, so that the peripheral area capacitor hole 20 and the dummy capacitor hole 11 together provide a transition condition for the storage capacitor hole 12.
  • the array area can be provided with or no longer provided with a dummy capacitor hole 11 in the first area close to the peripheral area, and the storage capacitor hole 12 can be directly formed, thereby increasing the area ratio of the storage capacitor hole 12.
  • step S330 while forming the first capacitor substructure 510 in the array area capacitor hole 10, the first capacitor substructure 510 can also be formed in the peripheral area capacitor hole 20 at the same time.
  • step S340 since the sacrificial material layer 301 and the second supporting material layer 401 located in the peripheral area are removed, the upper part of the first capacitor substructure 510 located in the peripheral area will be removed due to lack of support, and only the part located in the first supporting layer 200 of the peripheral area capacitor hole 20 is left, and this part is recorded as forming the peripheral supporting layer hole 21 (see FIG. 11).
  • the second capacitor substructure 520 film layer can be formed on the first capacitor substructure 510 retained in the first supporting layer 200 in the peripheral area. Afterwards, the first capacitor substructure 510 in the first supporting layer 200 in the peripheral area and the second capacitor substructure 520 film layer thereon can be removed. Afterwards, a second dielectric layer 600 covering the peripheral area and the array area can be formed (see FIG. 11). Then, a conductive interconnect structure 700 connected to the peripheral conductive structure 130 may be formed in the peripheral region (see FIG. 12 ).
  • the peripheral area capacitor hole 20 can provide transition conditions for the storage capacitor hole 12 in the second area, so that the capacitor hole deformation occurs in the peripheral area capacitor hole 20, thereby ensuring that the storage capacitor hole 12 has a precise graphic shape.
  • the thickness of the first support layer 200 in the third region is greater than its thickness in the second region, and the array region capacitor hole 10 includes a storage capacitor hole 12.
  • the depth of the peripheral region capacitor hole 20 is less than the depth of the storage capacitor hole 12.
  • the first support layer 200 is provided between the peripheral region capacitor hole 20 and the substrate 100, so that after step S340, the peripheral support layer hole 21 remaining in the first support layer is a blind hole.
  • the thickness of the first supporting layer 200 in the third region may be the same as or different from the thickness in the first region, which is not limited here.
  • the thickness of the first support layer 200 in the third area is greater than that in the second area, so that the first support layer 200 located in the third area can assist the first support layer 200 located in the first area, and more effectively prevent the collapse of the first capacitor substructure 510 formed in the array area capacitor hole 10 located at the edge of the array area.
  • the substrate 100 in the third region may be provided with other peripheral conductive structures 130 at a position opposite to the peripheral region capacitor hole 20, when the depth of the dummy capacitor hole 11 is set to be smaller than the depth of the storage capacitor hole 12, the third region can be effectively etched.
  • the peripheral conductive structure 130 is etched and damaged.
  • the depth of the peripheral region capacitor hole 20 is set to be smaller than the depth of the storage capacitor hole 12, and etching can be stopped after the first support layer 200 located in the second region is etched through, thereby effectively improving the etching efficiency.
  • a semiconductor device is further provided.
  • the semiconductor device includes a substrate 100 , a first supporting layer 200 , a second supporting layer 400 , and a capacitor 500 .
  • the base 100 may include a semiconductor substrate.
  • the semiconductor substrate may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III/V semiconductor substrates or II/VI semiconductor substrates.
  • the semiconductor substrate may also include a substrate such as Si/SiGe, Si/SiC, silicon on insulator (SOI), or silicon germanium on insulator.
  • the substrate 100 may also include a transistor structure, a capacitor contact structure 110, and a first dielectric layer 120.
  • the transistor structure and the capacitor contact structure 110 may be formed in the array region.
  • the transistor structure may be formed based on a semiconductor substrate.
  • the capacitor contact structure 110 may be formed in the first dielectric layer 120, and may connect the transistor structure to the capacitor 500.
  • the substrate 100 has an array region and a peripheral region.
  • the array region is used to form a memory array.
  • the peripheral region is used to form a logic circuit.
  • the substrate 100 has an array region and a peripheral region, the array region includes a first region and a second region, and the first region is located between the peripheral region and the second region.
  • the first region of the array region is located at the edge of the array region, which is closer to the peripheral region than the second region.
  • the first supporting layer 200 may be formed on the surface of the capacitor contact structure 110 and the first dielectric layer 120.
  • the material of the first supporting layer 200 may include but is not limited to silicon nitride or silicon oxynitride.
  • the first support layer 200 has different thicknesses in different areas of the array region, and its thickness in the first area located at the edge of the array region and close to the peripheral area is greater than its thickness in the second area of the array region.
  • the first support layer 200 can be a single-layer structure or a multi-layer structure, which is not limited here.
  • the capacitor 500 is located in the array region.
  • the capacitor 500 can be used as a storage unit in the array region.
  • the bottom of the capacitor 500 is formed in the first supporting layer 200. Meanwhile, the capacitor 500 also includes a portion located above the first supporting layer 200.
  • the semiconductor device further includes a second supporting layer 400 .
  • the capacitor 500 includes a first capacitor substructure 510 and a second capacitor substructure 520 .
  • the second supporting layer 400 is located in the array region and is spaced apart from the first supporting layer 200.
  • a plurality of second supporting layers 400 may be formed on the first supporting layer 200.
  • the second supporting layers 400 may be spaced apart from each other, and the second supporting layers 400 are spaced apart between the first supporting layers 200.
  • the material of the second supporting layer 400 may include, but is not limited to, silicon nitride or silicon oxynitride, which may be the same as or different from the material of the first supporting layer 200 .
  • the first capacitor substructure 510 extends from the second supporting layer 400 into the first supporting layer 200 .
  • the first capacitor substructure 510 may include a first capacitor electrode.
  • the material of the first capacitor electrode may include but is not limited to titanium nitride.
  • the first capacitor electrode may fill the array region capacitor hole 10.
  • the first capacitor electrode may also form the sidewall and bottom of the array region capacitor hole 10.
  • the first capacitor substructure 510 may also include a plurality of (e.g., two) capacitor electrodes formed on the sidewalls and bottom of the array region capacitor hole 10 and a capacitor dielectric layer between the capacitor electrodes.
  • the capacitor 500 includes the first capacitor substructure 510 located in the array region capacitor hole 10, and may also include other capacitor electrodes and capacitor dielectric layers.
  • the specific form of the first capacitor substructure 510 is not limited here.
  • the thickness of the first supporting layer 200 in the first region close to the peripheral region is greater than that in the first region far from the peripheral region.
  • the thickness of the second area can make the supporting effect of the first supporting layer 200 in the first area close to the peripheral area more solid.
  • the capacitor-related structure located at the edge of the array area can be effectively prevented from collapsing.
  • the first capacitor substructure 510 located at the edge of the array area can be effectively prevented from collapsing, thereby effectively improving the product yield.
  • the thickness of the second area away from the peripheral area is less than the thickness of the first area, so that the side wall of the first capacitor substructure 510 formed in the array area capacitor hole 10 located in the second area can be exposed more. At this time, the area facing the capacitor can be increased, thereby effectively ensuring that the capacitance of the capacitor 500 in the second area will not be affected by the thickness of the first supporting layer 200.
  • the difference between the thickness of the first supporting layer 200 in the first region and the thickness of the first supporting layer 200 in the second region is 20 nm to 100 nm.
  • the capacitor 500 in the dummy capacitor hole 11 located in the first region is a dummy capacitor.
  • the capacitor 500 in the second region is a storage capacitor.
  • the first capacitor substructure 510 of the dummy capacitor is located in the dummy capacitor hole 11, and the first capacitor substructure 510 of the storage capacitor is located in the storage capacitor hole 12.
  • the depth of the first capacitor substructure 510 of the dummy capacitor is less than the depth of the first capacitor substructure 510 of the storage capacitor.
  • the peripheral region includes a third region and a fourth region, and the third region is located between the fourth region and the array region.
  • a peripheral supporting layer hole 21 is disposed in the first supporting layer 200 of the third region.
  • the peripheral support layer holes 21 are blind holes.
  • the first capacitor substructure 510 includes a first capacitor electrode
  • the second capacitor substructure 520 includes a capacitor dielectric layer and a second capacitor electrode.
  • the first capacitor electrode is located in the array region capacitor hole 10.
  • the capacitor dielectric layer is located on the surface of the first capacitor electrode.
  • the second capacitor electrode is located on the surface of the capacitor dielectric layer.

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  • Semiconductor Integrated Circuits (AREA)

Abstract

本公开涉及一种半导体器件及其制备方法。半导体器件的制备方法包括：提供基底，基底具有阵列区以及外围区，阵列区包括第一区与第二区，第一区位于外围区与第二区之间；于基底上形成第一支撑层，第一支撑层在第一区的厚度大于其在第二区的厚度；于阵列区制作电容器，使电容器底部形成于第一支撑层内。

Description

半导体器件及其制备方法
相关申请的交叉引用
本公开要求于2023年01月09日提交中国专利局、申请号为2023100363339、发明名称为“半导体器件及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及集成电路技术领域，特别是涉及一种半导体器件及其制备方法。
背景技术
在半导体器件的制备过程中，通过双面电容工艺可以增加电容的两个电极之间的正对面积，进而可以增加电容值。在双面电容工艺中，可以首先形成支撑层以及牺牲层，然后形成贯穿支撑层与牺牲层的电容孔，且在电容孔内形成电容相关结构(如第一电容电极)。之后，可以通过湿法去除方式，将牺牲层去除，而保留的支撑层可以对电容孔内形成的结构进行支撑。
同时，在存储器件中，半导体器件通常只形成在阵列区。因此，在半导体器件形成过程中，通常会将位于外围区的支撑层去除。此时，在湿法去除牺牲层的过程中，位于阵列区边缘的电容孔内形成的电容器相关结构由于湿法刻蚀速率、应力以及离心力等问题容易倒塌，从而影响产品良率甚至导致晶圆报废。
发明内容
根据本公开的各种实施例，提供一种半导体器件及其制备方法。
根据本公开的各种实施例，提供一种半导体器件的制备方法，包括：
提供基底，所述基底具有阵列区以及外围区，所述阵列区包括第一区与第二区，所述第一区位于所述外围区与所述第二区之间；
于所述基底上形成第一支撑层，所述第一支撑层在所述第一区的厚度大于其在所述第二区的厚度；
于所述阵列区制作电容器，使所述电容器底部形成于所述第一支撑层内。
在一些实施例中，所述于所述阵列区制作电容器，使所述电容器底部形成于所述第一支撑层内，包括：
于所述第一支撑层上形成牺牲材料层与第二支撑材料层；
刻蚀所述第二支撑材料层、所述牺牲材料层以及所述第一支撑层，于所述第一区以及所述第二区形成阵列区电容孔；
于所述阵列区电容孔内形成第一电容子结构；
去除所述牺牲材料层以及位于所述外围区第二支撑材料层，以形成位于所述阵列区的第二支撑层，且于所述第一电容子结构表面形成第二电容子结构。
在一些实施例中，所述于所述基底上形成第一支撑层包括：
于所述基底上形成第一支撑材料层；
将位于所述第二区的所述第一支撑材料层减薄，以形成所述第一支撑层。
在一些实施例中，所述于所述基底上形成第一支撑层，包括：
于所述基底上形成第一支撑子层；
于位于所述第一区的所述第一支撑子层上形成第二支撑子层，所述第二支撑子层与所述第一支撑子层构成所述第一支撑层。
在一些实施例中，所述第一支撑层在所述第一区的厚度与其在所述第二区的厚度之差为20nm至100nm。
在一些实施例中，所述刻蚀所述第二支撑材料层、所述牺牲材料层以及所述第一支撑层，于所述第一区以及所述第二区形成阵列区电容孔，包括：
于所述第一区形成虚设电容孔，且于所述第二区形成存储电容孔，所述虚设电容孔用于形成虚设电容，所述存储电容孔用于形成存储电容。
在一些实施例中，所述虚设电容孔深度小于所述存储电容孔深度。
在一些实施例中，
所述外围区包括第三区以及第四区，所述第三区位于所述第四区与所述阵列区之间，
所述刻蚀所述第二支撑材料层、所述牺牲材料层以及所述第一支撑层，于所述第一区以及所述第二区形成阵列区电容孔的同时，还于所述第三区形成外围区电容孔。
在一些实施例中，第一支撑层在所述第三区的厚度大于其在所述第二区的厚度，所述阵列区电容孔包括存储电容孔，所述外围区电容孔深度小于所述存储电容孔深度。
在一些实施例中，所述第一电容子结构包括第一电容电极，
所述于所述第一电容子结构表面形成第二电容子结构，包括：
于所述第一电容电极表面形成电容介质层；
于所述电容介质层表面形成第二电容电极。
根据本公开的各种实施例，还提供一种半导体器件，包括：
基底，所述基底具有阵列区以及外围区，所述阵列区包括第一区与第二区，所述第一区位于所述外围区与所述第二区之间；
第一支撑层，位于所述基底上，所述第一支撑层在所述第一区的厚度大于其在所述第二区的厚度；
电容器，位于所述阵列区，所述电容器底部设置于所述第一支撑层内。
在一些实施例中，
所述半导体器件还包括第二支撑层，所述第二支撑层位于所述阵列区，且与所述第一支撑层间隔设置；
所述电容器包括第一电容子结构以及第二电容子结构，所述第一电容子结构由所述第二支撑层延伸入所述第一支撑层，所述第二电容子结构位于所述第一电容子结构表面。
在一些实施例中，所述第一支撑层在所述第一区的厚度与其在所述第二区的厚度之差为20nm至100nm。
在一些实施例中，
位于所述第一区的电容器为虚设电容，位于所述第二区的电容器为存储电容。
在一些实施例中，所述虚设电容的第一电容子结构深度小于所述存储电容的第一电容子结构深度。
在一些实施例中，
所述外围区包括第三区以及第四区，所述第三区位于所述第四区与所述阵列区之间，
所述第三区的所述第一支撑层内设置有外围支撑层孔。
在一些实施例中，所述外围支撑层孔为盲孔。
在一些实施例中，所述第一电容子结构包括第一电容电极，所述第二电容子结构包括电容介质层以及第二电容电极，所述电容介质层位于所述第一电容电极表面；所述第二电容电极位于所述电容介质层表面
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一实施例中提供的半导体器件的制备方法的流程图；
图2至图11为一实施例中提供的半导体器件的制备过程中所得结构的截面结构示意图；
图12为一实施例中形成的半导体器件的截面结构示意图。
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
具体实施方式
为了便于理解本公开，下面将参照相关附图对本公开进行更全面的描述。附图中给出了本公开的首选实施例。但是，本公开可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本公开的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中在本公开的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本公开。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应明白，当术语“组成”和/或“包括”在该说明书中使用时，可以确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。同时，在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
在一个实施例中，请参阅图1，提供一种半导体器件的制备方法，包括如下步骤：
步骤S10，提供基底100，基底100具有阵列区以及外围区，阵列区包括第一区与第二区，第一区位于外围区与第二区之间，请参阅图2；
步骤S20，于基底100上形成第一支撑层200，第一支撑层200在第一区的厚度大于其在第二区的厚度，请参阅图4；
步骤S30，于所述阵列区制作电容器500，使所述电容器500底部形成于所述第一支撑层200内，请参阅图11。
在步骤S10中，请参阅图2，基底100可以包括半导体衬底。半导体衬底可以包括硅(Si)衬底、硅锗(SiGe)衬底、硅锗碳(SiGeC)衬底、碳化硅(SiC)衬底、砷化镓(GaAs)衬底、砷化铟(InAs)衬底、磷化铟(InP)衬底或其它的III/V半导体衬底或II/VI半导体衬底。或者，半导体衬底也可以包括Si/SiGe、Si/SiC、绝缘体上硅(SOI)或绝缘体上硅锗等衬底。
此外，基底100还可以包括晶体管结构、电容接触结构110以及第一介质层120等。晶体管结构、电容接触结构110可以形成在阵列区。晶体管结构可以基于半导体衬底形成的。电容接触结构110可以形成在第一介质层120中，可以连接晶体管结构与电容器500。
同时，基底100具有阵列区以及外围区。阵列区用于形成存储阵列。外围区用于形成逻辑电路。阵列区的第一区位于阵列区的边缘，其相对于第二区更靠近外围区。
在步骤S20中，请参阅图4，第一支撑层200可以形成在电容接触结构110以及第一介质层120表面。第一支撑层200的材料可以包括但不限于为氮化硅或者氮氧化硅。
第一支撑层200在阵列区不同区域厚度不同，其在位于阵列区边缘的、靠近外围区的第一区的厚度大于在阵列区的第二区的厚度。第一支撑层200可以为单层结构，也可以为多层结构，这里对此并不做些限制。
在步骤S30中，于阵列区制作电容器500，电容器500可以用作阵列区的存储单元。电容器500底部形成于第一支撑层200内。同时，电容器500还包括位于第一支撑层200之上的部分。
作为示例，包括S30可以包括：
步骤S310，于第一支撑层200上形成牺牲材料层301与第二支撑材料层401，请参阅图4；
步骤S320，刻蚀第二支撑材料层401、牺牲材料层301以及第一支撑层200，于第一区以及第二区形成阵列区电容孔10，请参阅图5；
步骤S330，于阵列区电容孔10内形成第一电容子结构510，请参阅图6；
步骤S340，去除牺牲材料层301以及位于外围区第二支撑材料层401，以形成位于阵列区的第二支撑层400，且于第一电容子结构510表面形成第二电容子结构520，请参阅图11。
在步骤S310中，请参阅图4，牺牲材料层301的材料可以包括但不限于为氧化硅。第二支撑材料层401的材料可以包括但不限于为氮化硅或者氮氧化硅，其与第一支撑层200材料可以相同，也可以不同。
可以在第一支撑层200上形成多组牺牲材料层301与第二支撑材料层401。此时，可以在第一支撑层200上依次交替形成牺牲材料层301与第二支撑材料层401。当然，也可以在第一支撑层200上只形成一组牺牲材料层301与第二支撑材料层401。此时，可以在第一支撑层200表面一层牺牲材料层301，然后再于该层牺牲材料层301表面形成一层第二支撑材料层401。
同时，牺牲材料层301与第二支撑材料层401可以通过沉积工艺形成。沉积工艺可以包括但不限于化学气相沉积(Chemical Vapor Deposition，CVD)工艺、原子层沉积(Atomic Layer Deposition，ALD)工艺、高密度等离子沉积(High Density Plasma，HDP)工艺、等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)工艺及旋涂介质层(Spin-on Dielectric，SOD)等工艺中的一种或多种。
在步骤S320中，请参阅图4，可以首先在位于顶层的第二支撑材料层401表面形成掩 膜材料层801。掩膜材料层801可以是单层结构，也可以是多层堆叠结构。
之后，可以在掩膜材料层801上涂覆第一光刻胶，并经曝光、显影等一系列步骤，形成第一图形化光刻胶30层。请参阅图4，第一图形化光刻胶30层的开口定义阵列区电容孔10的位置及形状。
具体地，第一光刻胶可以为正胶，也可以为负胶。请参阅图4，当第一光刻胶为负胶时，在经过曝光、显影等一系列步骤后，第一光刻胶与第一曝光光罩50的遮光区域相对的部分被去除，而与第一曝光光罩50的透光区域相对的部分被保留，从而使得第一图形化光刻胶30层的开口与第一曝光光罩50的遮光区域相对。当第一光刻胶为正胶时，在经过曝光、显影等一系列步骤后，其与第一曝光光罩50的遮光区域相对的部分被保留，而与第一曝光光罩50的透光区域相对的部分被去除，从而使得第一图形化光刻胶30层的开口与第一曝光光罩50的透光区域相对。
之后，可以基于第一图形化光刻胶30，对掩膜材料层801进行刻蚀，从而形成图形化掩膜层。然后去除第一图形化光刻胶30。之后基于图形化掩膜层，由上至下依次刻蚀第二支撑材料层401、牺牲材料层301以及第一支撑层200，从而于第一区以及第二区形成阵列区电容孔10。此时，阵列区电容孔10由位于顶层的第二支撑材料层401表面延伸入第一支撑层200内，从而使得第一支撑层200可以对后续形成在阵列区电容孔10的第一电容子结构510进行支撑。之后去除图形化掩膜层。
在步骤S330中，请参阅图6，第一电容子结构510为电容器500的部分结构。第一电容子结构510形成于阵列区电容孔10内，因此第一电容子结构也由位于顶层的第二支撑材料层401表面延伸入第一支撑层200内。
作为示例，第一电容子结构510可以包括第一电容电极。第一电容电极的材料可以包括但不限于为氮化钛。
第一电容电极可以填满阵列区电容孔10。此时，可以首先在位于顶层的第二支撑材料层401以及阵列区电容孔10内形成下电极材料层，然后通过化学机械研磨(CMP)去除位于第二支撑材料层401表面的下电极材料层，保留在阵列区电容孔10内的电极材料层形成第一电容电极。
当然，第一电容电极也可以形成阵列区电容孔10的侧壁以及底部。
或者，在其他示例中，第一电容子结构510也可以包括在阵列区电容孔10的侧壁以及底部形成的多个(如两个)电容电极以及电容电极之间的电容介质层。此时，在步骤S340去除牺牲材料层301以及部分第二支撑材料层401之后，可以在第一电容子结构510的基础上形成其他的电容电极以及电容介质层。这里对第一电容子结构510的具体形式并不做限定。
在步骤S340中，请参阅图7至图10，可以首先对第二支撑材料层401进行干法刻蚀，去除其位于外围区的部分，且在阵列区内的第二支撑材料层401内形成开孔，从而暴露位于第二支撑材料层401下方的牺牲材料层301。之后可以通过湿法刻蚀方式，去除第二支撑材料层401下方的牺牲材料层301。
当在第一支撑层200上形成多组牺牲材料层301与第二支撑材料层401时，每组牺牲材料层301与第二支撑材料层401均可以按照上述方式进行处理，从而将所有牺牲材料层301去除，且去除位于外围区第二支撑材料层401，以形成位于阵列区的第二支撑层400。
例如，在第一支撑层200上形成两组牺牲材料层301与第二支撑材料层401时，可以首先对位于上层的第二支撑材料层401进行干法刻蚀(请参阅图7)。之后，对位于上层的牺牲材料层301进行湿法刻蚀去除(请参阅图8)。然后，对位于下层的第二支撑材料层401进行干法刻蚀(请参阅图9)。之后，对位于下层的牺牲材料层301进行湿法刻蚀去除(请参阅图10)。
在去除所有牺牲材料层301，且形成位于阵列区的第二支撑层400之后，形成在阵列 区电容孔10内的第一电容子结构510被第一支撑层200以及第二支撑层400支撑。
此后，请参阅图11，可以在第一电容子结构510的基础上继续进行加工形成第二电容子结构520，从而完成电容器500的制作。即电容器500包括第一电容子结构510以及第二电容子结构520。
作为示例，当第一电容子结构510包括第一电容电极时，于第一电容子结构510表面形成第二电容子结构520可以包括，首先于第一电容电极表面形成电容介质层；然后于电容介质层表面形成第二电容电极。此时，第二电容子结构520包括电容介质层以及第二电容电极。
电容介质层的材料可以包括但不限于为高介电常数材料，如氧化铝等。第二电容电极可以包括电极层与填充层，电极层可以位于电容介质层表面，填充层可以将阵列区电容孔10填满。电极层的材料可以包括但不限于为氮化钛，填充层的材料可以包括但不限于为多晶硅或者锗硅等。
在本实施例方法中，在基底100上形成在阵列区的不同区域(第一区与第二区)厚度不同的第一支撑层200。第一支撑层200在靠近外围区的第一区的厚度大于其在远离外围区的第二区的厚度，从而可以使得第一支撑层200在靠近外围区的第一区的支撑作用更加牢固。此时，可以有效防止电容器的相关结构倒塌。例如，可以有效防止位于阵列区边缘的阵列区电容孔10内形成的第一电容子结构510倒塌，从而可以有效提高产品良率。另一方面，远离外围区的第二区的厚度小于第一区的厚度，从而可以使得位于第二区的阵列区电容孔10内形成的第一电容子结构510侧壁更多的被暴露出来。此时，可以增加电容的正对面积，进而有效保证第二区的电容器500容值不会由于第一支撑层200厚而受到影响。
在一个实施例中，步骤S20包括：
步骤S211，于基底100上形成第一支撑材料层201，请参阅图2；
步骤S212，将位于第二区的第一支撑材料层201减薄，以形成第一支撑层200，请参阅图4。
在步骤S211中，可以通过沉积等方式，在阵列区以及外围区的基底100上形成厚度较大的第一支撑材料层201。
在步骤S212中，请参阅图3，可以首先于第一支撑材料层201表面形成第二光刻胶。然后通过第二曝光光罩对第二光刻胶进行曝光。之后再经过显影等处理，从而形成第二图形化光刻胶40。第二图形化光刻胶40的开口可以暴露阵列区的第二区。
然后，请参阅图3以及图4，可以基于第二图形化光刻胶40，刻蚀减薄位于第二区的第一支撑材料层201，刻蚀后保留的第一支撑材料层201形成第一支撑层200。之后可以去除第二图形化光刻胶40。
此时，位于第一区以及外围区的第一支撑层200厚度大于第二区的第一支撑层200厚度，从而使得位于外围区的第一支撑层200可以辅助位于第一区的第一支撑层200，更加有效防止位于阵列区边缘的阵列区电容孔10内形成的第一电容子结构510倒塌。
同时，第一支撑层200是对第一支撑材料层201进行减薄获取，第一支撑材料层201可以通过一次沉积工艺形成，此时可以形成膜质均匀的第一支撑层200。
在一个实施例中，步骤S20包括：
步骤S221，于基底100上形成第一支撑子层；
步骤S222，于位于第一区的第一支撑子层上形成第二支撑子层，第二支撑子层与第一支撑子层构成第一支撑层200。
在步骤S221中，可以通过沉积等方式，在阵列区以及外围区的基底100上形成厚度较小的第一支撑子层。
在步骤S222中，可以通过掩膜版将阵列区的第二区遮盖，然后在阵列区的第一区以 及外围区形成第二支撑子层。
第二支撑子层的材料与第一支撑子层的材料可以相同也可以不同，这里对此并不作限制。
在本实施例中，可以通过两次沉积工艺而获取第一支撑层200，从而可以省去一次光罩制程，从而可以提高工艺效率。
当然，在其他实施例中，步骤S20形成第一支撑层200的方式并不限于上述两种方式。例如，在一些实施例中，也可以在步骤S221之后，在第一支撑子层上形成一层与其材料不同的第二支撑材料子层。然后，通过光刻、刻蚀等方式去除第二区的第二支撑材料子层，而保留的第二支撑材料子层形成第二支撑子层。第二支撑子层与第一支撑子层构成第一支撑层200。此时，可以有效控制第一支撑层200在第二区的厚度。
在一个实施例中，第一支撑层200在第一区的厚度与其在第二区的厚度之差为20nm至100nm。
此时，第一支撑层200在第一区的厚度与其在第二区的厚度之差不会过大，从而不会影响第一支撑层200表面形成的牺牲材料层301的膜厚均匀性。此时，在第一支撑层200表面形成牺牲材料层301之后，可以省去对牺牲材料层301进行平坦化的步骤。
当然，在其他实施例中，第一支撑层200在第一区的厚度与其在第二区的厚度之差也可以为其他值，这里对此不作限制。
在一个实施例中，请参阅图5，步骤S320包括：
步骤S321，于第一区形成虚设电容孔11，且于第二区形成存储电容孔12，虚设电容孔11用于形成虚设电容，存储电容孔12用于形成存储电容。存储电容为实际用于存储的电容。虚设电容为非实际用于存储的电容。
此时，阵列区电容孔10包括位于第一区的虚设电容孔11与位于所述第二区的存储电容孔12。电容器500包括虚设电容以及存储电容，所述虚设电容的第一电容子结构510位于所述虚设电容孔11内，所述存储电容的第一电容子结构510位于所述存储电容孔12内。
如前述说明，可以在首先在位于顶层的第二支撑材料层401表面形成掩膜材料层801。之后，可以在掩膜材料层801上形成第一图形化光刻胶30层，第一图形化光刻胶30层的开口定义阵列区电容孔10(虚设电容孔11以及存储电容孔12)的位置及形状。然后，基于第一图形化光刻胶30对掩膜材料层801进行刻蚀，从而形成图形化掩膜层。之后基于图形化掩膜层形成阵列区电容孔10(虚设电容孔11以及存储电容孔12)。
在半导体器件的形成过程中，外围区不需要形成电容器500。因此，第一图形化光刻胶30层在阵列区与外围区具有不同的开口密度。此时，在第一图形化光刻胶30的形成过程中，靠近外围区的光刻胶的开口与其他区域的开口的所处环境不同，从而可能导致靠近外围区的开口变形，进而导致基于第一图形化光刻胶30形成的图形化掩膜层在靠近外围区时被刻蚀变形，进而导致最终形成的靠近外围区的阵列区电容孔10变形。
此时，在靠近外围区的第一区设置虚设电容孔11，从而可以为第二区的存储电容孔12提供过渡条件，使得阵列区电容孔10变形发生在虚设电容孔11，从而可以保证存储电容孔12具有精准的图形形状。而基于虚设电容孔11形成的虚设电容为非实际用于存储的电容，从而不会影响阵列区存储性能。
同时，将设置虚设电容孔11的区域作为具有较高厚度的第一支撑层200的区域(第一区)，将设置存储电容孔12的区域作为具有较低厚度的第一支撑层200的区域(第二区)，从而可以使得第一支撑层200的较厚的部分并不会影响存储电容的容值。
当然，其他实施例中，第一区以及第二区设置形式也并不限制此。例如，也可以在第一区形成一部分虚设电容孔11，第二区形成另一部分虚设电容孔11以及存储电容孔12。或者，也可以在第一区形成虚设电容孔11以及小部分存储电容孔12，第二区形成剩余部分存储电容孔12。
在一个实施例中，当于第一区形成虚设电容孔11，且于第二区形成存储电容孔12时，虚设电容孔11深度小于存储电容孔12深度。此时，虚设电容的第一电容子结构510深度小于存储电容的第一电容子结构510深度。
在形成阵列区电容孔10时，刻蚀第二支撑材料层401、牺牲材料层301以及第一支撑层200。第一支撑层200在第一区的厚度大于其在第二区的厚度，因此当刻蚀至位于第一区的第一支撑层200的上表面之后，在第一区对第一支撑层200进行刻蚀，而在第二区需要继续对剩余牺牲材料层301进行刻蚀。同时，第一支撑层200材料与牺牲材料层301的材料不同，牺牲材料层301(如氧化硅层)的刻蚀速率通常大于第一支撑层200(如氮化硅层)的刻蚀速率。此时设置虚设电容孔11深度小于存储电容孔12深度，可以在位于第二区的第一支撑层200刻穿之后即停止刻蚀，从而可以有效提高刻蚀效率。
当然，在一些实施例中，也可以在经过足够时间刻蚀后，使得虚设电容孔11深度也可以等于存储电容孔12深度，这里对此不作限制。
在一个实施例中，外围区包括第三区以及第四区(未图示)，第三区位于第四区与阵列区之间。
同时，请参阅图5，步骤S320于第一区以及第二区形成阵列区电容孔10的同时，还于第三区形成外围区电容孔20。例如，可以于第三区形成3至7个(如5个)外围区电容孔20。
此时，作为示例，阵列区可以在靠近外围区的第一区设置虚设电容孔11，进而使得外围区电容孔20与虚设电容孔11共同为存储电容孔12提供过渡条件。当然，此时，阵列区可以在靠近外围区的第一区设置也可以不再设有虚设电容孔11，而直接形成存储电容孔12，从而提高存储电容孔12的面积占比。
同时请参阅图6，此时，步骤S330之中，于阵列区电容孔10内形成第一电容子结构510的同时，也可以同时于外围区电容孔20内形成第一电容子结构510。而在步骤S340之中，由于牺牲材料层301以及位于外围区第二支撑材料层401被去除，因此位于外围区的第一电容子结构510的上部由于没有支撑而会随之被去除，外围区电容孔20只剩下位于所述第一支撑层200内的部分，将该部分记作形成外围支撑层孔21(请参阅图11)。在步骤S340在阵列区形成电容器500时，保留于外围区的第一支撑层200内的第一电容子结构510上可以同时被形成第二电容子结构520膜层。之后，位于外围区的第一支撑层200内的第一电容子结构510以及及其上的第二电容子结构520膜层膜层可以被去除。之后，可以形成覆盖外围区以及阵列区的第二介质层600(请参阅图11)。然后，可以在外围区形成连接外围导电结构130的导电互连结构700(请参阅图12)。
在本实施例中，类似于前述实施例的虚设电容孔11，外围区电容孔20可以为第二区的存储电容孔12提供过渡条件，使得电容孔变形发生在外围区电容孔20，从而可以保证存储电容孔12具有精准的图形形状。
在一个实施例中，请参阅图5，第一支撑层200在第三区的厚度大于其在第二区的厚度，阵列区电容孔10包括存储电容孔12。外围区电容孔20深度小于存储电容孔12深度。此时，外围区电容孔20与所述基底100之间具有所述第一支撑层200，进而使得步骤S340之后，剩余在第一支撑层内的外围支撑层孔21为盲孔。
第一支撑层200在第三区的厚度与其在第一区的厚度可以相同，也可以不同，这里对此不做限制。
第一支撑层200在第三区的厚度大于其在第二区的厚度，可以使得位于第三区的第一支撑层200可以辅助位于第一区的第一支撑层200，更加有效防止位于阵列区边缘的阵列区电容孔10内形成的第一电容子结构510倒塌。
同时，由于第三区的基底100在与外围区电容孔20相对的位置还可能设有其他的外围导电结构130，当设置虚设电容孔11深度小于存储电容孔12深度时，可以有效刻蚀第 一支撑层200时，刻蚀至该外围导电结构130，而对其造成损伤。
并且，类似于前述实施例的虚设电容孔11，此时设置外围区电容孔20深度小于存储电容孔12深度，可以在位于第二区的第一支撑层200刻穿之后即停止刻蚀，从而可以有效提高刻蚀效率。
应该理解的是，虽然图1的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图1中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
在一个实施例中，请参阅图11或图12，还提供一种半导体器件，半导体器件包括基底100、第一支撑层200、第二支撑层400以及电容器500。
基底100可以包括半导体衬底。半导体衬底可以包括硅(Si)衬底、硅锗(SiGe)衬底、硅锗碳(SiGeC)衬底、碳化硅(SiC)衬底、砷化镓(GaAs)衬底、砷化铟(InAs)衬底、磷化铟(InP)衬底或其它的III/V半导体衬底或II/VI半导体衬底。或者，半导体衬底也可以包括Si/SiGe、Si/SiC、绝缘体上硅(SOI)或绝缘体上硅锗等衬底。
此外，基底100还可以包括晶体管结构、电容接触结构110以及第一介质层120等。晶体管结构、电容接触结构110可以形成在阵列区。晶体管结构可以基于半导体衬底形成的。电容接触结构110可以形成在第一介质层120中，可以连接晶体管结构与电容器500。
同时，基底100具有阵列区以及外围区。阵列区用于形成存储阵列。外围区用于形成逻辑电路。基底100具有阵列区以及外围区，阵列区包括第一区与第二区，第一区位于外围区与第二区之间。阵列区的第一区位于阵列区的边缘，其相对于第二区更靠近外围区。
第一支撑层200可以形成在电容接触结构110以及第一介质层120表面。第一支撑层200的材料可以包括但不限于为氮化硅或者氮氧化硅。
第一支撑层200在阵列区不同区域厚度不同，其在位于阵列区边缘的、靠近外围区的第一区的厚度大于在阵列区的第二区的厚度。第一支撑层200可以为单层结构，也可以为多层结构，这里对此并不做些限制。
电容器500位于阵列区。电容器500可以用作阵列区的存储单元。电容器500底部形成于第一支撑层200内。同时，电容器500还包括位于第一支撑层200之上的部分。
作为示例，半导体器件还包括第二支撑层400。电容器500包括第一电容子结构510以及第二电容子结构520。
第二支撑层400位于阵列区，且与第一支撑层200间隔设置。作为示例，第一支撑层200上可以形成多个第二支撑层400。各第二支撑层400之间可以间隔设置，且第二支撑层400于第一支撑层200之间间隔设置。
第二支撑层400的材料可以包括但不限于为氮化硅或者氮氧化硅，其与第一支撑层200材料可以相同，也可以不同。
第一电容子结构510由第二支撑层400延伸入第一支撑层200。
例如，第一电容子结构510可以包括第一电容电极。第一电容电极的材料可以包括但不限于为氮化钛。第一电容电极可以填满阵列区电容孔10。或者，第一电容电极也可以形成阵列区电容孔10的侧壁以及底部。
或者，又如第一电容子结构510也可以包括在阵列区电容孔10的侧壁以及底部形成的多个(如两个)电容电极以及电容电极之间的电容介质层。电容器500处了位于阵列区电容孔10内的第一电容子结构510，还可以包括其他的电容电极以及电容介质层。这里对第一电容子结构510的具体形式并不做限定。
在本实施例中，第一支撑层200在靠近外围区的第一区的厚度大于其在远离外围区的 第二区的厚度，从而可以使得第一支撑层200在靠近外围区的第一区的支撑作用更加牢固。此时，可以有效防止位于阵列区边缘的电容相关结构倒塌。例如，可以有效防止位于阵列区边缘的第一电容子结构510倒塌，从而可以有效提高产品良率。另一方面，远离外围区的第二区的厚度小于第一区的厚度，从而可以使得位于第二区的阵列区电容孔10内形成的第一电容子结构510侧壁更多的被暴露出来。此时，可以增加电容的正对面积，进而有效保证第二区的电容器500容值不会由于第一支撑层200厚而受到影响。
在一个实施例中，第一支撑层200在第一区的厚度与其在第二区的厚度之差为20nm至100nm。
在一个实施例中，位于第一区的虚设电容孔11电容器500为虚设电容。位于第二区的电容器500为存储电容。虚设电容的第一电容子结构510位于虚设电容孔11内，存储电容的第一电容子结构510位于存储电容孔12内。
在一个实施例中，虚设电容的第一电容子结构510深度小于所述存储电容的第一电容子结构510深度。
在一个实施例中，外围区包括第三区以及第四区，第三区位于第四区与阵列区之间。第三区的第一支撑层200内设置有外围支撑层孔21。
在一个实施例中，外围支撑层孔21为盲孔。
在一个实施例中，第一电容子结构510包括第一电容电极，第二电容子结构520包括电容介质层以及第二电容电极。
第一电容电极位于阵列区电容孔10内。电容介质层位于第一电容电极表面。第二电容电极位于电容介质层表面。
上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本公开的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本公开构思的前提下，还可以做出若干变形和改进，这些都属于本公开的保护范围。因此，本公开专利的保护范围应以所附权利要求为准。

Claims (17)

  1. 一种半导体器件的制备方法，其特征在于，包括：
    提供基底(100)，所述基底(100)具有阵列区以及外围区，所述阵列区包括第一区与第二区，所述第一区位于所述外围区与所述第二区之间；
    于所述基底(100)上形成第一支撑层(200)，所述第一支撑层(200)在所述第一区的厚度大于其在所述第二区的厚度；
    于所述阵列区制作电容器(500)，使所述电容器(500)底部形成于所述第一支撑层(200)内。
  2. 根据权利要求1所述的半导体器件的制备方法，其特征在于，所述于所述阵列区制作电容器(500)，使所述电容器(500)底部形成于所述第一支撑层(200)内，包括：
    于所述第一支撑层(200)上形成牺牲材料层(301)与第二支撑材料层(401)；
    刻蚀所述第二支撑材料层(401)、所述牺牲材料层(301)以及所述第一支撑层(200)，于所述第一区以及所述第二区形成阵列区电容孔(10)；
    于所述阵列区电容孔(10)内形成第一电容子结构(510)；
    去除所述牺牲材料层(301)以及位于所述外围区第二支撑材料层(401)，以形成位于所述阵列区的第二支撑层(400)，且于所述第一电容子结构(510)表面形成第二电容子结构(520)。
  3. 根据权利要求1或2所述的半导体器件的制备方法，其特征在于，所述于所述基底(100)上形成第一支撑层(200)包括：
    于所述基底(100)上形成第一支撑材料层(201)；
    将位于所述第二区的所述第一支撑材料层(201)减薄，以形成所述第一支撑层(200)。
  4. 根据权利要求1至3任一项所述的半导体器件的制备方法，其特征在于，所述于所述基底(100)上形成第一支撑层(200)，包括：
    于所述基底(100)上形成第一支撑子层；
    于位于所述第一区的所述第一支撑子层上形成第二支撑子层，所述第二支撑子层与所述第一支撑子层构成所述第一支撑层(200)。
  5. 根据权利要求1至4任一项所述的半导体器件的制备方法，其特征在于，所述第一支撑层(200)在所述第一区的厚度与其在所述第二区的厚度之差为20nm至100nm。
  6. 根据权利要求2至5任一项所述的半导体器件的制备方法，其特征在于，所述刻蚀所述第二支撑材料层(401)、所述牺牲材料层(301)以及所述第一支撑层(200)，于所述第一区以及所述第二区形成阵列区电容孔(10)，包括：
    于所述第一区形成虚设电容孔(11)，且于所述第二区形成存储电容孔(12)，所述虚设电容孔(11)用于形成虚设电容，所述存储电容孔(12)用于形成存储电容。
  7. 根据权利要求6所述的半导体器件的制备方法，其特征在于，所述虚设电容孔(11)深度小于所述存储电容孔(12)深度。
  8. 根据权利要求2至7任一项所述的半导体器件的制备方法，其特征在于，
    所述外围区包括第三区以及第四区，所述第三区位于所述第四区与所述阵列区之间，
    所述刻蚀所述第二支撑材料层(401)、所述牺牲材料层(301)以及所述第一支撑层(200)，于所述第一区以及所述第二区形成阵列区电容孔(10)的同时，还于所述第三区形成外围区电容孔(20)。
  9. 根据权利要求8所述的半导体器件的制备方法，其特征在于，第一支撑层(200)在所述第三区的厚度大于其在所述第二区的厚度，所述阵列区电容孔(10)包括存储电容孔(12)，所述外围区电容孔(20)深度小于所述存储电容孔(12)深度。
  10. 根据权利要求2至9任一项所述的半导体器件的制备方法，其特征在于，所述第一电容子结构(510)包括第一电容电极，
    所述于所述第一电容子结构(510)表面形成第二电容子结构(520)，包括：
    于所述第一电容电极表面形成电容介质层；
    于所述电容介质层表面形成第二电容电极。
  11. 一种半导体器件，其特征在于，包括：
    基底(100)，所述基底(100)具有阵列区以及外围区，所述阵列区包括第一区与第二区，所述第一区位于所述外围区与所述第二区之间；
    第一支撑层(200)，位于所述基底(100)上，所述第一支撑层(200)在所述第一区的厚度大于其在所述第二区的厚度；
    电容器(500)，位于所述阵列区，所述电容器(500)底部设置于所述第一支撑层(200)内。
  12. 根据权利要求11所述的半导体器件，其特征在于，
    所述半导体器件还包括第二支撑层(400)，所述第二支撑层(400)位于所述阵列区，且与所述第一支撑层(200)间隔设置；
    所述电容器(500)包括第一电容子结构(510)以及第二电容子结构(520)，所述第一电容子结构(510)由所述第二支撑层(400)延伸入所述第一支撑层(200)，所述第二电容子结构(520)位于所述第一电容子结构(510)表面。
  13. 根据权利要求11或12所述的半导体器件，其特征在于，所述第一支撑层(200)在所述第一区的厚度与其在所述第二区的厚度之差为20nm至100nm。
  14. 根据权利要求11至13任一项所述的半导体器件，其特征在于，
    位于所述第一区的电容器(500)为虚设电容，位于所述第二区的电容器(500)为存储电容。
  15. 根据权利要求14所述的半导体器件，其特征在于，所述虚设电容的第一电容子结构(510)深度小于所述存储电容的第一电容子结构(510)深度。
  16. 根据权利要求12至15任一项所述的半导体器件，其特征在于，
    所述外围区包括第三区以及第四区，所述第三区位于所述第四区与所述阵列区之间，
    所述第三区的所述第一支撑层(200)内设置有外围支撑层孔(21)。
  17. 根据权利要求16所述的半导体器件，其特征在于，所述外围支撑层孔(21)为盲孔。
PCT/CN2023/111046 2023-01-09 2023-08-03 半导体器件及其制备方法 Ceased WO2024148797A1 (zh)

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