WO2024130695A1 - 阵列基板及其制备方法、显示面板、显示装置 - Google Patents

阵列基板及其制备方法、显示面板、显示装置 Download PDF

Info

Publication number
WO2024130695A1
WO2024130695A1 PCT/CN2022/141368 CN2022141368W WO2024130695A1 WO 2024130695 A1 WO2024130695 A1 WO 2024130695A1 CN 2022141368 W CN2022141368 W CN 2022141368W WO 2024130695 A1 WO2024130695 A1 WO 2024130695A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
orthographic projection
via hole
layer
conductive
Prior art date
Application number
PCT/CN2022/141368
Other languages
English (en)
French (fr)
Inventor
安晖
操彬彬
叶成枝
吕艳明
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/141368 priority Critical patent/WO2024130695A1/zh
Publication of WO2024130695A1 publication Critical patent/WO2024130695A1/zh

Links

Images

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, a display panel, and a display device.
  • the purpose of the present disclosure is to overcome the deficiencies of the above-mentioned prior art and to provide an array substrate and a preparation method thereof, a display panel, and a display device.
  • an array substrate comprising a display area and a transition area provided on at least one side of the display area, the array substrate comprising:
  • An insulating layer group is provided on one side of the first substrate, and a recessed portion is provided on the insulating layer group, and the recessed portion is located in the transition area;
  • a first electrode layer is provided on a side of the insulating layer group away from the first substrate;
  • the conductive enhancement layer is disposed on a side of the first electrode layer away from the first substrate, and the orthographic projection of the conductive enhancement layer on the first substrate is located within the orthographic projection of the first electrode layer on the first substrate.
  • a first via hole is further provided on the insulating layer group, the first via hole is located in the display area, and the orthographic projection area of the first via hole on the first base substrate is equal to or smaller than the orthographic projection area of the recessed portion on the first base substrate.
  • a second via and a third via are provided on the first electrode layer, the second via is located in the display area, the third via is located in the transition area, the orthographic projection of the recessed portion on the first substrate is located within the orthographic projection of the third via on the first substrate, and the orthographic projection of the first via on the first substrate is located within the orthographic projection of the second via on the first substrate.
  • an orthographic projection area of the third via hole on the first substrate is greater than or equal to an orthographic projection area of the second via hole on the first substrate.
  • a distance between an edge line of an orthographic projection of the recessed portion on the first substrate and an edge line of an orthographic projection of the third via on the first substrate is greater than or equal to a distance between an edge line of an orthographic projection of the first via on the first substrate and an edge line of an orthographic projection of the second via on the first substrate.
  • the conductive reinforcement layer comprises:
  • a first conductive strip extending along a first direction
  • the second conductive strip extends along a second direction, the second direction intersects the first direction, and the first direction and the second direction are parallel to a surface of the first substrate close to the insulating layer group.
  • the spacing between the edge line of the orthographic projection of the third via on the first substrate and the edge line of the orthographic projection of the adjacent first conductive strip on the first substrate is greater than or equal to the spacing between the edge line of the orthographic projection of the second via on the first substrate and the edge line of the orthographic projection of the adjacent first conductive strip on the first substrate; the spacing between the edge line of the orthographic projection of the third via on the first substrate and the edge line of the orthographic projection of the adjacent second conductive strip on the first substrate is greater than or equal to the spacing between the edge line of the orthographic projection of the second via on the first substrate and the edge line of the orthographic projection of the adjacent second conductive strip on the first substrate.
  • the array substrate further includes:
  • a switch layer group is provided between the first substrate and the insulating layer group, and the switch layer group includes:
  • a plurality of switch units are arranged in an array
  • a plurality of gate lines extending along the first direction, each of the gate lines being located between two adjacent switch units, and an orthographic projection of the first conductive strip on the first substrate at least partially overlaps with an orthographic projection of the gate line on the first substrate;
  • a plurality of data lines extend along the second direction, each of the data lines is located between two adjacent switch units, an orthographic projection of the second conductive strip on the first substrate at least partially overlaps with an orthographic projection of the data line on the first substrate, and a plurality of the gate lines and a plurality of the data lines intersect to form a plurality of pixel areas.
  • At least two of the recessed portions and at least two of the third via holes are provided in one of the pixel regions in the transition zone; one of the first via holes and one of the second via holes are provided in one of the pixel regions in the display zone.
  • the recessed portion and the first via hole located in a row of the pixel regions arranged along the first direction are located in the same region in the corresponding pixel region.
  • only one row of pixel areas arranged along the first direction is provided in the transition area on one side of the second direction of the display area, and only one column of pixel areas arranged along the second direction is provided in the transition area on one side of the first direction of the display area.
  • the switch unit does not include a drain and a drain connection lead, and an orthographic projection of the recess on the first substrate does not overlap with the switch unit.
  • a distance between a lowest point of the recessed portion and the first substrate is smaller than a distance between a lowest point of the first via hole and the first substrate.
  • the conductive reinforcement layer further includes:
  • each lead line is connected to the second conductive strip, and each lead line extends along the first direction toward a side away from the display area.
  • an orthographic projection of the lead line on the first substrate has no overlap with an orthographic projection of the gate line on the first substrate.
  • two data lines are arranged between orthographic projections of two adjacent second conductive strips on the first substrate.
  • the conductive reinforcement layer further includes:
  • the summary connecting bar is connected to an end of the lead bar away from the second conductive bar, and the summary connecting bar extends along the second direction.
  • the insulating layer group includes:
  • a first insulating layer disposed on one side of the first base substrate, wherein a fifth via hole is disposed on the first insulating layer, the fifth via hole is located in the display area and connected to the switch unit;
  • the organic insulating layer is arranged on a side of the first insulating layer away from the first base substrate, and a sixth via hole and a seventh via hole are arranged on the organic insulating layer.
  • the sixth via hole is the recessed portion, and the seventh via hole is connected with the fifth via hole to form the first via hole.
  • the array substrate further includes:
  • a second insulating layer arranged on a side of the conductive reinforcement layer away from the first substrate, a fourth via hole being arranged on the second insulating layer, an orthographic projection of the seventh via hole on the first substrate covering and being larger than an orthographic projection of the fourth via hole on the first substrate, the second insulating layer covering a hole side wall of the seventh via hole, and covering a portion of the first insulating layer exposed in the seventh via hole, so that the second insulating layer forms a step portion in the seventh via hole;
  • a second electrode layer is arranged on a side of the second insulating layer away from the first substrate, the second electrode layer includes a plurality of second electrodes, the second electrodes include a main body portion and a connecting portion connected to each other, the connecting portion is connected to the switch unit through the fourth via hole and the fifth via hole, and the main body portion is located on a side of the step portion away from the first substrate.
  • the array substrate further includes:
  • a first spacer is provided on a side of the second electrode layer away from the first substrate and is located between two adjacent switch units;
  • the orthographic projection of the first conductive strip on the first substrate is set as a curve, and the first conductive strip is bent toward a side away from the first spacer at a position adjacent to the first spacer.
  • an orthographic projection of the first conductive strip on the first substrate has no overlap with an orthographic projection of the first spacer on the first substrate.
  • the first conductive strip includes a first straight portion and a first curved portion
  • the orthographic projection of the first straight portion on the first substrate is located within the orthographic projection of the gate line on the first substrate
  • the orthographic projection of the first curved portion on the first substrate at least partially does not overlap with the orthographic projection of the gate line on the first substrate.
  • the array substrate further has a peripheral area, which is arranged on a side of the transition area away from the display area, and a plurality of peripheral leads are arranged in the peripheral area, and in a third direction, a height of the insulating layer group in the peripheral area is higher than a height of the insulating layer group in the display area, and the third direction is perpendicular to a side of the first substrate close to the insulating layer group.
  • a distance between an edge line of the recessed portion close to the display area and the display area is greater than a distance between an edge line of the recessed portion close to the peripheral area and the peripheral area.
  • an orthographic projection of the conductive enhancement layer on the first substrate has no overlap with an orthographic projection of the recessed portion on the first substrate.
  • the array substrate further includes:
  • the protective layer is disposed on a side of the conductive enhancement layer away from the first substrate.
  • a method for preparing an array substrate comprising:
  • the first base substrate has a display area and a transition area provided on at least one side of the display area, forming an insulating layer group on one side of the first base substrate, forming a recessed portion on the insulating layer group, and the recessed portion is located in the transition area;
  • a mask layer on a side of the conductive reinforcement material layer away from the first substrate, wherein a portion of the mask layer is formed in the recessed portion, and a thickness of the mask layer in the display area is uniform;
  • the first electrode material layer is patterned using the mask layer as a mask to form a first electrode layer, and the conductive reinforcing material layer is patterned to form a conductive reinforcing layer.
  • a first via is formed on the insulating layer group while the recess is formed, the first via is located in the display area, and an orthographic projection area of the first via on the first substrate is equal to or smaller than an orthographic projection area of the recess on the first substrate.
  • the first electrode material layer is patterned using the mask layer as a mask to form a first electrode layer
  • the conductive enhancement material layer is patterned to form a conductive enhancement layer, including:
  • the mask pattern comprising a first portion and a second portion, the first portion having a thickness greater than that of the second portion, a ninth via hole being formed on the second portion, a portion of the ninth via hole being arranged opposite to the first via hole, and another portion of the ninth via hole being arranged opposite to the recessed portion;
  • the remaining conductive enhancement material layer is patterned to form a conductive enhancement layer.
  • a display panel comprising:
  • An array substrate is any one of the array substrates described above;
  • the color filter substrate is arranged opposite to the array substrate, and the color filter substrate includes a black matrix.
  • the orthographic projection of the conductive enhancement layer on the first base substrate is located within the orthographic projection of the black matrix on the first base substrate.
  • a display panel comprising:
  • An array substrate is any one of the array substrates described above;
  • a color filter substrate is arranged opposite to the array substrate, the color filter substrate includes a black matrix, the orthographic projection of the conductive enhancement layer on the first base substrate is located within the orthographic projection of the black matrix on the first base substrate, and the edge line of one side of the black matrix close to the first conductive strip is set to a curve adapted to the first conductive strip.
  • a display device comprising: the display panel described above.
  • 1 to 7 are schematic structural diagrams of various steps of forming a conductive enhancement layer when the mask layer is relatively thick.
  • FIG. 8 is a schematic structural diagram of a first exemplary embodiment of an array substrate disclosed in the present invention.
  • FIG. 9 is a schematic structural diagram of an exemplary implementation of a gate layer in an array substrate of the present disclosure.
  • FIG. 10 is a schematic structural diagram of an active layer formed on the basis of FIG. 9 .
  • FIG. 11 is a schematic structural diagram of a connecting conductor layer formed on the basis of FIG. 10 .
  • FIG. 12 is a schematic structural diagram of an insulating layer group, a first electrode layer and a conductive reinforcement layer formed on the basis of FIG. 11 .
  • FIG. 13 is a schematic diagram showing the size relationship between the recessed portion of the transition region, the third via hole, and the conductive reinforcement layer.
  • FIG. 14 is a schematic diagram showing the size relationship between the first via hole and the second via hole in the display area and the conductive enhancement layer.
  • FIG. 15 is a schematic diagram of the structure of the conductive reinforcement layer.
  • FIG. 16 is a schematic structural diagram of a second exemplary embodiment of an array substrate disclosed herein.
  • FIG. 17 is a schematic structural diagram of a third exemplary embodiment of an array substrate disclosed herein.
  • FIG. 18 is a schematic diagram of a top view of the structure of a fourth exemplary embodiment of the array substrate disclosed in the present invention.
  • FIG. 19 is a schematic diagram of a top view of the structure of a fifth exemplary embodiment of the array substrate disclosed herein.
  • FIG. 20 is a schematic flow chart of an exemplary embodiment of a method for preparing an array substrate according to the present invention.
  • 21 to 27 are schematic structural diagrams of the various steps of the method for preparing the array substrate of the present invention.
  • FIG. 28 is a schematic structural diagram of an exemplary embodiment of a display panel according to the present disclosure.
  • Switch layer group 21. Switch unit; 22. Gate layer; 221. Gate line; 222. Gate; 223. Peripheral lead; 23. Gate insulation layer; 24. Active layer; 241. Channel portion; 242. Source; 243. Drain; 25. Connecting conductor layer; 251. Source connecting lead; 252. Drain connecting lead; 253. Data line; 26. Pixel region;
  • Insulating layer group 31. First insulating layer; 311. Fifth via hole; 32. Organic insulating layer; 321. Sixth via hole; 322. Seventh via hole; 323. Hole; 33. Concave portion; 34. First via hole;
  • second electrode layer 71. second electrode; 711. main body; 712. connecting part;
  • mask layer 91. mask pattern; 911. first part; 912. second part; 913. ninth via hole;
  • 201 second base substrate; 202, black matrix; 203, filter unit;
  • X first direction
  • Y second direction
  • Z third direction
  • AA display area
  • DUM transition area
  • WW peripheral area
  • connection should be understood in a broad sense.
  • connection can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium.
  • And/or is just a description of the association relationship of the associated objects, indicating that there can be three relationships.
  • a and/or B can mean: A exists alone, A and B exist at the same time, and B exists alone.
  • the character "/" in this article generally indicates that the previous and next associated objects are in an "or” relationship.
  • the display brightness of the display panel is uneven, mainly because the brightness of the edge area of the display area AA is low.
  • the inventors found that the main reason for this defect is that there is a lot of residue of the conductive enhancement layer 5 in the edge area of the display area AA, and the conductive enhancement layer 5 will affect the transmittance, so that the transmittance of the edge area of the display area AA is low; and the reason why there is a lot of residue of the conductive enhancement layer 5 in the display area AA is that the peripheral area WW is provided with a large area of peripheral leads 223, resulting in the height of the peripheral area WW being higher than the height of the display area AA and the height of the transition area DUM.
  • the mask layer 9 is formed by coating or printing process on the side of the conductive enhancement material layer 50 away from the first substrate 1. Since the material of the mask layer 9 has a certain fluidity, it will flow from the area with a higher height to the area with a lower height, so , the material of the mask layer 9 will flow from the peripheral area WW to the transition area DUM and the display area AA, resulting in a thicker mask layer 9 in the edge area of the display area AA close to the transition area DUM, which in turn results in more mask layer 9 remaining in the edge area of the display area AA close to the transition area DUM when the conductive reinforcement material layer 50 is etched to form the conductive reinforcement layer 5, that is, the mask layer 9 blocks a larger area of the conductive reinforcement material layer 50, and ultimately results in a larger area of the formed conductive reinforcement layer 5, resulting in lower light transmittance and lower brightness in the edge area of the display area AA.
  • An example embodiment of the present disclosure provides an array substrate 100, as shown in Figures 8 to 19, the array substrate 100 has a display area AA and a transition area DUM arranged on at least one side of the display area AA, the array substrate 100 may include a first base substrate 1, an insulating layer group 3, a first electrode layer 4 and a conductive enhancement layer 5; the insulating layer group 3 is arranged on one side of the first base substrate 1, and a recessed portion 33 is arranged on the insulating layer group 3, and the recessed portion 33 is located in the transition area DUM; the first electrode layer 4 is arranged on the side of the insulating layer group 3 away from the first base substrate 1; the conductive enhancement layer 5 is arranged on the side of the first electrode layer 4 away from the first base substrate 1, and the orthographic projection of the conductive enhancement layer 5 on the first base substrate 1 is located within the orthographic projection of the first electrode layer 4 on the first base substrate 1.
  • a recessed portion 33 is provided on the insulating layer group 3, and the recessed portion 33 is located in the transition area DUM; so that when the first electrode layer 4 and the conductive enhancement layer 5 are formed, the mask layer 9 formed on the side of the conductive enhancement material layer 50 away from the first base substrate 1 will flow into the recessed portion 33 of the transition area DUM when flowing from the peripheral area WW to the display area AA, so that the thickness of the mask layer 9 in the display area AA is uniform, and when the conductive enhancement material layer 50 is etched to form the conductive enhancement layer 5, the mask layer 9 at various locations in the display area AA blocks the conductive enhancement material layer 50 in substantially the same area, so that the area of the formed conductive enhancement layer 5 is substantially consistent, and the brightness at various locations in the display area AA is also substantially consistent.
  • the conductive enhancement layer 5 can reduce the resistance of the first electrode layer 4, thereby reducing the power consumption of the array substrate 100 and reducing
  • first direction X and the second direction Y are parallel to a surface of the first base substrate 1 close to the insulating layer group 3, and the first direction X intersects with the second direction Y.
  • first direction X may be perpendicular to the second direction Y.
  • the third direction Z is perpendicular to a surface of the first base substrate 1 close to the insulating layer group 3, that is, the third direction Z is perpendicular to both the first direction X and the second direction Y.
  • the array substrate 100 may include a display area AA, a transition area DUM and a peripheral area WW.
  • the transition area DUM is arranged on at least one side of the display area AA.
  • the transition area DUM may be arranged on all four sides of the display area AA.
  • the peripheral area WW is arranged on a side of the transition area DUM away from the display area AA, and the display area AA, the transition area DUM and the peripheral area WW are connected in sequence.
  • the material of the first base substrate 1 may include an inorganic material, for example, the inorganic material may be glass, quartz or metal.
  • the material of the first base substrate 1 may also include an organic material, for example, the organic material may be a resin material such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate and polyethylene naphthalate.
  • the base substrate may be formed by a plurality of material layers, for example, the base substrate may include a plurality of second base substrates 201, and the material of the second base substrate 201 may be any of the above materials.
  • the base substrate may also be set as a single layer, which may be any of the above materials.
  • a switch layer group 2 may be provided on one side of the first base substrate 1 , and the switch layer group 2 may include a gate layer 22 , a gate insulating layer 23 , an active layer 24 , and a connecting conductor layer 25 .
  • a gate layer 22 may be provided on one side of the first base substrate 1 , and the gate layer 22 may include multiple gates 222 and multiple gate lines 221 .
  • the gate line 221 extends along the first direction X, and multiple gates 222 are connected to one gate line 221 ; or a part of the gate line 221 may serve as the gate 222 .
  • a gate insulating layer 23 is disposed on a side of the gate layer 22 away from the first base substrate 1 .
  • an active layer 24 is provided on a side of the gate insulating layer 23 away from the first base substrate 1, and the active layer 24 may include a channel portion 241, a source electrode 242, and a drain electrode 243.
  • the channel portion 241 is provided on a side of the gate electrode 222 away from the first base substrate 1.
  • a portion of the gate line 221 is used as the gate electrode 222
  • a portion of the gate line 221 opposite to the channel portion 241 is used as the gate electrode 222.
  • Two portions are provided at opposite ends of the channel portion 241, one portion of which may be the source electrode 242, and the other portion of which may be the drain electrode 243.
  • a connection conductor layer 25 is provided on a side of the active layer 24 away from the first base substrate 1, and the connection conductor layer 25 may include a plurality of source connection leads 251, a plurality of drain connection leads 252, and a plurality of data lines 253.
  • the data lines 253 extend along the second direction Y. Therefore, the data lines 253 and the gate lines 221 are bound to intersect, and the plurality of data lines 253 and the plurality of gate lines 221 intersect to form a plurality of pixel regions 26.
  • the source 242 and the drain 243 are not limited to the above description.
  • a portion of the drain connection lead 252 overlapping one end of the channel portion 241 may also be the drain 243, and a portion of the source connection lead 251 overlapping the other end of the channel portion 241 may also be the source 242.
  • transition area DUM on one side of the second direction Y of the display area AA only one row of pixel areas 26 arranged along the first direction X is provided, and in the transition area DUM on one side of the first direction X of the display area AA, only one column of pixel areas 26 arranged along the second direction Y is provided.
  • a circle of pixel areas 26 may be provided around the periphery of the display area AA, that is, the number of rows and columns of the pixel areas 26 in the transition area DUM is reduced.
  • the transition area DUM Since there is no recessed portion 33 on the insulating layer group 3 on the transition area DUM, the transition area DUM approaches a relatively horizontal plane; however, a first via hole 34 is provided on the insulating layer group 3 of the display area AA, so that the average height of the display area AA is lower than the average height of the transition area DUM, so that the material of the mask layer 9 of the transition area DUM also has a tendency to flow toward the display area AA.
  • Reducing the number of rows and columns of the pixel area 26 in the transition area DUM reduces the area of the transition area DUM, reduces the total amount of material of the mask layer 9 of the transition area DUM, and can alleviate the amount of material of the mask layer 9 flowing toward the display area AA, avoid the thickness of the mask layer 9 in the edge area of the display area AA being thick, and avoid the defect of low transmittance and low brightness caused by more residue of the conductive enhancement layer 5.
  • One end of the source connection lead 251 is connected to the data line 253 , and the other end is connected to the source 242 ; a part of the data line 253 may also be used as the source connection lead 251 .
  • One end of the drain connection lead 252 is connected to the drain 243 .
  • the gate electrode 222 , the channel portion 241 , the source electrode 242 , the drain electrode 243 , and the like form a switching unit 21 , which is a thin film transistor.
  • the thin film transistor described in this specification is a bottom-gate thin film transistor.
  • the thin film transistor may also be a top-gate type or a dual-gate type, and its specific structure will not be described in detail here.
  • the functions of the "source 242" and the “drain 243" are sometimes interchanged. Therefore, in this specification, the "source 242" and the “drain 243" may be interchanged.
  • the above-mentioned switch unit 21 is a specific structure of the switch unit 21 of the display area AA.
  • the switch unit 21 may be provided in the transition area DUM, and the specific structure of the switch unit 21 may be the same as the specific structure of the switch unit 21 of the display area AA; in other exemplary embodiments of the present disclosure, since the source connection lead 251 is a part of the data line 253, and in order to maintain the consistency of the electrical performance, only a part of the source connection lead 251 close to the data line 253 may be provided, and the source connection lead 251 and the active layer 24 are formed by the same patterning process, therefore, referring to FIG.
  • An active layer 24 connected to the source connection lead 251 and located on the side of the source connection lead 251 close to the first substrate 1 may also be provided, that is, the drain connection lead 252 and another part of the active layer 24 connected to the drain connection lead 252 are not provided; that is, the drain connection lead 252 and the drain 243 connected to the drain connection lead 252 are not provided, so that the depth of the via hole can be made deeper, that is, the distance between the lowest point of the recessed portion 33 and the first substrate 1 is smaller than the distance between the lowest point of the first via hole 34 and the first substrate 1, and more materials of the mask layer 9 can be accommodated.
  • the active layer 24 connected to the source connection lead 251 and located on the side of the source connection lead 251 close to the first substrate 1 may also be not provided, that is, the active layer 24 is not provided in the transition area DUM.
  • the source connection lead 251 when the source connection lead 251 is not a part of the data line 253 , the source connection lead 251 may not be provided, and only the data line 253 may be provided.
  • the switch unit 21 of the transition zone DUM can be set according to product structure requirements and process requirements.
  • the switch unit 21 of the transition zone DUM does not need to be connected to the second electrode 71, and does not need to provide voltage to the second electrode 71. Therefore, the structure of the switch unit 21 may be incomplete, and may only include one component, two components or more components in the above-mentioned complete switch unit 21.
  • a plurality of peripheral leads 223 are provided in the peripheral area WW, and both the data line 253 and the gate line 221 are connected to the peripheral leads 223.
  • the peripheral leads 223 can be provided in the same layer and material as the gate line 221, or in the same layer and material as the data line 253, or can be provided with two layers of peripheral leads 223. Data signals are input to the data line 253 through the peripheral leads 223, control signals are input to the gate line 221 through the peripheral leads 223, and some feedback signals are output through the peripheral leads 223.
  • the mask layer 9 has a certain fluidity, and the material of the mask layer 9 will flow from the peripheral area WW to the transition area DUM and the display area AA, resulting in a thicker mask layer 9 in the edge area of the display area AA close to the transition area DUM, which in turn results in more mask layer 9 remaining in the edge area of the display area AA close to the transition area DUM when the conductive reinforcement material layer 50 is etched to form the conductive reinforcement layer 5, that is, the mask layer 9 blocks a larger area of the conductive reinforcement material layer 50, which ultimately results in a larger area of the formed conductive reinforcement layer 5, resulting in a lower light transmittance and brightness in the edge area of the display area AA.
  • an insulating layer group 3 is provided on the side of the connecting conductor layer 25 away from the first base substrate 1, and the insulating layer group 3 may include a first insulating layer 31 and an organic insulating layer 32.
  • the first insulating layer 31 is provided on the side of the connecting conductor layer 25 away from the first base substrate 1, and a fifth via hole 311 is provided on the first insulating layer 31.
  • the fifth via hole 311 is located in the display area AA, and the fifth via hole 311 is connected to the drain connection lead 252, so that the drain connection lead 252 is exposed.
  • the material of the first insulating layer 31 may be an inorganic material, for example, silicon nitride, silicon oxide, etc.
  • the thickness of the first insulating layer 31 is greater than or equal to 100 nm and less than or equal to 500 nm.
  • the organic insulating layer 32 is disposed on the side of the first insulating layer 31 away from the first base substrate 1 , and the material of the organic insulating layer 32 may be an organic material, for example, polyimide, polycarbonate, polyacrylate, etc.
  • the thickness of the organic insulating layer 32 is greater than or equal to 1.5 ⁇ m and less than or equal to 5 ⁇ m.
  • the organic insulating layer 32 can play a flattening role, providing a relatively flat base for the first electrode layer 4 formed subsequently, facilitating the forming of the first electrode layer 4, thereby improving the uniformity of the first electrode layer 4; in addition, the organic insulating layer 32 increases the distance between the first electrode layer 4 and the data line 253 in the third direction Z, weakens the mutual influence, and greatly reduces the parasitic capacitance, which is more conducive to the driving of the driving chip; after the distance between the first electrode layer 4 and the data line 253 in the third direction Z increases, the distance between the first electrode layer 4 and the data line 253 in other directions (for example, in the first direction X and the second direction Y) can be shortened, so that the width of the black matrix 202 of the color film substrate 200 can also be made smaller, thereby improving the aperture ratio of the product.
  • a sixth via hole 321 and a seventh via hole 322 are provided on the organic insulating layer 32.
  • the sixth via hole 321 is located in the transition area DUM, and the sixth via hole 321 forms a recessed portion 33 of the insulating layer group 3.
  • the seventh via hole 322 is located in the display area AA, and the seventh via hole 322 is connected to the fifth via hole 311 to form a first via hole 34 of the insulating layer group 3, so that the drain connection lead 252 is exposed.
  • an eighth via hole may be provided on the first insulating layer 31 , the eighth via hole being located in the transition area DUM, and the sixth via hole 321 may be connected to the eighth via hole to form a recessed portion 33 of the insulating layer group 3 .
  • the orthographic projection area of the first via hole 34 on the first base substrate 1 is equal to or smaller than the orthographic projection area of the recess 33 on the first base substrate 1, that is, the area of the recess 33 located in the transition zone DUM is set larger, so that the recess 33 can accommodate more photoresist material, thereby avoiding that the mask layer 9 in the edge area of the display area AA close to the transition zone DUM is thicker in the third direction Z, resulting in the residue of the conductive enhancement layer 5, thereby affecting the aperture ratio of the array substrate 100 and affecting the display effect of the display panel.
  • the insulating layer group 3 and the first electrode layer 4 are both transparent, the insulating layer group 3 and the first electrode layer 4 are not reflected, but the second via hole 41 and the third via hole 42 on the first electrode layer 4, the recessed portion 33 and the first via hole 34 on the insulating layer group 3 are reflected;
  • the first electrode layer 4 is provided on the side of the insulating layer group 3 away from the first base substrate 1, and the second via hole 41 and the third via hole 42 are provided on the first electrode layer 4, the second via hole 41 is located in the display area AA, and the second via hole 41 is connected to the first via hole 34;
  • the orthographic projection of the first via hole 34 on the first base substrate 1 is located within the orthographic projection of the second via hole 41 on the first base substrate 1, for example, the orthographic projection of the second via hole 41 on the first base substrate 1 covers the orthographic projection of the first via hole 34 on the first base substrate 1, and the area of the orthographic projection of the second
  • the third via 42 is located in the transition area DUM, and the third via 42 is connected to the recessed portion 33.
  • the orthographic projection of the recessed portion 33 on the first substrate 1 is located within the orthographic projection of the third via 42 on the first substrate 1.
  • the orthographic projection of the third via 42 on the first substrate 1 covers and is larger than the orthographic projection of the recessed portion 33 on the first substrate 1.
  • the gate layer 22 is omitted in the figure, and the distance (D1' and D3') between the edge line of the orthographic projection of the recessed portion 33 on the first base substrate 1 and the edge line of the orthographic projection of the third via 42 on the first base substrate 1 is greater than or equal to the distance (D1 and D3) between the edge line of the orthographic projection of the first via 34 on the first base substrate 1 and the edge line of the orthographic projection of the second via 41 on the first base substrate 1; D1' and D1 can be the distance in the second direction Y, and D1' is compared with D1; D3' and D3 can be the distance in the first direction X, and D3' is compared with D3. Of course, it can also be D1' compared with D3, and D1 compared with D3'.
  • the orthographic projection of the recessed portion 33 on the first substrate 1 refers to the orthographic projection of the side of the recessed portion 33 facing away from the first substrate 1 on the first substrate 1, that is, the orthographic projection of the top of the recessed portion 33 on the first substrate 1.
  • the orthographic projection of the third via 42 on the first substrate 1 refers to the orthographic projection of the side of the third via 42 facing away from the first substrate 1 on the first substrate 1, that is, the orthographic projection of the top of the third via 42 on the first substrate 1.
  • the orthographic projection of the first via 34 on the first substrate 1 refers to the orthographic projection of the side of the first via 34 facing away from the first substrate 1 on the first substrate 1, that is, the orthographic projection of the top of the first via 34 on the first substrate 1.
  • the orthographic projection of the second via 41 on the first substrate 1 refers to the orthographic projection of the side of the second via 41 facing away from the first substrate 1 on the first substrate 1, that is, the orthographic projection of the top of the second via 41 on the first substrate 1.
  • the orthographic projections of other vias on the first substrate 1 all refer to the orthographic projections of the top on the first substrate 1.
  • the orthographic projection area of the third via hole 42 on the first substrate 1 is greater than or equal to the orthographic projection area of the second via hole 41 on the first substrate 1.
  • the third via hole 42 and the second via hole 41 are set to be rectangles of the same shape, in the first direction X, the length of the third via hole 42 is greater than or equal to the length of the second via hole 41; in the second direction Y, the width of the third via hole 42 is greater than or equal to the width of the second via hole 41.
  • the material of the first electrode layer 4 may be ITO, and the thickness of the first electrode layer 4 may be greater than or equal to 400 angstroms and less than or equal to 700 angstroms.
  • the thickness of the first electrode layer 4 may be 450 angstroms, 550 angstroms, 580 angstroms, 635 angstroms, 674 angstroms, etc.
  • the material of the first electrode layer 4 may also be other transparent conductive materials.
  • the material of the first electrode layer 4 is a transparent conductive material
  • the first electrode layer 4 can be set as a whole layer, which will not affect the transmittance of the array substrate 100, nor will it affect the luminous brightness of the display panel.
  • the resistivity of the transparent conductive material is relatively large, resulting in a large resistance of the first electrode layer 4, which makes the power consumption of the array substrate 100 large and the heat generation serious.
  • a conductive reinforcement layer 5 is provided on the side of the first electrode layer 4 facing away from the first base substrate 1, and the orthographic projection of the conductive reinforcement layer 5 on the first base substrate 1 is located within the orthographic projection of the first electrode layer 4 on the first base substrate 1.
  • the orthographic projection of the first electrode layer 4 on the first base substrate 1 covers and is larger than the orthographic projection of the conductive reinforcement layer 5 on the first base substrate 1.
  • the conductive reinforcement layer 5 may be made of copper, and the thickness of the conductive reinforcement layer 5 may be greater than or equal to 1000 angstroms and less than or equal to 2000 angstroms.
  • the thickness of the conductive reinforcement layer 5 may be 1115 angstroms, 1200 angstroms, 1285 angstroms, 1358 angstroms, 1391 angstroms, 1425 angstroms, 1588 angstroms, 1638 angstroms, 1721 angstroms, 1785 angstroms, 1868 angstroms, 1926 angstroms, 1985 angstroms, etc.
  • the conductive reinforcement layer 5 may also be made of other metal materials such as aluminum and silver.
  • the resistivity of the metal material is relatively small.
  • ashing process When etching the conductive reinforcing material layer 50 to form the conductive reinforcing layer 5, an ashing process is required. The ashing process will cause oxidation corrosion to the conductive reinforcing material layer 50, thereby causing the first electrode material layer 40 to be etched when the conductive reinforcing material layer 50 is etched to form the conductive reinforcing layer 5, resulting in poor disconnection of the first electrode layer 4.
  • a protective layer is provided on the conductive reinforcing layer 5.
  • the protective layer protects the conductive reinforcing material layer 50 to avoid oxidation corrosion of the conductive reinforcing material layer 50 during the ashing process, thereby avoiding etching the first electrode layer 4 when the first electrode material layer 40 is patterned to form the first electrode layer 4, resulting in poor disconnection of the first electrode layer 4.
  • the material of the protective layer can be MoNbTi.
  • the conductive reinforcement layer 5 made of metal is opaque. Therefore, the conductive reinforcement layer 5 cannot be set as a whole layer. Instead, the conductive reinforcement layer 5 is set as much as possible at a position of the array substrate 100 that is originally opaque. In this way, the conductive reinforcement layer 5 can not only reduce the resistance of the first electrode layer 4, but also will not affect the aperture ratio of the array substrate 100.
  • the conductive enhancement layer 5 may include a first conductive strip 51 and a second conductive strip 52; the first conductive strip 51 extends along the first direction X, and the extension direction of the first conductive strip 51 is consistent with the extension direction of the gate line 221; the orthographic projection of the first conductive strip 51 on the first substrate 1 overlaps at least partially with the orthographic projection of the gate line 221 on the first substrate 1, for example, the orthographic projection of the first conductive strip 51 on the first substrate 1 may be located within the orthographic projection of the gate line 221 on the first substrate 1, that is, the width of the first conductive strip 51 in the second direction Y is less than or equal to the width of the gate line 221 in the second direction Y.
  • the number of the first conductive strips 51 may be the same as the number of the gate lines 221, that is, the first conductive strips 51 and the gate lines 221 are in a one-to-one correspondence; or, the number of the first conductive strips 51 may be less than the number of the gate lines 221.
  • the number of the first conductive strips 51 may be set to one, two or more.
  • the number of the second conductive strip 52 can be set to one, in which case the second conductive strip 52 is connected to one end of the first conductive strip 51 in the first direction X.
  • the number of the second conductive strip 52 can be set to two, one of which is connected to one end of the first conductive strip 51 in the first direction X, and the other is cross-connected with the first conductive strip 51.
  • the number of the second conductive strip 52 can be set to multiple, one of which is connected to one end of the first conductive strip 51 in the first direction X, and the rest are cross-connected with the first conductive strip 51.
  • the second conductive strip 52 extends along the second direction Y, and the extension direction of the second conductive strip 52 is consistent with the extension direction of the data line 253.
  • the orthographic projection of the second conductive strip 52 on the first base substrate 1 at least partially overlaps with the orthographic projection of the data line 253 on the first base substrate 1.
  • the orthographic projection of the second conductive strip 52 on the first base substrate 1 may be located within the orthographic projection of the data line 253 on the first base substrate 1, that is, the width of the second conductive strip 52 in the first direction X is less than or equal to the width of the data line 253 in the first direction X.
  • the number of the second conductive strips 52 may be less than the number of the data lines 253.
  • the number of the second conductive strips 52 may also be equal to the number of the data lines 253, that is, the second conductive strips 52 and the data lines 253 are in a one-to-one correspondence.
  • the conductive enhancement layer 5 may further include a plurality of lead lines 53, one end of each of the plurality of lead lines 53 may be connected to the second conductive strip 52, for example, one end of each of the plurality of lead lines 53 may be connected to the outermost second conductive strip 52; the lead line 53 extends along the first direction X toward the side away from the display area AA, and the extension direction of the lead line 53 may be consistent with the extension direction of the gate line 221; the other end of each of the plurality of lead lines 53 may be connected to the edge GOA, which is a row scanning signal line, and is ultimately connected to the binding pin of the peripheral area WW, through which a Com signal may be input, the Com signal being a common electrode signal, and then the Com signal is transmitted to the first electrode layer 4 and the conductive enhancement layer 5 of the display area AA through the plurality of lead lines 53.
  • the edge GOA which is a row scanning signal line, and is ultimately connected to the binding pin of the peripheral area WW, through which a Com signal may be input,
  • the orthographic projection of the lead line 53 on the first substrate 1 does not overlap with the orthographic projection of the gate line 221 on the first substrate 1 , that is, the lead line 53 and the gate line 221 are not arranged opposite to each other but are arranged offset to avoid parasitic capacitance between the lead line 53 and the gate line 221 .
  • the conductive reinforcement layer 5 may further include a summary connection bar 54, which may be connected to one end of the lead bar 53 away from the second conductive bar 52.
  • a summary connection bar 54 which may be connected to one end of the lead bar 53 away from the second conductive bar 52.
  • the summary connection bar 54 extends along the second direction Y, and the extension direction of the summary connection bar 54 may be consistent with the extension direction of the data line 253.
  • Multiple lead bars 53 are connected to the edge GOA through the summary connection bar.
  • the common electrode signal may be first transmitted to the summary connection bar 54, and then transmitted to the lead bar 53 and the first electrode layer 4 through the summary connection bar 54.
  • the spacing D2' between the edge line of the orthographic projection of the third via 42 on the first substrate 1 and the edge line of the orthographic projection of the adjacent first conductive strip 51 on the first substrate 1 is greater than or equal to the spacing D2 between the edge line of the orthographic projection of the second via 41 on the first substrate 1 and the edge line of the orthographic projection of the adjacent first conductive strip 51 on the first substrate 1.
  • the spacing between the edge line of the orthographic projection of the third via 42 on the first substrate 1 and the adjacent first conductive strip 51 is greater than or equal to 0.5 micrometers and less than or equal to 3 micrometers.
  • the spacing between the edge line of the orthographic projection of the second via 41 on the first substrate 1 and the edge line of the orthographic projection of the adjacent first conductive strip 51 on the first substrate 1 is greater than or equal to 2 micrometers and less than or equal to 5.5 micrometers.
  • the spacing D4' between the edge line of the orthographic projection of the third via 42 on the first substrate 1 and the edge line of the orthographic projection of the adjacent second conductive strip 52 on the first substrate 1 is greater than or equal to the spacing D4 between the edge line of the orthographic projection of the second via 41 on the first substrate 1 and the edge line of the orthographic projection of the adjacent second conductive strip 52 on the first substrate 1.
  • the spacing between the edge line of the orthographic projection of the third via 42 on the first substrate 1 and the adjacent second conductive strip 52 is greater than or equal to 0.5 micrometers and less than or equal to 3 micrometers.
  • the spacing between the edge line of the orthographic projection of the second via 41 on the first substrate 1 and the edge line of the orthographic projection of the adjacent second conductive strip 52 on the first substrate 1 is greater than or equal to 2 micrometers and less than or equal to 5.5 micrometers.
  • Such arrangement makes the distance between the second via hole 41 and the first conductive strip 51 and the second conductive strip 52 larger. Even if there are errors in the preparation process for forming the first conductive strip 51 and the second conductive strip 52, and the alignment accuracy fluctuates, the first conductive strip 51 and the second conductive strip 52 will not be formed in the second via hole 41, so that the first conductive strip 51 and the second conductive strip 52 will not be broken due to crossing the second via hole 41, and the pattern of the conductive reinforcement layer 5 and the first electrode 4 will not be abnormal due to the residue of the mask layer material in the second via hole 41. In addition, the defect of the first electrode 4 being short-circuited due to contact with the second electrode 71 caused by the residue of the first electrode 4 can be avoided.
  • the distance between the third via 42 and the first conductive strip 51 and the second conductive strip 52 is made larger. Even if there are errors in the preparation process for forming the first conductive strip 51 and the second conductive strip 52, and the alignment accuracy fluctuates, the first conductive strip 51 and the second conductive strip 52 will not be formed in the third via 42, so that the first conductive strip 51 and the second conductive strip 52 will not be broken due to crossing the third via 42, and the pattern of the conductive reinforcement layer 5 and the first electrode 4 will not be abnormal due to the residue of the mask layer material in the third via 42. In addition, the defect of the first electrode 4 being short-circuited due to contact with the second electrode 71 caused by the residue of the first electrode 4 can be avoided.
  • the recessed portion 33 and the first via hole 34 in a row of pixel regions 26 arranged along the first direction X are located in substantially the same region in the corresponding pixel region 26.
  • the recessed portion 33 and the first via hole 34 in the first row of pixel regions 26 are both located at the upper left corner of the pixel region 26, and the recessed portion 33 and the first via hole 34 in the second row of pixel regions 26 are both located at the upper right corner of the pixel region 26.
  • the recessed portion 33 and the first via hole 34 in a row of pixel regions 26 arranged along the second direction Y may also be located at substantially the same position in the pixel region 26.
  • a second insulating layer 6 is provided on the side of the conductive reinforcement layer 5 away from the first base substrate 1 , and the second insulating layer 6 is formed in the seventh via hole 322 on the organic insulating layer 32 to form a recessed structure.
  • a fourth via 61 is provided on the second insulating layer 6, and the orthographic projection of the seventh via 322 on the first base substrate 1 covers and is larger than the orthographic projection of the fourth via 61 on the first base substrate 1, that is, the fourth via 61 is connected to the seventh via 322, and the seventh via 322 on the organic insulating layer 32 is larger than the fourth via 61 on the second insulating layer 6, so that the second insulating layer 6 not only covers the side walls of the seventh via 322, but also covers the part of the first insulating layer 31 in the seventh via 322 that is not covered by the organic insulating layer 32, that is, the fourth via 61 does not completely occupy the bottom wall of the recessed structure, so that the second insulating layer 6 forms a step portion 62 in the seventh via 322, or it can be said that the step portion 62 is the residue of the second insulating layer 6 on the bottom wall of the seventh via 322.
  • a second electrode layer 7 is provided on the side of the second insulating layer 6 away from the first base substrate 1, and the second electrode 71 may be a pixel electrode.
  • the second electrode layer 7 includes a plurality of second electrodes 71, and the second electrode 71 includes a main body portion 711 and a connecting portion 712 connected to each other, and the connecting portion 712 is connected to the drain 243 of the switch unit 21 through the fourth via hole 61 and the fifth via hole 311, that is, the portion located in the fourth via hole 61 and the fifth via hole 311 is the connecting portion 712; and the main body portion 711 is located on the side of the step portion 62 away from the first base substrate 1, or it can be said that the main body portion 711 is located on the side of the fourth via hole 61 where the step portion 62 is provided, that is, a portion of the second insulating layer 6 that is located on the side away from the first base substrate 1 and close to the step portion 62 is the main body portion 711.
  • the second insulating layer 6 covering the side wall of the seventh via hole 322 close to the step portion 62 will not be etched, so that the second insulating layer 6 forms a complete protection for the organic insulating layer 32, and will not etch the organic insulating layer 32, and will not form a cavity 323 on the organic insulating layer 32, and the subsequently formed second electrode 71 will not cover the cavity 323, and the second electrode 71 will not have the risk of breaking or falling off; as shown in FIG.
  • the second insulating layer 6 covering the side wall of the seventh via hole 322 close to the step portion 62 will not be etched, so that the second insulating layer 6 forms a complete protection for the organic insulating layer 32, and will not etch the organic insulating layer 32, and will not form a cavity 323 on the organic insulating layer 32, and the subsequently formed second electrode 71 will not cover the cavity 323, and the second electrode 71 will not have the risk of breaking or falling off.
  • the four via holes 61 are offset to the other side where the step portion 62 does not need to be formed.
  • the second insulating layer 6 When the second insulating layer 6 is etched, the second insulating layer 6 on the other side covering the side wall of the seventh via hole 322 will be etched, so that the second insulating layer 6 will not form a complete protection for the organic insulating layer 32, and the organic insulating layer 32 will be etched, and a cavity 323 will be formed in the organic insulating layer 32.
  • a part of the second electrode 71 formed subsequently will cover the cavity 323, but because the main body 711 is not covered at the cavity 323, the main body 711 will not have the risk of breaking or falling off; moreover, it will not affect the connection between the main body 711 and the connecting portion 712, and will not affect the transmission of signals from the drain connecting lead 252 to the second electrode 71.
  • the material of the second insulating layer 6 may be an inorganic material, for example, silicon nitride, silicon oxide, etc.
  • the thickness of the second insulating layer 6 is greater than or equal to 100 nm and less than or equal to 500 nm.
  • the second electrode 71 may be made of ITO, and the thickness of the second electrode 71 may be greater than or equal to 400 angstroms and less than or equal to 700 angstroms.
  • the thickness of the first electrode may be 450 angstroms, 550 angstroms, 580 angstroms, 635 angstroms, 674 angstroms, etc.
  • the second electrode 71 may also be made of other transparent conductive materials.
  • a second electrode 71 can be set on the side of the organic insulating layer 32 away from the base substrate.
  • the second electrode 71 can be a pixel electrode.
  • the second electrode 71 is connected to the drain 243 through the fifth via 311 on the first insulating layer 31 and the seventh via 322 on the organic insulating layer 32; a second insulating layer 6 is set on the side of the second electrode 71 away from the base substrate; the first electrode layer 4 and the conductive reinforcement layer 5 are sequentially stacked on the side of the second insulating layer 6 away from the base substrate; the specific structures of the first electrode layer 4 and the conductive reinforcement layer 5 have been described in detail above, so they will not be repeated here.
  • At least two recessed portions 33 are provided in a pixel area 26 of the transition zone DUM, for example, two, three or more recessed portions 33 may be provided in a pixel area 26 of the transition zone DUM; and at least two third via holes 42 are provided, for example, two, three or more third via holes 42 may be provided in a pixel area 26 of the transition zone DUM; the third via holes 42 are in one-to-one correspondence with the recessed portions 33, and the number of the third via holes 42 is the same as the number of the recessed portions 33.
  • the distance D5 between two adjacent recessed portions 33 in the same pixel region 26 is greater than or equal to 4 micrometers, and the distance D6 between two adjacent third via holes 42 in the same pixel region 26 is greater than or equal to 2 micrometers.
  • the spacing between two adjacent recessed portions 33 and the spacing between two adjacent third via holes 42 are set according to the accuracy of the equipment to avoid two adjacent recessed portions 33 being connected to form one recessed portion 33 and to avoid two adjacent third via holes 42 being connected to form one third via hole 42. Therefore, when the accuracy of the equipment is high, the spacing between two adjacent recessed portions 33 and the spacing between two adjacent third via holes 42 can be set to be smaller.
  • a first via hole 34 and a second via hole 41 are disposed in a pixel region 26 of the display area AA, that is, the specific structure of the display area AA is the same as that of the above exemplary embodiment, which will not be described again.
  • the array substrate 100 may further include a first spacer 81 .
  • the first spacer 81 is disposed on a side of the second electrode layer 7 away from the first base substrate 1 .
  • the first spacer 81 can be set to a quadrangular pyramid structure, that is, the cross section of the first spacer 81 parallel to the first base substrate 1 is a rectangle, and the area of the bottom surface close to the first base substrate 1 is larger than the area of the top surface away from the first base substrate 1.
  • the first spacer 81 is located between two adjacent switch units 21; the length direction of the first spacer 81 is consistent with the extension direction of the data line 253, and the orthographic projection of the first spacer 81 on the first base substrate 1 overlaps with the orthographic projection of the data line 253 on the first base substrate 1, that is, the first spacer 81 and the data line 253 are arranged opposite to each other.
  • the positive projection of the first conductive strip 51 of the conductive enhancement layer 5 on the first base substrate 1 is set as a curve.
  • the curve may include multiple straight lines and multiple arcs, and the straight lines and arcs are alternately arranged and connected to each other.
  • the first conductive strip 51 is bent toward the side away from the first spacer 81 at a position adjacent to the first spacer 81, that is, the arc is bent toward the side away from the first spacer 81, and the bending depth H is greater than or equal to 2 microns and less than or equal to 3 microns.
  • the bending depth H can be 2.5 microns.
  • the bending depth H is the maximum distance between the arc and the straight line.
  • the specific value of the bending depth H can be specifically set according to the equipment and process accuracy.
  • the position where the first conductive strip 51 is bent is generally the position where it intersects with the data line 253.
  • the first conductive strip 51 may include a first straight portion 511 and a first curved portion 512
  • the orthographic projection of the first straight portion 511 on the first substrate substrate 1 is located within the orthographic projection of the gate line 221 on the first substrate substrate 1
  • the orthographic projection of the first curved portion 512 on the first substrate substrate 1 at least partially does not overlap with the orthographic projection of the gate line 221 on the first substrate substrate 1, that is, the orthographic projections of the two ends of the first curved portion 512 connected to the first straight portion 511 on the first substrate substrate 1 are located within the orthographic projection of the gate line 221 on the first substrate substrate 1, but the orthographic projection of the middle portion of the first curved portion 512 on the first substrate substrate 1 does not overlap with the orthographic projection of the gate line 221 on the first substrate substrate 1.
  • the first conductive strip 51 After the first conductive strip 51 is bent, space is reserved for the first spacer 81. Since the first spacer 81 is used to support the color film substrate 200, a relatively flat supporting plane needs to be set. Therefore, a relatively flat base plane needs to be provided for the first spacer 81. The first conductive strip 51 will cause the base plane for setting the first spacer 81 to be uneven. After the first conductive strip 51 is bent, the first spacer 81 does not need to be set on the side of the first conductive strip 51 away from the first base substrate 1, so as to provide a relatively flat base plane for the first spacer 81.
  • the first conductive strip 51 may not avoid the first spacer 81 , so that the orthographic projection of the first conductive strip 51 on the first base substrate 1 overlaps with the orthographic projection of the first spacer 81 on the first base substrate 1 .
  • the minimum distance K1 between the first spacer 81 and the first conductive strip 51 is greater than or equal to 2 microns and less than or equal to 4 microns.
  • the specific value of the minimum distance between the first spacer 81 and the first conductive strip 51 can be specifically set according to the equipment and process accuracy. Avoid the first spacer 81 being arranged on the side of the first conductive strip 51 away from the first base substrate 1 when errors occur in the process or equipment, resulting in an uneven base surface of the first spacer 81.
  • both the first spacer 81 and the first conductive strip 51 need to be shielded by the black matrix 202, so as to minimize the area of the black matrix 202 and improve the aperture ratio.
  • curves are not necessarily all composed of arcs, but may also be in the form of a broken line formed by a plurality of straight lines, or may be a mixture of straight lines and arcs.
  • the curved first conductive strip 51 has sufficient extension margin, which can effectively avoid the first conductive strip 51 from being broken.
  • the distance between the edge line of the recessed portion 33 on the side close to the display area AA and the display area AA is greater than the distance between the edge line of the recessed portion 33 on the side close to the peripheral area WW and the peripheral area WW. That is, the recessed portion 33 is closer to the peripheral area WW, which facilitates the material of the mask layer of the peripheral area WW to flow into the recessed portion 33, and avoids the material of the mask layer of the display area AA from flowing into the recessed portion 33 as much as possible, resulting in a thinning of the thickness of the mask layer of the display area AA.
  • the exemplary embodiment of the present disclosure further provides a method for preparing an array substrate 100.
  • the method for preparing the array substrate 100 may include the following steps:
  • Step S10 providing a first base substrate, wherein the first base substrate has a display area and a transition area arranged on at least one side of the display area, forming an insulating layer group on one side of the first base substrate, forming a recessed portion on the insulating layer group, and the recessed portion is located in the transition area.
  • Step S20 forming a first electrode material layer and a conductive reinforcement material layer in sequence on a side of the insulating layer group facing away from the first substrate.
  • Step S30 forming a mask layer on a side of the conductive reinforcing material layer away from the first base substrate, wherein a portion of the mask layer is formed in the recessed portion, and a thickness of the mask layer in the display area is uniform.
  • Step S40 patterning the first electrode material layer using the mask layer as a mask to form a first electrode layer, and patterning the conductive enhancement material layer to form a conductive enhancement layer.
  • a first substrate 1 is provided.
  • the first substrate 1 has a display area AA and a transition area DUM provided on at least one side of the display area AA.
  • the display area AA of the first substrate 1 is also the display area AA of the array substrate 100, and the transition area DUM of the first substrate 1 is also the transition area DUM of the array substrate 100.
  • the first substrate 1 also has a peripheral area WW, and the peripheral area WW of the first substrate 1 is also the peripheral area WW of the array substrate 100.
  • a gate layer 22 is formed on one side of the first base substrate 1, and the gate layer 22 may include a gate 222 and a gate line 221; a gate insulating layer 23 is formed on the side of the gate layer 22 away from the first base substrate 1; an active layer 24 is formed on the side of the gate insulating layer 23 away from the first base substrate 1, and the active layer 24 may include a channel portion 241, a source 242 and a drain 243, and the source 242 and the drain 243 are connected to opposite sides of the channel portion 241; a connecting conductor layer 25 is formed on the side of the active layer 24 away from the first base substrate 1, and the connecting conductor layer 25 may include a plurality of source connecting leads 251, a plurality of drain connecting leads 252 and a plurality of data lines 253.
  • a first insulating layer 31 and an organic insulating layer 32 are sequentially formed on the side of the connecting conductor layer 25 away from the first base substrate 1, and the organic insulating layer 32 is patterned to form a sixth via hole 321 and a seventh via hole 322, wherein the seventh via hole 322 is located in the display area AA, and the sixth via hole 321 is located in the transition area DUM; the material of the organic insulating layer 32 can be photoresist, and when forming the sixth via hole 321 and the seventh via hole 322 on the organic insulating layer 32, only exposure and development are required, and etching is not required, and the process is relatively simple.
  • the sixth via hole 321 forms a recessed portion 33.
  • the orthographic projection area of the first via hole 34 on the first base substrate 1 is smaller than or equal to the orthographic projection area of the recessed portion 33 on the first base substrate 1 .
  • a first electrode material layer 40 can be formed by sputtering on the side of the insulating layer group 3 away from the first base substrate 1, and a conductive reinforcement material layer 50 can be formed by sputtering on the side of the first electrode material layer 40 away from the first base substrate 1; the first electrode material layer 40 and the conductive reinforcement material layer 50 will both be formed in the first via hole 34 and the recessed portion 33, and the first electrode material layer 40 in the first via hole 34 is connected to the drain 243, but the first electrode material layer 40 ultimately forms a common electrode, which does not need to be connected to the drain 243. Therefore, the first electrode material layer 40 needs to be patterned, and the conductive reinforcement material layer 50 is made of metal, which is opaque. To avoid the conductive reinforcement material layer 50 affecting the transmittance of the array substrate 100, the conductive reinforcement material layer 50 also needs to be patterned.
  • a mask layer 9 is formed on the side of the conductive reinforcement material layer 50 away from the first base substrate 1 through a coating or printing process. Since the material of the mask layer 9 has a certain fluidity, it will flow from the area with higher height to the area with lower height. Since the peripheral area WW is provided with a large area of peripheral leads 233, the height of the peripheral area WW is higher than the height of the display area AA and the height of the transition area DUM. Therefore, the material of the mask layer 9 will flow from the peripheral area WW to the transition area DUM and the display area AA, resulting in a thicker thickness of the mask layer 9 in the edge area of the display area AA close to the transition area DUM.
  • the material of the mask layer 9 flows from the peripheral area WW to the transition area DUM, and then flows into the recess 33, thereby preventing the material of the mask layer 9 from further flowing to the display area AA, so that the thickness of the mask layer 9 in the display area AA is consistent, and preventing the thickness of the mask layer 9 in the edge area of the display area AA close to the transition area DUM from being thicker.
  • a mask plate is placed on the side of the mask layer 9 away from the base substrate, and the mask plate may include a light-transmitting portion, a light-shielding portion, and a semi-light-transmitting portion;
  • the semi-light-transmitting portion is arranged opposite to the second portion 912, that is, the orthographic projection of the semi-light-transmitting portion on the base substrate coincides with the orthographic projection of the second portion 912 on the base substrate;
  • the light-shielding portion is arranged opposite to the first portion 911, that is, the orthographic projection of the light-shielding portion on the base substrate coincides with the orthographic projection of the first portion 911 on the base substrate.
  • the light-transmitting portion is arranged opposite to other portions of the mask layer 9.
  • the mask layer 9 is exposed and developed to form a mask pattern 91, and the mask layer 9 disposed opposite to the light-transmitting portion is removed to form a ninth via hole 913, which exposes part of the conductive reinforcing material layer 50; a certain thickness of the mask layer 9 disposed opposite to the semi-light-transmitting portion is removed to form a second portion 912; the mask layer 9 disposed opposite to the light-shielding portion is completely retained to form a first portion 911, so that the thickness of the first portion 911 is greater than the thickness of the second portion 912. Moreover, since the overall thickness of the display area AA of the mask layer 9 is relatively uniform, the second portion 912 shown in FIG. 2 will not be thick.
  • the portion of the conductive reinforcing material layer 50 opposite to the ninth via hole 913 is etched away, that is, the exposed conductive reinforcing material layer 50 is etched for the first time, and the conductive reinforcing material layer 50 covered by the mask pattern 91 is retained.
  • the mask pattern 91 is ashed to remove the second portion 912, so that the conductive reinforcing material layer 50 covered by the second portion 912 is exposed, and the gas used in the ashing process may include SF6 and O2.
  • the second portion 912 is removed by the ashing process, so that the conductive reinforcing material layer 50 covered by the second portion 912 is exposed, and the thickness of the first portion 911 is also reduced.
  • the overall thickness of the display area AA of the mask layer 9 is relatively uniform, the situation shown in FIG. 4 where a portion of the second portion 912 remains will not occur.
  • a portion of the first electrode material layer 40 opposite to the ninth via hole 913 is etched away to form the first electrode layer 4; specifically, the first electrode material layer 40 is etched using the first portion 911 and the conductive reinforcement material layer 50 as a mask to form the first electrode layer 4, that is, the first electrode material layer 40 is etched on the first electrode layer 4 to form a second via hole 41 and a third via hole 42.
  • the remaining conductive enhancement material layer 50 is patterned to form a conductive enhancement layer 5, specifically, the conductive enhancement material layer 50 is etched using the first portion 911 as a mask to form the conductive enhancement layer 5.
  • the orthographic projection of the conductive enhancement layer 5 on the substrate overlaps with the orthographic projection of the gate line 221 on the substrate, specifically, the orthographic projection of the conductive enhancement layer 5 on the substrate is located within the orthographic projection of the gate line 221 on the substrate, that is, the extension direction of the conductive enhancement layer 5 is consistent with the extension direction of the gate line 221, and the width of the conductive enhancement layer 5 is slightly smaller than the width of the gate line 221.
  • the width of the conductive enhancement layer 5 is about 3.5 microns, and the width of the gate line 221 is about 4.5 microns. Since the conductive enhancement layer 5 is made of metal material, it is opaque and reflective. Therefore, in order to avoid its reflection and affecting the display effect, it needs to be shielded by the black matrix 202. The gate line 221 is also shielded by the black matrix 202.
  • the orthographic projection of the conductive enhancement layer 5 on the base substrate is located within the orthographic projection of the gate line 221 on the base substrate, which can avoid increasing the width of the black matrix 202 and thus avoid reducing the aperture ratio.
  • the overall thickness of the display area AA of the mask layer 9 is relatively uniform, the situation where a portion of the conductive reinforcement layer 5 remains as shown in FIG. 6 will not occur, that is, the situation where the width of the conductive reinforcement layer 5 is relatively wide as shown in FIG. 6 will not occur.
  • the remaining mask layer 9 is removed, that is, the remaining first portion 911 is peeled off.
  • a second insulating layer 6 is formed on the side of the conductive reinforcement layer 5 away from the first substrate 1 , and the second insulating layer 6 and the first insulating layer 31 are etched by the same patterning process to form a fifth via 311 in the first insulating layer 31 and a fourth via 61 in the second insulating layer 6 .
  • a second electrode material layer is formed on a side of the second insulating layer 6 away from the first base substrate 1 , and the second electrode material layer is patterned to form a plurality of second electrodes 71 .
  • the exemplary embodiment of the present disclosure also provides a display panel, as shown in FIG. 28 , the display panel may include an array substrate 100 and a color filter substrate 200; the array substrate 100 is any of the array substrates 100 described above; the specific structure of the array substrate 100 has been described in detail above, so it will not be repeated here.
  • the color filter substrate 200 is arranged opposite to the array substrate 100, and the color filter substrate 200 may include a black matrix 202, and the orthographic projection of the conductive enhancement layer 5 on the first base substrate 1 is located within the orthographic projection of the black matrix 202 on the first base substrate 1.
  • the color film substrate 200 may further include a second base substrate 201, a plurality of filter portions 203 and a black matrix 202 provided on one side of the second base substrate 201, and the plurality of filter portions 203 are arranged in an array on one side of the second base substrate 201; the plurality of filter portions 203 may include a red filter portion 203, a blue filter portion 203, and a green filter portion 203.
  • a second spacer 82 is provided on one side of the color filter substrate 200 close to the array substrate 100.
  • the second spacer 82 can also be set to a long strip shape. After the box is assembled, the second spacer 82 contacts the first spacer 81 and forms a cross structure. The second spacer 82 and the first spacer 81 support the color filter substrate 200 together to provide a storage space for the liquid crystal.
  • the thick black dotted line in the figure is the edge line of the black matrix 202.
  • the edge line of the black matrix 202 on one side close to the first conductive strip 51 is set to a curve adapted to the first conductive strip 51, so that the black matrix 202 can block the first conductive strip 51 without increasing too much opaque area, thereby ensuring the transmittance and brightness of the display panel.
  • the orthographic projection of the first spacer 81 on the first base substrate 1 is located within the orthographic projection of the black matrix 202 on the first base substrate 1, so that the black matrix 202 shields the first spacer 81; and the minimum distance K2 between the edge line of the orthographic projection of the first spacer 81 on the first base substrate 1 and the edge line of the orthographic projection of the black matrix 202 on the first base substrate 1 is greater than or equal to 2 microns and less than or equal to 4 microns, so as to avoid the black matrix 202 being unable to shield the first spacer 81 when errors occur in the process or equipment.
  • the orthographic projection of the first conductive strip 51 on the first substrate 1 is located within the orthographic projection of the black matrix 202 on the first substrate 1, so that the black matrix 202 shields the first conductive strip 51; the minimum distance K3 between the edge line of the orthographic projection of the first conductive strip 51 on the first substrate 1 and the edge line of the orthographic projection of the black matrix 202 on the first substrate 1 is greater than or equal to 2 micrometers and less than or equal to 4 micrometers, so as to avoid the black matrix 202 being unable to shield the first conductive strip 51 when errors occur in the process or equipment.
  • both the first spacers 81 and the first conductive strips 51 need to be shielded by the black matrix 202 to minimize the area of the black matrix 202 and increase the aperture ratio.
  • the orthographic projection of the second conductive strip 52 on the first substrate 1 is located within the orthographic projection of the black matrix 202 on the first substrate 1 , so that the black matrix 202 shields the second conductive strip 52 .
  • the exemplary embodiment of the present disclosure further provides a display device, which may include the display panel described above.
  • a display panel which may include the display panel described above.
  • the specific structure of the display panel has been described in detail above, so it will not be repeated here.
  • the specific type of the display device is not particularly limited, and any type of display device commonly used in the field can be used, such as mobile devices such as mobile phones, wearable devices such as watches, VR devices, etc. Technical personnel in this field can make corresponding choices based on the specific purpose of the display device, which will not be repeated here.
  • the display device in addition to the display panel, the display device also includes other necessary components and components, such as a housing, a circuit board, a power cord, etc. Taking the display as an example, technical personnel in this field can make corresponding supplements according to the specific use requirements of the display device, which will not be repeated here.
  • the beneficial effects of the display device provided by the exemplary embodiment of the present disclosure are the same as the beneficial effects of the array substrate 100 provided by the above exemplary embodiment, and are not described in detail herein.

Landscapes

  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板及其制备方法、显示面板、显示装置；该阵列基板(100)具有显示区(AA)和设于显示区(AA)至少一侧的过渡区(DUM)，该阵列基板(100)包括第一衬底基板(1)、绝缘层组(3)、第一电极层(4)以及导电增强层(5)；绝缘层组(3)设于第一衬底基板(1)的一侧，绝缘层组(3)上设置有凹陷部(33)，凹陷部(33)位于过渡区(DUM)；第一电极层(4)设于绝缘层组(3)背离第一衬底基板(1)的一侧；导电增强层(5)设于第一电极层(4)背离第一衬底基板(1)的一侧，导电增强层(5)在第一衬底基板(1)上的正投影位于第一电极层(4)在第一衬底基板(1)上的正投影内。该阵列基板(100)显示区(AA)各处的透光率基本一致。

Description

阵列基板及其制备方法、显示面板、显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种阵列基板及其制备方法、显示面板、显示装置。
背景技术
近年来，用户对显示画质的要求越来越高，使得现有显示产品的显示画质无法满足用户的要求。
发明内容
本公开的目的在于克服上述现有技术的不足，提供一种阵列基板及其制备方法、显示面板、显示装置。
根据本公开的一个方面，提供了一种阵列基板，具有显示区和设于所述显示区至少一侧的过渡区，所述阵列基板包括：
第一衬底基板；
绝缘层组，设于所述第一衬底基板的一侧，所述绝缘层组上设置有凹陷部，所述凹陷部位于所述过渡区；
第一电极层，设于所述绝缘层组背离所述第一衬底基板的一侧；
导电增强层，设于所述第一电极层背离所述第一衬底基板的一侧，所述导电增强层在所述第一衬底基板上的正投影位于所述第一电极层在所述第一衬底基板上的正投影内。
在本公开的一种示例性实施例中，所述绝缘层组上还设置有第一过孔，所述第一过孔位于所述显示区，所述第一过孔在所述第一衬底基板上的正投影面积等于或小于所述凹陷部在所述第一衬底基板上的正投影面积。
在本公开的一种示例性实施例中，所述第一电极层上设置有第二过孔和第三过孔，所述第二过孔位于所述显示区，所述第三过孔位于所述过渡区，所述凹陷部在所述第一衬底基板上的正投影位于所述第三过孔在所述第一衬底基板上的正投影之内，所述第一过孔在所述第一衬底基板上的正投影位于所述第二过孔在所述第一衬底基板上的正投影之内。
在本公开的一种示例性实施例中，所述第三过孔在所述第一衬底基板上的正投影面积大于或等于所述第二过孔在所述第一衬底基板上的正投影面积。
在本公开的一种示例性实施例中，所述凹陷部在所述第一衬底基板上的正投影的边沿线与所述第三过孔在所述第一衬底基板上的正投影的边沿线之间的间距，大于或等于所述第一过孔在所述第一衬底基板上的正投影的边沿线与所述第二过孔在所述第一衬底基板上的正投影的边沿线之间的间距。
在本公开的一种示例性实施例中，所述导电增强层包括：
第一导电条，沿第一方向延伸；
第二导电条，沿第二方向延伸，所述第二方向与所述第一方向相交，所述第一方向和所述第二方向与所述第一衬底基板靠近所述绝缘层组的一面平行。
在本公开的一种示例性实施例中，所述第三过孔在所述第一衬底基板上的正投影的边沿线与相邻的所述第一导电条在所述第一衬底基板上的正投影的边沿线之间的间距，大于或等于所述第二过孔在所述第一衬底基板上的正投影的边沿线与相邻的所述第一导电条在所述第一衬底基板上的正投影的边沿线之间的间距；所述第三过孔在所述第一衬底基板上的正投影的边沿线与相邻的所述第二导电条在所述第一衬底基板上的正投影的边沿线之间的间距，大于或等于所述第二过孔在所述第一衬底基板上的正投影的边沿线与相邻的所述第二导电条在所述第一衬底基板上的正投影的边沿线之间的间距。
在本公开的一种示例性实施例中，所述阵列基板还包括：
开关层组，设于所述第一衬底基板与所述绝缘层组之间，所述开关层组包括：
多个开关单元，呈阵列排布；
多根栅线，沿所述第一方向延伸，各个所述栅线位于相邻两个所述开关单元之间，所述第一导电条在所述第一衬底基板上的正投影与所述栅线在所述第一衬底基板上的正投影至少部分交叠；
多根数据线，沿所述第二方向延伸，各个所述数据线位于相邻两个所述开关单元之间，所述第二导电条在所述第一衬底基板上的正投影与所述数据线在所述第一衬底基板上的正投影至少部分交叠，多根所述栅线与多根所述数据线交叉形成多个像素区域。
在本公开的一种示例性实施例中，在所述过渡区的一个所述像素区域内设置有至少两个所述凹陷部，且设置有至少两个所述第三过孔；在所述显示区的一个所述像素区域内设置有一个所述第一过孔，且设置有一个所述第二过孔。
在本公开的一种示例性实施例中，位于沿所述第一方向排列的一行所述像素区域内的所述凹陷部和所述第一过孔位于对应所述像素区域内的相同区域。
在本公开的一种示例性实施例中，在所述显示区的所述第二方向的一侧所述过渡区内设置有沿所述第一方向排列的仅一行所述像素区域，在所述显示区的所述第一方向的一侧所述过渡区内设置有沿所述第二方向排列的仅一列所述像素区域。
在本公开的一种示例性实施例中，在所述过渡区，所述开关单元不包括漏极以及漏极连接引线，所述凹陷部在所述第一衬底基板上的正投影与所述开关单元无交叠。
在本公开的一种示例性实施例中，所述凹陷部的最低处与所述第一衬底基板之间的距离小于所述第一过孔的最低处与所述第一衬底基板之间的距离。
在本公开的一种示例性实施例中，所述导电增强层还包括：
多根引线条，所述引线条的一端连接于所述第二导电条，所述引线条沿所述第一方向朝向背离所述显示区的一侧延伸。
在本公开的一种示例性实施例中，所述引线条在所述第一衬底基板上的正投影与所述栅线 在所述第一衬底基板上的正投影无交叠。
在本公开的一种示例性实施例中，相邻两根所述第二导电条在所述第一衬底基板上的正投影之间设置有两根所述数据线。
在本公开的一种示例性实施例中，所述导电增强层还包括：
汇总连接条，连接于所述引线条背离所述第二导电条的一端，所述汇总连接条沿所述第二方向延伸。
在本公开的一种示例性实施例中，所述绝缘层组包括：
第一绝缘层，设于所述第一衬底基板的一侧，所述第一绝缘层上设置有第五过孔，所述第五过孔位于所述显示区，且连通至所述开关单元；
有机绝缘层，设于所述第一绝缘层背离所述第一衬底基板的一侧，所述有机绝缘层上设置有第六过孔和第七过孔，所述第六过孔为所述凹陷部，所述第七过孔与所述第五过孔连通形成所述第一过孔。
在本公开的一种示例性实施例中，所述阵列基板还包括：
第二绝缘层，设于所述导电增强层背离所述第一衬底基板的一侧，所述第二绝缘层上设置有第四过孔，所述第七过孔在所述第一衬底基板上的正投影覆盖且大于所述第四过孔在所述第一衬底基板上的正投影，所述第二绝缘层覆盖所述第七过孔的孔侧壁，且覆盖在所述第七过孔内裸露的部分所述第一绝缘层，以使所述第二绝缘层在所述第七过孔内形成台阶部；
第二电极层，设于所述第二绝缘层背离所述第一衬底基板的一侧，所述第二电极层包括多个第二电极，所述第二电极包括相互连接的本体部和连接部，所述连接部通过所述第四过孔以及所述第五过孔连接至所述开关单元，所述本体部位于所述台阶部背离所述第一衬底基板的一侧。
在本公开的一种示例性实施例中，所述阵列基板还包括：
第一隔垫物，设于所述第二电极层的背离所述第一衬底基板的一侧，且位于相邻两个开关单元之间；
所述第一导电条在所述第一衬底基板上的正投影设置为曲线，所述第一导电条在与所述第一隔垫物相邻的位置向远离所述第一隔垫物一侧折弯。
在本公开的一种示例性实施例中，所述第一导电条在所述第一衬底基板上的正投影与所述第一隔垫物在所述第一衬底基板上的正投影无交叠。
在本公开的一种示例性实施例中，所述第一导电条包括第一直线部和第一弯曲部，所述第一直线部在所述第一衬底基板上的正投影位于所述栅线在所述第一衬底基板上的正投影内，所述第一弯曲部在所述第一衬底基板上的正投影至少部分与所述栅线在所述第一衬底基板上的正投影不交叠。
在本公开的一种示例性实施例中，所述阵列基板还具有外围区，所述外围区设于所述过渡区背离所述显示区的一侧，在所述外围区设置有多根外围引线，在第三方向上，所述绝缘层组在所述外围区的高度高于所述绝缘层组在所述显示区的高度，所述第三方向与所述第一衬底基 板靠近所述绝缘层组的一面垂直。
在本公开的一种示例性实施例中，所述凹陷部靠近所述显示区一侧的边沿线与显示区之间的距离大于，所述凹陷部靠近所述外围区一侧的边沿线与所述外围区之间的距离。
在本公开的一种示例性实施例中，所述导电增强层在所述第一衬底基板上的正投影与所述凹陷部在所述第一衬底基板上的正投影无交叠。
在本公开的一种示例性实施例中，所述阵列基板还包括：
保护层，设于所述导电增强层背离所述第一衬底基板的一侧。
根据本公开的另一个方面，提供了一种阵列基板的制备方法，包括：
提供第一衬底基板，所述第一衬底基板具有显示区和设于显示区至少一侧的过渡区，在所述第一衬底基板的一侧形成绝缘层组，在所述绝缘层组上形成凹陷部，所述凹陷部位于所述过渡区；
在所述绝缘层组背离所述第一衬底基板的一侧依次形成第一电极材料层和导电增强材料层；
在所述导电增强材料层背离所述第一衬底基板的一侧形成掩模层，部分所述掩模层形成在所述凹陷部内，所述显示区的所述掩模层的厚度一致；
以所述掩模层为掩模对所述第一电极材料层进行图案化处理形成第一电极层，且对所述导电增强材料层进行图案化处理形成导电增强层。
在本公开的一种示例性实施例中，在形成所述凹陷部的同时，在所述绝缘层组上形成第一过孔，所述第一过孔位于所述显示区，所述第一过孔在所述第一衬底基板上的正投影面积等于或小于所述凹陷部在所述第一衬底基板上的正投影面积。
在本公开的一种示例性实施例中，以所述掩模层为掩模对所述第一电极材料层进行图案化处理形成第一电极层，且对所述导电增强材料层进行图案化处理形成导电增强层，包括：
对所述掩模层进行半掩模工艺形成掩模图案，所述掩模图案包括第一部分和第二部分，所述第一部分的厚度大于所述第二部分的厚度，所述第二部分上形成有第九过孔，一部分所述第九过孔与所述第一过孔相对设置，另一部分所述第九过孔与所述凹陷部相对设置；
对与所述第九过孔相对的部分所述导电增强材料层进行刻蚀去除；
对所述掩模图案进行灰化处理，以去除所述第二部分，使所述第二部分覆盖的所述导电增强材料层裸露；
对与所述第九过孔相对的部分所述第一电极材料层进行刻蚀去除，形成所述第一电极层；
对剩余的所述导电增强材料层进行图案化处理形成导电增强层。
根据本公开的又一个方面，提供了一种显示面板，包括：
阵列基板，是上述任意一项所述的阵列基板；
彩膜基板，与所述阵列基板相对设置，所述彩膜基板包括黑矩阵，导电增强层在第一衬底基板上的正投影位于所述黑矩阵在第一衬底基板上的正投影内。
根据本公开的另一个方面，提供了一种显示面板，包括：
阵列基板，是上述任意一项所述的阵列基板；
彩膜基板，与所述阵列基板相对设置，所述彩膜基板包括黑矩阵，导电增强层在第一衬底基板上的正投影位于所述黑矩阵在第一衬底基板上的正投影内，所述黑矩阵靠近第一导电条的一侧边沿线设置为与所述第一导电条相适配的曲线。
根据本公开的再一个方面，提供了一种显示装置，其中，包括：上述所述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1-图7为掩模层较厚的情况下形成导电增强层的各个步骤的结构示意图。
图8为本公开阵列基板第一示例实施方式的结构示意图。
图9为本公开阵列基板中的栅极层一示例实施方式的结构示意图。
图10为在图9的基础上形成有源层的结构示意图。
图11为在图10的基础上形成连接导体层的结构示意图。
图12为在图11的基础上形成绝缘层组、第一电极层和导电增强层的结构示意图。
图13为过渡区的凹陷部与第三过孔以及导电增强层之间的尺寸关系示意图。
图14为显示区的第一过孔与第二过孔以及导电增强层之间的尺寸关系示意图。
图15为导电增强层的结构示意图。
图16为本公开阵列基板第二示例实施方式的结构示意图。
图17为本公开阵列基板第三示例实施方式的结构示意图。
图18为本公开阵列基板第四示例实施方式的俯视结构示意图。
图19为本公开阵列基板第五示例实施方式的俯视结构示意图。
图20为本公开阵列基板的制备方法一示例实施方式的流程示意框图。
图21-图27为本公开阵列基板的制备方法的各个步骤的结构示意图。
图28为本公开显示面板一示例实施方式的结构示意图。
附图标记说明：
100、阵列基板；200、彩膜基板；
1、第一衬底基板；
2、开关层组；21、开关单元；22、栅极层；221、栅线；222、栅极；223、外围引线；23、栅绝缘层；24、有源层；241、沟道部；242、源极；243、漏极；25、连接导体层；251、源极连接引线；252、漏极连接引线；253、数据线；26、像素区域；
3、绝缘层组；31、第一绝缘层；311、第五过孔；32、有机绝缘层；321、第六过孔；322、第七过孔；323、空洞；33、凹陷部；34、第一过孔；
40、第一电极材料层；4、第一电极层；41、第二过孔；42、第三过孔；
50、导电增强材料层；5、导电增强层；51、第一导电条；511、第一直线部；512、第一弯曲部；52、第二导电条；53、引线条；54、汇总连接条；
6、第二绝缘层；61、第四过孔；62、台阶部；
7、第二电极层；71、第二电极；711、本体部；712、连接部；
81、第一隔垫物；82、第二隔垫物；
9、掩模层；91、掩模图案；911、第一部分；912、第二部分；913、第九过孔；
201、第二衬底基板；202、黑矩阵；203、滤光部；
X、第一方向；Y、第二方向；Z、第三方向；
AA、显示区；DUM、过渡区；WW、外围区。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
在本申请中，除非另有明确的规定和限定，术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
目前显示面板的显示亮度不均匀，主要是显示区AA的边缘区域的亮度较低。参照图1-图8所示，发明人发现导致该不良的主要原因在于，导电增强层5在显示区AA的边缘区域的 残留较多，导电增强层5会影响透过率，从而使得显示区AA的边缘区域的透光率较低；而导致导电增强层5在显示区AA的残留较多的原因是：外围区WW设置有大面积的外围引线223，导致外围区WW的高度比显示区AA的高度和过渡区DUM的高度均高，在导电增强材料层50背离第一衬底基板1的一侧通过涂覆或打印工艺形成掩模层9，由于掩模层9的材料具有一定的流动性，会从高度较高的区域流动至高度较低的区域，因此，掩模层9的材料会从外围区WW向过渡区DUM以及显示区AA流动，从而导致显示区AA靠近过渡区DUM的边缘区域内的掩模层9的厚度较厚，进而导致在对导电增强材料层50进行刻蚀形成导电增强层5时，在显示区AA靠近过渡区DUM的边缘区域内的掩模层9残留较多，即，使得掩模层9对导电增强材料层50的遮挡面积较大，最终导致形成的导电增强层5的面积较大，使得显示区AA的边缘区域的透光率较低、亮度较低。
本公开示例实施方式提供了一种阵列基板100，参照图8-图19所示，该阵列基板100具有显示区AA和设于显示区AA至少一侧的过渡区DUM，该阵列基板100可以包括第一衬底基板1、绝缘层组3、第一电极层4以及导电增强层5；绝缘层组3设于第一衬底基板1的一侧，绝缘层组3上设置有凹陷部33，凹陷部33位于过渡区DUM；第一电极层4设于绝缘层组3背离第一衬底基板1的一侧；导电增强层5设于第一电极层4背离第一衬底基板1的一侧，导电增强层5在第一衬底基板1上的正投影位于第一电极层4在第一衬底基板1上的正投影内。
本公开的阵列基板100及其制备方法，一方面，绝缘层组3上设置有凹陷部33，凹陷部33位于过渡区DUM；使得在形成第一电极层4和导电增强层5的时候，形成在导电增强材料层50背离第一衬底基板1一侧的掩模层9在从外围区WW流动至显示区AA时，会流动至过渡区DUM的凹陷部33内，从而使得掩模层9在显示区AA内的厚度均匀，在对导电增强材料层50进行刻蚀形成导电增强层5时，在显示区AA内的各处掩模层9对导电增强材料层50的遮挡面积基本相同，使得形成的导电增强层5的面积基本一致，使得显示区AA的各处的亮度也基本一致。另一方面，通过导电增强层5可以降低第一电极层4的电阻，从而减小阵列基板100的功耗，减轻阵列基板100的发热。
需要说明的是，在本说明书中，第一方向X和第二方向Y与第一衬底基板1的靠近绝缘层组3的一面平行，第一方向X与第二方向Y相交，例如，第一方向X可以与第二方向Y垂直。第三方向Z与第一衬底基板1的靠近绝缘层组3的一面垂直，即第三方向Z与第一方向X和第二方向Y均垂直。
阵列基板100可以包括显示区AA、过渡区DUM和外围区WW，在显示区AA的至少一侧设置过渡区DUM，例如，在显示区AA设置为矩形的情况下，可以在显示区AA的四周均设置有过渡区DUM，外围区WW设置在过渡区DUM背离显示区AA的一侧，而且显示区AA、过渡区DUM和外围区WW依次连接。
在本示例实施方式中，第一衬底基板1的材料可以包括无机材料，例如，该无机材料可以为玻璃、石英或金属等。第一衬底基板1的材料还可以包括有机材料，例如，该有机材料可以为聚酰亚胺、聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜、聚对苯二甲酸乙二醇酯和聚萘二 甲酸乙二醇酯等树脂类材料。该衬底基板可以由多层材料层形成，例如衬底基板可以包括多层第二衬底基板201，第二衬底基板201的材料可以是上述的任意一种材料。当然，衬底基板还可以设置为单层，可以是上述任一一种材料。
在本示例实施方式中，参照图8和图9所示，在第一衬底基板1的一侧可以设置有开关层组2，开关层组2可以包括栅极层22、栅绝缘层23、有源层24以及连接导体层25。
具体为，在第一衬底基板1的一侧可以设置有栅极层22，栅极层22可以包括多个栅极222和多根栅线221。栅线221沿第一方向X延伸，一根栅线221上连接有多个栅极222；也可以是栅线221的一部分作为栅极222。
在本示例实施方式中，参照图8所示，在栅极层22远离第一衬底基板1的一侧设置有栅绝缘层23。
参照图8和图10所示，在栅绝缘层23远离第一衬底基板1的一侧设置有有源层24，有源层24可以包括沟道部241、源极242和漏极243。沟道部241设于栅极222的背离第一衬底基板1的一侧。在将栅线221的一部分作为栅极222的情况下，与沟道部241相对的栅线221的一部分作为栅极222。在沟道部241的相对两端设置有两部分，其中一部分可以为源极242，另一部分可以为漏极243。
在本示例实施方式中，参照图8和图11所示，在有源层24背离第一衬底基板1的一侧设置有连接导体层25，连接导体层25可以包括多个源极连接引线251、多个漏极连接引线252和多根数据线253。数据线253沿第二方向Y延伸。因此，数据线253与栅线221必然会有交叉，多根数据线253与多根栅线221交叉形成多个像素区域26。
需要说明的是，源极242和漏极243不限于上述说明，例如，漏极连接引线252与沟道部241一端搭接的一部分也可以是漏极243，源极连接引线251与沟道部241相对另一端搭接的一部分也可以是源极242。
在显示区AA的第二方向Y的一侧过渡区DUM内设置有沿第一方向X排列的仅一行像素区域26，在显示区AA的第一方向X的一侧过渡区DUM内设置有沿第二方向Y排列的仅一列像素区域26。例如，可以是在显示区AA的外围围设有一圈像素区域26，即减少过渡区DUM内像素区域26的行数和列数。
由于在过渡区DUM上的绝缘层组3上没有设置凹陷部33的情况下，过渡区DUM趋近相对水平的平面；但是，在显示区AA的绝缘层组3上设置有第一过孔34，从而使得显示区AA的平均高度低于过渡区DUM的平均高度，使得过渡区DUM的掩模层9的材料也有向显示区AA流动的趋势。减少过渡区DUM内像素区域26的行数和列数，使得过渡区DUM的面积减小，使得过渡区DUM的掩模层9的材料的总量减少，可以缓解掩模层9的材料向显示区AA流动的量，避免显示区AA的边缘区域掩模层9的厚度较厚，避免导电增强层5的残留较多导致的透光率较低、亮度较低的不良。
源极连接引线251的一端连接于数据线253，另一端连接于源极242；也可以是数据线253的一部分作为源极连接引线251。漏极连接引线252的一端连接于漏极243。
栅极222、沟道部241、源极242以及漏极243等等形成一个开关单元21，该开关单元21是薄膜晶体管。
需要说明的是，本说明书中说明的薄膜晶体管为底栅型薄膜晶体管，在本公开的其他示例实施方式中，薄膜晶体管还可以是顶栅型或双栅型，对其具体结构在此不再赘述。而且，在使用极性相反的薄膜晶体管的情况或电路工作中的电流方向变化的情况等下，“源极242”及“漏极243”的功能有时互相调换。因此，在本说明书中，“源极242”和“漏极243”可以互相调换。
上述开关单元21为显示区AA的开关单元21的具体结构。在本公开的一些示例实施方式中，在过渡区DUM，可以设置开关单元21，而且，开关单元21的具体结构与显示区AA的开关单元21的具体结构可以相同；在本公开的另一些示例实施方式中，由于源极连接引线251为数据线253的一部分，且为了保持电学性能的一致性，因此，也可以仅设置靠近数据线253的一部分源极连接引线251，而且，源极连接引线251与有源层24通过同一次构图工艺形成，因此，参照图8所示，还可以设置与源极连接引线251连接且位于源极连接引线251靠近第一衬底基板1一侧的有源层24，即不设置漏极连接引线252以及与漏极连接引线252连接的另一部分有源层24；即不设置漏极连接引线252以及与漏极连接引线252连接的漏极243，可以使过孔的深度更深，即使得凹陷部33的最低处与第一衬底基板1之间的距离小于第一过孔34的最低处与第一衬底基板1之间的距离，能够容纳更多的掩模层9的材料。当然，在源极连接引线251与有源层24不是通过同一次构图工艺形成的情况下，还可以不设置与源极连接引线251连接且位于源极连接引线251靠近第一衬底基板1一侧的有源层24，即在过渡区DUM不设置有源层24。在本公开的再一些示例实施方式中，在源极连接引线251不是数据线253的一部分的情况下，也可以不设置源极连接引线251，仅设置数据线253。
过渡区DUM的开关单元21可以根据产品结构需要和工艺需要进行设置，过渡区DUM的开关单元21不需要与第二电极71连接，不需要为第二电极71提供电压，因此，开关单元21的结构可以不完整，可以仅包括上述完整的开关单元21中的一个部件、两个部件或多个部件。
参照图8所示，在外围区WW设置有多根外围引线223，数据线253和栅线221均连接至外围引线223，外围引线223可以与栅线221同层同材料设置，也可以与数据线253同层同材料设置，还可以是设置有两层外围引线223。通过外围引线223输入数据信号至数据线253，通过外围引线223输入控制信号至栅线221，而且通过外围引线223输出一些反馈信号。而且外围引线223的数量较多，几乎覆盖了整个外围区WW，导致在形成第一电极材料层40和导电增强材料层50后，外围区WW在第三方向Z的高度高于显示区AA在第三方向Z的高度，后续对第一电极材料层40和导电增强材料层50进行刻蚀时，形成在导电增强材料层50背离第一衬底基板1一侧的掩模层9后，掩模层9具有一定的流动性，掩模层9的材料会从外围区WW向过渡区DUM以及显示区AA流动，从而导致显示区AA靠近过渡区DUM的边缘区域内的掩模层9的厚度较厚，进而导致在对导电增强材料层50进行刻蚀形成导电增强层5时，在显示区AA靠近过渡区DUM的边缘区域内的掩模层9残留较多，即使得掩模层9对导电增 强材料层50的遮挡面积较大，最终导致形成的导电增强层5的面积较大，使得显示区AA的边缘区域的透光率较低、亮度较低。
在本示例实施方式中，参照图8所示，在连接导体层25背离第一衬底基板1的一侧设置有绝缘层组3，绝缘层组3可以包括第一绝缘层31和有机绝缘层32，第一绝缘层31设置在连接导体层25背离第一衬底基板1的一侧，第一绝缘层31上设置有第五过孔311，第五过孔311位于显示区AA，而且第五过孔311连通至漏极连接引线252，使得漏极连接引线252裸露。第一绝缘层31的材料可以是无机材料，例如，可以是氮化硅、氧化硅等等。第一绝缘层31的厚度大于等于100nm且小于等于500nm。
参照图8所示，有机绝缘层32设置在第一绝缘层31背离第一衬底基板1的一侧，有机绝缘层32的材料可以是有机材料，例如，可以是聚酰亚胺、聚碳酸酯、聚丙烯酸酯等等。有机绝缘层32的厚度大于等于1.5μm且小于等于5μm。
有机绝缘层32能够起到平坦化的作用，为后续形成的第一电极层4提供较为平整的基底，便于第一电极层4的成型，进而提高第一电极层4的均匀性；另外，有机绝缘层32使得第一电极层4与数据线253之间在第三方向Z的距离增大、相互影响减弱，寄生电容也会减小很多，更利于驱动芯片的驱动；第一电极层4与数据线253之间在第三方向Z的距离增大后，第一电极层4与数据线253之间在其他方向(例如在第一方向X和第二方向Y)上的距离距离可以缩短，从而彩膜基板200的黑矩阵202的宽度也可以制作得更小，进而提高产品的开口率。
在有机绝缘层32上设置有第六过孔321和第七过孔322，第六过孔321位于过渡区DUM，第六过孔321形成绝缘层组3的凹陷部33。第七过孔322位于显示区AA，且第七过孔322与第五过孔311连通形成绝缘层组3的第一过孔34，使得漏极连接引线252裸露。
当然，在本公开的另外一些示例实施方式中，还可以在第一绝缘层31上设置第八过孔，第八过孔位于过渡区DUM，第六过孔321可以与第八过孔连通形成绝缘层组3的凹陷部33。
第一过孔34在第一衬底基板1上的正投影面积等于或小于凹陷部33在第一衬底基板1上的正投影面积，即将位于过渡区DUM的凹陷部33的面积设置的较大，使得凹陷部33可以容纳较多的光阻材料，避免显示区AA靠近过渡区DUM的边沿区域内的掩模层9在第三方向Z的厚度较厚，导致导电增强层5的残留，从而影响阵列基板100的开口率，影响显示面板的显示效果。
在本示例实施方式中，参照图1和图12所示，图12中由于绝缘层组3以及第一电极层4均是透明的，因此，没有体现绝缘层组3以及第一电极层4，但是体现了第一电极层4上的第二过孔41和第三过孔42，绝缘层组3上的凹陷部33和第一过孔34；在绝缘层组3背离第一衬底基板1的一侧设置有第一电极层4，第一电极层4上设置有第二过孔41和第三过孔42，第二过孔41位于显示区AA，第二过孔41连通至第一过孔34；第一过孔34在第一衬底基板1上的正投影位于第二过孔41在第一衬底基板1上的正投影之内，例如，第二过孔41在第一衬底基板1上的正投影覆盖第一过孔34在第一衬底基板1上的正投影，且第二过孔41在第一 衬底基板1上的正投影的面积大于第一过孔34在第一衬底基板1上的正投影的面积。
第三过孔42位于过渡区DUM，第三过孔42与凹陷部33连通，凹陷部33在第一衬底基板1上的正投影位于第三过孔42在第一衬底基板1上的正投影之内，例如，第三过孔42在第一衬底基板1上的正投影覆盖且大于凹陷部33在第一衬底基板1上的正投影。
而且，参照图13和图14所示，由于图中表示的尺寸关系与栅极层22之间的关系不大，因此，图中省略栅极层22，凹陷部33在第一衬底基板1上的正投影的边沿线与第三过孔42在第一衬底基板1上的正投影的边沿线之间的间距(D1’和D3’)，大于或等于第一过孔34在第一衬底基板1上的正投影的边沿线与第二过孔41在第一衬底基板1上的正投影的边沿线之间的间距(D1和D3)；D1’和D1可以为第二方向Y的间距，D1’与D1比较；D3’和D3可以为第一方向X的间距，D3’与D3比较。当然，也可以是D1’与D3比较，D1与D3’比较。
需要说明的是，凹陷部33在第一衬底基板1上的正投影指的是凹陷部33背离第一衬底基板1的一侧在第一衬底基板1上的正投影，也就是凹陷部33的最顶部在第一衬底基板1上的正投影。第三过孔42在第一衬底基板1上的正投影指的是第三过孔42背离第一衬底基板1的一侧在第一衬底基板1上的正投影，也就是第三过孔42的最顶部在第一衬底基板1上的正投影。第一过孔34在第一衬底基板1上的正投影指的是第一过孔34背离第一衬底基板1的一侧在第一衬底基板1上的正投影，也就是第一过孔34的最顶部在第一衬底基板1上的正投影。第二过孔41在第一衬底基板1上的正投影指的是第二过孔41背离第一衬底基板1的一侧在第一衬底基板1上的正投影，也就是第二过孔41的最顶部在第一衬底基板1上的正投影。其他过孔在第一衬底基板1上的正投影均指的是最顶部在第一衬底基板1上的正投影。
为了在第三过孔42内设置面积较大的凹陷部33，因此，第三过孔42在第一衬底基板1上的正投影面积大于或等于第二过孔41在第一衬底基板1上的正投影面积，例如，第三过孔42和第二过孔41设置为形状相同的矩形的情况下，在第一方向X上，第三过孔42的长度大于或等于第二过孔41的长度；在第二方向Y上，第三过孔42的宽度大于或等于第二过孔41的宽度。
第一电极层4的材质可以是ITO，第一电极层4的厚度大于或等于400埃且小于或等于700埃，例如，第一电极层4的厚度可以为450埃、550埃、580埃、635埃、674埃等等。当然，第一电极层4的材质还可以是其他透明导电材质。
由于，第一电极层4的材质是透明导电材质，因此，第一电极层4可以是整层设置，不会对阵列基板100的透光率产生影响，也不会对显示面板的发光亮度产生影响，但是透明导电材质的电阻率较大，导致第一电极层4的电阻较大，使得阵列基板100的功耗较大，而且发热严重。
在本示例实施方式中，参照图1和图12所示，在第一电极层4背离第一衬底基板1的一侧设置有导电增强层5，导电增强层5在第一衬底基板1上的正投影位于第一电极层4第一衬底基板1上的正投影内，例如，第一电极层4第一衬底基板1上的正投影覆盖且大于导电增强层5在第一衬底基板1上的正投影。
导电增强层5的材质可以是铜，导电增强层5的厚度大于等于1000埃且小于等于2000埃，例如，导电增强层5的厚度可以为1115埃、1200埃、1285埃、1358埃、1391埃、1425埃、1588埃、1638埃、1721埃、1785埃、1868埃、1926埃、1985埃等等。当然，在本公开的其他示例实施方式中，导电增强层5的材质还可以是铝、银等其他金属材质。金属材质的电阻率较小，通过在第一电极层4背离第一衬底基板1的一侧增加导电增强层5可以减小第一电极层4的电阻，从而减小阵列基板100的功耗，减轻阵列基板100的发热。
在对导电增强材料层50进行刻蚀形成导电增强层5时，需要进行灰化工艺，灰化工艺会对导电增强材料层50造成氧化腐蚀，从而导致在对导电增强材料层50刻蚀形成导电增强层5时，会对第一电极材料层40刻蚀，导致形成第一电极层4的断开不良。在导电增强层5上设置有保护层，在对掩模层9进行灰化时，有保护层对导电增强材料层50进行保护，避免灰化工艺时对导电增强材料层50的氧化腐蚀，从而避免在对第一电极材料层40进行图案化处理形成第一电极层4时，对第一电极层4进行刻蚀，导致第一电极层4的断开的不良。保护层的材质可以是MoNbTi。
但是，金属材质的导电增强层5是不透明的，因此，导电增强层5不能整层设置，而是尽量将导电增强层5设置在阵列基板100本来就不透光的位置，从而使得导电增强层5不仅能够减小第一电极层4的电阻，而且不会对阵列基板100的开口率产生影响。
具体地，参照图12和图15所示，导电增强层5可以包括第一导电条51和第二导电条52；第一导电条51沿第一方向X延伸，第一导电条51的延伸方向与栅线221的延伸方向一致；第一导电条51在第一衬底基板1上的正投影与栅线221在第一衬底基板1上的正投影至少部分交叠，例如，第一导电条51在第一衬底基板1上的正投影可以位于栅线221在第一衬底基板1上的正投影之内，即第一导电条51在第二方向Y的宽度小于或等于栅线221在第二方向Y的宽度。如此设置，可以保证阵列基板100的开口率，从而保证显示面板的显示亮度。而且，第一导电条51的数量可以与栅线221的数量相同，即第一导电条51与栅线221是一一对应的关系；或者，第一导电条51的数量可以小于栅线221的数量。第一导电条51的数量可以设置为一根、两根或多跟。
第二导电条52的数量可以设置为一根，这种情况下，第二导电条52连接于第一导电条51的第一方向X的一端。第二导电条52的数量可以设置为两根，其中一根连接于第一导电条51的第一方向X的一端，另外一根与第一导电条51交叉连接。第二导电条52的数量可以设置为多根，其中一根连接于第一导电条51的第一方向X的一端，剩余的与第一导电条51交叉连接。
第二导电条52沿第二方向Y延伸，第二导电条52的延伸方向与数据线253的延伸方向一致，第二导电条52在第一衬底基板1上的正投影与数据线253在第一衬底基板1上的正投影至少部分交叠，例如，第二导电条52在第一衬底基板1上的正投影可以位于数据线253在第一衬底基板1上的正投影之内，即第二导电条52在第一方向X的宽度小于或等于数据线253在第一方向X的宽度。而且，第二导电条52的数量可以小于数据线253的数量，当然，也可 以是第二导电条52的数量等于数据线253的数量，即第二导电条52与数据线253是一一对应的关系。
导电增强层5还可以包括多根引线条53，多根引线条53的一端可以连接于第二导电条52，例如，多根引线条53的一端可以连接于最外侧的第二导电条52；引线条53沿第一方向X朝向背离显示区AA的一侧延伸，引线条53的延伸方向可以与栅线221的延伸方向一致；多根引线条53的相对另一端可以连接于边缘GOA，GOA为行扫描信号线，最终连接至外围区WW的绑定引脚，通过绑定引脚可以输入Com信号，Com信号为公共电极信号，然后通过多根引线条53将Com信号传输至显示区AA的第一电极层4和导电增强层5。
引线条53在第一衬底基板1上的正投影与栅线221在第一衬底基板1上的正投影无交叠，即引线条53与栅线221没有正对设置，而是错位设置，避免引线条53与栅线221之间产生寄生电容。
导电增强层5还可以包括汇总连接条54，汇总连接条54可以连接于引线条53背离第二导电条52的一端，在引线条53设置为一根的情况下，一根引线条53连接于汇总连接条54；在引线条53设置为两根或多根的情况下，两根或多根引线条53均连接于汇总连接条54。汇总连接条54沿第二方向Y延伸，汇总连接条54的延伸方向可以与数据线253的延伸方向一致，多根引线条53通过汇总连接条连接于边缘GOA。公共电极信号可以先传输至汇总连接条54，通过汇总连接条54传输至引线条53以及第一电极层4。
而且，参照图13和图14所示，第三过孔42在第一衬底基板1上的正投影的边沿线与相邻的第一导电条51在第一衬底基板1上的正投影的边沿线之间的间距D2’，大于或等于第二过孔41在第一衬底基板1上的正投影的边沿线与相邻的第一导电条51在第一衬底基板1上的正投影的边沿线之间的间距D2。第三过孔42在第一衬底基板1上的正投影的边沿线与相邻的第一导电条51之间的间距大于等于0.5微米且小于等于3微米。第二过孔41在第一衬底基板1上的正投影的边沿线与相邻的第一导电条51在第一衬底基板1上的正投影的边沿线之间的间距大于等于2微米且小于等于5.5微米。
第三过孔42在第一衬底基板1上的正投影的边沿线与相邻的第二导电条52在第一衬底基板1上的正投影的边沿线之间的间距D4’，大于或等于第二过孔41在第一衬底基板1上的正投影的边沿线与相邻的第二导电条52在第一衬底基板1上的正投影的边沿线之间的间距D4。第三过孔42在第一衬底基板1上的正投影的边沿线与相邻的第二导电条52之间的间距大于等于0.5微米且小于等于3微米。第二过孔41在第一衬底基板1上的正投影的边沿线与相邻的第二导电条52在第一衬底基板1上的正投影的边沿线之间的间距大于等于2微米且小于等于5.5微米。
如此设置，使得第二过孔41与第一导电条51以及第二导电条52之间的距离较大，即使形成第一导电条51以及第二导电条52的制备工艺有误差，以及对位精度有波动的情况下，第一导电条51以及第二导电条52也不会形成在第二过孔41内，从而不会产生第一导电条51以及第二导电条52由于跨越第二过孔41产生断裂的不良，也不会由于第二过孔41内的掩模 层材料的残留导致的导电增强层5和第一电极4的图案的异常的不良，而且避免第一电极4有残留的情况下，导致的第一电极4与第二电极71接触而短路的不良。
更进一步，使得第三过孔42与第一导电条51以及第二导电条52之间的距离较大，即使形成第一导电条51以及第二导电条52的制备工艺有误差，以及对位精度有波动的情况下，第一导电条51以及第二导电条52也不会形成在第三过孔42内，从而不会产生第一导电条51以及第二导电条52由于跨越第三过孔42产生断裂的不良，也不会由于第三过孔42内的掩模层材料的残留导致的导电增强层5和第一电极4的图案的异常的不良，而且避免第一电极4有残留的情况下，导致的第一电极4与第二电极71接触而短路的不良。
另外，参照图12所示，位于沿第一方向X排列的一行像素区域26内的凹陷部33和第一过孔34位于对应像素区域26内的基本相同区域，例如，第一行像素区域26内的凹陷部33和第一过孔34都位于像素区域26左上角的位置，第二行像素区域26内的凹陷部33和第一过孔34都位于像素区域26右上角的位置。当然，在本公开的另外一些示例实施方式中，也可以是位于沿第二方向Y排列的一行像素区域26内的凹陷部33和第一过孔34位于像素区域26内基本相同的位置。
在本示例实施方式中，参照图16和图17所示，在导电增强层5背离第一衬底基板1的一侧设置有第二绝缘层6，而且第二绝缘层6形成在有机绝缘层32上的第七过孔322内形成凹陷结构。在第二绝缘层6上设置有第四过孔61，第七过孔322在第一衬底基板1上的正投影覆盖且大于第四过孔61在第一衬底基板1上的正投影，即第四过孔61连通至第七过孔322，且有机绝缘层32上的第七过孔322比第二绝缘层6上的第四过孔61要大，使得第二绝缘层6不仅覆盖第七过孔322的孔侧壁，而且第二绝缘层6覆盖在第七过孔322内没有被机绝缘层32覆盖的部分第一绝缘层31上，即第四过孔61没有完全占据凹陷结构的底壁，以使第二绝缘层6在第七过孔322内形成台阶部62，也可以说是台阶部62是第二绝缘层6在第七过孔322的孔底壁上的残留。
在第二绝缘层6背离第一衬底基板1的一侧设置有第二电极层7，第二电极71可以是像素电极。第二电极层7包括多个第二电极71，第二电极71包括相互连接的本体部711和连接部712，连接部712通过第四过孔61以及第五过孔311连接至开关单元21的漏极243，即位于第四过孔61以及第五过孔311内的部分为连接部712；而且，本体部711位于台阶部62背离第一衬底基板1的一侧，也可以说是本体部711位于第四过孔61设置有台阶部62的一侧，即设置在第二绝缘层6背离第一衬底基板1的一侧且靠近台阶部62的一部分为本体部711。
如此设置，即使在形成第四过孔61的过程中加工设备具有误差以及对位工艺有误差，参照图16所示，如果形成的第四过孔61向需要形成台阶部62的一侧偏移，由于有足够的余量，在对第二绝缘层6进行刻蚀时，不会对靠近台阶部62一侧的覆盖在第七过孔322的孔侧壁的第二绝缘层6进行刻蚀，从而使得第二绝缘层6对有机绝缘层32形成完整的保护，不会对有机绝缘层32产生刻蚀，不会在有机绝缘层32上形成空洞323，后续形成的第二电极71不会覆盖在空洞323处，第二电极71不会产生断裂、脱落等风险；参照图17所示，如果形成的第 四过孔61向不需要形成台阶部62的其他侧偏移，在对第二绝缘层6进行刻蚀时，会对其他侧的覆盖在第七过孔322的孔侧壁的第二绝缘层6进行刻蚀，使得第二绝缘层6对有机绝缘层32不会形成完整的保护，会对有机绝缘层32产生刻蚀，会在有机绝缘层32上形成空洞323，后续形成的第二电极71的一部分会覆盖在空洞323处，但是由于本体部711没有覆盖在空洞323处，因此，本体部711不会产生断裂、脱落等风险；而且也不会影响本体部711与连接部712之间的连接，不会影响从漏极连接引线252向第二电极71传递信号。
第二绝缘层6的材料可以是无机材料，例如，可以是氮化硅、氧化硅等等。第二绝缘层6的厚度大于等于100nm且小于等于500nm。
第二电极71的材质可以是ITO，第二电极71的厚度大于或等于400埃且小于或等于700埃，例如，第一电极的厚度可以为450埃、550埃、580埃、635埃、674埃等等。当然，第二电极71的材质还可以是其他透明导电材质。
另外，在本公开的其他示例实施方式中，第一电极层4和第二电极层7的位置可以互换，具体为可以在有机绝缘层32的远离衬底基板的一侧设置第二电极71，第二电极71可以是像素电极，第二电极71通过第一绝缘层31上的第五过孔311和有机绝缘层32上的第七过孔322与漏极243连接；在第二电极71的远离衬底基板的一侧设置第二绝缘层6；在第二绝缘层6的远离衬底基板的一侧依次层叠设置第一电极层4和导电增强层5；第一电极层4和导电增强层5的具体结构上述已经进行了详细说明，因此，此处不再赘述。
参照图18所示，在本公开的另一些示例实施方式中，在过渡区DUM的一个像素区域26内设置有至少两个凹陷部33，例如，在过渡区DUM的一个像素区域26内可以设置有两个、三个或更多个凹陷部33；且设置有至少两个第三过孔42，例如，在过渡区DUM的一个像素区域26内可以设置有两个、三个或更多个第三过孔42；第三过孔42与凹陷部33是一一对应的，第三过孔42的数量与凹陷部33的数量相同。
位于同一像素区域26内的相邻两个凹陷部33之间的间距D5大于等于4微米，位于同一像素区域26内的相邻两个第三过孔42之间的间距D6大于等于2微米。
需要说明的是，上述相邻两个凹陷部33之间的间距以及相邻两个第三过孔42之间的间距是根据设备的精度设置的，避免相邻两个凹陷部33连通形成一个凹陷部33，避免相邻两个第三过孔42连通形成一个第三过孔42。因此，在设备的精度较高的情况下，相邻两个凹陷部33之间的间距以及相邻两个第三过孔42之间的间距还可以设置的更小。
在显示区AA的一个像素区域26内设置有一个第一过孔34，且设置有一个第二过孔41，即显示区AA的具体结构与上述示例实施方式的结构相同，此处不再赘述。
参照图19所示，阵列基板100还可以包括第一隔垫物81，第一隔垫物81设于第二电极层7的背离第一衬底基板1的一侧。
第一隔垫物81可以设置为四棱台的结构，即第一隔垫物81的与第一衬底基板1平行的截面为长方形，且靠近第一衬底基板1的底面的面积大于远离第一衬底基板1的顶面的面积。
一般在相邻两个开关单元21(薄膜晶体管)之间具有较为平整的平面可以设置第一隔垫 物81，因此，第一隔垫物81位于相邻两个开关单元21之间；第一隔垫物81的长度方向与数据线253的延伸方向一致，第一隔垫物81在第一衬底基板1上的正投影与数据线253在第一衬底基板1上的正投影有交叠，即第一隔垫物81与数据线253相对设置。
导电增强层5的第一导电条51在第一衬底基板1上的正投影设置为曲线，具体地，曲线可以包括多段直线和多段弧线，直线和弧线交替设置，且相互连接。第一导电条51在与第一隔垫物81相邻的位置向背离第一隔垫物81一侧折弯，即弧线向背离第一隔垫物81一侧折弯，折弯深度H大于等于2微米且小于等于3微米，例如，折弯深度H可以为2.5微米。折弯深度H为弧线与直线之间的最大距离。当然，折弯深度H的具体数值可以根据设备以及工艺精度具体设定。而且，第一导电条51折弯的位置一般是与数据线253相交的位置。
具体地，第一导电条51可以包括第一直线部511和第一弯曲部512，第一直线部511在第一衬底基板1上的正投影位于栅线221在第一衬底基板1上的正投影内，第一弯曲部512在第一衬底基板1上的正投影至少部分与栅线221在第一衬底基板1上的正投影不交叠，即第一弯曲部512与第一直线部511连接的两端部在第一衬底基板1上的正投影位于栅线221在第一衬底基板1上的正投影内，但是，第一弯曲部512的中间部分在第一衬底基板1上的正投影与栅线221在第一衬底基板1上的正投影不交叠。
第一导电条51折弯后为第一隔垫物81预留空间，因为，第一隔垫物81用于支撑彩膜基板200，需要设置较为平整的支撑平面，那么，就需要为第一隔垫物81提供较为平整的基础平面，第一导电条51会导致设置第一隔垫物81的基础平面不平整，将第一导电条51折弯后，第一隔垫物81不需要设置在第一导电条51的背离第一衬底基板1的一侧，为第一隔垫物81提供较为平整的基础平面。
当然，在本公开的其他一些示例实施方式中，第一导电条51可以不对第一隔垫物81进行避让，使得第一导电条51在第一衬底基板1上的正投影与第一隔垫物81在第一衬底基板1上的正投影有交叠。
而且，第一隔垫物81与第一导电条51之间的最小距离K1大于等于2微米且小于等于4微米。当然，第一隔垫物81与第一导电条51之间的最小距离的具体数值可以根据设备以及工艺精度具体设定。避免在工艺或设备产生误差的情况下，使得第一隔垫物81设置在第一导电条51背离第一衬底基板1的一侧，导致第一隔垫物81的基础面不平整。而且，第一隔垫物81与第一导电条51均需要被黑矩阵202遮挡，尽量减小黑矩阵202的面积，提高开口率。
需要说明的是，上述曲线并不一定全部是由弧形构成的，也可以是由多个直线形成的折线形的，还可以是由直线和弧形混合构成的。
而且，曲线的第一导电条51有足够的延伸余量，可以有效避免第一导电条51的断裂。
另外，在本公开的再一些示例实施方式中，凹陷部33靠近显示区AA一侧的边沿线与显示区AA之间的距离大于，凹陷部33靠近外围区WW一侧的边沿线与外围区WW之间的距离。即使得凹陷部33更靠近外围区WW，方便外围区WW的掩模层的材料流入至凹陷部33内，而且尽量避免显示区AA的掩模层的材料流入至凹陷部33内，导致显示区AA的掩模层 的厚度减薄。
基于同一发明构思，本公开示例实施方式还提供了一种阵列基板100的制备方法，参照图20所示，该阵列基板100的制备方法可以包括以下步骤：
步骤S10，提供第一衬底基板，所述第一衬底基板具有显示区和设于显示区至少一侧的过渡区，在所述第一衬底基板的一侧形成绝缘层组，在所述绝缘层组上形成凹陷部，所述凹陷部位于所述过渡区。
步骤S20，在所述绝缘层组背离所述第一衬底基板的一侧依次形成第一电极材料层和导电增强材料层。
步骤S30，在所述导电增强材料层背离所述第一衬底基板的一侧形成掩模层，部分所述掩模层形成在所述凹陷部内，所述显示区的所述掩模层的厚度一致。
步骤S40，以所述掩模层为掩模对所述第一电极材料层进行图案化处理形成第一电极层，且对所述导电增强材料层进行图案化处理形成导电增强层。
下面对阵列基板100的制备方法的各个步骤进行详细说明。
参照图1所示，提供第一衬底基板1，第一衬底基板1具有显示区AA和设于显示区AA至少一侧的过渡区DUM，第一衬底基板1的显示区AA也就是阵列基板100的显示区AA，第一衬底基板1的过渡区DUM也就是阵列基板100的过渡区DUM。第一衬底基板1还具有外围区WW，第一衬底基板1的外围区WW也就是阵列基板100的外围区WW。具体结构上述已经进行了详细说明，因此此处不再赘述。
在第一衬底基板1的一侧形成栅极层22，栅极层22可以包括栅极222和栅线221；在栅极层22背离第一衬底基板1的一侧形成栅绝缘层23；在栅绝缘层23背离第一衬底基板1的一侧形成有源层24，有源层24可以包括沟道部241、源极242和漏极243，源极242和漏极243连接于沟道部241的相对两侧；在有源层24背离第一衬底基板1的一侧形成连接导体层25，连接导体层25可以包括多个源极连接引线251、多个漏极连接引线252和多根数据线253。
在连接导体层25背离第一衬底基板1的一侧依次形成第一绝缘层31和有机绝缘层32，对有机绝缘层32进行图案化处理形成第六过孔321和第七过孔322，第七过孔322位于显示区AA，第六过孔321位于过渡区DUM；有机绝缘层32的材质可以是光刻胶，在有机绝缘层32上形成第六过孔321和第七过孔322时只需要进行曝光显影即可，不需要刻蚀，工艺过程较为简单。第六过孔321形成凹陷部33。
第一过孔34在第一衬底基板1上的正投影面积小于或等于凹陷部33在第一衬底基板1上的正投影面积。
在绝缘层组3背离第一衬底基板1的一侧可以通过溅射形成第一电极材料层40，在第一电极材料层40背离第一衬底基板1的一侧可以通过溅射形成导电增强材料层50；第一电极材料层40和导电增强材料层50均会形成在第一过孔34和凹陷部33内，位于第一过孔34内的第一电极材料层40与漏极243连接，但是，第一电极材料层40最终形成公共电极，是不需要与漏极243连接的因此，需要对第一电极材料层40进行图案化处理，而且，导电增强材料层 50的材质是金属，是不透光的，避免导电增强材料层50对阵列基板100的透光率产生影响，导电增强材料层50也需要进行图案化处理。
参照图21所示，在导电增强材料层50背离第一衬底基板1的一侧通过涂覆或打印工艺形成掩模层9，由于掩模层9的材料具有一定的流动性，会从高度较高的区域流动至高度较低的区域，由于外围区WW设置有大面积的外围引线233，导致外围区WW的高度比显示区AA的高度和过渡区DUM的高度均高，因此，掩模层9的材料会从外围区WW向过渡区DUM以及显示区AA流动，从而导致显示区AA靠近过渡区DUM的边缘区域内的掩模层9的厚度较厚。
在过渡区DUM设置凹陷部33后，掩模层9的材料从外围区WW流到过渡区DUM后，会流动至凹陷部33内，从而避免掩模层9的材料进一步流动至显示区AA，从而使得显示区AA的掩模层9的厚度一致，避免显示区AA靠近过渡区DUM的边缘区域内的掩模层9的厚度较厚。
具体为：在掩模层9的远离衬底基板的一侧放置掩模板，掩模板可以包括透光部、遮光部以及半透光部；半透光部与第二部分912相对设置，即半透光部在衬底基板上的正投影与第二部分912在衬底基板上的正投影重合；遮光部与第一部分911相对设置，即遮光部在衬底基板上的正投影与第一部分911在衬底基板上的正投影重合。透光部与掩模层9的其他部分相对设置。
然后，参照图22所示，对掩模层9进行曝光显影形成掩模图案91，去除与透光部相对设置的掩模层9形成第九过孔913，第九过孔913使得部分导电增强材料层50裸露；与半透光部相对设置的掩模层9去除一定厚度，形成第二部分912；与遮光部相对设置的掩模层9完全保留，形成第一部分911，使得第一部分911的厚度大于第二部分912的厚度。而且，由于掩模层9显示区AA的整体厚厚较为均匀，因此不会出现图2中所示的第二部分912较厚的情况。
最后，参照图23所示，对与第九过孔913相对的部分导电增强材料层50进行刻蚀去除，即对裸露的导电增强材料层50进行第一次刻蚀，保留被掩模图案91覆盖的导电增强材料层50。
参照图24所示，对掩模图案91进行灰化处理，以去除第二部分912，使第二部分912覆盖的导电增强材料层50裸露，灰化工艺采用的气体可以包括SF6和O2。通过灰化工艺去除第二部分912，使得第二部分912覆盖的导电增强材料层50裸露，而且第一部分911的厚度也有减薄。而且，由于掩模层9显示区AA的整体厚厚较为均匀，因此不会出现图4中所示的还残留一部分第二部分912的情况。
参照图25所示，对与第九过孔913相对的部分第一电极材料层40进行刻蚀去除，形成第一电极层4；具体为，以第一部分911以及导电增强材料层50为掩模对第一电极材料层40进行刻蚀形成第一电极层4，即在第一电极层4对第一电极材料层40进行刻蚀形成第二过孔41和第三过孔42。
参照图26所示，对剩余的导电增强材料层50进行图案化处理形成导电增强层5，具体为， 以第一部分911为掩模对导电增强材料层50进行刻蚀形成导电增强层5。导电增强层5在衬底基板上的正投影与栅线221在衬底基板上的正投影有交叠，具体为，导电增强层5在衬底基板上的正投影位于栅线221在衬底基板上的正投影内，即导电增强层5的延伸方向与栅线221的延伸方向一致，且导电增强层5的宽度稍小于栅线221的宽度。导电增强层5的宽度大约为3.5微米，栅线221的宽度大约为4.5微米。由于导电增强层5均是金属材质，是不透光的而且具有反光性，因此，为了避免其反光而影响显示效果，需要通过黑矩阵202对其进行遮挡，栅线221也通过黑矩阵202对其进行遮挡，导电增强层5在衬底基板上的正投影位于栅线221在衬底基板上的正投影内，可以避免增加黑矩阵202的宽度，从而避免减小开口率。
而且，由于掩模层9显示区AA的整体厚厚较为均匀，因此不会出现图6中所示的还残留一部分导电增强层5的情况，即不会出现图6中所示的导电增强层5的宽度较宽的情况。
参照图27所示，去除剩余的掩模层9，即剥离剩余的第一部分911。
在导电增强层5背离第一衬底基板1的一侧形成第二绝缘层6，并对第二绝缘层6和第一绝缘层31通过同一次构图工艺进行刻蚀，在第一绝缘层31上形成第五过孔311，在第二绝缘层6上形成第四过孔61。
最后，在第二绝缘层6背离第一衬底基板1的一侧形成第二电极材料层，并对第二电极材料层进行图案化处理形成多个第二电极71。
需要说明的是，尽管在附图中以特定顺序描述了本公开中阵列基板100的制备方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
基于相同的发明构思，本公开示例实施方式还提供了一种显示面板，参照图28所示，该显示面板可以包括阵列基板100和彩膜基板200；阵列基板100是上述任意一项所述的阵列基板100；阵列基板100的具体结构上述已经进行了详细说明，因此，此处不再赘述。彩膜基板200与阵列基板100相对设置，彩膜基板200可以包括黑矩阵202，导电增强层5在第一衬底基板1上的正投影位于黑矩阵202在第一衬底基板1上的正投影内。
在本示例实施方式中，彩膜基板200还可以包括第二衬底基板201，设于第二衬底基板201一侧的多个滤光部203和黑矩阵202，多个滤光部203阵列排布于第二衬底基板201的一侧；多个滤光部203可以包括红色滤光部203、蓝色滤光部203、绿色滤光部203。
在彩膜基板200的靠近阵列基板100的一侧设置有第二隔垫物82，第二隔垫物82也可以设置为长条形，对盒后第二隔垫物82与第一隔垫物81接触且形成十字交叉的结构，第二隔垫物82与第一隔垫物81一起支撑彩膜基板200，为液晶提供容纳空间。
参照图19所示，图中粗黑虚线为黑矩阵202的边沿线，在阵列基板100上的第一导电条51设置曲线的情况下，黑矩阵202靠近第一导电条51的一侧边沿线设置为与第一导电条51相适配的曲线，使得黑矩阵202既能够遮挡第一导电条51，而且不会增加太多的不透光面积，保证显示面板的透光率和亮度。
第一隔垫物81在第一衬底基板1上的正投影位于黑矩阵202在第一衬底基板1上的正投影之内；使得黑矩阵202将第一隔垫物81遮挡；而且，第一隔垫物81在第一衬底基板1上的正投影的边沿线与黑矩阵202在第一衬底基板1上的正投影的边沿线之间的最小距离K2大于等于2微米且小于等于4微米。避免在工艺或设备产生误差的情况下，使得黑矩阵202无法遮挡第一隔垫物81。
第一导电条51在第一衬底基板1上的正投影位于黑矩阵202在第一衬底基板1上的正投影之内；使得黑矩阵202将第一导电条51遮挡；第一导电条51在第一衬底基板1上的正投影的边沿线与黑矩阵202在第一衬底基板1上的正投影的边沿线之间的最小距离K3大于等于2微米且小于等于4微米。避免在工艺或设备产生误差的情况下，使得黑矩阵202无法遮挡第一导电条51。
而且，第一隔垫物81与第一导电条51均需要被黑矩阵202遮挡，尽量减小黑矩阵202的面积，提高开口率。
当然，第二导电条52在第一衬底基板1上的正投影位于黑矩阵202在第一衬底基板1上的正投影之内；使得黑矩阵202将第二导电条52遮挡。
当然，上述数值可以根据设备以及工艺精度具体设定。
基于相同的发明构思，本公开示例实施方式还提供了一种显示装置，该显示装置可以包括上述所述的显示面板。显示面板的具体结构上述已经进行了详细说明，因此，此处不再赘述。
而该显示装置的具体类型不受特别的限制，本领域常用的显示装置类型均可，具体例如手机等移动装置、手表等可穿戴设备、VR装置等等，本领域技术人员可根据该显示装置的具体用途进行相应地选择，在此不再赘述。
需要说明的是，该显示装置除了显示面板以外，还包括其他必要的部件和组成，以显示器为例，具体例如外壳、电路板、电源线，等等，本领域技术人员可根据该显示装置的具体使用要求进行相应地补充，在此不再赘述。
与现有技术相比，本公开示例实施方式提供的显示装置的有益效果与上述示例实施方式提供的阵列基板100的有益效果相同，在此不做赘述。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (32)

  1. 一种阵列基板，具有显示区和设于所述显示区至少一侧的过渡区，其中，所述阵列基板包括：
    第一衬底基板；
    绝缘层组，设于所述第一衬底基板的一侧，所述绝缘层组上设置有凹陷部，所述凹陷部位于所述过渡区；
    第一电极层，设于所述绝缘层组背离所述第一衬底基板的一侧；
    导电增强层，设于所述第一电极层背离所述第一衬底基板的一侧，所述导电增强层在所述第一衬底基板上的正投影位于所述第一电极层在所述第一衬底基板上的正投影内。
  2. 根据权利要求1所述的阵列基板，其中，所述绝缘层组上还设置有第一过孔，所述第一过孔位于所述显示区，所述第一过孔在所述第一衬底基板上的正投影面积等于或小于所述凹陷部在所述第一衬底基板上的正投影面积。
  3. 根据权利要求2所述的阵列基板，其中，所述第一电极层上设置有第二过孔和第三过孔，所述第二过孔位于所述显示区，所述第三过孔位于所述过渡区，所述凹陷部在所述第一衬底基板上的正投影位于所述第三过孔在所述第一衬底基板上的正投影之内，所述第一过孔在所述第一衬底基板上的正投影位于所述第二过孔在所述第一衬底基板上的正投影之内。
  4. 根据权利要求3所述的阵列基板，其中，所述第三过孔在所述第一衬底基板上的正投影面积大于或等于所述第二过孔在所述第一衬底基板上的正投影面积。
  5. 根据权利要求4所述的阵列基板，其中，所述凹陷部在所述第一衬底基板上的正投影的边沿线与所述第三过孔在所述第一衬底基板上的正投影的边沿线之间的间距，大于或等于所述第一过孔在所述第一衬底基板上的正投影的边沿线与所述第二过孔在所述第一衬底基板上的正投影的边沿线之间的间距。
  6. 根据权利要求3所述的阵列基板，其中，所述导电增强层包括：
    第一导电条，沿第一方向延伸；
    第二导电条，沿第二方向延伸，所述第二方向与所述第一方向相交，所述第一方向和所述第二方向与所述第一衬底基板靠近所述绝缘层组的一面平行。
  7. 根据权利要求6所述的阵列基板，其中，所述第三过孔在所述第一衬底基板上的正投影的边沿线与相邻的所述第一导电条在所述第一衬底基板上的正投影的边沿线之间的间距，大于或等于所述第二过孔在所述第一衬底基板上的正投影的边沿线与相邻的所述第一导电条在所述第一衬底基板上的正投影的边沿线之间的间距；所述第三过孔在所述第一衬底基板上的正投影的边沿线与相邻的所述第二导电条在所述第一衬底基板上的正投影的边沿线之间的间距，大于或等于所述第二过孔在所述第一衬底基板上的正投影的边沿线与相邻的所述第二导电条在所述第一衬底基板上的正投影的边沿线之间的间距。
  8. 根据权利要求6所述的阵列基板，其中，所述阵列基板还包括：
    开关层组，设于所述第一衬底基板与所述绝缘层组之间，所述开关层组包括：
    多个开关单元，呈阵列排布；
    多根栅线，沿所述第一方向延伸，各个所述栅线位于相邻两个所述开关单元之间，所述第一导电条在所述第一衬底基板上的正投影与所述栅线在所述第一衬底基板上的正投影至少部分交叠；
    多根数据线，沿所述第二方向延伸，各个所述数据线位于相邻两个所述开关单元之间，所述第二导电条在所述第一衬底基板上的正投影与所述数据线在所述第一衬底基板上的正投影至少部分交叠，多根所述栅线与多根所述数据线交叉形成多个像素区域。
  9. 根据权利要求8所述的阵列基板，其中，在所述过渡区的一个所述像素区域内设置有至少两个所述凹陷部，且设置有至少两个所述第三过孔；在所述显示区的一个所述像素区域内设置有一个所述第一过孔，且设置有一个所述第二过孔。
  10. 根据权利要求8所述的阵列基板，其中，位于沿所述第一方向排列的一行所述像素区域内的所述凹陷部和所述第一过孔位于对应所述像素区域内的相同区域。
  11. 根据权利要求8所述的阵列基板，其中，在所述显示区的所述第二方向的一侧所述过渡区内设置有沿所述第一方向排列的仅一行所述像素区域，在所述显示区的所述第一方向的一侧所述过渡区内设置有沿所述第二方向排列的仅一列所述像素区域。
  12. 根据权利要求8所述的阵列基板，其中，在所述过渡区，所述开关单元不包括漏极以及漏极连接引线，所述凹陷部在所述第一衬底基板上的正投影与所述开关单元无交叠。
  13. 根据权利要求12所述的阵列基板，其中，所述凹陷部的最低处与所述第一衬底基板之间的距离小于所述第一过孔的最低处与所述第一衬底基板之间的距离。
  14. 根据权利要求8所述的阵列基板，其中，所述导电增强层还包括：
    多根引线条，所述引线条的一端连接于所述第二导电条，所述引线条沿所述第一方向朝向背离所述显示区的一侧延伸。
  15. 根据权利要求14所述的阵列基板，其中，所述引线条在所述第一衬底基板上的正投影与所述栅线在所述第一衬底基板上的正投影无交叠。
  16. 根据权利要求14所述的阵列基板，其中，所述导电增强层还包括：
    汇总连接条，连接于所述引线条背离所述第二导电条的一端，所述汇总连接条沿所述第二方向延伸。
  17. 根据权利要求8所述的阵列基板，其中，相邻两根所述第二导电条在所述第一衬底基板上的正投影之间设置有两根所述数据线。
  18. 根据权利要求8所述的阵列基板，其中，所述绝缘层组包括：
    第一绝缘层，设于所述第一衬底基板的一侧，所述第一绝缘层上设置有第五过孔，所述第五过孔位于所述显示区，且连通至所述开关单元；
    有机绝缘层，设于所述第一绝缘层背离所述第一衬底基板的一侧，所述有机绝缘层上设置有第六过孔和第七过孔，所述第六过孔为所述凹陷部，所述第七过孔与所述第五过孔 连通形成所述第一过孔。
  19. 根据权利要求18所述的阵列基板，其中，所述阵列基板还包括：
    第二绝缘层，设于所述导电增强层背离所述第一衬底基板的一侧，所述第二绝缘层上设置有第四过孔，所述第七过孔在所述第一衬底基板上的正投影覆盖且大于所述第四过孔在所述第一衬底基板上的正投影，所述第二绝缘层覆盖所述第七过孔的孔侧壁，且覆盖在所述第七过孔内裸露的部分所述第一绝缘层，以使所述第二绝缘层在所述第七过孔内形成台阶部；
    第二电极层，设于所述第二绝缘层背离所述第一衬底基板的一侧，所述第二电极层包括多个第二电极，所述第二电极包括相互连接的本体部和连接部，所述连接部通过所述第四过孔以及所述第五过孔连接至所述开关单元，所述本体部位于所述台阶部背离所述第一衬底基板的一侧。
  20. 根据权利要求19所述的阵列基板，其中，所述阵列基板还包括：
    第一隔垫物，设于所述第二电极层的背离所述第一衬底基板的一侧，且位于相邻两个开关单元之间；
    所述第一导电条在所述第一衬底基板上的正投影设置为曲线，所述第一导电条在与所述第一隔垫物相邻的位置向远离所述第一隔垫物一侧折弯。
  21. 根据权利要求20所述的阵列基板，其中，所述第一导电条在所述第一衬底基板上的正投影与所述第一隔垫物在所述第一衬底基板上的正投影无交叠。
  22. 根据权利要求20所述的阵列基板，其中，所述第一导电条包括第一直线部和第一弯曲部，所述第一直线部在所述第一衬底基板上的正投影位于所述栅线在所述第一衬底基板上的正投影内，所述第一弯曲部在所述第一衬底基板上的正投影至少部分与所述栅线在所述第一衬底基板上的正投影不交叠。
  23. 根据权利要求1所述的阵列基板，其中，所述阵列基板还具有外围区，所述外围区设于所述过渡区背离所述显示区的一侧，在所述外围区设置有多根外围引线，在第三方向上，所述绝缘层组在所述外围区的高度高于所述绝缘层组在所述显示区的高度，所述第三方向与所述第一衬底基板靠近所述绝缘层组的一面垂直。
  24. 根据权利要求23所述的阵列基板，其中，所述凹陷部靠近所述显示区一侧的边沿线与显示区之间的距离大于，所述凹陷部靠近所述外围区一侧的边沿线与所述外围区之间的距离。
  25. 根据权利要求1所述的阵列基板，其中，所述导电增强层在所述第一衬底基板上的正投影与所述凹陷部在所述第一衬底基板上的正投影无交叠。
  26. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括：
    保护层，设于所述导电增强层背离所述第一衬底基板的一侧。
  27. 一种阵列基板的制备方法，其中，包括：
    提供第一衬底基板，所述第一衬底基板具有显示区和设于显示区至少一侧的过渡区， 在所述第一衬底基板的一侧形成绝缘层组，在所述绝缘层组上形成凹陷部，所述凹陷部位于所述过渡区；
    在所述绝缘层组背离所述第一衬底基板的一侧依次形成第一电极材料层和导电增强材料层；
    在所述导电增强材料层背离所述第一衬底基板的一侧形成掩模层，部分所述掩模层形成在所述凹陷部内，所述显示区的所述掩模层的厚度一致；
    以所述掩模层为掩模对所述第一电极材料层进行图案化处理形成第一电极层，且对所述导电增强材料层进行图案化处理形成导电增强层。
  28. 根据权利要求27所述的阵列基板的制备方法，其中，在形成所述凹陷部的同时，在所述绝缘层组上形成第一过孔，所述第一过孔位于所述显示区，所述第一过孔在所述第一衬底基板上的正投影面积等于或小于所述凹陷部在所述第一衬底基板上的正投影面积。
  29. 根据权利要求28所述的阵列基板的制备方法，其中，以所述掩模层为掩模对所述第一电极材料层进行图案化处理形成第一电极层，且对所述导电增强材料层进行图案化处理形成导电增强层，包括：
    对所述掩模层进行半掩模工艺形成掩模图案，所述掩模图案包括第一部分和第二部分，所述第一部分的厚度大于所述第二部分的厚度，所述第二部分上形成有第九过孔，一部分所述第九过孔与所述第一过孔相对设置，另一部分所述第九过孔与所述凹陷部相对设置；
    对与所述第九过孔相对的部分所述导电增强材料层进行刻蚀去除；
    对所述掩模图案进行灰化处理，以去除所述第二部分，使所述第二部分覆盖的所述导电增强材料层裸露；
    对与所述第九过孔相对的部分所述第一电极材料层进行刻蚀去除，形成所述第一电极层；
    对剩余的所述导电增强材料层进行图案化处理形成导电增强层。
  30. 一种显示面板，其中，包括：
    阵列基板，是权利要求1～26任意一项所述的阵列基板；
    彩膜基板，与所述阵列基板相对设置，所述彩膜基板包括黑矩阵，导电增强层在第一衬底基板上的正投影位于所述黑矩阵在第一衬底基板上的正投影内。
  31. 一种显示面板，其中，包括：
    阵列基板，是权利要求20～22任意一项所述的阵列基板；
    彩膜基板，与所述阵列基板相对设置，所述彩膜基板包括黑矩阵，导电增强层在第一衬底基板上的正投影位于所述黑矩阵在第一衬底基板上的正投影内，所述黑矩阵靠近第一导电条的一侧边沿线设置为与所述第一导电条相适配的曲线。
  32. 一种显示装置，其中，包括：权利要求30或31所述的显示面板。
PCT/CN2022/141368 2022-12-23 2022-12-23 阵列基板及其制备方法、显示面板、显示装置 WO2024130695A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/141368 WO2024130695A1 (zh) 2022-12-23 2022-12-23 阵列基板及其制备方法、显示面板、显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/141368 WO2024130695A1 (zh) 2022-12-23 2022-12-23 阵列基板及其制备方法、显示面板、显示装置

Publications (1)

Publication Number Publication Date
WO2024130695A1 true WO2024130695A1 (zh) 2024-06-27

Family

ID=91587363

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/141368 WO2024130695A1 (zh) 2022-12-23 2022-12-23 阵列基板及其制备方法、显示面板、显示装置

Country Status (1)

Country Link
WO (1) WO2024130695A1 (zh)

Similar Documents

Publication Publication Date Title
US8860898B2 (en) Array substrate and liquid crystal display
KR102081599B1 (ko) 액정표시장치용 어레이 기판 및 그 제조방법
CN109387985B (zh) 显示装置
JP3880568B2 (ja) 液晶表示装置の製造方法
WO2020133651A1 (zh) 像素电极结构及其制作方法
CN105679714A (zh) 阵列基板及其制作方法
CN111736393B (zh) 一种显示基板及其制备方法和液晶显示组件
JP4488688B2 (ja) 表示装置用配線基板及びその製造方法
US7982837B2 (en) Liquid crystal display device and its manufacturing method
CN113467145B (zh) 阵列基板及制作方法、显示面板
WO2015180302A1 (zh) 阵列基板及其制备方法、显示装置
CN113568230B (zh) 阵列基板及制作方法、显示面板
WO2024130695A1 (zh) 阵列基板及其制备方法、显示面板、显示装置
KR20070114472A (ko) 프린지 필드 스위칭 모드 액정표시장치 및 그 제조방법
CN113985662B (zh) 显示面板、阵列基板及其制造方法
CN203455564U (zh) 阵列基板及显示装置
KR20090100046A (ko) 액정표시장치용 어레이 기판의 제조방법
WO2023050271A1 (zh) 阵列基板及制备方法、显示面板及制备方法、显示装置
KR20080086062A (ko) 액정표시장치의 어레이 기판 및 그의 제조방법
JP4072561B2 (ja) 液晶表示装置の製造方法
KR20110018577A (ko) 액정표시장치용 어레이 기판 및 그 제조방법
KR102066020B1 (ko) 산화물 반도체를 이용한 표시장치용 어레이기판 및 그 제조방법
CN113690257B (zh) 阵列基板及其制作方法和显示面板
JPH03132626A (ja) 半導体装置と半導体装置の製造方法
US20240222392A1 (en) Array substrate and display panel