WO2023050271A1 - 阵列基板及制备方法、显示面板及制备方法、显示装置 - Google Patents

阵列基板及制备方法、显示面板及制备方法、显示装置 Download PDF

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Publication number
WO2023050271A1
WO2023050271A1 PCT/CN2021/122086 CN2021122086W WO2023050271A1 WO 2023050271 A1 WO2023050271 A1 WO 2023050271A1 CN 2021122086 W CN2021122086 W CN 2021122086W WO 2023050271 A1 WO2023050271 A1 WO 2023050271A1
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Prior art keywords
layer
base substrate
electrode
orthographic projection
material layer
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PCT/CN2021/122086
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English (en)
French (fr)
Inventor
叶成枝
操彬彬
吕艳明
安晖
马金念
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180002779.9A priority Critical patent/CN116210080A/zh
Priority to PCT/CN2021/122086 priority patent/WO2023050271A1/zh
Priority to US17/908,036 priority patent/US20240213271A1/en
Publication of WO2023050271A1 publication Critical patent/WO2023050271A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • the present disclosure relates to the field of display technology, in particular, to an array substrate and a method for preparing the array substrate, a display panel including the array substrate, a method for preparing the display panel, and a display device including the display panel.
  • the purpose of the present disclosure is to overcome the shortcomings of the above-mentioned prior art, and provide an array substrate and a manufacturing method, a display panel and a manufacturing method, and a display device.
  • a method for preparing an array substrate including:
  • a mask pattern is formed on a side of the protective material layer away from the first electrode material layer, the mask pattern includes a first part and a second part, the thickness of the first part is greater than the thickness of the second part ;
  • Patterning the protection material layer and the conduction enhancement material layer corresponds to forming a protection layer and a conduction enhancement layer.
  • the preparation method before ashing the mask pattern, the preparation method further includes:
  • Patterning is performed on the protection material layer and the conduction enhancing material layer to expose part of the first electrode material layer.
  • forming a mask pattern on a side of the protective material layer away from the first electrode material layer includes:
  • a mask layer is formed on a side of the protective material layer away from the first electrode material layer, and a half-mask process is performed on the mask layer to form the mask pattern.
  • the preparation method before forming the first electrode material layer, the preparation method further includes:
  • An organic insulating material layer is formed, and the organic insulating material layer is patterned to form an organic insulating layer and a second via hole.
  • the preparation method before forming the first electrode material layer, the preparation method further includes:
  • a plurality of grid lines and a plurality of thin film transistors arranged in an array are formed on one side of the base substrate, and the orthographic projection of the conduction enhancement layer on the base substrate is the same as that of the gate lines on the base substrate.
  • the orthographic projections overlap, and the orthographic projections of the protection layer on the base substrate overlap with the orthographic projections of the grid lines on the base substrate.
  • the preparation method further includes:
  • a second electrode is formed on a side of the second insulating layer away from the first electrode, and the second electrode is electrically connected to the data line of the thin film transistor.
  • a method for manufacturing a display panel including:
  • An array substrate is provided, and the array substrate is prepared by any one of the above-mentioned preparation methods;
  • a color filter substrate is provided, and the color filter substrate is combined with the array substrate.
  • the color filter substrate includes a black matrix, and the orthographic projection of the conductive enhancement layer on the base substrate is located at the position of the black matrix.
  • the orthographic projection of the protection layer on the base substrate is located within the orthographic projection of the black matrix on the base substrate.
  • an array substrate including:
  • a conductive enhancement layer disposed on one side of the first electrode
  • a protective layer is disposed on a side of the conduction enhancement layer away from the first electrode, and the oxidation resistance of the protection layer is stronger than that of the conduction enhancement layer.
  • the orthographic projection of the conductive enhancement layer on the first electrode coincides with the orthographic projection of the protection layer on the first electrode.
  • the array substrate further includes:
  • a plurality of thin film transistors and a plurality of gate lines, the plurality of thin film transistor arrays are arranged on one side of the base substrate, and the orthographic projection of the conduction enhancement layer on the base substrate is in line with the gate lines.
  • the orthographic projections on the base substrate overlap, and the orthographic projections of the protection layer on the base substrate overlap with the orthographic projections of the gate lines on the base substrate.
  • the extension direction of the conduction enhancement layer is consistent with the extension direction of the gate lines
  • the orthographic projection of the conduction enhancement layer on the base substrate is at least partially located on the In the orthographic projection of the grid lines on the base substrate
  • the extension direction of the protection layer is consistent with the extension direction of the grid lines
  • the orthographic projection of the protection layer on the base substrate is at least partly located on the The gridlines are within an orthographic projection on the substrate substrate.
  • the array substrate further includes:
  • the first spacer is arranged on the side of the first electrode away from the base substrate, and is located between two adjacent thin film transistors;
  • the orthographic projection of the conduction enhancement layer on the base substrate is set as a curve, and the conduction enhancement layer is concavely folded toward a side away from the first spacer at a position adjacent to the first spacer.
  • the orthographic projection of the protective layer on the base substrate is set as a curve, and the protective layer is concavely folded toward the side away from the first spacer at a position adjacent to the first spacer bend.
  • the conduction enhancement layer includes a first straight line portion and a first curved portion, and the orthographic projection of the first straight line portion on the base substrate is located at the gate In the orthographic projection of the line on the base substrate, the orthographic projection of the first curved portion on the base substrate at least partially does not overlap with the orthographic projection of the grid line on the base substrate;
  • the protective layer includes a second straight line portion and a second curved portion, the orthographic projection of the second straight line portion on the base substrate is located within the orthographic projection of the grid lines on the base substrate, the The orthographic projection of the second curved portion on the base substrate does not overlap at least part of the orthographic projection of the grid lines on the base substrate.
  • the array substrate includes thin film transistors and data lines
  • the extension direction of the conduction enhancement layer is consistent with the extension direction of the data lines
  • the conduction enhancement layer is on the substrate
  • the orthographic projection on the base substrate is at least partly located within the orthographic projection of the data line on the base substrate
  • the extension direction of the protection layer is consistent with the extension direction of the data line
  • the protection layer is on the backing
  • the orthographic projection on the base substrate is at least partially within the orthographic projection of the data line on the base substrate.
  • the array substrate includes thin film transistors and gate lines
  • the extension direction of the conduction enhancement layer is consistent with the extension direction of the gate lines
  • the conduction enhancement layer is located on the thin film
  • the extension direction of the protection layer is consistent with the extension direction of the gate line
  • the protection layer is located on the side of the thin film transistor away from the gate line.
  • the array substrate further includes:
  • the organic insulating layer is arranged between the plurality of thin film transistors and the first electrode.
  • the array substrate further includes:
  • a second insulating layer disposed on a side of the first electrode away from the base substrate
  • the second electrode is disposed on a side of the second insulating layer away from the base substrate, and the second electrode is electrically connected to the data line of the thin film transistor.
  • the protective layer is made of titanium alloy and has a thickness greater than or equal to 300A and less than or equal to 500A.
  • the titanium alloy includes at least three metal materials.
  • the material of the conduction enhancement layer is copper, and the thickness is greater than or equal to 1000A and less than or equal to 1500A.
  • the first electrode is a common electrode made of ITO.
  • a display panel including:
  • the array substrate is the array substrate described in any one of the above;
  • the color filter substrate is arranged opposite to the array substrate, the color filter substrate includes a black matrix, and the orthographic projection of the conductive enhancement layer on the base substrate is located at the front of the black matrix on the base substrate In projection, the orthographic projection of the protective layer on the base substrate is located within the orthographic projection of the black matrix on the base substrate.
  • a display device including: the above-mentioned display panel.
  • a protective material layer is formed on the side of the conductivity-enhancing material layer away from the first electrode material layer, and the oxidation resistance of the protection material layer is stronger than that of the conductivity-enhancing material layer.
  • the material layer away from the first electrode material layer forms a mask pattern, the mask pattern includes a first part and a second part, the thickness of the first part is greater than the thickness of the second part; the mask pattern is ashed to remove the second part so that The protective material layer covered by the second part is exposed; the first electrode material layer is patterned to form the first electrode; the protective material layer and the conduction enhancement material layer are patterned to form the protection layer and the conduction enhancement layer.
  • the patterning of the first electrode material layer and the patterning of the conductive enhancement material layer and the protective material layer can be completed through one mask, which reduces production costs and improves production line productivity; on the other hand, in the When the mask pattern is ashed, there is a protective material layer to protect the conductive enhancing material layer, so as to avoid oxidation and corrosion of the conductive enhancing material layer during the ashing process, thereby avoiding the formation of the first electrode material layer after the patterning process. electrode, the first electrode is etched, resulting in poor disconnection of the first electrode; on the other hand, the conductive enhancement material layer can effectively reduce the resistance of the first electrode, improve the uniformity of the first electrode, thereby effectively improving the display The color cast is bad.
  • FIG. 1 is a schematic block diagram of an exemplary embodiment of a manufacturing method of an array substrate of the present disclosure.
  • 2 to 14 are structural schematic diagrams of various steps in the method for preparing the array substrate of the present disclosure.
  • FIG. 15 is a schematic structural diagram of an exemplary embodiment of an array substrate of the present disclosure.
  • FIG. 16 is a schematic top view of the array substrate shown in FIG. 15 .
  • FIG. 17 is a schematic block diagram of an exemplary embodiment of a manufacturing method of a display panel of the present disclosure.
  • FIG. 18 is a schematic structural diagram of an exemplary embodiment of a display panel of the present disclosure.
  • Substrate substrate 2. Buffer layer; 3. Gate line; 31. Gate; 4. Gate insulating layer; 5. Data line; 51. Source;
  • First electrode material layer 811. First electrode; 812. Third via hole; 82.
  • Conductive enhancement material layer 821.
  • Color filter substrate 131. Base layer; 132. Black matrix; 133. Filter unit;
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • An exemplary embodiment of the present disclosure provides a method for preparing an array substrate.
  • the method for preparing an array substrate may include the following steps:
  • Step S10 sequentially forming a first electrode material layer, a conductivity enhancing material layer and a protection material layer, the oxidation resistance of the protection material layer is stronger than that of the conductivity enhancement material layer.
  • Step S20 forming a mask pattern on a side of the protective material layer away from the first electrode material layer, the mask pattern includes a first part and a second part, the thickness of the first part is greater than that of the second part thickness.
  • Step S30 ashing the mask pattern to remove the second portion to expose the protective material layer covered by the second portion.
  • Step S40 patterning the first electrode material layer to form a first electrode.
  • Step S50 patterning the protection material layer and the conduction enhancement material layer to form a protection layer and a conduction enhancement layer.
  • the method for preparing the array substrate of the present disclosure can complete the patterning of the first electrode material layer 81 and the patterning of the conductive enhancement material layer 82 and the protective material layer through one mask, reducing production costs, Improve the productivity of the production line; on the other hand, when the mask pattern 92 is ashed, the protective material layer 83 protects the conductive enhancing material layer 82, so as to avoid oxidation and corrosion of the conductive enhancing material layer 82 during the ashing process, thereby Avoid etching the first electrode 811 when the first electrode material layer 81 is patterned to form the first electrode 811, resulting in poor disconnection of the first electrode 811; on the other hand, the conductivity-enhancing material layer 82 can The resistance of the first electrode 811 is effectively reduced, and the uniformity of the first electrode 811 is improved, thereby effectively improving the poor color cast of the display.
  • step S10 a first electrode material layer 81 , a conductivity enhancing material layer 82 and a protection material layer 83 are sequentially formed, the oxidation resistance of the protection material layer 83 is stronger than that of the conductivity enhancement material layer 82 .
  • a base substrate 1 is provided, and the base substrate 1 may be a rigid substrate, for example, a glass substrate.
  • a buffer layer 2 may be formed on one side of the base substrate 1 .
  • a gate material layer is formed by sputtering a metal coating, and a gate pattern is formed by photolithography on the gate material layer.
  • the gate pattern may include a gate 31 and a gate line 3, The gate 31 is connected to the gate line 3 .
  • the gate insulation can be formed by PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition method) deposition.
  • PECVD Plasma enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition method
  • An active material layer may be formed by PECVD deposition on the side of the gate insulating layer 4 away from the base substrate 1 . Photolithography is performed on the active material layer to form the active layer 16 .
  • a source-drain material layer can be formed by sputtering metal coating deposition, and the source-drain material layer can be photo-treated.
  • Engraving forms source-drain pattern, and source-drain pattern can comprise data line 5, source and drain (not shown in the figure), and source and drain are all connected to active layer 16, and data line 5 and source or drain connection.
  • the TFTs described above are bottom-gate TFTs.
  • the TFTs may also be top-gate TFTs or dual-gate TFTs.
  • Its preparation method is not described in detail.
  • the first insulating layer 61 can be formed by PECVD deposition on the side of the source-drain pattern away from the base substrate 1, and the first insulating layer 61 is photolithographically formed on the first insulating layer 61.
  • a via hole 62 , the first via hole 62 is connected to the data line 5 , that is, the data line 5 at the first via hole 62 is exposed.
  • an organic insulating layer 71 can be formed by PECVD deposition, and the organic insulating layer 71 is photolithographically formed on the organic insulating layer 71.
  • the second via hole 72 is connected to the first via hole 62 , that is, the data line 5 at the second via hole 72 is exposed.
  • the material of the organic insulating layer 71 can be PAC (Photo active compound, photoactive compound).
  • the thickness of the organic insulating layer 71 is greater than or equal to 2 microns and less than or equal to 3 microns, for example, the thickness of the organic insulating layer 71 may be 2.4 microns.
  • the organic insulating layer 71 can play a role in planarization, providing a relatively flat base for the subsequently formed first electrode 811, facilitating the formation of the first electrode 811, thereby improving the uniformity of the first electrode 811; in addition, the organic insulating layer 71
  • the distance between the first electrode 811 and the data line 5 in the thickness direction is increased, the mutual influence is weakened, and the parasitic capacitance is also reduced a lot, which is more conducive to the driving of the driver chip; the thickness between the first electrode 811 and the data line 5 After the distance in one direction increases, the distance between the first electrode 811 and the data line 5 in other directions (for example, in a direction parallel to the base substrate 1) can be shortened, so that the width of the black matrix 132 of the color filter substrate 13 It can also be made smaller, thereby increasing the opening ratio of the product.
  • a first electrode material layer 81 can be formed by sputtering metal coating, the material of the first electrode material layer 81 can be ITO, the first electrode material The thickness of the layer 81 is greater than or equal to 400A and less than or equal to 700A, for example, the thickness of the first electrode material layer 81 may be 550A. Of course, the material of the first electrode material layer 81 can also be other conductive materials.
  • a conductive enhancing material layer 82 can be formed by sputtering metal coating, the material of the conductive enhancing material layer 82 can be copper, and the thickness of the conductive enhancing material layer 82 is greater than or equal to 1000 ⁇ . And less than or equal to 1500A, for example, the thickness of the conduction enhancing material layer 82 may be 1200A.
  • the material of the conduction enhancing material layer 82 may also be other metal materials such as aluminum and silver.
  • a protective material layer 83 can be formed by sputtering metal coating, the material of the protective material layer 83 can be MoNbTi, and the thickness of the protective material layer 83 is greater than or equal to 300A and less than or equal to 500A
  • the thickness of the protective material layer 83 may be 400A.
  • the material of the protective material layer 83 may also be other titanium alloys, as long as the oxidation resistance of the protective material layer 83 is stronger than that of the conductivity-enhancing material layer 82 .
  • Oxidation resistance refers to the ability of metal materials to resist the corrosion of oxidizing atmospheres at high temperatures. Materials with weak oxidation resistance (such as MoNb) react with the ashing gas to affect the plasma balance and cause Arcing (arc) alarms. Therefore, materials with stronger oxidation resistance are used.
  • the thickness of the above-mentioned first electrode material layer 81, the thickness of the conductivity enhancing material layer 82 and the thickness of the protective material layer 83 are all the data obtained by the inventor through numerous tests, the uniformity of the film formation is better, and the conductive effect is better, Higher efficiency. Because, too thick is not conducive to light and thin display panels, and the film forming time is long and the efficiency is low; too thin, the uniformity is not good, and the defect of disconnection is easy to occur.
  • Step S20 forming a mask pattern 92 on a side of the protective material layer 83 away from the first electrode material layer 81, the mask pattern 92 includes a first portion 921 and a second portion 922, the first portion 921 The thickness is greater than the thickness of the second portion 922 .
  • the arrows in the figure indicate the irradiating light, and the denser the arrows, the more the light passing through; on the contrary, the thinner the arrows, the less the light passing through;
  • the side away from the base substrate 1 may form a mask layer 91 by PECVD deposition, and perform a half-mask process on the mask layer 91 to form a mask pattern 92.
  • the mask pattern 92 may include a first portion 921 and a second portion 922, The thickness of the first part 921 is greater than the thickness of the second part 922 .
  • the mask plate 10 is placed on the side of the mask layer 91 away from the base substrate 1.
  • the mask plate 10 may include a light-transmitting portion 101, a light-shielding portion 102, and a semi-transparent portion 103; the semi-transparent portion 103 and the second
  • the part 922 is arranged opposite to each other, that is, the orthographic projection of the semi-transparent part 103 on the base substrate 1 coincides with the orthographic projection of the second part 922 on the base substrate 1;
  • the orthographic projection on the base substrate 1 coincides with the orthographic projection of the first portion 921 on the base substrate 1 .
  • the transparent portion 101 is disposed opposite to other portions of the mask layer 91 .
  • the mask layer 91 is exposed and developed, and the mask layer 91 arranged opposite to the light-transmitting portion 101 is removed, so that part of the protective material layer 83 is exposed; the mask arranged opposite to the semi-transparent portion 103 A certain thickness of the layer 91 is removed to form the second part 922 ; the mask layer 91 opposite to the light shielding part 102 is completely retained to form the first part 921 , so that the thickness of the first part 921 is greater than that of the second part 922 .
  • the exposed protective material layer 83 and the conduction enhancing material layer 82 opposite to this part of the protective material layer 83 are etched for the first time, and the protective material layer 83 covered by the mask pattern 92 remains. and a layer 82 of conductive enhancing material.
  • Step S30 ashing the mask pattern 92 to remove the second portion 922 to expose the protective material layer 83 covered by the second portion 922 .
  • an ashing process is performed on the mask pattern 92 , and the gas used in the ashing process may include SF6 and O2.
  • the gas used in the ashing process has strong oxidizing properties. Since the oxidation resistance of the protective material layer 83 is stronger than that of the conductivity-enhancing material layer 82, and the protective material layer 83 covers the conductivity-enhancing material layer 82, therefore , the protective material layer 83 can protect the conductive enhancement material layer 82, avoiding the oxidation and corrosion of the conductive enhancement material layer 82 by the oxidizing gas when the mask pattern 92 is ashed, thereby avoiding the conductive enhancement material layer 82 A disconnect occurs.
  • the second portion 922 is removed by an ashing process, so that the protective material layer 83 covered by the second portion 922 is exposed, and the thickness of the first portion 921 is also reduced.
  • Step S40 patterning the first electrode material layer 81 to form a first electrode 811 .
  • a third via hole 812 is formed on the first electrode 811, and the third via hole 812 communicates with the second via hole 72, that is, the data line 5 at the third via hole 812 is exposed. Since there is no disconnection on the conduction-enhancing material layer 82, the first electrode material layer covered by the protective material layer 83 and the conduction-enhancing material layer 82 will not be damaged during the etching process of the first electrode material layer 81. 81 is etched, so as to avoid the defect of disconnection on the first electrode 811 .
  • the first electrode 811 may be a common electrode.
  • Step S50 patterning the protection material layer 83 and the conduction enhancement material layer 82 to form a protection layer 831 and a conduction enhancement layer 821 .
  • the protective material layer 83 and the conductivity enhancing material layer 82 are etched using the first portion 921 as a mask to form the protective layer 831 and the conductivity enhancing layer 821 .
  • the orthographic projection of the conductive enhancement layer 821 on the base substrate 1 is substantially coincident with the orthographic projection of the protective layer 831 on the base substrate 1 .
  • the orthographic projection of the conduction enhancement layer 821 on the base substrate 1 overlaps the orthographic projection of the grid line 3 on the base substrate 1, specifically, the orthographic projection of the conduction enhancement layer 821 on the base substrate 1 is located at the gate line 3
  • the orthographic projection on the base substrate 1 that is, the extension direction of the protection layer 831 and the conduction enhancement layer 821 is consistent with the extension direction of the gate line 3
  • the width of the protection layer 831 and the conduction enhancement layer 821 is slightly smaller than the width of the gate line 3 .
  • the width of the conduction enhancement layer 821 is about 3.5 microns
  • the width of the protection layer 831 is also about 3.5 microns
  • the width of the grid lines 3 is about 4.5 microns.
  • the protective layer 831 and the conductive enhancement layer 821 are both made of metal, they are opaque and reflective. Therefore, in order to prevent their reflection from affecting the display effect, they need to be blocked by the black matrix 132, and the grid lines 3 are also passed through The black matrix 132 blocks it, and the orthographic projection of the conductive enhancement layer 821 on the base substrate 1 is located within the orthographic projection of the grid line 3 on the base substrate 1, which can avoid increasing the width of the black matrix 132, thereby avoiding reducing the opening Rate.
  • the protection layer 831 and the conduction enhancement layer 821 can be disposed on the side close to the data line 5, but since the data line 5 needs to be connected to the pixel electrode through a via hole, the conduction enhancement The orthographic projection of the layer 821 on the base substrate 1 and the orthographic projection of the grid lines 3 on the base substrate 1 still need to overlap.
  • the conduction enhancement layer 821 is disposed on the side of the first electrode 811 away from the substrate 1 and connected to the first electrode 811.
  • the conduction enhancement layer 821 can reduce the resistance of the first electrode 811, thereby increasing the conductivity of the first electrode 811. effect, and the conductive enhancement layer 821 can improve the uniformity of the first electrode 811, effectively improve the poor display color shift;
  • the material of the protective layer 831 is also a metal, which is a conductive material, so the protective layer 831 can further reduce the size of the first electrode. 811, so as to further increase the conductive effect of the first electrode 811, which can also improve the uniformity of the first electrode 811, and effectively improve the defect of display color shift.
  • the structure of the combination of the organic insulating film layer and the conduction enhancing layer 821 has the above-mentioned many beneficial effects, if the formation of the organic insulating film layer and the conduction enhancing layer 821 uses two masking processes, it will lead to increased costs, Production capacity is reduced; in order to reduce the number of masking processes, it is necessary to realize the preparation of the organic insulating film layer and the conductive enhancement layer 821 through a masking process; however, since the ashing process has an etching effect on the organic insulating layer 71, it is necessary to first Perform the ashing process and then perform the patterning treatment of the first electrode material layer 81.
  • the first electrode material layer 81 When the mask pattern 92 is subjected to the ashing process, the first electrode material layer 81 has a protective effect on the organic insulating layer 71, avoiding the ashing process. Etching of the organic insulating layer 71. However, the ashing process also has an oxidation and corrosion effect on the conductive enhancing material layer 82. In this disclosure, the conductive enhancing material layer 82 is protected by a protective material layer 83 with strong oxidation resistance, so as to avoid damage to the conductive enhancing material layer 82 during the ashing process. Oxidation corrosion occurs, thereby avoiding the defect that the layer of the first electrode 811 covered by the conductivity-enhancing material layer 82 is disconnected.
  • a second insulating layer 111 is formed on the side of the protective layer 831 and the first electrode 811 away from the base substrate 1 , and on the side of the second insulating layer 111 away from the substrate
  • a photoresist is formed on one side of the substrate 1, and the photoresist is exposed and developed to form a photoresist pattern; then, the second insulating layer 111 is etched using the photoresist pattern as a mask, so that the second insulating layer 111 A fourth via hole 112 is formed on it, and the fourth via hole 112 communicates with the third via hole 812 , that is, the data line 5 at the fourth via hole 112 is exposed; finally, the photoresist pattern is removed.
  • a second electrode material layer is formed on a side of the second insulating layer 111 away from the base substrate 1 , and the material of the second electrode material layer may be ITO. Then, photolithography is performed on the second electrode material layer to form the second electrode 12 .
  • the second electrode 12 is connected to the data line 5 through the fourth via hole 112 , the third via hole 812 , the second via hole 72 and the first via hole 62 , and the second electrode 12 can also be connected to the source or the drain.
  • the second electrode 12 may be a pixel electrode.
  • the second electrode 12 may be formed on the side of the organic insulating layer 71 away from the base substrate 1, and the second electrode 12 may be a pixel electrode,
  • the second electrode 12 is connected to the data line 5 through the first via hole 62 on the first insulating layer 61 and the second via hole 72 on the organic insulating layer 71; formed on the side of the second electrode 12 away from the base substrate 1
  • the second insulating layer 111; on the side of the second insulating layer 111 away from the base substrate 1, the first electrode material layer 81, the conductivity enhancing material layer 82 and the protective material layer 83 are sequentially stacked;
  • the etching method of the material layer 81 , the conductivity-enhancing material layer 82 and the protection material layer 83 is etched. The specific etching method has been described in detail above, so it will not be repeated here.
  • each film layer can be formed by sputtering metal coating or PECVD deposition. These descriptions are only for illustration and do not constitute a limitation to the present disclosure. In other exemplary embodiments of the present disclosure, each film layer can also be formed by Coating, printing, and other methods of chemical vapor deposition all fall within the protection scope of the present disclosure.
  • exemplary embodiments of the present disclosure also provide an array substrate, as shown in FIG.
  • the oxidation resistance is stronger than that of the conductivity enhancing layer 821 .
  • the array substrate may further include a base substrate 1, and the base substrate 1 may be a rigid substrate, for example, a glass substrate.
  • a buffer layer 2 is provided on one side of the base substrate 1 .
  • a gate pattern is provided on a side of the buffer layer 2 away from the base substrate 1 , and the gate pattern may include a gate 31 and a gate line 3 .
  • a gate insulating layer 4 is provided on a side of the gate pattern away from the base substrate 1 .
  • An active layer 16 is arranged on the side of the gate insulating layer 4 away from the base substrate 1, and a source-drain pattern is arranged on the side of the active layer 16 away from the base substrate 1, and the source-drain pattern may include a data line. 5.
  • Source and drain, the source and the drain are both connected to the active layer 16, and the data line 5 is connected to the source or the drain.
  • the gate 31 , the active layer 16 , the source and the drain form a thin film transistor, and a plurality of thin film transistor arrays are arranged on one side of the base substrate 1 .
  • the thin film transistor described above is a bottom-gate thin film transistor.
  • the thin film transistor may also be a top-gate thin film transistor or a double-gate thin film transistor, which will not be described in detail here.
  • a first insulating layer 61 is provided on the side of the source-drain pattern away from the base substrate 1, and a first via hole 62 is provided on the first insulating layer 61, and the first via hole 62 is connected to the data line 5.
  • An organic insulating layer 71 is disposed on the side of the first insulating layer 61 away from the base substrate 1, and a second via hole 72 is disposed on the organic insulating layer 71, and the second via hole 72 communicates with the first via hole 62, namely The second via hole 72 is also connected to the data line 5 .
  • a first electrode 811 is provided on the side of the organic insulating layer 71 away from the base substrate 1, and a third via hole 812 is provided on the first electrode 811.
  • the third via hole 812 communicates with the second via hole 72, that is, the first electrode 811
  • the three vias 812 are also connected to the data line 5 .
  • the first electrode 811 may be a common electrode.
  • a conduction enhancement layer 821 is provided, and the orthographic projection of the conduction enhancement layer 821 on the base substrate 1 overlaps with the orthographic projection of the gate line 3 on the base substrate 1. .
  • a protection layer 831 is provided on the side of the conduction enhancement layer 821 away from the base substrate 1, and the orthographic projection of the protection layer 831 on the base substrate 1 is substantially coincident with the orthographic projection of the conduction enhancement layer 821 on the base substrate 1, so that The orthographic projection of the protective layer 831 on the base substrate 1 and the orthographic projection of the grid lines 3 on the base substrate 1 also overlap. Due to the process, the orthographic projection of the protection layer 831 on the base substrate 1 is located within the orthographic projection of the conduction enhancement layer 821 on the base substrate 1 , that is, the protection layer 831 is slightly smaller than the conduction enhancement layer 821 .
  • the material of the first electrode 811 may be ITO, and the thickness of the first electrode 811 may be greater than or equal to 400A and less than or equal to 700A.
  • the thickness of the first electrode 811 may be 550A.
  • the material of the first electrode 811 can also be other conductive materials.
  • the material of the conduction enhancement layer 821 may be copper, and the thickness of the conduction enhancement layer 821 is greater than or equal to 1000A and less than or equal to 1500A, for example, the thickness of the conduction enhancement layer 821 may be 1200A.
  • the material of the conduction enhancement layer 821 may also be other metal materials such as aluminum and silver.
  • the material of the protection layer 831 may be MoNbTi, and the thickness of the protection layer 831 may be greater than or equal to 300A and less than or equal to 500A.
  • the thickness of the protection layer 831 may be 400A.
  • the material of the protective layer 831 may also be other titanium alloys, for example, it may be a titanium alloy including three metal materials, or it may be a titanium alloy including four metal materials, which Strong oxidation resistance, as long as the oxidation resistance of the protection layer 831 is stronger than that of the conductivity enhancing layer 821 .
  • the conduction enhancement layer 821 is arranged in multiples, and the plurality of conduction enhancement layers 821 are arranged in parallel with each other; the conduction enhancement layer 821 and the gate line 3 may have a one-to-one correspondence, that is, at a distance from a gate line 3
  • One side of the base substrate 1 is provided with a conductive enhancement layer 821 .
  • the protective layer 831 is also in one-to-one correspondence with the grid lines 3, that is, at the distance from the substrate of a grid line 3
  • One side of the substrate 1 is provided with a protective layer 831 .
  • a plurality of grid lines 3 are substantially evenly arranged on the array substrate, and a plurality of conduction enhancement layers 821 and a plurality of protective layers 831 correspond to the plurality of gate lines 3 one-to-one, so that the plurality of conduction enhancement layers 821 and the plurality of protection layers 831 are also It is evenly arranged on the array substrate, so that the resistance of the first electrode 811 is more uniform, and the display color shift is effectively improved.
  • the extension direction of the conduction enhancement layer 821 is consistent with the extension direction of the grid lines 3
  • the orthographic projection of the conduction enhancement layer 821 on the base substrate 1 is at least partly located on the grid line 3 .
  • the extension direction of the protection layer 831 is consistent with the extension direction of the grid lines 3
  • the orthographic projection of the protection layer 831 on the base substrate 1 is at least partially located at the front of the grid lines 3 on the base substrate 1. inside the projection.
  • the array substrate may further include a first spacer 141, and the first spacer 141 is disposed on the side of the first electrode 811 away from the base substrate 1, specifically, the first spacer 141 is disposed on the side of the second electrode 12. The side away from the base substrate 1 .
  • the first spacer 141 can be arranged as a rectangular truncated structure, that is, the cross section of the first spacer 141 parallel to the base substrate 1 is rectangular, and the area of the bottom surface close to the base substrate 1 is larger than that far away from the base substrate 1.
  • the area of the top surface; the length of the bottom surface of the first spacer 141 is greater than or equal to 19.6 microns and less than or equal to 21.6 microns, for example, the length of the bottom surface of the first spacer 141 can be 20.6 microns; the length of the first spacer 141
  • the width of the bottom surface is greater than or equal to 16 microns and less than or equal to 18 microns, for example, the width of the bottom surface of the first spacer 141 can be 17 microns; the height of the first spacer 141 is greater than or equal to 19.6 microns and less than or equal to 21.6 microns, for example, The height of the first spacer 141 may be 20.6 microns.
  • a first spacer 141 can be provided on a relatively flat plane between two adjacent thin film transistors, therefore, the first spacer 141 is located between two adjacent thin film transistors; the length of the first spacer 141 The direction is consistent with the extending direction of the data line 5, and the orthographic projection of the first spacer 141 on the base substrate 1 overlaps with the orthographic projection of the data line 5 on the base substrate 1, that is, the first spacer 141 and the The data lines 5 are arranged oppositely.
  • the orthographic projection of the conduction enhancement layer 821 on the base substrate 1 is set as a curve, and the conduction enhancement layer 821 is concavely bent toward the side away from the first spacer 141 at a position adjacent to the first spacer 141, and the concave bend
  • the depth H is greater than or equal to 2 microns and less than or equal to 3 microns.
  • the concave bending depth H can be 2.5 microns;
  • the orthographic projection of the protective layer 831 on the base substrate 1 is set as a curve, and the protective layer 831 is aligned with the first spacer.
  • the position adjacent to 141 is concavely bent toward the side away from the first spacer 141 , and the concave bending depth H is greater than or equal to 2 microns and less than or equal to 3 microns, for example, the concave bending depth H may be 2.5 microns.
  • the concave and bent positions of the conductive enhancement layer 821 and the protection layer 831 are generally the positions where they intersect with the data line 5 .
  • the conductive enhancement layer 821 may include a first straight line portion and a first curved portion (not shown in the figure due to being blocked by the second straight line portion 8311 and the second curved portion 8312), the first straight line portion
  • the orthographic projection on the base substrate 1 is located within the orthographic projection of the grid lines 3 on the base substrate 1, and the orthographic projection of the first curved portion on the base substrate 1 is at least partly the same as the orthographic projection of the grid lines 3 on the base substrate 1 do not overlap, that is, the orthographic projection of the two ends of the first curved portion connected to the first straight line portion on the base substrate 1 is located within the orthographic projection of the grid line 3 on the base substrate 1, but the first curved portion
  • the orthographic projection of the middle part on the base substrate 1 and the orthographic projection of the grid lines 3 on the base substrate 1 do not overlap.
  • the protective layer 831 may include a second straight portion 8311 and a second curved portion 8312, the orthographic projection of the second straight portion 8311 on the base substrate 1 is located within the orthographic projection of the grid line 3 on the base substrate 1, and the second curved portion
  • the orthographic projection of 8312 on the base substrate 1 does not overlap at least part of the orthographic projection of the grid line 3 on the base substrate 1, that is, the two ends connected by the second curved portion 8312 and the second straight line portion 8311 are on the base substrate
  • the orthographic projection on 1 is located within the orthographic projection of the grid line 3 on the base substrate 1, however, the orthographic projection of the middle part of the second curved portion 8312 on the base substrate 1 is the same as the orthographic projection of the grid line 3 on the base substrate 1 Orthographic projections do not overlap.
  • the conductive enhancement layer 821 and the protective layer 831 are bent and bent to reserve a space for the first spacer 141, because the first spacer 141 is used to support the color filter substrate 13, and it is necessary to set a relatively flat support plane, then , it is necessary to provide a relatively flat base plane for the first spacer 141, the conductive enhancement layer 821 and the protective layer 831 will cause the base plane on which the first spacer 141 is set to be uneven, and the conductive enhancement layer 821 and the protective layer 831 will be depressed. After bending, the first spacer 141 does not need to be disposed on the side of the conductive enhancement layer 821 and the protection layer 831 away from the base substrate 1 , so as to provide a relatively flat base plane for the first spacer 141 .
  • curves are not necessarily all formed by arcs, but may also be broken lines formed by a plurality of straight lines, or may be formed by mixing straight lines and arcs.
  • the curved conductivity enhancement layer 821 and the curved protection layer 831 have sufficient extension margin, which can effectively avoid the fracture of the conductivity enhancement layer 821 and the protection layer 831 .
  • a second insulating layer 111 is provided on the side of the protective layer 831 away from the base substrate 1, and a fourth via hole 112 is provided on the second insulating layer 111, and the fourth via hole 112 communicates with the third via hole 812, namely The fourth via hole 112 is also connected to the data line 5 .
  • a second electrode 12 is provided on the side of the second insulating layer 111 away from the base substrate 1 , and the second electrode 12 passes through the fourth via hole 112 , the third via hole 812 , the second via hole 72 and the first via hole 62 Connect to data line 5.
  • the second electrode 12 may be a pixel electrode.
  • the second electrode 12 may be provided on the side of the organic insulating layer 71 away from the base substrate 1 , the second electrode 12 may be a pixel electrode, and the second electrode 12 passes through the first insulating layer.
  • the first via hole 62 on the layer 61 and the second via hole 72 on the organic insulating layer 71 are connected to the data line 5; the second insulating layer 111 is arranged on the side of the second electrode 12 away from the base substrate 1; The first electrode 811, the conduction enhancement layer 821 and the protective layer 831 are sequentially stacked on the side of the second insulating layer 111 away from the base substrate 1; the structures of the first electrode 811, the conduction enhancement layer 821 and the protective layer 831 have been described in detail above. Note, therefore, will not repeat them here.
  • the extension direction of the conduction enhancement layer 821 may be consistent with the extension direction of the data line 5
  • the orthographic projection of the conduction enhancement layer 82 on the base substrate 1 is at least partially located on the surface of the data line 5 on the substrate.
  • the extension direction of the protection layer 831 may also be consistent with the extension direction of the data line 5, and the orthographic projection of the protection layer 831 on the base substrate 1 is at least partially located at the position of the data line 5 on the base substrate 1.
  • the conduction enhancement layer 821 and the data line 5 can be provided on the part of the data line 5 where the first spacer 141 is not provided, and the conduction enhancement layer 821 and the data line 5 can be arranged in multiple segments in a disconnected manner.
  • the extension direction of the conduction enhancement layer 821 may be consistent with the extension direction of the gate line 3, and the conduction enhancement layer 821 may be located on the side of the thin film transistor away from the gate line 3, that is, the conduction enhancement layer 821 and the gate line 3 are located on opposite sides of the thin film transistor; the extension direction of the protection layer 831 can also be consistent with the extension direction of the gate line 3, and the protection layer 831 can be located on the side of the thin film transistor away from the gate line 3, that is, the protection layer 831 and the gate line 3
  • the gate lines 3 are located on opposite sides of the TFT.
  • exemplary embodiments of the present disclosure also provide a method for manufacturing a display panel.
  • the method for manufacturing a display panel may include the following steps:
  • step S110 an array substrate 15 is provided, and the array substrate 15 is prepared by any one of the above-mentioned preparation methods.
  • Step S210 providing a color filter substrate 13, combining the color filter substrate 13 with the array substrate 15, the color filter substrate 13 includes a black matrix 132, and the conductive enhancement layer 821 is formed on the base substrate 1
  • the orthographic projection on is located in the orthographic projection of the black matrix 132 on the base substrate 1
  • the orthographic projection of the protective layer 831 on the base substrate 1 is located in the black matrix 132 on the substrate. Orthographic projection on substrate 1.
  • the protective layer 831 and the conductive enhancement layer 821 are both made of metal, they are opaque and reflective, and they are blocked by the black matrix 132, which can avoid their reflection and affect the display effect .
  • the array substrate 15 and the color filter substrate 13 are aligned so that the conductive enhancement layer 821 is on the substrate.
  • the orthographic projection on the substrate 1 is located in the orthographic projection of the black matrix 132 on the base substrate 1
  • the orthographic projection of the protective layer 831 on the base substrate 1 is located in the orthographic projection of the black matrix 132 on the base substrate 1; and in A liquid crystal material is added into the gap between the array substrate 15 and the color filter substrate 13 to form a display panel.
  • the display panel may include an array substrate 15 and a color filter substrate 13;
  • the array substrate 15 the specific structure of the array substrate 15 has been described in detail above, so it will not be repeated here.
  • the color filter substrate 13 is arranged opposite to the array substrate 15 .
  • the color filter substrate 13 may include a black matrix 132 , and the orthographic projection of the conductive enhancement layer 821 on the base substrate 1 is located within the orthographic projection of the black matrix 132 on the base substrate 1 .
  • the color filter substrate 13 may further include a base layer 131, a plurality of filter parts 133 and a black matrix 132 disposed on one side of the base layer 131, and a plurality of filter parts 133 are arranged in an array on the base layer 131 One side; the plurality of filter units 133 may include a red filter unit, a blue filter unit, and a green filter unit.
  • a second spacer 142 is arranged on the side of the color filter substrate 13 close to the array substrate 15, and the second spacer 142 can also be arranged in a strip shape.
  • the objects 141 contact and form a cross structure, and the second spacer 142 supports the color filter substrate 13 together with the first spacer 141 to provide an accommodating space for the liquid crystal.
  • exemplary embodiments of the present disclosure further provide a display device, which may include the above-mentioned display panel.
  • a display device which may include the above-mentioned display panel.
  • the specific structure of the display panel has been described in detail above, so it will not be repeated here.
  • the specific type of the display device is not particularly limited, and any type of display device commonly used in this field can be used, such as a mobile device such as a mobile phone, a wearable device such as a watch, a VR device, etc.
  • a mobile device such as a mobile phone
  • a wearable device such as a watch
  • a VR device etc.
  • the specific use of the corresponding selection, will not repeat them here.
  • the display device also includes other necessary components and components. Taking the display as an example, such as a casing, a circuit board, a power cord, etc., those skilled in the art can Specific usage requirements are supplemented accordingly, and will not be repeated here.
  • the beneficial effect of the display device provided by the exemplary embodiment of the present disclosure is the same as that of the array substrate 15 provided by the above exemplary embodiment, and will not be repeated here.

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Abstract

一种阵列基板的制备方法，包括：依次形成第一电极材料层（81）、导电增强材料层（82）和保护材料层（83），保护材料层（83）的抗氧化性强于导电增强材料层（82）的抗氧化性；在保护材料层（83）的远离第一电极材料层（81）的一侧形成掩模图案（92），掩模图案（92）包括第一部分（921）和第二部分（922），第一部分（921）的厚度大于第二部分（922）的厚度；对掩模图案（92）进行灰化，以去除第二部分（922）使第二部分（922）覆盖的保护材料层（83）裸露；对第一电极材料层（81）进行图案化处理形成第一电极（811）；对保护材料层（83）以及导电增强材料层（82）进行图案化处理对应形成保护层（831）和导电增强层（821）。该制备方法避免了第一电极（811）的断开的不良。

Description

阵列基板及制备方法、显示面板及制备方法、显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种阵列基板及阵列基板的制备方法、包括该阵列基板的显示面板及显示面板的制备方法、包括该显示面板的显示装置。
背景技术
近年来，用户对显示画质的要求越来越高，使得现有显示产品的显示画质无法满足用户的要求。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于克服上述现有技术的不足，提供一种阵列基板及制备方法、显示面板及制备方法、显示装置。
根据本公开的一个方面，提供了一种阵列基板的制备方法，包括：
依次形成第一电极材料层、导电增强材料层和保护材料层，所述保护材料层的抗氧化性强于所述导电增强材料层的抗氧化性；
在所述保护材料层的远离所述第一电极材料层的一侧形成掩模图案，所述掩模图案包括第一部分和第二部分，所述第一部分的厚度大于所述第二部分的厚度；
对所述掩模图案进行灰化，以去除所述第二部分使所述第二部分覆盖的所述保护材料层裸露；
对所述第一电极材料层进行图案化处理形成第一电极；
对所述保护材料层以及所述导电增强材料层进行图案化处理对应形成保护层和导电增强层。
在本公开的一种示例性实施例中，在对所述掩模图案进行灰化之前，所述制备方法还包括：
对所述保护材料层以及所述导电增强材料层进行图案化处理，使部分所述第一电极材料层裸露。
在本公开的一种示例性实施例中，在所述保护材料层的远离所述第一电极材料层的一侧形成掩模图案，包括：
在所述保护材料层的远离所述第一电极材料层的一侧形成掩模层，并对所述掩模层进行半掩模工艺形成所述掩模图案。
在本公开的一种示例性实施例中，在形成所述第一电极材料层之前，所述制备方法还包括：
形成有机绝缘材料层，并对所述有机绝缘材料层进行图案化处理形成有机绝缘层和第二过孔。
在本公开的一种示例性实施例中，在形成所述第一电极材料层之前，所述制备方法还包括：
在衬底基板的一侧形成多个栅线和多个阵列排布的薄膜晶体管，所述导电增强层在所述衬底基板上的正投影与所述栅线在所述衬底基板上的正投影有交叠，所述保护层在所述衬底基板上的正投影与所述栅线在所述衬底基板上的正投影有交叠。
在本公开的一种示例性实施例中，形成保护层和导电增强层之后，所述制备方法还包括：
在所述保护层的远离所述第一电极的一侧形成第二绝缘层，并对所述第二绝缘层进行图案化处理形成第四过孔；
在所述第二绝缘层的远离所述第一电极的一侧形成第二电极，所述第二电极与所述薄膜晶体管的数据线电连接。
根据本公开的另一个方面，提供了一种显示面板的制备方法，其中，包括：
提供一阵列基板，所述阵列基板通过上述任意一项所述的制备方法制备；
提供一彩膜基板，将所述彩膜基板与所述阵列基板对合，所述彩膜基板包括黑矩阵，所述导电增强层在所述衬底基板上的正投影位于所述黑矩阵在所述衬底基板上的正投影内，所述保护层在所述衬底基板上的正投影位于所述黑矩阵在所述衬底基板上的正投影内。
根据本公开的另一个方面，提供了一种阵列基板，包括：
第一电极；
导电增强层，设于所述第一电极的一侧；
保护层，设于所述导电增强层的远离所述第一电极的一侧，所述保护层的抗氧化性强于所述导电增强层的抗氧化性。
在本公开的一种示例性实施例中，所述导电增强层在所述第一电极上的正投影与所述保护层在所述第一电极上的正投影重合。
在本公开的一种示例性实施例中，所述阵列基板还包括：
衬底基板；
多个薄膜晶体管和多个栅线，所述多个薄膜晶体管阵列排布于所述衬底基板的一侧，所述导电增强层在所述衬底基板上的正投影与所述栅线在所述衬底基板上的正投影有交叠，所述保护层在所述衬底基板上的正投影与所述栅线在所述衬底基板上的正投影有交叠。
在本公开的一种示例性实施例中，所述导电增强层的延伸方向与所述栅线的延伸方向一致，所述导电增强层在所述衬底基板上的正投影至少部分位于所述栅线在所述衬底基板上的正投影内，所述保护层的延伸方向与所述栅线的延伸方向一致，所述保护层在所述衬底基板上的正投影至少部分位于所述栅线在所述衬底基板上的正投影内。
在本公开的一种示例性实施例中，所述阵列基板还包括：
第一隔垫物，设于所述第一电极的远离衬底基板的一侧，且位于相邻两个薄膜晶体管之间；
所述导电增强层在所述衬底基板上的正投影设置为曲线，所述导电增强层在与所述第一隔垫物相邻的位置向远离所述第一隔垫物一侧凹陷折弯，所述保护层在所述衬底基板上的正投影设置为曲线，所述保护层在与所述第一隔垫物相邻的位置向远离所述第一隔垫物一侧凹陷折弯。
在本公开的一种示例性实施例中，所述导电增强层包括第一直线部和第一弯曲部，所述第一直线部在所述衬底基板上的正投影位于所述栅线在所述衬底基板上的正投影内，所述第一弯曲部在所述衬底基板上的正投影至少部分与所述栅线在所述衬底基板上的正投影不交叠；所述保护层包括第二直线部和第二弯曲部，所述第二直线部在所述衬底基板上 的正投影位于所述栅线在所述衬底基板上的正投影内，所述第二弯曲部在所述衬底基板上的正投影至少部分与所述栅线在所述衬底基板上的正投影不交叠。
在本公开的一种示例性实施例中，所述导电增强层设置为多条，且延伸方向相同；所述保护层设置为多条，且延伸方向相同。
在本公开的一种示例性实施例中，所述阵列基板包括薄膜晶体管和数据线，所述导电增强层的延伸方向与所述数据线的延伸方向一致，所述导电增强层在所述衬底基板上的正投影至少部分位于所述数据线在所述衬底基板上的正投影内，所述保护层的延伸方向与所述数据线的延伸方向一致，所述保护层在所述衬底基板上的正投影至少部分位于所述数据线在所述衬底基板上的正投影内。
在本公开的一种示例性实施例中，所述阵列基板包括薄膜晶体管和栅线，所述导电增强层的延伸方向与所述栅线的延伸方向一致，所述导电增强层位于所述薄膜晶体管的远离所述栅线的一侧，所述保护层的延伸方向与所述栅线的延伸方向一致，所述保护层位于所述薄膜晶体管的远离所述栅线的一侧。
在本公开的一种示例性实施例中，所述阵列基板还包括：
有机绝缘层，设于所述多个薄膜晶体管与所述第一电极之间。
在本公开的一种示例性实施例中，所述阵列基板还包括：
第二绝缘层，设于所述第一电极的远离所述衬底基板的一侧；
第二电极，设于所述第二绝缘层的远离所述衬底基板的一侧，所述第二电极与所述薄膜晶体管的数据线电连接。
在本公开的一种示例性实施例中，所述保护层的材质是钛合金，厚度大于等于300A且小于等于500A。
在本公开的一种示例性实施例中，所述钛合金包括至少三种金属材料。
在本公开的一种示例性实施例中，所述导电增强层的材质是铜，厚度大于等于1000A且小于等于1500A。
在本公开的一种示例性实施例中，所述第一电极是公共电极，材质是ITO。
根据本公开的另一个方面，提供了一种显示面板，包括：
阵列基板，是上述任意一项所述的阵列基板；
彩膜基板，与所述阵列基板相对设置，所述彩膜基板包括黑矩阵，所述导电增强层在所述衬底基板上的正投影位于所述黑矩阵在所述衬底基板上的正投影内，所述保护层在所述衬底基板上的正投影位于所述黑矩阵在所述衬底基板上的正投影内。
根据本公开的另一个方面，提供了一种显示装置，包括：上述所述的显示面板。
本公开的阵列基板的制备方法，在导电增强材料层的远离第一电极材料层的一侧形成有保护材料层，保护材料层的抗氧化性强于导电增强材料层的抗氧化性，在保护材料层的远离第一电极材料层形成掩模图案，掩模图案包括第一部分和第二部分，第一部分的厚度大于第二部分的厚度；对掩模图案进行灰化，以去除第二部分使第二部分覆盖的保护材料层裸露；对第一电极材料层进行图案化处理形成第一电极；对保护材料层以及导电增强材料层进行图案化处理形成保护层和导电增强层。一方面，通过一次掩模即可完成对第一电极材料层的图案化处理和对导电增强材料层以及保护材料层的图案化处理，降低生产成本、提高产线产能；另一方面，在对掩模图案进行灰化时，有保护材料层对导电增强材料层进行保护，避免灰化工艺时对导电增强材料层的氧化腐蚀，从而避免在对第一电极材料层进行图案化处理形成第一电极时，对第一电极进行刻蚀，导致第一电极的断开的不良；再一方面，导电增强材料层可以有效降低第一电极的电阻，提高第一电极的均匀性，从而有效改善显示的色偏不良。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人 员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开阵列基板的制备方法一示例实施方式的流程示意框图。
图2-图14为本公开阵列基板的制备方法中各个步骤的结构示意图。
图15为本公开阵列基板一示例实施方式的结构示意图。
图16为图15所示的阵列基板的俯视结构示意图。
图17为本公开显示面板的制备方法一示例实施方式的流程示意框图。
图18为本公开显示面板一示例实施方式的结构示意图。
附图标记说明：
1、衬底基板；2、缓冲层；3、栅线；31、栅极；4、栅绝缘层；5、数据线；51、源极；
61、第一绝缘层；62、第一过孔；
71、有机绝缘层；72、第二过孔；
81、第一电极材料层；811、第一电极；812、第三过孔；82、导电增强材料层；821、导电增强层；83、保护材料层；831、保护层；8311、第二直线部；8312、第二弯曲部；
91、掩模层；92、掩模图案；921、第一部分；922、第二部分；
10、掩模板；101、透光部；102、遮光部；103、半透光部；
111、第二绝缘层；112、第四过孔；
12、第二电极；
13、彩膜基板；131、基底层；132、黑矩阵；133、滤光部；
141、第一隔垫物；142、第二隔垫物；
15、阵列基板；16、有源层。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似 的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
本公开示例实施方式提供了一种阵列基板的制备方法，参照图1所示，该阵列基板的制备方法可以包括以下步骤：
步骤S10，依次形成第一电极材料层、导电增强材料层和保护材料层，所述保护材料层的抗氧化性强于所述导电增强材料层的抗氧化性。
步骤S20，在所述保护材料层的远离所述第一电极材料层的一侧形成掩模图案，所述掩模图案包括第一部分和第二部分，所述第一部分的厚度大于所述第二部分的厚度。
步骤S30，对所述掩模图案进行灰化，以去除所述第二部分使所述第二部分覆盖的所述保护材料层裸露。
步骤S40，对所述第一电极材料层进行图案化处理形成第一电极。
步骤S50，对所述保护材料层以及所述导电增强材料层进行图案化处理形成保护层和导电增强层。
本公开的阵列基板的制备方法，一方面，通过一次掩模即可完成对第一电极材料层81的图案化处理和对导电增强材料层82以及保护材料层的图案化处理，降低生产成本、提高产线产能；另一方面，在对掩模图案92进行灰化时，有保护材料层83对导电增强材料层82进行保护， 避免灰化工艺时对导电增强材料层82的氧化腐蚀，从而避免在对第一电极材料层81进行图案化处理形成第一电极811时，对第一电极811进行刻蚀，导致第一电极811的断开的不良；再一方面，导电增强材料层82可以有效降低第一电极811的电阻，提高第一电极811的均匀性，从而有效改善显示的色偏不良。
下面对阵列基板的制备方法的各个步骤进行详细说明。
步骤S10，依次形成第一电极材料层81、导电增强材料层82和保护材料层83，所述保护材料层83的抗氧化性强于所述导电增强材料层82的抗氧化性。
在本示例实施方式中，提供一衬底基板1，衬底基板1可以是刚性基板，例如，可以是玻璃基板。
在本示例实施方式中，参照图2和图16所示，在衬底基板1的一侧可以形成缓冲层2。在缓冲层2的远离衬底基板1的一侧通过溅射金属镀膜形成栅极材料层，对栅极材料层进行光刻形成栅极图案，栅极图案可以包括栅极31以及栅线3，栅极31与栅线3连接。
参照图3和图16所示，在栅极图案以及裸露的缓冲层2的远离衬底基板1的一侧可以通过PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积法)沉积形成栅绝缘层4。
在栅绝缘层4的远离衬底基板1的一侧可以通过PECVD沉积形成有源材料层。对有源材料层进行光刻形成有源层16。
参照图4所示，在有源层16以及裸露的栅绝缘层4的远离衬底基板1的一侧可以通过溅射金属镀膜沉积形成源漏极材料层，并对源漏极材料层进行光刻形成源漏极图案，源漏极图案可以包括数据线5、源极和漏极(图中未示出)，源极和漏极均连接于有源层16，数据线5与源极或漏极连接。在使用极性相反的薄膜晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”可以互相调换。
至此完成薄膜晶体管的制备。
需要说明的是，上述说明的薄膜晶体管是底栅型的薄膜晶体管，在本公开的其他示例实施方式中，薄膜晶体管还可以是顶栅型的薄膜晶体 管或双栅型的薄膜晶体管，此处对其制备方法不做详细说明。
参照图5所示，在源漏极图案的远离衬底基板1的一侧可以通过PECVD沉积形成第一绝缘层61，并对第一绝缘层61进行光刻在第一绝缘层61上形成第一过孔62，第一过孔62连通至数据线5，即第一过孔62处的数据线5裸露。
参照图6所示，在第一绝缘层61的远离衬底基板1的一侧可以通过PECVD沉积形成有机绝缘层71，并对有机绝缘层71进行光刻在有机绝缘层71上形成第二过孔72，第二过孔72连通至第一过孔62，即第二过孔72处的数据线5裸露。有机绝缘层71的材质可以为PAC(Photo active compound，光活性化合物)。有机绝缘层71的厚度大于等于2微米且小于等于3微米，例如，有机绝缘层71的厚度可以是2.4微米。
有机绝缘层71能够起到平坦化的作用，为后续形成的第一电极811提供较为平整的基底，便于第一电极811的成型，进而提高第一电极811的均匀性；另外，有机绝缘层71使得第一电极811与数据线5之间在厚度方向的距离增大、相互影响减弱，寄生电容也会减小很多，更利于驱动芯片的驱动；第一电极811与数据线5之间在厚度方向的距离增大后，第一电极811与数据线5之间在其他方向(例如在与衬底基板1平行的方向)上的距离距离可以缩短，从而彩膜基板13的黑矩阵132的宽度也可以制作得更小，进而提高产品的开口率。
参照图7所示，在有机绝缘层71的远离衬底基板1的一侧可以通过溅射金属镀膜形成第一电极材料层81，第一电极材料层81的材质可以是ITO，第一电极材料层81的厚度大于或等于400A且小于或等于700A，例如，第一电极材料层81的厚度可以为550A。当然，第一电极材料层81的材质还可以是为他导电材质。
在第一电极材料层81的远离衬底基板1的一侧可以通过溅射金属镀膜形成导电增强材料层82，导电增强材料层82的材质可以是铜，导电增强材料层82的厚度大于等于1000A且小于等于1500A，例如，导电增强材料层82的厚度可以为1200A。当然，在本公开的其他示例实施方式中，导电增强材料层82的材质还可以是铝、银等其他金属材质。
在导电增强材料层82的远离衬底基板1的一侧可以通过溅射金属镀 膜形成保护材料层83，保护材料层83的材质可以是MoNbTi，保护材料层83的厚度大于等于300A且小于等于500A，例如，保护材料层83的厚度可以是400A。当然，在本公开的其他示例实施方式中，保护材料层83的材质还可以是其他钛合金，只要保护材料层83的抗氧化性强于导电增强材料层82的抗氧化性即可。抗氧化性是指金属材料在高温时抵抗氧化性气氛腐蚀作用的能力。抗氧化性弱的材料(例如MoNb)与灰化气体反应影响等离子平衡导致Arcing(电弧)报警，因此，采用抗氧化性较强的材料。
上述第一电极材料层81的厚度、导电增强材料层82的厚度以及保护材料层83的厚度均是发明人通过无数次试验得到的数据，成膜的均匀性较好，而且导电效果较好，效率较高。因为，厚度太厚不利于显示面板的轻薄化，而且成膜时间较长、效率低；厚度太薄，均匀性不好，容易产生断开的不良。
步骤S20，在所述保护材料层83的远离所述第一电极材料层81的一侧形成掩模图案92，所述掩模图案92包括第一部分921和第二部分922，所述第一部分921的厚度大于所述第二部分922的厚度。
在本示例实施方式中，参照图8所示，图中箭头表示照射光线，箭头越密表示透过的光线越多，反之，箭头越疏表示透过的光线越少；在保护材料层83的远离衬底基板1的一侧可以通过PECVD沉积形成掩模层91，并对掩模层91进行半掩模工艺形成掩模图案92，掩模图案92可以包括第一部分921和第二部分922，第一部分921的厚度大于第二部分922的厚度。
具体为：在掩模层91的远离衬底基板1的一侧放置掩模板10，掩模板10可以包括透光部101、遮光部102以及半透光部103；半透光部103与第二部分922相对设置，即半透光部103在衬底基板1上的正投影与第二部分922在衬底基板1上的正投影重合；遮光部102与第一部分921相对设置，即遮光部102在衬底基板1上的正投影与第一部分921在衬底基板1上的正投影重合。透光部101与掩模层91的其他部分相对设置。
然后，参照图9所示，对掩模层91进行曝光显影，去除与透光部 101相对设置的掩模层91，使得部分保护材料层83裸露；与半透光部103相对设置的掩模层91去除一定厚度，形成第二部分922；与遮光部102相对设置的掩模层91完全保留，形成第一部分921，使得第一部分921的厚度大于第二部分922的厚度。
最后，参照图10所示，对裸露的保护材料层83和与这部分保护材料层83相对设置的导电增强材料层82进行第一次刻蚀，保留被掩模图案92覆盖的保护材料层83和导电增强材料层82。
步骤S30，对所述掩模图案92进行灰化，以去除所述第二部分922使所述第二部分922覆盖的所述保护材料层83裸露。
在本示例实施方式中，参照图11所示，对掩模图案92进行灰化工艺，灰化工艺采用的气体可以包括SF6和O2。灰化工艺采用的气体具有较强的氧化性，由于保护材料层83的抗氧化性强于导电增强材料层82的抗氧化性，而且保护材料层83覆盖在导电增强材料层82之上，因此，保护材料层83能够对导电增强材料层82进行保护，避免在对掩模图案92进行灰化工艺的时候，氧化性气体对导电增强材料层82氧化腐蚀，从而避免在导电增强材料层82上产生断开。
通过灰化工艺去除第二部分922，使得第二部分922覆盖的保护材料层83裸露，而且第一部分921的厚度也有减薄。
步骤S40，对所述第一电极材料层81进行图案化处理形成第一电极811。
在本示例实施方式中，参照图12所示，以第一部分921、保护材料层83以及导电增强材料层82为掩模对第一电极材料层81进行刻蚀形成第一电极811，且在第一电极811上形成第三过孔812，第三过孔812与第二过孔72连通，即第三过孔812处的数据线5裸露。由于在导电增强材料层82上没有产生断开，因此，在对第一电极材料层81进行刻蚀的过程中，不会对保护材料层83以及导电增强材料层82覆盖的第一电极材料层81进行刻蚀，从而避免在第一电极811上产生断开的不良。
第一电极811可以是公共电极。
步骤S50，对所述保护材料层83以及所述导电增强材料层82进行图案化处理形成保护层831和导电增强层821。
在本示例实施方式中，参照图13所示，以第一部分921为掩模对保护材料层83以及导电增强材料层82进行刻蚀形成保护层831和导电增强层821。导电增强层821在衬底基板1上的正投影与保护层831在衬底基板1上的正投影基本重合。导电增强层821在衬底基板1上的正投影与栅线3在衬底基板1上的正投影有交叠，具体为，导电增强层821在衬底基板1上的正投影位于栅线3在衬底基板1上的正投影内，即保护层831和导电增强层821的延伸方向与栅线3的延伸方向一致，且保护层831和导电增强层821的宽度稍小于栅线3的宽度。导电增强层821的宽度大约为3.5微米，保护层831的宽度也大约为3.5微米，栅线3的宽度大约为4.5微米。由于保护层831和导电增强层821均是金属材质，是不透光的而且具有反光性，因此，为了避免其反光而影响显示效果，需要通过黑矩阵132对其进行遮挡，栅线3也通过黑矩阵132对其进行遮挡，导电增强层821在衬底基板1上的正投影位于栅线3在衬底基板1上的正投影内，可以避免增加黑矩阵132的宽度，从而避免减小开口率。
当然，在本公开的其他示例实施方式中，可以将保护层831和导电增强层821向靠近数据线5的一侧设置，但是由于数据线5需要通过过孔与像素电极连接，因此，导电增强层821在衬底基板1上的正投影与栅线3在衬底基板1上的正投影还是需要有交叠的。
导电增强层821设置在第一电极811的远离衬底基板1的一侧，且与第一电极811连接，导电增强层821可以减小第一电极811的电阻，从而增加第一电极811的导电效果，而且导电增强层821可以提高第一电极811的均匀性，有效改善显示色偏的不良；保护层831的材料也是金属，是导电材料，因此，保护层831可以进一步地减小第一电极811的电阻，从而进一步地增加第一电极811的导电效果，同样能够提高第一电极811的均匀性，有效改善显示色偏的不良。
最后，去除剩余的掩模图案92。
需要说明的是，虽然有机绝缘膜层与导电增强层821相结合的结构具有上述很多有益效果，但是如果有机绝缘膜层和导电增强层821的形成采用两次掩模工艺，会导致成本增加、产能降低；为了减少掩模工艺 次数，需要通过一次掩模工艺实现有机绝缘膜层和导电增强层821的制备；但是，由于灰化工艺对有机绝缘层71有刻蚀的作用，因此，需要先进行灰化工艺然后再进行第一电极材料层81的图案化处理，在对掩模图案92进行灰化工艺时，第一电极材料层81对有机绝缘层71有保护的作用，避免灰化工艺对有机绝缘层71的刻蚀。但是，灰化工艺对导电增强材料层82也有氧化腐蚀作用，本公开通过抗氧化性较强的保护材料层83对导电增强材料层82进行保护，避免在灰化工艺时对导电增强材料层82产生氧化腐蚀，从而避免导电增强材料层82覆盖的第一电极811层产生断开的不良。
在本示例实施方式中，参照图14所示，首先，在保护层831和第一电极811的远离衬底基板1的一侧形成第二绝缘层111，在第二绝缘层111的远离衬底基板1的一侧形成光刻胶，对光刻胶进行曝光显影形成光刻胶图案；然后，以光刻胶图案为掩模对第二绝缘层111进行刻蚀，使得在第二绝缘层111上形成第四过孔112，第四过孔112与第三过孔812连通，即第四过孔112处的数据线5裸露；最后，去除光刻胶图案。
在本示例实施方式中，参照图15所示，在第二绝缘层111的远离衬底基板1的一侧形成第二电极材料层，第二电极材料层的材质可以是ITO。然后，对第二电极材料层进行光刻形成第二电极12。第二电极12通过第四过孔112、第三过孔812、第二过孔72以及第一过孔62与数据线5连接，第二电极12也可以与源极或漏级连接。第二电极12可以是像素电极。
另外，在本公开的其他示例实施方式中，可以在形成有机绝缘层71以后，在有机绝缘层71的远离衬底基板1的一侧形成第二电极12，第二电极12可以是像素电极，第二电极12通过第一绝缘层61上的第一过孔62和有机绝缘层71上的第二过孔72与数据线5连接；在第二电极12的远离衬底基板1的一侧形成第二绝缘层111；在第二绝缘层111的远离衬底基板1的一侧依次层叠形成第一电极材料层81、导电增强材料层82和保护材料层83；然后，按照上述对第一电极材料层81、导电增强材料层82和保护材料层83的刻蚀方法进行刻蚀，具体的刻蚀方法上述已经进行了详细说明，因此，此处不再赘述。
上述具体说明了各个膜层可以通过溅射金属镀膜或PECVD沉积形成，这些说明只是举例说明，并不构成对本公开的限定，在本公开的其他示例实施方式中，各个膜层根据需要还可以通过涂覆、打印以及其他化学气相沉积等等方法形成，均属于本公开保护的范围。
需要说明的是，尽管在附图中以特定顺序描述了本公开中阵列基板的制备方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
基于相同的发明构思，本公开示例实施方式还提供了一种阵列基板，参照图15所示，该阵列基板可以通过上述任意一项所述的阵列基板的制备方法制备；该阵列基板可以包括第一电极811、导电增强层821以及保护层831；导电增强层821设于第一电极811的一侧；保护层831设于导电增强层821的远离第一电极811的一侧，保护层831的抗氧化性强于导电增强层821的抗氧化性。
在本示例实施方式中，阵列基板还可以包括衬底基板1，衬底基板1可以是刚性基板，例如，可以是玻璃基板。
在衬底基板1的一侧设置有缓冲层2。
在缓冲层2的远离衬底基板1的一侧设置有栅极图案，栅极图案可以包括栅极31以及栅线3。
在栅极图案的远离衬底基板1的一侧设置有栅绝缘层4。在栅绝缘层4的远离衬底基板1的一侧设置有有源层16，在有源层16的远离衬底基板1的一侧设置有源漏极图案，源漏极图案可以包括数据线5、源极和漏极，源极和漏极均连接于有源层16，数据线5与源极或漏极连接。
需要说明的是，栅极31、有源层16、源极和漏极形成一个薄膜晶体管，多个薄膜晶体管阵列排布于衬底基板1的一侧。上述说明的薄膜晶体管是底栅型的薄膜晶体管，在本公开的其他示例实施方式中，薄膜晶体管还可以是顶栅型的薄膜晶体管或双栅型的薄膜晶体管，此处不详细说明。
在源漏极图案的远离衬底基板1的一侧设置有第一绝缘层61，在第 一绝缘层61上设置有第一过孔62，第一过孔62连通至数据线5。
在第一绝缘层61的远离衬底基板1的一侧设置有有机绝缘层71，在有机绝缘层71上设置有第二过孔72，第二过孔72与第一过孔62连通，即第二过孔72也连通至数据线5。
在有机绝缘层71的远离衬底基板1的一侧设置有第一电极811，在第一电极811上设置有第三过孔812，第三过孔812与第二过孔72连通，即第三过孔812也连通至数据线5。第一电极811可以是公共电极。
在第一电极811的远离衬底基板1的一侧设置有导电增强层821，导电增强层821在衬底基板1上的正投影与栅线3在衬底基板1上的正投影有交叠。
在导电增强层821的远离衬底基板1的一侧设置有保护层831，保护层831在衬底基板1上的正投影与导电增强层821在衬底基板1上的正投影基本重合，使得保护层831在衬底基板1上的正投影与栅线3在衬底基板1上的正投影也有交叠。由于工艺的原因，保护层831在衬底基板1上的正投影位于导电增强层821在衬底基板1上的正投影内，即保护层831稍小于导电增强层821。
第一电极811的材质可以是ITO，第一电极811的厚度大于或等于400A且小于或等于700A，例如，第一电极811的厚度可以为550A。当然，第一电极811的材质还可以是为他导电材质。
导电增强层821的材质可以是铜，导电增强层821的厚度大于等于1000A且小于等于1500A，例如，导电增强层821的厚度可以为1200A。当然，在本公开的其他示例实施方式中，导电增强层821的材质还可以是铝、银等其他金属材质。
保护层831的材质可以是MoNbTi，保护层831的厚度大于等于300A且小于等于500A，例如，保护层831的厚度可以是400A。当然，在本公开的其他示例实施方式中，保护层831的材质还可以是其他钛合金，例如，可以是包括三种金属材料的钛合金，还可以是包括四种金属材料的钛合金，其抗氧化较强，只要保护层831的抗氧化性强于导电增强层821的抗氧化性即可。
在本示例实施方式中，导电增强层821设置为多条，且多条导电增 强层821相互平行设置；导电增强层821与栅线3可以是一一对应的，即在一个栅线3的远离衬底基板1的一侧设置有一个导电增强层821。保护层831也设置为多条，且多条保护层831也相互平行设置，当然，这种情况下，保护层831与栅线3也是一一对应的，即在一个栅线3的远离衬底基板1的一侧设置有一个保护层831。
多个栅线3基本均匀地设置在阵列基板上，多个导电增强层821和多个保护层831与多个栅线3一一对应，使得多个导电增强层821和多个保护层831也均匀地设置在阵列基板上，从而使得第一电极811的电阻更为均匀，有效改善显示色偏。
参照图16所示的阵列基板的俯视结构示意图，导电增强层821的延伸方向与栅线3的延伸方向一致，导电增强层821在衬底基板1上的正投影至少部分位于栅线3在衬底基板1上的正投影内，保护层831的延伸方向与栅线3的延伸方向一致，保护层831在衬底基板1上的正投影至少部分位于栅线3在衬底基板1上的正投影内。
阵列基板还可以包括第一隔垫物141，第一隔垫物141设于第一电极811的远离衬底基板1的一侧，具体地，第一隔垫物141设于第二电极12的远离衬底基板1的一侧。
第一隔垫物141可以设置为四棱台的结构，即第一隔垫物141的与衬底基板1平行的截面为长方形，且靠近衬底基板1的底面的面积大于远离衬底基板1的顶面的面积；第一隔垫物141的底面的长度大于等于19.6微米且小于等于21.6微米，例如，第一隔垫物141的底面的长度可以为20.6微米；第一隔垫物141的底面的宽度大于等于16微米且小于等于18微米，例如，第一隔垫物141的底面的宽度可以为17微米；第一隔垫物141的高度大于等于19.6微米且小于等于21.6微米，例如，第一隔垫物141的高度可以为20.6微米。
一般在相邻两个薄膜晶体管之间具有较为平整的平面可以设置第一隔垫物141，因此，第一隔垫物141位于相邻两个薄膜晶体管之间；第一隔垫物141的长度方向与数据线5的延伸方向一致，第一隔垫物141在衬底基板1上的正投影与数据线5在衬底基板1上的正投影有交叠，即第一隔垫物141与数据线5相对设置。
导电增强层821在衬底基板1上的正投影设置为曲线，导电增强层821在与第一隔垫物141相邻的位置向远离第一隔垫物141一侧凹陷折弯，凹陷折弯深度H大于等于2微米且小于等于3微米，例如，凹陷折弯深度H可以为2.5微米；保护层831在衬底基板1上的正投影设置为曲线，保护层831在与第一隔垫物141相邻的位置向远离第一隔垫物141一侧凹陷折弯，凹陷折弯深度H大于等于2微米且小于等于3微米，例如，凹陷折弯深度H可以为2.5微米。而且，导电增强层821和保护层831凹陷折弯的位置一般是与数据线5相交的位置。
具体地，导电增强层821可以包括第一直线部和第一弯曲部(由于被第二直线部8311和第二弯曲部8312遮挡，在图中未示出)，第一直线部在衬底基板1上的正投影位于栅线3在衬底基板1上的正投影内，第一弯曲部在衬底基板1上的正投影至少部分与栅线3在衬底基板1上的正投影不交叠，即第一弯曲部与第一直线部连接的两端部在衬底基板1上的正投影位于栅线3在衬底基板1上的正投影内，但是，第一弯曲部的中间部分在衬底基板1上的正投影与栅线3在衬底基板1上的正投影不交叠。保护层831可以包括第二直线部8311和第二弯曲部8312，第二直线部8311在衬底基板1上的正投影位于栅线3在衬底基板1上的正投影内，第二弯曲部8312在衬底基板1上的正投影至少部分与栅线3在衬底基板1上的正投影不交叠，即第二弯曲部8312与第二直线部8311连接的两端部在衬底基板1上的正投影位于栅线3在衬底基板1上的正投影内，但是，第二弯曲部8312的中间部分在衬底基板1上的正投影与栅线3在衬底基板1上的正投影不交叠。
导电增强层821和保护层831凹陷折弯折弯后为第一隔垫物141预留空间，因为，第一隔垫物141用于支撑彩膜基板13，需要设置较为平整的支撑平面，那么，就需要为第一隔垫物141提供较为平整的基础平面，导电增强层821和保护层831会导致设置第一隔垫物141的基础平面不平整，将导电增强层821和保护层831凹陷折弯后，第一隔垫物141不需要设置在导电增强层821和保护层831的远离衬底基板1的一侧，为第一隔垫物141提供较为平整的基础平面。
需要说明的是，上述曲线并不一定全部是由弧形构成的，也可以是 由多个直线形成的折线形的，还可以是由直线和弧形混合构成的。
曲线的导电增强层821和曲线的保护层831有足够的延伸余量，可以有效避免导电增强层821和保护层831的断裂。
在保护层831的远离衬底基板1的一侧设置有第二绝缘层111，在第二绝缘层111上设置有第四过孔112，第四过孔112与第三过孔812连通，即第四过孔112也连通至数据线5。
在第二绝缘层111的远离衬底基板1的一侧设置有第二电极12，第二电极12通过第四过孔112、第三过孔812、第二过孔72以及第一过孔62连接至数据线5。第二电极12可以是像素电极。
另外，在本公开的其他示例实施方式中，可以在有机绝缘层71的远离衬底基板1的一侧设置第二电极12，第二电极12可以是像素电极，第二电极12通过第一绝缘层61上的第一过孔62和有机绝缘层71上的第二过孔72与数据线5连接；在第二电极12的远离衬底基板1的一侧设置第二绝缘层111；在第二绝缘层111的远离衬底基板1的一侧依次层叠设置第一电极811、导电增强层821和保护层831；第一电极811、导电增强层821和保护层831的结构上述已经进行了详细说明，因此，此处不再赘述。
在本公开的另一些示例实施方式中，导电增强层821的延伸方向可以与数据线5的延伸方向一致，导电增强层82在衬底基板1上的正投影至少部分位于数据线5在衬底基板1上的正投影内，保护层831的延伸方向也可以与数据线5的延伸方向一致，保护层831在衬底基板1上的正投影至少部分位于数据线5在衬底基板1上的正投影内。例如，可以在数据线5的未设置第一隔垫物141的部分设置导电增强层821和数据线5，导电增强层821和数据线5可以断开设置为多段。
在本公开的再一些示例实施方式中，导电增强层821的延伸方向可以与栅线3的延伸方向一致，导电增强层821可以位于薄膜晶体管的远离栅线3的一侧，即导电增强层821和栅线3位于薄膜晶体管的相对两侧；保护层831的延伸方向也可以与栅线3的延伸方向一致，保护层831可以位于薄膜晶体管的远离栅线3的一侧，即保护层831和栅线3位于薄膜晶体管的相对两侧。
基于相同的发明构思，本公开示例实施方式还提供了一种显示面板的制备方法，参照图17所示，该显示面板的制备方法可以包括以下步骤：
步骤S110，提供一阵列基板15，所述阵列基板15通过上述任意一项所述的制备方法制备。
步骤S210，提供一彩膜基板13，将所述彩膜基板13与所述阵列基板15对合，所述彩膜基板13包括黑矩阵132，所述导电增强层821在所述衬底基板1上的正投影位于所述黑矩阵132在所述衬底基板1上的正投影内，所述保护层831在所述衬底基板1上的正投影位于所述黑矩阵132在所述衬底基板1上的正投影内。
本公开的显示面板的制备方法，由于保护层831和导电增强层821均是金属材质，是不透光的而且具有反光性，通过黑矩阵132对其进行遮挡，可以避免其反光而影响显示效果。
在本示例实施方式中，将阵列基板15上的对位标识与彩膜基板13上的对位标识对准后，将阵列基板15与彩膜基板13对盒，使得导电增强层821在衬底基板1上的正投影位于黑矩阵132在衬底基板1上的正投影内，保护层831在衬底基板1上的正投影位于黑矩阵132在衬底基板1上的正投影内；并在阵列基板15与彩膜基板13之间的间隙内添加液晶材料形成显示面板。
基于相同的发明构思，本公开示例实施方式还提供了一种显示面板，参照图18所示，该显示面板可以包括阵列基板15和彩膜基板13；阵列基板15是上述任意一项所述的阵列基板15；阵列基板15的具体结构上述已经进行了详细说明，因此，此处不再赘述。彩膜基板13与阵列基板15相对设置，彩膜基板13可以包括黑矩阵132，导电增强层821在衬底基板1上的正投影位于黑矩阵132在衬底基板1上的正投影内。
在本示例实施方式中，彩膜基板13还可以包括基底层131，设于基底层131一侧的多个滤光部133和黑矩阵132，多个滤光部133阵列排布于基底层131的一侧；多个滤光部133可以包括红色滤光部、蓝色滤光部、绿色滤光部。
在彩膜基板13的靠近阵列基板15的一侧设置有第二隔垫物142，第二隔垫物142也可以设置为长条形，对盒后第二隔垫物142与第一隔 垫物141接触且形成十字交叉的结构，第二隔垫物142与第一隔垫物141一起支撑彩膜基板13，为液晶提供容纳空间。
基于相同的发明构思，本公开示例实施方式还提供了一种显示装置，该显示装置可以包括上述所述的显示面板。显示面板的具体结构上述已经进行了详细说明，因此，此处不再赘述。
而该显示装置的具体类型不受特别的限制，本领域常用的显示装置类型均可，具体例如手机等移动装置、手表等可穿戴设备、VR装置等等，本领域技术人员可根据该显示装置的具体用途进行相应地选择，在此不再赘述。
需要说明的是，该显示装置除了显示面板以外，还包括其他必要的部件和组成，以显示器为例，具体例如外壳、电路板、电源线，等等，本领域技术人员可根据该显示装置的具体使用要求进行相应地补充，在此不再赘述。
与现有技术相比，本公开示例实施方式提供的显示装置的有益效果与上述示例实施方式提供的阵列基板15的有益效果相同，在此不做赘述。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (24)

  1. 一种阵列基板的制备方法，其中，包括：
    依次形成第一电极材料层、导电增强材料层和保护材料层，所述保护材料层的抗氧化性强于所述导电增强材料层的抗氧化性；
    在所述保护材料层的远离所述第一电极材料层的一侧形成掩模图案，所述掩模图案包括第一部分和第二部分，所述第一部分的厚度大于所述第二部分的厚度；
    对所述掩模图案进行灰化，以去除所述第二部分使所述第二部分覆盖的所述保护材料层裸露；
    对所述第一电极材料层进行图案化处理形成第一电极；
    对所述保护材料层以及所述导电增强材料层进行图案化处理对应形成保护层和导电增强层。
  2. 根据权利要求1所述的阵列基板的制备方法，其中，在对所述掩模图案进行灰化之前，所述制备方法还包括：
    对所述保护材料层以及所述导电增强材料层进行图案化处理，使部分所述第一电极材料层裸露。
  3. 根据权利要求1所述的阵列基板的制备方法，其中，在所述保护材料层的远离所述第一电极材料层的一侧形成掩模图案，包括：
    在所述保护材料层的远离所述第一电极材料层的一侧形成掩模层，并对所述掩模层进行半掩模工艺形成所述掩模图案。
  4. 根据权利要求1所述的阵列基板的制备方法，其中，在形成所述第一电极材料层之前，所述制备方法还包括：
    形成有机绝缘材料层，并对所述有机绝缘材料层进行图案化处理形成有机绝缘层和第二过孔。
  5. 根据权利要求1所述的阵列基板的制备方法，其中，在形成所述第一电极材料层之前，所述制备方法还包括：
    在衬底基板的一侧形成多个栅线和多个阵列排布的薄膜晶体管，所述导电增强层在所述衬底基板上的正投影与所述栅线在所述衬底基板上的正投影有交叠，所述保护层在所述衬底基板上的正投影与所述栅线在所述衬底基板上的正投影有交叠。
  6. 根据权利要求5所述的阵列基板的制备方法，其中，形成保护层和导电增强层之后，所述制备方法还包括：
    在所述保护层的远离所述第一电极的一侧形成第二绝缘层，并对所述第二绝缘层进行图案化处理形成第四过孔；
    在所述第二绝缘层的远离所述第一电极的一侧形成第二电极，所述第二电极与所述薄膜晶体管的数据线电连接。
  7. 一种显示面板的制备方法，其中，包括：
    提供一阵列基板，所述阵列基板通过权利要求1～6任意一项所述的制备方法制备；
    提供一彩膜基板，将所述彩膜基板与所述阵列基板对合，所述彩膜基板包括黑矩阵，所述导电增强层在所述衬底基板上的正投影位于所述黑矩阵在所述衬底基板上的正投影内，所述保护层在所述衬底基板上的正投影位于所述黑矩阵在所述衬底基板上的正投影内。
  8. 一种阵列基板，其中，包括：
    第一电极；
    导电增强层，设于所述第一电极的一侧；
    保护层，设于所述导电增强层的远离所述第一电极的一侧，所述保护层的抗氧化性强于所述导电增强层的抗氧化性。
  9. 根据权利要求8所述的阵列基板，其中，所述导电增强层在所述第一电极上的正投影与所述保护层在所述第一电极上的正投影重合。
  10. 根据权利要求8所述的阵列基板，其中，所述阵列基板还包括：
    衬底基板；
    多个薄膜晶体管和多个栅线，所述多个薄膜晶体管阵列排布于所述衬底基板的一侧，所述导电增强层在所述衬底基板上的正投影与所述栅线在所述衬底基板上的正投影有交叠，所述保护层在所述衬底基板上的正投影与所述栅线在所述衬底基板上的正投影有交叠。
  11. 根据权利要求10所述的阵列基板，其中，所述导电增强层的延伸方向与所述栅线的延伸方向一致，所述导电增强层在所述衬底基板上的正投影至少部分位于所述栅线在所述衬底基板上的正投影内，所述保护层的延伸方向与所述栅线的延伸方向一致，所述保护层在所述衬底基 板上的正投影至少部分位于所述栅线在所述衬底基板上的正投影内。
  12. 根据权利要求11所述的阵列基板，其中，所述阵列基板还包括：
    第一隔垫物，设于所述第一电极的远离衬底基板的一侧，且位于相邻两个薄膜晶体管之间；
    所述导电增强层在所述衬底基板上的正投影设置为曲线，所述导电增强层在与所述第一隔垫物相邻的位置向远离所述第一隔垫物一侧凹陷折弯，所述保护层在所述衬底基板上的正投影设置为曲线，所述保护层在与所述第一隔垫物相邻的位置向远离所述第一隔垫物一侧凹陷折弯。
  13. 根据权利要求12所述的阵列基板，其中，所述导电增强层包括第一直线部和第一弯曲部，所述第一直线部在所述衬底基板上的正投影位于所述栅线在所述衬底基板上的正投影内，所述第一弯曲部在所述衬底基板上的正投影至少部分与所述栅线在所述衬底基板上的正投影不交叠；所述保护层包括第二直线部和第二弯曲部，所述第二直线部在所述衬底基板上的正投影位于所述栅线在所述衬底基板上的正投影内，所述第二弯曲部在所述衬底基板上的正投影至少部分与所述栅线在所述衬底基板上的正投影不交叠。
  14. 根据权利要求11-13任意一项所述的阵列基板，其中，所述导电增强层设置为多条，且延伸方向相同；所述保护层设置为多条，且延伸方向相同。
  15. 根据权利要求8所述的阵列基板，其中，所述阵列基板包括薄膜晶体管和数据线，所述导电增强层的延伸方向与所述数据线的延伸方向一致，所述导电增强层在所述衬底基板上的正投影至少部分位于所述数据线在所述衬底基板上的正投影内，所述保护层的延伸方向与所述数据线的延伸方向一致，所述保护层在所述衬底基板上的正投影至少部分位于所述数据线在所述衬底基板上的正投影内。
  16. 根据权利要求8所述的阵列基板，其中，所述阵列基板包括薄膜晶体管和栅线，所述导电增强层的延伸方向与所述栅线的延伸方向一致，所述导电增强层位于所述薄膜晶体管的远离所述栅线的一侧，所述保护层的延伸方向与所述栅线的延伸方向一致，所述保护层位于所述薄膜晶体管的远离所述栅线的一侧。
  17. 根据权利要求10-13、15、16任意一项所述的阵列基板，其中，所述阵列基板还包括：
    有机绝缘层，设于所述多个薄膜晶体管与所述第一电极之间。
  18. 根据权利要求17所述的阵列基板，其中，所述阵列基板还包括：
    第二绝缘层，设于所述第一电极的远离所述衬底基板的一侧；
    第二电极，设于所述第二绝缘层的远离所述衬底基板的一侧，所述第二电极与所述薄膜晶体管的数据线电连接。
  19. 根据权利要求8所述的阵列基板，其中，所述保护层的材质是钛合金，厚度大于等于300A且小于等于500A。
  20. 根据权利要求19所述的阵列基板，其中，所述钛合金包括至少三种金属材料。
  21. 根据权利要求8所述的阵列基板，其中，所述导电增强层的材质是铜，厚度大于等于1000A且小于等于1500A。
  22. 根据权利要求8所述的阵列基板，其中，所述第一电极是公共电极，材质是ITO。
  23. 一种显示面板，其中，包括：
    阵列基板，是权利要求8～22任意一项所述的阵列基板；
    彩膜基板，与所述阵列基板相对设置，所述彩膜基板包括黑矩阵，所述导电增强层在所述衬底基板上的正投影位于所述黑矩阵在所述衬底基板上的正投影内，所述保护层在所述衬底基板上的正投影位于所述黑矩阵在所述衬底基板上的正投影内。
  24. 一种显示装置，其中，包括：权利要求23所述的显示面板。
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CN101330131A (zh) * 2007-06-20 2008-12-24 中国南玻集团股份有限公司 有机电致发光显示器件、透明导电膜基板及制作方法
CN205406523U (zh) * 2016-03-23 2016-07-27 信利半导体有限公司 一种oled的引线电极及oled显示器
CN109119428A (zh) * 2018-07-18 2019-01-01 深圳市华星光电技术有限公司 Tft基板的制作方法
CN109801929A (zh) * 2019-04-17 2019-05-24 南京中电熊猫平板显示科技有限公司 一种阵列基板及其制造方法

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CN205406523U (zh) * 2016-03-23 2016-07-27 信利半导体有限公司 一种oled的引线电极及oled显示器
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CN109801929A (zh) * 2019-04-17 2019-05-24 南京中电熊猫平板显示科技有限公司 一种阵列基板及其制造方法

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