WO2024122162A1 - スイッチング素子 - Google Patents

スイッチング素子 Download PDF

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Publication number
WO2024122162A1
WO2024122162A1 PCT/JP2023/034480 JP2023034480W WO2024122162A1 WO 2024122162 A1 WO2024122162 A1 WO 2024122162A1 JP 2023034480 W JP2023034480 W JP 2023034480W WO 2024122162 A1 WO2024122162 A1 WO 2024122162A1
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Prior art keywords
region
electric field
trench
field relaxation
trenches
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Ceased
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PCT/JP2023/034480
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English (en)
French (fr)
Japanese (ja)
Inventor
拓真 片野
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Denso Corp
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Denso Corp
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Priority to CN202380072975.2A priority Critical patent/CN120167137A/zh
Publication of WO2024122162A1 publication Critical patent/WO2024122162A1/ja
Priority to US19/229,613 priority patent/US20250301724A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices

Definitions

  • the technology disclosed in this specification relates to switching elements.
  • Japanese Patent Publication No. 2015-167208 discloses a switching element having a trench-type gate electrode.
  • the switching element When the switching element is turned off, the drift region is depleted and an electric field is generated within the drift region. In this type of switching element, the electric field tends to concentrate at the bottom end of the trench.
  • a technique is known in which a p-type electric field relaxation region is provided to suppress the electric field concentration at the bottom end of the trench.
  • the electric field relaxation region is placed in a depth range that includes the bottom end of the trench, or in a depth range that is lower than the bottom end of the trench. By providing the electric field relaxation region, the depletion layer tends to spread around the bottom end of the trench, and the electric field concentration at the bottom end of the trench is alleviated.
  • the switching element disclosed in this specification has a semiconductor substrate having a plurality of trenches on its upper surface, a gate insulating film covering the inner surface of the trench, and a gate electrode disposed within the trench and insulated from the semiconductor substrate by the gate insulating film.
  • the portion of the semiconductor substrate where the plurality of trenches are disposed is an element portion.
  • the element portion has a central portion and an outer peripheral portion.
  • the element portion has an n-type source region contacting the gate insulating film on the side surface of each of the trenches.
  • the element portion and the outer peripheral portion have a body region, a drift region, and an electric field relaxation region.
  • the body region is a p-type region contacting the gate insulating film on the side surface of each of the trenches.
  • the drift region is disposed below the body region, is separated from the source region by the body region, and is an n-type region contacting the gate insulating film on the side surface of each of the trenches.
  • the electric field relaxation region is disposed in a depth range including the lower end of each of the trenches or in a depth range below the lower end of each of the trenches, is connected to the body region, and is a plurality of p-type regions spaced apart in the lateral direction of the semiconductor substrate.
  • the drift region is distributed within the gap between the electric field buffer regions.
  • the value Wp/Wn obtained by dividing the width Wp of each electric field buffer region in the lateral direction by the width Wn of the gap between the electric field buffer regions is larger in the outer periphery than in the central portion.
  • the electric field at the bottom end of each trench is relaxed by the electric field relaxation region. Furthermore, the electric field relaxation region is arranged so that the value Wp/Wn is greater in the outer periphery than in the central portion. That is to say, within the depth range of the electric field relaxation region, the ratio of p-type regions is greater in the outer periphery than in the element portion. Therefore, in the outer periphery, the depletion layer is more likely to spread from the electric field relaxation region to its surroundings than in the element portion. This effectively relaxes the electric field concentration at the bottom end of the trench in the outer periphery. In this way, this switching element can relax the electric field concentration in the outer periphery of the element portion.
  • FIG. FIG. 1A is a vertical cross-sectional view of a central portion 60a along the x-direction (i.e., a vertical cross-sectional view taken along line III-III in FIG. 1).
  • 4 is a vertical cross-sectional view of the outer peripheral portion 60b along the x direction (i.e., a vertical cross-sectional view taken along line IV-IV in FIG. 1).
  • FIG. 2 is a vertical cross-sectional view of a central portion 60a along the y direction (i.e., a vertical cross-sectional view taken along line VV in FIG. 1).
  • FIG. 6 is a vertical cross-sectional view of the outer peripheral portion 60b along the y direction (i.e., a vertical cross-sectional view taken along line VI-VI in FIG. 1).
  • FIG. 13 is a cross-sectional perspective view of a switching element according to a first modified example.
  • FIG. 11 is a cross-sectional perspective view of a switching element according to a second modified example.
  • FIG. 11 is a cross-sectional perspective view of a switching element according to a third modified example.
  • the switching element disclosed in this specification may further include a source electrode (22) that covers the upper surface of the semiconductor substrate in the central portion and the outer periphery and contacts the body region and the source region, and an insulating layer (28) that covers the upper surface of the source electrode in the outer periphery.
  • This configuration makes it possible to prevent a high electric field from being applied to the gate insulating film in the outer periphery in a high temperature environment.
  • the outer periphery does not need to have the source region.
  • This configuration makes it possible to stabilize the operation of the switching element by suppressing the current flowing through the outer periphery.
  • the switching element 10 has a semiconductor substrate 12.
  • the semiconductor substrate 12 is made of SiC.
  • the semiconductor substrate 12 may be made of other semiconductors such as Si or GaN.
  • one direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x-direction
  • a direction parallel to the upper surface 12a and perpendicular to the x-direction is referred to as the y-direction
  • the thickness direction of the semiconductor substrate 12 is referred to as the z-direction.
  • a source electrode 22 and a plurality of electrode pads 23 are provided on the upper surface 12a of the semiconductor substrate 12.
  • the plurality of electrode pads 23 include an electrode pad for controlling the gate potential, an electrode pad for outputting the potential of the source electrode 22, an electrode pad for outputting the temperature of the semiconductor substrate 12, and the like.
  • a plurality of trenches 14 are provided on the upper surface 12a of the semiconductor substrate 12 within the range covered by the source electrode 22. Each trench 14 extends linearly in the y-direction. Each trench 14 is arranged at intervals in the x-direction.
  • the main part of the switching element 10 is formed in the range where the plurality of trenches 14 are provided.
  • the element portion 60 has a central portion 60a and an outer peripheral portion 60b.
  • the outer peripheral portion 60b is provided around the central portion 60a.
  • Figures 2 to 4 show the structure of the element portion 60. More specifically, Figures 2 and 3 show the structure of the central portion 60a, and Figure 4 shows the structure of the peripheral portion 60b. Note that the source electrode 22 is omitted in Figure 2. As shown in Figures 2 to 4, the inner surface of each trench 14 is covered with a gate insulating film 16. A gate electrode 18 is disposed in each trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. The upper surface of each gate electrode 18 is covered with an interlayer insulating film 20. The source electrode 22 is insulated from the gate electrode 18 by the interlayer insulating film 20.
  • the source electrode 22 is made of AlSi. As shown in FIG. 3, in the central portion 60a, the source electrode 22 is covered with a Ni layer 26. Although not shown, the Ni layer 26 is connected to an external electrode block by solder. As shown in FIG. 4, in the peripheral portion 60b, the source electrode 22 is covered with an insulating resin layer 28 (e.g., a polyimide layer). The insulating resin layer 28 has a low thermal conductivity. Therefore, the central portion 60a has higher heat dissipation properties than the peripheral portion 60b.
  • insulating resin layer 28 e.g., a polyimide layer
  • a drain electrode 24 is provided on the lower part of the semiconductor substrate 12.
  • the drain electrode 24 covers the lower surface 12b of the semiconductor substrate 12.
  • the semiconductor substrate 12 has a number of source regions 40, a body region 42, a drift region 44, a drain region 46, and a number of electric field relaxation regions 48.
  • Each source region 40 is an n-type region having a high n-type impurity concentration. As shown in Figures 2 and 3, each source region 40 is disposed in an area sandwiched between trenches 14. Each source region 40 is in ohmic contact with the source electrode 22. Each source region 40 is in contact with the gate insulating film 16 on the side of the trench 14. The source region 40 is provided in the central portion 60a. As shown in Figure 4, the source region 40 is not provided in the outer peripheral portion 60b.
  • the body region 42 is distributed across the central portion 60a and the peripheral portion 60b.
  • the body region 42 has multiple contact regions 42a and low-concentration regions 42b having a lower p-type impurity concentration than each of the contact regions 42a.
  • Each contact region 42a is disposed in an area sandwiched between the trenches 14.
  • Each contact region 42a is in ohmic contact with the source electrode 22.
  • the low-concentration regions 42b are in contact with the multiple source regions 40 and the multiple contact regions 42a from below.
  • the low-concentration regions 42b are in contact with the gate insulating film 16 on the side of the trench 14. In the central portion 60a, the low-concentration regions 42b are in contact with the gate insulating film 16 on the lower side of each source region 40.
  • the drift region 44 is distributed across the central portion 60a and the outer peripheral portion 60b.
  • the drift region 44 is an n-type region having a lower n-type impurity concentration than the source region 40.
  • the drift region 44 is distributed across the lower portions of the multiple trenches 14.
  • the upper end of the drift region 44 extends into the range between the trenches 14.
  • the drift region 44 contacts the low concentration region 42b from below within the range between the trenches 14.
  • the drift region 44 contacts the gate insulating film 16 below the low concentration region 42b.
  • the drain region 46 is distributed across the central portion 60a and the outer peripheral portion 60b.
  • the drain region 46 is an n-type region having a higher n-type impurity concentration than the drift region 44.
  • the drain region 46 contacts the drift region 44 from below.
  • the drain region 46 is in ohmic contact with the drain electrode 24 on the lower surface 12b of the semiconductor substrate 12.
  • the electric field relaxation regions 48 are provided in the central portion 60a and the outer peripheral portion 60b. Each electric field relaxation region 48 is arranged in an area surrounded by the drift region 44. Each electric field relaxation region 48 is arranged below the low concentration region 42b with a gap therebetween. A drift region 44 is distributed in the gap between each electric field relaxation region 48 and the low concentration region 42b. Each electric field relaxation region 48 extends linearly in the x direction. Each electric field relaxation region 48 is arranged with a gap in the y direction. A drift region 44 is distributed in each gap between the electric field relaxation regions 48. Hereinafter, the drift region 44 in each gap between the electric field relaxation regions 48 is referred to as a gap portion 44a. Each electric field relaxation region 48 is arranged in an area including the lower end of the trench 14 in the z direction. Therefore, each electric field relaxation region 48 contacts the gate insulating film 16 at the lower end of each trench 14.
  • the semiconductor substrate 12 has a p-type connection region 52.
  • the connection region 52 connects the electric field relaxation region 48 and the low concentration region 42b. Although one connection region 52 is shown in FIG. 2, at least one connection region 52 is provided for each electric field relaxation region 48. Therefore, the potential of each electric field relaxation region 48 is approximately equal to the potential of the body region 42.
  • the symbol Wp indicates the width of each electric field relaxation region 48 in the y direction
  • the symbol Wn indicates the width of each gap between the electric field relaxation regions 48 in the y direction (i.e., the width of the gap 44a).
  • the width Wp of the electric field relaxation region 48 is narrower in the central portion 60a than in the outer periphery 60b.
  • the width Wn of the gap 44a is wider in the central portion 60a than in the outer periphery 60b. Therefore, the value Wp/Wn obtained by dividing the width Wp by the width Wn is smaller in the central portion 60a than in the outer periphery 60b.
  • the value Wp/Wn represents the ratio of the electric field relaxation region 48 to the gap 44a within the range in the z direction in which the electric field relaxation region 48 exists.
  • the switching element 10 is used in a state where a voltage is applied in a direction in which the drain electrode 24 has a higher potential than the source electrode 22.
  • a potential equal to or higher than the gate threshold is applied to the gate electrode 18
  • a channel is formed in the body region 42 near the gate insulating film 16, and the source region 40 and the drift region 44 are connected by the channel. Therefore, electrons flow from the source electrode 22 to the drift region 44 via the source region 40 and the channel. Electrons that flow from the channel into the drift region 44 flow through the gap 44a to the drift region 44 below the electric field relaxation region 48. Electrons flow from the drift region 44 to the drain electrode 24 via the drain region 46. In this way, when a potential equal to or higher than the gate threshold is applied to the gate electrode 18, the switching element 10 turns on.
  • the switching element 10 when the switching element 10 is turned on, electrons pass through the gap 44a.
  • the value Wp/Wn is small, so the ratio of the gap 44a (i.e., the n-type region) is large within the depth range in which the electric field relaxation region 48 exists. Therefore, in the central portion 60a, the resistance of the gap 44a is small. Therefore, electrons can flow with low loss in the central portion 60a.
  • the value Wp/Wn is large, and the resistance of the gap 44a is high. However, fewer electrons flow in the outer peripheral portion 60b than in the central portion 60a.
  • the source region 40 is not provided in the outer peripheral portion 60b, very few electrons flow in the gap 44a in the outer peripheral portion 60b. Therefore, even if the resistance of the gap 44a is large in the outer peripheral portion 60b, not much loss occurs. Therefore, the on-resistance of the switching element 10 is low.
  • the channel disappears and the switching element 10 turns off.
  • the switching element 10 turns off, a reverse voltage is applied to the pn junction at the interface between the body region 42 and the drift region 44.
  • the electric field relaxation region 48 has approximately the same potential as the body region 42, a reverse voltage is also applied to the pn junction at the interface between the electric field relaxation region 48 and the drift region 44. Therefore, a depletion layer extends from the body region 42 and the electric field relaxation region 48 to the drift region 44.
  • the depleted drift region 44 holds the voltage between the drain electrode 24 and the source electrode 22.
  • the depletion layer extending from the electric field relaxation region 48 to the drift region 44 depletes the drift region 44 around the lower end of the trench 14. In this way, the drift region 44 is depleted around the lower end of the trench 14, thereby suppressing electric field concentration in the gate insulating film 16 covering the lower end of the trench 14.
  • the electric field is particularly likely to concentrate at the lower end of the trench 14 in the outer peripheral portion 60b.
  • the value Wp/Wn is large in the outer peripheral portion 60b, and the ratio of the electric field relaxation region 48 (i.e., p-type region) to the interval portion 44a (i.e., n-type region) is large. Therefore, in the outer peripheral portion 60b, the depletion layer is likely to spread from the electric field relaxation region 48 to its periphery. Therefore, the effect of relaxing the electric field concentration by the electric field relaxation region 48 is higher in the outer peripheral portion 60b than in the central portion 60a.
  • the electric field concentration at the lower end of the trench 14 in the outer peripheral portion 60b can be suppressed.
  • the outer peripheral portion 60b has lower heat dissipation than the central portion 60a, and the outer peripheral portion 60b is more likely to become hotter than the central portion 60a. If a high electric field is applied to the gate insulating film 16 in a high temperature state, the gate insulating film 16 is likely to deteriorate. By suppressing electric field concentration on the gate insulating film 16 in the outer peripheral portion 60b, which is prone to high temperatures, deterioration of the gate insulating film 16 can be more effectively suppressed.
  • the electric field relaxation regions 48 extend linearly in the x direction (i.e., the direction intersecting the trenches 14) and are spaced apart in the y direction.
  • the electric field relaxation regions 48 may extend linearly in the y direction (i.e., the direction parallel to the trenches 14) and be spaced apart in the x direction.
  • the electric field relaxation regions 48 may be arranged between the trenches 14 in the x direction, or as shown in FIG. 8, the electric field relaxation regions 48 may be arranged at positions overlapping with the trenches 14 in the x direction (i.e., below the trenches 14).
  • the electric field concentration on the gate insulating film 16 in the outer periphery 60b can be suppressed by making the value Wp/Wn larger in the outer periphery 60b than in the central portion 60a.
  • the electric field relaxation region 48 is disposed in a depth range including the lower end of the trench 14, but the electric field relaxation region 48 may be disposed in a depth range below the lower end of the trench 14.
  • the electric field relaxation region 48 may be disposed below the lower end of the trench 14 as shown in FIG. 9.
  • the electric field relaxation region 48 may be disposed below the lower end of the trench 14. Even if the electric field relaxation region 48 is disposed below the lower end of the trench 14, electric field concentration at the lower end of the trench 14 can be suppressed.
  • the source region 40 is not provided in the outer peripheral portion 60b, but the source region 40 may be provided in the outer peripheral portion 60b.
  • the width Wp is wider in the outer circumferential portion 60b than in the central portion 60a, and the width Wn is narrower in the outer circumferential portion 60b than in the central portion 60a.
  • the widths Wp and Wn may be set in any manner in the central portion 60a and the outer circumferential portion 60b.
  • the width Wp may be wider in the outer circumferential portion 60b than in the central portion 60a, and the width Wn may be equal in the outer circumferential portion 60b and the central portion 60a.
  • the width Wp may be equal in the outer circumferential portion 60b and the central portion 60a, and the width Wn may be narrower in the outer circumferential portion 60b than in the central portion 60a.

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PCT/JP2023/034480 2022-12-07 2023-09-22 スイッチング素子 Ceased WO2024122162A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202380072975.2A CN120167137A (zh) 2022-12-07 2023-09-22 开关元件
US19/229,613 US20250301724A1 (en) 2022-12-07 2025-06-05 Switching element

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JP2022195543A JP7852479B2 (ja) 2022-12-07 2022-12-07 スイッチング素子
JP2022-195543 2022-12-07

Related Child Applications (1)

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US19/229,613 Continuation US20250301724A1 (en) 2022-12-07 2025-06-05 Switching element

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011253837A (ja) * 2010-05-31 2011-12-15 Denso Corp 炭化珪素半導体装置およびその製造方法
JP2014138026A (ja) * 2013-01-15 2014-07-28 Sumitomo Electric Ind Ltd 炭化珪素半導体装置
WO2019008884A1 (ja) * 2017-07-04 2019-01-10 住友電気工業株式会社 炭化珪素半導体装置
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