CN112151598A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN112151598A
CN112151598A CN202010592346.0A CN202010592346A CN112151598A CN 112151598 A CN112151598 A CN 112151598A CN 202010592346 A CN202010592346 A CN 202010592346A CN 112151598 A CN112151598 A CN 112151598A
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low current
main
semiconductor substrate
semiconductor device
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神谷真行
川岛崇功
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Denso Corp
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Denso Corp
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Abstract

本发明的技术课题是让高的电流流过在端子的外侧的范围设置有有源区的半导体装置。一种半导体装置，具有：半导体基板；上部电极，设置于所述半导体基板的上表面；下部电极，其设置于所述半导体基板的下表面；以及端子，其与所述上部电极连接。所述半导体基板具有形成有开关元件的有源区，所述开关元件能够让电流流过所述上部电极与所述下部电极之间。所述有源区具有位于所述端子的正下方的主要区域、和位于所述主要区域的外部的外部区域。所述外部区域具有低电流区域。在所述低电流区域内的所述开关元件以及所述主要区域内的所述开关元件接通了时，所述低电流区域内的电流密度比所述主要区域内的电流密度低。

Description

半导体装置
技术领域
本说明书公开的技术涉及半导体装置。
背景技术
专利文献1公开的半导体装置具有：半导体基板；上部电极，设置于所述半导体基板的上表面；下部电极，设置于所述半导体基板的下表面；以及端子(铜块)，与所述上部电极连接。半导体基板具有形成有开关元件的有源区，所述开关元件能够让电流流过上部电极与下部电极之间。一般地，有源区仅形成于端子的正下方及其附近。因此，在电流流过开关元件而有源区发热时，通过端子将热从有源区散走。由此，抑制有源区的温度上升。
专利文献1：日本专利申请特开2018-129388号公报
为了扩大有源区，可以在端子的外侧的范围(未被端子覆盖的范围)大范围地设置有源区。然而，如果像这样在端子的外侧的范围大范围地设置有源区，则在该范围产生的热难以传导到端子。因此，在端子的外侧设置的有源区比端子的正下方的有源区的温度高。其结果，存在虽然端子的正下方的有源区(主要区域)未变为很高的温度，但电流无法再流过半导体装置的问题。在本说明书中，提出了一种半导体装置，其在端子的外侧的范围设置有有源区，并能够流过高的电流。
发明内容
本说明书公开的半导体装置具有：半导体基板；上部电极，设置于所述半导体基板的上表面；下部电极，设置于所述半导体基板的下表面；以及端子，与所述上部电极连接。所述半导体基板具有形成有开关元件的有源区，所述开关元件能够让电流流过所述上部电极与所述下部电极之间。所述有源区具有位于所述端子的正下方的主要区域、和位于所述主要区域的外部的外部区域。所述外部区域具有低电流区域。在所述低电流区域内的所述开关元件以及所述主要区域内的所述开关元件接通了时，所述低电流区域内的电流密度比所述主要区域内的电流密度低。
在该构成中，在主要区域内的开关元件以及低电流区域(端子的外侧的区域)内的开关元件同时接通了时，低电流区域内的电流密度比主要区域内的电流密度低。由此，抑制在低电流区域中的发热，抑制低电流区域的温度上升。因此，高的电流都能够流过半导体装置，直至主要区域变为高温。
附图说明
图1是半导体装置的剖视图。
图2是从上观察半导体基板和端子70的俯视图。
图3是主要区域的剖视图。
图4是实施例1的低电流区域的剖视图。
图5是实施例2的低电流区域的剖视图。
图6是实施例3的低电流区域的剖视图。
图7是示出变更了低电流区域的配置的变形例的俯视图。
图8是示出变更了低电流区域的配置的变形例的俯视图。
图9是示出附加了温度传感器的变形例的俯视图。
具体实施方式
[实施例1]
图1示出了实施例1的半导体装置10。如图1所示，半导体装置10具有半导体基板12。另外，在以下的说明中，x方向意味着与半导体基板12平行的一个方向，y方向意味着与半导体基板12平行并与x方向正交的一个方向，z方向意味着与半导体基板12垂直的一个方向。
半导体基板12由SiC(碳化硅)的单晶构成。在半导体基板12的内部设置有开关元件。在半导体基板12的上表面设置有上部电极14和信号电极18。如图2所示，在半导体基板12的上表面设置有多个信号电极18。如图1所示，在半导体基板12的下表面设置有下部电极16。下部电极16覆盖半导体基板12的整个下表面。
如图1所示，在上部电极14的上面配置有端子70。端子70是金属材质的块。端子70经由未图示的焊层与上部电极14连接。在端子70的上面配置有散热板72。散热板72是金属板。散热板72经由未图示的焊层与端子70连接。散热板72将热从半导体基板12散走。此外，散热板72作为与半导体基板12连接的电极板发挥功能。
各信号电极18通过键合线76与信号端子78连接。用于控制开关元件的各种信号输入输出到各信号电极18。
在下部电极16的下面配置有散热板74。散热板74是金属板。散热板74经由未图示的焊层与下部电极16连接。散热板74将热从半导体基板12散走。此外，散热板74还作为与半导体基板12连接的电极板发挥功能。
半导体基板12、端子70、散热板72、74的周围被绝缘树脂80覆盖。
图2示出了从上侧俯视半导体基板12时的上部电极14、信号电极18及端子70的配置。如图2所示，在半导体基板12的上表面的大范围内设置上部电极14。多个信号电极18设置于不存在上部电极14的范围。端子70覆盖上部电极14的大部分。上部电极14的一部分配置在端子70的外侧。如下文详细描述的那样，在上部电极14的下面的半导体区域形成有开关元件。以下，将上部电极14的下面的半导体区域称为有源区90。此外，被端子70覆盖的范围的有源区90称为主要区域92。此外，未被端子70覆盖的范围的有源区90称为外部区域94。如图2所示，外部区域94具有端子70的周围的部分96和与信号电极18相邻的部分98。在以下，将部分96称为周边区域。此外，下文中将详细描述到，与主要区域92及周边区域96相比，电流更难流过部分98。以下将部分98称为低电流区域98。
如图2所示，各信号电极18相对于主要区域92位于y方向上。低电流区域98从主要区域92及周边区域96向y方向凸出。即，低电流区域98相对于主要区域92位于y方向上。此外，低电流区域98相对于信号电极18位于x方向上。
图3示出了主要区域92的剖面构造。另外，周边区域96也具有与图3相同的剖面构造。此外，图4示出了低电流区域98的剖面构造。首先，以下说明主要区域92与低电流区域98共通的构造。
如图3、图4所示，在主要区域92及低电流区域98内的半导体基板12的上表面设置有槽40。各槽40在半导体基板12的上表面在x方向上伸长。各槽40的内表面被栅极绝缘膜42覆盖。在各槽40内配置有栅电极44。通过栅极绝缘膜42将各栅电极44从半导体基板12绝缘。各栅电极44的上表面被层间绝缘膜46覆盖。通过层间绝缘膜46将各栅电极44从上部电极14绝缘。
如图3、图4所示，主要区域92及低电流区域98内的半导体基板12具有多个源极区域20、多个触头区域22、主体区域24、漂移区域26及漏极区域28。
如图3、图4所示，各源极区域20是n型区域。各源极区域20配置在由相邻的槽40夹着的半导体区域(以下称为槽间半导体区域)内。在每个槽间半导体区域设置有2个源极区域20。各源极区域20与上部电极14欧姆接触。此外，各源极区域20在槽40的上端部与栅极绝缘膜42接触。
如图3、图4所示，各触头区域22是p型区域。各触头区域22配置于槽间半导体区域。在每个槽间半导体区域设置有1个触头区域22。各触头区域22在不存在源极区域20的范围与上部电极14欧姆接触。
如图3、图4所示，主体区域24是p型区域。主体区域24的p型杂质浓度比触头区域22的p型杂质浓度低。主体区域24跨多个槽间半导体区域而分布。在各槽间半导体区域，主体区域24从下侧接触源极区域20及触头区域22。主体区域24在各源极区域20的下侧与栅极绝缘膜42接触。
如图3、图4所示，漂移区域26是n型区域。漂移区域26的n型杂质浓度比源极区域20的n型杂质浓度低。漂移区域26从下侧接触主体区域24。漂移区域26在主体区域24的下侧与各栅极绝缘膜42接触。
如图3、图4所示，漏极区域28是n型区域。漏极区域28的n型杂质浓度比漂移区域26的n型杂质浓度高。漏极区域28从下侧接触漂移区域26。漏极区域28与下部电极16接触。
由源极区域20、触头区域22、主体区域24、漂移区域26、漏极区域28、栅极绝缘膜42及栅电极44等，在主要区域92、周边区域96及低电流区域98的各自区域形成开关元件(更具体而言，形成n沟道型MOSFET(metal oxide semiconductor field effect transistor))。主要区域92、周边区域96及低电流区域98内的各栅电极44通过未图示的栅极布线彼此连接。由此，共同的栅极电压施加于主要区域92内的栅电极44、周边区域96内的栅电极44及低电流区域98内的栅电极44。
接下来，对主要区域92与低电流区域98的构造的不同点进行说明。如图3、图4所示，低电流区域98内的主体区域24的p型杂质浓度比主要区域92内的主体区域24的p型杂质浓度高。因此，低电流区域98内的开关元件的栅极阈值比主要区域92内的开关元件的栅极阈值高。
此外，如上所述，在主要区域92内上部电极14与端子70连接，与之相对，在低电流区域98内上部电极14不与端子70连接。因此，低电流区域98的散热性能比主要区域92的散热性能低。
在使主要区域92、周边区域96及低电流区域98内的开关元件接通的情况下，使各栅电极44的电位上升为比低电流区域98内的开关元件的栅极阈值高的电位。于是，分别在主要区域92、周边区域96及低电流区域98中，在主体区域24的与栅极绝缘膜42接触的部分形成沟道，漂移区域26通过沟道与各源极区域20连接。于是，电流从下部电极16经由漏极区域28、漂移区域26、沟道及源极区域20流向上部电极14。低电流区域98内的开关元件的栅极阈值比主要区域92及周边区域96内的开关元件的栅极阈值高，因此在低电流区域98内形成的沟道的电阻比在主要区域92及周边区域96内形成的沟道的电阻高。因此，流过低电流区域98的电流的密度比流过主要区域92及周边区域96的电流的密度低。由此，低电流区域98中每单位面积的发热量比主要区域92及周边区域96中每单位面积的发热量小。如上所述，在主要区域92内端子70与上部电极14连接，因此主要区域92的散热性能高。此外，周边区域96配置在主要区域92(即，端子70)的周围，因此周边区域96的散热性能相对较高。由此，即使主要区域92和周边区域96的发热量大，也能抑制主要区域92和周边区域96的温度上升。此外，如上所述，在低电流区域98没有端子70连接在上部电极14上，因此低电流区域98的散热性能低。然而，低电流区域98的发热量小，因此抑制低电流区域98的温度上升。
如以上说明的那样，在实施例1的半导体装置10中，在主要区域92、周边区域96及低电流区域98之中的每个区域，都抑制了温度上升。尤其，在实施例1中，以使主要区域92的中央部的温度比低电流区域98的温度略高的方式，设定了主要区域92与低电流区域98的电流密度之比。由此，电流能够流过半导体装置10，直至主要区域92变为高温，而不受低电流区域98的温度带来的限制。此外，在该半导体装置10中，在电流流过主要区域92时，电流也流过低电流区域98。由此，与不存在低电流区域98的情况相比，高的电流能够流过半导体装置10。
此外，在实施例1中，如图2所示，在相对于信号电极18位于x方向上并且相对于主要区域92位于y方向上的范围中，存在低电流区域98。像这样，在与信号电极18相邻的空间设置低电流区域98，能够更加有效地利用半导体基板12，能够让更高的电流流过半导体基板12。
[实施例2]
接下来，对实施例2的半导体装置进行说明。实施例2的半导体装置的主要区域92和周边区域96，具有与实施例1的主要区域92和周边区域96相同的构造(图3的构造)。在实施例2的半导体装置中，低电流区域98的构造与实施例1(图4的构造)不同。
图5示出了实施例2的半导体装置的低电流区域98的构造。通过比较图3、图5明确可知，在实施例2的半导体装置中，低电流区域98内的栅极绝缘膜42比主要区域92内的栅极绝缘膜42厚。此外，在实施例2的半导体装置中，低电流区域98内的主体区域24的p型杂质浓度与主要区域92内的主体区域24的p型杂质浓度相同。在其他的方面，实施例2的低电流区域98的构造与实施例1的低电流区域98的构造相同。
如上所述，在实施例2中，低电流区域98内的栅极绝缘膜42比主要区域92内的栅极绝缘膜42厚。因此，低电流区域98内的开关元件的栅极阈值比主要区域92内的开关元件的栅极阈值高。由此，在实施例2中也与实施例1同样地，在使开关元件接通的情况下，流过低电流区域98的电流的密度比流过主要区域92及周边区域96的电流的密度低。由此，低电流区域98中每单位面积的发热量比主要区域92及周边区域96中每单位面积的发热量小。由此，抑制散热性能低的低电流区域98的温度上升。
在实施例2中，与实施例1同样地，以使主要区域92的中央部的温度比低电流区域98的温度略高的方式，设定了主要区域92与低电流区域98的电流密度之比。由此，电流能够流过半导体装置而不受低电流区域98的温度带来的限制。此外，在实施例2中，与实施例1同样地，电流不仅能够流过主要区域92和周边区域96，还能够流过低电流区域98。由此，与不存在低电流区域98的情况相比，高的电流能够流过半导体装置。
[实施例3]
接下来，对实施例3的半导体装置进行说明。实施例3的半导体装置的主要区域92和周边区域96具有与实施例1的主要区域92和周边区域96相同的构造(图3的构造)。在实施例3的半导体装置中，低电流区域98的构造与实施例1(图4的构造)不同。
图6示出了实施例3的半导体装置的低电流区域98的构造。通过比较图3、图6明确可知，在实施例3的半导体装置中，低电流区域98内的主体区域24的厚度比主要区域92内的主体区域24的厚度厚。低电流区域98内的各槽40贯通厚的主体区域24。因此，源极区域20与漂移区域26之间的间隔的沿着栅极绝缘膜42的距离Lc(所谓的沟道长度)，在低电流区域98内比在主要区域92内长。此外，在实施例3中，低电流区域98内的漂移区域26的厚度比主要区域92内的漂移区域26的厚度薄。此外，在实施例3的半导体装置中，低电流区域98内的主体区域24的p型杂质浓度与主要区域92内的主体区域24的p型杂质浓度相同。在其他的方面，实施例3的低电流区域98的构造与实施例1的低电流区域98的构造相同。
如上所述，在实施例3中，低电流区域98内的沟道长度Lc比主要区域92内的沟道长度Lc长。此外，沟道长度Lc长，与该长度差距相应地，则低电流区域98内的漂移区域26的厚度比主要区域92内的漂移区域26的厚度薄。通过这样的构成，在开关元件接通了时，低电流区域98内的电流路径的电阻比主要区域92内的电流路径的电阻高。由此，在实施例3中，也与实施例1同样地，在使开关元件接通的情况下，流过低电流区域98的电流的密度比流过主要区域92及周边区域96的电流的密度低。由此，低电流区域98中每单位面积的发热量比主要区域92及周边区域96中每单位面积的发热量小。由此，抑制散热性能低的低电流区域98的温度上升。
在实施例3中，与实施例1同样地，以使主要区域92的中央部的温度比低电流区域98的温度略高的方式，设定了主要区域92与低电流区域98的电流密度之比。由此，电流能够流过半导体装置而不受低电流区域98的温度带来的限制。此外，在实施例3中，与实施例1同样地，电流不仅能够流过主要区域92和周边区域96，还能够流过低电流区域98。由此，与不存在低电流区域98的情况相比，高的电流能够流过半导体装置。
另外，也可以将上述实施例1～3的构成进行组合。例如，也可以分别针对主体区域24的p型杂质浓度、栅极绝缘膜42的厚度及沟道长度，在主要区域92与低电流区域98之间设置差异，使低电流区域98的电流密度比主要区域92的电流密度低。
此外，在上述实施例1～3中，如图2那样，在排列有信号电极18的范围的单侧设置有低电流区域98。然而，也可以如图7那样，在排列有信号电极18的范围的两侧设置低电流区域98。此外，也可以如图8那样，在各信号电极18之间的范围设置低电流区域98。
此外，也可以如图9那样，在与端子70交叠的范围中设置温度传感器88。在图9的构成中，上部电极14被分隔为2个。在2个上部电极14之间的位置设置有温度传感器88。温度传感器88夹在半导体基板12与端子70之间。温度传感器88设置在半导体基板12的中央部。温度传感器88检测主要区域92的温度。只要使低电流区域98的温度比主要区域92的温度低，则能够通过温度传感器88来检测即使在半导体基板12中温度也是比较高的主要区域92的温度。因此，能够通过温度传感器88合适地检测半导体基板12的过热。
对上述实施方式的各构成要素与权利要求的各构成要素的关系进行说明。实施方式的源极区域是权利要求的第一区域的一个例子。实施方式的漂移区域是权利要求的第二区域的一个例子。
以下列举本说明书公开的技术要素。另外，以下的各技术要素分别是独立而有用的技术要素。
在本说明书公开的一个例子的半导体装置中，还可以具有设置于半导体基板的上表面且设置于有源区的外部的信号电极。此外，在俯视半导体基板的上表面的状态下，在将从主要区域向着信号电极的方向作为第一方向、并将与第一方向正交的方向作为第二方向时，也可以是，低电流区域相对于主要区域位于第一方向上，并且相对于信号电极位于第二方向上。
根据该构成，能够使半导体基板内的空置区域(space)作为低电流区域工作。
在本说明书公开的一个例子的半导体装置中，还可以具有测量主要区域的温度的温度传感器。
根据该构成，能够检测半导体基板中的高温部的温度。
在本说明书公开的一个例子的半导体装置中，可以是，有源区内的开关元件具有：n型的第一区域；p型的主体区域；n型的第二区域，其被主体区域从第一区域分离；栅极绝缘膜；栅电极，其隔着栅极绝缘膜与主体区域对置。在该情况下，低电流区域内的主体区域的p型杂质浓度也可以比主要区域内的主体区域的p型杂质浓度高。此外，低电流区域内的栅极绝缘膜的厚度也可以比主要区域内的栅极绝缘膜的厚度厚。此外，低电流区域内的第一区域与第二区域之间的间隔也可以比主要区域内的第一区域与第二区域之间的间隔长。
根据这些构成，能够使低电流区域内的电流密度比主要区域内的电流密度低。
在本说明书公开的一个例子的半导体装置中，半导体基板也可以由SiC构成。
以上，对实施方式详细进行了说明，但这些仅是例示，不用于限定权利要求的范围。权利要求书记载的技术包括将以上例示的具体例子进行各种变形、变更而得的技术。在本说明书或者附图中说明的技术要素是单独或者通过各种组合来发挥技术有用性的技术要素，不限于在申请时权利要求中记载的组合。此外，在本说明书或者附图中例示的技术是同时达成多个目的的技术，达成这些多个目的之中的一个目的即可使其具有技术有用性。

Claims (8)

1.一种半导体装置，具有：
半导体基板；
上部电极，设置于所述半导体基板的上表面；
下部电极，设置于所述半导体基板的下表面；以及
端子，与所述上部电极连接，
所述半导体基板具有形成有开关元件的有源区，所述开关元件能够让电流流过所述上部电极与所述下部电极之间，
所述有源区具有位于所述端子的正下方的主要区域、和位于所述主要区域的外部的外部区域，
所述外部区域具有低电流区域，
在所述低电流区域内的所述开关元件以及所述主要区域内的所述开关元件接通了时，所述低电流区域内的电流密度比所述主要区域内的电流密度低。
2.根据权利要求1所述的半导体装置，其中，还具有设置于所述半导体基板的所述上表面且位于所述有源区的外部的信号电极，
在俯视所述半导体基板的所述上表面的状态下，在将从所述主要区域向着所述信号电极的方向作为第一方向并将与所述第一方向正交的方向作为第二方向时，所述低电流区域相对于所述主要区域位于所述第一方向上，并且相对于所述信号电极位于所述第二方向上。
3.根据权利要求1或2所述的半导体装置，其中，还具有测量所述主要区域的温度的温度传感器。
4.根据权利要求1至3中任意一项所述的半导体装置，其中，所述有源区内的所述开关元件具有：
n型的第一区域；
p型的主体区域；
n型的第二区域，被所述主体区域从所述第一区域分离；
栅极绝缘膜；以及
栅电极，隔着所述栅极绝缘膜与所述主体区域对置。
5.根据权利要求4所述的半导体装置，其中，
所述低电流区域内的所述主体区域的p型杂质浓度，比所述主要区域内的所述主体区域的p型杂质浓度高。
6.根据权利要求4或5所述的半导体装置，其中，
所述低电流区域内的所述栅极绝缘膜的厚度比所述主要区域内的所述栅极绝缘膜的厚度厚。
7.根据权利要求4至6中任意一项所述的半导体装置，其中，
所述低电流区域内的所述第一区域与所述第二区域之间的间隔，比所述主要区域内的所述第一区域与所述第二区域之间的间隔长。
8.根据权利要求1至7中任意一项所述的半导体装置，其中，
所述半导体基板由SiC构成。
CN202010592346.0A 2019-06-27 2020-06-24 半导体装置 Pending CN112151598A (zh)

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