WO2024114392A1 - 电容模组及其制造方法 - Google Patents

电容模组及其制造方法 Download PDF

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Publication number
WO2024114392A1
WO2024114392A1 PCT/CN2023/131988 CN2023131988W WO2024114392A1 WO 2024114392 A1 WO2024114392 A1 WO 2024114392A1 CN 2023131988 W CN2023131988 W CN 2023131988W WO 2024114392 A1 WO2024114392 A1 WO 2024114392A1
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WO
WIPO (PCT)
Prior art keywords
capacitor
module
capacitors
pins
module carrier
Prior art date
Application number
PCT/CN2023/131988
Other languages
English (en)
French (fr)
Inventor
郑子卓
周少飞
黄进辉
卢旺林
陈忠建
朱翔
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2024114392A1 publication Critical patent/WO2024114392A1/zh

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering

Definitions

  • the present application relates to the technical field of semiconductor devices, and in particular to a capacitor module and a method for manufacturing the same.
  • a capacitor module and a manufacturing method thereof are proposed to solve the above technical problems and provide a capacitor that meets the capacitance requirements under the premise of limited capacitor placement area.
  • an embodiment of the present application provides a capacitor module, comprising: a module carrier and a plurality of capacitors fixed on the module carrier, the plurality of capacitors being divided into at least one capacitor group, each of the capacitor groups comprising at least one capacitor;
  • the module carrier comprises a first surface and a second surface arranged opposite to each other, the first surface is provided with a plurality of mounting areas, each of the mounting areas is provided with a power pad and a ground pad, the second surface is provided with a plurality of pins, each of the pins is electrically connected to the power pad or the ground pad through the module carrier;
  • the capacitors in each of the capacitor groups are stacked in different layers in sequence above the corresponding installation area, the positive electrode and the negative electrode of the first layer of capacitors in each of the capacitor groups close to the module carrier are respectively welded to the power pad and the ground pad in the corresponding installation area, and the capacitors in different layers in the same capacitor group are connected in parallel.
  • the capacitor module provided by the first aspect can also provide a larger capacitance value in a usage scenario with limited installation area, making it suitable for various large-capacitance product requirements, thereby improving the capacitor capacity density per unit area.
  • the plurality of mounting areas are arranged in an array on the first surface of the module carrier; and/or the type of some or all of the pads is different from the type of at least one of the adjacent pads.
  • the overall equivalent inductance of the capacitor module can be reduced and the overall filtering effect can be enhanced.
  • the plurality of pins are arranged on the second surface of the module carrier in a manner matching an arrangement of chip pins of a target chip; and/or,
  • the plurality of pins are arranged continuously on the second surface of the module carrier in a preset shape, wherein the preset shape includes a rhombus, Either rectangular or square; and/or,
  • the type of some or all of the pins is different from the type of at least one of the adjacent pins.
  • the capacitor module further includes:
  • the packaging layer is used to package the capacitor module.
  • each capacitor in the capacitor module and the first surface of the module carrier board can be isolated from the external environment, thereby protecting the entire capacitor module and improving the reliability and stability of the capacitor module.
  • the capacitor module further includes: at least one insulating plate fixed to the first surface of the module carrier, and each insulating plate is located between adjacent capacitor groups, so as to achieve electrical isolation between adjacent capacitor groups.
  • the insulating plate includes a plurality of insulating plates
  • the plurality of insulating plates are connected in sequence.
  • the capacitors of adjacent layers in each capacitor group are fixed with patch adhesive, and/or the first layer of capacitors and the module carrier are fixed with patch adhesive, so that the structural strength of the capacitor module can be improved.
  • the capacitors in the same capacitor group have the same shape and size, which can simplify the manufacturing process of the capacitor module and improve the manufacturing speed.
  • an embodiment of the present application provides a method for manufacturing a capacitor module, comprising:
  • the module carrier comprising a first surface and a second surface provided opposite to each other, the first surface being provided with a plurality of mounting areas, the second surface being provided with a plurality of pins, each of the pins being connected to the power pad or the ground pad through the module carrier;
  • the capacitors in the first layer of each capacitor group are respectively mounted in the corresponding mounting area, and the positive electrode and the negative electrode of each capacitor in the first layer are respectively fixed on the power pad and the ground pad in the corresponding mounting area by solder;
  • the capacitors of the next layer are respectively installed on the corresponding installed capacitors, and the positive electrodes and negative electrodes of the capacitors of the next layer are respectively fixed on the positive electrodes and negative electrodes of the corresponding installed capacitors by solder, and the steps of coating the positive electrodes and negative electrodes of the capacitors on the top layer of the current module carrier and the subsequent steps are repeated until the installation of the capacitors in all the capacitor groups is completed, and the capacitors on the same installation area belong to the same capacitor group;
  • Reflow soldering is performed to weld the positive electrodes and negative electrodes of each capacitor of the first layer to the corresponding power pads and ground pads, and to weld the capacitors of adjacent layers to each other, so as to obtain a capacitor module.
  • the plurality of mounting areas are arranged in an array on the first surface of the module carrier; and/or the type of some or all of the pads is different from the type of at least one of the adjacent pads.
  • the plurality of pins are arranged on the second surface of the module carrier in a manner matching an arrangement of chip pins of a target chip; and/or,
  • the plurality of pins are continuously arranged in a preset shape on the second surface of the module carrier, wherein the preset shape includes any one of a rhombus, a rectangle or a square; and/or, the type of some or all of the pins is different from the type of at least one of the adjacent pins.
  • the method further includes:
  • patch glue is applied on the capacitors of the current top layer on the module carrier, and the area where the patch glue is applied in each capacitor is different from the area where the positive electrode and the negative electrode of the capacitor are located.
  • the method further includes:
  • the capacitor module obtained by reflow soldering is packaged to form a packaging layer of the capacitor module.
  • the method further includes:
  • At least one insulating plate is fixed on the first surface of the module carrier, and each insulating plate is located between adjacent capacitor groups.
  • the insulating plate includes a plurality of insulating plates
  • the plurality of insulating plates are connected in sequence.
  • the capacitors in the same capacitor group have the same shape and size.
  • an embodiment of the present application provides a capacitor module, comprising: a plurality of module carriers, a plurality of metal connectors, and a plurality of capacitors welded and fixed on each of the module carriers;
  • each module carrier is respectively provided with a plurality of mounting areas, each of the mounting areas is provided with a power pad and a ground pad, and the bottommost module carrier among the plurality of module carriers further comprises a second surface arranged opposite to the first surface, and the second surface is provided with a plurality of pins;
  • Each of the capacitors is welded and fixed above the corresponding mounting area of the corresponding module carrier, and the positive electrode and the negative electrode are respectively welded on the power pad and the ground pad in the mounting area;
  • the plurality of metal connectors are used to fix the plurality of module carriers together, each of the metal connectors is welded and fixed on two corresponding module carriers, and each of the metal connectors is electrically connected to one or more capacitors on at least one of the two welded module carriers;
  • the targets of electrical connection of each pin include: one or more capacitors on the bottom module carrier, and/or one or more capacitors electrically connected to the metal connectors welded on the bottom module carrier.
  • the capacitor module provided by the third aspect can also provide a larger capacitance value in a usage scenario with limited installation area, making it suitable for various large capacitance product requirements, thereby improving the capacitor capacity density per unit area.
  • the capacitor module uses multiple module carriers and metal connectors to achieve structural stability of the capacitor module.
  • the plurality of mounting areas on the first surface of each module carrier are arranged in an array; and/or the type of some or all of the pads is different from the type of at least one of the adjacent pads.
  • the overall equivalent inductance of the capacitor module can be reduced and the overall filtering effect can be enhanced.
  • the plurality of pins are arranged on the second surface of the bottommost module carrier in a manner matching the arrangement of the chip pins of the target chip; and/or,
  • the plurality of pins are continuously arranged in a preset shape on the second surface of the module carrier, wherein the preset shape includes any one of a rhombus, a rectangle or a square; and/or, the type of some or all of the pins is different from the type of at least one of the adjacent pins.
  • each of the metal connectors is welded and fixed to two adjacent module carriers.
  • the capacitor module further includes:
  • the packaging layer is used to package the capacitor module.
  • each capacitor in the capacitor module and the first surface of the module carrier board can be isolated from the external environment, thereby protecting the entire capacitor module and improving the reliability and stability of the capacitor module.
  • the capacitor module further includes: at least one insulating plate, each of which is fixed to the first surface of the corresponding module carrier and is located between adjacent capacitors, so as to achieve electrical isolation between adjacent capacitor groups.
  • the capacitors have the same shape and size, which can simplify the manufacturing process of the capacitor module and increase the manufacturing speed.
  • an electronic device including:
  • each of the capacitor modules comprising the capacitor module described in the first aspect or one or more of the multiple possible implementations of the first aspect, or the capacitor module described in the third aspect or one or more of the multiple possible implementations of the third aspect;
  • the PCB is used to carry each of the chips and each of the capacitor modules.
  • Each of the chips is welded and fixed on a first surface of the PCB.
  • Each of the capacitor modules is welded and fixed on a second surface of the PCB opposite to the first surface through a plurality of pins.
  • FIG. 1 shows a chip power density variation trend curve.
  • FIG. 2 shows a chip power and current variation trend curve.
  • FIG. 3 is a schematic diagram showing the structure of a certain type of chip in the related art.
  • 4A-4C are schematic diagrams showing the structure of a capacitor in the related art.
  • FIG. 5A is a schematic three-dimensional diagram showing the structure of a capacitor module according to an embodiment of the present application.
  • 5B-5C show front views of a capacitor module according to an embodiment of the present application.
  • FIG. 5D shows a top view of a capacitor module according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram showing an installation and application of a capacitor module according to an embodiment of the present application.
  • FIGS. 7A-7E show top views of a first surface of a module carrier in a capacitor module according to an embodiment of the present application.
  • FIGS. 8A-8D illustrate top views of the second surface of a module carrier in a capacitor module according to an embodiment of the present application.
  • FIGS. 9A-9E show top views of a capacitor module according to an embodiment of the present application.
  • 10A-10B respectively show a side view and a top view of a capacitor module according to another embodiment of the present application.
  • FIG. 11 shows a side view of a capacitor module according to yet another embodiment of the present application.
  • FIG. 12 shows a side view of a capacitor module according to yet another embodiment of the present application.
  • FIG. 13 is a flow chart showing a method for manufacturing a capacitor module according to an embodiment of the present application.
  • FIG. 14 is a schematic flow chart showing a method for manufacturing a capacitor module according to an embodiment of the present application.
  • FIG. 15 is a schematic flow chart showing a method for manufacturing another capacitor module according to an embodiment of the present application.
  • FIG. 16 is a schematic flow chart showing a method for manufacturing another capacitor module according to an embodiment of the present application.
  • FIG1 shows a chip power density variation trend curve.
  • FIG2 shows a chip power and current variation trend curve.
  • FIG1 and FIG2 combined with the single chip power density variation trend shown in FIG1 and the single chip working mode change and current and power consumption change shown in FIG2, it can be seen that: with the continuous advancement of technology, the change of chip power density is rapidly increasing, and due to the limitations of single board size and power supply mode, the current single board condition (such as size) under high power density requirements cannot leave enough space for capacitor placement.
  • multilayer ceramic capacitors cannot increase indefinitely in thickness, number of electrode layers, and material properties at a fixed size due to manufacturing process limitations. Therefore, there is an upper limit to the evolution of the single-cell capacity of ceramic capacitors.
  • the size of ceramic capacitors increases accordingly. The larger the size of ceramic capacitors, the more likely they are to be affected by stress and crack during use. Therefore, it is impossible to completely rely on the increase in the capacity of single-cell ceramic capacitors to meet the current power supply capacity requirements.
  • Figure 3 shows a schematic diagram of the structure of a certain type of chip in the related technology. Based on the above two reasons, taking the power supply requirements of a certain type of chip shown in Figure 3 as an example, as shown in Figure 3, the chip uses a vertical through-current architecture, which needs to meet the large through-current requirements of more than 2KW/3KA.
  • the total vertical power supply low-frequency filter capacitance requirement is about 40000uF.
  • the current general flat capacitor design method shown in Figure 3 can only place 15000uF, and there is still a 2-fold capacitance gap, which cannot meet the chip filtering requirements.
  • the capacity density per unit area needs to be increased to meet the power supply requirements.
  • Figures 4A-4C show the schematic diagrams of the structure of capacitors in the related art. The following is a description of the problems existing in different capacitor expansion methods in the related art in conjunction with the examples of capacitor expansion methods given in Figures 4A-4C.
  • a pinless stacked ceramic capacitor is provided, which is formed by stacking two ceramic capacitor cores 1.
  • the ceramic capacitor core 1 is roughly a rectangular parallelepiped, and its opposite ends are respectively provided with end electrodes 11.
  • the ceramic capacitor core 1 is a multilayer ceramic capacitor core. Specifically, a first inner electrode 12 and a second inner electrode 13 are arranged inside the ceramic capacitor core 1.
  • the first inner electrode 12 is conductively connected to one end electrode 11, and the second inner electrode 13 is conductively connected to the other end electrode 11.
  • the first inner electrode 12 and the second inner electrode 13 are arranged in parallel and spaced apart, and a ceramic dielectric material is arranged between the first inner electrode 12 and the second inner electrode 13.
  • the end electrodes 11 are, from the inside to the outside, a base metal layer 111, a barrier layer 112 and an outermost coating 113.
  • An adhesive 3 for fixing is arranged between the two ceramic capacitor cores 1, and the electrodes 11 on the same side of the two ceramic capacitor cores 1 are welded to each other by solder 2 to form a welded joint, and the solder 2 covers the electrodes 11 on the same side of the two ceramic capacitor cores 1 to form a welded joint.
  • the adhesive 3 is used to make the multiple ceramic capacitor cores neatly stacked and fixed together, and the adhesive 3 is fixed.
  • Solder 2 is set at the position corresponding to the end electrode in the mold, the stacked ceramic capacitor core 1 is placed in the mold, and then the mold is placed in a vacuum eutectic furnace for heating and welding, so that the solder 2 melts and diffuses to the end electrode surfaces on the same side of the multiple ceramic capacitor cores 1 to form a welding joint.
  • the solution of the related technology 1 has the following problems: the assembly process is relatively complicated: it is necessary to first glue and then weld the mold, the assembly process is long, and the automation is poor; the PCB design requires the addition of special processes: when the stacked capacitor is used on the PCB, if it is used on the B side (also the Bottom side) of the chip, it is necessary to add special PCB processes to achieve the PCB T side (also the Top side) and B side network staggered layers to meet the stacked capacitor welding requirements.
  • a stacked MLCC capacitor including a multilayer ceramic capacitor, each multilayer ceramic capacitor including a plurality of first electrodes 9 and a plurality of second electrodes 10 stacked alternately, and a dielectric 11 between each first electrode 9 and each adjacent second electrode 10.
  • the first electrode 9 terminates at the first side
  • the second electrode 10 terminates at the second side.
  • the first instantaneous liquid phase sintered conductive layer is located on the first side and is in electrical contact with each first electrode; the second instantaneous liquid phase sintered conductive layer is located on the second side and is in electrical contact with each second electrode.
  • the ceramic capacitors are stacked alternately, and the electrodes are fixed with instantaneous liquid phase sintering materials.
  • the instantaneous liquid phase sintering material is mainly at 330°C for more than 90s, and the secondary remelting temperature needs to be above 600°C after the material is solidified.
  • the solution of the related technology 2 has the following problems: the transient liquid phase sintering (TLPS) paste as a bonding material needs to rely on high temperature heating and sintering to easily form intermetallic compounds. Although it has the advantage of improving mechanical strength, the high temperature heating and phase change process will increase the process variation factors.
  • TLPS transient liquid phase sintering
  • the microstructure of the sintered joint is observed, it is easy to form hard and brittle intermetallic compounds, or even micro cracks or micro gaps after phase change on the surface of the stacking position or bonding point. Even if its supporting strength is sufficient, it still cannot effectively provide toughness to resist repeated plate bending or vibration. Instead, it will promote stress concentration to form structural damage or crack sources, thus limiting the application of the product.
  • the transient liquid phase sintering (TLPS) paste cannot be filled with nickel or tin plating after sintering, and it is difficult to react with the electroplating solution to form a uniform and delicate electroplated surface. Therefore, the problem of micro cracks or micro gaps cannot be improved, which is the direction that people engaged in this industry are eager to study and improve.
  • a metal bracket capacitor including two ceramic capacitors 11 and two electrode sheets, the upper and lower ends of the ceramic capacitor 11 have end electrodes 11, the two ceramic capacitors 11 are horizontally stacked and connected in parallel, and the electrode sheet includes a horizontal plate 21 partially welded to the upper end surface or the lower end surface of the end electrode 11 of the ceramic capacitor 11, a pin 22 vertically arranged at the end of the horizontal plate 21 and spaced apart from the side of the end electrode 11, a supporting foot 23 vertically arranged on the horizontal plate 21 and close to the side of the end electrode 11, and three through holes 24 spaced apart on the pin 22, and the horizontal plate 21 is welded to the end electrode 11 by high-lead solder.
  • the related technology 3 has the following problems: the assembly process is cumbersome, and high-precision metal frame welding ends need to be customized according to the stacking size; the PCB design needs to add special processes when using this solution: when the stacked capacitor is used on the PCB, such as when it is used on the B side of the chip, it is necessary to add special PCB processes to achieve PCB T/B side network staggered layers to meet the stacked capacitor welding requirements; there are CTE differences between the metal frame and ceramic capacitors and PCB, and it is potentially easily affected by the metal frame, resulting in micro cracks in the solder joints, affecting the function; the equivalent inductance of the stacked capacitor is increased, resulting in reduced filtering effect.
  • the present application provides a capacitor module and a manufacturing method thereof.
  • the capacitor module can also provide a larger capacitance value in a usage scenario with limited installation area, making it suitable for various large capacitance product requirements, thereby improving the capacitor capacity density per unit area.
  • the present application provides a capacitor module as shown in FIG. 5A to FIG. 5D .
  • the capacitor module includes: A module carrier 1 and a plurality of capacitors 2 fixed on the module carrier 1.
  • the plurality of capacitors 2 are divided into at least one capacitor group, each of which includes at least one capacitor 2.
  • the capacitor module includes four capacitor groups, each of which includes three capacitors 2 stacked together.
  • the number of capacitors included in different capacitor groups can be the same or different. Including the same number of capacitors in different capacitor groups can simplify the manufacturing process of the capacitor module.
  • the module carrier 1 includes a first surface (i.e., the top surface, such as the T surface shown in FIGS. 7A-7B) and a second surface (i.e., the bottom surface, such as the B surface shown in FIGS. 8A-8D) that are arranged opposite to each other, and the first surface T is provided with a plurality of mounting areas S, and each of the mounting areas S is provided with a power pad 01 and a ground pad 02.
  • the second surface B is provided with a plurality of pins 11, and each of the pins 11 is electrically connected to the power pad 01 or the ground pad 02 through the module carrier 1.
  • a first surface i.e., the top surface, such as the T surface shown in FIGS. 7A-7B
  • a second surface i.e., the bottom surface, such as the B surface shown in FIGS. 8A-8D
  • the second surface B is provided with a plurality of pins 11, and each of the pins 11 is electrically connected to the power pad 01 or the ground pad 02 through
  • the pins 11 may include a power pin 111 and a ground pin 112.
  • the power pin 111 may be electrically connected to the power pad 01 in one or more mounting areas S on the first surface T of the module carrier through interlayer wiring and conductive holes in the module carrier 1 (the conductive holes may be through holes, blind holes, buried holes, etc. on the module carrier through metallization or metal filling on the inner wall).
  • the ground pin 112 can be electrically connected to the ground pad 02 in one or more mounting areas S on the first surface T of the module carrier through the interlayer wiring and the conductive hole in the module carrier 1.
  • the module carrier can be a PCB. In some embodiments, as shown in FIG.
  • each pin 11 can be a bump such as a solder ball protruding relative to the second surface of the module carrier 1; as shown in FIG. 5C , each pin 11 can be a pad disposed on the second surface of the module carrier 1.
  • a bump such as a solder ball protruding relative to the second surface of the module carrier 1
  • each pin 11 can be a pad disposed on the second surface of the module carrier 1.
  • the multiple mounting areas may be arranged in an array on the first side of the module carrier. So that the capacitors can be arranged in the same array on the module carrier. For example, it can be arranged in an array of 4 groups of capacitors of 2 ⁇ 2 as shown in FIG. 5D, or it can be arranged in an array of 2 capacitor groups of 1 ⁇ 2, 3 capacitor groups of 1 ⁇ 3, 4 capacitor groups of 1 ⁇ 4, 6 capacitor groups of 2 ⁇ 3, and 9 capacitor groups of 3 ⁇ 3 as shown in FIG. 9A-FIG. 9E.
  • the positions of power pads and ground pads in multiple installation areas, as well as the relative positions between different ground pads, between different power pads, and between ground pads and power pads in different installation areas can be set according to actual needs to meet the filtering requirements of the capacitor module.
  • the type of some or all pads is different from the type of at least one of the adjacent pads. In this way, the arrangement of pads of different types in an alternating manner can reduce the equivalent inductance of the capacitor module as a whole and enhance the overall filtering effect.
  • the plurality of power pads and the plurality of ground pads on the first surface of the module carrier 1 are arranged in a first alternating manner.
  • the first alternating manner may include at least one of the following: the types of pads in the same row are the same, and the types of pads in different rows in adjacent rows are different; in the same row, the types of some or all pads are different from the types of at least one of the adjacent pads; in the same column, the types of some or all pads are different from the types of the adjacent pads.
  • FIG. 7A to FIG. 7E use the first side of the module carrier board having four capacitor areas to schematically illustrate the alternating arrangement of ground pads and power pads.
  • the ground pads 02 in the four mounting areas S can be set in the middle position, so that the ground pads 02 of the four capacitor areas S are relatively set in the central area of the entire module carrier board, and the four power pads 01 are relatively set around the entire module carrier board to increase the distance between the power pads 01, that is, the pads are arranged according to the first alternating method of "in the same row, the type of some pads is different from the type of adjacent pads" in FIG7A .
  • the first alternating method of "in the same row, the type of some pads is different from the type of adjacent pads” is also followed.
  • the pads are arranged in a manner that "the types of the pads are different”.
  • a 2 ⁇ 2 capacitor area S is provided, and the pads are arranged in accordance with the first alternating manner that "in the same row, the types of all pads are different from the types of the adjacent pads" and "in the same column, the types of all pads are different from the types of the adjacent pads”.
  • FIG7D and FIG7E for the first surface T, a 2 ⁇ 2 capacitor area S is provided, and the pads are arranged in accordance with the first alternating manner that "in the same row, the types of all pads are different from the types of the adjacent pads".
  • the greater the degree of alternation of the pads the better the effect of reducing the equivalent inductance of the capacitor module as a whole and enhancing the overall filtering effect.
  • FIG7C has the largest degree of alternation, and its effect of reducing the equivalent inductance of the capacitor module as a whole and enhancing the overall filtering effect is relatively good. It can be understood that those skilled in the art can arrange the pads in the first alternating manner according to actual needs, and the present application does not limit this.
  • the plurality of pins 11 are arranged on the second side B of the module carrier in a manner matching the arrangement of the chip pins of the target chip, so that after the chip pins of the target chip and the plurality of pins of the capacitor module are respectively welded to the two opposite sides of the mainboard, the chip pins of the target chip and the pins of the corresponding capacitor module can be directly connected by means of the conductive through-holes between the target chip and the capacitor module on the mainboard, without the need for the interlayer wiring in the mainboard, simplifying the electrical connection between the target chip and the capacitor module.
  • the plurality of pins can also be arranged continuously on the first side of the module carrier in a preset shape, and the preset shape may include a rhombus (as shown in FIG. 8A and FIG. 8B), a rectangle or a square (as shown in FIG. 8C and FIG. 8D), etc., and the present application does not limit this.
  • the type of some or all of the pins is different from the type of at least one pin in the adjacent pins, so as to realize the alternating arrangement between the ground pin and the power pin.
  • the plurality of power pins connected to the power pad and the plurality of ground pins connected to the ground pad among the plurality of pins may be arranged in a second alternating manner.
  • the second alternating manner may include at least one of the following: the types of the pins in the same row are the same, and the types of the pins in different rows in adjacent rows are different; in the same row, the type of some or all of the pins is different from the type of at least one of the adjacent pins; in the same column, the type of some or all of the pins is different from the type of at least one of the adjacent pins.
  • the power pin 111 and the ground pin 112 can be in different rows as shown in FIG. 8A and FIG. 8C, and the row where the power pin 111 is located can be arranged alternately with the row where the ground pin 112 is located, that is, the pins in the examples shown in FIG. 8A and FIG. 8C are arranged according to the second alternating manner of "the types of the pins in the same row are the same, and the types of the pins in different rows in adjacent rows are different".
  • the power pin 111 and the ground pin 112 can also be arranged alternately in the same row as shown in FIG. 8B and FIG. 8D, that is, the pins in the example shown in FIG.
  • the capacitors 2 in each capacitor group are stacked in different layers in sequence above the corresponding installation area S (see Figures 7A-7B), and the positive electrode 21 and the negative electrode 22 of the first layer of capacitors close to the module carrier 1 in each capacitor group are respectively welded to the power pad 01 and the ground pad 02 in the corresponding installation area S, and the capacitors 2 in different layers in the same capacitor group are connected in parallel.
  • the capacitors 2 in different capacitor groups can be connected in parallel to one or more groups by means of the module carrier 1.
  • the pins 11 (including a power pin 111 and a ground pin 112) are connected so that the entire capacitor module can provide different capacitance values to meet the different capacitance value requirements of the chip.
  • the capacitor module can provide capacitance value selections of C1, 2 ⁇ C1 and 4 ⁇ C1.
  • each capacitor 2 can be set as a rectangular parallelepiped structure as shown in FIG. 5A, or can be set as other shapes with two relatively parallel surfaces (such as a cube, a cylinder, etc. having at least one pair of mutually parallel surfaces), so that each capacitor of the same capacitor group can be stacked using two relatively parallel surfaces.
  • a positive electrode 21 and a negative electrode 22 can be respectively set on two relatively parallel surfaces of the capacitor 2, and the positive electrode 21 and the negative electrode 22 are set as "surface electrodes" on the surface of the capacitor, and the positive electrodes on different surfaces are electrically connected. So that each capacitor 2 is used to connect to the module carrier 1 or to other capacitors 2. Both surfaces are provided with a positive electrode 21 and a negative electrode 22.
  • solder can be directly applied on the power pad 01 and the ground pad 02 of the module carrier to directly weld the positive electrode and the negative electrode on the surface of the capacitor to the power pad 01 and the ground pad 02.
  • solder can also be directly applied on the surface of the capacitor to achieve welding between capacitors. In this way, it is convenient to realize the electrical connection between the capacitor 2 and the module carrier 1, and between the capacitors of adjacent layers stacked on each other.
  • the number of capacitors in different layers of the same capacitor group can be the same or different, and the number of capacitors in each layer can be one or more.
  • the shapes and sizes of different capacitors in the same capacitor group can be set as needed under the premise of ensuring the electrical connection requirements between adjacent layer capacitors.
  • the shapes and/or sizes of different capacitors can be the same or different, and this application does not limit this.
  • the capacitor module can achieve electrical connection between the capacitor and the module carrier, and between the capacitors of adjacent layers by welding, and at the same time achieve fixed connection between the capacitor and the module carrier, and between the capacitors of adjacent layers, so as to achieve structural fixation of the entire capacitor module.
  • the solder can be conductive glue, solder paste, epoxy resin solder paste, and the material of the solder can be set according to the manufacturing process of the capacitor module, and this application does not limit this.
  • each first layer capacitor 2 can be pasted and fixed in the corresponding installation area by using patch glue 4, and/or, the patch glue 4 can also be used to paste and fix the capacitors 2 of adjacent layers in the same capacitor group.
  • the welding between the capacitor and the module carrier and the capacitors of adjacent layers is performed in the form of reflow soldering.
  • the tolerance temperature of the patch glue needs to be greater than the reflow temperature of the reflow soldering to ensure that the patch glue will not denature at the reflow temperature during the reflow soldering process, resulting in poor pasting performance or even complete melting and loss of function, and it is also necessary to ensure that the patch glue still has a shape in a normal working state after reflow soldering to continue to realize its pasting function.
  • the patch glue can be coated on the surface of each capacitor in an area different from the area where the positive electrode and the negative electrode are located, for example, as shown in FIG. 5B and FIG. 5C, the patch glue 4 is coated on the middle area 23 of the capacitor 2 and the area between the power pad and the ground pad in the installation area.
  • the capacitors 2 of the same capacitor group may have the same shape and size, so that the manufacturing process of the capacitor module can be simplified.
  • each capacitor in the capacitor module may have the same capacitance. In this way, when the shape, size, and capacitance are the same, the capacitor module may be directly stacked according to the number of capacitor groups and the number of capacitors in each capacitor group during the manufacturing process of the capacitor module, thereby further simplifying the manufacturing process of the capacitor module and improving the manufacturing speed.
  • the capacitor module shown in Figure 5A and other embodiments provided by the present application is still applied to the application scenario of a certain type of chip shown in Figure 3. Under the same installation area and power supply mode, the capacitor module shown in Figure 5A and other embodiments of the present application can provide a larger capacitance as shown in Figure 6.
  • the capacitor module may further include at least one insulating plate.
  • Each of the insulating plates may be fixed to the first surface of the module carrier, and each of the insulating plates may be located between adjacent capacitor groups.
  • the plurality of insulating plates may be an integral structure connected in sequence.
  • the capacitor module may include an insulating plate, the insulating plate including a plurality of sub-plates located between different capacitor groups, such as the insulating plate 6 in the capacitor module shown in FIGS. 10A and 10B, which includes four sub-plates, each of which is located between different capacitor groups.
  • the insulating plate may be an insulating material such as plastic to achieve electrical isolation between adjacent capacitor groups.
  • the capacitor module may further include an encapsulation layer 8 for encapsulating the entire capacitor module to isolate the capacitors in the capacitor module and the first surface of the module carrier from the external environment, protect the entire capacitor module, and provide reliability and stability of the capacitor module.
  • the encapsulation layer may be implemented in the form of plastic packaging, lamination, etc.
  • the encapsulation layer 8 may form a space with the module carrier 1 that can seal the module carrier 1 to the components on the first surface.
  • the present application also provides a method for manufacturing a capacitor module, as shown in Figures 13 and 14, the method includes steps S101 to S106.
  • Figure 14 is a schematic diagram of a manufacturing process of the capacitor module shown in Figure 11.
  • step S101 solder 3 is applied to the power pads 01 and ground pads 02 provided in each mounting area S of the module carrier 1.
  • step S101 may further include: applying patch adhesive 4 partially or completely to the area between the power pads 01 and the ground pads 02 in each mounting area S.
  • each capacitor 2 in the first layer of each capacitor group is installed in the corresponding installation area S.
  • the positive electrode and the negative electrode of each capacitor in the first layer are fixed on the power pad and the ground pad in the corresponding installation area by solder 3 (or solder 3 and patch adhesive 4).
  • step S103 solder 3 is applied to the positive electrode and the negative electrode of each of the capacitors 2 in the current top layer on the module carrier 1.
  • step S103 may also include: applying patch glue 4 to the middle area of each of the capacitors 2 in the current top layer on the module carrier 1.
  • solder or solder and patch glue
  • solder may be applied only to the capacitors of each of the capacitors 2 in the current top layer that need to be stacked later.
  • step S104 each capacitor 2 of the next layer is installed above the corresponding installed capacitor 2, and the positive electrode and negative electrode of each capacitor 2 of the next layer are fixed to the positive electrode and negative electrode of the corresponding installed capacitor by solder.
  • step S105 it is detected whether the assembly of the capacitor module has been completed. If the assembly has been completed, step S105 is executed, and if the assembly has not been completed, step S103 is continued. Among them, whether the assembly is completed can be determined based on whether the components on all module carriers have been installed, and these components may include capacitors, insulating plates, etc.
  • step S106 reflow soldering is performed to solder the positive electrodes and negative electrodes of each capacitor of the first layer to the corresponding power pads and ground pads, and to solder the capacitors of adjacent layers to obtain a capacitor module.
  • the method further includes: after step S106 , packaging the capacitor module obtained in step S106 to form a packaging layer 8 .
  • each insulating plate can be fixed to the module carrier at any step before encapsulation; or if the capacitor module does not include an encapsulation layer 8, each insulating plate can be fixed to the module carrier at any step before the entire capacitor module is manufactured.
  • the insulating plate can be clamped with a groove set on the module carrier, and can also be fixed to the module carrier by pasting with patch glue, etc. The method of fixing the insulating plate to the module carrier can be set according to actual needs, and this application does not limit this.
  • the capacitor module includes a plurality of module carriers 1, a plurality of metal connectors 5 and a plurality of capacitors 2 welded and fixed on each of the module carriers 1.
  • the first surface of each of the module carriers 1 is respectively provided with a plurality of mounting areas, each of the mounting areas is provided with a power pad and a ground pad, and the bottommost module carrier among the plurality of module carriers 1 also includes a second surface arranged opposite to the first surface and the second surface is provided with a plurality of pins 11.
  • Each of the capacitors 2 is welded and fixed above the corresponding mounting area of the corresponding module carrier 1, and the positive electrode and the negative electrode are respectively welded on the power pad and the ground pad in the mounting area.
  • the plurality of metal connectors 5 are used to fix the plurality of module carriers 1 together, each of the metal connectors 5 is welded and fixed on the corresponding two module carriers 1, and each of the metal connectors 5 is electrically connected to one or more capacitors 2 on at least one of the two welded module carriers 1.
  • the targets electrically connected to each of the pins 11 include: one or more of the capacitors 2 on the bottom module carrier 1, and/or one or more of the capacitors 2 electrically connected to the metal connector 5 welded on the bottom module carrier 1.
  • the difference between the capacitor module shown in FIG. 12 and the capacitor module shown in FIG. 5A-FIG. 5D and described above is that the assembly and assembly methods of the capacitor module are different, and the others are similar.
  • the difference between the capacitor module shown in FIG. 12 and the capacitor module shown in FIG. 5A-FIG. 5D and described above is that the number of module carriers in the capacitor module is different; and the capacitor module shown in FIG. 5A-FIG. 5D uses solder (or solder and patch glue) to ensure the structural stability of the capacitor module, and the capacitor module shown in FIG. 12 uses multiple module carriers and metal connectors to achieve the structural stability of the capacitor module.
  • the metal connector 5 can be a metal column, sheet, strip or other connector that is conductive and has structural support strength requirements such as copper.
  • the two module carriers welded by each metal connector 5 can be two adjacent module carriers, so that the fixed connection between the two adjacent module carriers can be achieved through one or more metal connectors between the two adjacent module carriers.
  • the two module carriers welded by each metal connector can be one of the bottom module carrier and one of the other module carriers, so that each module carrier can be fixedly connected to the bottom module carrier through one or more metal connectors.
  • Conductive holes may be provided on the module carrier to which the two ends of the metal connector are respectively welded (if the module carrier is the bottom module carrier, the conductive hole may be electrically connected to at least one capacitor on the bottom module carrier, or may not be connected to any capacitor. If the module carrier is any module carrier other than the bottom module carrier, the conductive hole may be electrically connected to at least one capacitor on the module carrier), so that the end of the metal connector can be placed in the conductive hole or pass through the conductive hole, and the end of the metal connector is welded to the conductive hole with the help of solder, so as to realize the fixed connection and electrical connection between the metal connector and the module carrier.
  • a through hole can be provided on the middle module carrier at a position corresponding to the metal connector, so that the metal connector can pass through the through hole.
  • the metal connector can also be welded to the middle module carrier to strengthen the overall structural strength of the capacitor module; and/or the through hole on the middle module carrier where the metal connector is welded can be a conductive hole, which can be electrically connected to at least one capacitor on the module carrier.
  • the welding states at both ends of the metal connectors can include any of the following: welding between adjacent module carriers, welding between the bottom module carrier and other module carriers not adjacent to the bottom module carrier, and welding between non-adjacent non-bottom module carriers. Therefore, the welding states of different metal connectors can be set according to actual needs, and this application does not limit this.
  • the capacitor module shown in Figure 12 may also include an insulating plate and/or a packaging layer.
  • the configuration of the insulating plate and the packaging layer is similar to the implementation of the above capacitor module, and the relevant descriptions can be referred to above. It is redundant and will not be repeated here.
  • the capacitor module manufacturing method can include the following two steps: a single board welding step and a multi-board assembly step.
  • Solder is applied to the power pad and ground pad in each installation area of each module carrier, and solder is also applied to the through-hole where the installation position of the metal connector needs to be welded is located. Then the capacitors to be installed on the model carrier are placed in the corresponding installation areas, and the positive electrode and negative electrode of each capacitor are respectively located at the power pad and ground pad of the entire installation area; and the metal connector to be welded is installed at the corresponding through-hole. The capacitors and metal connectors on each module carrier are welded to the first surface of the module carrier by reflow soldering.
  • the capacitor module After completing the welding of the capacitors and metal connectors on each module carrier, the capacitor module is assembled according to the stacking order of the capacitors on the module carrier, and each metal connector in the assembled capacitor module is welded to the second side of the upper module carrier.
  • the following steps can also be performed in sequence according to the stacking order of the module carriers, as shown in FIG. 16 : welding of capacitors and metal connectors on the bottom first-layer module carrier; welding of the second-layer module carrier and the metal connectors welded on the first-layer module carrier; welding of capacitors and metal connectors on the second-layer module carrier, and so on, until the welding of the last layer of module carrier and the metal connectors welded on the next layer of the last layer of module carrier and the welding of capacitors on the last layer of module carrier are performed, and it is determined that the manufacturing of the capacitor module is completed.
  • the capacitor module can be prepared by referring to the method shown in FIG. 16, which is redundant and will not be described here.
  • the capacitor module can be prepared by combining the methods shown in FIG. 15 and FIG. 16. It is understandable that the manufacturing process can be set according to the structure of the capacitor module shown in FIG. 12, and this application does not limit this.
  • the present application also provides an electronic device, including:
  • each capacitor module is any one of the capacitor modules described above;
  • the PCB is used to carry each of the chips and each of the capacitor modules.
  • Each of the chips is welded and fixed on a first surface of the PCB.
  • Each of the capacitor modules is welded and fixed on a second surface of the PCB opposite to the first surface through a plurality of pins.
  • each square frame in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the logical function of the specification.
  • the functions marked in the square frame can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square frames can actually be executed substantially in parallel, and they can also be executed in the opposite order sometimes, depending on the functions involved.
  • each box in the block diagram and/or flowchart, and the combination of boxes in the block diagram and/or flowchart can be implemented by hardware (such as circuits or ASICs (Application Specific Integrated Circuit)) that performs the corresponding function or action, or can be implemented by a combination of hardware and software, such as firmware.

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Abstract

一种电容模组及其制造方法，电容模组包括：模组载板(1)和固定在模组载板(1)上的多个电容器(2)，多个电容器(2)分为至少一个电容组，各电容组包括至少一个电容器(2)；模组载板(1)的第一面(T)有多个安装区域(S)，各安装区域(S)设置有电源焊盘(01)和接地焊盘(02)，模组载板(1)的第二面(B)有多个引脚(11)，各引脚(11)通过模组载板(1)电连接到电源焊盘(01)或接地焊盘(02)；各电容组中的各电容器(2)分不同层依次堆叠在对应的安装区域(S)上方，各电容组中靠近模组载板(1)的第一层电容器(2)的正电极(21)和负电极(22)分别焊接在对应的安装区域(S)中的电源焊盘(01)和接地焊盘(02)上，同一电容组中不同层的电容器(2)之间并联。电容模组在安装面积有限时可提供较大电容值，适用于各类不同大容值产品需求，提升了单位面积的电容器容量密度。

Description

电容模组及其制造方法
本申请要求于2022年12月01日提交中国专利局、申请号为202211543903.5，发明名称为“电容模组及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体器件技术领域，尤其涉及一种电容模组及其制造方法。
背景技术
随着人工智能AI计算行业技术的发展，尤其是无人驾驶，人工智能等方面的迅速发展，对芯片的算力要求越来越高。而随着算力的提升伴随着是芯片的电流、功率的迅速增长，单芯片功率要求演进后续将从450W上升至2000W。功率提升带来相应的通流需求随之增加，在未来3KA大通流、3KA/μs大动态场景下，供电链路对电容器容值的需求随之不断增大。而基于供电模式演进、单板尺寸限制，当前单板尺寸下往往没有足够面积放置增加的电容器，如何在有限的电容器放置面积的前提下，提供满足容值需求的电容器是亟待解决的技术问题。
发明内容
有鉴于此，提出了一种电容模组及其制造方法，以解决上述技术问题，在有限的电容器放置面积的前提下，提供满足容值需求的电容器。
第一方面，本申请的实施例提供了一种电容模组，包括：模组载板和固定在所述模组载板上的多个电容器，所述多个电容器分为至少一个电容组，各所述电容组包括至少一个电容器；
所述模组载板包括相对设置的第一面和第二面，所述第一面设置有多个安装区域，各所述安装区域设置有电源焊盘和接地焊盘，所述第二面设置有多个引脚，各所述引脚通过所述模组载板电连接到所述电源焊盘或所述接地焊盘；
各所述电容组中的各所述电容器分不同层依次堆叠在对应的安装区域上方，各所述电容组中靠近所述模组载板的第一层电容器的正电极和负电极分别焊接在对应的安装区域中的电源焊盘和接地焊盘上，同一电容组中不同层的所述电容器之间并联。
通过第一方面提供的电容模组在安装面积有限的使用场景下，也可以提供较大电容值使其适用于各类不同大容值产品需求，提升了单位面积的电容器容量密度。
在一种可能的实现方式中，所述多个安装区域在所述模组载板的第一面呈阵列排布；并且/或者，部分或全部焊盘的类型与相邻的各焊盘中的至少一个的类型不同。
这样，按照不同类型的焊盘交替方式进行排布，可以降低电容模组整体的等效电感，增强整体的滤波效果。
在一种可能的实现方式中，所述多个引脚在所述模组载板的第二面按照与目标芯片的芯片引脚的排布方式匹配的方式排布；并且/或者，
所述多个引脚在所述模组载板的第二面按照预设形状连续排布，所述预设形状包括菱形、 长方形或正方形中的任意一种；并且/或者，
部分或全部引脚的类型与相邻引脚中的至少一个引脚的类型不同。
这样，通过不同类型的引脚交替方式排布设置，电源引脚和接地引脚磁效应相互抵消，可降低电容模组的寄生电感，从而降低电容模组整体的等效电感，达到增强电容模组滤波效果的目的。
在一种可能的实现方式中，所述电容模组还包括：
封装层，用于封装所述电容模组。
这样，可以将电容模组中的各电容器以及模组载板的第一面与外部环境隔离，保护整个电容模组，提供搞电容模组的可靠性和稳定性。
在一种可能的实现方式中，所述电容模组还包括：至少一个绝缘板，固定在所述模组载板的第一面，各所述绝缘板处于相邻的电容组之间。可以实现相邻电容组之间的电隔离。
在一种可能的实现方式中，在所述绝缘板包括多个的情况下，所述多个绝缘板依次连接。
在一种可能的实现方式中，各所述电容组中的相邻层的电容器之间利用贴片胶固定，和/或第一层电容器与所述模组载板之间利用贴片胶固定。这样，可以提高电容模组的结构强度。
在一种可能的实现方式中，同一电容组的各所述电容器具有相同的形状和尺寸。这样，可以简化电容模组的制造过程，提高制造速度。
第二方面，本申请的实施例提供了一种电容模组的制造方法，包括：
在模组载板的各安装区域设置的电源焊盘和接地焊盘上涂覆焊料，所述模组载板包括相对设置的第一面和第二面，所述第一面设置有多个安装区域，所述第二面设置有多个引脚，各所述引脚通过所述模组载板连接到所述电源焊盘或所述接地焊盘；
将各电容组中处于第一层的各电容器分别安装于对应的安装区域，处于第一层的各电容器的正电极和负电极分别通过焊料固定在对应的安装区域中的电源焊盘和接地焊盘上；
在所述模组载板上当前最上方一层的各所述电容器的正电极和负电极上涂覆焊料；
将下一层的各电容器分别安装于对应的已安装完的电容器上方，下一层的各电容器的正电极和负电极分别通过焊料固定在对应的已安装完的电容器的正电极和负电极上，重复执行在当前模组载板上最上方一层的各所述电容器的正电极和负电极上涂覆焊料及之后的步骤，直至完成所有电容组中各电容器的安装，处于同一安装区域上方的各电容器属于同一电容组；
进行回流焊，以将第一层的各电容器的正电极和负电极分别与对应的电源焊盘和接地焊盘之间焊机以及将相邻层电容器之间焊接，得到电容模组。
在一种可能的实现方式中，所述多个安装区域在所述模组载板的第一面呈阵列排布；并且/或者，部分或全部焊盘的类型与相邻的各焊盘中的至少一个的类型不同。
在一种可能的实现方式中，所述多个引脚在所述模组载板的第二面按照与目标芯片的芯片引脚的排布方式匹配的方式排布；并且/或者，
所述多个引脚在所述模组载板的第二面按照预设形状连续排布，所述预设形状包括菱形、长方形或正方形中的任意一种；并且/或者，部分或全部引脚的类型与相邻引脚中的至少一个引脚的类型不同。
在一种可能的实现方式中，所述方法还包括：
在安装第一层的各所述电容器之前，在所述模组载板的各安装区域中胶黏区域涂覆贴片胶，所述安装区域中涂覆贴片胶的区域与所述电源焊盘和所述接地焊盘所在区域不同；和/或
在安装下一层的各所述电容器之前，在所述模组载板上当前最上方一层的各所述电容器上涂覆贴片胶，各所述电容器中涂覆贴片胶的区域与所述电容器的正电极和负电极所在区域不同。
在一种可能的实现方式中，所述方法还包括：
对回流焊得到的电容模组进行封装，形成所述电容模组的封装层。
在一种可能的实现方式中，所述方法还包括：
将至少一个绝缘板固定在所述模组载板的第一面，各所述绝缘板处于相邻的电容组之间。
在一种可能的实现方式中，在所述绝缘板包括多个的情况下，所述多个绝缘板依次连接。
在一种可能的实现方式中，同一电容组的各所述电容器具有相同的形状和尺寸。
第二方面以及第二方面的各种可能的实现方式中所提供的电容模组的制造方法的有益效果，与上述第一方面以及第一方面的各种可能的实现方式中所提供的电容模组对应相同，未免冗余，此处不予赘述。
第三方面，本申请的实施例提供了一种电容模组，包括：多个模组载板、多个金属连接件和焊接固定在各所述模组载板上的多个电容器；
各所述模组载板的第一面分别设置有多个安装区域，各所述安装区域设置有电源焊盘和接地焊盘，所述多个模组载板中的最下层模组载板还包括与所述第一面相对设置的第二面且所述第二面设置有多个引脚；
各所述电容器，焊接固定在对应模组载板的对应的安装区域上方、且正电极和负电极分别焊接在所在安装区域中的电源焊盘和接地焊盘上；
所述多个金属连接件用于将所述多个模组载板固定连接在一起，各所述金属连接件焊接固定在对应的两个所述模组载板上，且各所述金属连接件电连接到所焊接的两个所述模组载板中至少一个模组载板上的一个或多个电容器；
其中，各所述引脚电连接的目标包括：所述最下层模组载板上的一个或多个所述电容器、和/或焊接在所述最下层模组载板上的金属连接件电连接的所述电容器中一个或多个。
通过第三方面提供的电容模组在安装面积有限的使用场景下，也可以提供较大电容值使其适用于各类不同大容值产品需求，提升了单位面积的电容器容量密度。且电容模组中利用多个模组载板和金属连接件实现了电容模组的结构稳定。
在一种可能的实现方式中，各所述模组载板上第一面的所述多个安装区域在呈阵列排布；并且/或者，部分或全部焊盘的类型与相邻的各焊盘中的至少一个的类型不同。
这样，按照不同类型的焊盘交替方式进行排布，可以降低电容模组整体的等效电感，增强整体的滤波效果。
在一种可能的实现方式中，所述多个引脚在所述最下层模组载板的第二面按照与目标芯片的芯片引脚的排布方式匹配的方式排布；并且/或者，
所述多个引脚在所述模组载板的第二面按照预设形状连续排布，所述预设形状包括菱形、长方形或正方形中的任意一种；并且/或者，部分或全部引脚的类型与相邻引脚中的至少一个引脚的类型不同。
这样，通过不同类型的引脚交替方式排布设置，电源引脚和接地引脚磁效应相互抵消，可降低电容模组的寄生电感，从而降低电容模组整体的等效电感，达到增强电容模组滤波效 果的目的。
在一种可能的实现方式中，各所述金属连接件焊接固定在相邻的两个所述模组载板上。
在一种可能的实现方式中，所述电容模组还包括：
封装层，用于封装所述电容模组。
这样，可以将电容模组中的各电容器以及模组载板的第一面与外部环境隔离，保护整个电容模组，提供搞电容模组的可靠性和稳定性。
在一种可能的实现方式中，所述电容模组还包括：至少一个绝缘板，各所述绝缘板固定对应的所述模组载板的第一面、且处于相邻的电容器之间。可以实现相邻电容组之间的电隔离。
在一种可能的实现方式中，各所述电容器具有相同的形状和尺寸。这样，可以简化电容模组的制造过程，提高制造速度。
第四方面，本申请的实施例提供了一种电子设备，包括：
至少一个芯片；
至少一个电容模组，各所述电容模块包括第一方面或者第一方面的多种可能的实现方式中的一种或几种的电容模组所述的电容模组、或第三方面或者第三方面的多种可能的实现方式中的一种或几种的电容模组所述的电容模组；
PCB，用于承载各所述芯片和各所述电容模组，各所述芯片焊接固定在所述PCB的第一面，各所述电容模组通过多个引脚焊接固定在所述PCB的与所述第一面相对的第二面。
本申请的这些和其他方面在以下(多个)实施例的描述中会更加简明易懂。
附图说明
包含在说明书中并且构成说明书的一部分的附图与说明书一起示出了本申请的示例性实施例、特征和方面，并且用于解释本申请的原理。
图1示出芯片功率密度变化趋势曲线图。
图2示出芯片功率与通流变化趋势曲线图。
图3示出相关技术中某类芯片的结构示意图。
图4A-图4C示出相关技术中电容器的结构示意图。
图5A示出根据本申请一实施例的电容模组的结构立体示意图。
图5B-图5C示出根据本申请一实施例的电容模组的主视图。
图5D示出根据本申请一实施例的电容模组的俯视图。
图6示出根据本申请一实施例的电容模组的安装应用示意图。
图7A-图7E示出根据本申请一实施例的电容模组中模组载板的第一面的俯视图。
图8A-图8D示出根据本申请一实施例的电容模组中模组载板的第二面的俯视图。
图9A-图9E示出根据本申请一实施例的电容模组的俯视图。
图10A-图10B分别示出根据本申请另一实施例的电容模组的侧视图和俯视图。
图11示出根据本申请又一实施例的电容模组的侧视图。
图12示出根据本申请再一实施例的电容模组的侧视图。
图13示出根据本申请一实施例的电容模组的制造方法的流程图。
图14示出根据本申请一实施例的一电容模组的制造方法的流程示意图。
图15示出根据本申请一实施例的另一电容模组的制造方法的流程示意图。
图16示出根据本申请一实施例的又一电容模组的制造方法的流程示意图。
具体实施方式
以下将参考附图详细说明本申请的各种示例性实施例、特征和方面。附图中相同的附图标记表示功能相同或相似的元件。尽管在附图中示出了实施例的各种方面，但是除非特别指出，不必按比例绘制附图。
在这里专用的词“示例性”意为“用作例子、实施例或说明性”。这里作为“示例性”所说明的任何实施例不必解释为优于或好于其它实施例。
另外，为了更好的说明本申请，在下文的具体实施方式中给出了众多的具体细节。本领域技术人员应当理解，没有某些具体细节，本申请同样可以实施。在一些实例中，对于本领域技术人员熟知的方法、手段、元件和电路未作详细描述，以便于凸显本申请的主旨。
图1示出芯片功率密度变化趋势曲线图。图2示出芯片功率与通流变化趋势曲线图。如图1、图2所示，结合图1示出的单芯片功率密度变化趋势、以及图2示出的单芯片工作模式变化以及通流与功耗变化，可以看出：随着技术的不断进步，芯片功率密度的变化是急速增长的，而由于单板尺寸、供电模式的限制，在大功率密度需求下当前单板状况(如尺寸)并不能给电容器留下足够的放置空间。
多层陶瓷电容器作为使用较多的电容器，由于制造工艺限制，在固定尺寸下，陶瓷电容器的厚度、电极层数、材料属性都无法无限增加，因此陶瓷电容器单体容量有演进上限。同时随着陶瓷电容器单体容量增加，陶瓷电容器的尺寸随之增加，而陶瓷电容器尺寸越大越容易在在使用过程中受到应力影响而产生裂纹。故而无法完全依赖于单体陶瓷电容器容量提升来满足当前供电的容量需求。
图3示出相关技术中某类芯片的结构示意图。基于以上两点原因，以图3示出的某类芯片供电需求为例，如图3所示该芯片使用垂直通流架构，需要满足2KW/3KA以上的大通流需求垂直供电低频滤波容值总需求约40000uF，然而图3示出的当前通用平铺电容设计方式目前仅能放置15000uF，仍然存在2倍容值缺口，无法满足芯片滤波需求。需要增加单位面积的容量密度来满足供电需求。
相关技术中，通过堆叠的方式进行电容器的扩容，但都存在不同程度的问题。图4A-图4C示出相关技术中电容器的结构示意图。以下结合图4A-图4C所给出的电容器扩容方式示例，对相关技术中不同电容器扩容方式存在的问题进行说明。
图4A中所示出的相关技术1(参见CN113436887A)中，提供的是一种无引脚堆叠型陶瓷电容器，由两个陶瓷电容芯体1堆叠而成，陶瓷电容芯体1大致为长方体，其相对的两端分别设置有端电极11，陶瓷电容芯体1为多层陶瓷电容芯体，具体的陶瓷电容芯体1内部设置有第一内电极12和第二内电极13，第一内电极12与一端电极11导电连接，第二内电极13与另一端电极11导电连接，第一内电极12和第二内电极13交错平行间隔布置，且第一内电极12与第二内电极13之间设置有瓷介材料，端电极11由内向外依次为基体金属层111、阻挡层112和最外镀层113。两陶瓷电容芯体1之间设置有用于固定的粘结剂3，两陶瓷电容芯体1的同侧端电极11之间通过焊料2相互焊接形成焊接接头，焊料2包覆两陶瓷电容芯体1的同侧端电极11形成焊接接头。制备过程中：通过在相邻两陶瓷电容芯体1之间设置粘结 剂3，使多个陶瓷电容芯体整齐堆叠固定在一起，并使粘结剂3固定。在模具中对应端电极的位置设置焊料2，将堆叠好的陶瓷电容芯体1放入模具中，然后将模具放入真空共晶炉中加热焊接，使焊料2熔化扩散到多个陶瓷电容芯体1的同侧端电极表面形成焊接接头。但该相关技术1的方案存在以下问题：组装流程较为复杂：需要先胶粘、再模具焊接，组装流程较长，自动化性较差；PCB设计需要增加特殊工艺：堆叠电容在PCB上使用过程中，如使用在芯片B面(也即Bottom面)，需要通过增加PCB特殊工艺，实现PCB T面(也即Top面)以及B面网络错层，满足堆叠电容焊接要求。
图4B中所示出的相关技术2(参见CN104937684A)中，提供了一种堆叠的MLCC电容器，包括多层陶瓷电容器，每个多层陶瓷电容器包括交替堆叠的多个第一电极9和多个第二电极10，以及在每个第一电极9与每个相邻的第二电极10之间的电介质11。第一电极9终止于第一侧，第二电极10终止于第二侧。第一瞬时液相烧结导电层位于第一侧上，并与每个第一电极电接触；第二瞬时液相烧结导电层位于第二侧上并与每个第二电极电接触。陶瓷电容交替堆叠，电极之前采用瞬时液相烧结材料固定。瞬时液相烧结材料主要是在330℃下90s以上，材料固化后二次重熔温度需要600℃以上。但该相关技术2的方案存在以下问题：瞬时液相烧结(TLPS)膏作为接合材料需仰赖高温加热烧结始容易形成金属间化合物，虽然有提高机械强度的优势，但高温加热及相变化过程会使制程变异因素增加，倘若观察烧结完成的接合点的显微结构容易形成有硬脆的金属间化合物，甚至是堆叠位置或黏合点表面形成相变化后的微裂缝或体积变化后的微缝隙，纵使其支撑强度足够，但最终仍无法有效提供能抵抗反复板弯或震动的韧性，反而会促成应力集中现象形成结构破坏或破裂来源，遂使产品应用受到诸多限制，又碍于瞬时液相烧结(TLPS)膏于烧结完成后未能以镀镍、镀锡方式填补，也难以与电镀液反应形成均匀细致的电镀表面，故，微裂缝或微缝隙的问题，仍无法受到改善，即为从事于此行业者所亟欲研究改善的方向所在。再者，该方案使用中PCB设计也需要增加特殊工艺：堆叠电容在PCB上使用过程中，如使用在芯片B面，需要通过增加PCB特殊工艺，实现PCB T/B面网络错层，满足堆叠电容焊接要求。
图4C中所示出的相关技术3(参见CN211181983U)中，提供一种金属支架电容器，包括两个陶瓷电容器11和两电极片，陶瓷电容器11上下两端均具有端头电极11，两个陶瓷电容器11水平堆叠且并联在一起，电极片包括部分焊接在陶瓷电容器11端头电极11上端面或者下端面的水平板21、竖直设置在水平板21端部且与端头电极11侧面间隔布置的引脚22、竖直设置在水平板21上且紧贴端头电极11侧面的支撑脚23和间隔设置在引脚22上的三个通孔24，水平板21通过高铅焊料焊接在端头电极11上。但该相关技术3存在以下问题：组装过程繁琐，且需要根据堆叠尺寸定制高精度金属框架焊端；该方案使用中PCB设计需要增加特殊工艺：堆叠电容在PCB上使用过程中，如使用在芯片B面，需要通过增加PCB特殊工艺，实现PCB T/B面网络错层，满足堆叠电容焊接要求；金属框架与陶瓷电容、PCB存在CTE差异，潜在容易受金属框架影响，导致焊点存在微裂纹，影响功能；堆叠电容等效电感增大，导致滤波效果降低。
为解决上述技术问题，本申请提供了一种电容模组及其制造方法。该电容模组在安装面积有限的使用场景下，也可以提供较大电容值使其适用于各类不同大容值产品需求，提升了单位面积的电容器容量密度。
本申请提供如图5A-图5D所示的一种电容模组，如图5A-图5D所示，该电容模组包括： 模组载板1和固定在所述模组载板1上的多个电容器2。所述多个电容器2分为至少一个电容组，各所述电容组包括至少一个电容器2，如图5A-图5D所示电容模组包括4个电容组，每个电容组包括3个堆叠在一起的电容器2。不同电容组中所包含的电容器的数量可以相同，也可以不同。其中，不同电容组中包括相同数量的电容器，可以简化电容模组的制造过程。
如图5B-图5C、图7A-图7B、图8A-图8D所示，所述模组载板1包括相对设置的第一面(也即Top面，如图7A-图7B所示的T面)和第二面(也即Bottom面，如图8A-图8D所示的B面)，所述第一面T设置有多个安装区域S，各所述安装区域S设置有电源焊盘01和接地焊盘02。所述第二面B设置有多个引脚(pin)11，各所述引脚11通过所述模组载板1电连接到所述电源焊盘01或所述接地焊盘02。其中，如图8A-图8D所示，引脚11可以包括电源引脚111和接地引脚112。电源引脚111可以通过模组载板1内的层间布线和导电孔(导电孔可以为模组载板上的通过内壁镀金属或填充金属的通孔、盲孔、埋孔等孔结构)电连接到模组载板第一面T上的一个或多个安装区域S内的电源焊盘01。接地引脚112可以通过模组载板1内的层间布线和导电孔电连接到模组载板第一面T上的一个或多个安装区域S内的接地焊盘02。在一些实施例中，模组载板可以是PCB。在一些实施例中，如图5B所示，各引脚11可以为相对于模组载板1的第二面凸出的焊球等凸块；如图5C所示，各引脚11可以为设置于模组载板1的第二面的焊盘，本领域技术人员可以根据实际需要对引脚11的结构进行设置，本申请对此不作限制。
在一种可能的实现方式中，所述多个安装区域在所述模组载板的第一面可以呈阵列排布。以使得电容器可以在模组载板上呈相同的阵列排布。例如，可以如图5D所示呈2×2的4组电容组的阵列排布，还可以如图9A-图9E所示分别呈1×2的2个电容组、1×3的3个电容组、1×4的4个电容组、2×3的6个电容组、3×3的9个电容组的阵列排布。本领域技术人员可以根据电容模组的安装面积限定、各电容器的电容值、电容器的数量等对电容组的数量以及个安装区域在所述模组载板的第一面的排布方式进行设置，本申请对此不作限制。
在一种可能的实现方式中，可以根据实际需要对多个安装区域中电源焊盘和接地焊盘的位置，以及不同接地焊盘之间、不同电源焊盘之间、不同安装区域内的接地焊盘与电源焊盘之间的相对位置进行设置，以满足电容模组的滤波需求。在一些实施例中，部分或全部焊盘的类型与相邻的各焊盘中的至少一个的类型不同。这样，按照不同类型的焊盘交替方式进行排布，可以降低电容模组整体的等效电感，增强整体的滤波效果。例如，所述模组载板1的第一面上的多个所述电源焊盘和多个所述接地焊盘按照第一交替方式排布。其中，所述第一交替方式可以包括以下至少一种：同一行中焊盘的类型相同、且相邻行中不同行的焊盘的类型不同；同一行中，部分或全部焊盘的类型与相邻的各焊盘中的至少一个的类型不同；同一列中，部分或全部焊盘的类型与相邻的各焊盘的类型不同。
举例来说，图7A-图7E以模组载板的第一面设置有4个的电容区域，对接地焊盘、电源焊盘的交替排布方式进行示意性说明。如图7A所示对于第一面T设置有2×2的电容区域S，可以将四个安装区域S中的接地焊盘02设置于中间位置，使得四个电容区域S的接地焊盘02相对的设置于整个模组载板的中心区域，四个电源焊盘01相对地设置与整个模组载板的四周，增加电源焊盘01之间的距离，也即图7A中按照第一交替方式中的“同一行中，部分焊盘的类型与相邻的各焊盘的类型不同”进行焊盘的排布。如图7B所示，对于第一面T设置有2×2的电容区域S，也是按照第一交替方式中的“同一行中，部分焊盘的类型与相邻的 各焊盘的类型不同”进行焊盘的排布。如图7C所示，对于第一面T设置有2×2的电容区域S，是按照第一交替方式中的“同一行中，全部焊盘的类型与相邻的各焊盘的类型不同”以及“同一列中，全部焊盘的类型与相邻的各焊盘的类型不同”进行焊盘的排布。如图7D、图7E所示，对于第一面T设置有2×2的电容区域S，是按照第一交替方式中的“同一行中，全部焊盘的类型与相邻的各焊盘的类型不同”进行焊盘的排布。其中，焊盘交替的程度越大，降低电容模组整体的等效电感的效果和增强整体的滤波效果就越好，则在图7A-图7E所示的焊盘排布示例中，相比较而言，图7C的交替程度最大，其降低电容模组整体的等效电感的效果和增强整体的滤波效果相对较好。可以理解的是，本领域技术人员可以根据实际需要对第一交替方式进行焊盘的排布设置，本申请对此不作限制。
在一种可能的实现方式中，所述多个引脚11在所述模组载板的1第二面B按照与目标芯片的芯片引脚的排布方式匹配方式排布，这样，在目标芯片的芯片引脚和电容模组的多个引脚分别焊接到主板相对的两面之后，目标芯片的芯片引脚与对应的电容模组的引脚之间可以直接借助主板上目标芯片和电容模组之间的导电通孔连接，无需借助主板中的层间布线，简化目标芯片与电容模组之间的电连接。在一些实施例中，多个引脚在模组载板的第一面还可以按照预设形状连续排布，所述预设形状可以包括菱形(如图8A、图8B所示)、长方形或正方形(如图8C、图8D所示)等形状，本申请对此不作限制。在一些实施例中，部分或全部所述引脚的类型与相邻引脚中的至少一个引脚的类型不同，实现接地引脚和电源引脚之间的交替设置。这样，通过电源引脚和接地引脚的交替设置，电源引脚和接地引脚磁效应相互抵消，可降低电容模组的寄生电感，从而降低电容模组整体的等效电感，达到增强电容模组滤波效果的目的。在一些实施例中，所述多个引脚中连接电源焊盘的多个电源引脚和连接接地焊盘的多个接地引脚之间可以按照第二交替方式排布。其中，所述第二交替方式可以包括以下至少一种：同一行中各引脚的类型相同、且相邻行中不同行的引脚的类型不同；同一行中，部分或全部引脚的类型与相邻引脚中的至少一个引脚的类型不同；同一列中，部分或全部引脚的类型与相邻引脚中的至少一个引脚的类型不同。
举例来说，电源引脚111和接地引脚112可以如图8A、图8C所示分别处于不同的行，电源引脚111所在的行可以与接地引脚112所在的行交替设置，也即图8A、图8C所示的示例中引脚是按照第二交替方式中的“同一行中各引脚的类型相同、且相邻行中不同行的引脚的类型不同”排布的。也可以如图8B、图8D所示在同一行中将电源引脚111和接地引脚112交替设置，也即图8B所示的示例中引脚是按照第二交替方式中的“同一行中，每个引脚的类型与相邻引脚的类型不同”排布的，图8D所示的示例中引脚是按照第二交替方式中的“同一行中，每个引脚的类型与相邻引脚的类型不同”以及“同一列中，每个引脚的类型与相邻引脚的类型不同”排布的。其中，引脚交替的程度越大，降低电容模组整体的等效电感的效果和增强整体的滤波效果就越好，则在图8A-图7D所示的引脚排布示例中，相比较而言，图8D的交替程度最大，其降低电容模组整体的等效电感的效果和增强整体的滤波效果相对较好。
如图5A-图5D所示，各所述电容组中的各所述电容器2分不同层依次堆叠在对应的安装区域S(参见图7A-图7B)上方，各所述电容组中靠近所述模组载板1的第一层电容器的正电极21和负电极22分别焊接在对应的安装区域S中的电源焊盘01和接地焊盘02上，同一电容组中不同层的所述电容器2之间并联。
在本实施例中，不同电容组中电容器2可以一组或多组借助模组载板1并联到一对或多 对引脚11(包括一个电源引脚111和一个接地引脚112)，以使得整个电容模组可以提供不同电容值满足芯片的不同电容值需求。例如，假定图5A所示的电容模组中一个电容组中所有电容器并联后的电容值为C1，可以将图5A所示的电容模组中的一个电容组中最下层的电容器的正电极21和负电极22通过模组载板1电连接到多对引脚11，将图5A所示的电容模组中的两个电容组中最下层的电容器的正电极21和负电极22通过模组载板1电连接到另外的多对引脚11，将图5A所示的电容模组中的四个电容组中最下层的电容器的正电极21和负电极22通过模组载板1电连接到剩余的多对引脚11，则该电容模组可以提供C1、2×C1和4×C1的电容值选择。
在本实施例中，各电容器2可以设置为如图5A所示的长方体状结构，还可以设置成其他具有相对平行的两个表面的其他形状(如正方体、圆柱等具有至少一对相互平行的表面的形状)的结构，以使得同一电容组的各电容器可以利用相对平行的两个表面进行堆叠。在一些实施例中，可以在电容器2的相对平行的两个表面分别设置正电极21和负电极22，正电极21和负电极22设置为处于电容器表面的“面电极”，且不同表面的正电极之间电连接。使得每个电容器2用于与模组载板1连接或者与其他电容器2连接的两个表面均设置有正电极21和负电极22，在制造电容模组的过程中可以直接在模组载板的电源焊盘01和接地焊盘02上涂覆焊料以将电容器表面的正电极和负电极直接焊接到电源焊盘01和接地焊盘02，同理也可以直接在电容器表面涂覆焊料实现电容器之间的焊接。这样，便于实现电容器2与模组载板1之间、相互堆叠的相邻层的电容器之间的电连接。同一电容组中不同层的电容器数量可以相同或不同，每一层电容器的数量可以是一个或多个。同一电容组中不同电容器的形状、尺寸可以在保证相邻层电容器之间的电连接需求的前提下根据需要设置，不同电容器的形状和/或尺寸可以相同，也可以不同，本申请对此不作限制。
在本实施例中，由于电容器与模组载板之间通过焊接的方式实现电连接、相邻层的电容器之间也是通过焊接的方式实现电连接，而由于焊接工艺本身具有一定的强度，因此电容模组可以借助焊接实现电容器与模组载板之间、相邻层的电容器之间的电连接同时实现电容器与模组载板之间、相邻层的电容器之间固定连接，实现整个电容模组的结构固定。在一些实施例中，焊料可以是导电胶、锡膏、环氧树脂锡膏，可以根据电容模组的制造工艺过程对焊料的材料进行设置，本申请对此不作限制。
在一些实施例中，为进一步提高电容模组的结构强度，如图5B、图5C所示，可以利用贴片胶4将各第一层电容器2粘贴固定在对应的安装区域，并且/或者，还可以利用贴片胶4进行同一电容组中相邻层电容器2之间的粘贴固定。其中，为保证电容模组结构的稳定性和可靠性，在制造电容模组的工艺过程通过回流焊的形式进行电容器与模组载板之间、相邻层的电容器之间的焊接的情况下，贴片胶的耐受温度需要大于回流焊的回流温度，以保证回流焊过程中贴片胶不会在回流温度下变性导致粘贴性能变差甚至彻底融化失去作用，也要保证贴片胶在回流焊之后仍具备正常工作状态下的形状继续实现其粘贴作用。在一些实施例中，贴片胶可以涂覆在各电容器的表面与正电极和负电极所在区域不同的区域，例如，如图5B、图5C中贴片胶4涂覆在电容器2的中间区域23、涂覆在安装区域中电源焊盘与接地焊盘之间的区域。
在一些实施例中，同一电容组的各所述电容器2可以具有相同的形状和尺寸，这样，可以简化电容模组的制造过程。在一些实施例中，也可以设置电容模组中各电容器均具有相同 的形状和尺寸，这样可以进一步简化电容模组的制造过程，提高制造速度。在一些实施例中，还可以进一步设置电容模组中各电容器具有相同的电容量，这样，在形状、尺寸、电容量均相同的情况下，制造电容模组的过程中就可以按照电容组数量和每个电容组中电容器的数量，直接进行堆叠，进一步简化电容模组的制造过程，提高制造速度。
这样，通过本申请实施例提供的如图5A等所示的电容模组，仍旧应用于图3所示的某类芯片的应用场景下，相同的安装面积和供电模式的情况下，本申请图5A等所示的电容模组如图6所示可以提供更大的电容量。
在一种可能的实现方式中，电容模组还可以包括至少一个绝缘板。各所述绝缘板可以固定在模组载板的第一面，各所述绝缘板处于相邻的电容组之间。其中，在电容模组包括多个绝缘板的情况下，多个绝缘板可以为依次连接的一体结构。或者，电容模组可以包括一个绝缘板，绝缘板包括处于不同电容组之间的多个子板，如图10A、图10B所示的电容模组中的绝缘板6，其包括四个子板，各子板分别处于不同的电容组之间。绝缘板可以为塑料等绝缘材料，以实现相邻电容组之间的电隔离。
在一种可能的实现方式中，如图11所示，电容模组还可以包括封装层8，用于对整个电容模组进行封装，以将电容模组中的各电容器以及模组载板的第一面与外部环境隔离，保护整个电容模组，提供搞电容模组的可靠性和稳定性。其中，封装层可以通过塑封、覆膜等形式实现。封装层8可以与模组载板1形成能够密封模组载板1到第一面上各部件的空间。
本申请还提供一种电容模组的制造方法，如图13、图14所示，该方法包括步骤S101-步骤S106。其中，图14示出的是制造图11所示的电容模组的制造过程示意图。
在步骤S101中，在模组载板1的各安装区域S设置的电源焊盘01和接地焊盘02上涂覆焊料3。在一些实施例中，步骤S101中，还可以包括：在每个安装区域S中电源焊盘01和接地焊盘02之间的区域中的部分或全部涂覆贴片胶4。
在步骤S102中，将各电容组中处于第一层的各电容器2分别安装于对应的安装区域S。且使得处于第一层的各电容器的正电极和负电极分别通过焊料3(或者焊料3和贴片胶4)固定在对应的安装区域中的电源焊盘和接地焊盘上。
在步骤S103中，在所述模组载板1上当前最上方一层的各所述电容器2的正电极和负电极上涂覆焊料3。在一些实施例中，步骤S103还可以包括：在所述模组载板1上当前最上方一层的各所述电容器2的中间区域涂覆贴片胶4。在一些实施例中，若不同电容组电容的数量不一致，则在涂覆焊料(或者焊料和贴片胶)的过程中，可以仅在当前最上方一层的各所述电容器2中之后还需要堆叠电容器的电容器上涂覆焊料(或者焊料和贴片胶)。
在步骤S104中，将下一层的各电容器2分别安装于对应的已安装完的电容器2上方，下一层的各电容器2的正电极和负电极分别通过焊料固定在对应的已安装完的电容器的正电极和负电极上。
在步骤S105中，检测当前是否已经完成电容模组的组装。若已经完成组装，则执行步骤S105，若还未完成组装继续执行步骤S103。其中，是否完成组装可以根据是否已经完成所有模组载板上的部件安装来确定，这些部件可以包括电容器、绝缘板等。
在步骤S106中，进行回流焊，以将第一层的各电容器的正电极和负电极分别与对应的电源焊盘和接地焊盘之间焊接、将相邻层电容器之间焊接，得到电容模组。
这样，在完成电容模组的组装之后再进行回流焊，通过一次回流焊完成整个电容模组的 焊接，加工工艺简单，且避免电容模组二次回流应用中掉件等风险，解决了电容模组在B/T面均能应用问题。
在一种可能的实现方式中，如图14所示，该方法还包括：在步骤S106之后，对步骤S106得到的电容模组进行封装，形成封装层8。
在一种可能的实现方式中，在上述方法中，若电容模组还包括绝缘板，则若电容模组包括封装层8则可以在进行封装之前的任意步骤将各绝缘板固定在模组载板上；或者若电容模组不包括封装层8则可以在完成整个电容模组制造之前的任意步骤将各绝缘板固定在模组载板上。其中，绝缘板可以通过与模组载板上设置的凹槽卡接，还可以通过贴片胶等粘贴固定到模组载板上，可根据实际需要对绝缘板固定到模组载板上的方式进行设置，本申请对此不作限制。
本申请还提供另外一种电容模组，如图12所示，该电容模组包括多个模组载板1、多个金属连接件5和焊接固定在各所述模组载板1上的多个电容器2。各所述模组载板1的第一面分别设置有多个安装区域，各所述安装区域设置有电源焊盘和接地焊盘，所述多个模组载板1中的最下层模组载板还包括与所述第一面相对设置的第二面且所述第二面设置有多个引脚11。各所述电容器2，焊接固定在对应模组载板1的对应的安装区域上方、且正电极和负电极分别焊接在所在安装区域中的电源焊盘和接地焊盘上。所述多个金属连接件5用于将所述多个模组载板1固定连接在一起，各所述金属连接件5焊接固定在对应的两个所述模组载板1上，且各所述金属连接件5电连接到所焊接的两个所述模组载板1中至少一个模组载板1上的一个或多个电容器2。其中，各所述引脚11电连接的目标包括：所述最下层模组载板1上的一个或多个所述电容器2、和/或焊接在所述最下层模组载板1上的金属连接件5电连接的所述电容器2中一个或多个。其中，图12所示的电容模组与图5A-图5D所示以及上文所描述的电容模组之间的区别在于，电容模组的装配、组装方式不同，其他类似，为简明以下仅对不同部分进行描述，相同部分参见上文，此处不予赘述。其中，图12所示的电容模组与图5A-图5D所示以及上文所描述的电容模组之间的区别在于：电容模组中模组载板的数量不同；且图5A-图5D所示的电容模组是利用焊料(或者焊料和贴片胶)保证了电容模组的结构稳定性，图12所示的电容模组是利用多个模组载板和金属连接件实现了电容模组的结构稳定。
在本实施例中，金属连接件5可以是铜等导电且具有满足结构支撑强度需求的金属柱、片、条等连接件。在一些实施例中，各金属连接件5所焊接的两个模组载板可以是相邻的两个模组载板，这样，通过相邻的两个模组载板之间的一个或多个金属连接件就可以实现相邻两个模组载板之间的固定连接。在一些实施例中，各金属连接件所焊接的两个模组载板可以一个是最下层模组载板一个是其他模组载板，这样使得每个模组载板均可以通过一个或多个金属连接件固定连接到最下层模组载板。金属连接件的两端分别焊接的模组载板上可以设置有导电孔(若模组载板为最下层模组载板，则导电孔可以与最下层模组载板上的至少一个电容器电连接，也可以不和任何电容器连接。若模组载板为除最下层模组载板之外的任意一个模组载板，则导电孔可以与该模组载板上的至少一个电容器电连接)，以使得金属连接件的端部可以放置于导电孔中或穿过该导电孔，并借助焊料将金属连接件的端部焊接到所在导电孔中，实现金属连接件与模组载板之间的固定连接以及电连接。在金属连接件所焊接的两个模 组载板之间还有一个或多个处于中间的模组载板的情况下，可以在中间的模组载板上对应于金属连接件的位置设置通孔，以使得金属连接件可以穿过该通孔。其中，金属连接件也可以焊接到中间的模组载板上，以加固电容模组整体的结构强度；并且/或者，金属连接件焊接到中间的模组载板上通孔可以是导电孔，该导电孔可以与所在模组载板上的至少一个电容器电连接。
在本实施例中，利用多个金属连接件将多个模组载板固定连接的一起的方式是多种多样的。由于金属连接件两端的焊接状态可以包括以下任意一种：焊接在相邻层模组载板之间，焊接在最下层模组载板与和最下层模组载板不相邻的其他模组载板之间、不相邻的非最下层模组载板之间。因此，可以根据实际需要对不同金属连接件的焊接状态进行设置，本申请对此不作限制。
在本实施例中，图12所示的电容模组也可以包括绝缘板和/或封装层。其中，绝缘板和封装层的设置与上述电容模组的实现方式类似，可以参见上文相关描述，未免冗余，此处不予赘述。
若图12所示的各金属连接件均焊接在相邻层模组载板之间，则电容模组的制造过程可以如图15所示。该电容模组制造方法可以包括以下两个步骤：单板焊接步骤和多板组装步骤。
单板焊接步骤中：
在每个模组载板的各安装区域中电源焊盘和接地焊盘上涂覆焊料，并在需要焊接金属连接件的安装位置所在的通孔处也涂覆焊料。而后将需要安装到该模型载板上的电容器分别放置于对应的安装区域中，并使得各电容器的正电极和负电极分别处于所在安装全区域的电源焊盘和接地焊盘处；以及将需要焊接的金属连接件安装在对应的通孔处。通过回流焊将各模组载板上的电容器和金属连接件焊接到模组载板到第一面。
多板组装步骤：
在完成每个模组载板上电容器和金属连接件的焊接之后，按照模组载板上电容器的堆叠顺序组装出电容模组，并将组装后的电容模组中各金属连接件焊接到上层模组载板的第二面。
在一些实施例中，在制造图12所示的电容模组过程中，也可以如图16所示，按照模组载板的堆叠顺序，依次进行如下步骤：最下的第一层模组载板上电容器和金属连接件的焊接；第二层模组载板与焊接在第一层模组载板上金属连接件的焊接；第二层模组载板上电容器和金属连接件的焊接，以此类推，直至进行最后一层模组载板与焊接在最后一层的下一层的模组载板上金属连接件的焊接以及最后一层模组载板上电容器的焊接之后，确定完成电容模组的制造。
在一些实施例中，若图12所示的电容模组中各金属连接件均焊接在最下层模组载板和其他模组载板之间，则可以参照图16所示的方式进行电容模组的制备，未免冗余，此处不予赘述。或者，若图12所示的电容模组中部分金属连接件焊接在最下层模组载板和其他模组载板之间、其他金属连接件焊接在不包括最下层模组载板的两个模组载板之间，则可以结合图15和图16所示的方式进行电容模组的制备。可以理解的是，可以根据图12所示的电容模组的结构对制造过程进行设置，本申请对此不作限制。
本申请实施例还提供一种电子设备，包括：
至少一个芯片；
至少一个电容模组，各电容模组为上文所述的电容模组中的任意一个；
PCB，用于承载各所述芯片和各所述电容模组，各所述芯片焊接固定在所述PCB的第一面，各所述电容模组通过多个引脚焊接固定在所述PCB的与所述第一面相对的第二面。
附图中的流程图和框图显示了根据本申请的多个实施例的装置、系统、方法和计算机程序产品的可能实现的体系架构、功能和操作。在这点上，流程图或框图中的每个方框可以代表一个模块、程序段或指令的一部分，所述模块、程序段或指令的一部分包含一个或多个用于实现规定的逻辑功能的可执行指令。在有些作为替换的实现中，方框中所标注的功能也可以以不同于附图中所标注的顺序发生。例如，两个连续的方框实际上可以基本并行地执行，它们有时也可以按相反的顺序执行，这依所涉及的功能而定。
也要注意的是，框图和/或流程图中的每个方框、以及框图和/或流程图中的方框的组合，可以用执行相应的功能或动作的硬件(例如电路或ASIC(Application Specific Integrated Circuit，专用集成电路))来实现，或者可以用硬件和软件的组合，如固件等来实现。
尽管在此结合各实施例对本发明进行了描述，然而，在实施所要求保护的本发明过程中，本领域技术人员通过查看所述附图、公开内容、以及所附权利要求书，可理解并实现所述公开实施例的其它变化。在权利要求中，“包括”(comprising)一词不排除其他组成部分或步骤，“一”或“一个”不排除多个的情况。单个处理器或其它单元可以实现权利要求中列举的若干项功能。相互不同的从属权利要求中记载了某些措施，但这并不表示这些措施不能组合起来产生良好的效果。
以上已经描述了本申请的各实施例，上述说明是示例性的，并非穷尽性的，并且也不限于所披露的各实施例。在不偏离所说明的各实施例的范围和精神的情况下，对于本技术领域的普通技术人员来说许多修改和变更都是显而易见的。本文中所用术语的选择，旨在最好地解释各实施例的原理、实际应用或对市场中的技术的改进，或者使本技术领域的其它普通技术人员能理解本文披露的各实施例。

Claims (24)

  1. 一种电容模组，其特征在于，包括：模组载板和固定在所述模组载板上的多个电容器，所述多个电容器分为至少一个电容组，各所述电容组包括至少一个电容器；
    所述模组载板包括相对设置的第一面和第二面，所述第一面设置有多个安装区域，各所述安装区域设置有电源焊盘和接地焊盘，所述第二面设置有多个引脚，各所述引脚通过所述模组载板电连接到所述电源焊盘或所述接地焊盘；
    各所述电容组中的各所述电容器分不同层依次堆叠在对应的安装区域上方，各所述电容组中靠近所述模组载板的第一层电容器的正电极和负电极分别焊接在对应的安装区域中的电源焊盘和接地焊盘上，同一电容组中不同层的所述电容器之间并联。
  2. 根据权利要求1所述的电容模组，其特征在于，所述多个安装区域在所述模组载板的第一面呈阵列排布；并且/或者，部分或全部焊盘的类型与相邻的各焊盘中的至少一个的类型不同。
  3. 根据权利要求1所述的电容模组，其特征在于，所述多个引脚在所述模组载板的第二面按照与目标芯片的芯片引脚的排布方式匹配的方式排布；并且/或者，
    所述多个引脚在所述模组载板的第二面按照预设形状连续排布，所述预设形状包括菱形、长方形或正方形中的任意一种；并且/或者，
    部分或全部所述引脚的类型与相邻引脚中的至少一个引脚的类型不同。
  4. 根据权利要求1所述的电容模组，其特征在于，所述电容模组还包括：
    封装层，用于封装所述电容模组。
  5. 根据权利要求1所述的电容模组，其特征在于，所述电容模组还包括：
    至少一个绝缘板，固定在所述模组载板的第一面，各所述绝缘板处于相邻的电容组之间。
  6. 根据权利要求5所述的电容模组，其特征在于，在所述绝缘板包括多个的情况下，所述多个绝缘板依次连接。
  7. 根据权利要求1所述的电容模组，其特征在于，各所述电容组中的相邻层的电容器之间利用贴片胶固定，和/或第一层电容器与所述模组载板之间利用贴片胶固定。
  8. 根据权利要求1所述的电容模组，其特征在于，同一电容组的各所述电容器具有相同的形状和尺寸。
  9. 一种电容模组的制造方法，其特征在于，包括：
    在模组载板的各安装区域设置的电源焊盘和接地焊盘上涂覆焊料，所述模组载板包括相对设置的第一面和第二面，所述第一面设置有多个安装区域，所述第二面设置有多个引脚，各所述引脚通过所述模组载板连接到所述电源焊盘或所述接地焊盘；
    将各电容组中处于第一层的各电容器分别安装于对应的安装区域，处于第一层的各电容器的正电极和负电极分别通过焊料固定在对应的安装区域中的电源焊盘和接地焊盘上；
    在所述模组载板上当前最上方一层的各所述电容器的正电极和负电极上涂覆焊料；
    将下一层的各电容器分别安装于对应的已安装完的电容器上方，下一层的各电容器的正电极和负电极分别通过焊料固定在对应的已安装完的电容器的正电极和负电极上，重复执行在当前模组载板上最上方一层的各所述电容器的正电极和负电极上涂覆焊料及之后的步骤，直至完成所有电容组中各电容器的安装，处于同一安装区域上方的各电容器属于同一电容组；
    进行回流焊，以将第一层的各电容器的正电极和负电极分别与对应的电源焊盘和接地焊盘之间焊机以及将相邻层电容器之间焊接，得到电容模组。
  10. 根据权利要求9所述的方法，其特征在于，所述多个安装区域在所述模组载板的第一面呈阵列排布；并且/或者，部分或全部焊盘的类型与相邻的各焊盘中的至少一个的类型不同。
  11. 根据权利要求9所述的方法，其特征在于，所述多个引脚在所述模组载板的第二面按照与目标芯片的芯片引脚的排布方式匹配的方式排布；并且/或者，
    所述多个引脚在所述模组载板的第二面按照预设形状连续排布，所述预设形状包括菱形、长方形或正方形中的任意一种；并且/或者，
    部分或全部所述引脚的类型与相邻引脚中的至少一个引脚的类型不同。
  12. 根据权利要求9所述的方法，其特征在于，所述方法还包括：
    在安装第一层的各所述电容器之前，在所述模组载板的各安装区域中胶黏区域涂覆贴片胶，所述安装区域中涂覆贴片胶的区域与所述电源焊盘和所述接地焊盘所在区域不同；和/或
    在安装下一层的各所述电容器之前，在所述模组载板上当前最上方一层的各所述电容器上涂覆贴片胶，各所述电容器中涂覆贴片胶的区域与所述电容器的正电极和负电极所在区域不同。
  13. 根据权利要求9所述的方法，其特征在于，所述方法还包括：
    对回流焊得到的电容模组进行封装，形成所述电容模组的封装层。
  14. 根据权利要求9所述的方法，其特征在于，所述方法还包括：
    将至少一个绝缘板固定在所述模组载板的第一面，各所述绝缘板处于相邻的电容组之间。
  15. 根据权利要求14所述的方法，其特征在于，在所述绝缘板包括多个的情况下，所述多个绝缘板依次连接。
  16. 根据权利要求9所述的方法，其特征在于，同一电容组的各所述电容器具有相同的形状和尺寸。
  17. 一种电容模组，其特征在于，包括：多个模组载板、多个金属连接件和焊接固定在各所述模组载板上的多个电容器；
    各所述模组载板的第一面分别设置有多个安装区域，各所述安装区域设置有电源焊盘和接地焊盘，所述多个模组载板中的最下层模组载板还包括与所述第一面相对设置的第二面且所述第二面设置有多个引脚；
    各所述电容器，焊接固定在对应模组载板的对应的安装区域上方、且正电极和负电极分别焊接在所在安装区域中的电源焊盘和接地焊盘上；
    所述多个金属连接件用于将所述多个模组载板固定连接在一起，各所述金属连接件焊接固定在对应的两个所述模组载板上，且各所述金属连接件电连接到所焊接的两个所述模组载板中至少一个模组载板上的一个或多个电容器；
    其中，各所述引脚电连接的目标包括：所述最下层模组载板上的一个或多个所述电容器、和/或焊接在所述最下层模组载板上的金属连接件电连接的所述电容器中一个或多个。
  18. 根据权利要求17所述的电容模组，其特征在于，各所述模组载板上第一面的所述多个安装区域在呈阵列排布；并且/或者，部分或全部焊盘的类型与相邻的各焊盘中的至少一个 的类型不同。
  19. 根据权利要求17所述的电容模组，其特征在于，所述多个引脚在所述最下层模组载板的第二面按照与目标芯片的芯片引脚的排布方式匹配的方式排布；并且/或者，
    所述多个引脚在所述模组载板的第二面按照预设形状连续排布，所述预设形状包括菱形、长方形或正方形中的任意一种；并且/或者，
    部分或全部所述引脚的类型与相邻引脚中的至少一个引脚的类型不同。
  20. 根据权利要求17所述的电容模组，其特征在于，各所述金属连接件焊接固定在相邻的两个所述模组载板上。
  21. 根据权利要求17所述的电容模组，其特征在于，所述电容模组还包括：
    封装层，用于封装所述电容模组。
  22. 根据权利要求17所述的电容模组，其特征在于，所述电容模组还包括：
    至少一个绝缘板，各所述绝缘板固定对应的所述模组载板的第一面、且处于相邻的电容器之间。
  23. 根据权利要求17所述的电容模组，其特征在于，各所述电容器具有相同的形状和尺寸。
  24. 一种电子设备，其特征在于，包括：
    至少一个芯片；
    至少一个电容模组，各所述电容模块包括权利要求1-8任意一项所述的电容模组、或权利要求17-23任意一项所述的电容模组；
    PCB，用于承载各所述芯片和各所述电容模组，各所述芯片焊接固定在所述PCB的第一面，各所述电容模组通过多个引脚焊接固定在所述PCB的与所述第一面相对的第二面。
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CN217389115U (zh) * 2022-06-01 2022-09-06 亿咖通(湖北)技术有限公司 一种集成电路板、电子设备、智能座舱和汽车

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US20130248235A1 (en) * 2010-12-29 2013-09-26 Industrial Technology Research Institute Embedded capacitor module
CN203775526U (zh) * 2014-04-14 2014-08-13 东莞栢能电子科技有限公司 Pcb电容模块
CN206363893U (zh) * 2016-12-26 2017-07-28 北京元六鸿远电子科技股份有限公司 一种大容量mlcc电容阵列板
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