WO2024109870A1 - Mos器件的制备方法 - Google Patents

Mos器件的制备方法 Download PDF

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Publication number
WO2024109870A1
WO2024109870A1 PCT/CN2023/133565 CN2023133565W WO2024109870A1 WO 2024109870 A1 WO2024109870 A1 WO 2024109870A1 CN 2023133565 W CN2023133565 W CN 2023133565W WO 2024109870 A1 WO2024109870 A1 WO 2024109870A1
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source
drain region
drain
layer
doping
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PCT/CN2023/133565
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English (en)
French (fr)
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罗军
孔梦娟
孙祥烈
许静
李俊峰
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中国科学院微电子研究所
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Publication of WO2024109870A1 publication Critical patent/WO2024109870A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a method for preparing a MOS device.
  • MOS metal-oxide-semiconductor
  • CMOS complementary metal-oxide-semiconductor
  • source-drain contact resistance plays a vital role in improving device performance. Therefore, how to reduce source-drain contact resistance is a technical problem that technicians in this field need to solve urgently.
  • the present invention provides a method for preparing a MOS device, which can increase the impurity activation concentration at the source and drain surfaces, thereby reducing the source and drain contact resistivity.
  • the present invention provides a method for preparing a MOS device, comprising:
  • Metal silicide is formed on the surface of the source/drain region.
  • the doping the source/drain region includes: doping by ion implantation, or doping the source/drain by in-situ doping.
  • the pre-amorphizing the doped source/drain regions comprises: injecting one of Ge, Si and As into the doped source/drain regions.
  • any one of Ge, Si and As is implanted into the doped source/drain region, and the process conditions are: energy 0.5-3keV, dosage 1 ⁇ 10 14 cm -3 ⁇ 1 ⁇ 10 16 cm -3 .
  • the thickness of the amorphous layer is 6-9 nm.
  • the temperature range of treating the source/drain region by using an oxidation process is 300-600°C.
  • the method further comprises:
  • a first heat treatment is performed on the source/drain region to activate impurities.
  • forming a metal silicide on the surface of the source/drain region includes:
  • the source/drain region is subjected to a second heat treatment to make the metal layer react with the material on the surface of the source/drain region to form a metal silicide.
  • the metal layer is Ti, TiN or a combination of Ti and TiN.
  • a second heat treatment is performed on the source/drain region by using rapid thermal annealing or laser annealing, with a temperature of 400-600° C. and a time of 10-60 seconds.
  • the method for preparing a MOS device is to perform a pre-amorphization treatment on the surface of the substrate after source and drain doping, and then perform an oxidation process.
  • the oxidation process can enable impurities to be segregated at the surface of the substrate, thereby increasing the impurity activation concentration at the surface of the source and drain, and then reducing the source and drain contact resistivity. Since the pre-amorphization treatment is performed on the surface before the oxidation process, an amorphous layer is formed on the surface, which is conducive to more impurities being segregated to the surface of the substrate during the oxidation process.
  • the present invention effectively increases the doping concentration on the surface of the source and drain, it does not increase the source and drain junction depth, the process is simple, and it is compatible with the CMOS process.
  • FIG1 is a schematic diagram of a process flow of a method for preparing a MOS device according to an embodiment of the present invention
  • Step 3 device structure cross-sectional view.
  • a layer/element when a layer/element is referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element or an intervening layer/element may exist between them. In addition, if a layer/element is "on” another layer/element in one orientation, the layer/element may be "below” the other layer/element when the orientation is reversed.
  • contact resistance can be reduced by increasing the contact area and reducing the contact resistivity.
  • An important method to reduce the contact resistivity is to increase the impurity activation concentration on the source and drain surfaces. This is because as the impurity activation concentration on the source and drain surfaces increases, the Schottky barrier width becomes narrower, and the tunneling probability of carriers increases significantly.
  • the preparation method protected by this application is based on the consideration of increasing the impurity activation concentration.
  • An embodiment of the present invention provides a method for manufacturing a MOS device, as shown in FIG1 , comprising:
  • Step S101 providing a substrate, on which a gate region and a source/drain region are formed, and a through hole is formed in a dielectric layer on the substrate, wherein the through hole exposes the surface of the source/drain region;
  • Step S102 doping the source/drain regions
  • Step S103 performing a pre-amorphization treatment on the doped source/drain regions to form an amorphous layer on the surface of the source/drain regions;
  • Step S104 using an oxidation process to treat the source/drain region so that the impurities are close to the amorphous layer to achieve segregation;
  • Step S105 removing the oxidized amorphous layer
  • Step S106 forming metal silicide on the surface of the source/drain region.
  • Figures 2 to 7 show cross-sectional views of device structures corresponding to each step of an embodiment of the present invention.
  • a substrate is provided, on which a gate region 3 and a source/drain region 1 are formed, and a through hole is formed in a dielectric layer 4 on the substrate, and the through hole exposes the surface of the source/drain region 1.
  • the material of the substrate can be a semiconductor material such as Si, Ge or SiGe, and this embodiment is described by taking a Si substrate as an example.
  • a shallow trench isolation 5 is also formed on the substrate, and a spacer layer 6 is surrounded by the periphery of the gate region 3.
  • the above-mentioned substrate is a semi-finished substrate on which a source/drain region 1, a gate region 3, a dielectric layer 4 and a shallow trench isolation 5 have been prepared.
  • the formation process can refer to the existing preparation process, and this application does not limit it.
  • the source/drain region 1 is doped. If the MOS device is an NMOS device, the source/drain region 1 is doped with N-type impurities (such as nitrogen, phosphorus or arsenic); if the MOS device is a PMOS device, the source/drain region 1 is doped with P-type impurities (such as boron, gallium or indium).
  • the source/drain may be doped by ion implantation or in-situ doping. Taking the implantation of P ions as an example, the energy is 0.5-3keV, and the dose is 1 ⁇ 10 15 cm -3 ⁇ 1 ⁇ 10 16 cm -3 .
  • the doped source/drain region 1 is pre-amorphized to form an amorphous layer 7 on the surface of the source/drain region 1.
  • the pre-amorphization is performed by the following method: any one of Ge, Si, and As is injected into the doped source/drain region 1.
  • the injection of Ge, Si, or As can be performed under the same process conditions, and an optional process condition is: energy 0.5-3keV, dose 1 ⁇ 10 14 cm -3 ⁇ 1 ⁇ 10 16 cm -3 .
  • the thickness of the formed amorphous layer 7 is generally 6 to 9 nm.
  • step S104 the source/drain region 1 is treated with an oxidation process to make the impurities close to the amorphous layer 7 to achieve segregation.
  • the amorphous layer 7 is oxidized and converted into an oxidized amorphous layer 7'.
  • the oxidation process is performed so that the impurities are on the surface of the substrate (taking the silicon substrate as an example, that is, the SiO2 /Si interface).
  • the presence of the amorphous layer 7 facilitates more impurities to be segregated to the substrate surface during the oxidation process.
  • the temperature range of the oxidation process is 300° C. to 600° C.
  • the 600° C. ISSG oxidation process is taken as an example.
  • the source/drain region 1 needs to be subjected to a first heat treatment to activate the impurities; or, after the source/drain region 1 is treated with an oxidation process, the source/drain region 1 needs to be subjected to a first heat treatment to activate the impurities.
  • the first heat treatment is performed using spike annealing at a temperature of 1050° C. for 60 seconds.
  • step S105 the oxidized amorphous layer 7' is removed.
  • This step can be implemented using a wet etching process.
  • FIG6 shows a schematic diagram of the structure of removing the amorphous layer 7'.
  • the oxidized amorphous layer 7' is made of doped SiO2 , and the etchant is a mixed solvent of HF and water (1:100).
  • a metal silicide 8 is formed on the surface of the source/drain region 1.
  • the process includes: firstly depositing a metal layer 2, the metal layer 2 covers the bottom and sidewalls of the through hole and the surface of the dielectric layer 4; the metal layer 2 can be Ti, or TiN, or a combination of the two, or other metals used to form silicides, such as Ni, NiPt.
  • Ti/TiN is commonly used in 3D FinFET processes, with a Ti thickness of 5 to 10 nm and a TiN thickness of 5 to 10 nm.
  • a second heat treatment is performed on the source/drain region 1 to react the metal layer 2 with the material on the surface of the source/drain region 1 to form a metal silicide.
  • An optional method is to perform a second heat treatment on the source/drain region using rapid thermal annealing or laser annealing at a temperature of 400 to 600°C for 10 to 60 seconds.
  • a method for preparing a MOS device comprises the following steps: after source and drain doping, the substrate surface is subjected to a pre-amorphization treatment, and then an oxidation process is performed.
  • the oxidation process can cause impurities to be segregated at the substrate surface, thereby increasing the impurity activation concentration at the source and drain surface, and further reducing the source and drain contact resistivity. Since the surface is pre-amorphized before oxidation, an amorphous layer is formed on the surface, which is conducive to more impurities being segregated to the substrate surface during the oxidation process.
  • the present invention effectively increases the doping concentration on the source and drain surface, it does not increase the source and drain junction depth, the process is simple, and it is compatible with CMOS processes.

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Abstract

本发明提供一种MOS器件的制备方法，包括：提供衬底，衬底上形成有栅区、源/漏区，并在衬底上的介质层中形成有通孔，通孔暴露出源/漏区的表面；对源/漏区进行掺杂；对掺杂后的源/漏区进行预非晶化处理，以使源/漏区表面形成非晶层；使用氧化工艺处理源/漏区，使杂质靠近非晶层实现分凝；去除被氧化的非晶层；在源/漏区表面形成金属硅化物。本发明能够降低源漏接触电阻。

Description

MOS器件的制备方法
本申请要求于2022年11月25日提交中国专利局、申请号为202211515818.8、发明名称为“MOS器件的制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体技术领域，尤其涉及一种MOS器件的制备方法。
背景技术
在半导体器件中，包含MOS(金属-氧化物-半导体)结构的器件，比如MOS器件、CMOS(互补金属氧化物半导体)器件的应用非常广泛。
随着器件尺寸的缩小，尤其进入16/14nm及以下技术节点，源漏区接触电阻对器件性能的提升起着至关重要的作用。因此，如何降低源漏区接触电阻是本领域技术人员亟需解决的技术问题。
发明内容
为解决上述问题，本发明提供了一种MOS器件的制备方法，能够提高源漏表面处的杂质激活浓度，进而降低源漏接触电阻率。
本发明提供一种MOS器件的制备方法，包括：
提供衬底，所述衬底上形成有栅区、源/漏区，并在所述衬底上的介质层中形成有通孔，所述通孔暴露出所述源/漏区的表面；
对所述源/漏区进行掺杂；
对掺杂后的所述源/漏区进行预非晶化处理，以使所述源/漏区表面形成非晶层；
使用氧化工艺处理所述源/漏区，使杂质靠近所述非晶层实现分凝；
去除被氧化的所述非晶层；
在所述源/漏区表面形成金属硅化物。
可选地，所述对所述源/漏区进行掺杂包括：采用离子注入的方式掺杂，或者采用原位掺杂的方式对源漏进行掺杂。
可选地，所述对掺杂后的所述源/漏区进行预非晶化处理，包括：向掺杂后的所述源/漏区注入Ge、Si、As中的一种。
可选地，向掺杂后的所述源/漏区注入Ge、Si、As中的任意一种，其工艺条件为：能量0.5-3keV，剂量1×1014cm-3～1×1016cm-3。
可选地，所述非晶层的厚度为6～9nm。
可选地，使用氧化工艺处理所述源/漏区的温度范围在300～600℃。
可选地，所述方法还包括：
在预非晶化处理之前，对所述源/漏区进行第一热处理来激活杂质；
或者，在使用氧化工艺处理所述源/漏区之后，对所述源/漏区进行第一热处理来激活杂质。
可选地，所述在所述源/漏区表面形成金属硅化物，包括：
沉积金属层，所述金属层覆盖所述通孔的底部和侧壁以及所述介质层的表面；
对所述源/漏区进行第二热处理，使所述金属层与所述源/漏区表面的材料反应形成金属硅化物。
可选地，所述金属层为Ti、TiN或者Ti与TiN的组合。
可选地，使用快速热退火或者激光退火对所述源/漏区进行第二热处理，温度为400～600℃，时间10～60s。
本发明实施例提供的MOS器件的制备方法，源漏掺杂后，对衬底表面进行预非晶化处理，然后进行氧化工艺。氧化工艺可以使得杂质在衬底表面处实现分凝，从而提高源漏表面处的杂质激活浓度，进而降低源漏接触电阻率。由于氧化工艺之前在表面进行预非晶化处理，使表面形成非晶层，有利于更多的杂质在氧化工艺中分凝到衬底表面。而且本发明在有效提高源漏表面掺杂浓度的同时，不会增加源漏结深，工艺简单，并与CMOS工艺兼容。
附图说明
图1为本发明一实施例提供的MOS器件的制备方法的工艺流程示意图；
图2至图7分别示出了本发明一实施例MOS器件的制备方法的各步 骤器件结构剖面视图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
下面结合附图，对本发明的一些实施方式作详细说明。在不冲突的情况下，下述的实施例及实施例中的特征可以相互组合。
按照现有理论，接触电阻可以通过增大接触面积和降低接触电阻率来降低。降低接触电阻率的一个重要方法是增加源漏表面杂质激活浓度，这是因为源漏表面杂质激活浓度增加，肖特基势垒宽度随之变窄，载流子的隧穿几率会显著提高。本申请保护的制备方法就是从提高杂质激活浓度考虑的。
本发明一实施例提供一种MOS器件的制备方法，如图1所示，包括：
步骤S101，提供衬底，衬底上形成有栅区、源/漏区，并在衬底上的介质层中形成有通孔，通孔暴露出源/漏区的表面；
步骤S102，对源/漏区进行掺杂；
步骤S103，对掺杂后的源/漏区进行预非晶化处理，以使源/漏区表面形成非晶层；
步骤S104，使用氧化工艺处理源/漏区，使杂质靠近非晶层实现分凝；
步骤S105，去除被氧化的非晶层；
步骤S106，在源/漏区表面形成金属硅化物。
需要说明的是，本申请公开的制备方法适用于3D FinFET器件，也适用于平面MOS器件。
下面详细介绍本申请公开的制备方法的各步骤。图2至图7示出了本发明一个实施例各步骤对应的器件结构剖面视图。
在步骤S101，参考图2，提供衬底，衬底上形成有栅区3、源/漏区1，并在衬底上的介质层4中形成有通孔，通孔暴露出源/漏区1的表面。衬底的材料可以是Si、Ge或SiGe等半导体材料，本实施例以Si衬底为例进行说明。衬底上还形成有浅沟槽隔离5，栅区3的外围围绕有间隔层6。上述衬底是一个已经制备了源/漏区1、栅区3、介质层4和浅沟槽隔离5的半成品衬底，其形成过程可以参考现有的制备工艺，本申请不做限定。
在步骤S102，参考图3，对源/漏区1进行掺杂。如果MOS器件为NMOS器件，则对源/漏区1进行N型杂质(例如氮，磷或砷)掺杂；如果MOS器件为PMOS器件，则对源/漏区1进行P型杂质(例如硼、镓或铟)掺杂。可以采用离子注入的方式掺杂，或者采用原位掺杂的方式对源漏进行掺杂。以注入P离子为例，能量0.5-3keV,剂量1×1015cm-3～1×1016cm-3。
在步骤S103，参考图4，对掺杂后的源/漏区1进行预非晶化处理，以使源/漏区1表面形成非晶层7。本实施例中，进行预非晶化处理，通过以下方式实现：向掺杂后的源/漏区1注入Ge、Si、As中的任意一种。注入Ge、Si或者As，可以在相同的工艺条件下进行，一种可选的工艺条件为：能量0.5-3keV，剂量1×1014cm-3～1×1016cm-3。
形成的非晶层7的厚度一般为6～9nm。
在步骤S104，参考图5，使用氧化工艺处理源/漏区1，使杂质靠近非晶层7实现分凝。在该步骤中，非晶层7被氧化，转化为被氧化的非晶层7’。进行氧化工艺使得杂质在衬底表面(以硅衬底为例，即SiO2/Si界面) 处实现分凝，由于非晶层7的存在，有利于更多的杂质在氧化工艺中分凝到衬底表面。氧化工艺的温度范围在300℃～600℃。这里以600℃ISSG氧化工艺为例。
另外要说明的是，在预非晶化处理之前，需要对源/漏区1进行第一热处理来激活杂质；或者，在使用氧化工艺处理源/漏区1之后，对源/漏区1进行第一热处理来激活杂质。具体地，使用尖峰退火进行第一热处理，温度为1050℃，时间60s。
在步骤S105，去除被氧化的非晶层7’。该步骤可以使用湿法刻蚀工艺实现。图6示出了去除非晶层7’的结构示意图，被氧化的非晶层7’的材质是掺杂的SiO2，刻蚀剂使用HF和水(1:100)的混合溶剂。
在步骤S106，参考图7，在源/漏区1表面形成金属硅化物8。具体包括：首先沉积金属层2，金属层2覆盖通孔的底部和侧壁以及介质层4的表面；该金属层2可以是Ti，也可以是TiN或者二者组合，也可以是其它用来形成硅化物的金属，如Ni，NiPt。目前3D FinFET工艺普遍采用Ti/TiN，Ti厚度5～10nm，TiN厚度5～10nm。然后对源/漏区1进行第二热处理，使金属层2与源/漏区1表面的材料反应形成金属硅化物。一种可选的方式为：使用快速热退火或者激光退火对源/漏区进行第二热处理，温度为400～600℃，时间10～60s。
本发明实施例提供的一种MOS器件的制备方法，源漏掺杂后，对衬底表面进行预非晶化处理，然后进行氧化工艺。氧化工艺可以使得杂质在衬底表面处实现分凝，从而提高源漏表面处的杂质激活浓度，进而降低源漏接触电阻率。由于氧化之前在表面进行预非晶化处理，使表面形成非晶层，有利于更多的杂质在氧化工艺中分凝到衬底表面。而且本发明在有效提高源漏表面掺杂浓度的同时，不会增加源漏结深，工艺简单，并与CMOS工艺兼容。
另外说明的是，形成金属硅化物之后，还有一些后续工艺，例如去除表面的金属层，通孔填充金属引出源漏区，等等，均为本领域常规技术，本申请不再展开叙述。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成 所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的保护范围为准。

Claims (10)

  1. 一种MOS器件的制备方法，其特征在于，所述方法包括：
    提供衬底，所述衬底上形成有栅区、源/漏区，并在所述衬底上的介质层中形成有通孔，所述通孔暴露出所述源/漏区的表面；
    对所述源/漏区进行掺杂；
    对掺杂后的所述源/漏区进行预非晶化处理，以使所述源/漏区表面形成非晶层；
    使用氧化工艺处理所述源/漏区，使杂质靠近所述非晶层实现分凝；
    去除被氧化的所述非晶层；
    在所述源/漏区表面形成金属硅化物。
  2. 根据权利要求1所述的方法，其特征在于，所述对所述源/漏区进行掺杂包括：采用离子注入的方式掺杂，或者采用原位掺杂的方式对源漏进行掺杂。
  3. 根据权利要求1所述的方法，其特征在于，所述对掺杂后的所述源/漏区进行预非晶化处理，包括：向掺杂后的所述源/漏区注入Ge、Si、As中的任意一种。
  4. 根据权利要求3所述的方法，其特征在于，向掺杂后的所述源/漏区注入Ge、Si、As中的任意一种，其工艺条件为：能量0.5-3keV，剂量1×1014cm-3～1×1016cm-3。
  5. 根据权利要求1所述的方法，其特征在于，所述非晶层的厚度为6～9nm。
  6. 根据权利要求1所述的方法，其特征在于，使用氧化工艺处理所述源/漏区的温度范围在300～600℃。
  7. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    在预非晶化处理之前，对所述源/漏区进行第一热处理来激活杂质；
    或者，在使用氧化工艺处理所述源/漏区之后，对所述源/漏区进行第一热处理来激活杂质。
  8. 根据权利要求1所述的方法，其特征在于，所述在所述源/漏区表 面形成金属硅化物，包括：
    沉积金属层，所述金属层覆盖所述通孔的底部和侧壁以及所述介质层的表面；
    对所述源/漏区进行第二热处理，使所述金属层与所述源/漏区表面的材料反应形成金属硅化物。
  9. 根据权利要求8所述的方法，其特征在于，所述金属层为Ti、TiN或者Ti与TiN的组合。
  10. 根据权利要求8所述的方法，其特征在于，使用快速热退火或者激光退火对所述源/漏区进行第二热处理，温度为400～600℃，时间10～60s。
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CN112885724A (zh) * 2021-01-15 2021-06-01 中国科学院微电子研究所 一种半导体器件及其制造方法
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