WO2024105497A1 - 記憶装置 - Google Patents

記憶装置 Download PDF

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Publication number
WO2024105497A1
WO2024105497A1 PCT/IB2023/061251 IB2023061251W WO2024105497A1 WO 2024105497 A1 WO2024105497 A1 WO 2024105497A1 IB 2023061251 W IB2023061251 W IB 2023061251W WO 2024105497 A1 WO2024105497 A1 WO 2024105497A1
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WIPO (PCT)
Prior art keywords
wiring
transistor
insulator
conductor
semiconductor
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2023/061251
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English (en)
French (fr)
Japanese (ja)
Inventor
井上広樹
松嵜隆徳
楠本直人
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to KR1020257017737A priority Critical patent/KR20250109700A/ko
Priority to CN202380077250.2A priority patent/CN120167134A/zh
Priority to JP2024558476A priority patent/JPWO2024105497A1/ja
Publication of WO2024105497A1 publication Critical patent/WO2024105497A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate

Definitions

  • One aspect of the present invention relates to a transistor, a semiconductor device, a memory device, and an electronic device. Alternatively, one aspect of the present invention relates to a method for manufacturing a memory device or a semiconductor device. Alternatively, one aspect of the present invention relates to a semiconductor wafer and a module.
  • a semiconductor device refers to any device that can function by utilizing semiconductor characteristics.
  • Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic devices, and memory devices, are one embodiment of semiconductor devices.
  • Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be said to have semiconductor devices.
  • one aspect of the present invention is not limited to the above technical fields.
  • One aspect of the invention disclosed in this specification relates to an object, a method, or a manufacturing method.
  • Another aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter.
  • IC chips Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on printed wiring boards and used as one of the components of various electronic devices.
  • IC chips Semiconductor circuits
  • technology that uses semiconductor thin films to construct transistors has attracted attention.
  • These transistors have been put to practical use as electronic devices such as image display devices (also simply referred to as display devices), and it is expected that they will also be applied to the semiconductor circuits mentioned above.
  • Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials. Transistors using oxide semiconductors are known to have extremely small current flowing in the non-conducting state (off state).
  • Patent Literature 1 discloses a memory device that can retain stored contents for a long period of time by utilizing the characteristic of low leakage current of transistors that use oxide semiconductors.
  • Patent Document 2 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple overlapping memory cells.
  • Patent Document 3 discloses a vertical transistor in which the side surface of the oxide semiconductor is covered by a gate electrode via a gate insulator.
  • JP 2011-151383 A International Publication No. 2021/053473 JP 2013-211537 A
  • the memory cell disclosed in Patent Document 1 has a write transistor and a read transistor, and the read transistor changes the potential of the bit line (read line) by passing a current corresponding to the data potential held in the gate.
  • This memory cell does not require a large-volume capacitive element within the cell, as in DRAM, and it is possible to form a highly integrated storage device (memory).
  • a highly integrated storage device memory
  • one of the objectives of one embodiment of the present invention is to provide a memory device with high reliability in data reading. Another objective is to provide a memory device that can be highly integrated. Another objective is to provide a memory device with good electrical characteristics. Another objective is to provide a memory device with good reliability. Another objective is to provide a memory device with low power consumption. Another objective is to provide a new memory device. Another objective is to provide a new semiconductor device, etc.
  • One aspect of the present invention is a memory device having a memory cell, a first wiring, a second wiring, and a third wiring, the memory cell having a first transistor and a second transistor, the second transistor being provided above the first transistor, the first transistor having a first semiconductor, a first insulator, and a first conductor, the first semiconductor having a region formed on the side of a first opening penetrating the first wiring, the second insulator, and the second wiring, the first insulator having a region in contact with the first semiconductor and covering the first opening, the first conductor being provided to be in contact with the first insulator and fill the first opening, the second transistor having a second semiconductor, the second semiconductor having a region provided on the side of a second opening penetrating the third insulator and the third wiring, and the second semiconductor having a region in contact with the first conductor at the bottom of the second opening.
  • the second wiring can be provided on the second insulator, and the second insulator can be provided on the first wiring.
  • the second transistor has a fourth insulator and a second conductor, the fourth insulator has a region that contacts the second semiconductor and covers the second opening, and the second conductor can be arranged to contact the fourth insulator and fill the second opening.
  • the third wiring may be provided on a third insulator, and the third insulator may be provided on the first conductor.
  • the first wiring has a region that functions as one of the source electrode or drain electrode of the first transistor
  • the second wiring has a region that functions as the other of the source electrode or drain electrode of the first transistor
  • the third wiring has a region that functions as one of the source electrode or drain electrode of the second transistor
  • the first conductor can have a region that functions as the gate electrode of the first transistor and a region that functions as the other of the source electrode or drain electrode of the second transistor.
  • Another aspect of the present invention is a memory device having a memory cell, a first wiring, a second wiring, and a third wiring, the memory cell having a first transistor and a second transistor, the second transistor being provided above the first transistor, the first transistor having a first semiconductor, a first insulator, and a first conductor, the first semiconductor having a region formed on the side of a first opening penetrating the first wiring, the second insulator, the second wiring, and the third insulator, the first insulator having a region in contact with the first semiconductor and covering the first opening, the first conductor being provided to be in contact with the first insulator and fill the first opening, the second transistor having a second semiconductor, the second semiconductor having a region provided on the side of a second opening penetrating the fourth insulator and the third wiring, and the second semiconductor having a region in contact with the first conductor at the bottom of the second opening.
  • the third insulator can be provided on the second wiring, the second wiring can be provided on the second insulator, and the second insulator can be provided on the first wiring.
  • the second transistor has a fifth insulator and a second conductor, the fifth insulator having a region that contacts the second semiconductor and covers the second opening, and the second conductor can be arranged to contact the fifth insulator and fill the second opening.
  • the third wiring can be provided on a fourth insulator, and the fourth insulator can be provided on the first conductor.
  • the first wiring has a region that functions as one of the source electrode or drain electrode of the first transistor
  • the second wiring has a region that functions as the other of the source electrode or drain electrode of the first transistor
  • the third wiring has a region that functions as one of the source electrode or drain electrode of the second transistor
  • the first conductor can have a region that functions as the gate electrode of the first transistor and a region that functions as the other of the source electrode or drain electrode of the second transistor.
  • Another aspect of the present invention is a memory cell having a first wiring, a second wiring, a third wiring, and a fourth wiring, the memory cell having a first transistor, a second transistor, and a capacitor, the capacitor being provided between the first transistor and the second transistor, the first transistor having a first semiconductor, a first insulator, and a first conductor, the first semiconductor having a region formed on a side of a first opening penetrating the first wiring, the second insulator, and the second wiring, the first insulator having a region in contact with the first semiconductor and covering the first opening, the first conductor being in contact with the first insulator and filling the first opening.
  • the storage device is provided so as to embed the first and second conductors in the second opening
  • the capacitance element has a third insulator and a second conductor
  • the third insulator has a region formed on the side of the second opening penetrating the fourth insulator and the third wiring
  • the second conductor is provided so as to contact the third insulator and fill the second opening
  • the second conductor has a region in contact with the first conductor at the bottom of the second opening
  • the second transistor has a second semiconductor
  • the second semiconductor has a region provided on the side of the third opening penetrating the fifth insulator and the fourth wiring
  • the second semiconductor has a region in contact with the second conductor at the bottom of the third opening.
  • the second wiring can be provided on the second insulator, the second insulator can be provided on the first wiring, and the third wiring can be provided on the fourth insulator.
  • the second transistor has a sixth insulator and a third conductor, the sixth insulator having a region that contacts the second semiconductor and covers the third opening, and the third conductor can be arranged to contact the sixth insulator and fill the third opening.
  • the fourth wiring may be provided on a fifth insulator, and the fifth insulator may be provided on the second conductor.
  • the first wiring has a region that functions as one of the source electrode or drain electrode of the first transistor
  • the second wiring has a region that functions as the other of the source electrode or drain electrode of the first transistor
  • the third wiring has a region that functions as one electrode of a capacitance element
  • the fourth wiring has a region that functions as one of the source electrode or drain electrode of the second transistor
  • the first conductor has a region that functions as the gate electrode of the first transistor
  • the second conductor has a region that functions as the other electrode of the capacitance element and a region that functions as the other of the source electrode or drain electrode of the second transistor.
  • each of the first semiconductor and the second semiconductor is an oxide semiconductor, and it is preferable that the oxide semiconductor contains one or more selected from In, Ga, and Zn.
  • a memory device with high reliability in data reading can be provided.
  • a memory device that can be highly integrated can be provided.
  • a memory device having good electrical characteristics can be provided.
  • a memory device with good reliability can be provided.
  • a memory device with low power consumption can be provided.
  • a new memory device can be provided.
  • a new semiconductor device or the like can be provided.
  • FIG. 1 is a diagram illustrating a storage device.
  • 2A to 2C are circuit diagrams illustrating a memory cell.
  • FIG. 3 is a timing chart illustrating the operation of the memory cell.
  • FIG. 4 is a timing chart illustrating the operation of the memory cell.
  • FIG. 5 is a timing chart illustrating the operation of the memory cell.
  • 6A and 6B are perspective views illustrating a memory cell.
  • 7A and 7B are top views illustrating a memory cell
  • FIGS. 7C to 7E are cross-sectional views illustrating a memory cell.
  • Fig. 8A is a perspective view illustrating a memory cell
  • Fig. 8B and Fig. 8C are cross-sectional views illustrating a memory cell.
  • FIGS. 9B and 9C are cross-sectional views illustrating the memory cell.
  • Fig. 10A is a cross-sectional perspective view illustrating a memory cell
  • Fig. 10B and Fig. 10C are cross-sectional views illustrating a memory cell.
  • 11A and 11B are perspective views illustrating a memory cell.
  • Fig. 12A is a cross-sectional perspective view illustrating a memory cell
  • Fig. 12B and Fig. 12C are cross-sectional views illustrating a memory cell.
  • 13A and 13B are perspective views illustrating a memory cell.
  • 14A and 14B are diagrams illustrating a transistor.
  • 15A and 15B are diagrams illustrating an example of the configuration of a storage device.
  • 16A and 16B are diagrams illustrating an example of an electronic component.
  • 17A and 17B are diagrams for explaining an example of an electronic device
  • Fig. 17C to Fig. 17E are diagrams for explaining an example of a mainframe computer.
  • FIG. 18 is a diagram illustrating an example of space equipment.
  • FIG. 19 is a diagram illustrating an example of a storage system that can be applied to a data center.
  • an oxynitride is a material whose composition contains more oxygen than nitrogen.
  • examples of oxynitrides include silicon oxynitride, aluminum oxynitride, and hafnium oxynitride.
  • a nitride oxide is a material whose composition contains more nitrogen than oxygen. Examples of nitride oxides include silicon nitride oxide, aluminum nitride oxide, and hafnium nitride oxide.
  • the term “insulator” can be replaced with “insulating film” or “insulating layer.”
  • the term “conductor” can be replaced with “conductive film” or “conductive layer.”
  • the term “semiconductor” can be replaced with “semiconductor film” or “semiconductor layer.”
  • parallel refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes the case of -5 degrees or more and 5 degrees or less.
  • Approximately parallel refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less.
  • Perfect refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes the case of 85 degrees or more and 95 degrees or less.
  • approximately perpendicular refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
  • orthogonal refers to a state in which two straight lines cross or connect at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes the case of 85 degrees or more and 95 degrees or less. "Approximately perpendicular” or “approximately perpendicular” refers to a state in which two straight lines cross or connect at an angle of 60 degrees or more and 120 degrees or less.
  • arrows indicating the X direction, Y direction, and Z direction may be attached.
  • the "X direction” is the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated.
  • the X direction, Y direction, and Z direction are directions that intersect with each other. More specifically, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.
  • one of the X direction, Y direction, and Z direction may be called the "first direction” or "first direction”.
  • the other one may be called the “second direction” or “second direction”.
  • the remaining one may be called the "third direction” or "third direction”.
  • the memory device according to one embodiment of the present invention includes a first transistor and a second transistor in a memory cell.
  • vertical transistors are used that have a channel formation region along the side of an opening in an insulator.
  • Vertical transistors have a structure that allows for a short channel length and a long channel width, which makes it possible to increase the on-current.
  • Vertical transistors also allow for a small area to be occupied when viewed from above. Therefore, by using vertical transistors in memory cells, it is possible to form a memory device that is capable of high-speed operation and has a high degree of integration.
  • a memory cell is connected to multiple wirings, and parasitic capacitance occurs between each wiring and the data storage unit of the memory cell. Capacitive coupling due to the parasitic capacitance causes the potential of the data storage unit to fluctuate with changes in the potential of the wiring, which can impair the reliability of data reading.
  • the capacitance of the parasitic capacitance can be reduced by appropriately configuring the memory cell, thereby improving the reliability of data reading.
  • FIG. 1 is a perspective view showing a part of a memory device of one embodiment of the present invention, and illustrates a plurality of memory cells 150 (transistor 100, transistor 200).
  • Transistor 100 and transistor 200 are vertical transistors, and transistor 200 is provided above transistor 100.
  • Memory cell 150 is electrically connected to wiring 110, wiring 140, wiring 240, and wiring 210. Note that in FIG. 1, for clarity, insulators such as interlayer films are not shown, and wiring 210 located at the top is indicated by a dashed line.
  • Transistor 100 has wiring 110, wiring 140, and conductor 120 as its components.
  • Transistor 200 has conductor 120, wiring 240, and conductor 220 as its components.
  • the wiring 110 has a region that functions as one of the source electrode and the drain electrode of the transistor 100.
  • the wiring 140 has a region that functions as the other of the source electrode and the drain electrode of the transistor 100.
  • the conductor 120 has a region that functions as the gate electrode of the transistor 100 and a region that functions as one of the source electrode or drain electrode of the transistor 200. In other words, the conductor 120 has a region that shares the gate electrode of the transistor 100 and one of the source electrode or drain electrode of the transistor 200.
  • the wiring 240 has a region that functions as the other of the source electrode or drain electrode of the transistor 200.
  • the conductor 220 has a region that functions as the gate electrode of the transistor 200, and is electrically connected to the wiring 210 formed on the conductor 220. Note that the conductor 220 and the wiring 210 may be formed as the same element. Details of the configuration and connection form of each transistor will be described later.
  • FIG. 1 shows an example in which the memory cells 150 are arranged at equal intervals in the X and Y directions, the memory cells 150 may be arranged in a staggered fashion, with each memory cell 150 being shifted alternately.
  • Figure 2A is a diagram illustrating an example of a circuit diagram of a memory cell 150.
  • the transistor 100 has a function of reading data.
  • the transistor 200 has a function of writing data.
  • One of the source and drain of transistor 200 is connected to the gate of transistor 100. In FIG. 1, this connection is borne by conductor 120. Conductor 120 can also be said to be a component of node SN that holds the data potential in memory cell 150 shown in FIG. 2A.
  • the wiring 210 connected to the gate of the transistor 200 is a wiring that supplies a write word signal to the memory cell 150 and is also called a write word line (WWL).
  • the write word signal is a signal that controls the timing of writing data to the memory cell 150.
  • the wiring 240 connected to the other of the source and the drain of the transistor 200 is a wiring that applies a potential corresponding to a data signal (data) to the memory cell 150 and is also referred to as a write bit line (WBL).
  • the data signal is a signal expressed as a binary value of a high level (also referred to as "1" or VH ) or a low level (also referred to as "0" or VL ) that is written to the memory cell 150.
  • the wiring 110 connected to one of the source and drain of the transistor 100 is a wiring that supplies a read word signal to the memory cell 150, and is also called a read word line (RWL).
  • the read word signal is a signal that controls the timing of reading data from the memory cell 150.
  • the wiring 140 connected to the other of the source or drain of the transistor 100 is a wiring for reading out a potential corresponding to a data signal (data) stored in the memory cell 150, and is also called a read bit line (RBL).
  • the data can be read by inputting the potential to a sense amplifier.
  • parasitic capacitance Cp1 occurs between node SN and wiring 210.
  • Parasitic capacitance Cp2 occurs between node SN and wiring 240.
  • Parasitic capacitance Cp3 occurs between node SN and wiring 110.
  • Parasitic capacitance Cp4 occurs between node SN and wiring 140.
  • the components of each parasitic capacitance include the components of transistor 100 or transistor 200.
  • node SN Since node SN is floating, when the potential of each wiring fluctuates, one or more of the parasitic capacitances Cp1 to Cp4 are affected, and the potential of node SN also fluctuates due to capacitive coupling.
  • the range of fluctuation in the potential of node SN varies depending on the amount of fluctuation in the potential of each wiring and the electrostatic capacitance of each parasitic capacitance, but if the fluctuation in the potential of node SN is too large, transistor 100 may not operate normally and data may not be read accurately.
  • One of the countermeasures against the influence of these parasitic capacitances is to provide a capacitor 300 to which one of the source or drain of the transistor 200 and one of the gate electrodes of the transistor 100 are connected, as shown in FIG. 2C.
  • the other electrode of the capacitor 300 is connected to a wiring to which a fixed potential is supplied.
  • FIG. 3 is a timing chart for explaining an example of the operation of memory cell 150 shown in FIG. 2A.
  • FIG. 3 shows potentials applied to the wiring 210 (WWL), the wiring 240 (WBL), and the wiring 110 (RWL), a potential read out to the wiring 140 (RBL), and a potential of the node SN. Note that in FIG. 3, the standby state of the wiring 240 (WBL) is set to a low level (V L ).
  • Period T1 is a standby period.
  • Period T2 is a write period.
  • Period T3 is a standby period.
  • Periods T4 to T5 are read periods.
  • Period T6 is a standby period. Note that FIG. 3 illustrates data “1” or “0” written to memory cell 150 (node SN) via wiring 240 (WBL). Data written to memory cell 150 is data “1" when at high level and data "0" when at low level.
  • Figure 3 shows data "1” or “0” read from memory cell 150 via wiring 140 (RBL).
  • Wiring 140 (RBL) is precharged to a high-level potential (e.g., a high power supply potential such as VDD) during the read period, and data is read to an external read circuit connected to wiring 140 (RBL) according to changes in the precharged potential.
  • a high-level potential e.g., a high power supply potential such as VDD
  • the wiring 210 (WWL) is at a low level
  • the wiring 240 (WBL) is at a low level ( VL )
  • the wiring 110 (RWL) is at a high level
  • the wiring 140 (RBL) is at a high level.
  • the transistor 200 is in a non-conducting state.
  • the source and drain terminals of the transistor 100 have the same potential, so that no current flows.
  • the potential of the gate (node SN) of the transistor 100 is the potential VH or VL written in the previous write period.
  • the wiring 210 (WWL) is at a high level
  • the wiring 240 (WBL) is at a signal ( VH or VL ) corresponding to the data
  • the wiring 110 (RWL) is at a high level
  • the wiring 140 (RBL) is at a high level.
  • the transistor 200 is turned on, and the potential of the gate (node SN) of the transistor 100 becomes a potential corresponding to the data. Since the source and drain terminals of the transistor 100 are at the same potential, no current flows regardless of the gate potential.
  • the wiring 210 (WWL) is at a low level
  • the wiring 240 (WBL) is at a low level (V L )
  • the wiring 110 (RWL) is at a high level
  • the wiring 140 (RBL) is at a high level.
  • both the transistors 100 and 200 are in a non-conducting state.
  • the potential written to the gate (node SN) of the transistor 100 is held. Since the source and drain terminals of the transistor 100 have the same potential, no current flows regardless of the gate potential.
  • the wiring 210 (WWL) is at a low level
  • the wiring 240 (WBL) is at a low level (V L )
  • the wiring 110 (RWL) is at a high level.
  • the wiring 140 (RBL) is precharged to a high level (also referred to as a precharge potential V PRE ).
  • V PRE is, for example, VDD, which is equal to the high level of the wiring 140 (RBL). Since the source and drain terminals of the transistor 100 are at the same potential, no current flows regardless of the potential of the gate (node SN). In other words, the potential of the wiring 140 does not change.
  • the wiring 210 (WWL) is at a low level
  • the wiring 240 (WBL) is at a low level ( VL )
  • the wiring 110 (RWL) is at a low level.
  • the transistor 200 is in a non-conducting state.
  • the wiring 140 (RBL) is in an electrically floating state. That is, the potential fluctuates depending on the current flowing through the transistor 100 in the memory cell 150.
  • period T5 a potential difference occurs between the source and drain terminals of transistor 100, causing a current to flow according to the potential of the gate (node SN) of transistor 100.
  • the current flowing through transistor 100 is large, causing the potential of wiring 140 (RBL) to drop to a low level.
  • This change in the potential of wiring 140 (RBL) can be used to activate a sense amplifier connected to wiring 140 (RBL), allowing the data of the selected memory cell 150 to be read out to the outside.
  • the wiring 210 (WWL) is at a low level
  • the wiring 240 (WBL) is at a low level (V L )
  • the wiring 110 (RWL) is at a high level
  • the wiring 140 (RBL) is at a high level.
  • the transistor 200 is in a non-conducting state. Since the source and drain terminals of the transistor 100 have the same potential, no current flows regardless of the gate potential.
  • data can be read from the memory cells 150 in the selected row.
  • the influence of the parasitic capacitances Cp1 to Cp4 in the same operation as in FIG. 3 will be described using the timing chart shown in FIG. 4.
  • the actual capacitances of the parasitic capacitances Cp1 to Cp4 are different, but here they are treated as being approximately equal.
  • the behavior of the potential fluctuation of node SN caused by the parasitic capacitances shown in FIG. 4 is one example, and may differ slightly from the actual behavior in terms of the magnitude of the fluctuation, timing deviation, etc.
  • the node SN has a potential ("1" (V H ) or "0" (V L )) according to the data supplied to the wiring 240 (WBL).
  • the potential of the node SN decreases due to capacitive coupling caused by the parasitic capacitance Cp1 (the parasitic capacitance between the node SN and the wiring 210 (WWL)).
  • the wiring 240 (WWL) drops to a low level ( VL ), and the potential of the node SN corresponding to the data "1" is further lowered by capacitive coupling due to the parasitic capacitance Cp2 (parasitic capacitance between the node SN and the wiring 240 (WBL)).
  • the potential of the wiring 240 (WWL) does not change, and therefore the potential of the node SN does not change.
  • the potential of the wiring 140 (RBL) drops to approach the low level ( VL ), so that the potential of the node SN corresponding to the data "1” gradually drops due to capacitive coupling caused by the parasitic capacitance Cp4 (parasitic capacitance between the node SN and the wiring 140 (WBL)).
  • the potential of the wiring 140 (WWL) does not change, so the potential of the node SN does not change.
  • the potential of node SN fluctuates under the influence of the parasitic capacitances Cp1 to Cp4.
  • the potential of node SN drops under the influence of all of the parasitic capacitances Cp1 to Cp4 before the data is read, which may impair the reliability of the read data.
  • the standby state of the wiring 240 is set to a low level (V L ).
  • V H the standby state of the wiring 240
  • FIG. 5 is a timing chart when the standby state of the wiring 240 (WBL) is set to a high level (V H ).
  • the subsequent potential fluctuation of the node SN due to the parasitic capacitance is the same as that described in Fig. 4. Therefore, by setting the standby state of the wiring 240 (WBL) to a high level ( VH ), the potential fluctuation of the node SN can be reduced.
  • the parasitic capacitance that has the greatest effect on the potential fluctuation of node SN, regardless of whether data is "1" or "0" is parasitic capacitance Cp3, and it is preferable to reduce the capacitance of parasitic capacitance Cp3. Also, in order to reduce the effect when reading data "1", it is preferable to also reduce the capacitance of parasitic capacitance Cp4.
  • Fig. 6A is a perspective view illustrating a configuration example 1 of the memory cell 150.
  • an insulator such as an interlayer film is not shown, and the wiring 110, parts of the wiring 140 and wiring 240, and the wiring 210 are shown by dashed lines.
  • the memory cell 150 shown in FIG. 6A has a configuration in which a semiconductor layer (oxide semiconductor 170) is provided in an opening in the wiring 110 of the transistor 100, and the side surface of the wiring 110 in the opening is in contact with the semiconductor layer.
  • a semiconductor layer oxide semiconductor 170
  • FIG. 6A shows an example in which the width of the wiring 110 is constant in the longitudinal direction
  • the width of the wiring 110 may be wider near the opening.
  • a similar configuration can also be applied to the wiring 140 and the wiring 240.
  • Figure 7A is a top view illustrating a transistor 100
  • Figure 7B is a top view illustrating a transistor 200. Note that in the top views, some elements are omitted for clarity. The top views shown in Figures 7A and 7B are also common to other configuration examples of the memory cell 150 described in this embodiment.
  • Figure 7C is a diagram corresponding to a cross section taken along line segment A1-A2 shown in Figures 7A and 7B.
  • Figure 7D is a diagram corresponding to a cross section taken along line segment B1-B2 shown in Figures 7A and 7B.
  • Memory cell 150 has an insulator 160 on a substrate (not shown), a transistor 100 provided on insulator 160, and a transistor 200 provided on transistor 100. Note that insulator 180, insulator 185, insulator 280, insulator 285, etc., which function as interlayer films, can be provided between transistors and between various wirings.
  • the transistor 100 has an oxide semiconductor 170, an insulator 130, and a conductor 120.
  • the oxide semiconductor 170 functions as a semiconductor layer
  • the insulator 130 functions as a gate insulator
  • the conductor 120 functions as a gate electrode.
  • the wiring 110 has a region that functions as one of the source electrode and the drain electrode of the transistor 100.
  • the wiring 140 has a region that functions as the other of the source electrode and the drain electrode of the transistor 100.
  • An opening 190 is provided through the wiring 140, the insulator 180, and the wiring 110, reaching the insulator 160.
  • the opening 190 has a columnar shape with a roughly circular upper surface. This configuration allows for miniaturization or high integration of memory cells. Note that the side of the opening 190 is preferably perpendicular to the upper surface of the insulator 160.
  • the oxide semiconductor 170 is disposed in the opening 190.
  • the oxide semiconductor 170 has a region in contact with the side surface of the wiring 110, a region in contact with the side surface of the wiring 140, a region in contact with the top surface of the insulator 160, and a region in contact with the side surface of the insulator 180.
  • the insulator 130 is arranged so that at least a portion of it covers the opening 190.
  • the conductor 120 is arranged so that at least a portion of it is located in the opening 190. It is preferable that the conductor 120 is provided so as to fill the opening 190, and the top surface shape is preferably roughly circular to increase the degree of integration.
  • the electrostatic capacitance of the parasitic capacitance Cp3 between the conductor 120 (node SN) and the wiring 110 can be reduced.
  • the oxide semiconductor 170 acts as one or both of the dielectric and the other electrode.
  • the dielectric thickness d is small, and the parasitic capacitance Cp3b has a relatively large capacitance.
  • the parasitic capacitance Cp3b is part of the parasitic capacitance Cp3, and the capacitance of the parasitic capacitance Cp3 can be reduced by configuring the parasitic capacitance Cp3b so that it is not formed.
  • the region of the oxide semiconductor 170 facing the bottom surface of the conductor 120 is not in contact with an element that becomes n-type (such as the wiring 110), and therefore has i-type (intrinsic) conductivity and high resistance. Therefore, it can be said that the region of the oxide semiconductor 170 facing the bottom surface of the conductor 120 is unlikely to become an element of parasitic capacitance (the other electrode).
  • the transistor 200 has an oxide semiconductor 270, an insulator 230, and a conductor 220.
  • the oxide semiconductor 270 functions as a semiconductor layer
  • the insulator 230 functions as a gate insulator
  • the conductor 220 functions as a gate electrode.
  • the conductor 120 has a region that functions as one of the source electrode and the drain electrode of the transistor 200.
  • the wiring 240 has a region that functions as the other of the source electrode and the drain electrode of the transistor 200.
  • An opening 290 is provided through the wiring 240 and the insulator 280, reaching the conductor 120.
  • the opening 290 has a columnar shape with a roughly circular upper surface. This configuration allows for miniaturization or high integration of memory cells. Note that the side of the opening 290 is preferably perpendicular to the upper surface of the conductor 120.
  • the oxide semiconductor 270 is disposed in the opening 290. Note that the oxide semiconductor 270 has a region in contact with the top surface of the conductor 120 in the opening 290, a region in contact with the side surface of the wiring 240, and a region in contact with the side surface of the insulator 280.
  • the insulator 230 is arranged so that at least a portion of it covers the opening 290.
  • the conductor 220 is arranged so that at least a portion of it is located in the opening 290. It is preferable that the conductor 220 is provided so as to fill the opening 290, and it is preferable that the top surface shape is roughly circular to increase the degree of integration.
  • the wiring 210 is arranged on the conductor 220. It is also possible that the conductor 220 and the wiring 210 are formed as the same element.
  • the diameter of the opening 190 and the diameter of the opening 290 are preferably approximately the same, and the opening 190 and the opening 290 are preferably provided so as to overlap.
  • the width of the wiring 110 and the width of the wiring 210 are preferably approximately the same, and the wiring 110 and the wiring 210 are preferably provided so as to overlap.
  • the width of the wiring 140 and the width of the wiring 240 are preferably approximately the same, and the wiring 140 and the wiring 240 are preferably provided so as to overlap.
  • two transistors can be provided without significantly increasing the cell area, so the memory cells 150 can be arranged at a high density, and the memory capacity of the memory device can be increased. In other words, the memory device can be highly integrated.
  • one of the source electrode or drain electrode of transistor 200 and the gate electrode of transistor 100 are shared, that is, transistor 200 and transistor 100 are directly connected without an intervening wiring. Therefore, the electrical resistance between the two can be minimized, and data can be written quickly.
  • Fig. 8A is a perspective view illustrating the configuration example 2 of the memory cell 150.
  • an insulator such as an interlayer film is not shown, and the wiring 110, parts of the wiring 140 and wiring 240, and the wiring 210 are shown by dashed lines.
  • Figure 8B is a diagram corresponding to a cross section taken along line segment A1-A2 shown in Figures 7A and 7B.
  • Figure 8C is a diagram corresponding to a cross section taken along line segment B1-B2 shown in Figures 7A and 7B. Note that a description of each element common to configuration example 1 will be omitted.
  • Configuration example 2 is a configuration in which an opening 190 is formed in the wiring 110, similar to configuration example 1, and further reduces the electrostatic capacitance of the parasitic capacitance generated between the upper part of the conductor 120 and the wiring 110.
  • the conductor 120 is formed to fill the opening 190, it is preferable that the diameter of the upper part of the conductor 120 is larger than the diameter of the opening 190. In addition, because the conductor 120 also functions as one of the source electrode or drain electrode of the transistor 200, it is preferable that the area in contact with the oxide semiconductor 270 is large. In other words, it is preferable that the diameter of the upper part of the conductor 120 is larger than the diameter of the opening 290.
  • the upper part of the conductor 120 is one of the elements that increases the electrostatic capacitance of the parasitic capacitance generated between the conductor 120 and other wiring.
  • the transistor 100 is configured to have a thicker insulator 180 and a larger depth of the opening 190.
  • opening 190 and opening 290 are approximately equal in size, but in configuration example 2, opening 190 has a greater depth than opening 290. Increasing the depth of opening 190 is equivalent to a longer channel length in a vertical transistor, and is therefore effective when the on-current characteristics of transistor 100 are sufficiently high.
  • the distance between the wiring 110 and the top of the conductor 120 can be physically increased, and the capacitance of the parasitic capacitance Cp3 formed between the wiring 110 and the conductor 120 (node SN) can be reduced by using the insulator 180 or the like as a dielectric.
  • capacitance C ⁇ x S/d, this is equivalent to increasing the value of the thickness d of the dielectric to reduce C.
  • Fig. 9A is a perspective view illustrating the configuration example 3 of the memory cell 150.
  • an insulator such as an interlayer film is not shown, and the wiring 140 and a part of the wiring 240, as well as the wiring 210 are shown by dashed lines.
  • Figure 9B is a diagram corresponding to a cross section taken along line segment A1-A2 shown in Figures 7A and 7B.
  • Figure 9C is a diagram corresponding to a cross section taken along line segment B1-B2 shown in Figures 7A and 7B. Note that a description of each element common to configuration example 1 will be omitted.
  • Configuration example 3 like configuration example 1, has a configuration in which an opening 190 is formed in the wiring 110, and the depth of the opening 190 is increased by providing an insulator 181, and further, the electrostatic capacitance of the parasitic capacitance generated between the upper part of the conductor 120 and the wiring 140 is reduced.
  • the insulator 181 is formed on the wiring 140, and the opening 190 is formed to penetrate the insulator 181, the wiring 140, the insulator 180, and the wiring 110, and reach the insulator 160.
  • the distance between the wiring 110 and the top of the conductor 120, and the distance between the wiring 110 and the wiring 140 are greatly affected by the thickness of the insulator 180. Therefore, if the distance between the wiring 110 and the top of the conductor 120 is increased, the distance between the wiring 110 (one of the source electrode or drain electrode) and the wiring 140 (the other of the source electrode or drain electrode) also increases.
  • This configuration corresponds to a longer channel length in a vertical transistor. If the channel length is longer, the current value will be smaller, which may reduce the degree of freedom in circuit design.
  • the channel length can be adjusted by the thickness of the insulator 180.
  • the distance between the wiring 110 and the top of the conductor 120 can be adjusted by adjusting the thickness of the insulator 180 and the thickness of the insulator 181. This increases the degree of freedom in circuit design.
  • Fig. 10A is a cross-sectional perspective view illustrating the fourth configuration example of the memory cell 150.
  • an insulator such as an interlayer film is not shown, and the wiring 210 is shown by a dashed line.
  • the capacitance element 300 is cut in the Z direction to show the cross section.
  • Figure 10B is a diagram corresponding to a cross section taken along line A1-A2 in Figures 7A and 7B.
  • Figure 10C is a diagram corresponding to a cross section taken along line B1-B2 in Figures 7A and 7B.
  • the division position of the capacitance element 300 shown in Figure 10A is indicated by a dashed line. Note that a description of each element common to configuration example 1 will be omitted.
  • Configuration example 4 is a configuration in which, in addition to the configuration of configuration example 1, a capacitive element 300 is provided between transistor 100 and transistor 200. This configuration can be applied to memory cell 150 in the circuit diagram shown in FIG. 2C.
  • the capacitor element 300 has a conductor 320, an insulator 330, and a wiring 310.
  • the conductor 320 functions as one electrode
  • the insulator 330 functions as a dielectric
  • the wiring 310 functions as the other electrode.
  • An insulator 380 is provided on the transistor 100, and the wiring 310 is provided on the insulator 380.
  • An opening 390 is provided through the wiring 310 and the insulator 380, and the insulator 330 is provided to cover the opening 390.
  • an opening is provided in the insulator 330 that reaches the conductor 120.
  • the conductor 320 is provided to fill the opening 390, and is in contact with the conductor 120 at the bottom of the opening 390.
  • an insulator 385 that functions as an interlayer film is provided on the insulator 330.
  • the transistor 200 is provided on the insulator 385 and the conductor 320.
  • the oxide semiconductor 270 of the transistor 200 has a region in contact with the conductor 320 at the bottom of the opening 290. That is, it can be said that the conductor 320 also has a region that functions as one of the source electrode or drain electrode of the transistor 200. It can also be said that the conductor 320 has a function of wiring that connects one of the source electrode or drain electrode of the transistor 200 to the gate electrode (conductor 120) of the transistor 100.
  • the capacitance element 300 By providing the capacitance element 300, the capacitance of the node SN is increased, so that the potential fluctuation due to the capacitive coupling of each parasitic capacitance can be suppressed to a small value. Therefore, the reliability of the read data can be improved.
  • Figs. 10A to 10C show a configuration in which the capacitive element 300 is added to the configuration example 1, as shown in the perspective view of Fig. 11A, a configuration in which the capacitive element 300 is added to the configuration example 2 may also be used. Also, as shown in the perspective view of Fig. 11B, a configuration in which the capacitive element 300 is added to the configuration example 3 may also be used.
  • Fig. 12A is a perspective view for explaining the configuration example 5 of the memory cell 150.
  • an insulator such as an interlayer film is not shown, and the wiring 210 is shown by a dashed line.
  • the capacitance element 300 is cut in the Z direction to show a cross section.
  • Figure 12B is a diagram corresponding to a cross section taken along line A1-A2 in Figures 7A and 7B.
  • Figure 12C is a diagram corresponding to a cross section taken along line B1-B2 in Figures 7A and 7B.
  • the division position of the capacitance element 300 shown in Figure 12A is indicated by a dashed line. Note that a description of each element common to configuration example 1 and configuration example 4 will be omitted.
  • Configuration example 5 is an example in which a capacitive element 300 having a different configuration from configuration example 4 is provided.
  • the insulator 380, the wiring 310, the opening 390, and the insulator 330 have the same configuration as configuration example 4, and the conductor 320 is formed so as to cover the wiring 310 and the opening 390.
  • a capacitance can be formed outside the opening 390 with the wiring 310 as one electrode, the insulator 330 as the dielectric, and the conductor 320 as the other electrode.
  • the capacitance C ⁇ ⁇ S/d, this is equivalent to increasing the value of the electrode area S to increase C.
  • Figs. 12A to 12C show a configuration in which the capacitive element 300 is added to configuration example 1, as shown in the perspective view of Fig. 13A, a configuration in which the capacitive element 300 is added to configuration example 2 may also be used. Also, as shown in the perspective view of Fig. 13B, a configuration in which the capacitive element 300 is added to configuration example 3 may also be used.
  • transistors 100, 200 Next, details of the transistors 100 and 200 will be described. As described above, the transistors 100 and 200 differ from each other in terms of the wiring connection configuration, but the parts related to the operation can be regarded as basically having the same structure, and therefore the transistor 200 will be described here.
  • the transistor 200 can have a configuration including a conductor 120, a wiring 240 on an insulator 280, an oxide semiconductor 270 provided in contact with the upper surface of the conductor 120 exposed in the opening 290, the side surface of the insulator 280 in the opening 290, the side surface of the wiring 240 in the opening 290, and at least a portion of the upper surface of the wiring 240, an insulator 230 provided in contact with the upper surface of the oxide semiconductor 270, and a conductor 220 provided in contact with the upper surface of the insulator 230.
  • the bottom of the opening 290 is also the top surface of the conductor 120
  • the side of the opening 290 is also the side of the insulator 280 and the side of the wiring 240.
  • the opening 290 has a columnar shape with a roughly circular upper surface. This configuration allows for miniaturization or high integration of the memory device. It is preferable that the side of the opening 290 is perpendicular to the upper surface of the wiring 110.
  • the top surface shape of opening 290 and the top surface shape of opening 190 in which transistor 100 is formed are the same or similar.
  • the portions of the oxide semiconductor 270, the insulator 230, and the conductor 220 that are to be placed in the opening 290 are provided to reflect the shape of the opening 290.
  • the oxide semiconductor 270 is provided to cover the bottom and side surfaces of the opening 290
  • the insulator 230 is provided to cover the oxide semiconductor 270
  • the conductor 220 is provided to fill the recess in the insulator 230 that reflects the shape of the opening 290.
  • the opening 290 and the conductor 220 are roughly circular when viewed from above, but the present invention is not limited to this.
  • the opening 290 and the conductor 220 may be elliptical, polygonal such as a rectangle, or polygonal such as a rectangle with rounded corners when viewed from above.
  • the maximum width of the opening 290 may be calculated appropriately according to the shape of the opening 290 when viewed from above.
  • the maximum width of the conductor 220 may be calculated appropriately according to the shape of the conductor 220 when viewed from above.
  • the maximum width of the opening 290 may be the length of the diagonal of the rectangle.
  • the maximum width of the conductor 220 may be the length of the diagonal of the rectangle.
  • the maximum width of the opening 290 and the conductor 220 may be the diameter of the smallest circle (also called the minimum encompassing circle) that encompasses the shape of the opening 290 in top view.
  • opening 290 can also be applied to opening 190.
  • shape of conductor 220 can also be applied to conductor 120.
  • FIG. 14A shows an enlarged view of the oxide semiconductor 270 and its vicinity in FIG. 7C and FIG. 7D.
  • FIG. 14B shows a cross-sectional view in the XY plane including the wiring 240.
  • the oxide semiconductor 270 has a region 270i and regions 270na and 270nb arranged to sandwich the region 270i.
  • Region 270na is a region of oxide semiconductor 270 that is in contact with conductor 120. At least a portion of region 270na functions as one of the source region and drain region of transistor 200.
  • Region 270nb is a region of oxide semiconductor 270 that is in contact with wiring 240. At least a portion of region 270nb functions as the other of the source region and drain region of transistor 200.
  • wiring 240 is in contact with the entire outer periphery of oxide semiconductor 270.
  • the other of the source region and drain region of transistor 200 can be formed on the entire outer periphery of a portion of oxide semiconductor 270 that is formed in the same layer as wiring 240.
  • Region 270i is a region in the oxide semiconductor 270 that is sandwiched between regions 270na and 270nb. At least a part of region 270i functions as a channel formation region of the transistor 200. That is, the channel formation region of the transistor 200 is formed in a part of the oxide semiconductor 270 that is located in a region between the conductor 120 and the wiring 240. It can also be said that the channel formation region of the transistor 200 is located in a region of the oxide semiconductor 270 that is in contact with the insulator 280 or in a region in the vicinity of the insulator 280.
  • the channel length of the transistor 200 is the distance between the source region and the drain region. In other words, it can be said that the channel length of the transistor 200 is determined by the thickness of the insulator 280 on the conductor 120.
  • the channel length L of the transistor 200 is indicated by a dashed double-headed arrow. In a cross-sectional view, the channel length L is the distance between the end of the region where the oxide semiconductor 270 and the conductor 120 contact each other and the end of the region where the oxide semiconductor 270 and the wiring 240 contact each other. In other words, the channel length L corresponds to the length of the side surface of the insulator 280 on the opening 290 side in a cross-sectional view.
  • the channel length is set by the exposure limit of photolithography, but in the present invention, the channel length can be set by the film thickness of the insulator 280. Therefore, the channel length of the transistor 200 can be made into a very fine structure below the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more, or 5 nm or more). This increases the on-current of the transistor 200, and improves the frequency characteristics. Therefore, a memory device with high operating speed can be provided.
  • the exposure limit of photolithography for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more, or 5 nm or more.
  • a channel formation region, a source region, and a drain region can be formed in the opening 290. This allows the area occupied by the transistor 200 to be reduced compared to conventional transistors in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. This allows the memory device to be highly integrated, thereby increasing the memory capacity per unit area.
  • a transistor having a channel formation region along the side of the insulator 280 in the opening 290 is also called a vertical transistor.
  • the oxide semiconductor 270, the insulator 230, and the conductor 220 are arranged concentrically in the XY plane including the channel formation region of the oxide semiconductor 270. Therefore, the side surface of the conductor 220 arranged at the center faces the side surface of the oxide semiconductor 270 through the insulator 230. That is, in the top view, the entire circumference of the oxide semiconductor 270 becomes the channel formation region.
  • the channel width of the transistor 200 is determined by the outer periphery length of the oxide semiconductor 270. That is, it can be said that the channel width of the transistor 200 is determined by the maximum width of the opening 290 (maximum diameter when the opening 290 is circular in the top view). In FIGS.
  • the maximum width D of the opening 290 is indicated by a double-headed arrow of a two-dot chain line.
  • the channel width W of the transistor 200 is indicated by a double-dot chain line of a one-dot chain line.
  • the maximum width D of the opening 290 is set by the exposure limit of photolithography.
  • the maximum width D of the opening 290 is set by the film thickness of each of the oxide semiconductor 270, the insulator 230, and the conductor 220 provided in the opening 290.
  • the maximum width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. Note that when the opening 290 is circular in top view, the maximum width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D x ⁇ ".
  • the channel length L of the transistor 200 is preferably at least smaller than the channel width W of the transistor 200.
  • the channel length L of the transistor 200 of one embodiment of the present invention is 0.1 to 0.99 times, preferably 0.5 to 0.8 times, the channel width W of the transistor 200.
  • the oxide semiconductor 270, the insulator 230, and the conductor 220 are arranged concentrically. This makes the distance between the conductor 220 and the oxide semiconductor 270 roughly uniform, so that a gate electric field can be applied roughly uniformly to the oxide semiconductor 270.
  • the channel formation region of a transistor using an oxide semiconductor for the semiconductor layer has fewer oxygen vacancies or a lower concentration of impurities such as hydrogen, nitrogen, and metal elements than the source and drain regions.
  • impurities such as hydrogen, nitrogen, and metal elements
  • VOH defects in which hydrogen enters the oxygen vacancies and generate electrons that serve as carriers
  • VOH is also reduced in the channel formation region.
  • the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, it can be said that the channel formation region of the transistor is i-type (intrinsic) or substantially i-type.
  • the source and drain regions of a transistor that uses an oxide semiconductor for its semiconductor layer have more oxygen vacancies, more VOH , or a higher concentration of impurities such as hydrogen, nitrogen, or metal elements than the channel formation region, and thus have an increased carrier concentration and low resistance.
  • the source and drain regions of the transistor are n-type regions that have a higher carrier concentration and lower resistance than the channel formation region.
  • the opening 290 is provided so that the side of the opening 290 is perpendicular to the top surface of the wiring 110, but the present invention is not limited to this.
  • the side of the opening 290 may be tapered.
  • the band gap of the metal oxide used as the oxide semiconductor 270 is preferably 2 eV or more, more preferably 2.5 eV or more.
  • the frequency of the refresh operation can be about once per 10 sec, which is 10 times or more or 100 times or more. Note that in the memory device of one embodiment of the present invention, the frequency of the refresh operation can be set to once per 1 sec to 100 sec, preferably once per 5 sec to 50 sec.
  • oxide semiconductor 270 can be a single layer or a stack of metal oxides described in the [Metal Oxide] section below.
  • the composition in the vicinity includes a range of ⁇ 30% of the desired atomic ratio. It is also preferable to use gallium as the element M.
  • the above atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of the sputtering target used to form the metal oxide film.
  • energy dispersive X-ray spectrometry EDX
  • XPS X-ray photoelectron spectrometry
  • ICP-MS inductively coupled plasma mass spectrometry
  • ICP-AES inductively coupled plasma-atomic emission spectrometry
  • EDX energy dispersive X-ray spectrometry
  • XPS X-ray photoelectron spectrometry
  • ICP-MS inductively coupled plasma mass spectrometry
  • ICP-AES inductively coupled plasma-atomic emission spectrometry
  • the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.
  • the metal oxide can be formed preferably by sputtering or atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • the composition of the formed metal oxide may differ from the composition of the sputtering target.
  • the zinc content in the formed metal oxide may decrease to about 50% compared to the sputtering target.
  • the oxide semiconductor 270 preferably has crystallinity.
  • oxide semiconductors having crystallinity include CAAC-OS (c-axis aligned crystalline oxide semiconductor), nc-OS (nanocrystalline oxide semiconductor), polycrystalline oxide semiconductor, single crystal oxide semiconductor, and the like. It is preferable to use CAAC-OS or nc-OS as the oxide semiconductor 270, and it is particularly preferable to use CAAC-OS.
  • the CAAC-OS preferably has multiple layered crystal regions with the c-axis oriented in the normal direction to the surface on which it is formed.
  • the oxide semiconductor 270 preferably has layered crystals that are approximately parallel to the side surface of the opening 290, particularly to the side surface of the insulator 280. With this structure, the layered crystals of the oxide semiconductor 270 are formed approximately parallel to the channel length direction of the transistor 200, thereby increasing the on-state current of the transistor.
  • CAAC-OS is a metal oxide that has a highly crystalline and dense structure and has few impurities and defects (e.g., oxygen vacancies).
  • a temperature e.g. 400° C. or higher and 600° C. or lower
  • the CAAC-OS can be made to have a more crystalline and dense structure. In this way, the density of the CAAC-OS can be further increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.
  • the oxide semiconductor 270 by using a crystalline oxide such as CAAC-OS as the oxide semiconductor 270, it is possible to suppress the extraction of oxygen from the oxide semiconductor 270 by the source electrode or the drain electrode. As a result, even when heat treatment is performed, oxygen can be suppressed from being extracted from the oxide semiconductor 270, and the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.
  • a crystalline oxide such as CAAC-OS
  • the crystallinity of the oxide semiconductor 270 can be analyzed, for example, by an X-ray diffraction (XRD) pattern, a transmission electron microscope (TEM) image, or an electron diffraction (ED) pattern. Alternatively, the analysis may be performed by combining a plurality of these methods.
  • XRD X-ray diffraction
  • TEM transmission electron microscope
  • ED electron diffraction
  • oxide semiconductor 270 is shown as a single layer in Figures 7C, 7D, etc., the present invention is not limited to this.
  • the oxide semiconductor 270 may have a laminated structure of multiple oxide layers with different chemical compositions. For example, it may have a structure in which multiple types selected from the above metal oxides are appropriately laminated.
  • the insulators described in the [Insulator] section below can be used in a single layer or a multilayer.
  • silicon oxide or silicon oxynitride can be used as the insulator 230. Silicon oxide and silicon oxynitride are preferred because they are stable against heat.
  • the insulator 230 may be a material with a high relative dielectric constant, so-called high-k material, as described in the [Insulator] section below.
  • high-k material such as hafnium oxide or aluminum oxide may be used.
  • the film thickness of the insulator 230 is preferably 0.5 nm or more and 15 nm or less, more preferably 0.5 nm or more and 12 nm or less, and even more preferably 0.5 nm or more and 10 nm or less. It is sufficient that the insulator 230 has a region with the above film thickness in at least a portion.
  • the concentration of impurities such as water and hydrogen in the insulator 230 is reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor 270.
  • a portion of the insulator 230 is located outside the opening 290, i.e., above the wiring 240 and the insulator 280. At this time, it is preferable that the insulator 230 covers the side end of the oxide semiconductor 270. This can prevent the conductor 220 and the oxide semiconductor 270 from shorting out. It is also preferable that the insulator 230 covers the side end of the wiring 240. This can prevent the conductor 220 and the wiring 240 from shorting out.
  • the insulator 230 is shown as a single layer in Figures 7C and 7D, the present invention is not limited to this.
  • the insulator 230 may have a laminated structure.
  • the conductor 220 may be a single layer or a multilayer of the conductors described in the section [Conductor] below.
  • the conductor 220 may be a highly conductive material such as tungsten.
  • a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen as the conductor 220.
  • conductive materials include conductive materials that contain nitrogen (e.g., titanium nitride or tantalum nitride) and conductive materials that contain oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductor 220.
  • conductor 220 is shown as a single layer in Figures 7C and 7D, the present invention is not limited to this.
  • the conductor 220 may have a multilayer structure.
  • the wiring 240 can be made of a conductor, as described below in the section on conductors, in a single layer or multilayer.
  • the wiring 240 can be made of a highly conductive material, such as tungsten.
  • the wiring 240 is preferably made of a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen.
  • a conductive material that is difficult to oxidize For example, titanium nitride or tantalum nitride can be used. With this structure, excessive oxidation of the wiring 240 by the oxide semiconductor 270 can be suppressed.
  • a structure in which tungsten is laminated on titanium nitride may be used.
  • the conductivity of the wiring 240 can be improved.
  • the first conductor may be formed using a conductive material with high conductivity
  • the second conductor may be formed using a conductive material containing oxygen.
  • a conductive material containing oxygen as the second conductor of the wiring 240 that contacts the insulator 230, it is possible to suppress the diffusion of oxygen in the insulator 230 to the first conductor of the wiring 240.
  • the oxide semiconductor 270 comes into contact with the conductor 120, a metal compound or oxygen vacancy is formed, and the resistance of the region 270na of the oxide semiconductor 270 is reduced.
  • the contact resistance between the oxide semiconductor 270 and the conductor 120 is reduced.
  • the resistance of the region 270nb of the oxide semiconductor 270 is reduced. Therefore, the contact resistance between the oxide semiconductor 270 and the wiring 240 can be reduced.
  • the insulator 280 functions as an interlayer film, it is preferable that it has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the electrostatic capacitance of the parasitic capacitance occurring between wirings can be reduced.
  • an insulator containing a material with a low dielectric constant as described in the [Insulator] section below, can be used in a single layer or a multilayer configuration. Silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • the concentration of impurities such as water and hydrogen in the insulator 280 is reduced. This can suppress the intrusion of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor 270.
  • An insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is preferably used as the insulator 280.
  • excess oxygen an insulator containing oxygen that is released by heating
  • oxygen can be supplied from the insulator 280 to the channel formation region of the oxide semiconductor 270, thereby reducing oxygen vacancies and VOH .
  • the electrical characteristics of the transistor 200 can be stabilized and reliability can be improved.
  • an insulator having a function of capturing or fixing hydrogen as described in the section [Insulator] below, may be used. With such a structure, hydrogen in the oxide semiconductor 270 can be captured or fixed, and the hydrogen concentration in the oxide semiconductor 270 can be reduced.
  • the insulator 280 magnesium oxide, aluminum oxide, or the like can be used.
  • Insulator 280 is shown as a single layer in Figures 7C and 7D, but the present invention is not limited to this. Insulator 280 may have a laminated structure.
  • the substrate on which the transistor 100 and the transistor 200 are formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate.
  • the insulating substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria-stabilized zirconia substrate), and a resin substrate.
  • the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide.
  • Examples of the semiconductor substrate include a semiconductor substrate having an insulating region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate.
  • Examples of the conductive substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • Examples of the conductive substrate include a substrate having a metal nitride and a substrate having a metal oxide.
  • Examples of the conductive substrate include a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate.
  • a substrate provided with elements may be used.
  • the elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.
  • Insulator examples include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, each of which has insulating properties.
  • Examples of materials with a high dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.
  • materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic.
  • inorganic insulating materials with a low relative dielectric constant include silicon oxide with added fluorine, silicon oxide with added carbon, and silicon oxide with added carbon and nitrogen. Another example is silicon oxide with vacancies. These silicon oxides may contain nitrogen.
  • the electrical characteristics of a transistor using a metal oxide can be stabilized by surrounding the transistor with an insulator that has a function of suppressing the permeation of impurities and oxygen.
  • an insulator that has a function of suppressing the permeation of impurities and oxygen for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or a stacked layer.
  • metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide
  • metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.
  • Insulators in contact with a semiconductor such as a gate insulator, or insulators provided near a semiconductor layer are preferably insulators having a region containing excess oxygen.
  • insulators having a region containing excess oxygen in contact with a semiconductor layer or in the vicinity of the semiconductor layer, oxygen vacancies in the semiconductor layer can be reduced.
  • Examples of insulators that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide with vacancies.
  • Insulators that have a barrier property against oxygen include oxides containing either or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.
  • oxides containing either or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).
  • Insulators that have barrier properties against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.
  • An insulator that has a barrier property against oxygen and an insulator that has a barrier property against hydrogen can be said to have a barrier property against either or both of oxygen and hydrogen.
  • Insulators having the function of capturing or fixing hydrogen include oxides containing magnesium, or oxides containing one or both of aluminum and hafnium. It is more preferable that these oxides have an amorphous structure. In oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. It is preferable that these metal oxides have an amorphous structure, but crystalline regions may be formed in some parts.
  • a barrier insulating film refers to an insulating film having a barrier property.
  • the barrier property refers to a property that a corresponding substance is difficult to diffuse (also referred to as a property that a corresponding substance is difficult to permeate, a property that the permeability of a corresponding substance is low, or a function of suppressing the diffusion of a corresponding substance).
  • the function of capturing or fixing a corresponding substance can be rephrased as a barrier property.
  • hydrogen when described as a corresponding substance refers to at least one of, for example, a hydrogen atom, a hydrogen molecule, and a substance bonded to hydrogen such as a water molecule and OH ⁇ .
  • impurities when described as a corresponding substance refer to impurities in a channel formation region or a semiconductor layer unless otherwise specified, and refer to at least one of, for example, a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N 2 O, NO, NO 2 , etc.), a copper atom, etc.
  • oxygen when described as a corresponding substance refers to at least one of, for example, an oxygen atom, an oxygen molecule, etc.
  • the barrier property against oxygen refers to a property that at least one of an oxygen atom, an oxygen molecule, etc. is difficult to diffuse.
  • the conductor it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements.
  • a nitride of the alloy or an oxide of the alloy may be used as the alloy containing the above-mentioned metal elements as a component.
  • tantalum nitride titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc.
  • a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • conductive materials containing nitrogen such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum
  • conductive materials containing oxygen such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel
  • materials containing metal elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are difficult to oxidize, conductive materials that have a function of suppressing the diffusion of oxygen, or materials that maintain conductivity even when oxygen is absorbed.
  • examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide to which silicon has been added, indium zinc oxide, and indium zinc oxide containing tungsten oxide.
  • a conductive film formed using a conductive material containing oxygen may be called an oxide conductive film.
  • conductive materials primarily composed of tungsten, copper, or aluminum are preferred because they have high conductivity.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.
  • a metal oxide is used for the channel formation region of a transistor, it is preferable to use a layered structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined for the conductor that functions as the gate electrode. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.
  • a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as a conductor functioning as a gate electrode may also be used.
  • a conductive material containing the above-mentioned metal element and nitrogen may also be used.
  • a conductive material containing nitrogen such as titanium nitride or tantalum nitride, may be used.
  • Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon may also be used.
  • Indium gallium zinc oxide containing nitrogen may also be used.
  • Metal oxides may have lattice defects.
  • Lattice defects include point defects such as atomic vacancies and heteroatoms, line defects such as dislocations, surface defects such as grain boundaries, and volume defects such as voids.
  • Factors that cause lattice defects include a deviation in the ratio of the number of atoms of the constituent elements (an excess or deficiency of constituent atoms) and impurities.
  • the metal oxide used in the semiconductor layer of a transistor When a metal oxide is used in the semiconductor layer of a transistor, lattice defects in the metal oxide can cause carrier generation or capture. Therefore, if a metal oxide with many lattice defects is used in the semiconductor layer of a transistor, the electrical characteristics of the transistor may become unstable. Therefore, it is preferable that the metal oxide used in the semiconductor layer of a transistor has few lattice defects.
  • V O H oxygen vacancies
  • the transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region in the metal oxide. In other words, it is preferable that the carrier concentration of the channel formation region in the metal oxide is reduced and the channel formation region in the metal oxide is made i-type (intrinsic) or substantially i-type.
  • the types of lattice defects likely to exist in metal oxides and the amount of lattice defects present vary depending on the structure of the metal oxide or the method of forming the metal oxide film.
  • Non-single crystal structures include, for example, CAAC structures, polycrystalline structures, nc structures, pseudo-amorphous (a-like) structures, and amorphous structures.
  • A-like structures have a structure between the nc structures and the amorphous structures. The classification of crystal structures will be described later.
  • metal oxides having an a-like structure and metal oxides having an amorphous structure have voids or low-density regions. That is, metal oxides having an a-like structure and metal oxides having an amorphous structure have lower crystallinity than metal oxides having an nc structure and metal oxides having a CAAC structure. In addition, metal oxides having an a-like structure have a higher hydrogen concentration in the metal oxide than metal oxides having an nc structure and metal oxides having a CAAC structure. Therefore, lattice defects are easily generated in metal oxides having an a-like structure and metal oxides having an amorphous structure.
  • a metal oxide with high crystallinity for the semiconductor layer of the transistor.
  • a metal oxide having a CAAC structure or a metal oxide having a single crystal structure By using such a metal oxide for the transistor, a transistor with good electrical characteristics can be realized. In addition, a highly reliable transistor can be realized.
  • a metal oxide for the channel formation region of a transistor, which increases the on-state current of the transistor.
  • the crystal has a crystal structure in which multiple layers (e.g., a first layer, a second layer, and a third layer) are stacked. That is, the crystal has a layered crystal structure (also called a layered crystal or layered structure). In this case, the c-axis of the crystal is oriented in the direction in which the multiple layers are stacked.
  • metal oxides having the crystal include single crystal oxide semiconductors and CAAC-OS.
  • the c-axis of the crystal in the normal direction to the surface on which the metal oxide is formed or the film surface. This allows the multiple layers to be arranged parallel or approximately parallel to the surface on which the metal oxide is formed or the film surface. In other words, the multiple layers extend in the channel length direction.
  • the above three-layered crystal structure has the following structure.
  • the first layer has an atomic coordination structure of an oxygen octahedron with the metal of the first layer at the center.
  • the second layer has an atomic coordination structure of an oxygen trigonal bipyramid or tetrahedron with the metal of the second layer at the center.
  • the third layer has an atomic coordination structure of an oxygen trigonal bipyramid or tetrahedron with the metal of the third layer at the center.
  • the crystal structure of the above crystals includes, for example, a YbFe 2 O 4 type structure, a Yb 2 Fe 3 O 7 type structure, and modified structures thereof.
  • each of the first layer to the third layer is preferably composed of one metal element or multiple metal elements having the same valence, and oxygen.
  • the valence of the one or multiple metal elements constituting the first layer is preferably the same as the valence of the one or multiple metal elements constituting the second layer.
  • the first layer and the second layer may have the same metal element.
  • the valence of the one or multiple metal elements constituting the first layer is different from the valence of the one or multiple metal elements constituting the third layer.
  • the crystallinity of the metal oxide can be improved, and the mobility of the metal oxide can be increased. Therefore, by using the metal oxide in the channel formation region of a transistor, the on-state current of the transistor can be increased, and the electrical characteristics of the transistor can be improved.
  • Examples of the metal oxide of one embodiment of the present invention include indium oxide, gallium oxide, and zinc oxide.
  • the metal oxide of one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn).
  • the metal oxide preferably has two or three elements selected from indium, element M, and zinc.
  • the element M is a metal element or semimetal element having a high bond energy with oxygen, for example, a metal element or semimetal element having a higher bond energy with oxygen than indium.
  • the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.
  • the element M in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium.
  • the metal oxide of one embodiment of the present invention preferably has one or more selected from indium, gallium, and zinc.
  • metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal element” described in this specification, etc. may include metalloid elements.
  • indium zinc oxide In-Zn oxide
  • indium tin oxide In-Sn oxide
  • indium titanium oxide In-Ti oxide
  • indium gallium oxide In-Ga oxide
  • indium gallium aluminum oxide In-Ga-Al oxide
  • indium gallium tin oxide In-Ga-Sn oxide
  • gallium zinc oxide Ga-Zn oxide, also referred to as GZO
  • aluminum zinc oxide Al-Zn oxide, also referred to as AZO
  • IAZO indium Indium aluminum zinc oxide
  • indium tin zinc oxide In-Sn-Zn oxide
  • indium titanium zinc oxide In-Ti-Zn oxide
  • indium gallium tin zinc oxide In-Ga-Sn-Zn oxide, also written as IGZTO
  • the field effect mobility of the transistor can be increased.
  • the metal oxide may have one or more metal elements with a large periodic number instead of indium.
  • the metal oxide may have one or more metal elements with a large periodic number in addition to indium.
  • Examples of metal elements with a large periodic number include metal elements belonging to the fifth period and metal elements belonging to the sixth period.
  • the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
  • the metal oxide may also contain one or more nonmetallic elements.
  • the field effect mobility of the transistor may be increased.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • the metal oxide becomes highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed. Therefore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • the transistor can obtain a large on-current and high frequency characteristics.
  • In-Ga-Zn oxide may be used as an example of a metal oxide.
  • the metal oxide film formation method of the present invention it is preferable to deposit atoms one layer at a time.
  • the ALD method is used, so that it is easy to form a metal oxide having the above-mentioned layered crystal structure.
  • ALD plasma Enhanced ALD
  • the ALD method can deposit atoms one layer at a time, and therefore has the following advantages: extremely thin films can be formed; films can be formed on structures with high aspect ratios; films can be formed with fewer defects such as pinholes; films can be formed with excellent coverage; and films can be formed at low temperatures.
  • the PEALD method may be preferable because it can form films at lower temperatures by using plasma.
  • some precursors used in the ALD method contain elements such as carbon or chlorine.
  • films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. Note that the quantification of these elements can be performed using XPS or SIMS.
  • the metal oxide film formation method of one embodiment of the present invention uses the ALD method, but adopts one or both of the conditions of a high substrate temperature during film formation and the implementation of an impurity removal process, and therefore the amount of carbon and chlorine contained in the film may be smaller than when the ALD method is used without applying these.
  • the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece, unlike a film formation method in which particles released from a target are deposited. Therefore, it is a film formation method that is not easily affected by the shape of the workpiece and has good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.
  • the ALD method since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as a sputtering method or a CVD method, which have a fast film formation speed.
  • a method of forming a first metal oxide film using a sputtering method and forming a second metal oxide film on the first metal oxide using an ALD method can be mentioned.
  • the second metal oxide may grow as a crystal with the crystal part as a nucleus.
  • the ALD method can control the composition of the resulting film by the amount of raw material gas introduced.
  • the ALD method can form a film of any composition by adjusting the amount of raw material gas introduced, the number of introductions (also called the number of pulses), the time required for one pulse (also called the pulse time), and the like.
  • the ALD method can form a film whose composition changes continuously by changing the raw material gas while forming the film.
  • the time required for film formation can be shortened compared to forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of memory devices can be increased in some cases.
  • a transistor with high field-effect mobility can be realized.
  • a highly reliable transistor can be realized.
  • a miniaturized or highly integrated transistor can be realized. For example, a transistor with a channel length of 2 nm to 30 nm can be manufactured.
  • an oxide semiconductor having a low carrier concentration is preferably used for the channel formation region of the transistor.
  • the carrier concentration of the channel formation region of the oxide semiconductor is 1 ⁇ 10 18 cm ⁇ 3 or less, preferably 1 ⁇ 10 17 cm ⁇ 3 or less, more preferably 1 ⁇ 10 15 cm ⁇ 3 or less, more preferably 1 ⁇ 10 13 cm ⁇ 3 or less, more preferably 1 ⁇ 10 11 cm ⁇ 3 or less, and further preferably less than 1 ⁇ 10 10 cm ⁇ 3 and 1 ⁇ 10 ⁇ 9 cm ⁇ 3 or more. Note that in order to reduce the carrier concentration of the oxide semiconductor, it is only necessary to reduce the impurity concentration in the oxide semiconductor and reduce the density of defect states.
  • a semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic.
  • an oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.
  • a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor film may have a low density of trap states because of its low density of defect states.
  • the charge trapped in the trap states of the oxide semiconductor takes a long time to disappear and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.
  • an impurity in an oxide semiconductor refers to, for example, anything other than the main component that constitutes the oxide semiconductor.
  • an element with a concentration of less than 0.1 atomic % can be considered an impurity.
  • the band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), and is preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more.
  • the off-state current (also referred to as Ioff) of the transistor can be reduced.
  • OS transistors use oxide semiconductors, which are semiconductor materials with a large band gap, and therefore the short channel effect can be suppressed. In other words, OS transistors are transistors that do not have the short channel effect or have an extremely small short channel effect.
  • the short channel effect is a degradation of electrical characteristics that becomes evident as transistors are miniaturized (reduced channel length).
  • Specific examples of short channel effects include a decrease in threshold voltage, an increase in subthreshold swing value (sometimes referred to as S value), and an increase in leakage current.
  • S value refers to the amount of change in gate voltage in the subthreshold region that changes the drain current by one order of magnitude at a constant drain voltage.
  • characteristic length is widely used as an index of resistance to short channel effects.
  • Characteristic length is an index of how easily the potential of the channel formation region bends. The smaller the characteristic length, the steeper the potential rises, and therefore the more resistant it is to short channel effects.
  • OS transistors are accumulation-type transistors, while Si transistors are inversion-type transistors. Therefore, compared to Si transistors, OS transistors have smaller characteristic lengths between the source region and the channel-forming region, and between the drain region and the channel-forming region. Therefore, OS transistors are more resistant to the short-channel effect than Si transistors. In other words, when it is desired to manufacture a transistor with a short channel length, OS transistors are more suitable than Si transistors.
  • the OS transistor can also be regarded as having an n + / n ⁇ /n + accumulation-type junction-less transistor structure or an n + /n ⁇ /n + accumulation-type non-junction transistor structure in which the channel formation region is an n ⁇ type region and the source and drain regions are n + type regions.
  • the OS transistor can have good electrical characteristics even when the memory device is miniaturized or highly integrated. For example, good electrical characteristics can be obtained even when the channel length or gate length of the OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, and 1 nm or more, 3 nm or more, or 5 nm or more.
  • the OS transistor can be suitably used as a transistor having a shorter channel length than that of a Si transistor.
  • the gate length is the length of the gate electrode in the direction in which carriers move inside the channel formation region when the transistor is operating.
  • the cutoff frequency of the transistor can be improved.
  • the cutoff frequency of the transistor can be set to, for example, 50 GHz or more, preferably 100 GHz or more, and more preferably 150 GHz or more in a room temperature environment.
  • OS transistors As explained above, compared to Si transistors, OS transistors have the excellent advantages of having a smaller off-state current and being able to fabricate transistors with a short channel length.
  • the carbon concentration in a channel formation region of the oxide semiconductor measured by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, and further preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, and still more preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the nitrogen concentration in a channel formation region of an oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 5 ⁇ 10 18 atoms/cm 3 or less, more preferably 1 ⁇ 10 18 atoms/cm 3 or less, and further preferably 5 ⁇ 10 17 atoms/cm 3 or less.
  • Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy.
  • an electron serving as a carrier may be generated.
  • some of the hydrogen may bond to oxygen bonded to a metal atom to generate an electron serving as a carrier. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable that hydrogen in a channel formation region of the oxide semiconductor is reduced as much as possible.
  • the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is less than 1 ⁇ 10 20 atoms/cm 3 , preferably less than 5 ⁇ 10 19 atoms/cm 3 , more preferably less than 1 ⁇ 10 19 atoms/cm 3 , more preferably less than 5 ⁇ 10 18 atoms/cm 3 , and further preferably less than 1 ⁇ 10 18 atoms/cm 3 .
  • the concentration of the alkali metal or the alkaline earth metal in a channel formation region of the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms/cm 3 or less, preferably 2 ⁇ 10 16 atoms/cm 3 or less.
  • the oxide semiconductor 270 can be rephrased as a semiconductor layer including a channel formation region of a transistor.
  • a semiconductor material that can be used for the semiconductor layer is not limited to the above-mentioned metal oxides.
  • a semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used for the semiconductor layer.
  • a semiconductor of a single element, a compound semiconductor, or a layered material (also referred to as an atomic layer material, a two-dimensional material, or the like) is preferably used for the semiconductor material.
  • layered material is a general term for a group of materials having a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces.
  • Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
  • Examples of elemental semiconductors that can be used in the semiconductor material include silicon and germanium.
  • Examples of silicon that can be used in the semiconductor layer include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon.
  • An example of polycrystalline silicon is low temperature polysilicon (LTPS).
  • Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide.
  • the boron nitride that can be used for the semiconductor layer preferably includes an amorphous structure.
  • the boron arsenide that can be used for the semiconductor layer preferably includes crystals with a cubic crystal structure.
  • Layered materials include graphene, silicene, boron carbonitride, and chalcogenides.
  • boron carbonitride carbon atoms, nitrogen atoms, and boron atoms are arranged in a hexagonal lattice structure on a plane.
  • Chalcogenides are compounds that contain chalcogen. Chalcogen is a general term for elements that belong to Group 16, and includes oxygen, sulfur, selenium, tellurium, polonium, and livermorium.
  • Other examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.
  • transition metal chalcogenide that functions as a semiconductor.
  • transition metal chalcogenides that can be used as the semiconductor layer include molybdenum sulfide (representatively MoS 2 ), molybdenum selenide (representatively MoSe 2 ), molybdenum tellurium (representatively MoTe 2 ), tungsten sulfide (representatively WS 2 ), tungsten selenide (representatively WSe 2 ), tungsten tellurium (representatively WTe 2 ), hafnium sulfide (representatively HfS 2 ), hafnium selenide (representatively HfSe 2 ), zirconium sulfide (representatively ZrS 2 ), and zirconium selenide (representatively ZrSe 2 ).
  • a new transistor, a new semiconductor device, and a new memory device can be provided.
  • a memory device that can be miniaturized or highly integrated can be provided.
  • a memory device with good frequency characteristics can be provided.
  • a memory device with high operating speed can be provided.
  • a memory device with good reliability can be provided.
  • a memory device with low power consumption can be provided.
  • a memory device having a transistor with a large on-state current can be provided.
  • a memory device with little variation in transistor characteristics can be provided.
  • a memory device with good electrical characteristics can be provided.
  • Figure 15A shows a schematic perspective view of a storage device according to one embodiment of the present invention.
  • Figure 15B shows a block diagram of a storage device according to one embodiment of the present invention.
  • the memory device 750 shown in Figures 15A and 15B has a drive circuit layer 701 and n memory layers 700 (n is an integer equal to or greater than 1). Each memory layer 700 has a memory cell array 10.
  • the memory cell array 10 has a plurality of memory cells 11.
  • the n-layer memory layer 700 is provided on the drive circuit layer 701.
  • the area occupied by the memory device 750 can be reduced.
  • the memory capacity per unit area can be increased.
  • the first memory layer 700 is indicated as memory layer 700_1, the second memory layer 700 is indicated as memory layer 700_2, and the third memory layer 700 is indicated as memory layer 700_3.
  • the kth memory layer 700 (k is an integer between 1 and n) is indicated as memory layer 700_k, and the nth memory layer 700 is indicated as memory layer 700_n. Note that in this embodiment and the like, when describing matters related to the n memory layers 700 as a whole, or when indicating matters common to each layer of the n memory layers 700, the term "memory layer 700" may be used.
  • the drive circuit layer 701 has a PSW22 (power switch), a PSW23, and a peripheral circuit 31.
  • the peripheral circuit 31 has a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.
  • each circuit, signal, and voltage can be selected or removed as needed. Alternatively, other circuits or other signals may be added.
  • Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and signal RDA is an output signal to the outside.
  • Signal CLK is a clock signal.
  • Signals BW, CE, and GW are control signals.
  • Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal.
  • Signal ADDR is an address signal.
  • Signal WDA is write data, and signal RDA is read data.
  • Signals PON1 and PON2 are signals for power gating control. Signals PON1 and PON2 may be generated by control circuit 32.
  • the control circuit 32 is a logic circuit that has the function of controlling the overall operation of the memory device 750. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 750. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.
  • the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 750.
  • the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.
  • the voltage generation circuit 33 has a function of generating a negative voltage.
  • the signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 33. For example, when an H-level signal is given to the signal WAKE, the signal CLK is input to the voltage generation circuit 33, and the voltage generation circuit 33 generates a negative voltage.
  • the peripheral circuit 41 is a circuit for writing and reading data to the memory cells 11.
  • the peripheral circuit 41 has a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.
  • the row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR.
  • the row decoder 42 is a circuit for specifying the row to be accessed
  • the column decoder 44 is a circuit for specifying the column to be accessed.
  • the row driver 43 has the function of selecting the wiring WWL (write word line) or wiring RWL (read word line) specified by the row decoder 42.
  • the column driver 45 has the function of writing data to the memory cell 11, the function of reading data from the memory cell 11, and the function of retaining the read data.
  • the column driver 45 has the function of selecting the wiring WBL (write bit line) and wiring RBL (read bit line) specified by the column decoder 44.
  • the input circuit 47 has a function of holding a signal WDA.
  • the data held by the input circuit 47 is output to the column driver 45.
  • the output data of the input circuit 47 is the data (Din) to be written to the memory cell 11.
  • the data (Dout) read from the memory cell 11 by the column driver 45 is output to the output circuit 48.
  • the output circuit 48 has a function of holding Dout.
  • the output circuit 48 has a function of outputting Dout to the outside of the memory device 750.
  • the data output from the output circuit 48 is the signal RDA.
  • PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31.
  • PSW23 has a function of controlling the supply of VHM to the row driver 43.
  • the high power supply voltage of the memory device 750 is VDD
  • the low power supply voltage is GND (ground potential).
  • VHM is a high power supply voltage used to set the word line to a high level, and is higher than VDD.
  • the on/off of PSW22 is controlled by the signal PON1, and the on/off of PSW23 is controlled by the signal PON2.
  • the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but it is also possible to have multiple power domains. In this case, a power switch can be provided for each power domain.
  • Each of the n memory layers 700 has a memory cell array 10. Furthermore, the memory cell array 10 has a plurality of memory cells 11. Figures 15A and 15B show an example in which the memory cell array 10 has a plurality of memory cells 11 arranged in a matrix of p rows and q columns (p and q are integers equal to or greater than 2).
  • rows and columns extend in directions perpendicular to each other.
  • the X direction is referred to as the "rows” and the Y direction is referred to as the “columns”, but the X direction may also be referred to as the “columns” and the Y direction as the "rows”.
  • the memory cell 11 located in the first row and first column is indicated as memory cell 11[1,1]
  • the memory cell 11 located in the pth row and qth column is indicated as memory cell 11[p,q].
  • the memory cell 11 located in the ith row and jth column (i is an integer from 1 to p, and j is an integer from 1 to q) is indicated as memory cell 11[i,j].
  • memory cell 150 As an example of the circuit configuration of memory cell 11, the configuration described in the above embodiment (memory cell 150) can be applied.
  • the wiring WBL and wiring RBL are arranged in a direction perpendicular to the substrate surface.
  • the signal propagation distance between the wiring WBL and the sense amplifier connected to the wiring RBL can be shortened, and the resistance and parasitic capacitance of the wiring WBL and wiring RBL can be significantly reduced, thereby reducing power consumption and signal delay.
  • Embodiment 3 electronic components, electronic devices, large scale computers, space equipment, and data centers (also referred to as data centers (DCs)) that can use the memory devices described in the above embodiments will be described.
  • the electronic components, electronic devices, large scale computers, space equipment, and data centers that use the memory devices of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.
  • FIG. 16A shows a perspective view of a substrate (mounting substrate 704) on which an electronic component 709 is mounted.
  • the electronic component 709 shown in FIG. 16A has a memory device 710 in a mold 711. In FIG. 16A, some parts are omitted in order to show the inside of the electronic component 709.
  • the electronic component 709 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the memory device 710 via wires 714.
  • the electronic component 709 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.
  • the memory device 710 also has a drive circuit layer 715 and a memory layer 716.
  • the memory layer 716 is configured by stacking multiple memory cell arrays.
  • the stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In the monolithic stacked configuration, each layer can be connected without using a through electrode technology such as a TSV (Through Silicon Via) or a bonding technology such as Cu-Cu direct bonding.
  • TSV Through Silicon Via
  • a bonding technology such as Cu-Cu direct bonding.
  • the memory as an on-chip memory, it is possible to reduce the size of the connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and it is also possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, making it possible to improve the memory bandwidth (also called memory bandwidth).
  • the memory cell arrays in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked.
  • OS transistors By forming the memory cell arrays in a monolithic stacked configuration, it is possible to improve either or both of the memory bandwidth and the memory access latency.
  • the bandwidth is the amount of data transferred per unit time
  • the access latency is the time from access to the start of data exchange.
  • Si transistors when Si transistors are used for the memory layer 716, it is difficult to form a monolithic stacked configuration compared to OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked configuration.
  • the memory device 710 may also be referred to as a die.
  • a die refers to a chip piece obtained during the manufacturing process of a semiconductor chip by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and cutting it into a dice shape.
  • Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN).
  • Si silicon
  • SiC silicon carbide
  • GaN gallium nitride
  • a die obtained from a silicon substrate also called a silicon wafer
  • a silicon die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.
  • Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module).
  • Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple memory devices 710 provided on interposer 731.
  • the memory device 710 is used as a high bandwidth memory (HBM).
  • the semiconductor device 735 can be an integrated circuit such as a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA).
  • the package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate.
  • the interposer 731 may be, for example, a silicon interposer or a resin interposer.
  • the interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches.
  • the multiple wirings are provided in a single layer or multiple layers.
  • the interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732.
  • the interposer may be called a "rewiring substrate” or "intermediate substrate.”
  • a through electrode may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrode.
  • a TSV may be used as the through electrode.
  • the interposer on which the HBM is mounted is required to have fine, high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.
  • silicon interposers Furthermore, in SiP and MCM using silicon interposers, deterioration of reliability due to differences in the expansion coefficient between the integrated circuit and the interposer is unlikely to occur. Furthermore, since the surface of the silicon interposer is highly flat, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional mounting) in which multiple integrated circuits are arranged horizontally on the interposer.
  • a composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithic stacking memory cell array.
  • a heat sink may be provided overlapping the electronic component 730.
  • electrodes 733 may be provided on the bottom of the package substrate 732.
  • FIG. 16B shows an example in which the electrodes 733 are formed from solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved.
  • the electrodes 733 may also be formed from conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.
  • the electronic component 730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA.
  • mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).
  • FIG. 17A a perspective view of an electronic device 6500 is shown in FIG. 17A.
  • the electronic device 6500 shown in FIG. 17A is a portable information terminal that can be used as a smartphone.
  • the electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like.
  • the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device.
  • the storage device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.
  • the electronic device 6600 shown in FIG. 17B is an information terminal that can be used as a notebook personal computer.
  • the electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display unit 6615, a control device 6616, and the like.
  • the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a storage device.
  • the storage device of one embodiment of the present invention can be applied to the display unit 6615, the control device 6616, and the like. Note that the use of the storage device of one embodiment of the present invention for the above-described control device 6509 and the control device 6616 is preferable because power consumption can be reduced.
  • Fig. 17C shows a perspective view of the large scale computer 5600.
  • the large scale computer 5600 shown in Fig. 17C has a rack 5610 housing a plurality of rack-mounted computers 5620.
  • the large scale computer 5600 may also be called a supercomputer.
  • the computer 5620 can have the configuration shown in the perspective view of FIG. 17D, for example.
  • the computer 5620 has a motherboard 5630, which has multiple slots 5631 and multiple connection terminals.
  • a PC card 5621 is inserted into the slot 5631.
  • the PC card 5621 has connection terminals 5623, 5624, and 5625, each of which is connected to the motherboard 5630.
  • the PC card 5621 shown in FIG. 17E is an example of a processing board equipped with a CPU, a GPU, a storage device, and the like.
  • the PC card 5621 has a board 5622.
  • the board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629.
  • FIG. 17E illustrates semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, but for those semiconductor devices, please refer to the description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 described below.
  • connection terminal 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630.
  • An example of the standard for the connection terminal 5629 is PCIe.
  • Connection terminals 5623, 5624, and 5625 can be interfaces for supplying power to PC card 5621, inputting signals, and the like. They can also be interfaces for outputting signals calculated by PC card 5621, and the like. Examples of standards for connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when a video signal is output from connection terminals 5623, 5624, and 5625, examples of standards for each include HDMI (registered trademark).
  • the semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.
  • the semiconductor device 5627 has multiple terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring provided on the board 5622 using a reflow method.
  • Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU.
  • the electronic component 730 can be used as the semiconductor device 5627.
  • the semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected to the terminals by, for example, reflow soldering to wiring provided on the board 5622.
  • Examples of the semiconductor device 5628 include a memory device.
  • the electronic component 709 can be used as the semiconductor device 5628.
  • the mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for artificial intelligence learning and inference, for example.
  • the memory device of one embodiment of the present invention can be suitably used in space equipment, such as equipment for processing and storing information.
  • the memory device of one embodiment of the present invention can include an OS transistor.
  • the OS transistor has small changes in electrical characteristics due to radiation exposure.
  • the OS transistor has high resistance to radiation and can be preferably used in an environment where radiation may be incident.
  • the OS transistor can be preferably used in outer space.
  • Figure 18 shows an artificial satellite 6800 as an example of space equipment.
  • the artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807.
  • a planet 6804 is shown as an example of outer space.
  • outer space refers to an altitude of 100 km or more, for example, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.
  • the secondary battery 6805 may be provided with a battery management system (also called BMS) or a battery control circuit.
  • BMS battery management system
  • the use of OS transistors in the above-mentioned battery management system or battery control circuit is preferable because it has low power consumption and high reliability even in space.
  • outer space is an environment with radiation levels 100 times higher than on Earth.
  • radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.
  • the solar panel 6802 When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where the solar panel is not irradiated with sunlight, or where the amount of sunlight irradiating the solar panel is small, the amount of power generated is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is advisable to provide the satellite 6800 with a secondary battery 6805. Note that the solar panel may be called a solar cell module.
  • the artificial satellite 6800 can generate a signal.
  • the signal is transmitted via the antenna 6803, and can be received, for example, by a receiver installed on the ground or by another artificial satellite.
  • the position of the receiver that received the signal can be measured.
  • the artificial satellite 6800 can constitute a satellite positioning system.
  • the control device 6807 has a function of controlling the artificial satellite 6800.
  • the control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device.
  • the control device 6807 is preferably a storage device according to one embodiment of the present invention.
  • an OS transistor Compared to a Si transistor, an OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure. In other words, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.
  • the artificial satellite 6800 can also be configured to have a sensor.
  • the artificial satellite 6800 can have the function of detecting sunlight reflected off an object on the ground.
  • the artificial satellite 6800 can have a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. From the above, the artificial satellite 6800 can have the function of, for example, an earth observation satellite.
  • an artificial satellite is given as an example of space equipment, but the present invention is not limited to this.
  • a storage device according to one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.
  • OS transistors As explained above, compared to Si transistors, OS transistors have the advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance.
  • the storage device can be suitably used in a storage system applied to, for example, a data center.
  • the data center is required to perform long-term management of data, such as ensuring the immutability of the data.
  • long-term management of data such as ensuring the immutability of the data.
  • it is necessary to increase the size of the building, such as by installing storage and servers for storing a huge amount of data, by securing a stable power source for storing the data, or by securing cooling equipment required for storing the data.
  • a storage device By using a storage device according to one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and to miniaturize the storage device that stores the data. This makes it possible to miniaturize the storage system, the power source for storing data, and the cooling equipment. This makes it possible to save space in the data center.
  • the memory device of one embodiment of the present invention consumes less power, and therefore heat generation from the circuit can be reduced. This reduces adverse effects of heat generation on the circuit itself, peripheral circuits, and modules. Furthermore, by using the memory device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. This improves the reliability of the data center.
  • FIG 19 shows a storage system applicable to a data center.
  • the storage system 7000 shown in Figure 19 has multiple servers 7001sb as hosts 7001 (illustrated as Host Computer). It also has multiple storage devices 7003md as storage 7003 (illustrated as Storage).
  • the host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).
  • SAN Storage Area Network
  • the host 7001 corresponds to a computer that accesses data stored in the storage 7003.
  • the hosts 7001 may be connected to each other via a network.
  • Storage 7003 uses flash memory to reduce data access speed, i.e. the time required to store and output data, but this time is significantly longer than the time required by DRAM, which can be used as cache memory within the storage.
  • storage systems usually provide cache memory within the storage to reduce the time required to store and output data.
  • the above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.
  • OS transistors as transistors for storing data in the above-mentioned cache memory and configuring them to hold a potential corresponding to the data, it is possible to reduce the frequency of refreshing and reduce power consumption.
  • configuring the memory cell array in a stacked manner it is possible to reduce the size.
  • the application of the storage device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframes, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the performance or integration of storage devices, the use of the storage device of one embodiment of the present invention can reduce emissions of greenhouse gases such as carbon dioxide (CO 2 ). In addition, the storage device of one embodiment of the present invention is also effective as a measure against global warming because of its low power consumption.
  • CO 2 greenhouse gases

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