WO2024095464A1 - 半導体デバイスの製造方法 - Google Patents

半導体デバイスの製造方法 Download PDF

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Publication number
WO2024095464A1
WO2024095464A1 PCT/JP2022/041199 JP2022041199W WO2024095464A1 WO 2024095464 A1 WO2024095464 A1 WO 2024095464A1 JP 2022041199 W JP2022041199 W JP 2022041199W WO 2024095464 A1 WO2024095464 A1 WO 2024095464A1
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WO
WIPO (PCT)
Prior art keywords
carrier
semiconductor device
manufacturing
adhesive layer
grinding
Prior art date
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Ceased
Application number
PCT/JP2022/041199
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English (en)
French (fr)
Japanese (ja)
Inventor
克彦 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Resonac Corp
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Filing date
Publication date
Application filed by Resonac Corp filed Critical Resonac Corp
Priority to JP2024554064A priority Critical patent/JPWO2024095464A1/ja
Priority to PCT/JP2022/041199 priority patent/WO2024095464A1/ja
Priority to CN202280095458.2A priority patent/CN119137731A/zh
Priority to US18/857,189 priority patent/US20250329549A1/en
Priority to TW112141219A priority patent/TW202420556A/zh
Publication of WO2024095464A1 publication Critical patent/WO2024095464A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/014—Manufacture or treatment using batch processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H10P72/7418—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. a chip mounting substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/10—Configurations of laterally-adjacent chips

Definitions

  • This disclosure relates to a method for manufacturing a semiconductor device.
  • Patent Document 1 discloses an example of a fan-out type semiconductor device.
  • a redistribution layer is provided between the semiconductor chip and the external connection terminal, and the redistribution layer widens the terminal spacing of the semiconductor chip and connects it to the external connection terminal.
  • FIG. 5A For example, multiple semiconductor chips 110 are temporarily fixed on a glass carrier 120 with a temporary fixing material 112 and sealed with a sealing material 130. The sealing material 130 is then polished until the connection terminals of the semiconductor chips 110 are exposed, and a redistribution layer 140 (see FIG. 5B) is formed thereon.
  • the semiconductor chips 110 since the semiconductor chips 110 are temporarily fixed to the carrier 120 with the temporary fixing material 112, when the sealing material 130 is molded by a molding machine, the pressure may cause the semiconductor chips 110 to move from their original installation position, resulting in a so-called die shift S1. If a die shift occurs, a separate alignment process is required for the subsequent process (e.g., the exposure process).
  • the outer periphery S2 of the temporary fixing material 112 sandwiched between the glass carrier 120 and the sealing material 130 is exposed and may be damaged by the chemicals used. This may cause the glass carrier 120 and the sealing material 130 to peel off during the process. Furthermore, as shown in FIG. 5B, when the temporary fixing material 112 is peeled off from the sealing material 130, cracks may occur between the semiconductor chip 110 and the sealing material 130 due to the force applied when peeling it off. Residual resin from the temporary fixing material 112 may remain on the surface of the sealing material 130 or the semiconductor chip 110 (S3), microcracks S4 may occur in the glass carrier 120 during the process, or metal S5 used in the process may be mixed into the microcracks S4.
  • the present disclosure aims to provide a method for manufacturing semiconductor devices that can easily improve the cleanliness of the chip surface while suppressing misalignment of the semiconductor chip.
  • the present disclosure relates to a method for manufacturing a semiconductor device.
  • the manufacturing method includes the steps of preparing a laminate in which a plurality of semiconductor chips are each fixed on a carrier by an adhesive layer, and each connection terminal of the plurality of semiconductor chips is fixed to a first carrier surface of the carrier so as to face away from the carrier; forming a redistribution layer that connects to each connection terminal of the plurality of semiconductor chips; and grinding the carrier in the laminate from a second carrier surface opposite the first carrier surface toward the first carrier surface.
  • the carrier and the adhesive layer are scraped off to expose the second chip surface opposite the first chip surface on which the redistribution layer of the plurality of semiconductor chips is provided.
  • the semiconductor device manufacturing method multiple semiconductor chips are fixed onto the carrier by an adhesive layer.
  • the semiconductor chips are fixed to the carrier by an adhesive layer that provides a permanent fixation rather than a temporary fixation. In this case, misalignment of the semiconductor chips is reliably suppressed.
  • the carrier is scraped off in the grinding step to expose a second chip surface opposite to the first chip surface on which the rewiring layer of the multiple semiconductor chips is provided. In this case, because the carrier is scraped off, no resin residue or the like remains, and it is possible to improve the cleanliness of the chip surface.
  • the adhesive layer may be a layer of hardened thermosetting adhesive, and may be provided for each of the multiple semiconductor chips.
  • the adhesive layer can be easily ground in the process of grinding the carrier.
  • the thickness of the adhesive layer is 50 ⁇ m or less. In this case, the adhesive layer can be easily ground in the step of grinding the carrier. It is further preferable that the thickness of the adhesive layer is 20 ⁇ m or less. In this case, the adhesive layer can be even more easily ground.
  • the adhesive layer contains a curable resin component and an inorganic filler, and the content of the inorganic filler is preferably 50% by mass to 95% by mass based on the total amount of adhesive before the adhesive layer hardens.
  • the adhesive layer can be easily ground in the step of grinding the carrier.
  • the content of the inorganic filler is 80% by mass to 95% by mass based on the total amount of adhesive before the adhesive layer hardens. In this case, the adhesive layer can be even more easily ground in the step of grinding the carrier.
  • the step of preparing a laminate may include a step of fixing each of the multiple semiconductor chips to the carrier with an adhesive layer, and a step of forming an encapsulant layer by encapsulating the multiple semiconductor chips on the carrier with an encapsulant so as to cover them.
  • the encapsulant contains a curable resin component and an inorganic filler, and the content of the inorganic filler in the encapsulant may be 50 mass% or more, based on the total amount of the encapsulant, and is preferably 80 mass% or more. In this case, it is possible to reliably grind the encapsulant layer.
  • the step of preparing the stack may further include, after the sealing step, a step of grinding the encapsulant layer covering the multiple semiconductor chips until the first chip surfaces of the multiple semiconductor chips are exposed.
  • the step of grinding the carrier preferably includes a step of roughly grinding the second carrier surface of the carrier with a first grindstone, and a step of finish-grinding the roughly ground carrier with a second grindstone having a grit greater than that of the first grindstone.
  • the grinding speed of the carrier can be increased by rough grinding
  • the finish of the ground surface can be improved by finish grinding.
  • the first grindstone may be a grindstone having a grit size of #200 to #1000
  • the second grindstone may be a grindstone having a grit size of #2000 to #6000. This makes it possible to more reliably improve the grinding speed and the finish accuracy of the ground surface.
  • the rough grinding step may be performed by grinding off at least a portion of the carrier and the adhesive layer with the first grindstone
  • the finish grinding step may be performed by polishing the encapsulant layer and the second chip surface of the semiconductor chip with the second grindstone. This makes it possible to more reliably improve the grinding speed and the finish accuracy of the ground surface.
  • the carrier is a silicon carrier
  • the grinding step may further include a step of recovering the ground silicon sludge (silicon scraps) for reuse.
  • the silicon used can be reused, making the manufacturing method environmentally friendly.
  • impurities can be removed from the ground silicon sludge and it can be used as regenerated silicon.
  • the present disclosure provides a method for manufacturing semiconductor devices that can easily improve the cleanliness of the chip surface while suppressing misalignment of the semiconductor chip.
  • FIG. 1 is a cross-sectional view showing an example of a semiconductor device.
  • 2A to 2C are diagrams sequentially showing a method for manufacturing a semiconductor device.
  • 3A and 3B are diagrams sequentially showing a method for manufacturing a semiconductor device, illustrating steps performed following the step in FIG. 4A to 4C are diagrams sequentially showing a method for manufacturing a semiconductor device, illustrating steps performed following the step in FIG. 5A and 5B are diagrams showing a method for manufacturing a semiconductor device according to a comparative example.
  • FIG. 1 is a cross-sectional view showing an example of a semiconductor device.
  • the semiconductor device 1 includes a semiconductor chip 2, a protective portion 3, a redistribution layer 4, and bumps 5.
  • the semiconductor chip 2 is, for example, a semiconductor chip such as a processor or memory.
  • the protective portion 3 is a portion made of sealing resin or the like, and protects the semiconductor chip 2.
  • the redistribution layer 4 (RDL) is a wiring layer having an insulating portion and wiring (for example, copper wiring) formed within the insulating portion.
  • the redistribution layer 4 connects between the connection terminals of the semiconductor chip 2 and the bumps 5.
  • the bumps 5 are, for example, made of a metal material such as solder.
  • FIGS. 2 to 4 are diagrams sequentially showing the method for manufacturing the semiconductor device 1.
  • the semiconductor device 1 is manufactured, for example, through the following steps (a) to (d).
  • (a) A step of preparing a laminate T1 in which each of a plurality of semiconductor chips 10 is fixed onto a carrier 20 by an adhesive layer 12.
  • each of the connection terminals 10c of the plurality of semiconductor chips 10 is fixed to a first carrier surface 20a of the carrier 20 so as to face away from the carrier 20.
  • (b) A step of forming a rewiring layer 40 that is connected to each of the connection terminals 10 c of the plurality of semiconductor chips 10 .
  • step (c) A step of grinding the carrier 20 in the laminate T2 from a second carrier surface 20b opposite to the first carrier surface 20a toward the first carrier surface 20a. In this step (c), the carrier 20 and the adhesive layer 12 are scraped off to expose the second chip surface 10b opposite to the first chip surface 10a on which the rewiring layers 40 of the multiple semiconductor chips 10 are provided.
  • step (d) A process of dicing the laminate T3 from which the carrier 20 has been scraped off into individual semiconductor devices each including a semiconductor chip 10. In this process (d), a predetermined number of bumps (corresponding to the bumps 5 in FIG. 1 ) are formed on the rewiring layer 40 before the dicing.
  • step (a) first, as shown in FIG. 2(a), a plurality of semiconductor chips 10 are prepared. An adhesive layer 12 is adhered to each semiconductor chip 10.
  • the semiconductor chips 10 correspond to the semiconductor chip 2 in the semiconductor device 1 shown in FIG. 1.
  • the semiconductor chip 10 has a first chip surface 10a on which connection terminals 10c are provided, and a second chip surface 10b opposite the first chip surface 10a.
  • An adhesive layer 12 is attached to the second chip surface 10b. In other words, the adhesive layer 12 is provided corresponding to each semiconductor chip 10.
  • the adhesive layer 12 is in an uncured state when prepared.
  • the adhesive layer 12 is, for example, a film containing a thermosetting adhesive such as a die attach film (DAF).
  • the thermosetting adhesive constituting the adhesive layer 12 contains, for example, a polymeric resin component and a thermosetting component.
  • the thickness of the adhesive layer 12 is, for example, 50 ⁇ m or less. By having a thickness of the adhesive layer 12 of 50 ⁇ m or less, the adhesive layer 12 can be easily scraped off during cutting in step (c).
  • the thickness of the adhesive layer 12 may be 20 ⁇ m or less, 10 ⁇ m or less, 9 ⁇ m or less, 8 ⁇ m or less, or 7 ⁇ m or less, or may be 1 ⁇ m or more, 2 ⁇ m or more, 3 ⁇ m or more, 4 ⁇ m or more, or 5 ⁇ m or more. Note that the thickness of the adhesive layer 12 here refers to the thickness after curing.
  • the high molecular weight resin component contained in the adhesive layer 12 may include, for example, at least one type of resin selected from the group consisting of acrylic rubber, polyimide, and phenoxy resin.
  • the high molecular weight resin component may have a reactive group such as an epoxy group.
  • the weight average molecular weight of the high molecular weight resin component (standard polystyrene equivalent value according to the GPC method) may be 100,000 to 3,000,000.
  • the content of the high molecular weight resin component may be 30 to 80 parts by mass per 10 parts by mass of the total mass of the adhesive layer 12.
  • thermosetting component that may be included in the adhesive layer 12 is a compound having a reactive group that forms a crosslinked structure by self-polymerization and/or reaction with a curing agent.
  • the thermosetting component may include, for example, at least one selected from the group consisting of epoxy resins, bismaleimide resins, triazine resins, and phenolic resins.
  • the content of the thermosetting component may be 1 to 30 parts by mass per 100 parts by mass of the adhesive layer 12.
  • thermosetting adhesive constituting the adhesive layer 12 may contain other components as necessary.
  • other components include a curing agent that reacts with the thermosetting component, a curing accelerator that promotes the reaction between the thermosetting component and the curing agent, a coupling agent (e.g., a silane coupling agent), and a filler (e.g., silica).
  • a curing agent that reacts with the thermosetting component
  • a curing accelerator that promotes the reaction between the thermosetting component and the curing agent
  • a coupling agent e.g., a silane coupling agent
  • a filler e.g., silica
  • the filler contained in the adhesive layer 12 may be an inorganic filler.
  • inorganic fillers include aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide, aluminum oxide, aluminum nitride, aluminum borate whiskers, boron nitride, crystalline silica, and amorphous silica. These may be used alone or in combination of two or more.
  • the content of the filler contained in the adhesive layer 12 may be 50% by mass to 95% by mass based on the total amount of the adhesive layer 12 (adhesive) before curing.
  • the content of the filler contained in the adhesive layer 12 is preferably 60% by mass or more, more preferably 70% by mass or more, particularly preferably 80% by mass or more, and preferably 80% by mass to 95% by mass based on the total amount of the adhesive layer 12 (adhesive) before curing.
  • the carrier 20 is prepared.
  • a silicon carrier can be used as the carrier 20.
  • the silicon carrier may be single crystal silicon or polycrystalline silicon.
  • the carrier 20 has a thickness of, for example, 0.6 to 1.1 mm and a flatness of a calculated average roughness of 50 nm or less.
  • the carrier 20 is, for example, in the form of a wafer or a panel, and is not particularly limited, and may be, for example, a circular wafer with a diameter of 200 mm, 300 mm, or 450 mm, or a rectangular panel with a side of 200 to 700 mm or less.
  • a prepreg without copper foil may be used as the carrier 20.
  • the semiconductor chips 10 are fixed to the first carrier surface 20a of the carrier 20 so that each connection terminal 10c of the semiconductor chips 10 faces away from the carrier 20 (in a so-called face-up state).
  • This fixing is performed by attaching each semiconductor chip 10 to the carrier 20 with the adhesive layer 12 before hardening, and then hardening the adhesive layer 12 attached to each semiconductor chip 10. Since this fixing is strong, the semiconductor chip 10 cannot move after being fixed to the first carrier surface 20a of the carrier 20.
  • the surface of the carrier 20 opposite the first carrier surface 20a is the second carrier surface 20b.
  • the semiconductor chips 10 on the carrier 20 are sealed with a sealing material so as to cover them.
  • This sealing with the sealing material can be performed, for example, by molding with a mold.
  • the semiconductor chips 10 are firmly fixed to the carrier 20 by the adhesive layer 12, so that even if the sealing material is sealed with a molding machine, the phenomenon of the semiconductor chips 10 shifting (die shift) does not occur. In this way, a sealing material layer 30 that covers the semiconductor chips 10 is formed.
  • the sealing material used as the sealing material layer 30 may be, for example, a sealing material containing an epoxy resin, and may contain a curable resin component and an inorganic filler.
  • the content of the inorganic filler in the sealing material may be 50 mass% or more based on the total amount of the sealing material before curing.
  • the content of the inorganic filler in the sealing material is preferably 60 mass% or more, more preferably 70 mass% or more, and particularly preferably 80 mass% or more based on the total amount of the sealing material before curing.
  • the content of the inorganic filler in the sealing material may be 60 mass% to 90 mass% based on the total amount of the sealing material before curing.
  • the filler contained in the sealing material layer 30 may be an inorganic filler.
  • inorganic fillers include aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide, aluminum oxide, aluminum nitride, aluminum borate whisker, boron nitride, crystalline silica, and amorphous silica. These may be used alone or in combination of two or more.
  • the sealing material layer 30 is ground until the connection terminals 10c (first chip surface 10a) of the semiconductor chip 10 are exposed, forming a sealing material layer 30A.
  • the sealing material layer 30 may be ground to a grinding amount of, for example, 30 ⁇ m or more.
  • the thickness of the ground sealing material layer 30A may be 50 ⁇ m or more, 100 ⁇ m or more, or 150 ⁇ m or more.
  • a redistribution layer 40 is formed to connect to each of the connection terminals 10c of the multiple semiconductor chips 10.
  • the distance between the wirings, which are conductors, is gradually increased as it moves away from the semiconductor chip 10 (toward the top in the figure).
  • the redistribution layer 40 is formed on the first chip surface 10a of the multiple semiconductor chips 10 and on the surface of the encapsulant layer 30A. Note that the redistribution layer 40 can be formed using a conventional method, so a detailed description will be omitted. As described above, a laminate T2 provided with the redistribution layer 40 is formed.
  • step (c) when the redistribution layer 40 is formed, the carrier 20 in the laminate T2 is ground from the second carrier surface 20b toward the first carrier surface 20a while protecting the redistribution layer 40 with a BG tape 45 (backgrind tape) or the like.
  • the carrier 20 is first roughly ground with a first grindstone 50 from the second carrier surface 20b toward the first carrier surface 20a, as shown in (a) and (b) of FIG. 4.
  • the first grindstone 50 is, for example, a grindstone with a grit size of #200 to #1000.
  • the carrier 20 is first ground, and then the adhesive layer 12 and the surface portion of the encapsulant layer 30A (the area of the same layer as the adhesive layer 12) are ground.
  • grinding may be performed until the second chip surface 10b of the semiconductor chip 10 is exposed, or may be performed until just before the second chip surface 10b of the semiconductor chip 10 is exposed.
  • the silicon sludge (waste) generated mainly by rough grinding can be collected and reused.
  • the roughly ground carrier 20A is finish-ground with a second grindstone 55 having a higher grit than the first grindstone 50, as shown in FIG. 4(c).
  • the second grindstone 55 has a grit size of #2000 to #6000.
  • the finish-grinding process the second chip surface 10b of the semiconductor chip 10 and the surface of the encapsulant layer 30A are polished. This improves the cleanliness of the second chip surface 10b of the semiconductor chip 10 encapsulated in the encapsulant layer 30A.
  • a stack T3 is formed that includes multiple semiconductor chips 10 provided with a redistribution layer 40.
  • step (d) the laminate T3 from which the carrier 20 has been removed is diced into individual semiconductor devices each having a semiconductor chip 10. Note that bumps may be attached to the redistribution layer 40 before dicing. This makes it possible to obtain multiple semiconductor devices 1 as shown in FIG. 1.
  • the semiconductor device manufacturing method As described above, in the semiconductor device manufacturing method according to this embodiment, multiple semiconductor chips 10 are fixed onto the carrier 20 by the adhesive layer 12. In this way, the semiconductor chips 10 are firmly fixed to the carrier 20 by the adhesive layer 12, which is not a temporary fixation but a permanent fixation. In this case, misalignment of the semiconductor chips 10 is reliably suppressed. Also, in this semiconductor device manufacturing method, in the grinding step, the carrier 20 is scraped off to expose the second chip surface 10b opposite the first chip surface 10a on which the rewiring layer 40 of the multiple semiconductor chips 10 is provided. In this case, because the carrier 20 is scraped off, no resin residue or the like remains, and it is possible to improve the cleanliness of the chip surface.
  • the adhesive layer 12 is a layer of hardened thermosetting adhesive, and may be provided for each of the multiple semiconductor chips 10. This allows the adhesive layer 12 to be easily ground when grinding the carrier 20.
  • the thickness of the adhesive layer 12 can be set to 50 ⁇ m or less. In this case, the adhesive layer 12 can be easily ground when grinding the carrier 20.
  • the adhesive layer 12 contains a curable resin component and an inorganic filler, and the content of the inorganic filler can be 50% to 95% by mass based on the total amount of adhesive before the adhesive layer 12 hardens.
  • the adhesive layer 12 can be easily ground when the carrier 20 is ground.
  • the process of preparing the laminate T1 includes a process of fixing each of the multiple semiconductor chips 10 to the carrier 20 with an adhesive layer 12, and a process of sealing the multiple semiconductor chips 10 on the carrier 20 with a sealing material to cover them, thereby forming a sealing material layer 30.
  • the sealing material contains a curable resin component and an inorganic filler, and the content of the inorganic filler in the sealing material may be 50 mass% or more based on the total amount of the sealing material before hardening. In this case, it is possible to reliably grind the sealing material layer 30.
  • the step of preparing the laminate T1 may further include, after the sealing step, a step of grinding the encapsulant layer 30 covering the multiple semiconductor chips 10 until the first chip surfaces 10a of the multiple semiconductor chips 10 are exposed.
  • the step of grinding the carrier 20 includes a step of roughly grinding the second carrier surface 20b of the carrier 20 with a first grindstone 50, and a step of finish-grinding the roughly ground carrier 20A with a second grindstone 55 having a grit size higher than that of the first grindstone 50.
  • the rough grinding can increase the grinding speed of the carrier 20, and the finish grinding can improve the finish of the ground surface.
  • the first grindstone may be a grindstone having a grit size of #200 to #1000
  • the second grindstone may be a grindstone having a grit size of #2000 to #6000. This makes it possible to more reliably improve the grinding speed and the finish accuracy of the ground surface.
  • the carrier 20 and at least a part of the adhesive layer 12 may be scraped off by the first grindstone 50.
  • the finish grinding step the encapsulant layer 30A and the second chip surface 10b of the semiconductor chip 10 may be polished by the second grindstone 55. This makes it possible to more reliably improve the grinding speed and the finish accuracy of the grinding surface.
  • the carrier 20 may be a silicon carrier.
  • the grinding step may further include a step of recovering the ground silicon sludge for reuse.
  • the silicon used can be reused, making this an environmentally friendly manufacturing method.
  • 1...semiconductor device 10...semiconductor chip, 10a...first chip surface, 10b...second chip surface, 10c...connection terminal, 12...adhesive layer, 20, 20A...carrier, 20a...first carrier surface, 20b...second carrier surface, 30, 30A...sealing material layer, 40...rewiring layer, 50...first grinding wheel, 55...second grinding wheel, T1, T2...laminated body.

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PCT/JP2022/041199 2022-11-04 2022-11-04 半導体デバイスの製造方法 Ceased WO2024095464A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2024554064A JPWO2024095464A1 (https=) 2022-11-04 2022-11-04
PCT/JP2022/041199 WO2024095464A1 (ja) 2022-11-04 2022-11-04 半導体デバイスの製造方法
CN202280095458.2A CN119137731A (zh) 2022-11-04 2022-11-04 半导体元件的制造方法
US18/857,189 US20250329549A1 (en) 2022-11-04 2022-11-04 Semiconductor device manufacturing method
TW112141219A TW202420556A (zh) 2022-11-04 2023-10-27 半導體元件的製造方法

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PCT/JP2022/041199 WO2024095464A1 (ja) 2022-11-04 2022-11-04 半導体デバイスの製造方法

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JP (1) JPWO2024095464A1 (https=)
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WO (1) WO2024095464A1 (https=)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009283607A (ja) * 2008-05-21 2009-12-03 Hitachi Chem Co Ltd ウエハ薄化加工兼用の半導体用接着テープ及びウエハ薄化加工兼用の半導体用接着テープの半導体ウエハ表面への貼り付け方法
JP2015213201A (ja) * 2015-08-25 2015-11-26 日東電工株式会社 半導体装置の製造方法
JP2019033124A (ja) * 2017-08-04 2019-02-28 リンテック株式会社 半導体装置の製造方法、及び接着積層体

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JP2009283607A (ja) * 2008-05-21 2009-12-03 Hitachi Chem Co Ltd ウエハ薄化加工兼用の半導体用接着テープ及びウエハ薄化加工兼用の半導体用接着テープの半導体ウエハ表面への貼り付け方法
JP2015213201A (ja) * 2015-08-25 2015-11-26 日東電工株式会社 半導体装置の製造方法
JP2019033124A (ja) * 2017-08-04 2019-02-28 リンテック株式会社 半導体装置の製造方法、及び接着積層体

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