WO2024093025A1 - 半导体互连结构及其形成方法、半导体封装结构 - Google Patents

半导体互连结构及其形成方法、半导体封装结构 Download PDF

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Publication number
WO2024093025A1
WO2024093025A1 PCT/CN2023/071233 CN2023071233W WO2024093025A1 WO 2024093025 A1 WO2024093025 A1 WO 2024093025A1 CN 2023071233 W CN2023071233 W CN 2023071233W WO 2024093025 A1 WO2024093025 A1 WO 2024093025A1
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conductive
substrate
grooves
connection pad
interconnect structure
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PCT/CN2023/071233
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English (en)
French (fr)
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刘志拯
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长鑫存储技术有限公司
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Publication of WO2024093025A1 publication Critical patent/WO2024093025A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

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  • the present disclosure relates to the field of integrated circuits, and in particular to a semiconductor interconnect structure and a method for forming the same, and a semiconductor packaging structure.
  • Through Silicon Via (TSV) technology is a high-density packaging technology that is gradually replacing the current more mature wire bonding technology and is considered to be the fourth generation packaging technology.
  • Through Silicon Via technology achieves vertical electrical interconnection of through silicon vias by filling conductive materials such as copper, tungsten, and polysilicon.
  • Through Silicon Via technology can reduce the interconnection length, reduce signal delay, and reduce capacitance/inductance through vertical interconnection, achieve low power consumption between chips, high-speed communication, increase bandwidth, and realize miniaturization of device integration.
  • Three-dimensional (3D) packaging based on through silicon via technology has better electrical interconnection performance, wider bandwidth, higher interconnection density, lower power consumption, smaller size, and lighter weight.
  • the technical problem to be solved by the present disclosure is to provide a semiconductor interconnect structure and a method for forming the same, and a semiconductor packaging structure, which can improve the heat dissipation performance and mechanical strength of the semiconductor interconnect structure.
  • a semiconductor interconnection structure which includes: a substrate having a first surface and a second surface arranged opposite to each other; a plurality of conductive pillars independent of each other, arranged in the substrate, and each of the conductive pillars extends from the first surface to the second surface, the first end of the conductive pillar is exposed to the first surface, and the second end of the conductive pillar is exposed to the second surface; a first conductive connection pad, arranged on the first surface of the substrate, the first conductive connection pad includes a mesh structure, the mesh structure includes a plurality of first nodes, each of the first nodes is connected to the first ends of one or more of the conductive pillars, or the first end of each of the conductive pillars is connected to one or more of the first nodes, and the first ends of all the conductive pillars are interconnected through the first conductive connection pad.
  • the first conductive connection pad includes a first pattern extending along a first direction and arranged at intervals along a second direction, and a second pattern extending along the second direction and arranged along the first direction, and the intersection of the first pattern and the second pattern constitutes the first node.
  • the first end of the conductive pillar falls within the first node.
  • a second conductive connection pad is further included.
  • the second conductive connection pad is disposed on the second surface of the substrate and connected to the second end of the conductive column. The second ends of all the conductive columns are interconnected through the second conductive connection pad.
  • the second conductive connection pad comprises a mesh structure
  • the mesh structure comprises a plurality of second nodes, each of the second nodes is connected to the second end of one or more of the conductive pillars, or the second end of each of the conductive pillars is connected to one or more of the second nodes.
  • the second conductive connection pad includes a third pattern extending along the first direction and arranged at intervals along the second direction, and a fourth pattern extending along the second direction and arranged along the first direction, and the intersection of the third pattern and the fourth pattern constitutes the second node.
  • the second end of the conductive pillar falls within the second node.
  • the thickness of the substrate is 30-50 microns.
  • the maximum dimension of the conductive pillar in a cross section parallel to the substrate ranges from 2 to 5 micrometers.
  • the conductive column and the first conductive connection pad are integrally formed.
  • the first surface has a recessed area, the recessed area forms a groove, and the first conductive connection pad is at least partially located in the groove.
  • a seed layer is further included, and the seed layer is disposed between the conductive pillar and the substrate and between the first conductive connection pad and the substrate.
  • An embodiment of the present disclosure also provides a method for forming a semiconductor interconnect structure, which includes: providing a substrate; forming a plurality of through holes and a plurality of grooves in the substrate, wherein the plurality of grooves are connected to form a mesh groove, wherein one intersection of the mesh grooves exposes one or more of the through holes, or one or more intersections of the mesh grooves expose one of the through holes; filling the through holes and the mesh grooves with conductive material to form conductive columns in the through holes and a first conductive connection pad in the mesh groove; and thinning the substrate to expose one end of the conductive column away from the first conductive connection pad.
  • the step of forming the through hole and the mesh groove in the substrate includes: forming via holes in the substrate, the via holes are arranged in an array along a first direction and a second direction; removing part of the thickness of the substrate to form a plurality of first grooves and a plurality of second grooves, the first grooves extend along the second direction and are arranged at intervals along the first direction, the second grooves extend along the first direction and are arranged at intervals along the second direction, the first grooves and the second grooves pass through the via holes, and the intersection area of the first grooves and the second grooves is the intersection point.
  • the step of forming the through hole and the mesh groove in the substrate includes: removing part of the thickness of the substrate to form a plurality of first grooves and a plurality of second grooves, the first grooves extending along the second direction and arranged at intervals along the first direction, the second grooves extending along the first direction and arranged at intervals along the second direction, and the intersection area of the first grooves and the second grooves being the intersection point; at the intersection point, removing the substrate in a direction perpendicular to the substrate to form the through hole.
  • the step before the step of filling the through hole and the mesh groove with conductive material, the step also includes: forming a seed layer on the inner wall of the through hole and the mesh groove; in the step of filling the through hole and the mesh groove with conductive material, the conductive material covers the seed layer and fills the through hole and the mesh groove.
  • the embodiment of the present disclosure also provides a semiconductor packaging structure, which includes the semiconductor interconnection structure as described above.
  • the semiconductor interconnect structure divides a conductive column with a large cross-sectional area into a conductive column array composed of multiple conductive columns with small cross-sectional areas, which greatly increases the surface area of the conductive column and the heat dissipation performance of the semiconductor interconnect structure.
  • the multiple conductive columns are dispersedly arranged in the substrate, and the substrate further supports the conductive columns, thereby increasing the mechanical properties of the semiconductor interconnect structure.
  • the first conductive connection pad is a mesh structure, rather than a one-piece structure, which increases the surface area of the first conductive connection pad and further increases the heat dissipation area of the semiconductor interconnect structure.
  • FIG1A is a top view of a semiconductor interconnect structure provided by a first embodiment of the present disclosure
  • FIG1B is a schematic cross-sectional view along line A-A' in FIG1A ;
  • FIG2 is a perspective schematic diagram of a semiconductor interconnect structure provided by a second embodiment of the present disclosure.
  • 3A is a top view of a semiconductor interconnect structure provided by a second embodiment of the present disclosure.
  • FIG3B is a schematic cross-sectional view along line B-B' in FIG3A;
  • FIG. 4 is a top view of a semiconductor interconnect structure provided by a third embodiment of the present disclosure.
  • FIG. 5A is a top view of a semiconductor interconnect structure provided by a fourth embodiment of the present disclosure.
  • 5B is a top view of a semiconductor interconnect structure provided in accordance with a fifth embodiment of the present disclosure.
  • FIG. 6 is a bottom view of a semiconductor interconnect structure provided by a sixth embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of steps of a method for forming a semiconductor interconnect structure provided by a seventh embodiment of the present disclosure.
  • 8A to 8M are schematic diagrams of semiconductor structures formed by main steps of a method provided in a seventh embodiment of the present disclosure.
  • FIGS. 9A to 9B are schematic diagrams of a semiconductor structure formed by main steps of a method provided in an eighth embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a semiconductor package structure provided by a ninth embodiment of the present disclosure.
  • the semiconductor interconnect structure and its forming method, and the specific implementation of the semiconductor packaging structure provided by the present disclosure are described in detail below in conjunction with the accompanying drawings.
  • the semiconductor packaging structure in this specific implementation can be but is not limited to a DRAM.
  • FIG. 1A is a top view of a semiconductor interconnect structure provided in a first embodiment of the present disclosure
  • FIG. 1B is a schematic cross-sectional view along line A-A' in FIG. 1A.
  • the semiconductor interconnect structure includes a substrate 100, a conductive column 110, and a first conductive connection pad 120.
  • the conductive column 110 penetrates the substrate 100 and is connected to the first conductive connection pad 120 disposed on the first surface 100A of the substrate 100.
  • the conductive column 110 includes but is not limited to a through silicon via structure, which is used to electrically connect the first conductive connection pad 120 to other semiconductor structures.
  • one conductive column can be connected to multiple first conductive connection pads 120.
  • three first conductive connection pads 120 independently disposed are illustrated in FIG. 1A and FIG. 1B, and the three first conductive connection pads 120 independently disposed are all connected to the same conductive column 110.
  • FIG. 2 is a three-dimensional schematic diagram of a semiconductor interconnect structure provided in the second embodiment of the present disclosure
  • FIG. 3A is a top view of the semiconductor interconnect structure provided in the second embodiment of the present disclosure
  • FIG. 3B is a cross-sectional schematic diagram along line B-B’ in FIG. 3A , wherein, in FIG. 2 , in order to clearly show the semiconductor interconnect structure provided in the embodiment of the present disclosure, the substrate 200 is not drawn.
  • the semiconductor interconnect structure includes: a substrate 200 having a first surface 200A and a second surface 200B opposite to each other; a plurality of mutually independent conductive pillars 210 disposed in the substrate 200, and each conductive pillar 210 extends from the first surface 200A to the second surface 200B, a first end 210A of the conductive pillar 210 is exposed to the first surface 200A, and a second end 210B of the conductive pillar 210 is exposed to the second surface 200B; a first conductive connection pad 220 disposed on the first surface 200A of the substrate 200, the first conductive connection pad 220 includes a mesh structure, the mesh structure includes a plurality of first nodes 221, each first node 221 is connected to the first end 210A of one or more conductive pillars 210, or each first end 210A of the conductive pillar 210 is connected to the one or more first nodes 221, and the first ends 210A of all conductive pillars 210 are
  • the semiconductor interconnect structure provided in this embodiment divides a conductive pillar 210 with a large cross-sectional area into a conductive pillar array composed of multiple conductive pillars 210 with small cross-sectional areas, which greatly increases the surface area of the conductive pillars 210 and improves the heat dissipation performance of the semiconductor interconnect structure.
  • the multiple conductive pillars 210 are dispersedly arranged in the substrate 200, and the substrate 200 further supports the conductive pillars 210, thereby increasing the mechanical properties and anti-deformation ability of the semiconductor interconnect structure.
  • the first conductive connection pad 220 is a mesh structure, rather than a one-piece structure, which increases the surface area of the first conductive connection pad 220 and further increases the heat dissipation area of the semiconductor interconnect structure.
  • the mesh structure of the first conductive connection pad 220 can also improve the anti-deformation ability of the conductive pillar array, thereby improving the supporting performance of the semiconductor interconnect structure.
  • the base 200 includes a substrate 201 and a protective layer 202 disposed on the surface of the substrate 201.
  • the protective layer 202 may be an oxide layer or a nitride layer. In other embodiments, the base 200 may also include only the substrate 201.
  • the substrate 201 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate or an SOI substrate, etc.; the substrate 201 may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide or silicon carbide, etc., and the substrate 201 may also be a laminated structure, such as a silicon/silicon germanium laminate, etc.; in addition, the substrate 201 may be an ion-doped substrate, which may be P-type doped or N-type doped; a plurality of peripheral devices may also be formed in the substrate 201, such as field effect transistors, capacitors, inductors and/or diodes, etc. In this embodiment, the substrate 201 is a silicon substrate, and other device structures may also be included therein, such as a transistor structure, a metal wiring structure, etc., but they are not shown because they are irrelevant to the present invention.
  • the first surface 200A of the substrate 200 is the upper surface of the substrate 200
  • the second surface 200B of the substrate 200 is the lower surface of the substrate 200 .
  • the upper surface and the lower surface are disposed opposite to each other.
  • the plurality of conductive pillars 210 are disposed independently of each other, that is, the plurality of conductive pillars 210 do not contact each other.
  • each conductive pillar 210 extends in a direction perpendicular to the first surface 200A of the substrate 200 (such as the Z direction in FIG. 2 ), and the plurality of conductive pillars 210 are disposed in a direction parallel to the first surface 200A of the substrate 200 (such as the X direction in FIG. 2 ) at intervals and are parallel to each other.
  • Each conductive pillar 210 penetrates the substrate 200 in a direction perpendicular to the first surface 200A of the substrate 200 (such as the Z direction in FIG. 2 ), and the first end 210A of the conductive pillar 210 is exposed to the first surface 200A, and the second end 210B of the conductive pillar 210 is exposed to the second surface 200B.
  • the first surface 200A of the substrate 200 has a groove for embedding the first conductive connection pad 220, and the first end 210A of the conductive pillar 210 is exposed to the bottom surface of the groove.
  • the conductive pillar 210 is formed in the substrate 200, it is necessary to form a through hole first, and then form the conductive pillar 210 in the through hole.
  • the aspect ratio of the through hole is affected by the thickness of the substrate 200 and the width requirement of the conductive pillar 210. The thicker the substrate 200 is and the smaller the width requirement of the conductive pillar 210 is, the greater the aspect ratio of the through hole is.
  • the etching material cannot enter all the way to the bottom of the through hole, and the bottom of the through hole is not completely etched, which will form a through hole that is wide at the top and narrow at the bottom, so that the width of the conductive pillar 210 formed in the through hole is also inconsistent; and the deposition of the conductive material forming the conductive pillar 210 at the bottom of the through hole is also insufficient, so that the conductive pillar 210 formed at the bottom of the through hole has defects, affecting the reliability of the conductive pillar 210. Therefore, in some embodiments, the thickness of the substrate 200 (the dimension along the Z direction in FIG. 2 ) is relatively thin.
  • the thickness of the substrate 200 is 30 to 50 microns, so a conductive column 210 with a smaller width (the dimension along the X direction in FIG. 2 ) can be formed.
  • the maximum dimension of the conductive column 210 on a cross section parallel to the substrate 200 ranges from 2 to 5 microns, and there are no problems caused by through holes with a high aspect ratio, thereby ensuring the width consistency and reliability of the conductive column 210 in its extension direction (the dimension along the Z direction in FIG. 2 ).
  • the first conductive connection pad 220 is disposed on the first surface 200A of the substrate 200, that is, the first conductive connection pad 220 protrudes from the substrate 200, while in other embodiments, the first surface 200A of the substrate 200 has a mesh-shaped recessed area, the recessed area forms a groove, and the first conductive connection pad 220 is at least partially located in the groove, that is, the first conductive connection pad 220 extends below the first surface 200A.
  • the first conductive connection pad 220 is completely located in the groove, and the top surface of the first conductive connection pad 220 is flush with the first surface 200A of the substrate 200.
  • the protrusions between the grooves of the substrate 200 can fit into the gaps of the mesh structure of the first conductive connection pad 220, thereby strengthening the mechanical strength of the first conductive connection pad 220, and further improving the mechanical strength of the semiconductor interconnect structure.
  • the first ends 210A of all the conductive pillars 210 are interconnected through the first conductive connection pad 220, and the electrical signal of the first conductive connection pad 220 is transmitted through all the conductive pillars 210, rather than only through one of the conductive pillars 210 or part of the conductive pillars 210, that is, all the conductive pillars 210 are used as the same conductive structure rather than being used as multiple conductive structures.
  • the first conductive connection pad 220 includes a first pattern 222 extending along the first direction and arranged at intervals along the second direction, and a second pattern 223 extending along the second direction and arranged along the first direction, and the intersection of the first pattern 222 and the second pattern 223 constitutes a first node 221.
  • the first direction is perpendicular to the second direction, for example, the first direction is the X direction, and the second direction is the Y direction.
  • the first pattern 222 is a bar pattern extending along the X direction, and a plurality of bar patterns are arranged at intervals along the Y direction.
  • the second pattern 223 is a bar pattern extending along the Y direction, and a plurality of bar patterns are arranged at intervals along the X direction.
  • first graphic 222 and the second graphic 223 are arranged vertically, while in other embodiments, as shown in Figure 4, which is a top view of the semiconductor interconnect structure provided in the third embodiment of the present disclosure, the first graphic 222 and the second graphic 223 are arranged at an acute angle, rather than being arranged vertically at an angle of 90 degrees.
  • a first node 221 is connected to a first end 210A of a conductive pillar 210, and the first node 221 and the conductive pillar 210 are in a one-to-one relationship, while in other embodiments, the first node 221 and the conductive pillar 210 are in a one-to-many or many-to-one relationship.
  • each first node 221 is connected to the first ends 210A of multiple conductive pillars 210, that is, multiple conductive pillars 210 are arranged below each first node 221; for another example, as shown in FIG5B, it is a top view of the semiconductor interconnect structure provided in the fifth embodiment of the present disclosure, the first end 210A of a conductive pillar 210 is connected to multiple first nodes 221, that is, multiple first nodes 221 are arranged above each conductive pillar 210.
  • the first end 210A of the conductive pillar 210 falls within the first node 221, that is, the projection of the conductive pillar 210 on the substrate 201 is located within the projection of the first node 221 on the substrate 201.
  • the first node 221 is connected to the conductive pillar 210 one-to-one, and the first end 210A of the conductive pillar 210 falls within the first node 221, that is, the length W1 of the shortest side of the first node 221 is greater than the diameter D of the conductive pillar 210, so that the conductive pillar 210 can be maximized and the conductive performance of the semiconductor interconnect structure can be improved.
  • the conductive column 210 and the first conductive connection pad 220 are integrally formed, that is, the conductive column 210 and the first conductive connection pad 220 are made in the same process step using the same conductive material, which greatly reduces the contact resistance between the conductive column 210 and the first conductive connection pad 220 and improves the conductive performance of the semiconductor interconnect structure.
  • the semiconductor interconnect structure further includes a seed layer 230, which is disposed between the conductive pillar 210 and the substrate 200 and between the first conductive pad 220 and the substrate 200.
  • the seed layer 230 insulates and isolates the conductive pillar 210 from the substrate 200 and the first conductive pad 220 from the substrate 200.
  • the seed layer 230 may be an oxide layer, such as a silicon oxide layer.
  • other semiconductor structures eg semiconductor devices
  • a second conductive connection pad 240 is provided on the second surface 200B of the substrate 200, the semiconductor structure is connected to the second conductive connection pad 240, and the conductive pillar 210 is connected to the first conductive connection pad 220 through the second conductive connection pad 240.
  • the second conductive connection pad 240 covers the second surface 200B of the substrate 200 and is connected to the second end 210B of the conductive pillar 210, and the second ends 210B of all the conductive pillars 210 are interconnected through the second conductive connection pad 240.
  • the second conductive connection pad 240 is a one-piece structure, while in the sixth embodiment of the present disclosure, the second conductive connection pad 240 includes a mesh structure.
  • FIG. 6, is a bottom view of the semiconductor interconnect structure provided by the sixth embodiment of the present disclosure, wherein the conductive column 210 is blocked by the second conductive connection pad 240.
  • the outline of the conductive column 210 is drawn with a dotted line.
  • the second conductive connection pad 240 includes a mesh structure, and the mesh structure includes a plurality of second nodes 241, each second node 241 is connected to the second end 210B of one or more conductive columns 210, or the second end 210B of each conductive column 210 is connected to one or more second nodes 241.
  • the second conductive connection pad 240 is a mesh structure, rather than a one-piece structure, which increases the surface area of the second conductive connection pad 240, further increases the heat dissipation area of the semiconductor interconnect structure, and at the same time, the mesh structure of the second conductive connection pad 240 can also improve the anti-deformation ability of the conductive column array, thereby improving the supporting performance of the semiconductor interconnect structure.
  • the second conductive connection pad 240 is disposed on the second surface 200B of the substrate 200, that is, the second conductive connection pad 240 protrudes from the substrate 200, while in other embodiments, such as the sixth embodiment, the second surface 200B of the substrate 200 has a recessed area, the recessed area forms a groove, and the second conductive connection pad 240 is at least partially located in the groove, that is, the second conductive connection pad 240 extends below the second surface 200B, for example, in the second embodiment, the second conductive connection pad 240 is completely located in the groove, and the top surface of the second conductive connection pad 240 is flush with the second surface 200B of the substrate 200.
  • the protrusions between the grooves of the substrate 200 can fit into the gaps of the mesh structure of the second conductive connection pad 240, thereby strengthening the mechanical strength of the second conductive connection pad 240, and further improving the mechanical strength of the semiconductor interconnect structure.
  • a second node 241 is connected to the second end 210B of a conductive column 210, and the second node 241 and the conductive column 210 are in a one-to-one relationship. In other embodiments, the second node 241 and the conductive column 210 are in a one-to-many or many-to-one relationship. Please refer to Figures 5A and 5B, which will not be repeated here.
  • the second conductive connection pad 240 includes a third pattern 242 extending along a first direction (such as the X direction in FIG. 6) and arranged at intervals along a second direction (such as the Y direction in FIG. 6), and a fourth pattern 243 extending along the second direction (such as the Y direction in FIG. 6) and arranged along the first direction (such as the X direction in FIG. 6), and the intersection of the third pattern 242 and the fourth pattern 243 constitutes a second node 241.
  • the third pattern 242 and the fourth pattern 243 are arranged vertically, while in other embodiments, the third pattern 242 and the fourth pattern 243 are arranged at an acute angle, rather than being arranged vertically at a 90-degree angle, please refer to FIG. 4.
  • the structure of the second conductive connection pad 240 is the same as that of the first conductive connection pad 220. It is understandable that in other embodiments, the structure of the second conductive connection pad 240 is different from that of the first conductive connection pad 240, which will not be described in detail.
  • the second end 210B of the conductive pillar 210 falls within the second node 241, that is, the projection of the conductive pillar 210 on the substrate 201 is located within the projection of the second node 241 on the substrate 201.
  • the second node 241 is connected to the conductive pillar 210 one-to-one, and the second end 210B of the conductive pillar 210 falls within the second node 241, that is, the length W2 of the shortest side of the second node 241 is greater than the diameter D of the conductive pillar 210, so that the conductive pillar 210 can be maximized and the conductive performance of the semiconductor interconnect structure can be improved.
  • the embodiment of the present disclosure also provides a method for forming a semiconductor interconnect structure.
  • FIG7 is a schematic diagram of the steps of the method for forming a semiconductor interconnect structure, and the method includes: step S70, providing a substrate; step S71, forming a plurality of through holes and a plurality of grooves in the substrate, the plurality of grooves are connected to form a mesh groove, one intersection of the mesh grooves exposes one or more through holes, or one or more intersections of the mesh grooves expose a through hole; step S72, filling the through hole and the mesh groove with conductive material to form a conductive column in the through hole, and forming a first conductive connection pad in the mesh groove; step S73, thinning the substrate to expose one end of the conductive column away from the first conductive connection pad.
  • 8A to 8M are schematic diagrams of semiconductor structures formed by main steps of the method provided in the seventh embodiment of the present disclosure.
  • step S70 providing a substrate 200.
  • the substrate 200 includes a substrate 201 and a protective layer 202 disposed on a surface of the substrate 201.
  • the substrate 200 may also include only the substrate 201.
  • step S71 a plurality of through holes 300 and a plurality of grooves 310 are formed in the substrate 200, the plurality of grooves are connected to form a mesh groove 310, one intersection 310A of the mesh groove 310 exposes one or more through holes 300, or one or more intersections 310A of the mesh groove 310 expose one through hole 300.
  • the through hole 300 extends from the first surface 200A of the substrate 200 to the inside of the substrate 200, and does not penetrate the substrate 200, that is, the through hole 300 is a blind hole.
  • the seventh embodiment of the present disclosure provides a method for forming a through hole 300 in a substrate 200, the method steps comprising:
  • FIG. 8B and FIG. 8C where FIG. 8B is a top view and FIG. 8C is a cross-sectional schematic diagram along the line B-B' in FIG. 8B.
  • a via hole 800 is formed in the substrate 200, and the via holes 800 are arranged in an array along the first direction and the second direction.
  • the first direction is the X direction and the second direction is the Y direction.
  • a mask layer having a pattern corresponding to the via hole 800 can be used as a shield, and the substrate 200 is etched to transfer the pattern of the mask layer to the substrate 200 to form the via hole 800, and then the mask layer is removed.
  • the depth of the via hole 800 can be set according to the height requirement of the conductive column 210 to be formed subsequently.
  • the depth of the via hole 800 is greater than the depth of the conductive column 210 to be formed later, for example, the depth of the via hole 800 is equal to the sum of the height of the conductive column 210 to be formed later and the depth of the first groove 810.
  • first grooves 810 extend along the first direction and are arranged at intervals along the second direction.
  • the second grooves 820 extend along the second direction and are arranged at intervals along the first direction.
  • the first grooves 810 and the second grooves 820 pass through the via hole 800, and the intersection area of the first grooves 810 and the second grooves 820 is the intersection point 310A.
  • FIG. 8D and FIG. 8E wherein FIG. 8D is a top view, and FIG. 8E is a schematic cross-sectional view along the line B-B' in FIG. 8D, where a portion of the thickness of the substrate 200 is removed to form a plurality of first grooves 810.
  • the first grooves 810 extend along a first direction and pass through the vias 800.
  • a mask layer having a pattern corresponding to the first grooves 810 is used as a shield, and the substrate 200 is etched, the pattern of the mask layer is transferred to the substrate 200, the first grooves 810 are formed, and the mask layer is removed.
  • the first direction is perpendicular to the second direction, for example, the first direction is the X direction, and the second direction is the Y direction.
  • FIG. 8F is a top view and FIG. 8G is a cross-sectional schematic diagram along the line B-B' in FIG. 8F.
  • Part of the thickness of the substrate 200 is removed to form a plurality of second grooves 820.
  • the second grooves 820 extend along the second direction and pass through the vias 800.
  • the first grooves 810 and the second grooves 820 intersect to form a mesh groove 310.
  • the intersection area of the first grooves 810 and the second grooves 820 is the intersection point 310A.
  • a mask layer having a pattern corresponding to the second grooves 820 is used as a shield, and the substrate 200 is etched to transfer the pattern of the mask layer to the substrate 200 to form the second grooves 820, and then the mask layer is removed.
  • the eighth embodiment of the present disclosure further provides a method for forming a through hole 300 in a substrate 200.
  • the method for forming a through hole 300 in a substrate 200 includes:
  • Figure 9A is a top view
  • Figure 9B is a cross-sectional schematic diagram along line B-B’ in Figure 9A.
  • Part of the thickness of the substrate 200 is removed to form a plurality of first grooves 810 and a plurality of second grooves 820.
  • the first grooves 810 extend along a first direction (such as the X direction in Figure 9A) and are arranged at intervals along a second direction (such as the Y direction in Figure 9A).
  • the second grooves 820 extend along the second direction (such as the Y direction in Figure 9A) and are arranged at intervals along the first direction (such as the X direction in Figure 9A).
  • the first grooves 810 and the second grooves 820 intersect to form a mesh structure, and the intersection area of the first grooves 810 and the second grooves 820 is the intersection point 310A.
  • a mask layer having a pattern corresponding to the first groove 810 can be used as a shield, and the substrate 200 is etched to transfer the pattern of the mask layer to the substrate 200 to form the first groove 810; a mask layer having a pattern corresponding to the second groove 820 is used as a shield, and the substrate 200 having the first groove 810 is etched to transfer the pattern of the mask layer to the substrate 200 to form the second groove 820; after the second groove 820 is formed, the mask layer is removed.
  • the substrate 200 is removed in a direction perpendicular to the substrate 200 to form the through hole 300.
  • a mask layer having a pattern corresponding to the through hole can be used to cover the surface of the substrate 200, and the mask layer is used as a shield to etch the substrate 200 to form the through hole 300.
  • FIG. 8H and FIG. 8I where FIG. 8H is a top view and FIG. 8I is a cross-sectional schematic diagram along the line B-B' in FIG. 8H.
  • a seed layer 230 is formed on the inner wall of the through hole 300.
  • the seed layer 230 covers the through hole 300 and the inner wall of the mesh groove.
  • the seed layer 230 can be used to insulate and isolate the substrate 200 from the conductive pillar 210 and the first conductive connection pad 220.
  • the seed layer 230 includes but is not limited to an oxide layer, which can be formed by a chemical vapor deposition process or a thermal oxidation process.
  • Step S72 filling the through hole 300 and the mesh groove 310 with a conductive material to form a conductive column 210 in the through hole 300 and a first conductive connection pad 220 in the mesh groove 310.
  • a chemical vapor deposition, atomic layer deposition or other process may be used to deposit the conductive material, and the conductive material fills the through hole 300 and the mesh groove 310.
  • the conductive material covers the surface of the seed layer 230 and fills the through hole 300 and the mesh groove 310.
  • the conductive material also covers the first surface 200A of the substrate 200, and the conductive material is removed by a chemical mechanical polishing process until the first surface 200A of the substrate 200 is stopped to form a first conductive connection pad 220 with a flat surface.
  • the conductive material includes but is not limited to copper.
  • the first conductive connection pad 220 and the conductive column 210 are formed in the same step using the same conductive material, there is no substantial interface between the two, the contact resistance is small, and the connectivity is better, which greatly improves the electrical and mechanical properties of the semiconductor interconnect structure.
  • FIG. 8L is a cross-sectional schematic diagram, step S73, thinning the substrate 200 to expose one end of the conductive pillar 210 away from the first conductive connection pad 220.
  • the substrate 200 can be thinned by chemical mechanical polishing or other processes until the second end 210B of the conductive pillar 210 is exposed, so as to facilitate subsequent electrical connection between other semiconductor structures and the conductive pillar 210.
  • the second end 210B of the conductive pillar 210 is exposed to the second surface 200B of the substrate 200.
  • FIG. 8M is a cross-sectional schematic diagram.
  • a step of forming a second conductive connection pad 240 on the second surface 200B of the substrate 200 is further included.
  • a conductive layer can be directly formed on the second surface 200B of the substrate 200, and the conductive layer can be patterned to form the second conductive connection pad 240.
  • the conductive column 210 and the first conductive connection pad 220 can be formed in the same step by only using a one-step etching process. Compared with the conductive column 210 and the first conductive connection pad 220 being formed in different steps by using a two-step etching process, the process is simpler and damage to the connection interface between the conductive column 210 and the first conductive connection pad 220 by the etching process is avoided, thereby improving the electrical performance, mechanical performance and stability of the semiconductor interconnect structure.
  • the present disclosure also provides a semiconductor packaging structure, which includes the semiconductor interconnect structure as above.
  • Figure 10 is a schematic diagram of the semiconductor packaging structure provided by the ninth embodiment of the present disclosure.
  • the semiconductor packaging structure includes a first semiconductor structure 1, a semiconductor interconnect structure 2 and a second semiconductor structure 3.
  • the first semiconductor structure 1 is electrically connected to the second semiconductor structure 3 through the semiconductor interconnect structure 2.
  • the third conductive connection pad 10 of the first semiconductor structure 1 is connected to the third conductive connection pad 30 of the second semiconductor structure 3 through the second conductive connection pad 240, the conductive column 210 and the first conductive connection pad 220 of the semiconductor interconnect structure 2.
  • the first semiconductor structure 1 and the second semiconductor structure 3 include but are not limited to circuit boards, packaging substrates, logic chips, memory chips, etc.
  • the semiconductor packaging structure uses the semiconductor interconnect structure 2 as a connection intermediate layer between two semiconductor structures, and its heat dissipation performance and mechanical performance are greatly improved, and the stability of the semiconductor packaging structure is improved.

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Abstract

本公开实施例提供一种半导体互连结构，其包括：基底，具有相对设置的第一表面及第二表面；多个彼此独立的导电柱，设置在所述基底内，一所述导电柱自所述第一表面延伸至所述第二表面，所述导电柱的第一端暴露于所述第一表面，所述导电柱的第二端暴露于所述第二表面；第一导电连接垫，设置在所述基底的第一表面上，所述第一导电连接垫包括网状结构，所述网状结构包括多个第一节点，每一所述第一节点与一个或多个所述导电柱的第一端连接，或者每一所述导电柱的第一端与一个或多个所述第一节点连接，所有所述导电柱的第一端通过所述第一导电连接垫互连。本公开实施例提供的半导体互连结构具有良好的散热性能及机械性能。

Description

半导体互连结构及其形成方法、半导体封装结构
相关申请引用说明
本申请要求于2022年11月04日递交的中国专利申请号202211375324.4、申请名为“半导体互连结构及其形成方法、半导体封装结构”的优先权，其全部内容以引用的形式附录于此。
技术领域
本公开涉及集成电路领域，尤其涉及一种半导体互连结构及其形成方法、半导体封装结构。
背景技术
硅通孔技术(Through Silicon Via，TSV)技术是一项高密度封装技术，正在逐渐取代目前工艺比较成熟的引线键合技术，被认为是第四代封装技术。硅通孔技术通过铜、钨、多晶硅等导电物质的填充，实现硅通孔的垂直电气互连。硅通孔技术可以通过垂直互连减小互联长度，减小信号延迟，降低电容/电感，实现芯片间的低功耗，高速通讯，增加宽带和实现器件集成的小型化。基于硅通孔技术的三维(3D)封装具有更好的电气互连性能、更宽的带宽、更高的互连密度、更低的功耗、更小的尺寸及更轻的质量。
随着三维(3D)封装的日益发展，硅通孔技术变得更重要。硅通孔的性能直接关系到三维封装的可靠性及良率等问题，为了提高三维封装的可靠性及良率，需要提供具有高稳定性和高可靠性的硅通孔。因此，如何提高硅通孔的稳定性和可靠性成为目前亟需解决的问题。
发明内容
本公开所要解决的技术问题是，提供一种半导体互连结构及其形成方法、半导体封装结构，其能够提高半导体互连结构的散热性能及机械强度。
为了解决上述问题，本公开提供了一种半导体互连结构，其包括：基底，具有相对设置的第一表面及第二表面；多个彼此独立的导电柱，设置在所述基底内，且每一所述导电柱自所述第一表面延伸至所述第二表面，所述导电柱的第一端暴露于所述第一表面，所述导电柱的第二端暴露于所述第二表面；第一导电连接垫，设置在所述基底的第一表面上，所述第一导电连接垫包括网状结构，所述网状结构包括多个第一节点，每一所述第一节点与一个或多个所述导电柱的第一端连接，或者每一所述导电柱的第一端与一个或多个所述第一节点连接，所有所述导电柱的第一端通过所述第一导电连接垫互连。
在一实施例中，所述第一导电连接垫包括沿第一方向延伸且沿第二方向间隔排列的第一图形、以及沿所述第二方向延伸且沿所述第一方向排列的第二图形，所述第一图形与所述第二图形相交处构成所述第一节点。
在一实施例中，所述导电柱的第一端落在所述第一节点内。
在一实施例中，还包括第二导电连接垫，所述第二导电连接垫设置在所述基底的第二表面，且与所 述导电柱的第二端连接，所有所述导电柱的第二端通过所述第二导电连接垫互连。
在一实施例中，所述第二导电连接垫包括网状结构，所述网状结构包括多个第二节点，每一所述第二节点与一个或多个所述导电柱的第二端连接，或者每一所述导电柱的第二端与一个或多个所述第二节点连接。
在一实施例中，所述第二导电连接垫包括沿第一方向延伸且沿第二方向间隔排列的第三图形、以及沿所述第二方向延伸且沿所述第一方向排列的第四图形，所述第三图形与所述第四图形相交处构成所述第二节点。
在一实施例中，所述导电柱的第二端落在所述第二节点内。
在一实施例中，所述基底的厚度为30～50微米。
在一实施例中，所述导电柱在平行于所述基底的剖面上的最大尺寸的范围为2～5微米。
在一实施例中，所述导电柱与所述第一导电连接垫一体成型。
在一实施例中，所述第一表面具有凹陷区域，所述凹陷区域形成沟槽，所述第一导电连接垫至少部分位于所述沟槽内。
在一实施例中，还包括种子层，所述种子层设置在所述导电柱与所述基底之间及所述第一导电连接垫与所述基底之间。
本公开实施例还提供一种半导体互连结构的形成方法，其包括：提供基底；在所述基底内形成多个通孔以及多条沟槽，所述多条沟槽连接成网状沟槽述网状沟槽的一个交叉点暴露一个或多个所述通孔，或者所述网状沟槽的一个或多个交叉点暴露一个所述通孔；在所述通孔与所述网状沟槽内填充导电材料，以在所述通孔内形成导电柱，在所述网状沟槽内形成第一导电连接垫；减薄所述基底，暴露所述导电柱背离所述第一导电连接垫的一端。
在一实施例中，在所述基底内形成所述通孔与所述网状沟槽的步骤包括：在所述基底内形成过孔，所述过孔沿第一方向及第二方向阵列排布；去除所述基底的部分厚度形成多条第一沟槽与多条第二沟槽，所述第一沟槽沿所述第二方向延伸且沿所述第一方向间隔排布，所述第二沟槽沿所述第一方向延伸且沿所述第二方向间隔排布，所述第一沟槽与所述第二沟槽经过所述过孔，所述第一沟槽与所述第二沟槽的交叉区域为所述交叉点。
在一实施例中，在所述基底内形成所述通孔与所述网状沟槽的步骤包括：去除所述基底的部分厚度形成多条第一沟槽与多条第二沟槽，所述第一沟槽沿所述第二方向延伸且沿所述第一方向间隔排布，所述第二沟槽沿所述第一方向延伸且沿所述第二方向间隔排布，所述第一沟槽与所述第二沟槽的交叉区域为所述交叉点；在所述交叉点，沿垂直所述基底方向去除所述基底形成所述通孔。
在一实施例中，在所述通孔与所述网状沟槽内填充导电材料的步骤之前还包括：在所述通孔与所述网状沟槽内壁形成种子层；在所述通孔与所述网状沟槽内填充导电材料的步骤中，所述导电材料覆盖所述种子层，且填满所述通孔与所述网状沟槽。
本公开实施例还提供一种半导体封装结构，其包括如上所述的半导体互连结构。
本公开实施例提供的半导体互连结构及其形成方法、半导体封装结构中，半导体互连结构将一个横截面积大的导电柱分隔为由多个横截面积小的导电柱构成的导电柱阵列，大大提高了所述导电柱的表面积，增加了所述半导体互连结构的散热性能，且多个所述导电柱分散设置在所述基底中，所述基底对所述导电柱起到进一步的支撑作用，进而增加了所述半导体互连结构的机械性能。另外，所述第一导电连接垫为网状结构，而并非是一片式结构，增大了所述第一导电连接垫的表面积，也进一步增大了所述半导体互连结构的散热面积。
附图说明
图1A是本公开第一实施例提供的半导体互连结构的俯视图；
图1B是沿图1A中A-A’线的截面示意图；
图2是本公开第二实施例提供的半导体互连结构的立体示意图；
图3A是本公开第二实施例提供的半导体互连结构的俯视图；
图3B是沿图3A中B-B’线的截面示意图；
图4是本公开第三实施例提供的半导体互连结构的俯视图；
图5A是本公开第四实施例提供的半导体互连结构的俯视图；
图5B是本公开第五实施例提供的半导体互连结构的俯视图；
图6是本公开第六实施例提供的半导体互连结构的仰视图；
图7是本公开第七实施例提供的半导体互连结构的形成方法的步骤示意图；
图8A～图8M是本公开第七实施例提供的方法的主要步骤形成的半导体结构示意图；
图9A～图9B是本公开第八实施例提供的方法的主要步骤形成的半导体结构示意图；
图10是本公开第九实施例提供的半导体封装结构的示意图。
具体实施方式
下面结合附图对本公开提供的半导体互连结构及其形成方法、半导体封装结构的具体实施方式做详细说明。本具体实施方式中的半导体封装结构可以是但不限于DRAM。
图1A是本公开第一实施例提供的半导体互连结构的俯视图，图1B是沿图1A中A-A’线的截面示意图。请参阅图1A及图1B，半导体互连结构包括基底100、导电柱110及第一导电连接垫120。导电 柱110贯穿基底100，并与设置在基底100第一表面100A上的第一导电连接垫120连接。导电柱110包括但不限于硅通孔结构，其用于将第一导电连接垫120与其他半导体结构电连接。在第一实施例中，一个导电柱可与多个第一导电连接垫120连接，例如在图1A及图1B中绘示了三个彼此独立设置的第一导电连接垫120，三个彼此独立设置的第一导电连接垫120均与同一导电柱110连接。
发明人发现，第一实施例提供的半导体互连结构散热性能及机械性能较差，无法满足要求。发明人经进一步研究，提供一种半导体互连结构，其能够提高半导体互连结构的散热性能及机械性能。
图2是本公开第二实施例提供的半导体互连结构的立体示意图，图3A是本公开第二实施例提供的半导体互连结构的俯视图，图3B是沿图3A中B-B’线的截面示意图，其中，在图2中，为了清楚显示本公开实施例提供的半导体互连结构，基底200未被绘示。请参阅图2、图3A及图3B，半导体互连结构包括：基底200，具有相对设置的第一表面200A及第二表面200B；多个彼此独立的导电柱210，设置在基底200内，且每一导电柱210自第一表面200A延伸至第二表面200B，导电柱210的第一端210A暴露于第一表面200A，导电柱210的第二端210B暴露于第二表面200B；第一导电连接垫220，设置在基底200的第一表面200A上，第一导电连接垫220包括网状结构，网状结构包括多个第一节点221，每一第一节点221与一个或多个导电柱210的第一端210A连接，或者每一导电柱210的第一端210A与一个或多个第一节点221连接，所有导电柱210的第一端210A通过第一导电连接垫220互连。在俯视图(例如图2)中，导电柱210被第一导电连接垫220遮挡，为了清楚说明本公开实施例技术方案，采用虚线绘示导电柱210轮廓。
本实施例提供的半导体互连结构将一个横截面积大的导电柱210分隔为由多个横截面积小的导电柱210构成的导电柱阵列，大大提高了导电柱210的表面积，增加了半导体互连结构的散热性能，且多个导电柱210分散设置在基底200中，基底200对导电柱210起到进一步的支撑作用，进而增加了半导体互连结构的机械性能及抗变形的能力。另外，第一导电连接垫220为网状结构，而并非是一片式结构，增大了第一导电连接垫220的表面积，也进一步增大了半导体互连结构的散热面积，同时，第一导电连接垫220的网状结构还可以提高导电柱阵列的抗变形能力，从而提高半导体互连结构的支撑性能。
在本实施例中，基底200包括衬底201及设置在衬底201表面的保护层202，保护层202可为氧化物层或者氮化物层。在另一些实施例中，基底200也可仅包括衬底201。
衬底201可以包括硅衬底、锗(Ge)衬底、锗化硅(SiGe)衬底或SOI衬底等；衬底201还可以为包括其他元素半导体或化合物半导体的衬底，例如砷化镓、磷化铟或碳化硅等，衬底201还可以为叠层结构，例如硅/锗硅叠层等；另外，衬底201可以为进行离子掺杂后的衬底，可以进行P型掺杂，也可以进行N型掺杂；衬底201中还可以形成有多个外围器件，如场效应晶体管、电容、电感和/或二极管等。本实施 例中，衬底201为硅衬底，其内部还可以包括其他器件结构，例如晶体管结构、金属布线结构等，但由于与本发明无关，所以不绘示。
在本实施例中，基底200的第一表面200A为基底200的上表面，基底200的第二表面200B为基底200的下表面，上表面与下表面相对设置。
多个导电柱210彼此独立设置，即多个导电柱210彼此互不接触。在本实施例中，每一导电柱210沿垂直基底200第一表面200A的方向(如图2中Z方向)延伸，且多个导电柱210沿平行基底200第一表面200A的方向(如图2中X方向)间隔设置，且彼此平行。
每一导电柱210沿垂直基底200第一表面200A的方向(如图2中Z方向)贯穿基底200，导电柱210的第一端210A暴露于第一表面200A，导电柱210的第二端210B暴露于第二表面200B。在本实施例中，基底200的第一表面200A具有凹槽，用于嵌入第一导电连接垫220，则导电柱210的第一端210A暴露于凹槽底面。
若是在基底200中形成导电柱210，则需要先形成通孔，再在通孔中形成导电柱210，而通孔的深宽比受到基底200厚度与导电柱210宽度要求的影响，基底200越厚、导电柱210宽度要求越小，通孔的深宽比越大。对于高深宽比的通孔，刻蚀材料无法全部进入至通孔底部，通孔底部刻蚀不完全，则会形成上宽下窄的通孔，使得形成在通孔内的导电柱210宽度也不一致；且形成导电柱210的导电材料在通孔底部的沉积也不充分，使得在通孔底部形成的导电柱210存在缺陷，影响导电柱210的可靠性。因此，在一些实施例中，基底200的厚度(沿图2中Z方向的尺寸)较薄，例如，在第二实施例中，基底200的厚度为30～50微米，则能够形成宽度(沿图2中X方向的尺寸)较小的导电柱210，例如，在第二实施例中，导电柱210在平行于基底200的剖面上的最大尺寸的范围为2～5微米，不存在高深宽比的通孔带来的问题，进而保证了导电柱210在其延伸方向(沿图2中Z方向的尺寸)上的宽度一致性及可靠性。
在一些实施例中，第一导电连接垫220设置在基底200的第一表面200A上，即第一导电连接垫220突出于基底200，而在另一些实施例中，基底200的第一表面200A具有网状的凹陷区域，凹陷区域形成沟槽，第一导电连接垫220至少部分位于沟槽内，即第一导电连接垫220延伸至第一表面200A下，例如在第二实施例中，第一导电连接垫220完全位于沟槽内，第一导电连接垫220的顶面与基底200的第一表面200A平齐。由于第一导电连接垫220嵌入基底200内，基底200的沟槽之间的凸起能够嵌合第一导电连接垫220网状结构的空隙，从而加强了第一导电连接垫220的机械强度，进而提高了半导体互连结构的机械强度。
在本公开实施例中，所有导电柱210的第一端210A通过第一导电连接垫220互连，第一导电连接垫220的电信号经所有导电柱210传输，而并非是仅经其中一个导电柱210或者部分导电柱210传输， 即所有导电柱210作为同一导电结构使用，而并非是作为多个导电结构使用。
在一些实施例中，第一导电连接垫220包括沿第一方向延伸且沿第二方向间隔排列的第一图形222、以及沿第二方向延伸且沿第一方向排列的第二图形223，第一图形222与第二图形223相交处构成第一节点221。在本实施例中，第一方向与第二方向垂直，例如第一方向为X方向，第二方向为Y方向，第一图形222为条形图形，其沿X方向延伸，且多个条形图形沿Y方向间隔排列，第二图形223为条形图形，其沿Y方向延伸，且多个条形图形沿X方向间隔排列。
在本实施例中，第一图形222与第二图形223垂直设置，而在另一些实施例中，如图4所示，其为本公开第三实施例提供的半导体互连结构的俯视图，其中，第一图形222与第二图形223呈锐角夹角设置，而并非是呈90度夹角垂直设置。
在本实施例中，一个第一节点221与一个导电柱210的第一端210A连接，接第一节点221与导电柱210为一对一的关系，而在另一些实施例中，第一节点221与导电柱210为一对多或者多对一的关系。例如，如图5A所示，其为本公开第四实施例提供的半导体互连结构的俯视图，每一第一节点221与多个导电柱210的第一端210A连接，即在每一第一节点221的下方设置有多个导电柱210；再例如，如图5B所示，其为本公开第五实施例提供的半导体互连结构的俯视图，一个导电柱210的第一端210A与多个第一节点221连接，即在每一个导电柱210的上方设置有多个第一节点221。
在一些实施例中，导电柱210的第一端210A落在第一节点221内，即导电柱210在衬底201上的投影位于第一节点221在衬底201上的投影内。具体地说，在本实施例中，第一节点221与导电柱210一对一连接，导电柱210的第一端210A落在第一节点221内，即第一节点221最短边的长度W1大于导电柱210的直径D，则可使得导电柱210被最大化应用，提高半导体互连结构的导电性能。
在一些实施例中，导电柱210与第一导电连接垫220一体成型，即导电柱210与第一导电连接垫220在同一步工艺中采用同一导电材料一步制成，大大降低了导电柱210与第一导电连接垫220之间的接触电阻，提高了半导体互连结构的导电性能。
在一些实施例中，半导体互连结构还包括种子层230，种子层230设置在导电柱210与基底200之间及第一导电连接垫220与基底200之间。种子层230绝缘隔离导电柱210与基底200及第一导电连接垫220与基底200。种子层230可为氧化物层，例如氧化硅层。
在基底200的第二表面200B，其他半导体结构(例如半导体器件)可与导电柱210的第二端210B电连接，进而实现半导体结构与第一导电连接垫220之间的电连接。
为了进一步提高半导体结构与导电柱210第二端连接的可靠性，在基底200的第二表面200B设置有第二导电连接垫240，半导体结构与第二导电连接垫240连接，且通过第二导电连接垫240、导电柱 210与第一导电连接垫220连接。第二导电连接垫240覆盖基底200的第二表面200B，且与导电柱210的第二端210B连接，所有导电柱210的第二端210B通过第二导电连接垫240互连。
在第二实施例中，第二导电连接垫240为一片式结构，而在本公开第六实施例中，第二导电连接垫240包括网状结构。请参阅图6，其为本公开第六实施例提供的半导体互连结构的仰视图，其中，导电柱210被第二导电连接垫240遮挡，为了清楚说明本公开实施例技术方案，采用虚线绘示导电柱210轮廓。第二导电连接垫240包括网状结构，网状结构包括多个第二节点241，每一第二节点241与一个或多个导电柱210的第二端210B连接，或者每一导电柱210的第二端210B与一个或多个第二节点241连接。第二导电连接垫240为网状结构，而并非是一片式结构，增大了第二导电连接垫240的表面积，进一步增大了半导体互连结构的散热面积，同时，第二导电连接垫240的网状结构还可以提高导电柱阵列的抗变形能力，从而提高半导体互连结构的支撑性能。
在一些实施例中，第二导电连接垫240设置在基底200的第二表面200B上，即第二导电连接垫240突出于基底200，而在另一些实施例中，例如在第六实施例中，基底200的第二表面200B具有凹陷区域，凹陷区域形成沟槽，第二导电连接垫240至少部分位于沟槽内，即第二导电连接垫240延伸至第二表面200B下，例如在第二实施例中，第二导电连接垫240完全位于沟槽内，第二导电连接垫240的顶面与基底200的第二表面200B平齐。由于第二导电连接垫240嵌入基底200内，基底200的沟槽之间的凸起能够嵌合第二导电连接垫240网状结构的空隙，从而加强了第二导电连接垫240的机械强度，进而提高了半导体互连结构的机械强度。
在本实施例中，一个第二节点241与一个导电柱210的第二端210B连接，第二节点241与导电柱210为一对一的关系，而在另一些实施例中，第二节点241与导电柱210为一对多或者多对一的关系，请参考图5A及图5B，此处不再赘述。
第二导电连接垫240包括沿第一方向(如图6中X方向)延伸且沿第二方向(如图6中Y方向)间隔排列的第三图形242、以及沿第二方向(如图6中Y方向)延伸且沿第一方向(如图6中X方向)排列的第四图形243，第三图形242与第四图形243相交处构成第二节点241。在本实施例中，第三图形242与第四图形243垂直设置，而在另一些实施例中，第三图形242与第四图形243呈锐角夹角设置，而并非是呈90度夹角垂直设置，请参考图4。
在本实施例中，第二导电连接垫240的结构与第一导电连接垫220的结构相同。可以理解的是，在另一些实施例中，第二导电连接垫240的结构与第二导电连接垫240的结构不同，不再赘述。
在一些实施例中，导电柱210的第二端210B落在第二节点241内，即导电柱210在衬底201上的投影位于第二节点241在衬底201上的投影内。具体地说，在本实施例中，第二节点241与导电柱210 一对一连接，导电柱210的第二端210B落在第二节点241内，即第二节点241最短边的长度W2大于导电柱210的直径D，则可使得导电柱210被最大化应用，提高半导体互连结构的导电性能。
本公开实施例还提供一种半导体互连结构的形成方法。请参阅图7，其为半导体互连结构的形成方法的步骤示意图，方法包括：步骤S70，提供基底；步骤S71，在基底内形成多个通孔以及多条沟槽，多条沟槽连接成网状沟槽，网状沟槽的一个交叉点暴露一个或多个通孔，或者网状沟槽的一个或多个交叉点暴露一个通孔；步骤S72，在通孔与网状沟槽内填充导电材料，以在通孔内形成导电柱，在网状沟槽内形成第一导电连接垫；步骤S73，减薄基底，暴露导电柱背离第一导电连接垫的一端。
图8A～图8M是本公开第七实施例提供的方法的主要步骤形成的半导体结构示意图。
请参阅图7及图8A，步骤S70，提供基底200。在本实施例中，基底200包括衬底201及设置在衬底201表面的保护层202。在另一些实施例中，基底200也可仅包括衬底201。
请参阅图7、图8F及图8G，步骤S71，在基底200内形成多个通孔300以及多条沟槽310，多条沟槽连接成网状沟槽310，网状沟槽310的一个交叉点310A暴露一个或多个通孔300，或者网状沟槽310的一个或多个交叉点310A暴露一个通孔300。在该步骤中，通孔300自基底200的第一表面200A向基底200内部延伸，并未贯穿基底200，即通孔300为盲孔。
作为示例，本公开第七实施例提供一种在基底200内形成通孔300的方法，方法步骤包括：
请参阅图8B及图8C，其中，图8B为俯视图，图8C为沿图8B中B-B’线的截面示意图，在基底200内形成过孔800，过孔800沿第一方向及第二方向阵列排布。在本实施例中，第一方向为X方向，第二方向为Y方向。在该步骤中可采用具有与过孔800对应的图案的掩膜层作为遮挡，并对基底200进行刻蚀，将掩膜层的图案转移到基底200中，形成过孔800，并去除掩膜层。过孔800的深度可根据后续需要形成的导电柱210的高度要求而设定。在本实施例中，由于后续需要在过孔端部形成第一沟槽810及第二沟槽820，因此，过孔800的深度大于后续需要形成的导电柱210的深度，例如，过孔800的深度等于后续形成的导电柱210的高度与第一沟槽810的深度之和。
形成过孔800后，去除基底200的部分厚度形成多条第一沟槽810与多条第二沟槽820，第一沟槽810沿第一方向延伸且沿第二方向间隔排布，第二沟槽820沿第二方向延伸且沿第一方向间隔排布，第一沟槽810与第二沟槽820经过过孔800，第一沟槽810与第二沟槽820的交叉区域为交叉点310A。
具体地说，请参阅图8D及图8E，其中，图8D为俯视图，图8E为沿图8D中B-B’线的截面示意图，去除基底200的部分厚度形成多条第一沟槽810。第一沟槽810沿第一方向延伸且经过过孔800。在该步骤中，采用具有与第一沟槽810对应的图案的掩膜层作为遮挡，并对基底200进行刻蚀，将掩膜层的图案转移到基底200中，形成第一沟槽810，并去除掩膜层。在本实施例中，第一方向与第二方向垂 直，例如第一方向为X方向，第二方向为Y方向。
请参阅图8F及图8G，其中，图8F为俯视图，图8G为沿图8F中B-B’线的截面示意图，去除基底200的部分厚度形成多条第二沟槽820，第二沟槽820沿第二方向延伸且经过过孔800，第一沟槽810与第二沟槽820交叉构成网状沟槽310，第一沟槽810与第二沟槽820的交叉区域为交叉点310A。在该步骤中，采用具有与第二沟槽820对应的图案的掩膜层作为遮挡，并对基底200进行刻蚀，将掩膜层的图案转移到基底200中，形成第二沟槽820，并去除掩膜层。
作为示例，本公开第八实施例还提供一种在基底200内形成通孔300的方法，请参阅图9A～图9B，在基底200内形成通孔300的方法包括：
请参阅图9A及图9B，其中，图9A为俯视图，图9B为沿图9A中B-B’线的截面示意图，去除基底200的部分厚度形成多条第一沟槽810与多条第二沟槽820，第一沟槽810沿第一方向(如图9A中X方向)延伸且沿第二方向(如图9A中Y方向)间隔排布，第二沟槽820沿第二方向(如图9A中Y方向)延伸且沿第一方向(如图9A中X方向)间隔排布，第一沟槽810与第二沟槽820交叉构成网状结构，第一沟槽810与第二沟槽820的交叉区域为交叉点310A。
在该步骤中，可采用具有与第一沟槽810对应的图案的掩膜层作为遮挡，并对基底200进行刻蚀，将掩膜层的图案转移到基底200中，形成第一沟槽810；采用具有与第二沟槽820对应的图案的掩膜层作为遮挡，并对具有第一沟槽810的基底200进行刻蚀，将掩膜层的图案转移到基底200中，形成第二沟槽820；形成第二沟槽820后去除掩膜层。
在形成第一沟槽810及第二沟槽820后，在交叉点310A，沿垂直基底200方向去除基底200形成通孔300。例如，在本实施例中，可采用具有与通孔对应图案的掩膜层覆盖基底200表面，并以掩膜层作为遮挡，刻蚀基底200，形成通孔300。
请参阅图8H及图8I，其中，图8H为俯视图，图8I为沿图8H中B-B’线的截面示意图。在形成通孔300及网状沟槽310后，在通孔300内壁形成种子层230。种子层230覆盖通孔300及网状沟槽内壁，种子层230可用于绝缘隔离基底200与导电柱210及第一导电连接垫220。种子层230包括但不限于氧化物层，可通过化学气相沉积工艺或者热氧化工艺等方法形成，
请参阅图7及图8J及图8K，其中，图8J为俯视图，图8K为沿图8J中B-B’线的截面示意图。步骤S72，在通孔300与网状沟槽310内填充导电材料，以在通孔300内形成导电柱210，在网状沟槽310内形成第一导电连接垫220。在该步骤中可采用化学气相沉积、原子层沉积等工艺沉积导电材料，导电材料填满通孔300与网状沟槽310。在该实施例中，导电材料覆盖种子层230表面且填满通孔300与网状沟槽310。在一些实施例中，导电材料还覆盖基底200的第一表面200A，采用化学机械研磨工艺去 除导电材料至基底200的第一表面200A停止，以形成具有平坦表面的第一导电连接垫220。导电材料包括但不限于铜。
由于第一导电连接垫220与导电柱210在同一步骤中采用同一导电材料形成，两者之间不存在实质的交界面，接触电阻较小，且连接性更好，大大提高了半导体互连结构的电学性能及机械性能。
请参阅图7及图8L，图8L为截面示意图，步骤S73，减薄基底200，暴露导电柱210背离第一导电连接垫220的一端。在该步骤中，可采用化学机械研磨等工艺减薄基底200，至暴露出导电柱210的第二端210B为止，以便于后续其他半导体结构与导电柱210的电连接。在该步骤之后，导电柱210的第二端210B暴露于基底200的第二表面200B。
请参阅图8M，其为截面示意图，在一些实施例中，在减薄基底200之后，还包括在基底200的第二表面200B形成第二导电连接垫240的步骤。在一些实施例中，可直接在基底200的第二表面200B形成导电层，并对导电层进行图案化处理形成第二导电连接垫240。
本公开实施例提供的半导体互连结构的形成方法中，导电柱210及第一导电连接垫220在同一步骤中仅采用一步刻蚀工艺即可形成，则相对于导电柱210与第一导电连接垫220在不同步骤中采用两步刻蚀工艺形成而言，工艺更简单，也避免了刻蚀工艺对导电柱210与第一导电连接垫220连接界面的破坏，提高了半导体互连结构的电学性能、机械性能及稳定性。
本公开实施例还提供一种半导体封装结构，其包括如上的半导体互连结构。请参阅图10，其为本公开第九实施例提供的半导体封装结构的示意图。半导体封装结构包括第一半导体结构1、半导体互连结构2及第二半导体结构3。第一半导体结构1通过半导体互连结构2与第二半导体结构3电连接。具体地说，第一半导体结构1的第三导电连接垫10通过半导体互连结构2的第二导电连接垫240、导电柱210及第一导电连接垫220与第二半导体结构3的第三导电连接垫30连接。第一半导体结构1及第二半导体结构3包括但不限于电路板、封装基板、逻辑芯片、存储芯片等。
半导体封装结构利用半导体互连结构2作为两个半导体结构之间的连接中介层，其散热性能、机械性能被大大提高，半导体封装结构的稳定性得到改善。
以上仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (17)

  1. 一种半导体互连结构，包括：
    基底，具有相对设置的第一表面及第二表面；
    多个彼此独立的导电柱，设置在所述基底内，且每一所述导电柱自所述第一表面延伸至所述第二表面，所述导电柱的第一端暴露于所述第一表面，所述导电柱的第二端暴露于所述第二表面；
    第一导电连接垫，设置在所述基底的第一表面上，所述第一导电连接垫包括网状结构，所述网状结构包括多个第一节点，每一所述第一节点与一个或多个所述导电柱的第一端连接，或者每一所述导电柱的第一端与一个或多个所述第一节点连接，所有所述导电柱的第一端通过所述第一导电连接垫互连。
  2. 根据权利要求1所述的半导体互连结构，其中，所述第一导电连接垫包括沿第一方向延伸且沿第二方向间隔排列的第一图形、以及沿所述第二方向延伸且沿所述第一方向排列的第二图形，所述第一图形与所述第二图形相交处构成所述第一节点。
  3. 根据权利要求1所述的半导体互连结构，其中，所述导电柱的第一端落在所述第一节点内。
  4. 根据权利要求1所述的半导体互连结构，其中，还包括第二导电连接垫，所述第二导电连接垫设置在所述基底的第二表面，且与所述导电柱的第二端连接，所有所述导电柱的第二端通过所述第二导电连接垫互连。
  5. 根据权利要求4所述的半导体互连结构，其中，所述第二导电连接垫包括网状结构，所述网状结构包括多个第二节点，每一所述第二节点与一个或多个所述导电柱的第二端连接，或者每一所述导电柱的第二端与一个或多个所述第二节点连接。
  6. 根据权利要求5所述的半导体互连结构，其中，所述第二导电连接垫包括沿第一方向延伸且沿第二方向间隔排列的第三图形、以及沿所述第二方向延伸且沿所述第一方向排列的第四图形，所述第三图形与所述第四图形相交处构成所述第二节点。
  7. 根据权利要求5所述的半导体互连结构，其中，所述导电柱的第二端落在所述第二节点内。
  8. 根据权利要求1所述的半导体互连结构，其中，所述基底的厚度为30～50微米。
  9. 根据权利要求8所述的半导体互连结构，其中，所述导电柱在平行于所述基底的剖面上的最大尺寸的范围为2～5微米。
  10. 根据权利要求1所述的半导体互连结构，其中，所述导电柱与所述第一导电连接垫一体成型。
  11. 根据权利要求1至10任一项所述的半导体互连结构，其中，所述第一表面具有凹陷区域，所述凹陷 区域形成沟槽，所述第一导电连接垫至少部分位于所述沟槽内。
  12. 根据权利要求1至10任一项所述的半导体互连结构，其中，还包括种子层，所述种子层设置在所述导电柱与所述基底之间及所述第一导电连接垫与所述基底之间。
  13. 一种半导体互连结构的形成方法，包括：
    提供基底；
    在所述基底内形成多个通孔以及多条沟槽，所述多条沟槽连接成网状沟槽，所述网状沟槽的一个交叉点暴露一个或多个所述通孔，或者所述网状沟槽的一个或多个交叉点暴露一个所述通孔；
    在所述通孔与所述网状沟槽内填充导电材料，以在所述通孔内形成导电柱，在所述网状沟槽内形成第一导电连接垫；
    减薄所述基底，暴露所述导电柱背离所述第一导电连接垫的一端。
  14. 根据权利要求13所述的半导体互连结构的形成方法，其中，在所述基底内形成所述通孔与所述网状沟槽的步骤包括：
    在所述基底内形成过孔，所述过孔沿第一方向及第二方向阵列排布；
    去除所述基底的部分厚度形成多条第一沟槽与多条第二沟槽，所述第一沟槽沿所述第一方向延伸且沿所述第二方向间隔排布，所述第二沟槽沿所述第二方向延伸且沿所述第一方向间隔排布，所述第一沟槽与所述第二沟槽经过所述过孔，所述第一沟槽与所述第二沟槽的交叉区域为所述交叉点。
  15. 根据权利要求13所述的半导体互连结构的形成方法，其中，在所述基底内形成所述通孔与所述网状沟槽的步骤包括：
    去除所述基底的部分厚度形成多条第一沟槽与多条第二沟槽，所述第一沟槽沿所述第一方向延伸且沿所述第二方向间隔排布，所述第二沟槽沿所述第二方向延伸且沿所述第一方向间隔排布，所述第一沟槽与所述第二沟槽的交叉区域为所述交叉点；
    在所述交叉点，沿垂直所述基底方向去除所述基底形成所述通孔。
  16. 根据权利要求13所述的半导体互连结构的形成方法，其中，在所述通孔与所述网状沟槽内填充导电材料的步骤之前还包括：在所述通孔与所述网状沟槽内壁形成种子层；
    在所述通孔与所述网状沟槽内填充导电材料的步骤中，所述导电材料覆盖所述种子层，且填满所述通孔与所述网状沟槽。
  17. 一种半导体封装结构，其中，包括如权利要求1～12任意一项所述的半导体互连结构。
PCT/CN2023/071233 2022-11-04 2023-01-09 半导体互连结构及其形成方法、半导体封装结构 WO2024093025A1 (zh)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002261455A (ja) * 2001-02-27 2002-09-13 Kyocera Corp 多層配線基板およびこれを用いた電子装置
JP2003069231A (ja) * 2001-08-29 2003-03-07 Kyocera Corp 多層配線基板
CN101504935A (zh) * 2008-02-05 2009-08-12 台湾积体电路制造股份有限公司 焊垫结构
KR20120051807A (ko) * 2010-11-15 2012-05-23 현대중공업 주식회사 Ｍｗｔ형 태양전지 및 그 제조방법
CN103426847A (zh) * 2012-05-22 2013-12-04 三星电子株式会社 具有通孔焊盘嵌件的硅通孔(tsv )半导体器件

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002261455A (ja) * 2001-02-27 2002-09-13 Kyocera Corp 多層配線基板およびこれを用いた電子装置
JP2003069231A (ja) * 2001-08-29 2003-03-07 Kyocera Corp 多層配線基板
CN101504935A (zh) * 2008-02-05 2009-08-12 台湾积体电路制造股份有限公司 焊垫结构
KR20120051807A (ko) * 2010-11-15 2012-05-23 현대중공업 주식회사 Ｍｗｔ형 태양전지 및 그 제조방법
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