WO2024087955A1 - Hemt器件及半导体器件 - Google Patents

Hemt器件及半导体器件 Download PDF

Info

Publication number
WO2024087955A1
WO2024087955A1 PCT/CN2023/120170 CN2023120170W WO2024087955A1 WO 2024087955 A1 WO2024087955 A1 WO 2024087955A1 CN 2023120170 W CN2023120170 W CN 2023120170W WO 2024087955 A1 WO2024087955 A1 WO 2024087955A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
conductive layer
conductive
gate
substrate
Prior art date
Application number
PCT/CN2023/120170
Other languages
English (en)
French (fr)
Inventor
房育涛
王倩
叶念慈
张洁
Original Assignee
湖南三安半导体有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN202211327142.XA external-priority patent/CN115663019A/zh
Priority claimed from CN202211327296.9A external-priority patent/CN115498020A/zh
Application filed by 湖南三安半导体有限责任公司 filed Critical 湖南三安半导体有限责任公司
Publication of WO2024087955A1 publication Critical patent/WO2024087955A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Definitions

  • the present disclosure generally relates to the field of semiconductor devices, and more specifically, to a HEMT device and a semiconductor device.
  • HEMT high electron mobility transistors
  • the gate field plate can improve the breakdown voltage of the device, it is widely used in HEMT devices.
  • the gate field plate is usually arranged on the passivation layer on the top of the semiconductor device and connected to the gate or source. Although it can improve the breakdown voltage of the device, people still hope to develop a new technology that can improve the breakdown voltage of the device. It is best to continue to apply the gate field plate on this new technology to significantly improve the breakdown voltage of the device.
  • the present disclosure provides a HEMT device and a semiconductor device.
  • the HEMT has a higher breakdown voltage when no gate field plate is used, and has an even higher breakdown voltage when a gate field plate is used.
  • a HEMT device comprising: a substrate; an epitaxial layer, arranged on the substrate, comprising: a first semiconductor stack and a second semiconductor layer arranged on the first semiconductor stack; a two-dimensional electron gas is formed at an interface between the first semiconductor stack and the second semiconductor layer; a source electrode, a drain electrode, and a gate electrode, which are arranged on the second semiconductor layer and are arranged at intervals; a conductive layer, which is arranged in the epitaxial layer and between the substrate and the two-dimensional electron gas; an electrical coupling structure, one end of which is electrically connected to the gate electrode, and the other end of which extends into the epitaxial layer and is electrically connected to the conductive layer; and a high-resistance structure, which is at least partially arranged between the conductive layer and the two-dimensional electron gas, and between the electrical coupling structure and the two-dimensional electron gas.
  • a semiconductor device comprises: a substrate; an epitaxial layer, arranged on the substrate, comprising: a first semiconductor stack and a second semiconductor layer arranged on the first semiconductor stack; a two-dimensional electron gas is formed at the interface between the first semiconductor stack and the second semiconductor layer; a source electrode, a drain electrode and a gate electrode, which are arranged on the second semiconductor layer and arranged at intervals; a conductive layer, which is arranged at intervals in the epitaxial layer and located between the substrate and the two-dimensional electron gas; an electrical coupling structure, which is used to electrically couple the conductive layer to the gate; a first high-resistance portion, which is used to insulate and isolate the conductive layer from the two-dimensional electron gas; and a second high-resistance portion, which is used to insulate and isolate the electrical coupling structure from the two-dimensional electron gas.
  • a conductive layer capable of being electrically coupled to a gate is provided inside the device, and the conductive layer and the two-dimensional electron gas, as well as the electrically coupled structure and the two-dimensional electron gas are isolated by a barrier structure, so that the electric field strength of the gate of the semiconductor device under high voltage can be effectively reduced through the conductive layer connected to the gate, thereby improving the breakdown voltage of the device.
  • FIG1 is a schematic diagram of a top view of a semiconductor device provided in a first embodiment of the present disclosure
  • FIG2 is a cross-sectional view of the structure of the semiconductor device taken along line A-A in FIG1 ;
  • FIG3 is a cross-sectional view of the structure of the semiconductor device taken along line B-B in FIG1 ;
  • 3A is a cross-sectional view of a structure of a semiconductor device taken along line B-B in another embodiment
  • FIG4 shows a conductive layer and an electrical coupling structure of the semiconductor device shown in FIG1 ;
  • 5a to 5i show the manufacturing process diagram of the semiconductor device according to the first embodiment of the present disclosure
  • FIG6 is a schematic diagram of a top view of the structure of a semiconductor device provided in the second embodiment of the present disclosure.
  • FIG7 is a cross-sectional view of the structure of the semiconductor device taken along line A-A in FIG6 ;
  • FIG8 shows the conductive layer and electrical coupling structure of the semiconductor device shown in FIG6 ;
  • 9a to 9i show the manufacturing process diagram of the semiconductor device according to the second embodiment of the present disclosure.
  • FIG10 is a schematic diagram of a top view of the structure of a semiconductor device provided in Embodiment 3 of the present disclosure.
  • FIG11 is a cross-sectional view of the structure of the semiconductor device taken along line A-A in FIG10 ;
  • FIG13 is a schematic diagram of a top view of a semiconductor device provided in a fourth embodiment of the present disclosure.
  • FIG14 is a cross-sectional view of the structure of the semiconductor device taken along line A-A in FIG13 ;
  • 15a to 15i show the manufacturing process diagram of the semiconductor device according to the fourth embodiment of the present disclosure.
  • FIG16 shows the conductive layer and electrical coupling structure of the semiconductor device shown in FIG13 ;
  • FIG17 is a schematic diagram of a top view of the structure of a semiconductor device provided in Embodiment 5 of the present disclosure.
  • FIG18 is a cross-sectional view of the structure of the semiconductor device taken along line A-A in FIG17 ;
  • 19a to 19i show the manufacturing process diagram of the semiconductor device according to the fifth embodiment of the present disclosure.
  • FIG20 is a schematic diagram of a top view of the structure of a semiconductor device provided in Embodiment 6 of the present disclosure.
  • FIG21 is a cross-sectional view of the structure of the semiconductor device taken along line A-A in FIG20 ;
  • 22a to 22i show the manufacturing process diagram of the semiconductor device according to the sixth embodiment of the present disclosure.
  • FIG23 is a cross-sectional view of the semiconductor device provided by the seventh embodiment of the present disclosure taken along line A-A;
  • FIG24 is a cross-sectional view of the structure of the semiconductor device taken along line BB in FIG23;
  • 25a to 25i show the manufacturing process diagram of the semiconductor device according to the seventh embodiment of the present disclosure.
  • FIG26 is a cross-sectional view of the semiconductor device provided by the eighth embodiment of the present disclosure taken along line A-A;
  • 27a to 27i show the manufacturing process diagram of the semiconductor device according to the eighth embodiment of the present disclosure.
  • FIG28 is a cross-sectional view of the semiconductor device provided by the ninth embodiment of the present disclosure taken along line A-A;
  • FIG29 is a cross-sectional view of the semiconductor device provided by the tenth embodiment of the present disclosure taken along line A-A;
  • FIG30 is a cross-sectional view of the semiconductor device provided by the eleventh embodiment of the present disclosure taken along line A-A;
  • FIG31 is a cross-sectional view of the semiconductor device provided by the twelfth embodiment of the present disclosure taken along line A-A;
  • FIG32 is a schematic diagram of a top view of the structure of a semiconductor device provided in Embodiment 13 of the present disclosure.
  • FIG33 is a cross-sectional view of the structure of the semiconductor device taken along line A-A in FIG32 ;
  • FIG34 is a cross-sectional view of the structure of the semiconductor device provided by the fourteenth embodiment of the present disclosure taken along line A-A;
  • FIG35 shows the conductive layer and electrical coupling structure of the semiconductor device provided in the fifteenth embodiment of the present disclosure.
  • epitaxial growth refers to growing a layer structure with certain requirements on the material to be processed.
  • the technologies involved in “epitaxial growth” may include metal-organic chemical vapor deposition (MOCVD), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), atomic layer deposition (ALD), etc.
  • MOCVD metal-organic chemical vapor deposition
  • LPE liquid phase epitaxy
  • VPE vapor phase epitaxy
  • MBE molecular beam epitaxy
  • ALD atomic layer deposition
  • etching should be understood in a broad sense, that is, a layer of photoresist is grown on the surface of the material to be processed, the photoresist is selectively exposed and developed through a mask to leave a photoresist layer identical to the mask pattern on the surface of the material to be processed, and then the material to be processed is selectively corroded by chemical or physical methods, and finally the photoresist layer is stripped off to form a structure corresponding to the mask pattern on the material to be processed.
  • ion implantation is to grow a layer of photoresist on the surface of the material to be processed, selectively expose and develop the photoresist through a mask to leave a photoresist layer on the surface of the material to be processed that is the same as the mask pattern, then accelerate the charged ions to a certain high energy and inject them into the material to be processed, and finally peel off the photoresist layer to form a structure corresponding to the mask pattern in the material to be processed.
  • the negative impact of ion implantation is that the material to be processed produces lattice fractures or damage due to ion collisions, so annealing treatment is required to eliminate the fractures or damage.
  • Each embodiment of the present disclosure provides a semiconductor device, or a high electron mobility transistor (High electron mobility transistor), which has the advantages of high breakdown voltage and high conductivity, and can be used as a semiconductor power device or a semiconductor radio frequency device, and has been widely used in base station communications, the Internet of Things, aerospace, radar systems and other fields.
  • High electron mobility transistor high electron mobility transistor
  • the semiconductor device includes a substrate 1 and a semiconductor layer 2 disposed on the substrate 1 .
  • the substrate 1 may be formed of silicon (Si), silicon carbide (SiC) or sapphire.
  • the semiconductor layer 2 includes a first semiconductor stack and a second semiconductor layer disposed on the first semiconductor stack.
  • the second semiconductor layer includes a barrier layer 204, the main manufacturing material of which may be alloy nitride, in particular aluminum gallium nitride (AlGaN), with a thickness of 5nm-50nm ("nm" means nanometer).
  • the first semiconductor stack includes a buffer layer 202 and a channel layer 203 disposed on the buffer layer 202, wherein the main manufacturing material of the channel layer 203 may be III-V nitride, in particular nitrogen nitride (GaN), and the thickness is generally 100nm-1000nm.
  • the channel layer 203 and the barrier layer 204 are heterostructures. Due to the large difference in polarization intensity and bandgap width between the two, a two-dimensional electron gas (2DEG) is formed at the interface between the two.
  • the channel layer 203 and the barrier layer 204 can be a single layer or multiple layers.
  • the channel layer 203 includes a 300nm high-resistance gallium nitride layer and a 200nm high-temperature gallium nitride layer arranged in a direction away from the substrate 1, and the barrier layer 204 includes a 1nm aluminum nitride layer, a 20nm aluminum gallium nitride layer, and a 2nm gallium nitride layer arranged in a direction away from the channel layer 203.
  • the semiconductor layer 2 may further include a nucleation layer 201 disposed on the substrate 1, and a buffer layer 202 disposed on the nucleation layer 201.
  • the nucleation layer 201 is formed of aluminum carbide (AlN) or gallium nitride (GaN), with a thickness of 10nm-500nm, and is used to improve the growth quality of the buffer layer 202 and has an isolation effect.
  • the buffer layer 202 is formed of iron-doped gallium nitride, carbon-doped gallium nitride, gallium nitride (GaN) or aluminum gallium nitride (AlGaN), with a thickness of 100nm-10um, and is used to improve the growth quality of III-V group nitrides.
  • the buffer layer 202 may be a one-layer or multi-layer structure. When the substrate 1 is selected as silicon material, the buffer layer 202 can be a three-layer structure.
  • the first layer is aluminum gallium nitride with an aluminum content of 75% and a total thickness of 400nm
  • the second layer is aluminum gallium nitride with an aluminum content of 50% and a total thickness of 900nm
  • the third layer is aluminum gallium nitride with an aluminum content of 25% and a total thickness of 1500nm.
  • the semiconductor device further includes a terminal layer disposed on the second semiconductor layer.
  • the semiconductor device further includes a terminal layer disposed on the barrier layer 204.
  • the terminal layer includes a gate 5, a drain 4 and a source 6 arranged at intervals.
  • Both the source 6 and the drain 4 may be a single-layer structure or a multi-layer structure.
  • the drain 4 and the source 6 may include a titanium (Ti) layer, an aluminum (Al) layer, a nickel (Ni) layer and a gold (Au) layer connected in sequence, respectively.
  • the source 6 makes ohmic contact with the barrier layer 204 and is electrically coupled with the two-dimensional electron gas.
  • the drain 4 also makes ohmic contact with the barrier layer 204 and is electrically coupled with the two-dimensional electron gas.
  • the gate 5 mainly includes one or two of a nickel (Ni) layer and a gold (Au) layer, and makes Schottky contact with the barrier layer 204.
  • Ni nickel
  • Au gold
  • the semiconductor device further includes a passivation layer 9.
  • the passivation layer 9 is disposed on the barrier layer 204 and avoids the gate 5, the drain 4 and the source 6.
  • the passivation layer 9 has a plurality of avoidance holes for the gate 5, the drain 4 and the source 6 to penetrate respectively, so that the passivation layer 9 is used to insulate and isolate the gate 5, the drain 4 and the source 6 to prevent the semiconductor device from malfunctioning due to erroneous connection between the terminals.
  • the passivation layer 9 is made of one of insulating compounds such as silicon dioxide, silicon nitride, aluminum nitride and aluminum oxide.
  • the semiconductor device also includes a conductive layer 7, which is arranged in the semiconductor layer 2 and is located between the substrate 1 and the two-dimensional electron gas; and an electrical coupling structure 57, which extends from the gate 5 into the semiconductor layer 2 and is connected to the conductive layer 7, and is used to couple the conductive layer 7 to the gate 5.
  • the electrical coupling decoupling structure 57 may be a rod-shaped structure.
  • the passivation layer 9 is disposed on the second semiconductor layer, and the passivation layer 9 is located between the electrical coupling structure 57 and the source electrode 6, and between the gate electrode 5 and the drain electrode 4.
  • the passivation layer may have an avoidance hole through which the power supply coupling structure 57 passes, so that one end of the electrical coupling structure 57 is located in the semiconductor layer 2 and connected to the connection area of the conductive layer 7, while the other end of the electrical coupling structure 57 is located outside the semiconductor layer 2 and connected to the side of the gate electrode 5 facing the source electrode 6.
  • the electrical coupling structure 57 which is a rod-shaped structure, can not only realize the electrical coupling between the conductive layer 7 and the gate electrode 5, but also the structure used is very simple.
  • the electrical coupling structure 57 can be perpendicular to the conductive layer 7 and formed by a metal material so as to be suitable for formation by deposition and etching.
  • the metal can be one or more high-temperature resistant materials such as tungsten, molybdenum, tantalum and nickel.
  • one end of the electrical coupling structure 57 is located inside the semiconductor layer 2 and connected to the connection region of the conductive layer 7, while the other end of the electrical coupling structure 57 is located outside the semiconductor layer 2 and connected to the side of the gate 5 facing the drain 4, refer to FIG. 3A.
  • the conductive layer 7 includes a first surface away from the substrate 1, a second surface opposite thereto and close to the substrate 1, and a side surface connected to the first surface and the second surface.
  • the conductive layer 7 may be selected as one, and the conductive layer 7 intersects with the orthographic projection of the gate 5 on the substrate 1.
  • the source 6 and the drain 4 can be connected by means of the two-dimensional electron gas, and the conductive layer 7 can adjust the electric field distribution between the channel layer 203 and the barrier layer 204, reduce the peak value of the electric field intensity near the gate 5, and increase the breakdown voltage of the device, thereby improving the working characteristics of the device under high voltage, high power and/or high frequency.
  • the orthographic projection of the conductive layer 7 on the substrate 1 is closer to the orthographic projection of the drain 4 on the substrate 1 than the orthographic projection of the gate 5 on the substrate 1, thereby the conductive layer 7 can further reduce the peak electric field strength near the gate 5 and further increase the breakdown voltage of the device.
  • the conductive layer 7 is disposed in the channel layer 203 .
  • the first surface of the conductive layer 7 and the second surface of the conductive layer 7 are both located in the channel layer 203, so that the conductive layer 7 can be suitable for being formed by ion implantation and tempering activation.
  • the channel layer 203 includes at least two layers to ensure that the conductive layer 7 is suitable for being formed between the at least two layers by epitaxial growth (conductive layer 7 made of semiconductor material)/deposition (conductive layer 7 made of metal material) and etching.
  • the first surface of the conductive layer 7 is located in the channel layer 203, and the second surface of the conductive layer 7 is connected to the interface between the buffer layer 202 and the channel layer 203.
  • a conductive layer can be prepared before growing the channel layer 203, thereby simplifying the device manufacturing process.
  • the conductive layer 7 is disposed in the buffer layer, so that the insulation property of the buffer layer can be used to strengthen the insulation between the conductive layer 7 and the two-dimensional electron gas.
  • the buffer layer 202 includes at least two layers to ensure that the conductive layer 7 is suitable for being formed between at least two layers by epitaxial growth/deposition and etching.
  • the first surface of the conductive layer 7 is connected to the side of the buffer layer 202 away from the substrate 1, and the second surface of the conductive layer 7 is located in the buffer layer 202, so that the conductive layer 7 can be suitable for being formed by ion implantation and tempering activation.
  • the buffer layer 202 includes a first layer structure and a second layer structure, a conductive material layer is grown on the first layer structure, the conductive material layer is etched to obtain the conductive layer 7, and then a second layer structure that wraps the conductive layer 7 is grown on the first layer structure.
  • the thickness of the second layer structure is the same as that of the conductive layer 7, the first surface of the conductive layer 7 is connected to the side of the buffer layer 202 away from the substrate 1.
  • the conductive layer 7 can be a rectangular body that is easy to shape, as shown in Figure 4.
  • the thickness of the conductive layer 7 is 10nm-1000nm, and can be 100nm.
  • the conductive layer 7 can be a structure formed by a metal material, suitable for formation by a deposition method and an etching method.
  • the metal can be one or more of high temperature resistant materials such as tungsten, molybdenum, tantalum and nickel.
  • the conductive layer can be made of a semiconductor material, suitable for formation by an epitaxial growth method and an etching method.
  • the conductive layer 7 can be an n-type or p-type GaN conductive layer.
  • the size of the conductive layer 7 along the first direction is larger than the size of the conductive layer 7 along the second direction (i.e., the arrangement direction from the substrate 1 to the semiconductor layer 2), so that its structure is flattened, thereby reducing the occupancy ratio of the conductive layer 7 to the semiconductor layer 2, such as the occupancy ratio of the channel layer 203, effectively avoiding a significant decrease in the two-dimensional electron gas concentration due to the excessive volume of the conductive layer 7, thereby ensuring that the switching characteristics of the semiconductor device are still useful and efficient.
  • the conductive layer 7 is made of semiconductor material.
  • the semiconductor device further includes a high resistance structure 8, which is at least partially disposed between the conductive layer 7 and the two-dimensional electron gas, and between the electrical coupling structure 57 and the two-dimensional electron gas.
  • the high-resistance structure 8 includes a first high-resistance portion 801, which is disposed above the conductive layer 7 and is used to insulate the conductive layer 7 from the two-dimensional electron gas, thereby intercepting the leakage current generated by the two-dimensional electron gas flowing toward the conductive layer 7, thereby effectively reducing the risk of failure or damage of the semiconductor device during high-voltage operation.
  • the first high resistance portion 801 is disposed above the conductive layer 7 to insulate the conductive layer 7 from the two-dimensional electron gas.
  • the first surface of the conductive layer 7 includes a connection area for connecting to the electrical coupling structure 57
  • the first high resistance portion 801 is disposed on the first surface of the conductive layer 7 except the connection area.
  • the manufacturing material of the first high resistance portion 801 is one of silicon dioxide, silicon nitride, aluminum nitride and aluminum oxide, and the thickness can be selected to be 5nm-1000nm to ensure that it is suitable for formation by epitaxial growth method and etching method.
  • the high-resistance structure 8 further includes a second high-resistance portion 802 that wraps the electrical coupling structure 57, and is used to insulate the electrical coupling structure 57 from the two-dimensional electron gas, intercept the leakage current generated by the two-dimensional electron gas and flowing toward the electrical coupling structure 57, thereby effectively reducing the risk of failure or damage of the semiconductor device during high-voltage operation.
  • the second high-resistance portion 802 is similar to a sleeve-shaped structure, and its manufacturing material is one of silicon dioxide, silicon nitride, aluminum nitride and aluminum oxide, and the thickness can be selected to be 5nm-1000nm to ensure that it is suitable for formation by epitaxial growth and etching.
  • the high resistance structure 8 covers the first surface of the conductive layer 7 and the side of the buffer layer 202 away from the substrate, and is located on the side of the channel layer 203 close to the substrate 1. In this way, the high resistance structure 8 can be directly constructed as a layer structure between the channel layer 203 and the buffer layer 202.
  • the conductive layer 7 is made of a metal material.
  • the semiconductor device further includes a high resistance structure 8 and a barrier material 8 '.
  • the high resistance structure 8 is at least partially disposed between the conductive layer 7 and the two-dimensional electron gas, and between the electrical coupling structure 57 and the two-dimensional electron gas.
  • the barrier material 8 ' is connected to the first high resistance portion 801 and covers the side of the conductive layer 7.
  • the first high-resistance portion 801 at least covers the upper surface of the conductive layer 7, and the barrier material 8' at least covers the side of the conductive layer 7.
  • the transition between the upper surface and the side of the conductive layer 7 can be the first high-resistance portion 801 or the barrier material 8'.
  • the barrier material 8' is connected to the first high-resistance portion 801 to cover the upper surface and the side of the conductive layer 7 as a whole, so that the conductive layer 7 is insulated from the epitaxial layer on its side and above.
  • the high-resistance structure 8 and the barrier material 8' are both made of high-resistance materials, which is beneficial to the insulation between the conductive layer 7 and the semiconductor layer 2.
  • the high-resistance structure 8 includes a first high-resistance portion 801, which is disposed above the conductive layer 7 and is used to insulate the conductive layer 7 from the two-dimensional electron gas, thereby intercepting the leakage current generated by the two-dimensional electron gas flowing toward the conductive layer 7, thereby effectively reducing the risk of failure or damage of the semiconductor device during high-voltage operation.
  • the first high resistance portion 801 is disposed above the conductive layer 7 to insulate the conductive layer 7 from the two-dimensional electron gas.
  • the first surface of the conductive layer 7 includes a connection area for connecting to the electrical coupling structure 57
  • the first high resistance portion 801 is disposed on the first surface of the conductive layer 7 except the connection area.
  • the manufacturing material of the first high resistance portion 801 is one of silicon dioxide, silicon nitride, aluminum nitride and aluminum oxide, and the thickness can be selected to be 5nm-1000nm to ensure that it is suitable for formation by epitaxial growth method and etching method.
  • the high-resistance structure 8 further includes a second barrier portion 802 that wraps the electrical coupling structure 57, and is used to insulate the electrical coupling structure 57 from the two-dimensional electron gas, intercepting the leakage current generated by the two-dimensional electron gas and flowing toward the electrical coupling structure 57, thereby effectively reducing the risk of failure or damage of the semiconductor device during high-voltage operation.
  • the second high-resistance portion 802 is similar to a sleeve-shaped structure, and its manufacturing material is one of silicon dioxide, silicon nitride, aluminum nitride and aluminum oxide, and the thickness can be selected to be 5nm-1000nm to ensure that it is suitable for formation by epitaxial growth and etching.
  • the high resistance structure 8 covers the first surface of the conductive layer 7 and the side of the buffer layer 202 away from the substrate 1, and is located on the side of the channel layer 203 close to the substrate 1. In this way, the high resistance structure 8 can be directly constructed as a layer structure between the channel layer 203 and the buffer layer 202.
  • the manufacturing steps and selected materials of the barrier material 8' and the first high resistance portion 801 of the high resistance structure 8 may be the same or different.
  • FIGS. 13-14 and 29 there are multiple conductive layers 7 , and the multiple conductive layers 7 are spaced apart along the third direction (ie, a direction perpendicular to the first direction and the second direction).
  • each conductive layer 7 is equal, and the total size of the plurality of conductive layers 7 along the first direction is smaller than the size of a single conductive layer 7 in the second direction, wherein the second direction is the arrangement direction from the substrate 1 to the semiconductor layer 2.
  • each electrical coupling structure 57 can be a rod-shaped body perpendicular to the corresponding conductive layer 7, and one end of each electrical coupling structure 57 is connected to the connection area of the conductive layer 7, and the other end is connected to the gate 5.
  • the conductive layer 7 includes: first conductive layers 701 disposed at intervals and second conductive layers 702 connecting the first conductive layers 701 disposed at intervals.
  • the second conductive layer 702 is perpendicular to the first conductive layer 701.
  • the first conductive layers 701 are arranged at intervals along a first direction, wherein the first direction is an arrangement direction of the source 6 to the drain 4 .
  • the first conductive layers 701 are spaced apart along the third direction.
  • connection area 703 of the conductive layer 7 is located on one of the multiple first conductive layers 701; there is one electrical coupling structure 57, and one end of the electrical coupling structure 57 is connected to the first conductive layer 701 having the connection area, and the other end is connected to the gate 5.
  • connection region 703 is located on an extended region of the first conductive layer 701 having the connection region 703 extending away from the second conductive layer 702. That is, the columnar first conductive layer 701 has opposite free ends and a connection end connected to the second conductive layer 702, and the connection region 703 extends from the connection end in a direction away from the second conductive layer.
  • a conductive layer 7 electrically coupled to the gate 5 is provided inside the semiconductor device, and the conductive layer 7 and the two-dimensional electron gas, as well as the electrical coupling structure 57 and the two-dimensional electron gas are isolated by a high-resistance structure 8, so that the electric field strength of the gate 5 under high voltage of the semiconductor device can be effectively reduced by the conductive layer 7 connected to the gate 5, thereby improving the breakdown voltage of the device.
  • the material of the conductive layer 7 is a conductive doped semiconductor material or a metal material.
  • the metal is easy to react with the ammonia in the epitaxial growth in the subsequent epitaxial growth process of the device.
  • the conductive layer is isolated in the first high-resistance part 801 of the high-resistance structure 8 and the barrier material 8' through the high-resistance structure 8, so that the corrosion of the conductive layer 7 by the ammonia in the epitaxial growth can be reduced, thereby ensuring that the conductive layer 7 can be electrically connected to the gate 5 and helping to reduce the electric field near the gate 5.
  • the first high-resistance part 801 of the high-resistance structure 8 and the barrier material 8' of the embodiment of the present disclosure can also prevent the conductive layer 7 from reacting with the ammonia used in the subsequent device manufacturing process, especially in the epitaxial growth, to ensure that it can smoothly achieve the above-mentioned effect.
  • the semiconductor device may further include a gate field plate 11, which is located on the passivation layer 9 between the gate 5 and the drain 4.
  • the gate field plate 11 can assist the conductive layer 7 in adjusting the electric field distribution between the channel layer 203 and the barrier layer 204, further reducing the peak value of the electric field intensity near the gate 5, thereby significantly improving the breakdown voltage of the device.
  • the semiconductor device has a higher breakdown voltage when the gate field plate 11 is not used, and will have an even higher breakdown voltage when the gate field plate 11 is used.
  • the conductive layer 7 can be connected to the gate 5 or the source 6, but because the potential of the source 6 is not as strong as the potential of the gate 5, and the peak value of the electric field intensity near the gate 5 is synchronized with the potential of the gate 5 but not with the potential of the source 6, the conductive layer 7 connected to the gate 5 must have a stronger and more accurate electric field adjustment capability near the gate, which is beneficial to ensure that the peak value of the electric field intensity near the gate 5 is lower and the breakdown voltage of the device is higher.
  • the conductive layer connected to the source 6 is easy to achieve during the manufacturing method, but when it is necessary When the conductive layer 7 is to be connected to the gate 5, it is difficult to connect the conductive layer 7 to the gate 5 during the manufacturing process because the gate 5 cannot be directly extended to the conductive layer 7 due to the problem of destroying the two-dimensional electron gas.
  • an electrical coupling structure 57 that passes through the barrier layer 204 and the channel layer 203 can be added to the device to connect the conductive layer 7 and the gate 5
  • a first blocking structure 8 can be added between the conductive layer 7 and the two-dimensional electron gas and between the electrical coupling structure 57 and the two-dimensional electron gas, so that the first blocking structure 8 can insulate the conductive layer 7 from the two-dimensional electron gas, and then insulate the electrical coupling structure 57 from the two-dimensional electron gas, thereby intercepting the leakage current generated by the two-dimensional electron gas and flowing to the conductive layer 7 and the electrical coupling structure 57, effectively improving the breakdown voltage of the device, so that the semiconductor device can operate normally at a higher operating voltage.
  • the conductive layer 7 is made of a semiconductor material. Based on this, the present disclosure also discloses a method for manufacturing a semiconductor device, the method comprising the following steps:
  • a semiconductor epitaxial structure comprising a substrate 1 and a semiconductor layer 2; wherein the semiconductor layer 2 comprises a first semiconductor stack and a second semiconductor layer arranged on the first semiconductor stack; a two-dimensional electron gas is formed at an interface between the first semiconductor stack and the second semiconductor layer;
  • a conductive layer 7 is formed in the semiconductor layer 2 and is located between the substrate 1 and the two-dimensional electron gas;
  • An electric coupling structure 57 and a high resistance structure 8 are formed in the semiconductor layer 2.
  • the electric coupling structure 57 extends from the semiconductor layer 2 into the semiconductor layer 2 and is connected to the conductive layer 7.
  • the high resistance structure 8 is at least partially disposed between the conductive layer 7 and the two-dimensional electron gas, and between the electric coupling structure 57 and the two-dimensional electron gas.
  • a terminal layer including a source electrode 6 , a drain electrode 4 and a gate electrode 5 is formed on the second semiconductor layer, and the gate electrode 5 is connected to an electrical coupling structure 57 .
  • the semiconductor device prepared by the above method by arranging a conductive layer 7 that can be electrically coupled with the gate 5 inside the device, and isolating the conductive layer 7 and the two-dimensional electron gas, and the electrical coupling structure 57 and the two-dimensional electron gas through the high-resistance structure 8, can effectively reduce the electric field strength of the gate 5 under high voltage of the semiconductor device through the conductive layer 7 connected to the gate 5, thereby improving the breakdown voltage of the device.
  • the first semiconductor stack includes: a buffer layer 202 close to the substrate 1, and a channel layer 203 disposed on the buffer layer 202, and forming the conductive layer 7 in the semiconductor layer 2 includes:
  • Conductive layer 7 is formed in channel layer 203 .
  • the conductive layer 7 is disposed in the channel layer 203 , which can ensure that the conductive layer 7 is located below the two-dimensional electron gas while reducing the distance between the conductive layer 7 and the gate 5 .
  • forming the conductive layer 7 in the channel layer 203 includes:
  • a conductive material layer formed of a conductive type doped semiconductor material is grown on the buffer layer 202 , and the conductive material layer is etched to obtain a conductive layer 7 formed of the remaining conductive material layer.
  • forming the conductive layer 7 in the channel layer 203 includes:
  • Conductive dopants are implanted into the channel layer 203 at a fixed area and depth by ion implantation, and then annealed to activate the conductive layer 7 .
  • the method for setting the conductive layer 7 in the channel layer 203 is not limited to the above-mentioned ion implantation method.
  • a conductive material layer is also grown by the same growth method and then etched to form the conductive layer 7, and then a secondary epitaxial growth is performed to form the remaining channel layer 203.
  • the conductive dopant is implanted into the channel layer 203 in a fixed area and depth by the ion implantation method, and then annealed to activate it into the conductive layer 7, which makes the implementation process simpler and the cost lower.
  • the first semiconductor stack includes: a buffer layer 202 close to the substrate 1, and a channel layer disposed on the buffer layer 202, and a conductive layer is formed in the semiconductor layer 2, including:
  • Conductive layer 7 is formed in buffer layer 202 .
  • forming the conductive layer 7 in the buffer layer 202 includes:
  • the conductive dopant is implanted into the buffer layer 202 at a fixed area and depth by ion implantation, and then annealed to activate it into the conductive layer 7. Similar to the above-mentioned embodiment formed in the channel layer 203, the conductive dopant is implanted into the buffer layer 202 at a fixed area and depth by ion implantation, and then annealed to activate it into the conductive layer 7, which makes the implementation process simpler and the cost lower.
  • the conductive layer 7 is made of a metal material. Based on this, the present disclosure also discloses a method for manufacturing a semiconductor device, the method comprising the following steps:
  • a semiconductor epitaxial structure comprising a substrate 1 and a semiconductor layer 2; wherein the semiconductor layer 2 comprises a first semiconductor stack and a second semiconductor layer arranged on the first semiconductor stack; a two-dimensional electron gas is formed at an interface between the first semiconductor stack and the second semiconductor layer;
  • a conductive layer 7 is formed in the semiconductor layer 2 and is located between the substrate 1 and the two-dimensional electron gas;
  • a source electrode 6, a drain electrode 4 and a gate electrode 5 are formed on the second semiconductor layer; an electrical coupling structure 57 is formed by extending the gate electrode 5 into the semiconductor layer 2 and electrically connecting to the conductive layer 7;
  • a high resistance structure 801 is provided on a side of the conductive layer 7 away from the substrate 1, wherein the high resistance structure 8 is used to insulate and isolate the conductive layer 7 and the electrical coupling structure 57 from the two-dimensional electron gas;
  • a barrier material 8' is arranged on a side of the conductive layer 7, wherein the side is adjacent to a side of the conductive layer away from the substrate 1.
  • the semiconductor device prepared by the above method by providing a conductive layer 7 electrically connected to the gate 5 inside the device, and isolating the conductive layer 7 from the two-dimensional electron gas, and the electrical coupling structure 57 from the two-dimensional electron gas, by the high resistance structure 8, can effectively reduce the electric field strength of the gate 5 under high voltage of the semiconductor device through the conductive layer 7 connected to the gate 5, thereby improving the breakdown voltage of the device.
  • the barrier material 8' can prevent the conductive layer 7 from reacting with the ammonia used in the subsequent device manufacturing process, especially in the epitaxial growth, to ensure the conductive performance of the conductive layer 7.
  • the first semiconductor stack includes: a buffer layer 202 close to the substrate 1, and a channel layer 203 disposed on the buffer layer 202, and forming the conductive layer 7 in the semiconductor layer 2 includes:
  • Conductive layer 7 is formed in channel layer 203 .
  • the conductive layer 7 is disposed in the channel layer 203 , which can ensure that the conductive layer 7 is located below the two-dimensional electron gas while reducing the distance between the conductive layer 7 and the gate 5 .
  • forming the conductive layer 7 in the channel layer 203 includes:
  • a conductive material layer formed of a metal material is grown on the buffer layer 202, and the conductive material layer is etched to obtain a conductive layer formed of the remaining conductive material layer.
  • the conductive material layer can be grown by the same growth method and then etched to form the conductive layer 7, and then the remaining channel layer 203 can be grown by secondary epitaxial growth.
  • a high resistance structure 8 is provided on a side of the conductive layer 7 away from the substrate 1, and a barrier material 8' is provided on a side of the conductive layer 7, including:
  • a high-resistance material layer formed of an insulating compound is grown on the conductive layer 7, and the high-resistance material layer is etched to obtain a first high-resistance portion 801 of the high-resistance structure 8 formed by the remaining high-resistance material layer and located above the conductive layer 7, and a barrier material 8' located on the side of the conductive layer 7.
  • the present embodiment provides a semiconductor device, which is also called a high electron mobility transistor (High electron mobility transistor), which has the advantages of high breakdown voltage and high conductivity. It can be used as a semiconductor power device or a semiconductor radio frequency device, and has been widely used in base station communications, the Internet of Things, aerospace, radar systems and other fields.
  • a semiconductor device which is also called a high electron mobility transistor (High electron mobility transistor)
  • High electron mobility transistor which has the advantages of high breakdown voltage and high conductivity. It can be used as a semiconductor power device or a semiconductor radio frequency device, and has been widely used in base station communications, the Internet of Things, aerospace, radar systems and other fields.
  • the semiconductor device includes a substrate 1 and a semiconductor layer 2 (also called an epitaxial layer) disposed on the substrate 1.
  • the substrate 1 can be formed of silicon (Si), silicon carbide (SiC) or sapphire.
  • the semiconductor layer 2 includes a first semiconductor stack and a second semiconductor layer disposed on the first semiconductor stack.
  • the second semiconductor layer includes a barrier layer 204, the main manufacturing material of which can be selected as alloy nitride, especially aluminum gallium nitride (AlGaN), with a thickness of 5nm-50nm ("nm" means nanometer).
  • the first semiconductor stack includes a buffer layer 202 and a channel layer 203 disposed on the buffer layer 202, wherein the main manufacturing material of the channel layer 203 can be selected as III-V nitride, especially nitrogen nitride (GaN), and the thickness is generally 100nm-1000nm.
  • the channel layer 203 includes III-V group nitrides and the barrier layer 204 includes alloy nitrides
  • the channel layer 203 and the barrier layer 204 are heterostructures. Due to the large difference in polarization intensity and bandgap width between the two, a two-dimensional electron gas (2DEG) is formed at the interface between the two.
  • the channel layer 203 and the barrier layer 204 can be a single layer or multiple layers.
  • the channel layer 203 includes a 300nm high-resistance gallium nitride layer and a 200nm high-temperature gallium nitride layer arranged in a direction away from the substrate 1, and the barrier layer 204 includes a 1nm aluminum nitride layer, a 20nm aluminum gallium nitride layer, and a 2nm gallium nitride layer arranged in a direction away from the channel layer 203.
  • the semiconductor layer 2 may also include a nucleation layer 201 disposed on the substrate 1, and a buffer layer 202 disposed on the nucleation layer 201.
  • the nucleation layer 201 is formed of aluminum carbide (AlN) or gallium nitride (GaN), with a thickness of 10nm-500nm, and is used to improve the growth quality of the buffer layer 202 and has an isolation effect.
  • the buffer layer 202 is formed of iron-doped gallium nitride, carbon-doped gallium nitride, gallium nitride (GaN) or aluminum gallium nitride (AlGaN), with a thickness of 100nm-10um, and is used to improve the growth quality of III-V group nitrides.
  • the buffer layer 202 may be a one-layer or multi-layer structure.
  • the buffer layer 202 may be a three-layer structure, the first layer is aluminum gallium nitride with an aluminum content of 75% and a total thickness of 400nm, the second layer is aluminum gallium nitride with an aluminum content of 50% and a total thickness of 900nm, and the third layer is aluminum gallium nitride with an aluminum content of 25% and a total thickness of 1500nm.
  • the semiconductor device also includes a terminal layer mainly arranged on the barrier layer 204.
  • the terminal layer includes a gate 5, a drain 4 and a source 6.
  • the source 6 and the drain 4 can both be a single-layer structure or a multi-layer structure, and can include a titanium (Ti) layer, an aluminum (Al) layer, a nickel (Ni) layer and a gold (Au) layer connected in sequence.
  • the source 6 makes ohmic contact with the barrier layer 204 and is electrically coupled with the two-dimensional electron gas.
  • the drain 4 also makes ohmic contact with the barrier layer 204 and is electrically coupled with the two-dimensional electron gas.
  • the gate 5 mainly includes one or two of a nickel (Ni) layer and a gold (Au) layer, and makes Schottky contact with the barrier layer 204.
  • Ni nickel
  • Au gold
  • the semiconductor device further includes a passivation layer 9.
  • the passivation layer 9 is disposed on the barrier layer 204 and avoids the gate 5, the drain 4 and the source 6, that is, the passivation layer 9 has a plurality of avoidance holes for the gate 5, the drain 4 and the source 6 to penetrate respectively, so that the passivation layer 9 is used to insulate and isolate the gate 5, the drain 4 and the source 6 to prevent the semiconductor device from malfunctioning due to erroneous connection between the terminals.
  • the passivation layer 9 is made of a material including one of insulating compounds such as silicon dioxide, silicon nitride, aluminum nitride and aluminum oxide.
  • the semiconductor device further includes a conductive layer 7 disposed in the channel layer 203, and an electrical coupling structure 57 for electrically coupling the conductive layer 7 to the gate 5.
  • the conductive layer 7 is made of a conductive type doped semiconductor material or a metal material.
  • the conductive layer 7 includes a first surface away from the substrate 1, a second surface opposite thereto and close to the substrate 1, and a side surface connected to the first surface and the second surface.
  • the conductive layer 7 can be selected as one, and the conductive layer 7 intersects with the positive projection of the gate 5 on the substrate 1.
  • the source 6 and the drain 4 can be connected by means of a two-dimensional electron gas, and the conductive layer 7 can adjust the electric field distribution between the channel layer 203 and the barrier layer 204, reduce the peak value of the electric field intensity near the gate 5, and increase the breakdown voltage of the device, thereby improving the working characteristics of the device under high voltage, high power and/or high frequency.
  • the conductive layer 7 can further reduce the peak electric field strength near the gate 5 and further increase the breakdown voltage of the device.
  • the first surface of the conductive layer 7 is located in the channel layer 203, and the second surface of the conductive layer 7 is connected to the interface between the buffer layer 202 and the channel layer 203 to ensure that the conductive layer 7 is suitable for being formed by epitaxial growth and etching.
  • the conductive layer 7 can be a rectangular body that is easy to shape, as shown in Figure 4.
  • the thickness of the conductive layer 7 is 10nm-1000nm, which can be 100nm, and can be a structure formed by a metal material, which is suitable for being formed by epitaxial growth and etching.
  • the metal can be one or more of high temperature resistant materials such as tungsten, molybdenum, tantalum and nickel.
  • the size of the conductive layer 7 along the first direction is larger than the size of the conductive layer 7 along the second direction (i.e., the arrangement direction of the substrate 1 to the semiconductor layer 2), so that its structure is flattened, thereby reducing the occupation ratio of the conductive layer 7 to the channel layer 203, effectively avoiding the significant decrease in the concentration of the two-dimensional electron gas due to the excessive volume of the conductive layer 7, and ensuring that the switching characteristics of the semiconductor device are still useful and efficient.
  • the electric coupling structure 57 is a rod-shaped structure.
  • the passivation layer 9 also has avoidance holes through which the electric coupling structure 57 respectively penetrates, so that one end of the electric coupling structure 57
  • the electrical coupling structure 57 is located in the semiconductor layer 2 and connected to the connection area of the conductive layer 7, while the other end of the electrical coupling structure 57 is located outside the semiconductor layer 2 and connected to the side of the gate 5 facing the source 6.
  • the electrical coupling structure 57 which is a rod-shaped structure, can not only realize the electrical coupling between the conductive layer 7 and the gate 5, but also has a very simple structure.
  • the electrical coupling structure 57 is preferably perpendicular to the conductive layer 7 and is formed of a metal material so as to be suitable for formation by epitaxial growth and etching.
  • the metal can be one or more high-temperature resistant materials such as tungsten, molybdenum, tantalum and nickel.
  • the high resistance structure 8 includes a first high resistance portion 801, which is arranged above the conductive layer 7, and is used to insulate the conductive layer 7 from the two-dimensional electron gas, intercept the leakage current generated by the two-dimensional electron gas flowing to the conductive layer 7, thereby effectively reducing the risk of failure or damage of the semiconductor device during high-voltage operation.
  • the high resistance structure 8 can also prevent the conductive layer 7 from reacting with the ammonia used in the subsequent device manufacturing process, especially with the epitaxial growth, to ensure the effectiveness of the conductive layer 7.
  • the first high resistance portion 801 is arranged on the first surface of the conductive layer 7 except the connection area.
  • the manufacturing material of the first high resistance portion 801 is one of silicon dioxide, silicon nitride, aluminum nitride and aluminum oxide, and the thickness can be selected to be 5nm-1000nm to ensure that it is suitable for formation by epitaxial growth and etching.
  • the high resistance structure 8 also includes a second high resistance portion 802 that wraps the electrical coupling structure 57, which is used to insulate the electrical coupling structure 57 from the two-dimensional electron gas, intercept the leakage current generated by the two-dimensional electron gas and flowing to the electrical coupling structure 57, thereby effectively reducing the risk of failure or damage of the semiconductor device during high-voltage operation.
  • the second high resistance portion 802 is similar to a sleeve-shaped structure, and its manufacturing material is one of silicon dioxide, silicon nitride, aluminum nitride and aluminum oxide, and the thickness can be selected to be 5nm-1000nm to ensure that it is suitable for formation by epitaxial growth method and etching method.
  • the semiconductor device may further include a gate field plate 11 disposed on the passivation layer 9 and connected to the gate 5.
  • the gate field plate 11 can assist the conductive layer 7 in adjusting the electric field distribution between the channel layer 203 and the barrier layer 204, further reducing the peak value of the electric field intensity near the gate 5, thereby significantly improving the breakdown voltage of the device.
  • a method for manufacturing a semiconductor device includes: providing a substrate 1, as shown in Figure 5a for details; growing a nucleation layer 201 on the substrate 1; growing a buffer layer 202 on the nucleation layer 201, as shown in Figure 5b for details; growing a conductive material layer formed of a metal material on the buffer layer 202; etching the conductive material layer to obtain a conductive layer 7 formed of a remaining conductive material layer; growing a high-resistance material layer formed of an insulating compound on the buffer layer 202 and the conductive layer 7; etching the high-resistance material layer to obtain a first high-resistance portion 801 of a high-resistance structure 8 formed by the remaining high-resistance material layer and located above the conductive layer 7; growing a channel layer 203 on the buffer layer 202 that can cover the first high-resistance portion 801 of the high-resistance structure 8; and growing a barrier layer
  • the barrier layer 204, the channel layer 203 and the first high-resistance portion 801 of the high-resistance structure 8 are opened by etching to obtain a first slot 57a that leaks out of the conductive layer 7, as shown in FIG. 5e; an insulating material 9a is grown on the barrier layer 204 and in the first slot 57a, as shown in FIG.
  • the insulating material 9a on the barrier layer 204 is opened by etching to obtain a source hole region, a gate hole region and a drain hole region; a source 6, a gate 5 and a drain 4 are formed in the source hole region, the gate hole region and the drain hole region respectively by growth, etching and tempering, and a connection gate 5 is formed on the insulating material 9a.
  • the insulating material 9a located inside and outside the first slot 57a is opened by etching to obtain a second slot 57b which is thinner than the first slot 57a and through which the conductive layer 7 can leak out, as shown in FIG5h; a conductive material is grown in the second slot 57b, and then the conductive material is etched to obtain an electrical coupling structure 57 formed by the conductive material and connecting the conductive layer 7 to the gate 5, as well as a passivation layer 9 formed by the remaining insulating material 9a and located on the barrier layer 204 and a second high-resistance portion 802 of the high-resistance structure 8 for covering the electrical coupling structure 57, as shown in FIG5i.
  • the conductive layer 7 includes first conductive layers 701 spaced apart along the first direction (i.e., the arrangement direction of the source 6 to the drain 4) and second conductive layers 702 connecting the spaced apart first conductive layers 701, and a connection region (third conductive layer) 703 in contact with the electrical coupling structure 57 is provided on one of the plurality of first conductive layers 701.
  • the connection region 703 is located on an extended region of the first conductive layer 701 having the connection region 703 extending away from the second conductive layer 702.
  • the second conductive layer 702 is perpendicular to the first conductive layer 701 to reduce the difficulty of manufacturing.
  • the orthographic projection of at least one first conductive layer 701 on the substrate 1 intersects with the orthographic projection of the gate 5 on the substrate 1.
  • the source 6 and the drain 4 can be connected by means of the two-dimensional electron gas, and the conductive layer 7 mainly uniformly adjusts the electric field distribution between the channel layer 203 and the barrier layer 204 by means of the multiple first conductive layers 701.
  • the semiconductor device having the first conductive layer 701 and the second conductive layer 702 can more effectively reduce the peak value of the electric field intensity near the gate 5, and further improve the breakdown voltage of the device, and improve the working characteristics of the device under high voltage, high power and/or high frequency.
  • the orthographic projection of the first conductive layer 701 closest to the drain 4 among the orthographic projections of the multiple first conductive layers 701 on the substrate 1 is closer to the orthographic projection of the drain 4 on the substrate 1 than the orthographic projection of the gate 5 on the substrate 1, thereby the first conductive layer 701 closest to the drain 4 can better reduce the peak value of the electric field intensity near the gate 5 and more effectively improve the breakdown voltage of the device.
  • the first surface of the conductive layer 7 is located in the channel layer 203, and the second surface of the conductive layer 7 is connected to the surface of the buffer layer 202 away from the substrate 1 to ensure that the conductive layer 7 is suitable for being formed by epitaxial growth and etching.
  • Each first conductive layer 701 can be a rectangular body that is easy to form.
  • the thickness of the conductive layer 7 is 10nm-1000nm, which can be 100nm, and can be a structure formed by a metal material, which is suitable for being formed by epitaxial growth and etching.
  • the metal can be one or more of high temperature resistant materials such as tungsten, molybdenum, tantalum and nickel.
  • each first conductive layer 701 along the first direction is greater than the size of the first conductive layer 7 along the second direction (i.e., the arrangement direction from the substrate 1 to the semiconductor layer 2), thereby reducing the occupation ratio of the conductive layer 7 to the channel layer 203, effectively avoiding the significant decrease in the concentration of the two-dimensional electron gas, and ensuring that the switching characteristics of the semiconductor device are still useful and efficient.
  • the electric coupling structure 57 is a rod-shaped structure, and the passivation layer 9 also has an avoidance hole through which the power supply coupling structure 57 passes, so that one end of the electric coupling structure 57 is located in the semiconductor layer 2 and is internally connected to the connection area of the first conductive layer 701, while the other end of the electric coupling structure 57 is located outside the semiconductor layer 2 and is connected to the side of the gate 5 facing the source 6.
  • the electric coupling structure 57 in a rod-shaped structure can not only realize the electrical coupling between the conductive layer 7 and the gate 5, but also the structure used is very simple.
  • the electric coupling structure 57 is preferably perpendicular to the conductive layer 7 and is formed of a metal material so as to be suitable for formation by epitaxial growth and etching.
  • the metal can be one or more high-temperature resistant materials such as tungsten, molybdenum, tantalum and nickel.
  • the first high resistance portion 801 is disposed on the first surface of the conductive layer 7 except for the connection area.
  • the number of the first high resistance portions 801 can be selected to be one or more. When the number of the first high resistance portions 801 is selected to be one, the first high resistance portion 801 covers the first surface (i.e., the upper surface) of all the first conductive layers 701 and leaves only the connection area for connecting the electrical coupling structure 57.
  • first high resistance portion 801 covers the first surface of the first conductive layer 701 having the connection area and leaves only the connection area for connecting the electrical coupling structure 57, and each of the remaining first high resistance portions 801 can independently cover the first surface of a first conductive layer 701.
  • the manufacturing material of the first high resistance portion 801 is one of silicon dioxide, silicon nitride, aluminum nitride and aluminum oxide, and the thickness can be selected to be 5nm-1000nm, which is suitable for formation by epitaxial growth and etching.
  • the high resistance structure 8 also includes a second high resistance portion 802 that wraps the electrical coupling structure 57, It is used to insulate the electric coupling structure 57 from the two-dimensional electron gas, intercept the leakage current generated by the two-dimensional electron gas and flowing to the electric coupling structure 57, thereby effectively reducing the risk of failure or damage of the semiconductor device during high-voltage operation.
  • the manufacturing material of the second high-resistance portion 802 is one of silicon dioxide, silicon nitride, aluminum nitride and aluminum oxide, and the thickness can be selected from 5nm to 1000nm, which is suitable for formation by epitaxial growth method and etching method.
  • a method for manufacturing a semiconductor device includes: providing a substrate 1; growing a nucleation layer 201 on the substrate 1; growing a buffer layer 202 on the nucleation layer 201; growing a conductive material layer formed of a metal material on the buffer layer 202; etching the conductive material layer to obtain a conductive layer 7 formed of a remaining conductive material layer; growing a high-resistance material layer formed of an insulating compound on the buffer layer 202 and the conductive layer 7; etching the high-resistance material layer to obtain a first high-resistance portion 801 of a high-resistance structure 8 formed by the remaining high-resistance material layer and located above the conductive layer 7; growing a channel layer 203 on the buffer layer 202 that can cover the first high-resistance portion 801 of the high-resistance structure 8; and growing a barrier layer 204 on the channel layer 203.
  • the barrier layer 204, the channel layer 203 and the first high-resistance portion 801 of the high-resistance structure 8 are opened by etching to obtain a first slot 57a that leaks out of the conductive layer 7; insulating material is grown on the barrier layer 204 and in the first slot 57a; the insulating material on the barrier layer 204 is opened by etching to obtain a source hole region, a gate hole region and a drain hole region; a source 6, a gate 5 and a drain 4 are formed in the source hole region, the gate hole region and the drain hole region respectively by growth, etching and tempering, and a connecting gate is formed on the insulating material.
  • the gate field plate 11 of the electrode 5 is formed by etching the insulating material inside and outside the first slot 57a to obtain a second slot 57b that can leak the conductive layer 7 and is thinner than the first slot 57a; a conductive material is grown in the second slot 57b, and then the conductive material is etched to obtain an electrically coupled structure 57 formed by the conductive material and connecting the conductive layer 7 to the gate 5, and a passivation layer 9 formed by the remaining insulating material and located on the barrier layer 204 and a second high resistance portion 802 of the high resistance structure 8 for covering the electrically coupled structure 57.
  • the corresponding steps can be seen in Figures 9a-9i. It can be understood that the steps of Figures 9a-9i correspond logically to those of Figures 5a-5i. A person skilled in the art can understand the operation steps of Figures 9a-9i on the premise of knowing Figures 5a-5i.
  • the first conductive layers 701 are arranged at intervals along the third direction, wherein the third direction is perpendicular to the first direction and the second direction, that is, the first, second and third directions form a rectangular coordinate system.
  • the semiconductor device further includes a plurality of conductive layers 7 of equal size arranged in the channel layer 203, and a plurality of electrical coupling structures 57 for electrically coupling each conductive layer 7 to the gate 5.
  • the plurality of conductive layers 7 are arranged at intervals along the third direction, and each conductive layer 7 is provided with a connection area for receiving the electrical coupling structure 57, as shown in FIG. 16. It can be understood that the connection relationship between each conductive layer 7 and the corresponding electrical coupling structure 57 can be: the electrical coupling structure 57 is connected to the upper surface or side surface (i.e., end) of the conductive layer 7.
  • each conductive layer 7 along the third direction is greater than the size of a single conductive layer 7 along the second direction, and each conductive layer 7 includes a first surface away from the substrate 1 and a second surface opposite thereto and close to the substrate 1.
  • at least one conductive layer 7 intersects with the orthographic projection of the gate 5 on the substrate 1.
  • a semiconductor device having multiple conductive layers 7 can more effectively reduce the peak value of the electric field intensity near the gate 5, and further improve the breakdown voltage of the device, and improve the working characteristics of the device under high voltage, high power and/or high frequency.
  • the orthographic projection of the conductive layer 7 closest to the drain 4 among the orthographic projections of the multiple conductive layers 7 on the substrate 1 is closer to the orthographic projection of the drain 4 on the substrate 1 than the orthographic projection of the gate 5 on the substrate 1, thereby the first conductive layer 7 closest to the drain 4 can better reduce the peak value of the electric field intensity near the gate 5 and more effectively improve the breakdown voltage of the device.
  • the first surface of the conductive layer 7 is located in the channel layer 203, and the second surface of the conductive layer 7 is connected to the interface between the buffer layer 202 and the channel layer 203 to ensure that the conductive layer 7 is suitable for being formed by epitaxial growth and etching.
  • the thickness of the conductive layer 7 is 10nm-1000nm, and can be 100nm, and can be selected as a conductive type doped semiconductor junction, which is suitable for being formed by epitaxial growth and etching.
  • Each conductive type doped semiconductor junction can be selected as one of an N-type doped semiconductor structure and a P-type doped semiconductor structure, especially a structure formed by silicon doped gallium nitride and having a doping concentration of 1E18/cm3.
  • the conductive layer 7 has a high structural stability due to the use of doped semiconductor materials, and will not react with gases (such as ammonia) in the subsequent steps of the device manufacturing process, ensuring that it can smoothly achieve the effect of regulating the electric field.
  • the size of the conductive layer 7 along the first direction is greater than the size of the conductive layer 7 along the second direction (i.e., the arrangement direction from the substrate 1 to the semiconductor layer 2), thereby reducing the occupancy ratio of the conductive layer 7 to the channel layer 203, effectively avoiding a significant decrease in the two-dimensional electron gas concentration, and ensuring that the switching characteristics of the semiconductor device are still useful and efficient.
  • the electric coupling structure 57 is a rod-shaped structure, and the passivation layer 9 also has avoidance holes through which the power supply coupling structure 57 passes, so that one end of the electric coupling structure 57 is located in the connection area of the semiconductor layer 2 connected to the conductive layer 7, and the other end of the electric coupling structure 57 is located outside the semiconductor layer 2 and connected to the side of the gate 5 facing the source 6.
  • the number of the electric coupling structures 57 is the same as that of the conductive layer 7, so that each conductive layer 7 can be connected to the gate 5 through an electric coupling structure 57 perpendicular thereto.
  • the electric coupling structure 57 in a rod-shaped structure can not only realize the electrical coupling between the conductive layer 7 and the gate 5, but also the structure used is very simple.
  • the electric coupling structure 57 can be perpendicular to the conductive layer 7 and formed of a metal material, so as to be suitable for formation by epitaxial growth and etching.
  • the metal can be one or more high-temperature resistant materials such as tungsten, molybdenum, tantalum and nickel.
  • the high resistance structure 8 includes a first high resistance portion 801, which is arranged above the conductive layer 7 and is used to insulate and isolate the conductive layer 7 from the two-dimensional electron gas, intercept the leakage current generated by the two-dimensional electron gas and flowing to the conductive layer 7, thereby effectively reducing the risk of failure or damage of the semiconductor device during high-voltage operation.
  • the high resistance structure 8 can also prevent the conductive layer 7 from reacting with the ammonia used in the subsequent device manufacturing process, especially in the epitaxial growth, to ensure the effectiveness of the conductive layer 7.
  • the number of the first high resistance portion 801 can be selected as one or more.
  • the first high resistance portion 801 When the number of the first high resistance portion 801 is selected as one, the first high resistance portion 801 covers the first surface of all the conductive layers 7 and leaves a connection area on each conductive layer 7 for connecting to the corresponding electrical coupling structure 57; when the number of the first high resistance portion 801 is selected as multiple, each first high resistance portion 801 can independently cover a conductive layer 7 and leave a connection area on the conductive layer 7 for connecting to the electrical coupling structure 57.
  • the first high resistance portion 801 is made of a material selected from silicon dioxide, silicon nitride, aluminum nitride and aluminum oxide, and has a thickness of 5 nm to 1000 nm, and is suitable for being formed by epitaxial growth and etching.
  • the high-resistance structure 8 also includes a second high-resistance portion 802 that wraps the electrical coupling structure 57, which is used to insulate the electrical coupling structure 57 from the two-dimensional electron gas, intercept the leakage current generated by the two-dimensional electron gas and flowing toward the electrical coupling structure 57, thereby effectively reducing the semiconductor device from being damaged during high-voltage operation.
  • the number of the second high resistance part 802 can be selected as one or more.
  • the second high resistance part 802 wraps all the electric coupling structures 57; when the number of the second high resistance part 802 is selected as more than one, each first high resistance part 801 can independently wrap an electric coupling structure 57, and ensure that each electric coupling structure 57 is wrapped by a second high resistance part 802.
  • the manufacturing material of the second high resistance part 802 is one of silicon dioxide, silicon nitride, aluminum nitride and aluminum oxide, and the thickness can be selected as 5nm-1000nm, which is suitable for formation by epitaxial growth method and etching method.
  • a method for manufacturing a semiconductor device includes: providing a substrate 1; growing a nucleation layer 201 on the substrate 1; growing a buffer layer 202 on the nucleation layer 201; growing a conductive material layer formed of a conductive type doped semiconductor material on the buffer layer 202; growing a high-resistance material layer formed of an insulating compound on the conductive material layer; etching the conductive material layer and the high-resistance material layer to obtain a conductive layer 7 formed by the remaining conductive material layer and a first high-resistance portion 801 of a high-resistance structure 8 formed by the remaining high-resistance material layer and located above the conductive layer 7; growing a channel layer 203 on the buffer layer 202 that can cover the conductive layer 7 and the first high-resistance portion 801; growing a barrier layer 204 on the channel layer 203; and opening the barrier layer 204, the channel layer 203 and the first high-res
  • an insulating material is grown on the barrier layer 204 and in the first slot 57a; the insulating material on the barrier layer 204 is opened by etching to obtain a source hole region, a gate hole region and a drain hole region; a source 6, a gate 5 and a drain 4 are formed in the source hole region, the gate hole region and the drain hole region respectively by growth, etching and tempering, and a gate field plate 11 connected to the gate 5 is formed on the insulating material; the insulating material inside and outside the first slot 57a is opened by etching to obtain a second slot 57b that can leak out the conductive layer 7 and is thinner than the first slot 57a;
  • a conductive material is grown in the second slot 57b and then etched to obtain an electrical coupling structure 57 formed by the conductive material and connecting the conductive layer 7 to the gate 5, a passivation layer 9 formed by the remaining insulating material and located on the barrier layer 204, and a second high-resistance portion 802 of the high-resistance structure 8 formed by the remaining insulating material and used to cover the electrical coupling structure 57.
  • the first surface of the conductive layer 7 is located in the channel layer 203, and the second surface of the conductive layer 7 is also located in the channel layer 203 to ensure that the conductive layer 7 is suitable for being formed by ion implantation and tempering activation.
  • the conductive layer 7 can be a rectangular body that is easy to shape.
  • the thickness of the conductive layer 7 is 10nm-1000nm, which can be 100nm, and can be a conductive type doped semiconductor structure, which is suitable for being formed by ion implantation and tempering activation.
  • the conductive type doped semiconductor junction can be selected as one of an N-type doped semiconductor structure and a P-type doped semiconductor structure, especially a structure formed by silicon doped gallium nitride and having a doping concentration of 5E17/cm3.
  • the size of the conductive layer 7 along the first direction i.e., the arrangement direction of the source 6 to the drain 4) is greater than the size of the conductive layer 7 along the second direction (i.e., the arrangement direction of the substrate 1 to the semiconductor layer 2), thereby reducing the occupation ratio of the conductive layer 7 to the channel layer 203, effectively avoiding a significant decrease in the concentration of the two-dimensional electron gas, and ensuring that the switching characteristics of the semiconductor device are still useful and efficient.
  • the electric coupling structure 57 is a rod-shaped structure, and the passivation layer 9 also has an avoidance hole through which the power coupling structure 57 passes, so that one end of the electric coupling structure 57 is located in the semiconductor layer 2 and connected to the connection area of the conductive layer 7, and the other end of the electric coupling structure 57 is located outside the semiconductor layer 2 and connected to the side of the gate 5 facing the source 6.
  • the electric coupling structure 57 in a rod-shaped structure can not only realize the electrical coupling between the conductive layer 7 and the gate 5, but also the structure used is very simple, as shown in FIG4.
  • the electric coupling structure 57 is preferably perpendicular to the conductive layer 7 and formed of a metal material so as to be suitable for formation by epitaxial growth and etching.
  • the metal can be one or more high-temperature resistant materials such as tungsten, molybdenum, tantalum and nickel.
  • the high resistance structure 8 includes a first high resistance portion 801, which is arranged above the conductive layer 7 and is used to insulate the conductive layer 7 from the two-dimensional electron gas.
  • the manufacturing material of the first high resistance portion 801 can be selected as a high resistance doped semiconductor structure such as boron-doped gallium nitride, and the thickness can be selected to be 5nm-1000nm, which is suitable for formation by ion implantation and tempering activation.
  • the first high resistance portion 801 is arranged on the first surface of the conductive layer 7 except the connection area.
  • the first high resistance portion 801 is a structure formed by boron-doped gallium nitride and having a doping concentration of 5E17/cm3. Since high resistance dopants such as boron ions can disrupt the crystal lattice in the semiconductor structure to achieve high resistance, and use the high resistance characteristics to block the leakage current generated by the two-dimensional electron gas and flowing to the conductive layer 7, the risk of failure or damage of the semiconductor device during high voltage operation can be effectively reduced.
  • the high resistance structure 8 also includes a second high resistance portion 802 that wraps the electrical coupling structure 57, which is used to insulate the electrical coupling structure 57 from the two-dimensional electron gas, intercept the leakage current generated by the two-dimensional electron gas and flowing to the electrical coupling structure 57, thereby effectively reducing the risk of failure or damage of the semiconductor device during high-voltage operation.
  • the manufacturing material of the second high resistance portion 802 is one of silicon dioxide, silicon nitride, aluminum nitride and aluminum oxide, and the thickness can be selected from 5nm to 1000nm, which is suitable for formation by epitaxial growth method and etching method.
  • a method for manufacturing a semiconductor device includes: providing a substrate 1; growing a nucleation layer 201 on the substrate 1; growing a buffer layer 202 on the nucleation layer 201; growing a channel layer 203 on the buffer layer 202; growing a barrier layer 204 on the channel layer 203; injecting a conductive dopant into the channel layer 203 at a fixed area and depth by an ion implantation method to obtain a conductive doped region; annealing and activating the conductive doped region to form it into a conductive layer 7; injecting a high-resistance dopant into the channel layer 203 at a fixed area and depth by an ion implantation method to obtain a high-resistance doped region above the conductive doped region; annealing and activating the high-resistance doped region to form it into a first high-resistance portion 801 of a high-resistance structure 8; and opening the barrier
  • an insulating material is grown on the barrier layer 204 and in the first slot 57a; holes are opened in the insulating material in the barrier layer 204 by etching to obtain a source hole region, a gate hole region and a drain hole region; a source 6, a gate 5 and a drain 4 are formed in the source hole region, the gate hole region and the drain hole region respectively by growth, etching and tempering, and a gate field plate 11 connected to the gate 5 is formed on the insulating material; holes are opened in the insulating material inside and outside the first slot 57a by etching to obtain a second slot 57b that can leak out the conductive layer 7 and is thinner than the first slot 57a; a conductive material is grown in the second slot 57b and etched to obtain an electrical coupling structure 57 formed by the conductive material and connecting the conductive layer 7 to the gate 5, as well as a passivation layer 9 formed by the remaining insulating material and located on the barrier layer 204 and a second high resistance portion 802 of
  • the semiconductor device further includes a conductive layer 7 disposed in the buffer layer 202, and an electrical coupling structure 57 for electrically coupling the conductive layer 7 to the gate 5.
  • the conductive layer 7 includes a first surface away from the substrate 1 and a second surface opposite thereto and close to the substrate 1. One may be selected, and the conductive layer 7 intersects with the orthographic projection of the gate 5 on the substrate 1.
  • the source 6 and the drain 4 can be connected by means of the two-dimensional electron gas, and the conductive layer 7 can adjust the electric field distribution between the channel layer 203 and the barrier layer 204, reduce the peak value of the electric field intensity near the gate 5, and increase the breakdown voltage of the device, and improve the working characteristics of the device under high voltage, high power and/or high frequency.
  • the conductive layer 7 can further reduce the peak value of the electric field intensity near the gate 5 and further increase the breakdown voltage of the device.
  • the first surface of the conductive layer 7 is connected to the side of the buffer layer 202 away from the substrate, and the second surface of the conductive layer 7 is located in the buffer layer 202 to ensure that the conductive layer 7 is suitable for being formed by ion implantation and tempering activation.
  • the conductive layer 7 can be a rectangular body that is easy to shape.
  • the thickness of the conductive layer 7 is 10nm-1000nm, which can be 100nm, and can be a conductive type doped semiconductor structure, which is suitable for being formed by ion implantation and tempering activation.
  • the conductive type doped semiconductor junction can be selected as one of an N-type doped semiconductor structure and a P-type doped semiconductor structure, especially a structure formed by silicon doped gallium nitride and having a doping concentration of 5E17/cm3.
  • the size of the conductive layer 7 along the first direction i.e., the arrangement direction of the source 6 to the drain 4) is greater than the size of the conductive layer 7 along the second direction (i.e., the arrangement direction of the substrate 1 to the semiconductor layer 2), thereby reducing the occupation ratio of the conductive layer 7 to the channel layer 203, effectively avoiding a significant decrease in the concentration of the two-dimensional electron gas, and ensuring that the switching characteristics of the semiconductor device are still useful and efficient.
  • the electric coupling structure 57 is a rod-shaped structure, and the passivation layer 9 also has an avoidance hole through which the power supply coupling structure 57 passes, so that one end of the electric coupling structure 57 is located in the semiconductor layer 2 and connected to the connection area of the conductive layer 7, while the other end of the electric coupling structure 57 is located outside the semiconductor layer 2 and connected to the side of the gate 5 facing the source 6.
  • the electric coupling structure 57 in a rod-shaped structure can not only realize the electrical coupling between the conductive layer 7 and the gate 5, but also the structure used is very simple.
  • the electric coupling structure 57 can be perpendicular to the conductive layer 7 and formed by a metal material so as to be suitable for formation by epitaxial growth and etching.
  • the metal can be one or more high-temperature resistant materials such as tungsten, molybdenum, tantalum and nickel.
  • the high resistance structure 8 includes a first high resistance portion 801 (high resistance layer) formed of a high resistance material, which can cover the first surface of the conductive layer 7 and leave a connection area of the conductive layer 7.
  • the first high resistance portion 801 is used to insulate the conductive layer 7 from the two-dimensional electron gas and intercept the leakage current generated by the two-dimensional electron gas and flowing to the conductive layer 7, thereby effectively reducing the risk of failure or damage of the semiconductor device during high-voltage operation.
  • the first high resistance portion 801 is selected as a whole layer structure, so the positive projection area of the first high resistance portion 801 on the substrate 1 is much larger than the positive projection area of the conductive layer 7 on the substrate 1, which can effectively insulate the conductive layer 7 from the two-dimensional electron gas.
  • the first high resistance portion 801 is selected as a whole layer structure, the first high resistance portion 801 includes a lower surface connected to the side of the buffer layer 202 away from the substrate 1, and an upper surface connected to the side of the channel layer 203 close to the substrate 1.
  • the manufacturing material of the first high resistance portion 801 includes one of insulating compounds such as silicon dioxide, silicon nitride, aluminum nitride and aluminum oxide, and the thickness can be selected to be 5nm-1000nm, which is suitable for formation by epitaxial growth method to simplify the preparation process.
  • the first high resistance portion 801 is a structure formed by boron-doped gallium nitride with a doping concentration of 5E17/cm3. It should be noted that in other embodiments, the first high resistance portion 801 of the high resistance structure 8 can also be a non-whole layer structure, such as a non-whole layer structure that only covers the conductive layer 7 like the third embodiment.
  • the high resistance structure 8 also includes a second high resistance portion 802 (see FIG. 3 ) wrapping the electrical coupling structure 57, which is used to insulate the electrical coupling structure 57 from the two-dimensional electron gas, intercept the leakage current generated by the two-dimensional electron gas and flowing to the electrical coupling structure 57, thereby effectively reducing the risk of failure or damage of the semiconductor device during high-voltage operation.
  • the second high resistance portion 802 is made of one of silicon dioxide, silicon nitride, aluminum nitride and aluminum oxide, and has a thickness of 5nm-1000nm, which is suitable for formation by epitaxial growth and etching.
  • a method for manufacturing a semiconductor device includes: providing a substrate 1; growing a nucleation layer 201 on the substrate 1; growing a buffer layer 202 on the nucleation layer 201; injecting a conductive dopant into the buffer layer 202 at a fixed area and depth by ion implantation to obtain a conductive doped region; annealing and activating the conductive doped region to form it into a conductive layer 7; growing a high resistance layer on the buffer layer 202; growing a channel layer 203 on the first high resistance portion 801 (high resistance layer); growing a barrier layer 204 on the channel layer 203, and opening the barrier layer 204, the channel layer 203 and the high resistance layer by etching to obtain a first slot 57a that leaks out the conductive layer 7; and growing an insulating material on the barrier layer 204 and in the first slot 57a.
  • the insulating material in the barrier layer 204 is opened by etching to obtain a source hole region, a gate hole region and a drain hole region; a source 6, a gate 5 and a drain 4 are respectively formed in the source hole region, the gate hole region and the drain hole region by growth, etching and tempering, and a gate field plate 11 connected to the gate 5 is formed on the insulating material; the insulating material in and outside the first slot 57a is opened by etching to obtain a second slot 57b that can leak out the conductive layer 7 and is thinner than the first slot 57a; a conductive material is grown in the second slot 57b and etched to obtain an electrical coupling structure 57 formed by the conductive material and connecting the conductive layer 7 to the gate 5, as well as a passivation layer 9 formed by the insulating material and located on the barrier layer 204 and a second high-resistance portion 802 of the high-resistance structure 8 for covering the electrical coupling structure 57.
  • the semiconductor device includes a substrate 1 and a semiconductor layer 2 disposed on the substrate 1.
  • the substrate 1 can be formed of silicon (Si), silicon carbide (SiC) or sapphire.
  • the semiconductor layer 2 includes a first semiconductor stack and a second semiconductor layer disposed on the first semiconductor stack.
  • the second semiconductor layer includes a barrier layer 204, the main manufacturing material of which can be selected as alloy nitride, especially aluminum gallium nitride (AlGaN), with a thickness of 5nm-50nm ("nm" means nanometer).
  • the first semiconductor stack includes a buffer layer 202 and a channel layer 203 disposed on the buffer layer 202, wherein the main manufacturing material of the channel layer 203 can be selected as III-V nitride, especially nitrogen nitride (GaN), and the thickness is generally 100nm-1000nm.
  • the channel layer 203 includes III-V group nitrides and the barrier layer 204 includes alloy nitrides
  • the channel layer 203 and the barrier layer 204 are heterostructures. Due to the large difference in polarization intensity and bandgap width between the two, a two-dimensional electron gas (2DEG) is formed at the interface between the two.
  • the channel layer 203 and the barrier layer 204 can be a single layer or multiple layers.
  • the channel layer 203 includes a 300nm high-resistance gallium nitride layer and a 200nm high-temperature gallium nitride layer arranged in a direction away from the substrate 1, and the barrier layer 204 includes a 1nm aluminum nitride layer, a 20nm aluminum gallium nitride layer, and a 2nm gallium nitride layer arranged in a direction away from the channel layer 203.
  • the semiconductor layer 2 may also include a nucleation layer 201 disposed on the substrate 1, and a buffer layer 202 disposed on the nucleation layer 201.
  • the nucleation layer 201 is formed of aluminum carbide (AlN) or gallium nitride (GaN) with a thickness of 10nm-500nm, and is used to improve the growth quality of the buffer layer 202 and has an isolation effect.
  • the buffer layer 202 is formed of iron-doped gallium nitride, carbon-doped gallium nitride, gallium nitride (GaN) or aluminum gallium nitride (AlGaN) with a thickness of 100nm-10um, and is used to improve the growth quality of III-V group nitrides.
  • the buffer layer 202 can be a one-layer or multi-layer structure.
  • the buffer layer 202 can be a three-layer structure, the first layer is aluminum gallium nitride with an aluminum content of 75% and a total thickness of 400nm, the second layer is aluminum gallium nitride with an aluminum content of 50% and a total thickness of 900nm, and the third layer is aluminum gallium nitride with an aluminum content of 50% and a total thickness of 100nm. 25%, aluminum gallium nitride with a total layer thickness of 1500nm.
  • the semiconductor device also includes a gate 5, a drain 4 and a source 6 mainly arranged on the barrier layer 204.
  • the source 6 and the drain 4 can both be a single-layer structure or a multi-layer structure, and can include a titanium (Ti) layer, an aluminum (Al) layer, a nickel (Ni) layer and a gold (Au) layer connected in sequence.
  • the source 6 is in ohmic contact with the barrier layer 204 and is electrically coupled with the two-dimensional electron gas.
  • the drain 4 is also in ohmic contact with the barrier layer 204 and is electrically coupled with the two-dimensional electron gas.
  • the gate 5 mainly includes one or two of a nickel (Ni) layer and a gold (Au) layer, and is in Schottky contact with the barrier layer 204.
  • Ni nickel
  • Au gold
  • the semiconductor device further includes a passivation layer 9.
  • the passivation layer 9 is disposed on the barrier layer 204 and avoids the gate 5, the drain 4 and the source 6, that is, the passivation layer 9 has a plurality of avoidance holes for the gate 5, the drain 4 and the source 6 to penetrate respectively, so that the passivation layer 9 is used to insulate and isolate the gate 5, the drain 4 and the source 6 to prevent the semiconductor device from malfunctioning due to erroneous connection between the electrodes.
  • the passivation layer 9 is made of a material including one of insulating compounds such as silicon dioxide, silicon nitride, aluminum nitride and aluminum oxide.
  • the semiconductor device further includes a conductive layer 7 disposed in the channel layer 203, and an electrical coupling structure 57 for electrically coupling the conductive layer 7 to the gate 5.
  • the conductive layer 7 includes a first surface away from the substrate 1, a second surface opposite thereto and close to the substrate 1, and a side surface connected to the first surface and the second surface.
  • the conductive layer 7 can be selected as one, and the conductive layer 7 intersects with the positive projection of the gate 5 on the substrate 1.
  • the source 6 and the drain 4 can be connected by means of a two-dimensional electron gas, and the conductive layer 7 can adjust the electric field distribution between the channel layer 203 and the barrier layer 204, reduce the peak value of the electric field intensity near the gate 5, and increase the breakdown voltage of the device, thereby improving the working characteristics of the device under high voltage, high power and/or high frequency.
  • the conductive layer 7 can further reduce the peak electric field strength near the gate 5 and further improve the breakdown voltage of the device.
  • the first surface of the conductive layer 7 is located in the channel layer 203, and the second surface of the conductive layer 7 is connected to the interface between the buffer layer 202 and the channel layer 203 to ensure that the conductive layer 7 is suitable for being formed by epitaxial growth and etching.
  • the conductive layer 7 can be a rectangular body that is easy to shape, as shown in Figure 4.
  • the thickness of the conductive layer 7 is 10nm-1000nm, which can be 100nm, and can be a structure formed by a metal material, which is suitable for being formed by epitaxial growth and etching.
  • the conductive layer 7 can be one or more of high temperature resistant materials such as tungsten, molybdenum, titanium and nickel.
  • the size of the conductive layer 7 along the first direction is larger than the size of the conductive layer 7 along the second direction (i.e., the arrangement direction of the substrate 1 to the semiconductor layer 2), so that its structure is flattened, thereby reducing the proportion of the conductive layer 7 occupying the communication layer 3, effectively avoiding the significant decrease in the concentration of the two-dimensional electron gas due to the excessive volume of the conductive layer 7, and ensuring that the switching characteristics of the semiconductor device are still useful and efficient.
  • the electric coupling structure 57 is a rod-shaped structure, and the passivation layer 9 also has avoidance holes through which the power supply coupling structure 57 respectively penetrates, so that one end of the electric coupling structure 57 is located in the semiconductor layer 2 and connected to the connection area of the conductive layer 7, and the other end of the electric coupling structure 57 is located outside the semiconductor layer 2 and connected to the side of the gate 5 facing the source 6.
  • the electric coupling structure 57 in a rod-shaped structure can not only realize the electrical coupling between the conductive layer 7 and the gate 5, but also the structure used is very simple.
  • the electric coupling structure 57 is preferably perpendicular to the conductive layer 7 and formed by a metal material so as to be suitable for formation by epitaxial growth and etching.
  • the electric coupling structure 57 can be one or more high-temperature resistant materials such as tungsten, molybdenum, tantalum and nickel.
  • the high-resistance structure 8 includes a first high-resistance portion 801, which is arranged above the conductive layer 7, and is used to insulate the conductive layer 7 from the two-dimensional electron gas, intercept the leakage current generated by the two-dimensional electron gas flowing to the conductive layer 7, thereby effectively reducing the risk of failure or damage of the semiconductor device during high-voltage operation.
  • the high-resistance structure 8 can also prevent the conductive layer 7 from reacting with the ammonia used in the subsequent device manufacturing process, especially with the epitaxial growth, to ensure that it can smoothly achieve the above-mentioned effect.
  • the first high-resistance portion 801 is arranged on the first surface of the conductive layer 7 except the connection area.
  • the manufacturing material of the first high-resistance portion 801 is one of silicon dioxide, silicon nitride, aluminum nitride and aluminum oxide, and the thickness can be selected from 5nm-1000nm to ensure that it is suitable for formation by epitaxial growth and etching.
  • the high-resistance structure 8 also includes a second high-resistance portion 802 that wraps the electrical coupling structure 57, which is used to insulate the electrical coupling structure 57 from the two-dimensional electron gas, intercept the leakage current generated by the two-dimensional electron gas and flowing to the electrical coupling structure 57, thereby effectively reducing the risk of failure or damage of the semiconductor device during high-voltage operation.
  • the second barrier portion 802 is similar to a sleeve-shaped structure, and its manufacturing material is one of silicon dioxide, silicon nitride, aluminum nitride and aluminum oxide, and the thickness can be selected to be 5nm-1000nm to ensure that it is suitable for formation by epitaxial growth and etching.
  • the semiconductor device further includes a barrier material 8', which is connected to the high resistance structure 8 and covers the side of the conductive layer 7.
  • the manufacturing steps and selected materials of the barrier material 8' and the first high resistance portion 801 of the high resistance structure 8 may be the same or different.
  • the semiconductor device may further include a gate field plate 11 disposed on the passivation layer 9 and connected to the gate 5.
  • the gate field plate 11 can assist the conductive layer 7 in adjusting the electric field distribution between the channel layer 203 and the barrier layer 204, further reducing the peak value of the electric field intensity near the gate 5, thereby significantly improving the breakdown voltage of the device.
  • a method for manufacturing a semiconductor device includes: providing a substrate 1, as shown in Figure 25a for details; growing a nucleation layer 201 on the substrate 1; growing a buffer layer 202 on the nucleation layer 201, as shown in Figure 25b for details; growing a conductive material layer formed of a metal material on the buffer layer 202; etching the conductive material layer to obtain a conductive layer 7 formed of a remaining conductive material layer; growing a high-resistance material layer formed of an insulating compound on the buffer layer 202 and the conductive layer 7; etching the high-resistance material layer to obtain a first high-resistance portion 801 of a high-resistance structure 8 formed by the remaining high-resistance material layer and located above the conductive layer 7, and a barrier material 8' covering the side of the conductive layer 7, as shown in Figure 25c for details; growing a channel layer 203 on the buffer layer 202 that can cover the first high-
  • the barrier layer 204, the channel layer 203 and the first high-resistance portion 801 of the high-resistance structure 8 are opened by etching to obtain a first slot 57a that leaks out of the conductive layer 7, as shown in FIG. 25e; an insulating material 9a is grown on the barrier layer 204 and in the first slot 57a, as shown in FIG.
  • the insulating material 9a on the barrier layer 204 is opened by etching to obtain a source hole region, a gate hole region and a drain hole region; a source 6, a gate 5 and a drain 4 are formed in the source hole region, the gate hole region and the drain hole region respectively by growth, etching and tempering, and at the same time, a connection to the gate 5 is formed on the insulating material 9a.
  • the gate field plate 11 is shown in FIG25g for details; the insulating material 9a located inside and outside the first slot 57a is opened by etching to obtain a second slot 57b which is thinner than the first slot 57a and through which the conductive layer 7 can leak out, as shown in FIG25h for details; a conductive material is grown in the second slot 57b, and then the conductive material is etched to obtain an electrical coupling structure 57 formed by the conductive material and connecting the conductive layer 7 to the gate 5, as well as a passivation layer 9 formed by the remaining insulating material 9a and located on the barrier layer 204 and a second high resistance portion 802 of the high resistance structure 8 used to cover the electrical coupling structure 57, as shown in FIG25i for details.
  • the main difference between the seventh embodiment and the first embodiment is the material of the conductive layer 7 and the arrangement of the barrier material 8'.
  • the relevant technical features of this embodiment on the premise of the first embodiment.
  • the conductive layer 7 includes first conductive layers 701 spaced apart along the first direction (i.e., the arrangement direction of the source 5 to the drain 4) and second conductive layers 702 connecting the spaced apart first conductive layers 701, and a connection region in contact with the electrical coupling structure 57 is provided on one of the plurality of first conductive layers 701.
  • the connection region is located on an extended region of the first conductive layer 701 having the connection region extending away from the second conductive layer 702.
  • the second conductive layer 702 is perpendicular to the first conductive layer 701 to reduce the difficulty of manufacturing.
  • the orthographic projection of at least one first conductive layer 701 on the substrate 1 intersects with the orthographic projection of the gate 5 on the substrate 1.
  • the source 6 and the drain 4 can be connected by means of the two-dimensional electron gas, and the conductive layer 7 mainly uniformly adjusts the electric field distribution between the channel layer 203 and the barrier layer 204 by means of the multiple first conductive layers 701.
  • the semiconductor device having the first conductive layer 701 and the second conductive layer 702 can more effectively reduce the peak value of the electric field intensity near the gate 5, and further improve the breakdown voltage of the device, and improve the working characteristics of the device under high voltage, high power and/or high frequency.
  • the orthographic projection of the first conductive layer 701 closest to the drain 4 among the orthographic projections of the multiple first conductive layers 701 on the substrate 1 is closer to the orthographic projection of the drain 4 on the substrate 1 than the orthographic projection of the gate 5 on the substrate 1, thereby the first conductive layer 701 closest to the drain 4 can better reduce the peak value of the electric field intensity near the gate 5 and more effectively improve the breakdown voltage of the device.
  • the first surface of the conductive layer 7 is located in the channel layer 203, and the second surface of the conductive layer 7 is connected to the surface of the buffer layer 202 away from the substrate 1 to ensure that the conductive layer 7 is suitable for being formed by epitaxial growth and etching.
  • Each first conductive layer 701 can be a rectangular body that is easy to form.
  • the thickness of the conductive layer 7 is 10nm-1000nm, which can be 100nm, and can be a structure formed by a metal material, which is suitable for being formed by epitaxial growth and etching.
  • the conductive layer 7 can be one or more of high temperature resistant materials such as tungsten, molybdenum, tantalum and nickel.
  • each first conductive layer 701 along the first direction is greater than the size of the first conductive layer 7 along the second direction (i.e., the arrangement direction from the substrate 1 to the semiconductor layer 2), thereby reducing the proportion of the conductive layer 7 occupying the communication layer 3, effectively avoiding the significant decrease in the concentration of the two-dimensional electron gas, and ensuring that the switching characteristics of the semiconductor device are still useful and efficient.
  • the electric coupling structure 57 is a rod-shaped structure, and the passivation layer 9 also has an avoidance hole through which the power coupling structure 57 passes, so that one end of the electric coupling structure 57 is located in the semiconductor layer 2 and is internally connected to the connection area of the first conductive layer 701, while the other end of the electric coupling structure 57 is located outside the semiconductor layer 2 and is connected to the side of the gate 5 facing the source 6.
  • the electric coupling structure 57 in a rod-shaped structure can not only realize the electrical coupling between the conductive layer 7 and the gate 5, but also the structure used is very simple.
  • the electric coupling structure 57 is preferably perpendicular to the conductive layer 7 and is formed of a metal material so as to be suitable for formation by epitaxial growth and etching.
  • the metal can be one or more high-temperature resistant materials such as tungsten, molybdenum, titanium and nickel.
  • the first high resistance portion 801 is disposed on the first surface of the conductive layer 7 except the connection area.
  • the number of the first high resistance portion 801 can be selected as one or more. When the number of the first high resistance portion 801 is selected as one, the first high resistance portion 801 covers the first surface (i.e., the upper surface) of all the first conductive layers 701 and leaves only the connection area for connecting the electrical coupling structure 57. When the number of the first high resistance portion 801 is selected as multiple, one first high resistance portion 801 covers the first surface of the first conductive layer 701 having the connection area and leaves only the connection area for connecting the electrical coupling structure 57, and each of the remaining first high resistance portions 801 can independently cover the first surface of a first conductive layer 701.
  • the manufacturing material of the first high resistance portion 801 is one of silicon dioxide, silicon nitride, aluminum nitride and aluminum oxide, and the thickness can be selected as 5nm-1000nm, which is suitable for being formed by epitaxial growth method and etching method.
  • the high resistance structure 8 also includes a second high resistance portion 802 that wraps the electrical coupling structure 57, which is used to insulate the electrical coupling structure 57 from the two-dimensional electron gas, intercept the leakage current generated by the two-dimensional electron gas and flowing to the electrical coupling structure 57, thereby effectively reducing the risk of failure or damage of the semiconductor device during high-voltage operation.
  • the manufacturing material of the second high resistance portion 802 is one of silicon dioxide, silicon nitride, aluminum nitride and aluminum oxide, and the thickness can be selected from 5nm to 1000nm, which is suitable for formation by epitaxial growth method and etching method.
  • a method for manufacturing a semiconductor device includes: providing a substrate 1; growing a nucleation layer 201 on the substrate 1; growing a buffer layer 202 on the nucleation layer 201; growing a conductive material layer formed of a metal material on the buffer layer 202; etching the conductive material layer to obtain a conductive layer 7 formed of a remaining conductive material layer; growing a high-resistance material layer formed of an insulating compound on the buffer layer 202 and the conductive layer 7; etching the high-resistance material layer to obtain a first high-resistance portion 801 of a high-resistance structure 8 formed by the remaining high-resistance material layer and located above the conductive layer 7, and a barrier material 8' covering the side of the conductive layer 7; growing a channel layer 203 on the buffer layer 202 that can cover the first high-resistance portion 801 of the high-resistance structure 8 and the barrier material 8'; and
  • the barrier layer 204, the channel layer 203 and the first barrier portion 801 of the first barrier structure 8 are opened by etching to obtain a first slot 57a through which the conductive layer 7 is leaked; insulating material is grown on the barrier layer 204 and in the first slot 57a; the insulating material on the barrier layer 204 is opened by etching to obtain a source hole region, a gate hole region and a drain hole region; a source 6, a gate 5 and a drain 4 are formed in the source hole region, the gate hole region and the drain hole region respectively by growth, etching and tempering, and a connection is formed on the insulating material at the same time.
  • the gate field plate 11 of the gate 5 is formed; the insulating material inside and outside the first slot 57a is opened by etching to obtain a second slot 57b that can leak the conductive layer 7 and is thinner than the first slot 57a; a conductive material is grown in the second slot 57b, and then the conductive material is etched to obtain an electrical coupling structure 57 formed by the conductive material and connecting the conductive layer 7 to the gate 5, and a passivation layer 9 formed by the remaining insulating material and located on the barrier layer 204 and a second high resistance portion 802 of the high resistance structure 8 for covering the electrical coupling structure 57.
  • the corresponding steps can be seen in Figures 27a-27i.
  • the material of the conductive layer 7 and the setting of the barrier material 8' is the material of the conductive layer 7 and the setting of the barrier material 8'.
  • the first conductive layers 701 are arranged at intervals along the third direction, wherein the third direction is perpendicular to the first direction and the second direction, that is, the first, second, and third directions form a rectangular coordinate system.
  • the main difference between the ninth embodiment and the third embodiment is the material of the conductive layer 7 and the arrangement of the barrier material 8'.
  • the semiconductor device further includes a plurality of conductive layers 7 of equal size disposed in the channel layer 203, and a plurality of electrical coupling structures 57 for electrically coupling each conductive layer 7 to the gate 5.
  • the plurality of conductive layers 7 are arranged at intervals along the first direction, and each conductive layer 7 is provided with a connection area for receiving the electrical coupling structure 57, as shown in FIG. 16.
  • the total size of each conductive layer 7 along the third direction is greater than the total size of a single conductive layer 7 along the second direction.
  • the dimension in the direction of the conductive layer 7 is 200, and each conductive layer 7 includes a first surface away from the substrate 1 and a second surface opposite thereto and close to the substrate 1.
  • At least one conductive layer 7 intersects with the orthographic projection of the gate 5 on the substrate 1.
  • the source 6 and the drain 4 can be connected by means of the two-dimensional electron gas, and the conductive layer 7 can adjust the electric field distribution between the channel layer 203 and the barrier layer 204.
  • a semiconductor device with multiple conductive layers 7 can more effectively reduce the peak value of the electric field intensity near the gate 5, and further increase the breakdown voltage of the device, and improve the working characteristics of the device under high voltage, high power and/or high frequency.
  • the orthographic projection of the conductive layer 7 closest to the drain 4 among the orthographic projections of the multiple conductive layers 7 on the substrate 1 is closer to the orthographic projection of the drain 4 on the substrate 1 than the orthographic projection of the gate 5 on the substrate 1, thereby the first conductive layer 7 closest to the drain 4 can better reduce the peak electric field strength near the gate 5 and more effectively improve the breakdown voltage of the device.
  • the first surface of the conductive layer 7 is located in the channel layer 203, and the second surface of the conductive layer 7 is also located in the channel layer 203 to ensure that the conductive layer 7 is suitable for being formed by ion implantation and tempering activation.
  • the conductive layer 7 can be a rectangular body that is easy to form.
  • the thickness of the conductive layer 7 is 10nm-1000nm, which can be 100nm, and can be a conductive type doped semiconductor structure, which is suitable for being formed by ion implantation and tempering activation.
  • the conductive type doped semiconductor junction can be selected as one of an N-type doped semiconductor structure and a P-type doped semiconductor structure, especially a structure formed by silicon doped gallium nitride and having a doping concentration of 5E17/cm3.
  • the size of the conductive layer 7 along the first direction i.e., the arrangement direction of the source 6 to the drain 4) is greater than the size of the conductive layer 7 along the second direction (i.e., the arrangement direction of the substrate 1 to the semiconductor layer 2), thereby reducing the occupation ratio of the conductive layer 7 to the channel layer 203, effectively avoiding a significant decrease in the concentration of the two-dimensional electron gas, and ensuring that the switching characteristics of the semiconductor device are still useful and efficient.
  • This manufacturing method is different from the seventh embodiment in that after the first epitaxial growth of the channel layer 203 to a certain height, a metal material layer is grown by the same growth method and then etched to form a conductive layer 7 composed of metal material, and then a second epitaxial growth is performed to grow the remaining channel layer 203.
  • the first surface of the conductive layer 7 is located in contact with the side of the buffer layer 202 away from the substrate, and the second surface of the conductive layer 7 is located in the buffer layer 202 to ensure that the conductive layer 7 is suitable for being formed by ion implantation and tempering activation.
  • the conductive layer 7 can be a rectangular body that is easy to shape.
  • the thickness of the conductive layer 7 is 10nm-1000nm, for example, it can be 100nm, and it can be selected as a conductive type doped semiconductor structure, which is suitable for being formed by ion implantation and tempering activation.
  • the conductive type doped semiconductor junction can be selected as one of an N-type doped semiconductor structure and a P-type doped semiconductor structure, especially a structure formed by silicon doped gallium nitride and having a doping concentration of 5E17/cm3.
  • the size of the conductive layer 7 along the first direction i.e., the arrangement direction of the source 6 to the drain 4) is greater than the size of the conductive layer 7 along the second direction (i.e., the arrangement direction of the substrate 1 to the epitaxial layer 2), thereby reducing the occupation ratio of the conductive layer 7 to the channel layer 203, effectively avoiding the significant decrease in the concentration of the two-dimensional electron gas, and ensuring that the switching characteristics of the semiconductor device are still useful and efficient.
  • the first high resistance portion 801 can cover the first surface of the conductive layer 7 and leave a connection area of the conductive layer 7.
  • the first high resistance portion 801 is used to insulate the conductive layer 7 from the two-dimensional electron gas and intercept the leakage current generated by the two-dimensional electron gas and flowing to the conductive layer 7, thereby effectively reducing the risk of failure or damage of the semiconductor device during high-voltage operation.
  • the first high resistance portion 801 is selected as a whole layer structure, so the positive projection area of the first high resistance portion 801 on the substrate 1 is much larger than the positive projection area of the conductive layer 7 on the substrate 1, which can effectively insulate the conductive layer 7 from the two-dimensional electron gas.
  • the first high resistance portion 801 is selected as a whole layer structure, the first high resistance portion 801 includes a lower surface connected to the side of the buffer layer 202 away from the substrate 1, and an upper surface connected to the side of the channel layer 203 close to the substrate 1.
  • the first high resistance portion 801 of the high resistance structure 8 can also be a non-whole layer structure, such as a non-whole layer structure that only covers the conductive layer 7 like the tenth embodiment.
  • This manufacturing method is different from the eleventh embodiment in that after the buffer layer 202 is first epitaxially grown to a certain height, a metal material layer is grown by the same growth method and then etched to form a conductive layer 7 composed of metal material, and then a second epitaxial growth is performed to grow the remaining buffer layer.
  • the electrical coupling structure 57 may also be located below the gate 5.
  • the electrical coupling structure 57 includes a slot body and a conductive material, the slot body extends from the surface of the second semiconductor layer (204) into the semiconductor layer, the conductive material fills the slot body, one end of the conductive material is directly connected to the conductive layer, and the other end of the conductive material is directly connected to the lower surface of the gate 5, and the second high resistance portion 802 wraps the conductive material filled in the slot body.
  • the electrical coupling structure 57 can be located on the side or below the gate 5. This embodiment is only used as an example to show a variation of the first embodiment.
  • connection area for connecting with the electrical coupling structure 57 is arranged on the first surface of the conductive layer 7, and the first high resistance portion 801 is arranged on the first surface other than the connection area of the conductive layer 7.
  • this embodiment further proposes that the connection area of the conductive layer 7 may also be located on the side of the conductive layer 7, rather than the first surface of the conductive layer 7 in the first embodiment.
  • the electrical coupling structure 57 is connected to the side of the connection area 703. Therefore, correspondingly, referring to FIG35, this embodiment continues to propose that the electrical coupling structure 57 can also be connected to the upper surface of the connection area 703. It can be understood that the variation of this connection method can be applied at least in the second and third embodiments.
  • the present disclosure mainly describes the overall technical solution through two aspects, namely, the embodiments corresponding to the conductive layer made of semiconductor material and the embodiments corresponding to the conductive layer made of metal material. Furthermore, the main difference between the above two aspects lies in the setting of the barrier material. However, this does not mean that the embodiments corresponding to the conductive layer made of metal material must be provided with the barrier material, or that the embodiments corresponding to the conductive layer made of semiconductor material must not be provided with the barrier material.
  • the embodiments corresponding to the above two aspects can be arbitrarily combined without conflict, and are all in the present disclosure. Within the scope of protection.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

一种半导体器件及其制造方法，其中半导体器件包括：衬底（1）；半导体层（2），其设置在衬底（1）上，包括：第一半导体叠层和设置在第一半导体叠层上的第二半导体层；第一半导体叠层和第二半导体层之间的界面处形成有二维电子气；设置在第二半导体层上且间隔布置的源极（6）、漏极（4）和栅极（5）；导电层（7），其设置在半导体层（2）内并位于衬底（1）与二维电子气之间；电耦合结构（57），其一端与栅极（5）电连接，另一端向半导体层（2）内延伸并与导电层（7）电连接；以及高阻结构（8），其至少部分地设置在导电层（7）与二维电子气之间，以及电耦合结构（57）与二维电子气之间。该半导体器件能够有效降低半导体器件高电压下栅极的电场强度，从而提高器件的击穿电压。

Description

HEMT器件及半导体器件 技术领域
本公开一般地涉及半导体器件领域。更具体地，本公开涉及一种HEMT器件及半导体器件。
背景技术
半导体器件又称高电子迁移率晶体管(High electron mobility transistor,HEMT)，凭借其高电子迁移率、高二维电子气浓度和高击穿电压等特性，在高频、高压、高温和高功率密度领域有着广泛的应用。
半导体器件的一种令人期望的属性是具有更高的击穿电压，栅场板由于能够提高器件的击穿电压，所以被广泛应用在HEMT器件中。栅场板通常设在半导体器件顶部的钝化层上并与栅极或源极连接，其虽然可以提高器件的击穿电压，但是人们还是希望研究出一种能够提高器件击穿电压的新技术，最好可以是在此新技术上继续应用栅场板，以便大幅度地提高器件的击穿电压。
发明内容
为了解决上述部分或全部问题，本公开提供了一种HEMT器件及半导体器件，该HEMT在不使用栅场板的情况下就具有较高的击穿电压，在使用栅场板的情况下将具有更高的击穿电压。
根据本公开，提供了一种HEMT器件，包括：衬底；外延层，设置在所述衬底上，包括：第一半导体叠层和设置在所述第一半导体叠层上的第二半导体层；所述第一半导体叠层和所述第二半导体层之间的界面处形成有二维电子气；源极、漏极、和栅极，设置在所述第二半导体层上且间隔布置；导电层，设置所述外延层内并位于所述衬底与所述二维电子气之间；电耦合结构，其一端与所述栅极电连接，另一端向所述外延层内延伸并与所述导电层电连接；以及高阻结构，至少部分地设置在所述导电层与所述二维电子气之间，以及所述电耦合结构与所述二维电子气之间。
一种半导体器件，包括：衬底；外延层，设置在所述衬底上，包括：第一半导体叠层和设置在所述第一半导体叠层上的第二半导体层；所述第一半导体叠层和所述第二半导体层之间的界面处形成有二维电子气；源极、漏极和栅极，设置在所述第二半导体层上且间隔布置；导电层，间隔设置在所述外延层内并位于所述衬底与所述二维电子气之间；电耦合结构，用于将所述导电层电耦合至所述栅极；第一高阻部，用于绝缘隔离所述导电层与所述二维电子气；以及第二高阻部，用于绝缘隔离所述电耦合结构与所述二维电子气。
在本公开实施例提供的HEMT器件及半导体器件，通过在器件内部设置能够与栅极电耦合的导电层，并且通过阻隔结构将导电层与二维电子气之间、以及电耦合结构与二维电子气之间隔离，从而能够通过栅极所连接的导电层有效降低半导体器件高电压下栅极的电场强度，从而提高器件的击穿电压。
附图说明
下面将结合附图来对本公开的优选实施例进行详细地描述。在图中：
图1为本公开实施例一所提供的半导体器件的俯视结构示意图；
图2为图1中半导体器件的结构的A-A线的剖视图；
图3为图1中半导体器件的结构的B-B线的剖视图；
图3A为另一个实施例中半导体器件的结构的B-B线的剖视图；
图4显示了图1所示半导体器件的导电层及电耦合结构；
图5a到图5i显示了本公开实施例一的半导体器件的制造过程图；
图6为本公开实施例二所提供的半导体器件的俯视结构示意图；
图7为图6中半导体器件的结构的A-A线的剖视图；
图8显示了图6所示半导体器件的导电层及电耦合结构；
图9a到图9i显示了本公开实施例二的半导体器件的制造过程图；
图10为本公开实施例三所提供的半导体器件的俯视结构示意图；
图11为图10中半导体器件的结构的A-A线的剖视图；
图12a到图12i显示了本公开实施例三的半导体器件的制造过程图；
图13为本公开实施例四所提供的半导体器件的俯视结构示意图；
图14为图13中半导体器件的结构的A-A线的剖视图；
图15a到图15i显示了本公开实施例四的半导体器件的制造过程图；
图16显示了图13所示半导体器件的导电层及电耦合结构；
图17为本公开实施例五所提供的半导体器件的俯视结构示意图；
图18为图17中半导体器件的结构的A-A线的剖视图；
图19a到图19i显示了本公开实施例五的半导体器件的制造过程图；
图20为本公开实施例六所提供的半导体器件的俯视结构示意图；
图21为图20中半导体器件的结构的A-A线的剖视图；
图22a到图22i显示了本公开实施例六的半导体器件的制造过程图；
图23为本公开实施例七所提供的半导体器件的A-A线的剖视图；
图24为图23中半导体器件的结构的B-B线的剖视图；
图25a到图25i显示了本公开实施例七的半导体器件的制造过程图；
图26为本公开实施例八所提供的半导体器件的A-A线的剖视图；
图27a到图27i显示了本公开实施例八的半导体器件的制造过程图；
图28为本公开实施例九所提供的半导体器件的A-A线的剖视图；
图29为本公开实施例十所提供的半导体器件的A-A线的剖视图；
图30为本公开实施例十一所提供的半导体器件的A-A线的剖视图；
图31为本公开实施例十二所提供的半导体器件的A-A线的剖视图；
图32为本公开实施例十三所提供的半导体器件的俯视结构示意图；
图33为图32中半导体器件的结构的A-A线的剖视图；
图34为本公开实施例十四所提供半导体器件的结构的A-A线的剖视图；
图35为本公开实施例十五所提供的半导体器件的的导电层及电耦合结构。
在附图中，相同的部件使用相同的附图标记。附图并未按照实际的比例绘制。
具体实施方式
下面将结合附图对本公开做进一步说明。
在本申请的描述中，“外延生长”指在待处理材料上生长一层有一定要求的层结构。涉及“外延生长”的技术可以包含金属有机化学气相沉积技术(metal-organic chemical vapor deposition，MOCVD)、液相外延技术(liquid Phase Epitaxy，LPE)、气相外延技术(vapor phase epitaxy，VPE)，分子束外延技术(molecular Beam Epitaxy，MBE)，原子层沉积技术(atomic layer deposition，ALD)等。对于本领域的普通技术人员而言，可以根据实际情况选择合适的外延生长技术。
在本申请的描述中，“刻蚀”应按广义理解，即在待处理材料表面生长一层光刻胶，透过掩模对光刻胶进行选择性曝光和显影，以在待处理材料表面上留下与掩模图形相同的光刻胶层，然后用化学或物理方法对待处理材料进行选择腐蚀，并且最后剥离光刻胶层以在待处理材料上形成与掩模图形对应的结构。
在本申请的描述中，“离子注入法”是在待处理材料表面生长一层光刻胶，透过掩模对光刻胶进行选择性曝光和显影，以在待处理材料表面上留下与掩模图形相同的光刻胶层，然后将带电离子加速到一定高能量后注入待处理材料内，并且最后剥离光刻胶层以在待处理材料内形成与掩模图形对应的结构。离子注入法带来的负面影响是由于离子碰撞而导致待处理材料产生晶格断裂或者损伤，所以需要进行退火处理来消除断裂或损伤。
在本申请的描述中，“上”或“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
本公开各个实施例均提供了一种半导体器件，或者说是高电子迁移率晶体管(High electron mobility transistor)，具有高击穿电压和高电导率等优点，可以作为半导体功率器件或半导体射频器件，在基站通信、物联网、航空航天和雷达系统等领域得到了广泛应用。
如图1-3，6-7，10-11，13-14，17-18，20-21，23-24，26，28-31所示，半导体器件包括衬底1及设在衬底1上的半导体层2。
示例性地，如图1-2，和23-24所示，衬底1可由硅(Si)、碳化硅(SiC)或蓝宝石(Sapphire)形成。该半导体层2包括第一半导体叠层和设置在第一半导体叠层上的第二半导体层。在一些实施方式中，第二半导体层包括势垒层204，其主要制造材料可选为合金氮化物，特别是铝镓氮(AlGaN)，厚度为5nm-50nm(“nm”为纳米)。第一半导体叠层包括缓冲层202和设在缓冲层202上的沟道层203，其中沟道层203的主要制造材料可选为III-V族氮化物，特别是氮化氮(GaN)，厚度一般为100nm-1000nm。当沟道层203包含III-V族氮化物而势垒层204包含合金氮化物时，沟道层203和势垒层204为异质结构，由于两者之间存在较大的极化强度差和禁带宽度差，使得两者的界面处形成有二维电子气(Two-dimensional electron gas,2DEG)。其中，沟道层203和势垒层204皆可以为一层或多层结构。在一些实施方式中，沟道层203包含沿着远离衬底1方向排布的300nm高阻氮化镓层和200nm高温氮化镓层，而势垒层204包括沿着远离沟道层203方向排布的1nm氮化铝层、20nm铝镓氮层和2nm氮化镓层。
示例性地，半导体层2还可包括设在衬底1上的成核层201，缓冲层202设在成核层201上。成核层201由碳化铝(AIN)或氮化镓(GaN)形成，厚度为10nm-500nm，用于提高缓冲层202的生长质量，并具有隔离作用。而缓冲层202由铁掺杂氮化镓、碳掺杂氮化镓、氮化镓(GaN)或铝镓氮(AlGaN)形成，厚度为100nm-10um，用于提高III-V族氮化物的生长质量。缓冲层202可以为一层或多层结构。当衬底1选为硅材料时，缓冲层202可以为三层结构，第一层是含铝量为75％、整层厚度为400nm的铝镓氮，第二层是含铝量为50％、整层厚度为900nm的铝镓氮，第三层是含铝量为25％、整层厚度为1500nm的铝镓氮。
如图1-3，6-7，10-11，13-14，17-18，20-21，23-24，26，28-31所示，半导体器件还包括设置在第二半导体层上的端子层。
示例性地，如图1-2，和23-24所示，半导体器件还包括设在势垒层204上的端子层。该端子层包括间隔布置的栅极5、漏极4和源极6。源极6和漏极4均可为一层结构或多层结构，示例性地，漏极4和源极6分别可包括顺序相连的钛(Ti)层、铝(Al)层、镍(Ni)层和金(Au)层。源极6与势垒层204进行欧姆接触，并与二维电子气进行电耦合。漏极4也与势垒层204进行欧姆接触，并与二维电子气进行电耦合。栅极5主要包括镍(Ni)层和金(Au)层中的一个或两个，并与势垒层204进行肖特基接触。在使用半导体器件时，改变栅极5的电场可以调控二维电子气并控制源极6和漏极4的导通与关断。
示例性地，半导体器件还包括钝化层9。钝化层9设在势垒层204上并对栅极5、漏极4和源极6实施避让，即钝 化层9具有供栅极5、漏极4和源极6分别贯穿的多个避让孔，使得钝化层9用以对栅极5、漏极4和源极6进行绝缘性隔离，以防止半导体器件因端子间出现错误接通而产生故障。钝化层9制造材料包括二氧化硅、氮化硅、氮化铝和氧化铝等绝缘化合物中的一种。
如图1-3，6-7，10-11，13-14，17-18，20-21，23-24，26，28-31所示，半导体器件还包括导电层7，其设置半导体层2内并位于衬底1和二维电子气之间；以及电耦合结构57，该电耦合结构57从栅极5向半导体层2内延伸并与导电层7连接，用于将导电层7耦合至栅极5。
示例性地，如图3和图24所示，电耦合解结构57可以为杆状结构。
基于此，在一些实施方式中，如图3和图24所示，钝化层9设置在第二半导体层上，且钝化层9位于所述电耦合结构57与源极6之间，以及栅极5与漏极4之间。换而言之，钝化层可以具有供电耦合结构57贯穿的避让孔，使得该电耦合结构57的一端处于半导体层2内并连接导电层7的连接区，而电耦合结构57的另一端处于半导体层2外并连接栅极5面向源极6的一侧。呈现为杆状结构的电耦合结构57不但可以实现导电层7与栅极5的电耦合，而且所使用的结构也非常简单。示例性地，电耦合结构57可以与导电层7垂直，并由金属材料所形成，以适用于通过沉积法和刻蚀法形成。其中，金属可以为钨、钼、钽和镍等耐高温材料中的一种或多种。
需要指出的是，本申请的实施例并不限制将电耦合结构57的一端连接在栅极5面向源极一侧。也就是说，在一些实施例中，电耦合结构57的一端处于半导体层2内并连接导电层7的连接区，而电耦合结构57的另一端处于半导体层2外并连接栅极5面向漏极4的一侧，参考图3A。
在一些实施方式中，导电层7包含远离衬底1的第一表面及与之相对并靠近衬底1的第二表面，以及与第一表面和第二表面相接的侧面。导电层7可选为一个，且导电层7与栅极5在衬底1上的正投影相交。在向半导体器件的栅极5施加电势时，源极6和漏极4可以借助二维电子气连通，导电层7可以调节沟道层203和势垒层204之间的电场分布，降低栅极5附近电场强度峰值，并提高器件的击穿电压，改善器件在高电压、高功率和/或高频率下的工作特性。
在另一些实施方式中，由于电场强度峰值出现在栅极5与漏极4之间并紧邻栅极5，导电层7在衬底1上的正投影比栅极5在衬底1上的正投影更靠近漏极4在衬底1上的正投影，由此该导电层7可以进一步地降低栅极5附近电场强度峰值，并进一步提高器件的击穿电压。
在一些实施方式中，导电层7设置在沟道层203中。
在一些实施方式中，导电层7的第一表面和导电层7的第二表面均位于沟道层203内，如此，能够使得导电层7适用于通过离子注入法和回火激活形成。另一方面，沟道层203包括至少两层结构，以保证导电层7适用于通过外延生长法(由半导体材料制成的导电层7)/沉积法(由金属材料制成的导电层7)和刻蚀法形成在至少两层结构之间。
在另一些实施方式中，导电层7的第一表面位于沟道层203内，导电层7的第二表面与缓冲层202和沟道层203之间的界面相接，如此，在保证导电层7适用于通过外延生长法/沉积法和刻蚀法形成过程中，可以在生长沟道层203之前制备一层导电层，从而简化器件的制作流程。
在另一些实施方式中，导电层7设置在缓冲层内，从而可以利用缓冲层的绝缘特性加强导电层7与二维电子气之间的绝缘性。如此，缓冲层202包括至少两层结构，以保证导电层7适用于通过外延生长法/沉积法和刻蚀法形成在至少两层结构之间。在一些实施方式中，为了简化导电层的制作流程，导电层7的第一表面与缓冲层202远离衬底1的一侧相接，导电层7的第二表面位于缓冲层202内，如此，能够使得导电层7适用于通过离子注入法和回火激活形成。另一方面，缓冲层202包括第一层结构和第二层结构，在第一层结构上生长出导电材料层，对导电材料层进行刻蚀并得到导电层7，然后第一层结构上生长包裹导电层7的第二层结构，当第二层结构的厚度与导电层7相同时，导电层7的第一表面便与缓冲层202远离衬底1的一侧相接。
在一些实施方式中，导电层7可以为易于成型的矩形体，详见图4。导电层7的厚度为10nm-1000nm，可以为100nm。示例性地，导电层7可由金属材料所形成的结构，适用于通过沉积法和刻蚀法形成。其中，该金属可以为钨、钼、钽和镍等耐高温材料中的一种或多种。示例性地，导电层可由半导体材料制成，适用于通过外延生长法和刻蚀法形成。其中，该导电层7可以为n型或p型GaN导电层。
导电层7沿第一方向(即源极6至漏极4的布置方向)的尺寸大于导电层7沿第二方向(即衬底1至半导体层2的布置方向)的尺寸，使得其结构扁平化，由此降低导电层7对半导体层2的占用比例，例如沟道层203的占用比例，有效避免二维电子气浓度因导电层7的体积过大而明显下降，保证半导体器件的开关特性依旧有用且高效。
在一实施例中，如图1-22所示，导电层7由半导体材料制成。此时，半导体器件还包括高阻结构8，该高阻结构8至少部分地设在导电层7与二维电子气之间，以及电耦合结构57与二维电子气之间。
在一些实施方式中，如图2所示，高阻结构8包括第一高阻部801，其设置在导电层7的上方，用于将导电层7与二维电子气进行绝缘性隔离，从而可以拦截二维电子气产生的向导电层7流动的漏电流，由此可以有效降低该半导体器件在高压工作过程中因此而发生失效或损坏的风险。
在一些实施方式中，如图2所示，第一高阻部801设置在导电层7的上方，用于将导电层7与二维电子气进行绝缘性隔离。示例性地，请再参阅图4，需要补充的是，导电层7的第一表面包括用于与电耦合结构57连接的连接区，第一高阻部801设置在导电层7的除连接区之外的第一表面上。第一高阻部801的制造材料为二氧化硅、氮化硅、氮化铝和氧化铝中的一种，厚度可选为5nm-1000nm，以保证其适用于通过外延生长法和刻蚀法形成。
在一些实施方式中，高阻结构8还包括包裹电耦合结构57的第二高阻部802，用于将电耦合结构57与二维电子气进行绝缘性隔离，拦截二维电子气产生的且向电耦合结构57流动的漏电流，由此可以有效降低该半导体器件在高压工作过程中因此而发生失效或损坏的风险。第二高阻部802类似于套状结构，其制造材料为二氧化硅、氮化硅、氮化铝和氧化铝中的一种，厚度可选为5nm-1000nm，以保证其适用于通过外延生长法和刻蚀法形成。
在一些实施方式中，高阻结构8覆盖在导电层7的第一表面以及覆盖在缓冲层202远离所述衬底的一侧，且位于沟道层203靠近衬底1的一侧。如此，高阻结构8便可直接构造为介于沟道层203和缓冲层202之间的层结构。
在另一实施例中，如图23-31所示，导电层7由金属材料制成。此时，为了阻止导电层7在后续器件制造工艺中尤其是与外延生长内所使用的氨气发生反应(即腐蚀作用)，半导体器件还包括高阻结构8和阻隔材料8’。其中，该高阻结构8至少部分地设在导电层7与二维电子气之间，以及电耦合结构57与二维电子气之间。阻隔材料8’与第一高阻部801相连且覆盖在导电层7的侧面。
需要说明的是，在一些实施例中，第一高阻部801至少覆盖导电层7的上表面，阻隔材料8’至少覆盖导电层7的侧面。其中，用于覆盖所述导电层7的上表面与侧面的过渡处可以是第一高阻部801，也可以是阻隔材料8’，总之，阻隔材料8’与第一高阻部801相连以整体覆盖导电层7的上表面和侧面，从而使得导电层7与其侧方和上方的外延层绝缘。
需要说明的是，高阻结构8和阻隔材料8’均由高阻材料制备而成，有利于导电层7与半导体层2之间绝缘。
在一些实施方式中，如图23所示，高阻结构8包括第一高阻部801，其设置在导电层7的上方，用于将导电层7与二维电子气进行绝缘性隔离，从而可以拦截二维电子气产生的向导电层7流动的漏电流，由此可以有效降低该半导体器件在高压工作过程中因此而发生失效或损坏的风险。
在一些实施方式中，如图23所示，第一高阻部801设置在导电层7的上方，用于将导电层7与二维电子气进行绝缘性隔离。示例性地，请再参阅图23，需要补充的是，导电层7的第一表面包括用于与电耦合结构57连接的连接区，第一高阻部801设置在导电层7的除连接区之外的第一表面上。第一高阻部801的制造材料为二氧化硅、氮化硅、氮化铝和氧化铝中的一种，厚度可选为5nm-1000nm，以保证其适用于通过外延生长法和刻蚀法形成。
在一些实施方式中，高阻结构8还包括包裹电耦合结构57的第二阻隔部802，用于将电耦合结构57与二维电子气进行绝缘性隔离，拦截二维电子气产生的且向电耦合结构57流动的漏电流，由此可以有效降低该半导体器件在高压工作过程中因此而发生失效或损坏的风险。第二高阻部802类似于套状结构，其制造材料为二氧化硅、氮化硅、氮化铝和氧化铝中的一种，厚度可选为5nm-1000nm，以保证其适用于通过外延生长法和刻蚀法形成。
在一些实施方式中，高阻结构8覆盖在导电层7的第一表面以及覆盖在缓冲层202远离所述衬底1的一侧，且位于沟道层203靠近衬底1的一侧。如此，高阻结构8便可直接构造为介于沟道层203和缓冲层202之间的层结构。
在一些实施方式中，阻隔材料8’和高阻结构8的第一高阻部801的制造步骤和选用材料可以相同，也可以不同。
对于上述两个实施例，如图13-14和29所示，导电层7为多个，且多个所述导电层7沿第三方向(即垂直于第一方向和第二方向的方向)间隔设置。
在一些实施方式中，请再参阅图13-14和29，每个导电层7的尺寸相等，且多个导电层7沿第一方向的总尺寸小于单个导电层7第二方向的尺寸，其中，第二方向为衬底1至半导体层2的布置方向。基于此，电耦合结构57也对应为多个，其中每个电耦合结构57可以分别为与对应的导电层7垂直的杆状体，每个电耦合结构57一端连接导电层7的连接区，另一端连接栅极5。
在另一些实施例方式中，为了减少电耦合结构的数量，如图6-7，10-11，26和28所示，导电层7包括：间隔设置的第一导电层701和将间隔设置的第一导电层701连接起来的第二导电层702。示例性地，第二导电层702与第一导电层701相互垂直。如此，由于间隔设置的第一导电层701之间由第二导电层702连接起来，故只需要一个与栅极5电耦合的电耦合结构57即可实现导电层7与栅极5之间的电耦合。
在一些实施方式中，如图6-7，8和26所示，第一导电层701沿第一方向间隔设置，其中，第一方向为源极6至漏极4的布置方向。
在一些实施方式中，如图10-11，8和28所示，第一导电层701沿第三方向间隔设置。
在一些实施方式中，如图6-7，10-11，26和28所示，导电层7的连接区703位于多个第一导电层701中的一个上；电耦合结构57为一个，且电耦合结构57的一端连接于具有连接区的第一导电层701，另一端连接于栅极5。
在一些实施方式中，如图6-7，10-11，26和28所示，连接区703位于具有连接区703的第一导电层701背离第二导电层702延伸的延伸区域上。也就是说，该柱状的第一导电层701具有相对的自由端和与所述第二导电层702连接的连接端，所述连接区703从所述连接端沿远离所述第二导电层的方向延伸。
上述实施例中，通过在半导体器件的内部设置能够与栅极5电耦合的导电层7，并且通过高阻结构8将导电层7与二维电子气之间、以及电耦合结构57与二维电子气之间隔离，从而能够通过栅极5所连接的导电层7有效降低半导体器件高电压下栅极5的电场强度，从而提高器件的击穿电压。
如上所述，导电层7的材料为导电型掺杂半导体材料或者金属材料。
当导电层7主要由金属制成时，金属在器件的后续外延生长工艺中容易与外延生长中的氨气发生反应，通过高阻结构8和阻隔材料8’将导电层隔离在高阻结构8的第一高阻部801和阻隔材料8’内，从而可以减少导电层7被外延生长中的氨气腐蚀，从而确保导电层7能够与栅极5电连接而帮助降低栅极5附近的电场。如此，本公开实施例的高阻结构8的第一高阻部801和阻隔材料8’还可以阻止导电层7与其在后续器件制造工艺中尤其是外延生长内所使用的氨气发生反应，保证其可以顺利实现前述功效。
在一些实施方式中，如图2和图23所示，半导体器件还可包括栅场板11，该栅场板11位于栅极5与漏极4之间的钝化层9上。栅场板11能协助导电层7调节沟道层203和势垒层204之间的电场分布，进一步降低栅极5附近电场强度峰值，从而大幅度地提高器件的击穿电压。
上述实施例中，通过将类似于栅场板11的导电层7设置在器件内，并利用该导电层7提高器件的击穿电压，由此半导体器件在不使用栅场板11的情况下就具有较高的击穿电压，而在使用栅场板11的情况下将具有更高的击穿电压。事实上，该导电层7可以连接栅极5或源极6，但是由于源极6的电势不如栅极5的电势强，且栅极5附近电场强度峰值与栅极5的电势同步而不与源极6的电势同步，所以连接栅极5的导电层7要具有更强、更准的栅极附近电场调节能力，有利于保证栅极5附近电场强度峰值更低，以及器件的击穿电压更高。当需要将导电层7与源极6连接时，由于源极6可以直接延伸至导电层7所在处并与其相连，所以连接源极6的导电层在制造方法过程中容易实现，但当需 要将导电层7与栅极5连接时，由于栅极5存在破坏二维电子气的问题而不可以直接延伸至导电层7所在处，所以连接栅极5的导电层7在制造方法过程中难以实现，申请人经过刻苦的研究后发现：可以在器件中增设穿过势垒层204和沟道层203的电耦合结构57并通过其连接导电层7和栅极5，同时在导电层7与二维电子气之间及电耦合结构57与二维电子气之间增设第一阻隔结构8，以利于第一阻隔结构8将导电层7与二维电子气进行绝缘性隔离，再将电耦合结构57与二维电子气进行绝缘性绝缘，由此可以拦截二维电子气产生的且向导电层7和电耦合结构57流动的漏电流，有效提高器件的击穿电压，使得半导体器件可以在更高工作电压下正常运行。
请再结合图1-22，该实施例中，导电层7由半导体材料制成。基于此，本公开实施例还公开了一种半导体器件的制造方法，该方法步骤包括：
提供半导体外延结构，该半导体外延结构包括衬底1和半导体层2；其中，该半导体层2包括第一半导体叠层和设置在第一半导体叠层上的第二半导体层；该第一半导体叠层和第二半导体层之间的界面处形成有二维电子气；
在半导体层2内形成导电层7，并使其位于衬底1与二维电子气之间；
在半导体层2内形成电耦合结构57和高阻结构8，该电耦合结构57自半导体层2向半导体层2内延伸并与导电层7连接，该高阻结构8至少部分地设在导电层7与二维电子气之间，以及电耦合结构57与二维电子气之间；
在第二半导体层上形成包括源极6、漏极4和栅极5的端子层，并使栅极5和电耦合结构57相连。
如此，通过上述方法制备的半导体器件，通过在器件内部设置能够与栅极5电耦合的导电层7，并且通过高阻结构8将导电层7与二维电子气之间、以及电耦合结构57与二维电子气之间隔离，从而能够通过栅极5所连接的导电层7有效降低半导体器件高电压下栅极5的电场强度，从而提高器件的击穿电压。
在一些实施方式中，第一半导体叠层包括：靠近衬底1的缓冲层202，以及设置在缓冲层202上的沟道层203，在半导体层2内形成导电层7包括：
在沟道层203中形成导电层7。
如此，导电层7设置在沟道层203内，可以在保证导电层7位于二维电子气的下方的同时，减少导电层7到栅极5之间的距离。
在一些实施方式中，在沟道层203中形成导电层7，包括：
在缓冲层202上生长出由导电型掺杂半导体材料所形成的导电材料层，对导电材料层进行刻蚀，得到由剩余的导电材料层形成的导电层7。
在一些实施方式中，在沟道层203中形成导电层7，包括：
通过离子注入法将导电型掺杂剂定区、定深地注入沟道层203内，接着进行回火以将其激活为导电层7。
当然，如图17-19所示，对于沟道层203内设置导电层7的方式，不仅仅可以是上述的离子注入法，实际上，也可以采用在沟道层203的第一次外延生长到一定高度后同样采用生长法生长导电材料层后刻蚀形成导电层7，之后再进行二次外延生长出剩余的沟道层203。相比这种方式而言，通过离子注入法将导电型掺杂剂定区、定深地注入沟道层203内，接着进行回火以将其激活为导电层7，实现流程更加简单，成本更低。
在另一些实施方式中，第一半导体叠层包括：靠近衬底1的缓冲层202，以及设置在缓冲层202上的沟道层，在半导体层2内形成导电层，包括：
在缓冲层202中形成导电层7。
在一些实施方式中，在缓冲层202中形成导电层7，包括：
通过离子注入法将导电型掺杂剂定区、定深地注入缓冲层202内，接着进行回火以将其激活为导电层7。与上述形成在沟道层203的实施方式类似，通过离子注入法将导电型掺杂剂定区、定深地注入缓冲层202内，接着进行回火以将其激活为导电层7，实现流程更加简单，成本更低。
请再结合图23-31，该实施例中，导电层7由金属材料制成。基于此，本公开实施例还公开了一种半导体器件的制造方法，该方法步骤包括：
提供半导体外延结构，该半导体外延结构包括衬底1和半导体层2；其中，该半导体层2包括第一半导体叠层和设置在第一半导体叠层上的第二半导体层；该第一半导体叠层和第二半导体层之间的界面处形成有二维电子气；
在半导体层2内形成导电层7，并使其位于衬底1与二维电子气之间；
在第二半导体层上形成源极6、漏极4和栅极5；从栅极5向半导体层2内延伸并与导电层7电连接形成电耦合结构57；
在导电层7远离衬底1的一侧设置高阻结构801，其中，高阻结构8用于将导电层7和电耦合结构57与二维电子气进行绝缘性隔离；
在导电层7的侧面设置阻隔材料8’，其中，该侧面与导电层远离衬底1的一侧相邻。
如此，通过上述方法制备的半导体器件，通过在器件内部设置能够与栅极5电连接的导电层7，并且通过高阻结构8将导电层7与二维电子气之间、以及电耦合结构57与二维电子气之间隔离，从而能够通过栅极5所连接的导电层7有效降低半导体器件高电压下栅极5的电场强度，从而提高器件的击穿电压。同时通过阻隔材料8’可以阻止导电层7与其在后续器件制作工艺中尤其是外延生长内所使用的氨气发生反应，保证导电层7的导电性能。
在一些实施方式中，第一半导体叠层包括：靠近衬底1的缓冲层202，以及设置在缓冲层202上的沟道层203，在半导体层2内形成导电层7包括：
在沟道层203中形成导电层7。
如此，导电层7设置在沟道层203内，可以在保证导电层7位于二维电子气的下方的同时，减少导电层7到栅极5之间的距离。
在一些实施方式中，在沟道层203中形成导电层7，包括：
在缓冲层202上生长出由金属材料所形成的导电材料层，对导电材料层进行刻蚀，得到由剩余的导电材料层形成 的导电层7；
当然，对于沟道层203内设置导电层7的方式，可以采用在沟道层203的第一次外延生长到一定高度后同样采用生长法生长导电材料层后刻蚀形成导电层7，之后再进行二次外延生长出剩余的沟道层203。
在另一些实施方式中，在导电层7远离衬底1的一侧设置高阻结构8，以及在导电层7的侧面设置阻隔材料8’，包括：
在导电层7上生长出由绝缘化合物所形成的高阻材料层，并对高阻材料层进行刻蚀，以得到由剩余高阻材料层形成的且位于导电层7的上方的高阻结构8的第一高阻部801以及位于导电层7的侧面的阻隔材料8’。
关于上述实施例中的方法，其中各个方法执行步骤的具体方式已经在有关该器件的实施例中进行了详细描述，此处将不做详细阐述说明。
为了能够进一步理解本公开实施例提供的半导体器件以及半导体器件的制作方法，以下通过下述具体实施例对上述公开进行进一步的说明。
在本申请的描述中，除实施例一之外，其他实施例均采用尽量避重方式撰写，即重点记载各自与别的实施例不同。在这些实施例中，任何技术特征如没有明确记载，均可参见实施例一的对应描述。
实施例一
本实施例提供了一种半导体器件，其又称高电子迁移率晶体管(High electron mobility transistor)，具有高击穿电压和高电导率等优点，可以作为半导体功率器件或半导体射频器件，在基站通信、物联网、航空航天和雷达系统等领域得到了广泛应用。
如图2和图3所示，半导体器件包括衬底1及设在衬底1上的半导体层2(也称为外延层)。衬底1可由硅(Si)、碳化硅(SiC)或蓝宝石(Sapphire)形成。该半导体层2包括第一半导体叠层和设置在第一半导体叠层上的第二半导体层。其中，第二半导体层包括势垒层204，其主要制造材料可选为合金氮化物，特别是铝镓氮(AlGaN)，厚度为5nm-50nm(“nm”为纳米)。第一半导体叠层包括缓冲层202和设在缓冲层202上的沟道层203，其中沟道层203的主要制造材料可选为III-V族氮化物，特别是氮化氮(GaN)，厚度一般为100nm-1000nm。当沟道层203包含III-V族氮化物而势垒层204包含合金氮化物时，沟道层203和势垒层204为异质结构，由于两者之间存在较大的极化强度差和禁带宽度差，使得两者的界面处形成有二维电子气(Two-dimensional electron gas,2DEG)。其中，沟道层203和势垒层204皆可以为一层或多层结构。一些实施方式中，沟道层203包含沿着远离衬底1方向排布的300nm高阻氮化镓层和200nm高温氮化镓层，而势垒层204包括沿着远离沟道层203方向排布的1nm氮化铝层、20nm铝镓氮层和2nm氮化镓层。
半导体层2还可包括设在衬底1上的成核层201，缓冲层202设在成核层201上。成核层201由碳化铝(AIN)或氮化镓(GaN)形成，厚度为10nm-500nm，用于提高缓冲层202的生长质量，并具有隔离作用。而缓冲层202由铁掺杂氮化镓、碳掺杂氮化镓、氮化镓(GaN)或铝镓氮(AlGaN)形成，厚度为100nm-10um，用于提高III-V族氮化物的生长质量。缓冲层202可以为一层或多层结构。当衬底1选为硅材料时，缓冲层202可以为三层结构，第一层是含铝量为75％、整层厚度为400nm的铝镓氮，第二层是含铝量为50％、整层厚度为900nm的铝镓氮，第三层是含铝量为25％、整层厚度为1500nm的铝镓氮。
半导体器件还包括主要设在势垒层204上的端子层。端子层包括栅极5、漏极4和源极6。源极6和漏极4均可为一层结构或多层结构，可以地包括顺序相连的钛(Ti)层、铝(Al)层、镍(Ni)层和金(Au)层。源极6与势垒层204进行欧姆接触，并与二维电子气进行电耦合。漏极4也与势垒层204进行欧姆接触，并与二维电子气进行电耦合。栅极5主要包括镍(Ni)层和金(Au)层中的一个或两个，并与势垒层204进行肖特基接触。在使用半导体器件时，改变栅极5的电场可以调控二维电子气并控制源极6和漏极4的导通与关断。
半导体器件还包括钝化层9。钝化层9设在势垒层204上并对栅极5、漏极4和源极6实施避让，即钝化层9具有供栅极5、漏极4和源极6分别贯穿的多个避让孔，使得钝化层9用以对栅极5、漏极4和源极6进行绝缘性隔离，以防止半导体器件因端子间出现错误接通而产生故障。钝化层9制造材料包括二氧化硅、氮化硅、氮化铝和氧化铝等绝缘化合物中的一种。
如图3和图4所示，半导体器件还包括设在沟道层203内的导电层7，以及用于将导电层7电耦合至栅极5的电耦合结构57。导电层7由导电型掺杂半导体材料或金属材料制成。导电层7包含远离衬底1的第一表面及与之相对并靠近衬底1的第二表面，以及与第一表面和第二表面相接的侧面。导电层7可选为一个，且导电层7与栅极5在衬底1上的正投影相交。在向半导体器件的栅极5施加电势时，源极6和漏极4可以借助二维电子气连通，导电层7可以调节沟道层203和势垒层204之间的电场分布，降低栅极5附近电场强度峰值，并提高器件的击穿电压，改善器件在高电压、高功率和/或高频率下的工作特性。然而，由于电场强度峰值出现在栅极5与漏极4之间并紧邻栅极5，所以建议这样设置，即导电层7在衬底1上的正投影比栅极5在衬底1上的正投影更靠近漏极4在衬底1上的正投影，由此该导电层7可以进一步地降低栅极5附近电场强度峰值，并进一步提高器件的击穿电压。
导电层7的第一表面位于沟道层203内，导电层7的第二表面与缓冲层202和沟道层203之间的界面相接，以保证导电层7适用于通过外延生长法和刻蚀法形成。导电层7可以为易于成型的矩形体，详见图4。导电层7的厚度为10nm-1000nm，可以为100nm，可选为由金属材料所形成的结构，适用于通过外延生长法和刻蚀法形成。其中，该金属可以为钨、钼、钽和镍等耐高温材料中的一种或多种。导电层7沿第一方向(即源极6至漏极4的布置方向)的尺寸大于导电层7沿第二方向(即衬底1至半导体层2的布置方向)的尺寸，使得其结构扁平化，由此降低导电层7对沟道层203的占用比例，有效避免二维电子气浓度因导电层7的体积过大而明显下降，保证半导体器件的开关特性依旧有用且高效。
电耦合结构57为杆状结构，钝化层9还具有供电耦合结构57分别贯穿的避让孔，使得该电耦合结构57的一端处 于半导体层2内并连接导电层7的连接区，而电耦合结构57的另一端处于半导体层2外并连接栅极5面向源极6的一侧。呈现为杆状结构的电耦合结构57不但可以实现导电层7与栅极5的电耦合，而且所使用的结构也非常简单。一些实施方式中，电耦合结构57最好与导电层7垂直，并由金属材料所形成，以适用于通过外延生长法和刻蚀法形成。其中，金属可以为钨、钼、钽和镍等耐高温材料中的一种或多种。
高阻结构8包括第一高阻部801，其设置在导电层7的上方，用于将导电层7与二维电子气进行绝缘性隔离，拦截二维电子气产生的向导电层7流动的漏电流，由此可以有效降低该半导体器件在高压工作过程中因此而发生失效或损坏的风险。此外，高阻结构8还可以阻止导电层7在后续器件制造工艺中尤其是与外延生长内所使用的氨气发生反应，保证导电层7的有效性。一些实施方式中，第一高阻部801设置在导电层7的除连接区之外的第一表面上。第一高阻部801的制造材料为二氧化硅、氮化硅、氮化铝和氧化铝中的一种，厚度可选为5nm-1000nm，以保证其适用于通过外延生长法和刻蚀法形成。
高阻结构8还包括包裹电耦合结构57的第二高阻部802，用于将电耦合结构57与二维电子气进行绝缘性隔离，拦截二维电子气产生的且向电耦合结构57流动的漏电流，由此可以有效降低该半导体器件在高压工作过程中因此而发生失效或损坏的风险。第二高阻部802类似于套状结构，其制造材料为二氧化硅、氮化硅、氮化铝和氧化铝中的一种，厚度可选为5nm-1000nm，以保证其适用于通过外延生长法和刻蚀法形成。
半导体器件还可包括设在钝化层9上且连接栅极5的栅场板11。栅场板11能协助导电层7调节沟道层203和势垒层204之间的电场分布，进一步降低栅极5附近电场强度峰值，从而大幅度地提高器件的击穿电压。
接下来介绍半导体器件的制造方法，该制造方法的步骤包括：提供衬底1，详见图5a；在衬底1生长出成核层201；在成核层201生长出缓冲层202，详见图5b；在缓冲层202上生长出由金属材料所形成的导电材料层；对导电材料层进行刻蚀，得到由剩余导电材料层形成的导电层7；在缓冲层202及导电层7上出生长出由绝缘化合物所形成的高阻材料层；对高阻材料层进行刻蚀，得到由剩余高阻材料层形成且位于导电层7的上方的高阻结构8的第一高阻部801；在缓冲层202上生长能够覆盖高阻结构8的第一高阻部801的沟道层203；在沟道层203上生长势垒层204，详见图5d。
接着，通过刻蚀法对势垒层204、沟道层203和高阻结构8的第一高阻部801进行开孔，得到漏出导电层7的第一槽孔57a，详见图5e；在势垒层204上及第一槽孔57a中生长绝缘材料9a，详见图5f；通过刻蚀法对处于势垒层204上的绝缘材料9a进行开孔，得到源极孔区、栅极孔区和漏极孔区；通过生长、刻蚀和回火方式在源极孔区、栅极孔区和漏极孔区内分别形成源极6、栅极5和漏极4，同时在绝缘材料9a上形成连接栅极5的栅场板11，详见图5g；通过刻蚀法对处于第一槽孔57a内外的绝缘材料9a进行开孔，得到能够漏出导电层7的且比第一槽孔57a更细的第二槽孔57b，详见图5h；在第二槽孔57b内生长导电材料，然后对导电材料实施刻蚀，得到由导电材料所形成的且将导电层7连接栅极5的进行电耦合结构57，以及由剩余绝缘材料9a所形成且处于势垒层204上的钝化层9和用于包覆电耦合结构57的高阻结构8的第二高阻部802，详见图5i。
实施例二
如图6-8所示，与实施例一不同的是，导电层7包括沿着第一方向(即源极6至漏极4的布置方向)间隔设置的第一导电层701和将间隔设置的第一导电层701连接起来的第二导电层702，在多个第一导电层701中的一个上设有与电耦合结构57相接触的连接区(第三导电层)703。一些实施方式中，连接区703位于具有连接区703的第一导电层701背离第二导电层702延伸的延伸区域上。一些实施方式中，第二导电层702与第一导电层701相互垂直，以其降低制造难度。至少一个第一导电层701在衬底1上的正投影与栅极5在衬底1上的正投影相交。在向半导体器件的栅极5施加电势时，源极6和漏极4可以借助二维电子气连通，导电层7主要借助多个第一导电层701均匀地调节沟道层203和势垒层204之间的电场分布,相比于实施例一的半导体器件，具有第一导电层701和第二导电层702的半导体器件能更有效地降低栅极5附近电场强度峰值，并进一步提高器件的击穿电压，改善器件在高电压、高功率和/或高频率下的工作特性。然而，由于电场强度峰值出现栅极5与漏极4之间并紧邻栅极5，所以建议这样设置,即多个第一导电层701在衬底1上的正投影中最靠近漏极4的第一导电层701的正投影比栅极5在衬底1上的正投影更靠近漏极4在衬底1上的正投影，由此该最靠近漏极4的第一导电层701可以更好地降低栅极5的附近电场强度峰值，更有效地提高器件的击穿电压。
导电层7的第一表面位于沟道层203内，导电层7的第二表面与缓冲层202远离衬底1的表面相接，以保证导电层7适用于通过外延生长法和刻蚀法形成。各个第一导电层701可以为易于成型的矩形体。导电层7的厚度为10nm-1000nm，可以为100nm，可选为由金属材料所形成的结构，适用于通过外延生长法和刻蚀法形成。其中，该金属可以为钨、钼、钽和镍等耐高温材料中的一种或多种。各个第一导电层701沿第一方向的尺寸大于第一导电层7沿第二方向(即衬底1至半导体层2的布置方向)的尺寸，由此降低导电层7对沟道层203的占用比例，有效避免二维电子气浓度因此而明显下降，保证半导体器件的开关特性依旧有用且高效。
电耦合结构57为杆状结构，钝化层9还具有供电耦合结构57贯穿的避让孔，使得该电耦合结构57的一端处于半导体层2并内连接第一导电层701的连接区，而电耦合结构57的另一端处于半导体层2外并连接栅极5面向源极6的一侧。呈现为杆状结构的电耦合结构57不但可以实现导电层7与栅极5的电耦合，而且所使用的结构也非常简单。一些实施方式中，电耦合结构57最好与导电层7垂直，并由金属材料所形成，以适用于通过外延生长法和刻蚀法形成。其中，金属可以为钨、钼、钽和镍等耐高温材料中的一种或多种。
一些实施方式中，第一高阻部801设置在导电层7的除连接区之外的第一表面上。第一高阻部801的数量可选为一个或多个，当第一高阻部801的数量选为一个时，第一高阻部801覆盖所有的第一导电层701的第一表面(即上表面)并仅留出连接电耦合结构57用的连接区。当第一高阻部801的数量选为多个时，一个第一高阻部801覆盖具有连接区的第一导电层701的第一表面并仅留出连接电耦合结构57用的连接区，剩下的每个第一高阻部801均可独立覆盖一个第一导电层701的第一表面。第一高阻部801的制造材料为二氧化硅、氮化硅、氮化铝和氧化铝中的一种，厚度可选为5nm-1000nm，适用于通过外延生长法和刻蚀法形成。高阻结构8还包括包裹电耦合结构57的第二高阻部802， 用于将电耦合结构57与二维电子气进行绝缘性隔离，拦截二维电子气产生的且向电耦合结构57流动的漏电流，由此可以有效降低该半导体器件在高压工作过程中因此而发生失效或损坏的风险。第二高阻部802的制造材料为二氧化硅、氮化硅、氮化铝和氧化铝中的一种，厚度可选为5nm-1000nm，适用于通过外延生长法和刻蚀法形成。
接下来介绍半导体器件的制造方法，该制造方法的步骤包括：提供衬底1；在衬底1生长出成核层201；在成核层201生长出缓冲层202；在缓冲层202上生长出由金属材料所形成的导电材料层；对导电材料层进行刻蚀，得到由剩余导电材料层形成的导电层7；在缓冲层202及导电层7上出生长出由绝缘化合物所形成的高阻材料层；对高阻材料层进行刻蚀，得到由剩余高阻材料层形成且位于导电层7的上方的高阻结构8的第一高阻部801；在缓冲层202上生长能够覆盖高阻结构8的第一高阻部801的沟道层203；在沟道层203上生长势垒层204。
接着，通过刻蚀法对势垒层204、沟道层203和高阻结构8的第一高阻部801进行开孔，得到漏出导电层7的第一槽孔57a；在势垒层204上及第一槽孔57a中生长绝缘材料；通过刻蚀法对处于势垒层204上的绝缘材料进行开孔，得到源极孔区、栅极孔区和漏极孔区；通过生长、刻蚀和回火方式在源极孔区、栅极孔区和漏极孔区内分别形成源极6、栅极5和漏极4，同时在绝缘材料上形成连接栅极5的栅场板11；通过刻蚀法对处于第一槽孔57a内外的绝缘材料进行开孔，得到能够漏出导电层7的且比第一槽孔57a更细的第二槽孔57b；在第二槽孔57b内生长导电材料，然后对导电材料实施刻蚀，得到由导电材料所形成的且将导电层7连接栅极5的进行电耦合结构57，以及由剩余绝缘材料所形成且处于势垒层204上的钝化层9和用于包覆电耦合结构57的高阻结构8的第二高阻部802。对应步骤可参见图9a-9i，可以理解的是，图9a-9i的步骤与图5a-5i逻辑对应。本领域技术人员可以在获知图5a-5i的前提下，理解图9a-9i的操作步骤。
实施例三
如图8，10-11所示，与实施例二不同的是，第一导电层701沿着第三方向间隔设置。其中，第三方向与所述第一方向和第二方向垂直。也就是说，第一第二第三方向构成了直角坐标系。
本实施例的半导体器件的制造方法可参见图12a-12i。可以理解的是，图12a-12i的步骤与图5a-5i逻辑对应。本领域技术人员可以在获知图5a-5i的前提下，理解图12a-12i的操作步骤。
实施例四
如图13-14和16所示，与实施例二不同的是，半导体器件还包括设在沟道层203内的尺寸相等的多个导电层7，以及用于将每个导电层7均电耦合至栅极5的多个电耦合结构57。多个导电层7沿第三方向间隔设置，且每个导电层7上均设有用于接收电耦合结构57的连接区，详见图16。可以理解的，每个导电层7和对应电耦合结构57的连接关系可以为：电耦合结构57连接在导电层7的上表面或侧面(即端部)。每个导电层7沿第三方向的总尺寸大于单个导电层7沿第二方向的尺寸，每个导电层7包含远离衬底1的第一表面及与之相对并靠近衬底1的第二表面。在多个导电层7中，至少有一个导电层7与栅极5在衬底1上的正投影相交。在向半导体器件的栅极5施加电势时，源极6和漏极4可以借助二维电子气连通，导电层7可以调节沟道层203和势垒层204之间的电场分布，相比于仅具有一个导电层的半导体器件，具有多个导电层7的半导体器件能更有效地降低栅极5附近电场强度峰值，并进一步提高器件的击穿电压，改善器件在高电压、高功率和/或高频率下的工作特性。然而，由于电场强度峰值出现在栅极5与漏极4之间并紧邻栅极5，所以建议这样设置,即多个导电层7在衬底1上的正投影中最靠近漏极4的导电层7的正投影比栅极5在衬底1上的正投影更靠近漏极4在衬底1上的正投影，由此该最靠近漏极4的第一导电层7可以更好地降低栅极5的附近电场强度峰值，更有效地提高器件的击穿电压。
导电层7的第一表面位于沟道层203内，导电层7的第二表面与缓冲层202和沟道层203之间的界面相接，以保证导电层7适用于通过外延生长法和刻蚀法形成。导电层7的厚度为10nm-1000nm，可以为100nm，可选为导电型掺杂半导体结，适用于通过外延生长法和刻蚀法形成。各个导电型掺杂半导体结可选为N型掺杂半导体结构和P型掺杂半导体结构中的一种，尤其是由硅掺杂氮化镓所形成且掺杂浓度为1E18/cm3的结构。该导电层7因采用了掺杂半导体材料而具有较高的结构稳定性，不会在器件制造工艺的后续工序中与气体(例如氨气)发生反应，保证其可以顺利实现调节电场的功效。导电层7沿第一方向的尺寸大于导电层7沿第二方向(即衬底1至半导体层2的布置方向)的尺寸，由此降低导电层7对沟道层203的占用比例，有效避免二维电子气浓度因此而明显下降，保证半导体器件的开关特性依旧有用且高效。
电耦合结构57为杆状结构，钝化层9还具有供电耦合结构57分别贯穿的避让孔，使得该电耦合结构57的一端处于半导体层2内连接导电层7的连接区，而电耦合结构57的另一端处于半导体层2外并连接栅极5面向源极6的一侧。电耦合结构57的个数与导电层7相同，使得每个导电层7均可通过一个与之垂直的电耦合结构57连接栅极5。呈现为杆状结构的电耦合结构57不但可以实现导电层7与栅极5的电耦合，而且所使用的结构也非常简单。一些实施方式中，电耦合结构57可以与导电层7垂直，并由金属材料所形成，以适用于通过外延生长法和刻蚀法形成。其中，金属可以为钨、钼、钽和镍等耐高温材料中的一种或多种。
高阻结构8包括第一高阻部801，其设置在导电层7的上方，用于将导电层7与二维电子气进行绝缘性隔离，拦截二维电子气产生的且向导电层7流动的漏电流，由此可以有效降低该半导体器件在高压工作过程中因此而发生失效或损坏的风险。此外，高阻结构8还可以阻止导电层7在后续器件制造工艺中尤其是与外延生长内所使用的氨气发生反应，保证导电层7的有效性。第一高阻部801的数量可选为一个或多个，当第一高阻部801的数量选为一个时，第一高阻部801覆盖所有的导电层7的第一表面并在各个导电层7上留出连接对应电耦合结构57用的连接区；当第一高阻部801的数量选为多个时，每个第一高阻部801均可独立覆盖一个导电层7并在该导电层7上留出连接电耦合结构57用的连接区。第一高阻部801的制造材料为二氧化硅、氮化硅、氮化铝和氧化铝中的一种，厚度可选为5nm-1000nm，适用于通过外延生长法和刻蚀法形成。
高阻结构8还包括包裹电耦合结构57的第二高阻部802，用于将电耦合结构57与二维电子气进行绝缘性隔离，拦截二维电子气产生的且向电耦合结构57流动的漏电流，由此可以有效降低该半导体器件在高压工作过程中因此而发生 失效或损坏的风险。第二高阻部802的数量可选为一个或多个，当第二高阻部802的数量选为一个时，第二高阻部802包裹所有的电耦合结构57；当第二高阻部802的数量选为多个时，每个第一高阻部801可独立包裹一个电耦合结构57，并保证每个电耦合结构57均被一个第二高阻部802所包裹。第二高阻部802的制造材料为二氧化硅、氮化硅、氮化铝和氧化铝中的一种，厚度可选为5nm-1000nm，适用于通过外延生长法和刻蚀法形成。
接下来介绍半导体器件的制造方法，该制造方法的步骤包括：提供衬底1；在衬底1生长出成核层201；在成核层201生长出缓冲层202；在缓冲层202上生长出由导电型掺杂半导体材料所形成的导电材料层；在导电材料层生长出由绝缘化合物所形成的高阻材料层；对导电材料层和高阻材料层进行刻蚀，得到由剩余导电材料层形成的导电层7和由剩余高阻材料层形成且位于导电层7的上方的高阻结构8的第一高阻部801；在缓冲层202上生长能够覆盖导电层7和第一高阻部801的沟道层203；在沟道层203上生长势垒层204；通过刻蚀法对势垒层204、沟道层203和高阻结构8的第一高阻部801进行开孔，得到漏出导电层7的第一槽孔57a。
接着，在势垒层204上及第一槽孔57a中生长绝缘材料；通过刻蚀法对处于势垒层204上的绝缘材料进行开孔，得到源极孔区、栅极孔区和漏极孔区；通过生长、刻蚀和回火方式在源极孔区、栅极孔区和漏极孔区内分别形成源极6、栅极5和漏极4，同时在绝缘材料上形成连接栅极5的栅场板11；通过刻蚀法对处于第一槽孔57a内外的绝缘材料进行开孔，得到能够漏出导电层7的且比第一槽孔57a更细的第二槽孔57b；
此后，在第二槽孔57b内生长导电材料，然后对导电材料实施刻蚀，得到由导电材料所形成的且将导电层7连接栅极5的进行电耦合结构57，以及由剩余绝缘材料所形成且处于势垒层204上的钝化层9，由剩余绝缘材料所形成且用于包覆电耦合结构57的高阻结构8的第二高阻部802。
对应步骤可参见图15a-15i，可以理解的是，图15a-15i的步骤与图5a-5i逻辑对应。本领域技术人员可以在获知图5a-5i的前提下，理解图15a-15i的操作步骤。
实施例五
如图17-18所示，与实施例一不同的是，导电层7的第一表面位于沟道层203内，导电层7的第二表面也位于沟道层203内，以保证导电层7适用于通过离子注入法和回火激活形成。导电层7可以为易于成型的矩形体。导电层7的厚度为10nm-1000nm，可以为100nm，可选为导电型掺杂半导体结构，适用于通过离子注入法和回火激活形成。其中，电型掺杂半导体结可选为N型掺杂半导体结构和P型掺杂半导体结构中的一种，尤其是由硅掺杂氮化镓所形成且掺杂浓度为5E17/cm3的结构。导电层7沿第一方向(即源极6至漏极4的布置方向)的尺寸大于导电层7沿第二方向(即衬底1至半导体层2的布置方向)的尺寸，由此降低导电层7对沟道层203的占用比例，有效避免二维电子气浓度因此而明显下降，保证半导体器件的开关特性依旧有用且高效。
电耦合结构57为杆状结构，钝化层9还具有供电耦合结构57贯穿的避让孔，使得该电耦合结构57的一端处于半导体层2内并连接导电层7的连接区，而电耦合结构57的另一端处于半导体层2外并连接栅极5面向源极6的一侧。呈现为杆状结构的电耦合结构57不但可以实现导电层7与栅极5的电耦合，而且所使用的结构也非常简单，可参考图4。一些实施方式中，电耦合结构57最好与导电层7垂直，并由金属材料所形成，以适用于通过外延生长法和刻蚀法形成。其中，金属可以为钨、钼、钽和镍等耐高温材料中的一种或多种。
高阻结构8包括第一高阻部801，其设置在导电层7的上方，用于将导电层7与二维电子气进行绝缘性隔离。第一高阻部801的制造材料可选为硼掺杂氮化镓等高阻型掺杂半导体结构，厚度可选为5nm-1000nm，适用于通过离子注入法和回火激活形成。一些实施方式中，第一高阻部801设置在导电层7的除连接区之外的第一表面上。一些实施方式中，第一高阻部801是由硼掺杂氮化镓所形成且掺杂浓度为5E17/cm3的结构。由于硼离子等高阻型掺杂剂可以打乱半导体结构内晶体晶格进而实现高阻，并利用该高阻特性阻拦二维电子气产生的且向导电层7流动的漏电流，由此可以有效降低该半导体器件在高压工作过程中因此而发生失效或损坏的风险。
高阻结构8还包括包裹电耦合结构57的第二高阻部802，用于将电耦合结构57与二维电子气进行绝缘性隔离，拦截二维电子气产生的且向电耦合结构57流动的漏电流，由此可以有效降低该半导体器件在高压工作过程中因此而发生失效或损坏的风险。第二高阻部802的制造材料为二氧化硅、氮化硅、氮化铝和氧化铝中的一种，厚度可选为5nm-1000nm，适用于通过外延生长法和刻蚀法形成。
接下来介绍半导体器件的制造方法，该制造方法的步骤包括：提供衬底1；在衬底1生长出成核层201；在成核层201生长出缓冲层202；在缓冲层202上生长出沟道层203；在沟道层203上生长势垒层204；通过离子注入法将导电型掺杂剂定区、定深地注入沟道层203内，得到导电型掺杂区；对导电型掺杂区进行回火激活以将其形成为导电层7；通过离子注入法将高阻掺杂剂定区、定深地注入沟道层203内，以在导电型掺杂区的上方得到高阻型掺杂区；对高阻型掺杂区进行回火激活以将其形成为高阻结构8的第一高阻部801；通过刻蚀法对势垒层204、沟道层203和高阻结构8的第一高阻部801进行开孔，得到漏出导电层7的第一槽孔57a。
接着，在势垒层204上及第一槽孔57a中生长绝缘材料；通过刻蚀法对处于势垒层204的绝缘材料进行开孔，得到源极孔区、栅极孔区和漏极孔区；通过生长、刻蚀和回火方式在源极孔区、栅极孔区和漏极孔区内分别形成源极6、栅极5和漏极4，同时在绝缘材料上形成连接栅极5的栅场板11；通过刻蚀法对处于第一槽孔57a内外的绝缘材料进行开孔，得到能够漏出导电层7的且比第一槽孔57a更细的第二槽孔57b；在第二槽孔57b内上生长出导电材料并对导电材料实施刻蚀，得到由导电材料所形成的且将导电层7连接栅极5的进行电耦合结构57，以及由剩余绝缘材料所形成且处于势垒层204上的钝化层9及用于包覆电耦合结构57的高阻结构8的第二高阻部802。对应步骤可参见图19a-19i，可以理解的是，图19a-19i的步骤与图5a-5i逻辑对应。本领域技术人员可以在获知图5a-5i的前提下，理解图19a-19i的操作步骤。
实施例六
如图20-21所示，与实施例一不同的是，半导体器件还包括设在缓冲层202内的导电层7，以及用于将导电层7电耦合至栅极5的电耦合结构57。导电层7包含远离衬底1的第一表面及与之相对并靠近衬底1的第二表面。导电层7 可选为一个，且导电层7与栅极5在衬底1上的正投影相交。在向半导体器件的栅极5施加电势时，源极6和漏极4可以借助二维电子气连通，导电层7可以调节沟道层203和势垒层204之间的电场分布，降低栅极5附近电场强度峰值，并提高器件的击穿电压，改善器件在高电压、高功率和/或高频率下的工作特性。然而，由于电场强度峰值出现在栅极5与漏极4之间并紧邻栅极5，所以建议这样设置,即导电层7在衬底1上的正投影比栅极5在衬底1上的正投影更靠近漏极4在衬底1上的正投影，由此该导电层7可以进一步地降低栅极5附近电场强度峰值，并进一步提高器件的击穿电压。
导电层7的第一表面与缓冲层202远离衬底的一侧相接，导电层7的第二表面位于缓冲层202内，以保证导电层7适用于通过离子注入法和回火激活形成。导电层7可以为易于成型的矩形体。导电层7的厚度为10nm-1000nm，可以为100nm，可选为导电型掺杂半导体结构，适用于通过离子注入法和回火激活形成。其中，电型掺杂半导体结可选为N型掺杂半导体结构和P型掺杂半导体结构中的一种，尤其是由硅掺杂氮化镓所形成且掺杂浓度为5E17/cm3的结构。导电层7沿第一方向(即源极6至漏极4的布置方向)的尺寸大于导电层7沿第二方向(即衬底1至半导体层2的布置方向)的尺寸，由此降低导电层7对沟道层203的占用比例，有效避免二维电子气浓度因此而明显下降，保证半导体器件的开关特性依旧有用且高效。
电耦合结构57为杆状结构，钝化层9还具有供电耦合结构57贯穿的避让孔，使得该电耦合结构57的一端处于半导体层2内并连接导电层7的连接区，而电耦合结构57的另一端处于半导体层2外并连接栅极5面向源极6的一侧。呈现为杆状结构的电耦合结构57不但可以实现导电层7与栅极5的电耦合，而且所使用的结构也非常简单。一些实施方式中，电耦合结构57可以与导电层7垂直，并由金属材料所形成，以适用于通过外延生长法和刻蚀法形成。其中，金属可以为钨、钼、钽和镍等耐高温材料中的一种或多种。
高阻结构8包括由高阻材料所形成的第一高阻部801(高阻层)，其能覆盖在导电层7的第一表面并留出导电层7的连接区。第一高阻部801用于将导电层7与二维电子气进行绝缘性隔离拦截二维电子气产生的且向导电层7流动的漏电流，由此可以有效降低该半导体器件在高压工作过程中因此而发生失效或损坏的风险。第一高阻部801选为了整层结构，所以第一高阻部801在衬底1的正投影面积要远远大于导电层7在衬底1的正投影面积，能够有效将导电层7与二维电子气进行绝缘性隔离。也是因为第一高阻部801选为了整层结构，所以第一高阻部801包括与缓冲层202远离衬底1的一侧相接的下表面，以及与沟道层203靠近衬底1的一侧相接的上表面。第一高阻部801的制造材料包括二氧化硅、氮化硅、氮化铝和氧化铝等绝缘化合物中的一种，厚度可选为5nm-1000nm，适用于通过外延生长法形成，简化制备流程。一些实施方式中，第一高阻部801是由硼掺杂氮化镓所形成且掺杂浓度为5E17/cm3的结构。需要注意的是，在其他实施例中，高阻结构8的第一高阻部801也可以是非整层结构，比如是像实施例三似得仅覆盖导电层7的非整层结构。
高阻结构8还包括包裹电耦合结构57的第二高阻部802(可参考图3)，其用于将电耦合结构57与二维电子气进行绝缘性隔离，拦截二维电子气产生的且向电耦合结构57流动的漏电流，由此可以有效降低该半导体器件在高压工作过程中因此而发生失效或损坏的风险。第二高阻部802的制造材料为二氧化硅、氮化硅、氮化铝和氧化铝中的一种，厚度可选为5nm-1000nm，适用于通过外延生长法和刻蚀法形成。
接下来介绍半导体器件的制造方法，该制造方法的步骤包括：提供衬底1；在衬底1生长出成核层201；在成核层201生长出缓冲层202；通过离子注入法将导电型掺杂剂定区、定深地注入缓冲层202内，得到导电型掺杂区；对导电型掺杂区进行回火激活以将其形成为导电层7；在缓冲层202上生长出高阻层；在第一高阻部801(高阻层)上生长出沟道层203；在沟道层203上生长势垒层204，通过刻蚀法对势垒层204、沟道层203和高阻层进行开孔，得到漏出导电层7的第一槽孔57a；在势垒层204上及第一槽孔57a中生长绝缘材料。
接着，通过刻蚀法对处于势垒层204的绝缘材料进行开孔，得到源极孔区、栅极孔区和漏极孔区；通过生长、刻蚀和回火方式在源极孔区、栅极孔区和漏极孔区内分别形成源极6、栅极5和漏极4，同时在绝缘材料上形成连接栅极5的栅场板11；通过刻蚀法对处于第一槽孔57a内外的绝缘材料进行开孔，得到能够漏出导电层7的且比第一槽孔57a更细的第二槽孔57b；在第二槽孔57b内上生长出导电材料并对导电材料实施刻蚀，得到由导电材料所形成的且将导电层7连接栅极5的进行电耦合结构57，以及由绝缘材料所形成且处于势垒层204上的钝化层9及用于包覆电耦合结构57的高阻结构8的第二高阻部802。对应步骤可参见图22a-22i，可以理解的是，图22a-22i的步骤与图5a-5i逻辑对应。本领域技术人员可以在获知图5a-5i的前提下，理解图22a-22i的操作步骤。
实施例七
如图1，23-24所示，半导体器件包括衬底1及设在衬底1上的半导体层2。衬底1可由硅(Si)、碳化硅(SiC)或蓝宝石(Sapphire)形成。该半导体层2包括第一半导体叠层和设置在第一半导体叠层上的第二半导体层。其中，第二半导体层包括势垒层204，其主要制造材料可选为合金氮化物，特别是铝镓氮(AlGaN)，厚度为5nm-50nm(“nm”为纳米)。第一半导体叠层包括缓冲层202和设在缓冲层202上的沟道层203，其中沟道层203的主要制造材料可选为III-V族氮化物，特别是氮化氮(GaN)，厚度一般为100nm-1000nm。当沟道层203包含III-V族氮化物而势垒层204包含合金氮化物时，沟道层203和势垒层204为异质结构，由于两者之间存在较大的极化强度差和禁带宽度差，使得两者的界面处形成有二维电子气(Two-dimensional electron gas,2DEG)。其中，沟道层203和势垒层204皆可以为一层或多层结构。一些实施方式中，沟道层203包含沿着远离衬底1方向排布的300nm高阻氮化镓层和200nm高温氮化镓层，而势垒层204包括沿着远离沟道层203方向排布的1nm氮化铝层、20nm铝镓氮层和2nm氮化镓层。
半导体层2还可包括设在衬底1上的成核层201，缓冲层202设在成核层201上。成核层201由碳化铝(AIN)或氮化镓(GaN)形成，厚度为10nm-500nm，用于提高缓冲层202的生长质量，并具有隔离作用。而缓冲层202由铁掺杂氮化镓、碳掺杂氮化镓、氮化镓(GaN)或铝镓氮(AlGaN)形成，厚度为100nm-10um，用于提高III-V族氮化物的生长质量。缓冲层202可以为一层或多层结构。当衬底1选为硅材料时，缓冲层202可以为三层结构，第一层是含铝量为75％、整层厚度为400nm的铝镓氮，第二层是含铝量为50％、整层厚度为900nm的铝镓氮，第三层是含铝量为 25％、整层厚度为1500nm的铝镓氮。
半导体器件还包括主要设在势垒层204上栅极5、漏极4和源极6。源极6和漏极4均可为一层结构或多层结构，可以包括顺序相连的钛(Ti)层、铝(Al)层、镍(Ni)层和金(Au)层。源极6与势垒层204进行欧姆接触，并与二维电子气进行电耦合。漏极4也与势垒层204进行欧姆接触，并与二维电子气进行电耦合。栅极5主要包括镍(Ni)层和金(Au)层中的一个或两个，并与势垒层204进行肖特基接触。在使用半导体器件时，改变栅极5的电场可以调控二维电子气并控制源极6和漏极4的导通与关断。
半导体器件还包括钝化层9。钝化层9设在势垒层204上并对栅极5、漏极4和源极6实施避让，即钝化层9具有供栅极5、漏极4和源极6分别贯穿的多个避让孔，使得钝化层9用以对栅极5、漏极4和源极6进行绝缘性隔离，以防止半导体器件因电极间出现错误接通而产生故障。钝化层9制造材料包括二氧化硅、氮化硅、氮化铝和氧化铝等绝缘化合物中的一种。
如图23和图24所示，半导体器件还包括设在沟道层203内的导电层7，以及用于将导电层7电耦合至栅极5的电耦合结构57。导电层7包含远离衬底1的第一表面及与之相对并靠近衬底1的第二表面，以及与第一表面和第二表面相接的侧面。导电层7可选为一个，且导电层7与栅极5在衬底1上的正投影相交。在向半导体器件的栅极5施加电势时，源极6和漏极4可以借助二维电子气连通，导电层7可以调节沟道层203和势垒层204之间的电场分布，降低栅极5附近电场强度峰值，并提高器件的击穿电压，改善器件在高电压、高功率和/或高频率下的工作特性。然而，由于电场强度峰值出现在栅极5与漏极4之间并紧邻栅极5，所以建议这样设置,即导电层7在衬底1上的正投影比栅极5在衬底1上的正投影更靠近漏极4在衬底1上的正投影，由此该导电层7可以进一步地降低栅极5附近电场强度峰值，并进一步提高器件的击穿电压。
导电层7的第一表面位于沟道层203内，导电层7的第二表面与缓冲层202和沟道层203之间的界面相接，以保证导电层7适用于通过外延生长法和刻蚀法形成。导电层7可以为易于成型的矩形体，详见图4。导电层7的厚度为10nm-1000nm，可以为100nm，可选为由金属材料所形成的结构，适用于通过外延生长法和刻蚀法形成。其中，该导电层7可以为钨、钼、钛和镍等耐高温材料中的一种或多种。导电层7沿第一方向(即源极5至漏极4的布置方向)的尺寸大于导电层7沿第二方向(即衬底1至半导体层2的布置方向)的尺寸，使得其结构扁平化，由此降低导电层7对沟通层3的占用比例，有效避免二维电子气浓度因导电层7的体积过大而明显下降，保证半导体器件的开关特性依旧有用且高效。
电耦合结构57为杆状结构，钝化层9还具有供电耦合结构57分别贯穿的避让孔，使得该电耦合结构57的一端处于半导体层2内并连接导电层7的连接区，而电耦合结构57的另一端处于半导体层2外并连接栅极5面向源极6的一侧。呈现为杆状结构的电耦合结构57不但可以实现导电层7与栅极5的电耦合，而且所使用的结构也非常简单。一些实施方式中，电耦合结构57最好与导电层7垂直，并由金属材料所形成，以适用于通过外延生长法和刻蚀法形成。其中，电耦合结构57可以为钨、钼、钽和镍等耐高温材料中的一种或多种。
高阻结构8包括第一高阻部801，其设置在导电层7的上方，用于将导电层7与二维电子气进行绝缘性隔离，拦截二维电子气产生的向导电层7流动的漏电流，由此可以有效降低该半导体器件在高压工作过程中因此而发生失效或损坏的风险。此外，高阻结构8还可以阻止导电层7在后续器件制造工艺中尤其是与外延生长内所使用的氨气发生反应，保证其可以顺利实现前述功效。一些实施方式中，第一高阻部801设置在导电层7的除连接区之外的第一表面上。第一高阻部801的制造材料为二氧化硅、氮化硅、氮化铝和氧化铝中的一种，厚度可选为5nm-1000nm，以保证其适用于通过外延生长法和刻蚀法形成。
高阻结构8还包括包裹电耦合结构57的第二高阻部802，用于将电耦合结构57与二维电子气进行绝缘性隔离，拦截二维电子气产生的且向电耦合结构57流动的漏电流，由此可以有效降低该半导体器件在高压工作过程中因此而发生失效或损坏的风险。第二阻隔部802类似于套状结构，其制造材料为二氧化硅、氮化硅、氮化铝和氧化铝中的一种，厚度可选为5nm-1000nm，以保证其适用于通过外延生长法和刻蚀法形成。
为了进一步阻止导电层7在后续器件制造工艺中发生反应，半导体器件还包括阻隔材料8’，其与高阻结构8相连且覆盖在导电层7的侧面。其中，阻隔材料8’和高阻结构8的第一高阻部801的制造步骤和选用材料可以相同，也可以不同。
半导体器件还可包括设在钝化层9上且连接栅极5的栅场板11。栅场板11能协助导电层7调节沟道层203和势垒层204之间的电场分布，进一步降低栅极5附近电场强度峰值，从而大幅度地提高器件的击穿电压。
接下来介绍半导体器件的制造方法，该制造方法的步骤包括：提供衬底1，详见图25a；在衬底1生长出成核层201；在成核层201生长出缓冲层202，详见图25b；在缓冲层202上生长出由金属材料所形成的导电材料层；对导电材料层进行刻蚀，得到由剩余导电材料层形成的导电层7；在缓冲层202及导电层7上出生长出由绝缘化合物所形成的高阻材料层；对高阻材料层进行刻蚀，得到由剩余高阻材料层形成且位于导电层7的上方的高阻结构8的第一高阻部801，以及覆盖在导电层7的侧面的阻隔材料8’，详见图25c；在缓冲层202上生长能够覆盖高阻结构8的第一高阻部801及阻隔材料8’的沟道层203；在沟道层203上生长势垒层204，详见图25d。
接着，通过刻蚀法对势垒层204、沟道层203和高阻结构8的第一高阻部801进行开孔，得到漏出导电层7的第一槽孔57a，详见图25e；在势垒层204上及第一槽孔57a中生长绝缘材料9a，详见图25f；通过刻蚀法对处于势垒层204上的绝缘材料9a进行开孔，得到源极孔区、栅极孔区和漏极孔区；通过生长、刻蚀和回火方式在源极孔区、栅极孔区和漏极孔区内分别形成源极6、栅极5和漏极4，同时在绝缘材料9a上形成连接栅极5的栅场板11，详见图25g；通过刻蚀法对处于第一槽孔57a内外的绝缘材料9a进行开孔，得到能够漏出导电层7的且比第一槽孔57a更细的第二槽孔57b，详见图25h；在第二槽孔57b内生长导电材料，然后对导电材料实施刻蚀，得到由导电材料所形成的且将导电层7连接栅极5的进行电耦合结构57，以及由剩余绝缘材料9a所形成且处于势垒层204上的钝化层9和用于包覆电耦合结构57的高阻结构8的第二高阻部802，详见图25i。
可以理解的，实施例七与实施例一的主要区别在于导电层7的材质和阻隔材料8’的设置。本领域技术人员可以在或者实施例一的前提下，理解本实施例的相关技术特征。
实施例八
如图6，8，26所示，与实施例七不同的是，导电层7包括沿着第一方向(即源极5至漏极4的布置方向)间隔设置的第一导电层701和将间隔设置的第一导电层701连接起来的第二导电层702，在多个第一导电层701中的一个上设有与电耦合结构57相接触的连接区。一些实施方式中，连接区位于具有连接区的第一导电层701背离第二导电层702延伸的延伸区域上。一些实施方式中，第二导电层702与第一导电层701相互垂直，以其降低制造难度。至少一个第一导电层701在衬底1上的正投影与栅极5在衬底1上的正投影相交。在向半导体器件的栅极5施加电势时，源极6和漏极4可以借助二维电子气连通，导电层7主要借助多个第一导电层701均匀地调节沟道层203和势垒层204之间的电场分布，相比于实施例一的半导体器件，具有第一导电层701和第二导电层702的半导体器件能更有效地降低栅极5附近电场强度峰值，并进一步提高器件的击穿电压，改善器件在高电压、高功率和/或高频率下的工作特性。然而，由于电场强度峰值出现栅极5与漏极4之间并紧邻栅极5，所以建议这样设置,即多个第一导电层701在衬底1上的正投影中最靠近漏极4的第一导电层701的正投影比栅极5在衬底1上的正投影更靠近漏极4在衬底1上的正投影，由此该最靠近漏极4的第一导电层701可以更好地降低栅极5的附近电场强度峰值，更有效地提高器件的击穿电压。
导电层7的第一表面位于沟道层203内，导电层7的第二表面与缓冲层202远离衬底1的表面相接，以保证导电层7适用于通过外延生长法和刻蚀法形成。各个第一导电层701可以为易于成型的矩形体。导电层7的厚度为10nm-1000nm，可以为100nm，可选为由金属材料所形成的结构，适用于通过外延生长法和刻蚀法形成。其中，该导电层7可以为钨、钼、钽和镍等耐高温材料中的一种或多种。各个第一导电层701沿第一方向的尺寸大于第一导电层7沿第二方向(即衬底1至半导体层2的布置方向)的尺寸，由此降低导电层7对沟通层3的占用比例，有效避免二维电子气浓度因此而明显下降，保证半导体器件的开关特性依旧有用且高效。
电耦合结构57为杆状结构，钝化层9还具有供电耦合结构57贯穿的避让孔，使得该电耦合结构57的一端处于半导体层2并内连接第一导电层701的连接区，而电耦合结构57的另一端处于半导体层2外并连接栅极5面向源极6的一侧。呈现为杆状结构的电耦合结构57不但可以实现导电层7与栅极5的电耦合，而且所使用的结构也非常简单。一些实施方式中，电耦合结构57最好与导电层7垂直，并由金属材料所形成，以适用于通过外延生长法和刻蚀法形成。其中，金属可以为钨、钼、钛和镍等耐高温材料中的一种或多种。
一些实施方式中，第一高阻部801设置在导电层7的除连接区之外的第一表面上。第一高阻部801的数量可选为一个或多个，当第一高阻部801的数量选为一个时，第一高阻部801覆盖所有的第一导电层701的第一表面(即上表面)并仅留出连接电耦合结构57用的连接区。当第一高阻部801的数量选为多个时，一个第一高阻部801覆盖具有连接区的第一导电层701的第一表面并仅留出连接电耦合结构57用的连接区，剩下的每个第一高阻部801均可独立覆盖一个第一导电层701的第一表面。第一高阻部801的制造材料为二氧化硅、氮化硅、氮化铝和氧化铝中的一种，厚度可选为5nm-1000nm，适用于通过外延生长法和刻蚀法形成。高阻结构8还包括包裹电耦合结构57的第二高阻部802，用于将电耦合结构57与二维电子气进行绝缘性隔离，拦截二维电子气产生的且向电耦合结构57流动的漏电流，由此可以有效降低该半导体器件在高压工作过程中因此而发生失效或损坏的风险。第二高阻部802的制造材料为二氧化硅、氮化硅、氮化铝和氧化铝中的一种，厚度可选为5nm-1000nm，适用于通过外延生长法和刻蚀法形成。
接下来介绍半导体器件的制造方法，该制造方法的步骤包括：提供衬底1；在衬底1生长出成核层201；在成核层201生长出缓冲层202；在缓冲层202上生长出由金属材料所形成的导电材料层；对导电材料层进行刻蚀，得到由剩余导电材料层形成的导电层7；在缓冲层202及导电层7上出生长出由绝缘化合物所形成的高阻材料层；对高阻材料层进行刻蚀，得到由剩余高阻材料层形成且位于导电层7的上方的高阻结构8的第一高阻部801，以及覆盖在导电层7的侧面的阻隔材料8’；在缓冲层202上生长能够覆盖高阻结构8的第一高阻部801及阻隔材料8’的沟道层203；在沟道层203上生长势垒层204。
接着，通过刻蚀法对势垒层204、沟道层203和第一阻隔结构8的第一阻隔部801进行开孔，得到漏出导电层7的第一槽孔57a；在势垒层204上及第一槽孔57a中生长绝缘材料；通过刻蚀法对处于势垒层204上的绝缘材料进行开孔，得到源极孔区、栅极孔区和漏极孔区；通过生长、刻蚀和回火方式在源极孔区、栅极孔区和漏极孔区内分别形成源极6、栅极5和漏极4，同时在绝缘材料上形成连接栅极5的栅场板11；通过刻蚀法对处于第一槽孔57a内外的绝缘材料进行开孔，得到能够漏出导电层7的且比第一槽孔57a更细的第二槽孔57b；在第二槽孔57b内生长导电材料，然后对导电材料实施刻蚀，得到由导电材料所形成的且将导电层7连接栅极5的进行电耦合结构57，以及由剩余绝缘材料所形成且处于势垒层204上的钝化层9和用于包覆电耦合结构57的高阻结构8的第二高阻部802。对应步骤可参见图27a-27i。
可以理解的，实施例八与实施例二的主要区别在于导电层7的材质和阻隔材料8’的设置。本领域技术人员可以在获知实施例二的前提下，理解本实施例的相关技术特征。
实施例九
如图8，10，28所示，与实施例八不同的是，第一导电层701沿着第三方向间隔设置。其中，第三方向与所述第一方向和第二方向垂直。也就是说，第一第二第三方向构成了直角坐标系。
可以理解的，实施例九与实施例三的主要区别在于导电层7的材质和阻隔材料8’的设置。本领域技术人员可以在获知实施例三的前提下，理解本实施例的相关技术特征。
实施例十
如图13，16，29所示，与实施例八不同的是，半导体器件还包括设在沟道层203内的尺寸相等的多个导电层7，以及用于将每个导电层7均电耦合至栅极5的多个电耦合结构57。多个导电层7沿第一方向间隔设置，且每个导电层7上均设有用于接收电耦合结构57的连接区，详见图16。每个导电层7沿第三方向的总尺寸大于单个导电层7沿第二 方向的尺寸，每个导电层7包含远离衬底1的第一表面及与之相对并靠近衬底1的第二表面。在多个导电层7中，至少有一个导电层7与栅极5在衬底1上的正投影相交。在向半导体器件的栅极5施加电势时，源极6和漏极4可以借助二维电子气连通，导电层7可以调节沟道层203和势垒层204之间的电场分布，相比于仅具有一个导电层的半导体器件，具有多个导电层7的半导体器件能更有效地降低栅极5附近电场强度峰值，并进一步提高器件的击穿电压，改善器件在高电压、高功率和/或高频率下的工作特性。然而，由于电场强度峰值出现在栅极5与漏极4之间并紧邻栅极5，所以建议这样设置,即多个导电层7在衬底1上的正投影中最靠近漏极4的导电层7的正投影比栅极5在衬底1上的正投影更靠近漏极4在衬底1上的正投影，由此该最靠近漏极4的第一导电层7可以更好地降低栅极5的附近电场强度峰值，更有效地提高器件的击穿电压。
可以理解的，实施例十与实施例四的主要区别在于导电层7的材质和阻隔材料8’的设置。本领域技术人员可以在获知实施例四的前提下，理解本实施例的相关技术特征。
实施例十一
如图17和30所示，与实施例七不同的是，导电层7的第一表面位于沟道层203内，导电层7的第二表面也位于沟道层203内，以保证导电层7适用于通过离子注入法和回火激活形成。导电层7可以为易于成型的矩形体。导电层7的厚度为10nm-1000nm，可以为100nm，可选为导电型掺杂半导体结构，适用于通过离子注入法和回火激活形成。其中，电型掺杂半导体结可选为N型掺杂半导体结构和P型掺杂半导体结构中的一种，尤其是由硅掺杂氮化镓所形成且掺杂浓度为5E17/cm3的结构。导电层7沿第一方向(即源极6至漏极4的布置方向)的尺寸大于导电层7沿第二方向(即衬底1至半导体层2的布置方向)的尺寸，由此降低导电层7对沟道层203的占用比例，有效避免二维电子气浓度因此而明显下降，保证半导体器件的开关特性依旧有用且高效。
该制造方法与实施例七不同的是，采用在沟道层203的第一次外延生长到一定高度后同样采用生长法生长金属材料层后刻蚀形成由金属材料组成的导电层7，之后再进行二次外延生长出剩余的沟道层203。
可以理解的，实施例十一与实施例五的主要区别在于导电层7的材质和阻隔材料8’的设置。本领域技术人员可以在获知实施例五的前提下，理解本实施例的相关技术特征。
实施例十二
如图20和31所示，与实施例十一不同的是，导电层7的第一表面位于与缓冲层202远离衬底的一侧相接，导电层7的第二表面位于缓冲层202内，以保证导电层7适用于通过离子注入法和回火激活形成。导电层7可以为易于成型的矩形体。导电层7的厚度为10nm-1000nm，例如可以为100nm，可选为导电型掺杂半导体结构，适用于通过离子注入法和回火激活形成。其中，电型掺杂半导体结可选为N型掺杂半导体结构和P型掺杂半导体结构中的一种，尤其是由硅掺杂氮化镓所形成且掺杂浓度为5E17/cm3的结构。导电层7沿第一方向(即源极6至漏极4的布置方向)的尺寸大于导电层7沿第二方向(即衬底1至外延层2的布置方向)的尺寸，由此降低导电层7对沟道层203的占用比例，有效避免二维电子气浓度因此而明显下降，保证半导体器件的开关特性依旧有用且高效。
与实施例十一不同的是，第一高阻部801能覆盖在导电层7的第一表面并留出导电层7的连接区。第一高阻部801用于将导电层7与二维电子气进行绝缘性隔离拦截二维电子气产生的且向导电层7流动的漏电流，由此可以有效降低该半导体器件在高压工作过程中因此而发生失效或损坏的风险。第一高阻部801选为了整层结构，所以第一高阻部801在衬底1的正投影面积要远远大于导电层7在衬底1的正投影面积，能够有效将导电层7与二维电子气进行绝缘性隔离。也是因为第一高阻部801选为了整层结构，所以第一高阻部801包括与缓冲层202远离衬底1的一侧相接的下表面，以及与沟道层203靠近衬底1的一侧相接的上表面。在其他实施例中，高阻结构8的第一高阻部801也可以是非整层结构，比如是像实施例十似的仅覆盖导电层7的非整层结构。
该制造方法与实施例十一不同的是，采用缓冲层202的第一次外延生长到一定高度后同样采用生长法生长金属材料层刻蚀形成由金属材料组成的导电层7，之后再进行二次外延生长出剩余的缓冲层。
可以理解的，实施例十二与实施例六的主要区别在于导电层7的材质和阻隔材料8’的设置。本领域技术人员可以在获知实施例六的前提下，理解本实施例的相关技术特征。
实施例十三
本申请进一步提出，所述电耦合结构57也可以位于栅极5的下方。参考图32和33，具体地，所述电耦合结构57包括槽体和导电材料，所述槽体从所述第二半导体层(204)表面向所述半导体层中延伸，所述导电材料填充所述槽体，所述导电材料一端与所述导电层直接相连，所述导电材料的另一端与所述栅极5的下表面直接相连，所述第二高阻部802包裹填充在所述槽体中的导电材料。
可以理解，本案公开的所有实施例中，在不存在冲突的前提下，所述电耦合结构57可以位于栅极5的侧面或下方。本实施例仅作为示例展示实施例一的变体。
实施例十四
在实施例一中，用于与电耦合结构57连接的连接区设置在导电层7的所述第一表面上，且第一高阻部801设置在导电层7的除连接区之外的第一表面上。对应地，参考图34，本实施例继续提出，导电层7的所述连接区也可以位于导电层7的侧面，而非实施例一中导电层7的第一表面。
实施例十五
在实施例二和三中，电耦合结构57连接在连接区703的侧面。因此对应地，参考图35，本实施例继续提出，该电耦合结构57也可以连接在连接区703的上表面。可以理解的，该连接方式的变体可以至少应用在实施例二和三中。
本领域技术人员可以理解，本公开主要通过两个方面对整体技术方案进行阐述，即由半导体材料制成的导电层对应的实施例和由金属材料制成的导电层对应的实施例。进一步地，上述两个方面的主要差异在于阻隔材料的设置。然而，这不意味着由金属材料制成的导电层对应的实施例一定设置有该阻隔材料，或由半导体材料制成的导电层对应的实施例一定不设置有该阻隔材料。上述两个方面对应的实施例，在没有冲突的情况下可以任意结合，且均在本公开的 保护范围内。
以上所述仅为本公开的优选实施方式，但本公开保护范围并不局限于此。任何本领域的技术人员在本公开公开的技术范围内，可容易地进行改变或变化，而这种改变或变化都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求书的保护范围为准。只要不存在结构冲突，各个实施例中所提到的各项技术特征均可以任意方式组合起来。本公开并不局限于文中公开的特定实施例，而是包括落入权利要求的范围内的所有技术方案。

Claims (21)

  1. 一种HEMT器件，其特征在于，包括：
    衬底；
    外延层，设置在所述衬底上，包括：第一半导体叠层和设置在所述第一半导体叠层上的第二半导体层；所述第一半导体叠层和所述第二半导体层之间的界面处形成有二维电子气；
    源极、漏极、和栅极，设置在所述第二半导体层上且间隔布置；
    导电层，设置所述外延层内并位于所述衬底与所述二维电子气之间；
    电耦合结构，其一端与所述栅极电连接，另一端向所述外延层内延伸并与所述导电层电连接；以及
    高阻结构，至少部分地设置在所述导电层与所述二维电子气之间，以及所述电耦合结构与所述二维电子气之间。
  2. 根据权利要求1所述的HEMT器件，其特征在于，所述高阻结构包括：
    第一高阻部，设置在所述外延层中且位于所述导电层的上方；
    第二高阻部，设置在所述外延层中且包裹所述电耦合结构。
  3. 根据权利要求2所述的HEMT器件，其特征在于，所述第一高阻部材料为硼掺杂氮化镓、二氧化硅、氮化硅、氮化铝和氧化铝的一种或多种，所述第二高阻部的材料为二氧化硅、氮化硅、氮化铝和氧化铝的一种或多种。
  4. 根据权利要求2所述的HEMT器件，其特征在于，所述电耦合结构包括槽体和导电材料，所述槽体从所述第二半导体层表面向所述外延层中延伸，所述导电材料填充所述槽体，所述导电材料一端与所述导电层直接相连，所述导电材料的另一端与所述栅极直接相连，所述第二高阻部包裹填充在所述槽体中的导电材料。
  5. 根据权利要求2所述的HEMT器件，其特征在于，所述电耦合结构包括槽体和导电材料，所述槽体从所述第二半导体层表面向所述外延层中延伸，所述导电材料填充所述槽体，所述导电材料一端与所述导电层直接相连，所述导电材料的另一端延伸出所述第二半导体层与所述栅极直接相连；所述HEMT器件进一步包括设置在所述第二半导体层上的钝化层，所述钝化层将所述栅极、所述源极、所述漏极、和所述导电材料绝缘性隔离。
  6. 根据权利要求4或5所述的HEMT器件，其特征在于，所述导电材料为钨、钼、钽、和镍中的一种或多种。
  7. 根据权利要求2所述的HEMT器件，其特征在于，所述导电层在所述衬底上的正投影与所述栅极在所述衬底上的正投影至少部分重合。
  8. 根据权利要求7所述的HEMT器件，其特征在于，所述导电层为完整的板状结构。
  9. 根据权利要求8所述的HEMT器件，其特征在于，所述导电层包括远离所述衬底的第一表面和靠近所述衬底的第二表面，其中，所述第一表面包括用于与所述电耦合结构电连接的连接区，所述第一高阻部设置在所述导电层除所述连接区之外的第一表面上。
  10. 根据权利要求7所述的HEMT器件，其特征在于，所述导电层包括间隔设置的多个第一导电层和将所述多个第一导电层连接起来的第二导电层。
  11. 根据权利要求10所述的HEMT器件，其特征在于，所述第二导电层包括相对的第一侧和第二侧，所述第二导电层的所述第一侧连接所述多个第一导电层。
  12. 根据权利要求11所述的HEMT器件，其特征在于，所述多个第一导电层沿第一方向间隔设置且沿第二方向延伸，所述第二导电层在所述第一方向将所述多个第一导电层连接，其中，所述第一方向为所述栅极与所述漏极的布置方向，所述第二方向为所述栅极的延伸方向。
  13. 根据权利要求11所述的HEMT器件，其特征在于，所述多个第一导电层沿第二方向间隔设置且沿第一方向延伸，所述第二导电层在所述第二方向将所述多个第一导电层连接，其中，所述第一方向为所述源极与所述漏极的布置方向，所述第二方向为所述栅极的延伸方向。
  14. 根据权利要求11所述的HEMT器件，其特征在于，所述多个第一导电层和所述第二导电层均包括远离所述衬底的第一表面和靠近所述衬底的第二表面，其中，所述第二导电层的所述第一表面包括用于与所述电耦合结构电连接的连接区，所述第一高阻部设置在所述第一导电层的所述第一表面和所述第二导电层的除所述连接区之外的所述第一表面上。
  15. 根据权利要求11所述的HEMT器件，其特征在于，所述第二导电层的所述第二侧包括用于与所述电耦合结构电连接的连接区，所述多个第一导电层和所述第二导电层均包括远离所述衬底的第一表面和靠近所述衬底的第二表面，其中，所述第一高阻部设置在所述第一导电层的所述第一表面和所述第二导电层的所述第一表面之上。
  16. 根据权利要求15所述的HEMT器件，其特征在于，所述导电层进一步包括第三导电层，所述第二导电层的所述第二侧与所述电耦合结构之间通过所述第三导电层连接；所述第三导电层包括远离所述衬底的第一表面和靠近所述衬底的第二表面，其中，所述第一高阻部设置在所述第一导电层的所述第一表面、所述第二导电层的所述第一表面、和所述第三导电层的所述第一表面之上。
  17. 根据权利要求3所述的HEMT器件，其特征在于，所述导电层为多个，所述多个导电层沿第二方向间隔设置且沿第一方向延伸，其中，所述第一方向为所述源极与所述漏极的布置方向，所述第二方向为所述栅极的延伸方向；
    所述电耦合结构为多个，每一所述电耦合结构与对应的所述导电层电连接。
  18. 根据权利要求17所述的HEMT器件，其特征在于，每一所述导电层包括远离所述衬底的第一表面和靠近所述衬底的第二表面，所述第一高阻部设置在所述第一表面上。
  19. 根据权利要求2所述的HEMT器件，其特征在于，所述导电层的材料为导电型掺杂半导体材料或金属材料。
  20. 根据权利要求19所述的HEMT器件，其特征在于，所述导电层的材料为金属材料，包括远离所述衬底的第一表面和靠近所述衬底的第二表面和连接所述第一表面和所述第二表面的侧面，所述导电层的侧面覆盖阻隔材料。
  21. 一种半导体器件，其特征在于，包括：
    衬底；
    外延层，设置在所述衬底上，包括：第一半导体叠层和设置在所述第一半导体叠层上的第二半导体层；所述第一半导体叠层和所述第二半导体层之间的界面处形成有二维电子气；
    源极、漏极和栅极，设置在所述第二半导体层上且间隔布置；
    导电层，间隔设置在所述外延层内并位于所述衬底与所述二维电子气之间；
    电耦合结构，用于将所述导电层电耦合至所述栅极；
    第一高阻部，用于绝缘隔离所述导电层与所述二维电子气；以及
    第二高阻部，用于绝缘隔离所述电耦合结构与所述二维电子气。
PCT/CN2023/120170 2022-10-25 2023-09-20 Hemt器件及半导体器件 WO2024087955A1 (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN202211327142.XA CN115663019A (zh) 2022-10-25 2022-10-25 Hemt器件及其制造方法
CN202211327296.9 2022-10-25
CN202211327296.9A CN115498020A (zh) 2022-10-25 2022-10-25 半导体器件及其制造方法
CN202211327142.X 2022-10-25

Publications (1)

Publication Number Publication Date
WO2024087955A1 true WO2024087955A1 (zh) 2024-05-02

Family

ID=90829960

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/120170 WO2024087955A1 (zh) 2022-10-25 2023-09-20 Hemt器件及半导体器件

Country Status (1)

Country Link
WO (1) WO2024087955A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130153967A1 (en) * 2011-12-20 2013-06-20 Infineon Technologies Austria Ag Compound Semiconductor Device with Buried Field Plate
CN112018176A (zh) * 2019-05-30 2020-12-01 苏州捷芯威半导体有限公司 一种半导体器件及其制造方法
CN112368843A (zh) * 2018-07-06 2021-02-12 美国亚德诺半导体公司 具有后场板的复合器件
CN115498020A (zh) * 2022-10-25 2022-12-20 湖南三安半导体有限责任公司 半导体器件及其制造方法
CN115663019A (zh) * 2022-10-25 2023-01-31 湖南三安半导体有限责任公司 Hemt器件及其制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130153967A1 (en) * 2011-12-20 2013-06-20 Infineon Technologies Austria Ag Compound Semiconductor Device with Buried Field Plate
CN112368843A (zh) * 2018-07-06 2021-02-12 美国亚德诺半导体公司 具有后场板的复合器件
CN112018176A (zh) * 2019-05-30 2020-12-01 苏州捷芯威半导体有限公司 一种半导体器件及其制造方法
CN115498020A (zh) * 2022-10-25 2022-12-20 湖南三安半导体有限责任公司 半导体器件及其制造方法
CN115663019A (zh) * 2022-10-25 2023-01-31 湖南三安半导体有限责任公司 Hemt器件及其制造方法

Similar Documents

Publication Publication Date Title
US10868134B2 (en) Method of making transistor having metal diffusion barrier
CN109585545B (zh) 一种增强型半导体器件及其制备方法
EP2763179B1 (en) High Electron Mobility Transistor (HEMT)
US11862719B2 (en) Group III-nitride high-electron mobility transistors with buried p-type layers and process for making the same
JP5953706B2 (ja) 化合物半導体装置及びその製造方法
US7649215B2 (en) III-nitride device passivation and method
JP5609055B2 (ja) 化合物半導体装置及びその製造方法
US20110227132A1 (en) Field-effect transistor
JP5866766B2 (ja) 化合物半導体装置及びその製造方法
JP2013058774A (ja) 支持されたゲート電極を備えるトランジスタの作製方法およびそれに関連するデバイス
TW200531277A (en) Enhancement mode iii-nitride fet
US20120320642A1 (en) Compound semiconductor device and method of manufacturing the same
JP2017157589A (ja) 半導体装置および半導体装置の製造方法
WO2018191096A1 (en) Diamond air bridge for thermal management of high power devices
KR20240008373A (ko) 향상된 성능을 갖는 고전자 이동도 트랜지스터들의 제조 방법들
WO2020181548A1 (zh) GaN基超结型垂直功率晶体管及其制作方法
CN115663019A (zh) Hemt器件及其制造方法
CN109148574A (zh) 半导体装置和制造半导体装置的方法
CN113192836A (zh) 射频半导体器件的制备方法及其结构
CN111933709A (zh) 一种具有高可靠性的氮化物器件及其制备方法
CN115498020A (zh) 半导体器件及其制造方法
WO2024087955A1 (zh) Hemt器件及半导体器件
JP2023041688A (ja) 埋込みｐ型層を有する第ＩＩＩ族窒化物高電子移動度トランジスタおよびその作製プロセス
WO2022033360A1 (zh) 一种混合栅场效应管及制备方法、开关电路
US20220367697A1 (en) Group iii-nitride transistors with back barrier structures and buried p-type layers and methods thereof