WO2024087629A1 - 三相电源变换电路的控制方法、装置、设备和存储介质 - Google Patents

三相电源变换电路的控制方法、装置、设备和存储介质 Download PDF

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WO2024087629A1
WO2024087629A1 PCT/CN2023/097374 CN2023097374W WO2024087629A1 WO 2024087629 A1 WO2024087629 A1 WO 2024087629A1 CN 2023097374 W CN2023097374 W CN 2023097374W WO 2024087629 A1 WO2024087629 A1 WO 2024087629A1
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Prior art keywords
bus
load
voltage
conversion circuit
phase power
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PCT/CN2023/097374
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English (en)
French (fr)
Inventor
龙谭
胡斌
黄招彬
刘文龙
周宏明
徐云松
毕然
黄正辉
韦东
张杰楠
Original Assignee
邯郸美的制冷设备有限公司
广东美的制冷设备有限公司
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Publication of WO2024087629A1 publication Critical patent/WO2024087629A1/zh

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Classifications

    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F24—HEATING; RANGES; VENTILATING
    • F24F—AIR-CONDITIONING; AIR-HUMIDIFICATION; VENTILATION; USE OF AIR CURRENTS FOR SCREENING
    • F24F11/00—Control or safety arrangements
    • F24F11/88—Electrical aspects, e.g. circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for ac mains or ac distribution networks
    • H02J3/01—Arrangements for reducing harmonics or ripples
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for ac mains or ac distribution networks
    • H02J3/26—Arrangements for eliminating or reducing asymmetry in polyphase networks
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from ac input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M7/219—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration

Definitions

  • the present application relates to the field of power supply circuits, and in particular to a control method, device, equipment and storage medium for a three-phase power supply conversion circuit.
  • PFC Power Factor Correction circuits
  • UPS uninterruptible power supplies
  • the voltage stress of the switch tube in the three-level PFC circuit is half of the voltage stress of the switch tube in the two-level PFC circuit under the same bus voltage.
  • the inductor volume in the three-level PFC circuit under the same power and switching frequency is smaller than the inductor volume in the two-level PFC circuit. Therefore, the three-level PFC circuit is widely used.
  • the present invention provides a control method for a three-phase power conversion circuit.
  • Devices, equipment and storage media are designed to effectively suppress interference such as harmonics and current distortion caused by unbalanced loads.
  • an embodiment of the present application provides a control method for a three-phase power conversion circuit, wherein the three-phase power conversion circuit is connected to a full bus load and a half bus load, and the method includes:
  • two-stage electrolytic capacitors are connected in series between the positive bus and the negative bus of the three-phase power conversion circuit
  • the full bus load is a load connected between the positive bus and the negative bus
  • the half bus load is a load connected to both ends of any one of the two-stage electrolytic capacitors
  • the half bus includes: an upper half bus between the midpoint of the two-stage electrolytic capacitor and the positive bus and a lower half bus between the midpoint of the two-stage electrolytic capacitor and the negative bus.
  • the half-bus load is divided into a first load corresponding to the upper half-bus and a second load corresponding to the lower half-bus, and adjusting the voltage magnitude relationship of the half-buses of the three-phase power conversion circuit based on the acquired operating power value includes:
  • the voltage of the upper bus is controlled to be greater than the voltage of the lower bus.
  • the method further comprises:
  • the voltage proportional relationship of the half bus of the three-phase power conversion circuit is adjusted.
  • the step of adjusting the voltage ratio of the half busbars of the three-phase power conversion circuit includes:
  • a voltage proportional relationship between the upper half bus and the lower half bus is determined.
  • the step of adjusting the voltage proportional relationship of the half-bus of the three-phase power conversion circuit includes:
  • the voltage proportional relationship between the half bus supplying power to the corresponding half bus load and the full bus of the three-phase power conversion circuit is determined.
  • the method further comprises:
  • the first current value is the current value flowing out of the intersection of the two-stage electrolytic capacitor corresponding to the positive bus
  • the second current value is the current value flowing back from the intersection of the two-stage electrolytic capacitor corresponding to the negative bus.
  • adjusting the voltage ratio of the half bus of the three-phase power conversion circuit includes:
  • the voltage ratio between the upper busbar and the lower busbar is controlled to be negatively correlated with the ratio of the first current value to the second current value.
  • an embodiment of the present application provides a control device for a three-phase power conversion circuit, wherein the three-phase power conversion circuit is connected to a full bus load and a half bus load, and the control device includes:
  • An acquisition module is configured to acquire the respective operating conditions of the full bus load and the half bus load. Power value;
  • a voltage regulating module configured to adjust the voltage magnitude relationship of the half bus of the three-phase power conversion circuit based on the acquired operating power value
  • two-stage electrolytic capacitors are connected in series between the positive bus and the negative bus of the three-phase power conversion circuit
  • the full bus load is a load connected between the positive bus and the negative bus
  • the half bus load is a load connected to both ends of any one of the two-stage electrolytic capacitors
  • the half bus includes: an upper half bus between the midpoint of the two-stage electrolytic capacitor and the positive bus and a lower half bus between the midpoint of the two-stage electrolytic capacitor and the negative bus.
  • an embodiment of the present application provides a control device for a three-phase power conversion circuit, comprising: a processor and a memory for storing a computer program that can be run on the processor, wherein the processor is configured to execute the steps of the method described in the first aspect of the embodiment of the present application when running the computer program.
  • an embodiment of the present application provides a storage medium, on which a computer program is stored.
  • the computer program is executed by a processor, the steps of the method described in the first aspect of the embodiment of the present application are implemented.
  • the technical solution provided by the embodiment of the present application obtains the operating power values of the full bus load and the half bus load of the three-phase power conversion circuit; based on the obtained operating power value, the voltage magnitude relationship of the half bus of the three-phase power conversion circuit is adjusted; wherein, two-stage electrolytic capacitors are connected in series between the positive bus and the negative bus of the three-phase power conversion circuit, the full bus load is the load connected between the positive bus and the negative bus, the half bus load is the load connected to both ends of any one of the two-stage electrolytic capacitors, and the half bus includes: the upper half bus between the midpoint of the two-stage electrolytic capacitor and the positive bus and the lower half bus between the midpoint of the two-stage electrolytic capacitor and the negative bus.
  • the voltage magnitude relationship of the half bus can be adjusted online based on the condition of load imbalance, which can effectively suppress interference such as harmonics and current distortion caused by unbalanced load.
  • FIG1 is a schematic diagram of a three-phase active PFC circuit based on VIENNA according to an embodiment of the present application
  • FIG2 is a schematic diagram of a three-phase power conversion circuit connected to a full bus load and a half bus load;
  • 3A and 3B are schematic diagrams of one-phase circuits of other three-phase power conversion circuits
  • FIG4 is a flow chart of a control method for a three-phase power conversion circuit according to an embodiment of the present application.
  • FIG5 is a circuit diagram of a three-phase power conversion circuit connected to a load in an application example of the present application
  • FIG6 is a schematic diagram of the structure of a control device for a three-phase power conversion circuit according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of the structure of a control device of a three-phase power conversion circuit according to an embodiment of the present application.
  • the embodiment of the present application provides a control method for a three-phase power conversion circuit, wherein the three-phase power conversion circuit is connected to a full bus load and a half bus load. Based on the control method of the embodiment of the present application, interference such as harmonics and current distortion caused by unbalanced loads can be effectively suppressed.
  • the three-phase power conversion circuit is first described by way of example.
  • the three-phase power conversion circuit of the embodiment of the present application can be a three-phase active PFC circuit, for example, a three-level topology circuit based on VIENNA (Vienna) or NPC (Neutral point clamped).
  • Figure 1 shows a three-phase active PFC circuit based on VIENNA, including: three PFC inductors, a Vienna PFC module and two-stage electrolytic capacitors; the three PFC inductors are connected to a three-phase power supply for filtering the three-phase power supply; the Vienna PFC module is connected to the output ends of the three PFC inductors for power factor correction of the filtered power supply; the two-stage electrolytic capacitor includes: a positive bus and a negative bus connected in series with the Vienna PFC module; The first capacitor C1 and the second capacitor C2, and the connection point between the first capacitor C1 and the second capacitor C2 is used as the neutral point O.
  • Full bus refers to the line between the positive and negative busbars of the two-stage electrolytic capacitors connected in series in the high-voltage DC bus filter circuit;
  • Half bus refers to the high voltage DC bus filter circuit using two-stage electrolytic capacitors in series.
  • the area between the midpoint of the two-stage electrolytic capacitors in series and the negative bus is the lower half bus
  • the area between the midpoint of the two-stage electrolytic capacitors in series and the positive bus is the upper half bus.
  • Both the upper half bus and the lower half bus are half buses.
  • Midpoint potential the voltage between the midpoint of the two-stage electrolytic capacitor and the capacitor ground, that is, the voltage between the neutral point O and the grounding point G.
  • the three-phase power conversion circuit can be connected to a full bus load and a half bus load.
  • the full bus load is a load connected between the positive bus and the negative bus, that is, a load connected to the full bus
  • the half bus load is a load connected to either end of any one of the two-stage electrolytic capacitors.
  • the half bus load is divided into a first load corresponding to the upper half bus (i.e., the upper half bus load) and a second load corresponding to the lower half bus (i.e., the lower half bus load).
  • FIG. 3A and FIG. 3B respectively illustrate schematic diagrams of one phase circuit of the three-phase power conversion circuit.
  • the control method of the three-phase power conversion circuit in the embodiment of the present application includes:
  • Step 401 obtaining the operating power values of the full bus load and the half bus load respectively.
  • Step 402 Based on the acquired operating power value, adjust the voltage magnitude relationship of the half bus of the three-phase power conversion circuit.
  • the half bus of the three-phase power conversion circuit includes: an upper half bus between the midpoint of the two-stage electrolytic capacitor and the positive bus and a lower half bus between the midpoint of the two-stage electrolytic capacitor and the negative bus.
  • Adjusting the voltage magnitude relationship of the half bus can be understood as adjusting the voltage magnitude relationship between the upper half bus and the lower half bus, that is, adjusting the voltage u po of the capacitor C1 and the capacitor C2 shown in Figures 1 and 2.
  • the voltage relationship of the half busbar can be adjusted online based on the load imbalance condition, which can effectively suppress interference such as harmonics and current distortion caused by unbalanced load.
  • the half-bus load is divided into a first load corresponding to the upper half-bus and a second load corresponding to the lower half-bus, and based on the acquired operating power value, the voltage magnitude relationship of the half-bus of the three-phase power conversion circuit is adjusted, including:
  • the voltage of the upper half bus is controlled to be equal to the voltage of the lower half bus
  • the voltage of the upper half bus is controlled to be less than the voltage of the lower half bus
  • the voltage of the upper bus is controlled to be greater than the voltage of the lower bus.
  • adjusting the voltage magnitude relationship of the half busbars of the three-phase power conversion circuit may include the following situations:
  • the operating power value of the upper bus load is greater than the operating power value of the lower bus load; if the average current flowing from the neutral point O to the load is positive, it is deemed that the operating power value of the lower bus load is greater than the operating power value of the upper bus load.
  • control method further includes:
  • the voltage proportional relationship of the half bus of the three-phase power conversion circuit is adjusted.
  • the half-bus voltage can be adjusted more accurately, thereby better suppressing interference such as harmonics and current distortion caused by unbalanced loads.
  • adjusting the voltage ratio of the half bus of the three-phase power conversion circuit includes:
  • a voltage proportional relationship between the upper bus and the lower bus is determined.
  • the voltage ratio relationship between the upper bus and the lower bus is determined, as shown in the following formula (1):
  • u po is the voltage of the upper bus, i.e., the voltage of capacitor C1
  • u on is the voltage of the lower bus, i.e., the voltage of capacitor C2
  • k c is the proportionality coefficient
  • P pn is the operating power value of the full bus load
  • P po is the operating power value of the first load (i.e., the upper bus load)
  • P on is the operating power value of the second load (i.e., the lower bus load).
  • k c is 1.
  • the voltage ratio of the half bus of the three-phase power conversion circuit is adjusted, including include:
  • the voltage proportional relationship between the half bus supplying power to the corresponding half bus load and the full bus of the three-phase power conversion circuit is determined.
  • the voltage ratio between the half-bus supplying power to the corresponding half-bus load and the full bus of the three-phase power conversion circuit is determined as shown in the following formula (2):
  • u on is the voltage of the lower half bus, that is, the voltage of capacitor C2
  • u pn is the voltage of the full bus, that is, the voltage between the two-stage electrolytic capacitors
  • k c is the proportionality coefficient
  • P pn is the operating power value of the full bus load
  • P on is the operating power value of the second load (that is, the lower half bus load).
  • k c is 1.
  • control method further includes:
  • the first current value is the current value flowing out of the intersection of the two-stage electrolytic capacitors corresponding to the positive bus
  • the second current value is the current value flowing back to the intersection of the two-stage electrolytic capacitors corresponding to the negative bus.
  • the first current value is the current value i p flowing from point P to the load
  • the second current value is the current value i n flowing back to the capacitor from point N.
  • adjusting the voltage ratio of the half bus of the three-phase power conversion circuit includes:
  • the voltage ratio between the upper busbar and the lower busbar is controlled to be negatively correlated with the ratio of the first current value to the second current value.
  • the ratio of the upper bus voltage u po and the lower bus voltage u on can be adjusted according to the ratio of the current value i p flowing to the load at point P and the current value in flowing back to the capacitor at point N.
  • the larger the ratio of the current values in the smaller the ratio of the voltage upo to the voltage u on , that is, the two have a negative correlation.
  • u po is the voltage of the upper busbar, i.e., the voltage of capacitor C1
  • u on is the voltage of the lower busbar, i.e., the voltage of capacitor C2
  • k c is the proportionality coefficient
  • ip is the first current value
  • in is the second current value.
  • k c is 1.
  • the operating power value of the half-bus load can be calculated from the current value i o flowing from the neutral point O to the load and the voltages of the upper and lower half-buses.
  • the operating power value of the entire bus load can be calculated based on the aforementioned first current value, the second current value and the voltage u pn of the entire bus, for example, as shown in the following formula (4):
  • the current value ip flowing from point P to the load, the current value in flowing out of the load from point N , and the current value io flowing to the load from point O can be obtained from the three-phase currents ia, ib, ic and the on-off conditions of the three-phase switches Sa, Sb, Sc.
  • voltage limit values may be set for different mounting modes, as follows:
  • the voltage of the upper half busbar is controlled to be lower than the voltage upper limit Umax to avoid overvoltage on the upper capacitor; the voltage of the lower half busbar is controlled to be lower than the voltage upper limit Umax and higher than the voltage lower limit Umin to meet the load demand and avoid overvoltage on the lower capacitor.
  • the voltage of the upper half busbar is controlled to be lower than the voltage upper limit Umax and higher than the voltage lower limit Umin, to meet the load demand and avoid overvoltage of the upper capacitor; the voltage of the lower half busbar is controlled to be lower than the voltage upper limit Umax to avoid overvoltage of the lower capacitor;
  • the voltage of the upper busbar is controlled to be lower than the voltage on the upper busbar.
  • the voltage limit Umax is higher than the voltage lower limit Umin1
  • the voltage of the lower half bus is controlled to be lower than the voltage upper limit Umax and higher than the voltage lower limit Umin2, avoiding overvoltage of the upper and lower capacitors and meeting the voltage requirements of the upper and lower loads.
  • the voltage upper limit value Umax is determined by the smaller value of the capacitor voltage allowable value and the load withstand voltage value. If there is no load connected, the load withstand voltage value is equal to the capacitor voltage allowable value by default; the voltage lower limit values Umin, Umin1 and Umin2 are determined by the required voltage of the load. For example, when the full bus is mounted and the lower half bus is mounted, the required voltage of the lower bus load is 250V, then Umin is 250V.
  • control method of the embodiment of the present application is illustrated below with reference to an application example.
  • a three-phase power conversion circuit is used as a power supply unit of a variable frequency air conditioner, wherein the compressor load is powered by the full bus, and the fan load is powered by the lower half bus.
  • the voltage U on of the lower half bus is controlled to be lower than the voltage U po of the upper half bus; in addition, the ratio of the voltage U po to the voltage U on can also be controlled according to the operating power value P pn of the compressor and the operating power value P on of the fan, as shown in the following formula (5):
  • the voltage U on of the lower bus is controlled between Umax and Umin.
  • Umax is determined by the smaller value of the capacitor voltage allowable value and the withstand voltage value of the fan IPM (intelligent power module) to avoid overvoltage damage to the device;
  • Umin is the maximum required voltage of the fan, that is, the required voltage at the maximum speed and maximum power.
  • the embodiment of the present application also provides a control device for a three-phase power conversion circuit.
  • the control device for the three-phase power conversion circuit corresponds to the above-mentioned control method, and each step in the above-mentioned control method embodiment is also fully applicable to the control device embodiment of the three-phase power conversion circuit.
  • the control device of the three-phase power conversion circuit includes: an acquisition module 601 and a voltage regulation module 602.
  • the acquisition module 601 is configured to acquire the full bus load and the half bus load.
  • the voltage regulating module 602 is configured to adjust the voltage magnitude relationship of the half bus of the three-phase power conversion circuit based on the acquired operating power value; wherein, two-stage electrolytic capacitors are connected in series between the positive bus and the negative bus of the three-phase power conversion circuit, the full bus load is the load connected between the positive bus and the negative bus, the half bus load is the load connected to both ends of any one of the two-stage electrolytic capacitors, and the half bus includes: an upper half bus between the midpoint of the two-stage electrolytic capacitor and the positive bus and a lower half bus between the midpoint of the two-stage electrolytic capacitor and the negative bus.
  • the half-bus load is divided into a first load corresponding to the upper half-bus and a second load corresponding to the lower half-bus, and the voltage regulating module 602 regulates the voltage magnitude relationship of the half-bus of the three-phase power conversion circuit, including:
  • the voltage of the upper bus is controlled to be greater than the voltage of the lower bus.
  • the voltage regulation module 602 is further configured to:
  • the voltage proportional relationship of the half bus of the three-phase power conversion circuit is adjusted.
  • the voltage regulating module 602 regulates the voltage ratio of the half bus of the three-phase power conversion circuit, including:
  • a voltage proportional relationship between the upper half bus and the lower half bus is determined.
  • the voltage regulating module 602 regulates the voltage proportional relationship of the half bus of the three-phase power conversion circuit, including:
  • the voltage proportional relationship between the half bus supplying power to the corresponding half bus load and the full bus of the three-phase power conversion circuit is determined.
  • the acquisition module 601 is also configured to acquire a first current value and a second current value;
  • the voltage regulation module 602 is also configured to adjust the voltage proportional relationship of the half bus of the three-phase power conversion circuit based on the proportional relationship between the first current value and the second current value; wherein the first current value is the current value flowing out of the intersection of the two-stage electrolytic capacitor corresponding to the positive bus, and the second current value is the current value returning from the intersection of the two-stage electrolytic capacitor corresponding to the negative bus.
  • the voltage regulation module 602 regulates the voltage ratio relationship of the half bus of the three-phase power conversion circuit, including: controlling the voltage ratio relationship between the upper half bus and the lower half bus and the ratio of the first current value to the second current value to be negatively correlated.
  • the acquisition module 601 and the voltage regulation module 602 can be implemented by a processor.
  • the processor needs to run the computer program in the memory to implement its function.
  • control device for the three-phase power conversion circuit provided in the above embodiment only uses the division of the above program modules as an example when performing control.
  • the above processing can be assigned to different program modules as needed, that is, the internal structure of the device is divided into different program modules to complete all or part of the processing described above.
  • control device for the three-phase power conversion circuit provided in the above embodiment belongs to the same concept as the aforementioned control method embodiment. The specific implementation process is detailed in the method embodiment and will not be repeated here.
  • the embodiment of the present application also provides a control device for a three-phase power conversion circuit.
  • FIG7 only shows an exemplary structure of the control device rather than the entire structure. Part of the structure shown in FIG7 can be implemented as needed. structure or all structures.
  • the control device 700 provided in the embodiment of the present application includes: at least one processor 701, a memory 702 and a user interface 703.
  • the various components in the control device 700 are coupled together via a bus system 704.
  • the bus system 704 is used to realize the connection and communication between these components.
  • the bus system 704 also includes a power bus, a control bus and a status signal bus.
  • various buses are marked as bus system 704 in FIG. 7 .
  • the user interface 703 may include a display, a keyboard, a mouse, a trackball, a click wheel, keys, buttons, a touch pad or a touch screen.
  • the memory 702 in the embodiment of the present application is used to store various types of data to support the operation of the control device. Examples of such data include: any computer program used to operate on the control device.
  • the control method of the control device disclosed in the embodiment of the present application can be applied to the processor 701, or implemented by the processor 701.
  • the processor 701 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the control method of the control device can be completed by the hardware integrated logic circuit in the processor 701 or the instructions in the form of software.
  • the above-mentioned processor 701 can be a general-purpose processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc.
  • the processor 701 can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiment of the present application.
  • the general-purpose processor can be a microprocessor or any conventional processor, etc.
  • the decoding processor 701 In combination with the steps of the method disclosed in the embodiment of the present application, it can be directly embodied as a hardware decoding processor to execute, or it can be executed by a combination of hardware and software modules in the decoding processor.
  • the software module can be located in a storage medium, which is located in the memory 702.
  • the processor 701 reads the information in the memory 702 and completes the steps of the control method of the control device provided in the embodiment of the present application in combination with its hardware.
  • control device may be one or more application specific integrated circuits.
  • the method can be implemented by an ASIC (Application Specific Integrated Circuit), a DSP, a programmable logic device (PLD), a complex programmable logic device (CPLD), a field programmable gate array (FPGA), a general-purpose processor, a controller, a microcontroller (MCU), a microprocessor, or other electronic components to execute the aforementioned method.
  • ASIC Application Specific Integrated Circuit
  • DSP digital signal processor
  • PLD programmable logic device
  • CPLD complex programmable logic device
  • FPGA field programmable gate array
  • controller a microcontroller
  • MCU microcontroller
  • microprocessor or other electronic components to execute the aforementioned method.
  • the memory 702 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories.
  • the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disk, or a compact disc read-only memory (CD-ROM); the magnetic surface memory can be a disk memory or a tape memory.
  • the volatile memory can be a random access memory (RAM), which is used as an external cache.
  • RAM Static Random Access Memory
  • SSRAM Synchronous Static Random Access Memory
  • DRAM Dynamic Random Access Memory
  • SDRAM Synchronous Dynamic Random Access Memory
  • DDRSDRAM Double Data Rate Synchronous Dynamic Random Access Memory
  • ESDRAM Enhanced Synchronous Dynamic Random Access Memory
  • SLDRAM SyncLink Dynamic Random Access Memory
  • SDRAM SyncLink Dynamic Random Access Memory
  • the present application also provides a storage medium, namely a computer storage medium, which may be a computer-readable storage medium, for example, a memory 702 storing a computer program, and the computer program may be executed by a processor 701 of a control device to complete the steps described in the method of the present application.
  • the computer-readable storage medium may be a memory such as a ROM, a PROM, an EPROM, an EEPROM, a Flash Memory, a magnetic surface memory, an optical disk, or a CD-ROM.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Combustion & Propulsion (AREA)
  • Mechanical Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Supply And Distribution Of Alternating Current (AREA)

Abstract

本申请公开了一种三相电源变换电路的控制方法、装置、设备和存储介质。该方法包括：获取三相电源变换电路的全母线负载和半母线负载各自的运行功率值；基于获取的运行功率值，调节三相电源变换电路的半母线的电压大小关系；其中，三相电源变换电路的正母线、负母线之间串联两级电解电容，全母线负载为连接于正母线与负母线之间的负载，半母线负载为连接于两级电解电容中任一个电容两端的负载，半母线包括：两级电解电容的中点与正母线之间的上半母线和两级电解电容的中点与负母线之间的下半母线。

Description

三相电源变换电路的控制方法、装置、设备和存储介质
相关申请的交叉引用
本申请基于申请号为202211327044.6、申请日为2022年10月25日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及电源电路领域，尤其涉及一种三相电源变换电路的控制方法、装置、设备和存储介质。
背景技术
PFC(Power Factor Correction，功率因数校正)电路广泛应用在通信电源和不间断电源(UPS，Uninterrupted Power Supply)中，它除了需要把交流电压转换为直流电压外，同时还要校正输入的功率因数，满足各种标准对输入特性的要求。三电平PFC电路中的开关管的电压应力是相同母线电压下两电平PFC电路的开关管的电压应力的一半，同时，相同功率和开关频率下的三电平PFC电路中的电感体积小于两电平PFC电路中的电感体积，因此，三电平PFC电路得到广泛应用。
相关技术中，为了避免负载不平衡导致的谐波、电压控制稳定等问题，三电平PFC电路的上半母线和下半母线的负载需要平衡设置，从而使得三电平PFC电路的应用受限。
发明内容
有鉴于此，本申请实施例提供了一种三相电源变换电路的控制方法、 装置、设备和存储介质，旨在有效抑制不平衡负载导致的谐波、电流畸变等干扰。
本申请实施例的技术方案是这样实现的：
第一方面，本申请实施例提供了一种三相电源变换电路的控制方法，所述三相电源变换电路连接全母线负载和半母线负载，所述方法包括：
获取所述全母线负载和所述半母线负载各自的运行功率值；
基于获取的所述运行功率值，调节所述三相电源变换电路的半母线的电压大小关系；
其中，所述三相电源变换电路的正母线、负母线之间串联两级电解电容，所述全母线负载为连接于所述正母线与所述负母线之间的负载，所述半母线负载为连接于所述两级电解电容中任一个电容两端的负载，所述半母线包括：所述两级电解电容的中点与所述正母线之间的上半母线和所述两级电解电容的中点与所述负母线之间的下半母线。
在一些实施方案中，所述半母线负载分为对应于所述上半母线的第一负载和对应于所述下半母线的第二负载，所述基于获取的所述运行功率值，调节所述三相电源变换电路的半母线的电压大小关系，包括：
若确定所述第一负载的运行功率值等于所述第二负载的运行功率值，则控制所述上半母线的电压和所述下半母线的电压相等；
若确定所述第一负载的运行功率值大于所述第二负载的运行功率值，则控制所述上半母线的电压小于所述下半母线的电压；
若确定所述第一负载的运行功率值小于所述第二负载的运行功率值，则控制所述上半母线的电压大于所述下半母线的电压。
在一些实施方案中，所述方法还包括：
基于获取的所述运行功率值，调节所述三相电源变换电路的半母线的电压比例关系。
在一些实施方案中，所述调节所述三相电源变换电路的半母线的电压比例关系，包括：
基于所述全母线负载的运行功率值、所述第一负载的运行功率值及所述第二负载的运行功率值，确定所述上半母线与所述下半母线之间的电压比例关系。
在一些实施方案中，若所述三相电源变换电路的半母线负载为所述第一负载和所述第二负载中的一种，所述调节所述三相电源变换电路的半母线的电压比例关系，包括：
基于所述全母线负载的运行功率值与相应的所述半母线负载的运行功率值，确定供电给相应的所述半母线负载的半母线与所述三相电源变换电路的全母线之间的电压比例关系。
在一些实施方案中，所述方法还包括：
获取第一电流值和第二电流值；
基于所述第一电流值与所述第二电流值的比例关系，调节所述三相电源变换电路的半母线的电压比例关系；
其中，所述第一电流值为所述两级电解电容相应于所述正母线的交点流出的电流值，所述第二电流值为所述两级电解电容相应于所述负母线的交点回流的电流值。
在一些实施方案中，所述调节所述三相电源变换电路的半母线的电压比例关系，包括：
控制所述上半母线与所述下半母线之间的电压比例关系和所述第一电流值与所述第二电流值的比值呈负相关性。
第二方面，本申请实施例提供了一种三相电源变换电路的控制装置，所述三相电源变换电路连接全母线负载和半母线负载，所述控制装置包括：
获取模块，配置为获取所述全母线负载和所述半母线负载各自的运行 功率值；
电压调节模块，配置为基于获取的所述运行功率值，调节所述三相电源变换电路的半母线的电压大小关系；
其中，所述三相电源变换电路的正母线、负母线之间串联两级电解电容，所述全母线负载为连接于所述正母线与所述负母线之间的负载，所述半母线负载为连接于所述两级电解电容中任一个电容两端的负载，所述半母线包括：所述两级电解电容的中点与所述正母线之间的上半母线和所述两级电解电容的中点与所述负母线之间的下半母线。
第三方面，本申请实施例提供了一种三相电源变换电路的控制设备，包括：处理器和用于存储能够在处理器上运行的计算机程序的存储器，其中，所述处理器配置为运行计算机程序时，执行本申请实施例第一方面所述方法的步骤。
第四方面，本申请实施例提供了一种存储介质，所述存储介质上存储有计算机程序，所述计算机程序被处理器执行时，实现本申请实施例第一方面所述方法的步骤。
本申请实施例提供的技术方案，获取三相电源变换电路的全母线负载和半母线负载各自的运行功率值；基于获取的运行功率值，调节三相电源变换电路的半母线的电压大小关系；其中，三相电源变换电路的正母线、负母线之间串联两级电解电容，全母线负载为连接于正母线与负母线之间的负载，半母线负载为连接于两级电解电容中任一个电容两端的负载，半母线包括：两级电解电容的中点与正母线之间的上半母线和两级电解电容的中点与负母线之间的下半母线。如此，能够基于负载不平衡的条件，在线对半母线的电压大小关系进行调节，可以有效抑制不平衡负载导致的谐波、电流畸变等干扰。
附图说明
图1为本申请实施例基于VIENNA的三相有源PFC电路的示意图；
图2为三相电源变换电路连接全母线负载和半母线负载的示意图；
图3A及图3B为其他三相电源变换电路的一相电路示意图；
图4为本申请实施例三相电源变换电路的控制方法的流程示意图；
图5为本申请一应用示例中三相电源变换电路连接负载的电路示意图；
图6为本申请实施例三相电源变换电路的控制装置的结构示意图；
图7为本申请实施例三相电源变换电路的控制设备的结构示意图。
具体实施方式
下面结合附图及实施例对本申请再作进一步详细的描述。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
本申请实施例提供了一种三相电源变换电路的控制方法，所述三相电源变换电路连接全母线负载和半母线负载。基于本申请实施例的控制方法，可以有效抑制不平衡负载导致的谐波、电流畸变等干扰。
在对本申请实施例的控制方法进行说明之前，先对该三相电源变换电路进行示例性说明。
本申请实施例的三相电源变换电路可以为三相有源PFC电路，例如，基于VIENNA(维也纳)或者NPC(Neutral point clamped，中性点钳位)的三电平拓扑电路。图1示出了基于VIENNA的三相有源PFC电路，包括：三个PFC电感、维也纳PFC模块和两级电解电容；该三个PFC电感连接三相电源，用于对所述三相电源进行滤波处理；该维也纳PFC模块连接所述三个PFC电感的输出端，用于对滤波处理后的电源进行功率因数校正处理；该两级电解电容包括：串接于所述维也纳PFC模块的正母线、负母线之间 的第一电容C1和第二电容C2，第一电容C1与第二电容C2之间的连接点作为中性点O。
针对上述三相电源变换电路，定义如下术语：
全母线，指在采用两级电解电容串联的高压直流母线滤波电路中，两级电解电容串联的正负母线之间的线路；
半母线，指在采用两级电解电容串联的高压直流母线滤波电路中，两级电解电容串联的中点到负母线之间为下半母线，两级电解电容串联的中点与正母线之间为上半母线，上半母线和下半母线都是半母线；
中点电位，两级电解电容的中点相对于电容地的电压，即中性点O到接地点G之间的电压。
示例性地，如图2所示，三相电源变换电路可以连接全母线负载和半母线负载。其中，全母线负载为连接于正母线与负母线之间的负载，即接入至全母线上的负载，半母线负载为连接于两级电解电容中任一个电容两端的负载，半母线负载分为对应于上半母线的第一负载(即上半母线负载)和对应于下半母线的第二负载(即下半母线负载)。
需要说明的是，三相电源变换电路可以有其他变形形式，例如，图3A及图3B分别示意出三相电源变换电路的一相电路示意图。
本申请实施例三相电源变换电路的控制方法，如图4所示，包括：
步骤401，获取全母线负载和半母线负载各自的运行功率值。
步骤402，基于获取的运行功率值，调节三相电源变换电路的半母线的电压大小关系。
本申请实施例中，三相电源变换电路的半母线包括：两级电解电容的中点与正母线之间的上半母线和两级电解电容的中点与负母线之间的下半母线，调节半母线的电压大小关系可以理解为调节上半母线与下半母线之间的电压大小关系，即调节图1及图2所示的电容C1的电压upo和电容C2 的电压uon的大小关系。如此，能够基于负载不平衡的条件，在线对半母线的电压大小关系进行调节，可以有效抑制不平衡负载导致的谐波、电流畸变等干扰。
示例性地，半母线负载分为对应于上半母线的第一负载和对应于下半母线的第二负载，基于获取的运行功率值，调节三相电源变换电路的半母线的电压大小关系，包括：
若确定第一负载的运行功率值等于第二负载的运行功率值，则控制上半母线的电压和下半母线的电压相等；
若确定第一负载的运行功率值大于第二负载的运行功率值，则控制上半母线的电压小于下半母线的电压；
若确定第一负载的运行功率值小于第二负载的运行功率值，则控制上半母线的电压大于下半母线的电压。
举例来说，调节三相电源变换电路的半母线的电压大小关系，可以包括以下情形：
1)、当仅有全母线负载或上、下半母线负载相等时，上、下半母线等效负载相等，即第一负载的运行功率值等于第二负载的运行功率值，控制上半母线的电压和下半母线的电压相等；
2)、当全母线挂载、下半母线挂载时，则视为下半母线负载的运行功率值大于上半母线负载的运行功率值，则控制上半母线的电压大于下半母线的电压；
3)、当全母线挂载、上半母线挂载时，则视为上半母线负载的运行功率值大于下半母线负载的运行功率值，则控制上半母线的电压小于下半母线的电压；
4)、当上半母线挂载、下半母线挂载时，若上半母线负载的运行功率值大于下半母线负载的运行功率值，则控制上半母线的电压小于下半母线 的电压；若下半母线负载的运行功率值大于上半母线负载的运行功率值，则控制上半母线的电压大于下半母线的电压。
在其他实施例中，当上半母线挂载、下半母线挂载时，若中性点O流向负载的平均电流为负，则视为上半母线负载的运行功率值大于下半母线负载的运行功率值；若中性点O流向负载的平均电流为正，则视为下半母线负载的运行功率值大于上半母线负载的运行功率值。
在一些实施例中，该控制方法还包括：
基于获取的运行功率值，调节三相电源变换电路的半母线的电压比例关系。
如此，通过调节三相电源变换电路的半母线的电压比例关系，可以更精确地对半母线电压进行调节，从而更好地抑制不平衡负载导致的谐波、电流畸变等干扰。
示例性地，调节三相电源变换电路的半母线的电压比例关系，包括：
基于全母线负载的运行功率值、第一负载的运行功率值及第二负载的运行功率值，确定上半母线与下半母线之间的电压比例关系。
在一应用示例中，基于全母线负载的运行功率值、第一负载的运行功率值及第二负载的运行功率值，确定上半母线与下半母线之间的电压比例关系，具体如下公式(1)所示：
其中，upo为上半母线的电压，即电容C1的电压，uon为下半母线的电压，即电容C2的电压，kc为比例系数，Ppn为全母线负载的运行功率值，Ppo为第一负载(即上半母线负载)的运行功率值，Pon为第二负载(即下半母线负载)的运行功率值。优选地，为了达到最佳的抑制效果，kc为1。
在一些实施方案中，若三相电源变换电路的半母线负载为第一负载和第二负载中的一种，调节三相电源变换电路的半母线的电压比例关系，包 括：
基于全母线负载的运行功率值与相应的半母线负载的运行功率值，确定供电给相应的半母线负载的半母线与三相电源变换电路的全母线之间的电压比例关系。
在一应用示例中，假定三相电源变换电路的半母线负载为下半母线负载(即第二负载)，则确定供电给相应的半母线负载的半母线与三相电源变换电路的全母线之间的电压比例关系如下公式(2)所示：
其中，uon为下半母线的电压，即电容C2的电压，upn为全母线的电压，即两级电解电容之间的电压，kc为比例系数，Ppn为全母线负载的运行功率值，Pon为第二负载(即下半母线负载)的运行功率值。优选地，为了达到最佳的抑制效果，kc为1。
在一些实施例中，该控制方法还包括：
获取第一电流值和第二电流值；
基于第一电流值与第二电流值的比例关系，调节三相电源变换电路的半母线的电压比例关系；
其中，第一电流值为两级电解电容相应于正母线的交点流出的电流值，第二电流值为两级电解电容相应于负母线的交点回流的电流值。
参照图2，第一电流值即P点流向负载的电流值ip，第二电流值即N点流回电容的电流值in。
示例性地，调节三相电源变换电路的半母线的电压比例关系，包括：
控制上半母线与下半母线之间的电压比例关系和第一电流值与第二电流值的比值呈负相关性。
这里，可以根据P点流向负载的电流值ip和N点流回电容的电流值in的比值，调节上母线的电压upo和下母线的电压uon的比例，当电流值ip与 电流值in的比值越大，电压upo与电压uon的比值越小，即二者具有负相关性。
示例性地，基于第一电流值和第二电流值，调节三相电源变换电路的半母线的电压比例关系，具体如下公式(3)所示：
其中，upo为上半母线的电压，即电容C1的电压，uon为下半母线的电压，即电容C2的电压，kc为比例系数，ip为第一电流值，in为第二电流值。优选地，为了达到最佳的抑制效果，kc为1。
示例性地，半母线负载的运行功率值可以由中性点O流向负载的电流值io和上、下半母线的电压计算得到。
示例性地，全母线负载的运行功率值可以基于前述的第一电流值、第二电流值和全母线的电压upn计算得到，例如，如下公式(4)所示：
示例性地，P点流向负载的电流值ip、N点流出负载的电流值in和O点流向负载的电流值io可以由三相电流ia、ib、ic与三相开关管Sa、Sb、Sc的开通关断情况得到。
示例性地，还可以针对不同挂载方式，设置电压限制值，具体如下：
当全母线挂载、下半母线挂载时，控制上半母线的电压低于电压上限值Umax，避免上电容过压；控制下半母线的电压低于电压上限值Umax且高于电压下限值Umin，满足负载需求且避免下电容过压。
当全母线挂载、上半母线挂载时，控制上半母线的电压低于电压上限值Umax且高于电压下限值Umin，，满足负载需求且避免上电容过压；控制下半母线的电压低于电压上限值Umax，避免下电容过压；
当上半母线和下半母线均有挂载时，控制上半母线的电压低于电压上 限值Umax且高于电压下限值Umin1，控制下半母线的电压低于电压上限值Umax且高于电压下限值Umin2，避免上下电容的过压且满足上下负载的电压需求。
其中，对于电压限制值，电压上限值Umax由电容电压允许值和负载耐压值中的较小值决定，若没有接负载，则负载耐压值默认等于电容电压允许值；电压下限值Umin、Umin1和Umin2由负载的需求电压决定。例如，当全母线挂载、下半母线挂载时，下母线负载的需求电压为250V，则此时Umin取250V。
下面结合一应用示例对本申请实施例的控制方法进行举例说明。
本应用示例中，如图5所示，三相电源变换电路作为变频空调的供电单元，其中，压缩机负载由全母线供电，风机负载由下半母线供电。在全母线负载和半母线负载均工作时，控制下半母线的电压Uon低于上半母线的电压Upo；此外，还可以根据压缩机的运行功率值Ppn和风机的运行功率值Pon，控制电压Upo和电压Uon的比例，具体如下公式(5)所示：
其中，下半母线的电压Uon控制在Umax和Umin之间，Umax由电容电压允许值和风机IPM(智能功率模块)的耐压值中的较小值确定，避免过压损坏器件；Umin取风机的最大需求电压，即其在最大转速且最大功率时的需求电压。
为了实现本申请实施例的方法，本申请实施例还提供一种三相电源变换电路的控制装置，该三相电源变换电路的控制装置与上述控制方法对应，上述控制方法实施例中的各步骤也完全适用于本三相电源变换电路的控制装置实施例。
如图6所示，该三相电源变换电路的控制装置包括：获取模块601和电压调节模块602。获取模块601配置为获取所述全母线负载和所述半母线 负载各自的运行功率值；电压调节模块602配置为基于获取的所述运行功率值，调节所述三相电源变换电路的半母线的电压大小关系；其中，所述三相电源变换电路的正母线、负母线之间串联两级电解电容，所述全母线负载为连接于所述正母线与所述负母线之间的负载，所述半母线负载为连接于所述两级电解电容中任一个电容两端的负载，所述半母线包括：所述两级电解电容的中点与所述正母线之间的上半母线和所述两级电解电容的中点与所述负母线之间的下半母线。
在一些实施例中，所述半母线负载分为对应于所述上半母线的第一负载和对应于所述下半母线的第二负载，电压调节模块602调节所述三相电源变换电路的半母线的电压大小关系，包括：
若确定所述第一负载的运行功率值等于所述第二负载的运行功率值，则控制所述上半母线的电压和所述下半母线的电压相等；
若确定所述第一负载的运行功率值大于所述第二负载的运行功率值，则控制所述上半母线的电压小于所述下半母线的电压；
若确定所述第一负载的运行功率值小于所述第二负载的运行功率值，则控制所述上半母线的电压大于所述下半母线的电压。
在一些实施例中，电压调节模块602还配置为：
基于获取的所述运行功率值，调节所述三相电源变换电路的半母线的电压比例关系。
在一些实施例中，电压调节模块602调节所述三相电源变换电路的半母线的电压比例关系，包括：
基于所述全母线负载的运行功率值、所述第一负载的运行功率值及所述第二负载的运行功率值，确定所述上半母线与所述下半母线之间的电压比例关系。
在一些实施例中，若所述三相电源变换电路的半母线负载为所述第一 负载和所述第二负载中的一种，电压调节模块602调节所述三相电源变换电路的半母线的电压比例关系，包括：
基于所述全母线负载的运行功率值与相应的所述半母线负载的运行功率值，确定供电给相应的所述半母线负载的半母线与所述三相电源变换电路的全母线之间的电压比例关系。
在一些实施例中，获取模块601还配置为获取第一电流值和第二电流值；电压调节模块602还配置为基于所述第一电流值与所述第二电流值的比例关系，调节所述三相电源变换电路的半母线的电压比例关系；其中，所述第一电流值为所述两级电解电容相应于所述正母线的交点流出的电流值，所述第二电流值为所述两级电解电容相应于所述负母线的交点回流的电流值。
在一些实施例中，电压调节模块602调节所述三相电源变换电路的半母线的电压比例关系，包括：控制所述上半母线与所述下半母线之间的电压比例关系和所述第一电流值与所述第二电流值的比值呈负相关性。
实际应用时，获取模块601和电压调节模块602，可以由处理器来实现。当然，处理器需要运行存储器中的计算机程序来实现它的功能。
需要说明的是：上述实施例提供的三相电源变换电路的控制装置在进行控制时，仅以上述各程序模块的划分进行举例说明，实际应用中，可以根据需要而将上述处理分配由不同的程序模块完成，即将装置的内部结构划分成不同的程序模块，以完成以上描述的全部或者部分处理。另外，上述实施例提供的三相电源变换电路的控制装置与前述的控制方法实施例属于同一构思，其具体实现过程详见方法实施例，这里不再赘述。
基于上述程序模块的硬件实现，且为了实现本申请实施例的方法，本申请实施例还提供一种三相电源变换电路的控制设备。图7仅仅示出了该控制设备的示例性结构而非全部结构，根据需要可以实施图7示出的部分 结构或全部结构。
如图7所示，本申请实施例提供的控制设备700包括：至少一个处理器701、存储器702和用户接口703。控制设备700中的各个组件通过总线系统704耦合在一起。可以理解，总线系统704用于实现这些组件之间的连接通信。总线系统704除包括数据总线之外，还包括电源总线、控制总线和状态信号总线。但是为了清楚说明起见，在图7中将各种总线都标为总线系统704。
其中，用户接口703可以包括显示器、键盘、鼠标、轨迹球、点击轮、按键、按钮、触感板或者触摸屏等。
本申请实施例中的存储器702用于存储各种类型的数据以支持控制设备的操作。这些数据的示例包括：用于在控制设备上操作的任何计算机程序。
本申请实施例揭示的控制设备的控制方法可以应用于处理器701中，或者由处理器701实现。处理器701可能是一种集成电路芯片，具有信号的处理能力。在实现过程中，控制设备的控制方法的各步骤可以通过处理器701中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器701可以是通用处理器、数字信号处理器(DSP，Digital Signal Processor)，或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。处理器701可以实现或者执行本申请实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者任何常规的处理器等。结合本申请实施例所公开的方法的步骤，可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于存储介质中，该存储介质位于存储器702，处理器701读取存储器702中的信息，结合其硬件完成本申请实施例提供的控制设备的控制方法的步骤。
在示例性实施例中，控制设备可以被一个或多个应用专用集成电路 (ASIC，Application Specific Integrated Circuit)、DSP、可编程逻辑器件(PLD，Programmable Logic Device)、复杂可编程逻辑器件(CPLD，Complex Programmable Logic Device)、现场可编程逻辑门阵列(FPGA，Field Programmable Gate Array)、通用处理器、控制器、微控制器(MCU，Micro Controller Unit)、微处理器(Microprocessor)、或者其他电子元件实现，用于执行前述方法。
可以理解，存储器702可以是易失性存储器或非易失性存储器，也可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(ROM，Read Only Memory)、可编程只读存储器(PROM，Programmable Read-Only Memory)、可擦除可编程只读存储器(EPROM，Erasable Programmable Read-Only Memory)、电可擦除可编程只读存储器(EEPROM，Electrically Erasable Programmable Read-Only Memory)、磁性随机存取存储器(FRAM，ferromagnetic random access memory)、快闪存储器(Flash Memory)、磁表面存储器、光盘、或只读光盘(CD-ROM，Compact Disc Read-Only Memory)；磁表面存储器可以是磁盘存储器或磁带存储器。易失性存储器可以是随机存取存储器(RAM，Random Access Memory)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(SRAM，Static Random Access Memory)、同步静态随机存取存储器(SSRAM，Synchronous Static Random Access Memory)、动态随机存取存储器(DRAM，Dynamic Random Access Memory)、同步动态随机存取存储器(SDRAM，Synchronous Dynamic Random Access Memory)、双倍数据速率同步动态随机存取存储器(DDRSDRAM，Double Data Rate Synchronous Dynamic Random Access Memory)、增强型同步动态随机存取存储器(ESDRAM，Enhanced Synchronous Dynamic Random Access Memory)、同步连接动态随机存取存储器(SLDRAM，SyncLink Dynamic  Random Access Memory)、直接内存总线随机存取存储器(DRRAM，Direct Rambus Random Access Memory)。本申请实施例描述的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
在示例性实施例中，本申请实施例还提供了一种存储介质，即计算机存储介质，具体可以是计算机可读存储介质，例如包括存储计算机程序的存储器702，上述计算机程序可由控制设备的处理器701执行，以完成本申请实施例方法所述的步骤。计算机可读存储介质可以是ROM、PROM、EPROM、EEPROM、Flash Memory、磁表面存储器、光盘、或CD-ROM等存储器。
需要说明的是：“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
另外，本申请实施例所记载的技术方案之间，在不冲突的情况下，可以任意组合。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请披露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (10)

  1. 一种三相电源变换电路的控制方法，所述三相电源变换电路连接全母线负载和半母线负载，所述方法包括：
    获取所述全母线负载和所述半母线负载各自的运行功率值；
    基于获取的所述运行功率值，调节所述三相电源变换电路的半母线的电压大小关系；
    其中，所述三相电源变换电路的正母线、负母线之间串联两级电解电容，所述全母线负载为连接于所述正母线与所述负母线之间的负载，所述半母线负载为连接于所述两级电解电容中任一个电容两端的负载，所述半母线包括：所述两级电解电容的中点与所述正母线之间的上半母线和所述两级电解电容的中点与所述负母线之间的下半母线。
  2. 根据权利要求1所述的方法，其中，所述半母线负载分为对应于所述上半母线的第一负载和对应于所述下半母线的第二负载，所述基于获取的所述运行功率值，调节所述三相电源变换电路的半母线的电压大小关系，包括：
    若确定所述第一负载的运行功率值等于所述第二负载的运行功率值，则控制所述上半母线的电压和所述下半母线的电压相等；
    若确定所述第一负载的运行功率值大于所述第二负载的运行功率值，则控制所述上半母线的电压小于所述下半母线的电压；
    若确定所述第一负载的运行功率值小于所述第二负载的运行功率值，则控制所述上半母线的电压大于所述下半母线的电压。
  3. 根据权利要求2所述的方法，其中，所述方法还包括：
    基于获取的所述运行功率值，调节所述三相电源变换电路的半母线的电压比例关系。
  4. 根据权利要求3所述的方法，其中，所述调节所述三相电源变换电路的半母线的电压比例关系，包括：
    基于所述全母线负载的运行功率值、所述第一负载的运行功率值及所述第二负载的运行功率值，确定所述上半母线与所述下半母线之间的电压比例关系。
  5. 根据权利要求3所述的方法，其中，若所述三相电源变换电路的半母线负载为所述第一负载和所述第二负载中的一种，所述调节所述三相电源变换电路的半母线的电压比例关系，包括：
    基于所述全母线负载的运行功率值与相应的所述半母线负载的运行功率值，确定供电给相应的所述半母线负载的半母线与所述三相电源变换电路的全母线之间的电压比例关系。
  6. 根据权利要求2所述的方法，其中，所述方法还包括：
    获取第一电流值和第二电流值；
    基于所述第一电流值与所述第二电流值的比例关系，调节所述三相电源变换电路的半母线的电压比例关系；
    其中，所述第一电流值为所述两级电解电容相应于所述正母线的交点流出的电流值，所述第二电流值为所述两级电解电容相应于所述负母线的交点回流的电流值。
  7. 根据权利要求6所述的方法，其中，所述调节所述三相电源变换电路的半母线的电压比例关系，包括：
    控制所述上半母线与所述下半母线之间的电压比例关系和所述第一电流值与所述第二电流值的比值呈负相关性。
  8. 一种三相电源变换电路的控制装置，所述三相电源变换电路连接全母线负载和半母线负载，所述控制装置包括：
    获取模块，配置为获取所述全母线负载和所述半母线负载各自的运行 功率值；
    电压调节模块，配置为基于获取的所述运行功率值，调节所述三相电源变换电路的半母线的电压大小关系；
    其中，所述三相电源变换电路的正母线、负母线之间串联两级电解电容，所述全母线负载为连接于所述正母线与所述负母线之间的负载，所述半母线负载为连接于所述两级电解电容中任一个电容两端的负载，所述半母线包括：所述两级电解电容的中点与所述正母线之间的上半母线和所述两级电解电容的中点与所述负母线之间的下半母线。
  9. 一种三相电源变换电路的控制设备，包括：处理器和用于存储能够在处理器上运行的计算机程序的存储器，其中，
    所述处理器，配置为运行计算机程序时，执行权利要求1至7任一项所述方法的步骤。
  10. 一种存储介质，所述存储介质上存储有计算机程序，所述计算机程序被处理器执行时，实现权利要求1至7任一项所述方法的步骤。
PCT/CN2023/097374 2022-10-25 2023-05-31 三相电源变换电路的控制方法、装置、设备和存储介质 WO2024087629A1 (zh)

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CN103236786A (zh) * 2013-04-17 2013-08-07 华为技术有限公司 一种均压电路及逆变器
JP2016021824A (ja) * 2014-07-15 2016-02-04 ダイキン工業株式会社 電源装置
CN110612658A (zh) * 2017-01-12 2019-12-24 雷诺股份公司 双向蓄电电池组的充电器
CN212305171U (zh) * 2020-09-30 2021-01-05 重庆美的制冷设备有限公司 电子电路和空调器
CN112436779A (zh) * 2020-10-21 2021-03-02 华为技术有限公司 一种电驱动系统、动力总成以及电动汽车
CN113794376A (zh) * 2021-09-29 2021-12-14 阳光电源股份有限公司 一种对称三电平Boost电路及其控制方法

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CN103236786A (zh) * 2013-04-17 2013-08-07 华为技术有限公司 一种均压电路及逆变器
JP2016021824A (ja) * 2014-07-15 2016-02-04 ダイキン工業株式会社 電源装置
CN110612658A (zh) * 2017-01-12 2019-12-24 雷诺股份公司 双向蓄电电池组的充电器
CN212305171U (zh) * 2020-09-30 2021-01-05 重庆美的制冷设备有限公司 电子电路和空调器
CN112436779A (zh) * 2020-10-21 2021-03-02 华为技术有限公司 一种电驱动系统、动力总成以及电动汽车
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