WO2024087198A1 - 一种显示面板及显示装置 - Google Patents

一种显示面板及显示装置 Download PDF

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Publication number
WO2024087198A1
WO2024087198A1 PCT/CN2022/128358 CN2022128358W WO2024087198A1 WO 2024087198 A1 WO2024087198 A1 WO 2024087198A1 CN 2022128358 W CN2022128358 W CN 2022128358W WO 2024087198 A1 WO2024087198 A1 WO 2024087198A1
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WIPO (PCT)
Prior art keywords
orthographic projection
electrode
active
base substrate
substrate
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PCT/CN2022/128358
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English (en)
French (fr)
Inventor
王佩佩
边若梅
张勇
王建
毕谣
金红贵
段智龙
刘洋
周久磊
张冬华
杨越
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to PCT/CN2022/128358 priority Critical patent/WO2024087198A1/zh
Publication of WO2024087198A1 publication Critical patent/WO2024087198A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel and a display device.
  • LCD display products have shown a diversification trend, and wearable products have derived low-frequency and low-power consumption requirements.
  • the use of low refresh rates will cause the display panel to have the risk of jitter and flicker.
  • the purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and provide a display panel and a display device.
  • a display panel comprising a plurality of pixel driving circuits arrayed along a first direction and a second direction, the pixel driving circuit comprising a driving transistor, the gate of the driving transistor being connected to a gate signal line, the first direction intersecting with the second direction; the display panel further comprising: a substrate; a first conductive layer located on one side of the substrate, the first conductive layer comprising: a plurality of gate signal lines, the gate signal line comprising a main body and a plurality of additional parts, the main body extending along the first direction in the orthographic projection of the substrate, the plurality of additional parts being spaced apart in the first direction and connected to one side of the main body in the second direction, the additional parts being used to form the gate of the driving transistor; an active layer located on a side of the first conductive layer away from the substrate, the active layer comprising: a plurality of active structures arranged corresponding to the plurality of additional parts, the plurality of active structures being separated
  • the multiple active portions include a first active portion and a second active portion, and the first active portion and the second active portion are spaced apart in the first direction; wherein the orthographic projection of the additional portion on the base substrate covers the orthographic projection of the first active portion and the orthographic projection of the second active portion on the base substrate corresponding to the additional portion.
  • the first electrode of the driving transistor is connected to the pixel electrode; the first direction is the row direction, and the second direction is the column direction; the display panel further includes: a second conductive layer, which is located on the side of the active layer away from the base substrate, and the second conductive layer includes: a plurality of first electrode structures, which correspond to the plurality of additional portions one by one, and the first electrode structure is used to form the pixel electrode; wherein the plurality of pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit, the first pixel driving circuit and the second pixel driving circuit are alternately distributed in the row direction, and the first pixel driving circuit is located in the same column, and the second pixel driving circuit is located in the same column; the gate signal line in the first pixel driving circuit is a first gate signal line, and the gate signal line in the second pixel driving circuit is a second gate signal line; the orthographic projections of the first gate signal line and the second gate signal line in this row on the base
  • an orthographic projection of the added portion on the base substrate covers an orthographic projection of the active structure corresponding thereto on the base substrate.
  • a distance between an edge of an orthographic projection of the active structure on the base substrate and an edge of an orthographic projection of the added portion on the base substrate is greater than or equal to 2.5 ⁇ m.
  • the main body portion has a first side edge and a second side edge opposite to each other in a column direction on the orthographic projection of the base substrate, the first side edge is located on a side of the second side edge away from the orthographic projection of the corresponding first electrode structure on the base substrate, and a first distance exists between the first side edge and the second side edge;
  • the first electrode structure has a second distance between the orthographic projection of the base substrate and the second side edge corresponding thereto, the second distance is greater than or equal to 2.5 ⁇ m, and the first distance is greater than the second distance.
  • the pixel driving circuit also includes a storage capacitor, a first electrode of the storage capacitor is connected to the pixel electrode, and a second electrode is connected to the common electrode;
  • the display panel also includes: a fourth conductive layer, located on the side of the second conductive layer away from the base substrate, the fourth conductive layer includes: a plurality of second electrode structures, each of the second electrode structures is connected to each other to form a grid structure, the orthographic projection of the second electrode structure on the base substrate partially overlaps with the orthographic projection of the first electrode structure on the base substrate; wherein the first electrode structure is also used to form the first electrode of the storage capacitor, and the second electrode structure is also used to form the second electrode of the storage capacitor.
  • the first electrode structure includes a first electrode portion and a second electrode portion, and an extension direction of the first electrode portion intersects with an extension direction of the second electrode portion; the extension direction of the first electrode portion has a first angle with the column direction, and the extension direction of the second electrode portion has a second angle with the column direction, the first angle is the same as the second angle, and the extension lengths of the first electrode portion and the second electrode portion are the same, and are connected to the first bending portion.
  • the first conductive layer also includes: a first conductive line, the orthographic projection of which on the base substrate extends along the row direction, the first conductive line connects the second electrode structure, and the orthographic projection of the first conductive line on the base substrate at least partially overlaps with the orthographic projection of the first bend on the base substrate.
  • an orthographic projection of the first conductive line on the base substrate covers an orthographic projection of the first bending portion on the base substrate.
  • the orthographic projection of the first conductive line on the substrate substrate has a third side and a fourth side relative to each other in a column direction, and the third side and the fourth side have a first width in the column direction;
  • the orthographic projection of the first electrode structure on the substrate substrate has a fifth side and a sixth side relative to each other in the column direction, and the fifth side and the sixth side have a second width in the column direction;
  • the ratio of the first width to the second width is 0.05 to 0.06.
  • the display panel includes a plurality of repeating units, and the repeating unit includes the first pixel driving circuit and the second pixel driving circuit adjacent to each other in a row direction;
  • the first conductive layer also includes: a second conductive line, the orthographic projection of which on the base substrate extends along the row direction, and the second conductive line connects the second electrode structure; a third conductive line, the orthographic projection of which on the base substrate extends along the row direction, and the third conductive line connects the second electrode structure; wherein, in the same repeating unit, the second conductive line and the third conductive line are located between the first gate signal line and the second gate signal line, the orthographic projection of the second conductive line on the base substrate intersects with the orthographic projection of one end of the first electrode portion away from the first bending portion on the base substrate; the orthographic projection of the third conductive line on the base substrate intersects with the orthographic projection of one end of the second electrode portion away from the first bending portion on the base substrate.
  • the orthographic projections of the second conductive line and the third conductive line on the substrate have a seventh side and an eighth side opposite to each other in a column direction, and the seventh side and the eighth side have a third width in the column direction;
  • the orthographic projection of the first electrode structure on the substrate has a fifth side and a sixth side opposite to each other in the column direction, and the fifth side and the sixth side have a second width in the column direction;
  • the ratio of the third width to the second width is 0.05 to 0.06.
  • the orthographic projection of the first electrode structure in the same repeating unit on the substrate substrate and the orthographic projection of the second electrode structure on the substrate substrate have a second overlapping area S2; in any two adjacent repeating units in the row direction, the orthographic projection of the first electrode structure in the first pixel driving circuit on the substrate substrate and the orthographic projection of the first electrode in the second pixel driving circuit in the adjacent repeating unit on the substrate substrate have a sixth distance in the horizontal direction.
  • the display panel also includes: a third conductive layer, located on the side of the second conductive layer away from the base substrate, the third conductive layer includes: a virtual signal line, extending in the column direction in the orthographic projection of the base substrate, and located between the orthographic projections of two adjacent repeating units in the row direction on the base substrate; wherein, in the same repeating unit, the orthographic projection of the first electrode structure on the base substrate and the orthographic projection of the second electrode structure on the base substrate have a first overlapping area S1, and the first overlapping area is smaller than the second overlapping area S2; the first electrode structure in the first pixel driving circuit has a fifth distance in the row direction between the orthographic projection of the base substrate and the first electrode structure in the second pixel driving circuit in the adjacent repeating unit in the row direction on the base substrate, and the fifth distance is greater than the sixth distance.
  • a third conductive layer located on the side of the second conductive layer away from the base substrate, the third conductive layer includes: a virtual signal line, extending in the column direction
  • a ratio of the second overlapping area to the first overlapping area is 0.77 to 0.79.
  • the first electrode of the driving transistor is connected to the data signal terminal;
  • the active structure further includes: a first sub-active portion, which is arranged corresponding to the first active portion and connected to one side of the first active portion, and the first sub-active portion is used to form the first electrode of the driving transistor;
  • a second sub-active portion which is arranged corresponding to the second active portion and connected to a side of the second active portion away from the first active portion, and the second sub-active portion is used to form the second electrode of the driving transistor;
  • a third sub-active portion which is connected between the first active portion and the second active portion corresponding to it;
  • the display panel further includes: a third conductive layer, which is located on the side of the second conductive layer away from the base substrate, and the third conductive layer It includes: a first conductive part, whose orthographic projection on the base substrate covers the orthographic projection of the first sub-active part on the base substrate, and the first conductive part is electrically connected to the first sub-active part to connect the
  • the third conductive layer also includes: a data signal line, which extends along the column direction in the orthographic projection of the base substrate, and the data signal line is connected to the first conductive portion to connect the first electrode of the driving transistor; wherein the display panel includes a plurality of repeating units, and the repeating unit includes the first pixel driving circuit and the second pixel driving circuit adjacent to each other in the row direction; the first pixel driving circuit in the repeating unit of this row and the second pixel driving circuit in the repeating unit of the previous row reuse the same data signal line.
  • the second conductive layer further includes: a spare conductive portion, located between the adjacent first pixel driving circuit and the second pixel driving circuit; wherein the orthographic projection of the spare conductive portion on the base substrate is located within the orthographic projection of the corresponding data signal line on the base substrate.
  • a display device comprising the display panel described in any embodiment of the present disclosure.
  • the display panel provided by the present disclosure has an additional portion of the gate signal line protruding from one side of the main body in the second direction, and is used to form the gate of the driving transistor, so that the gate of the driving transistor is an integral structure.
  • Multiple active portions are used to form the gate of the driving transistor, and the positive projection of the additional portion on the substrate covers the positive projection of the corresponding multiple active portions on the substrate, so that the driving transistor forms a multi-gate structure.
  • the driving transistor of the present disclosure is a multi-gate structure and the multiple gates are an integrated structure.
  • the driving transistor can improve the ability to suppress off-state leakage current, thereby reducing the off-state leakage current of the driving transistor, thereby reducing the screen flickering phenomenon of the display panel when driven at a low frequency.
  • the gate of the driving transistor of the present disclosure is an integral multi-gate structure, which can further improve the ability to suppress off-state leakage current compared to the multi-gate structure with gate separation in the prior art, and has a better effect on reducing the screen flickering phenomenon of the display panel under low-frequency driving.
  • FIG1 is a schematic diagram of a circuit structure of a pixel driving circuit according to an embodiment of the present disclosure
  • FIG2 is a structural diagram of a display panel according to one embodiment of the present disclosure.
  • FIG3 is a structural diagram of the first conductive layer in FIG2 ;
  • FIG4 is a structural diagram of the active layer in FIG2 ;
  • FIG5 is a stacking layout of the first conductive layer and the active layer
  • FIG6 is a structural diagram of the second conductive layer in FIG2 ;
  • FIG7 is a structural diagram of the third conductive layer in FIG2;
  • FIG8 is a structural diagram of the fourth conductive layer in FIG2;
  • FIG9 is a schematic diagram of a structure in which the first conductive layer and the active layer overlap in the row direction;
  • FIG10 is a schematic structural diagram of the complete first electrode structure in FIG2 ;
  • FIG11a is a schematic structural diagram of a complete second electrode structure in FIG2 ;
  • FIG11b is a stacking layout of the first conductive layer and the third conductive layer
  • FIG12 is a structural diagram of a display panel according to another embodiment of the present disclosure.
  • FIG13 is a structural layout diagram of the first conductive layer in FIG12;
  • FIG14 is a stacking layout of a first conductive layer and a second conductive layer
  • FIG15 is a structural diagram of a display panel according to another embodiment of the present disclosure.
  • FIG16a is a structural layout diagram of the first conductive layer in FIG15;
  • FIG16 b is a structural layout diagram of a repeating unit of the first conductive layer in FIG15 ;
  • FIG17 is a stacking layout of a first conductive layer and a second conductive layer
  • FIG18 is a structural layout diagram of the third conductive layer in FIG12;
  • FIG. 19 is a structural layout diagram of the third conductive layer in FIG. 15 .
  • a transistor is an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • the channel region refers to the region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the "source electrode” and the “drain electrode” may be interchanged.
  • LCD display products are showing a diversified trend, and different products are seeking performance improvements.
  • Wearable products such as smart watches and bracelets, are becoming more and more lightweight and convenient, so low power consumption has become the direction of their performance improvement.
  • the display industry has introduced low-frequency and low-power solutions, taking into account the characteristics of its display needs, to achieve low power consumption by reducing the screen refresh frequency.
  • the brightness of the pixel changes with the change of frames, which makes the human eye feel flicker.
  • the leakage of the pixel electrode Vpixel increases, and the screen flicker will be aggravated.
  • the brightness of the pixel changes with the change of frames, which makes the human eye feel flicker.
  • ⁇ Vp is the value changed by the capacitive coupling effect of the pixel electrode due to the opening or closing of Gate/Data
  • Cgs is the capacitance between the TFT gate and the pixel electrode
  • Cst is the capacitance between the common electrode and the pixel electrode
  • Clc is the liquid crystal capacitance
  • VGH and VGL are the opening and closing voltages of the TFT respectively.
  • ⁇ Vp leakage is related to Ioff, frame rate fframe and Cst.
  • Ioff decreases
  • ⁇ Vp leakage decreases
  • frame rate fframe decreases
  • ⁇ Vp leakage increases
  • Cst increases
  • ⁇ Vp leakage decreases.
  • the inventor proposes a technical solution to solve the screen flicker problem under low-frequency driving by increasing the storage capacitor and reducing the off-state leakage current.
  • the technical solution disclosed in this disclosure is specifically introduced below with reference to the accompanying drawings.
  • the pixel driving circuit may include a driving transistor T and a storage capacitor Cst, wherein the gate of the driving transistor T is connected to the gate driving signal terminal Gate, the first electrode is connected to the data signal terminal Vdata, and the second electrode is connected to the pixel electrode Vpixel.
  • the first electrode of the storage capacitor Cst is connected to the pixel electrode Vpixel, and the second electrode is connected to the common electrode Vcom.
  • FIG. 2 is a structural layout of a display panel according to the embodiment of the present disclosure.
  • FIG. 3 is a structural layout of a first conductive layer in FIG. 2 .
  • FIG. 4 is a structural layout of an active layer in FIG. 2 .
  • FIG. 5 is a stacked layout of the first conductive layer and the active layer.
  • the display panel includes a plurality of pixel driving circuits distributed in an array along a first direction X and a second direction Y.
  • the pixel driving circuit is used to drive a light-emitting device to emit light.
  • the light-emitting device may be, for example, a liquid crystal.
  • the display panel described in the present disclosure may be a liquid crystal display panel.
  • the first direction X intersects with the second direction Y.
  • the display panel may further include: a base substrate, a first conductive layer 1 and an active layer 2, wherein the first conductive layer 1 is located on one side of the base substrate, the first conductive layer 1 may include a plurality of gate signal lines Gate, the gate signal line Gate includes a main portion G0 and a plurality of additional portions G1, the orthographic projection of the main portion G0 on the base substrate extends along a first direction X, the plurality of additional portions G1 are spaced apart in the first direction X and connected to one side of the main portion G0 in a second direction Y, the additional portion G1 is used to form a gate of the driving transistor T; the active layer 2 is located on one side of the first conductive layer 1, the active layer 2 may include a plurality of active structures AC, the orthographic projections of the plurality of active structures AC on the base substrate are separated from each other, the active structure AC
  • the additional portion G1 of the gate signal line Gate protrudes from one side of the main body G0 in the second direction Y, and is used to form the gate of the driving transistor T, so that the gate of the driving transistor T is an integral structure.
  • Multiple active portions are used to form the gate of the driving transistor T, and the positive projection of the additional portion G1 on the substrate covers the positive projection of the corresponding multiple active portions on the substrate, so that the driving transistor T forms a multi-gate structure.
  • the driving transistor T of the present disclosure is a multi-gate structure and the multiple gates are an integrated structure.
  • the ability of the driving transistor T to suppress the off-state leakage current can be improved, thereby reducing the off-state leakage current of the driving transistor T, thereby reducing the screen flickering phenomenon of the display panel when driven at a low frequency.
  • the gate of the driving transistor T of the present disclosure is an integral multi-gate structure, which can further improve the ability to suppress the off-state leakage current compared to the multi-gate structure with gate separation in the prior art, and has a better effect on reducing the screen flickering phenomenon of the display panel under low-frequency driving.
  • the first direction X may be a row direction
  • the second direction Y may be a column direction
  • the active layer 2 of the present disclosure may be located on the side of the first conductive layer 1 away from the substrate 1 to form a driving transistor T with a bottom gate structure; or the active layer 2 may also be located between the first conductive layer 1 and the substrate to form a driving transistor T with a top gate structure.
  • the present disclosure is only exemplified by taking the bottom gate structure as an example, which should not be understood as limiting the present disclosure.
  • the gate signal line Gate can be used to provide the gate driving signal terminal Gate in FIG. 1 , the main body G0 of the gate signal line Gate extends along the first direction X in the orthographic projection of the base substrate, the additional portion G1 of the gate signal line Gate is located on one side of the main body G0 in the second direction Y, and each additional portion G1 on the same gate signal line Gate can be located on the same side of the main body G0 in the second direction Y.
  • the additional portion G1 of the gate signal line Gate can be used to form the gate of the driving transistor T.
  • a described in the present disclosure extends along the C direction, which means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along the C direction, and the length of the main part extending along the C direction is greater than the length of the secondary part extending along other directions.
  • One active structure AC includes multiple active parts independent of each other, and the active parts are used to form the channel region of the driving transistor T, so that one active structure AC forms multiple channel regions of the driving transistor T.
  • orthographic projections of a certain structure A and another structure B described in the present disclosure on the substrate are separated from each other, indicating that there is no overlapping area between the orthographic projection of structure A on the substrate and the orthographic projection of structure B on the substrate, that is, structure A and structure B are independent structures.
  • the orthographic projection of the additional part G1 of the present disclosure on the base substrate covers the orthographic projection of the active part on the base substrate.
  • the additional part G1 may include multiple substructures, and each substructure corresponds to each active part one by one.
  • the orthographic projection of the substructure on the base substrate can cover the orthographic projection of the corresponding active part on the base substrate. Accordingly, the substructure of the additional part G1 forms the gate of the driving transistor T. Therefore, the orthographic projection of one additional part G1 on the base substrate covers the orthographic projections of multiple corresponding active parts on the base substrate, indicating that one additional part G1 forms multiple gates of the driving transistor T, and further, the additional part G1 of an integral structure forms multiple gates of the driving transistor T.
  • the present disclosure increases the channel length of the driving transistor T by forming the driving transistor T into a multi-gate structure, thereby reducing the off-state leakage current of the driving transistor T.
  • the present disclosure increases the channel length L of the driving transistor T by forming a driving transistor with a multi-gate structure, thereby reducing the off-state leakage current of the driving transistor T, thereby reducing the flicker and jitter phenomenon of the display panel when driven at a low frequency.
  • orthographic projection of a certain structure A on the substrate described in the present disclosure covers the orthographic projection of another structure B on the substrate, which can be understood as the outline of the projection of B on the plane of the substrate is completely inside the outline of the projection of A in the same plane.
  • the plurality of active parts may include a plurality of first active parts AC1 and a plurality of second active parts AC2, and the first active parts AC1 and the second active parts AC2 are arranged at intervals in the first direction X; wherein, one additional part G1 corresponds to one first active part AC1 and one second active part AC2, and the orthographic projection of the additional part G1 on the substrate covers the orthographic projection of the first active part AC1 and the orthographic projection of the second active part AC2 on the substrate corresponding to it.
  • an active structure AC includes the first active part AC1 and the second active part AC2, that is, an active structure AC includes two channel regions.
  • the first active part AC1 and the second active part AC2 are arranged at intervals in the first direction X, that is, the first active part AC1 and the second active part AC2 are arranged separately in the first direction X.
  • One additional portion G1 corresponds to one first active portion AC1 and one second active portion AC2, that is, one additional portion G1 corresponds to two channel regions, that is, one additional portion G1 forms two gates of the driving transistor T, that is, the transistor in this exemplary embodiment is a dual-gate structure, and there is no hollow structure between the two gates.
  • the present disclosure improves the channel length of the driving transistor T by forming a dual-gate structure.
  • the driving transistor T of the present disclosure has a dual-gate structure, which can further improve the ability of the driving transistor T to suppress the off-state leakage current, that is, it is conducive to further reducing the low-frequency driving jitter problem of the display panel.
  • Table 1 shows a simulation comparison result of the present disclosure.
  • the driving transistor T of the dual-gate structure of the present disclosure can reduce the off-state leakage current to 1.43pA, which is significantly less than the off-state leakage current of the driving transistor T of the driving single-gate structure with a small channel length.
  • the off-state leakage current of the driving transistor T of the single-gate structure is 1.53pA, which is significantly greater than the off-state leakage current of the driving transistor T of the dual-gate structure in the present disclosure.
  • the structure of increasing the channel length of the driving transistor T by forming a dual-gate structure can further improve the ability to suppress the off-state leakage current, that is, it can further reduce the off-state leakage current of the driving transistor T, thereby further reducing the screen jitter phenomenon.
  • the orthographic projection of the additional portion G1 on the substrate can cover the orthographic projection of the corresponding active structure AC on the substrate. That is, the orthographic projection of the active structure AC on the substrate is completely located within the orthographic projection of the corresponding additional portion G1 on the substrate. In other words, the edge of the orthographic projection of the additional portion G1 on the substrate must exceed the edge of the orthographic projection of the corresponding active structure AC on the substrate by a certain distance.
  • the distance between the edge of the orthographic projection of the active structure AC on the substrate and the edge of the orthographic projection of the additional portion G1 on the substrate can be greater than or equal to 2.5 ⁇ m, for example, 2.5 ⁇ m, 2.6 ⁇ m, 2.7 ⁇ m, 2.8 ⁇ m, etc.
  • the gate signal line Gate can completely block the incident light on the light-entering side, and can block the incident light from irradiating the active structure AC, thereby avoiding the interference of light on the active structure AC.
  • the orthographic projections of the additional part G1 and the active structure AC on the substrate can be rectangular, and the distance between the edge of the orthographic projection of the active structure AC on the substrate and the edge of the orthographic projection of the additional part G1 on the substrate can be understood as the distance between the side of the rectangle formed by the orthographic projection of the active structure AC on the substrate and the side of the rectangle formed by the orthographic projection of the additional part G1 on the substrate wrapped around the active structure AC on the substrate in the row direction or column direction.
  • the orthographic projections of the active structure AC and the additional part G1 on the substrate can also be other structures, such as a circle, an ellipse, etc.
  • the edge of the orthographic projection of the active structure AC on the substrate is composed of a plurality of discrete nodes, and the line connecting any node K and the center of the active structure AC on the substrate forms an intersection M with the edge of the orthographic projection of the additional part G1 on the substrate, and the distance between the node K and the intersection M is the distance between the edge of the orthographic projection of the active structure AC on the substrate and the edge of the orthographic projection of the additional part G1 on the substrate.
  • the active structure AC may include a conductor portion after conductorization and a semiconductor portion (active portion) that has not been conductorized, wherein the semiconductor portion is used to form a channel region of a transistor, and the conductor portion may be used, for example, to connect the source and drain electrodes of the transistor.
  • the active structure AC in the active layer 2 may also include a first sub-active portion AC-1, a second sub-active portion AC-2, and a third sub-active portion AC-3, wherein the first sub-active portion AC-1 is arranged corresponding to the first active portion AC1 and connected to one side of the first active portion AC1, and the first sub-active portion AC-1 may be used to form a first pole of the driving transistor T.
  • the second sub-active portion AC-2 is arranged corresponding to the second active portion AC2 and connected to a side of the second active portion AC2 away from the first active portion AC1, and the second sub-active portion AC-2 may be used to form a second pole of the driving transistor T, and the third sub-active portion AC-3 is connected between the first active portion AC1 and the second active portion AC2 corresponding thereto.
  • the first sub-active portion AC-1 to the third sub-active portion AC-3 can be conductorized, so that the first sub-active portion AC-1 to the third sub-active portion AC-3 are all conductor structures.
  • the driving transistor of the present disclosure is a dual-gate structure, which is equivalent to two transistors, and the two transistors are connected through the conductorized third sub-active portion AC-3.
  • the third sub-active portion AC-3 serves as both the first pole of one of the transistors and the second pole of the other transistor.
  • the display panel of the present disclosure may also include a second conductive layer 3, a third conductive layer 4 and a fourth conductive layer 5.
  • the first conductive layer 1, the active layer 2, the second conductive layer 3, the third conductive layer 4 and the fourth conductive layer 5 are sequentially stacked on one side of the substrate.
  • An insulating layer may be provided between the above functional layers.
  • a gate insulating layer may be provided between the first conductive layer 1 and the active layer 2.
  • FIG6 is a structural layout diagram of the second conductive layer in FIG2
  • FIG7 is a structural layout diagram of the third conductive layer in FIG2
  • FIG8 is a structural layout diagram of the fourth conductive layer in FIG2
  • FIG9 is a schematic diagram of the structure in which the first conductive layer and the active layer overlap in the row direction.
  • the second conductive layer 3 may include a plurality of first electrode structures Pix, and the first electrode structures Pix are arranged in a one-to-one correspondence with the additional portions G1, that is, one additional portion G1 corresponds to one first electrode structure Pix, and the first electrode structure Pix may be used to form a pixel electrode Vpixel and a first electrode of a storage capacitor Cst.
  • the first electrode structure Pix may be an electrode block, and exemplarily, FIG10 is a schematic structural diagram of a complete first electrode structure in FIG2 , as shown in FIG10 , the first electrode structure Pix may include a first electrode portion Pix1 and a second electrode portion Pix2, and the extension direction of the first electrode portion Pix1 intersects with the extension direction of the second electrode portion Pix2, and the first electrode portion Pix1 and the second electrode portion Pix2 intersect at a first bending portion Pix3. As shown in FIG10 , the first electrode portion Pix1 and the second electrode portion Pix2 may both extend at a certain angle away from the column direction, so as to be connected at the first bending portion Pix3.
  • the extension direction of the first electrode portion Pix1 may have a first angle ⁇ with the column direction
  • the extension direction of the second electrode portion Pix2 may have a second angle ⁇ with the column direction
  • the first angle ⁇ may be the same as the second angle ⁇
  • the extension length of the first electrode portion Pix1 may be the same as the extension length of the second electrode portion Pix2, thereby making the first bending portion Pix3 located in the middle position of the first electrode structure Pix in the second direction Y, that is, the first electrode portion Pix1 and the second electrode portion Pix2 intersect at a bending portion Pix3 in the middle position of the first electrode structure Pix along the column direction.
  • the extension length of the first electrode portion Pix1 described in this exemplary embodiment is the same as the extension length of the second electrode portion Pix2, which can be the same as the extension length of the first electrode portion Pix1 and the extension length of the second electrode portion Pix2, or the extension length of the first electrode portion Pix1 and the extension length of the second electrode portion Pix2 are very close, for example, the ratio of the extension length of the first electrode portion Pix1 to the extension length of the second electrode portion Pix2 is between 0.8 and 1.2, or for example, the absolute value of the difference between the extension length of the first electrode portion Pix1 and the extension length of the second electrode portion Pix2 is within the set redundancy range, which can be considered that the extension length of the first electrode portion Pix1 is the same as the extension length of the second electrode portion Pix2.
  • the first electrode structure Pix can also be other structures, such as a slit electrode.
  • the second conductive layer 3 may further include a spare conductive portion 30, the spare conductive portion 30 being located between two adjacent first electrode structures Pix in the first direction X, that is, the spare conductive portion 30 is distributed in the gap between the two adjacent first electrode structures Pix in the first direction X, and the spare conductive portion 30 is separated from the first electrode structure Pix, that is, the spare conductive portion 30 and the first electrode structure Pix are not connected.
  • the spare conductive portion 30 may be arranged in a one-to-one correspondence with the data signal line Data of the third conductive layer 4, and the orthographic projection of the spare conductive portion 30 on the substrate may be the same as the extension direction of the orthographic projection of the data signal line Data on the substrate and at least partially overlap in the extension direction, for example, the orthographic projection of the data signal line Data on the substrate may cover the orthographic projection of the spare conductive portion 30 on the substrate.
  • the spare conductive part 30 can be connected to the data signal line Data of the third conductive layer 4 through a via, so that the spare conductive part 30 becomes a parallel structure of the data signal line Data.
  • the data signal can still be transmitted through the spare conductive part 30 connected thereto, so that the display panel will not be unusable due to the breakage of the data signal line Data, thereby improving the service life and reliability of the display panel to a certain extent.
  • a spare conductive portion 30 may also be provided at a position corresponding to the virtual signal line D-line.
  • the orthographic projection of the virtual signal line D-line on the substrate may cover the orthographic projection of the corresponding spare conductive portion 30 on the substrate.
  • the dummy signal line D-line may be connected to the common electrode line of the non-display area so that the dummy signal line D-line and the common electrode have the same potential.
  • a plurality of pixel driving circuits may include a first pixel driving circuit P1 and a second pixel driving circuit P2, the first pixel driving circuit P1 and the second pixel driving circuit P2 are alternately distributed in the row direction, and the first pixel driving circuit P1 is located in the same column, and the second pixel driving circuit P2 is located in the same column;
  • the gate signal line in the first pixel driving circuit P1 is the first gate signal line Gate1, and the gate signal line in the second pixel driving circuit P2 is the second gate signal line Gate2;
  • the orthographic projections of the first gate signal line Gate1 and the second gate signal line Gate2 of this row on the substrate are respectively located on both sides of the orthographic projection of the first electrode structure Pix of this row on the substrate in the column direction;
  • the additional portion in the first gate signal line Gate1 of this row is located on the side of the corresponding main body close to the second gate signal line Gate2 of the previous row, and the additional portion in the second gate signal line Gate2 of the
  • the third conductive layer 4 may include a data signal line Data, the orthographic projection of the data signal line Data on the substrate may extend along the second direction Y, and the data signal line Data may be used to provide the data signal terminal Vdata in FIG1 .
  • the third conductive layer 4 may also include a first conductive portion 31, a second conductive portion 32, and a third conductive portion 33, wherein the orthographic projection of the first conductive portion 31 on the substrate may cover the orthographic projection of the first sub-active portion AC-1 on the substrate, and the first conductive portion 31 is electrically connected to the first sub-active portion AC-1 to connect the first electrode of the driving transistor T.
  • the orthographic projection of the second conductive portion 32 on the substrate may cover the orthographic projection of the second sub-active portion AC-2 on the substrate, and the second conductive portion 32 is electrically connected to the second sub-active portion AC-2 to connect the second electrode of the driving transistor T.
  • the third conductive part 33 is arranged in one-to-one correspondence with the third sub-active part AC-3.
  • the third conductive part 33 is located between the first conductive part 31 and the second conductive part 32.
  • the orthographic projection of the third conductive part 33 on the substrate covers the orthographic projection of the corresponding third sub-active part AC-3 on the substrate, and the third conductive part 33 is not connected to the first conductive part 31 and the second conductive part 32.
  • the plurality of pixel driving circuits disclosed in the present invention may include a first pixel driving circuit P1 and a second pixel driving circuit P2, and the first pixel driving circuit P1 and the second pixel driving circuit P2 are sequentially spaced and distributed in the first direction X, that is, there is a second pixel driving circuit P2 between two adjacent first pixel driving circuits P1 in the first direction X, in other words, there is a first pixel driving circuit P1 between two adjacent second pixel driving circuits P2 in the first direction X.
  • the first pixel driving circuit P1 and the second pixel driving circuit P2 adjacent in the first direction X can constitute a repeating unit Q, and the two adjacent repeating units Q in the second direction Y can reuse the same data signal line Data, specifically, the first pixel driving circuit P1 in the repeating unit Q of this row can reuse the same data signal line Data with the second pixel driving circuit P2 in the repeating unit Q of the previous row.
  • the number of data signal lines Data can be reduced, which is conducive to optimizing the layout space and improving the space utilization of the layout.
  • the third conductive layer 4 may further include a virtual signal line D-line.
  • the extension direction of the orthographic projection of the virtual signal line D-line on the substrate may be the same as the extension direction of the data signal line Data on the substrate.
  • the virtual signal line D-line may be located in a gap between two adjacent repeating units Q in the first direction X, so that the data signal line Data is distributed in a gap between the first pixel driving circuit P1 and the second pixel driving circuit P2 in the same repeating unit Q, and the virtual signal line D-line is distributed in a gap between two adjacent repeating units Q in the row direction.
  • the fourth conductive layer 5 may include a second electrode structure Com, and the second electrode structure Com may be used to form a common electrode Vcom and a second electrode of a storage capacitor Cst.
  • FIG11a is a schematic diagram of the structure of the complete second electrode structure in FIG2 .
  • the second electrode structure Com may include a slit electrode.
  • the slit electrode may include a slit portion Com1 and a strip electrode portion located between adjacent slit portions Com1.
  • the strip electrode portion may include a plurality of first strip portions Com2 and a plurality of second strip portions Com3.
  • the extension direction of the first strip portion Com2 intersects with the extension direction of the second strip portion Com3, and the first strip portion Com2 and the second strip portion Com3 are connected at the second bending portion Com4.
  • the second bending portion Com4 may be located in the middle of the second electrode structure Com in the column direction, and the orthographic projections of the second bending portion Com4 and the first bending portion Pix3 on the substrate may overlap.
  • the second electrode structure Com may also be other structures, such as an electrode block.
  • the orthographic projection of the second electrode structure Com on the substrate substrate has an overlapping portion with the orthographic projection of the first electrode structure Pix on the substrate substrate. Because the first electrode structure Pix can form the first pole of the storage capacitor Cst, and the second electrode structure Com can form the second pole of the storage capacitor Cst, the overlapping area of the orthographic projection of the first electrode structure Pix and the second electrode structure Com on the substrate substrate determines the size of the storage capacitor Cst. In an exemplary embodiment, the orthographic projection area of the first electrode structure Pix on the substrate substrate can be increased to increase the overlapping area of the first end electrode structure and the second electrode structure Com, thereby increasing the storage capacitor Cst. For details, please refer to the introduction of the subsequent embodiments.
  • the display panel may include a display area and a non-display area, and the non-display area surrounds the display area.
  • the present disclosure may set a common electrode line in the non-display area, and the second electrode structure Com may extend to the non-display area to connect with the common electrode line.
  • FIG11b is a stacking layout of the first conductive layer and the third conductive layer.
  • the main body G0 of the gate signal line Gate has a first side L1 and a second side L2 opposite to each other in the column direction in the orthographic projection of the substrate, the first side L1 is located on the side of the second side L2 away from the orthographic projection of the corresponding first electrode structure Pix on the substrate, and a first distance d1 is provided between the first side L1 and the second side L2;
  • the first electrode structure Pix has a second distance d2 between the orthographic projection of the substrate and the second side L2 corresponding thereto, the second distance d2 is greater than or equal to 2.5 ⁇ m, and the first distance d1 is greater than the second distance d2.
  • the distance between the gate signal line and the first electrode structure Pix in the column direction to be greater than or equal to 2.5 ⁇ m, a large gate-pixel electrode capacitance Cgs can be prevented from being generated between the pixel electrode and the gate signal line due to the close distance, thereby avoiding the flicker phenomenon caused by the increase of ⁇ vp in formula (1).
  • FIG12 is a structural layout diagram of a display panel according to another embodiment of the present disclosure
  • FIG13 is a structural layout diagram of the first conductive layer in FIG12
  • FIG14 is a stacked layout diagram of the first conductive layer and the second conductive layer.
  • the first conductive layer 1 may further include a first conductive line 11, the orthographic projection of the first conductive line 11 on the substrate may extend along the row direction, the first conductive line 11 may extend from the display area to the non-display area, and connect the common electrode line of the non-display area, and the orthographic projection of the first conductive line 11 on the substrate at least partially overlaps with the orthographic projection of the first bending portion Pix3 on the substrate.
  • the first conductive line 11 is connected to the common electrode line, so the first conductive line 11 constitutes a part of the common electrode Vcom, thereby increasing the overlapping area of the pixel electrode Vpixel and the common electrode Vcom by overlapping the first conductive line 11 with the first bending portion Pix3, thereby increasing the storage capacitor Cst.
  • the first bent portion Pix3 can be located in the middle of the first electrode structure Pix in the column direction, so that the present exemplary embodiment forms the first conductive line 11 in the middle of the first electrode structure Pix in the column direction to increase the overlapping area of the common electrode Vcom and the pixel electrode Vpixel, thereby increasing the storage capacitor Cst.
  • the distance between this position and other structures of the first conductive layer 1 is relatively far, so it will not affect the design parameters of the display panel product at the Array stage.
  • the orthographic projection of the first conductive line 11 on the base substrate can cover the orthographic projection of the first bend Pix3 on the base substrate.
  • the pixel space can be fully utilized to increase the width of the first conductive line 11 in the column direction without affecting the pixel aperture ratio, thereby increasing the overlap between the first conductive line 11 and the pixel electrode Vpixel, and further increasing the increase in the storage capacitor Cst.
  • the orthographic projection of the first conductive line 11 on the substrate has a third side L3 and a fourth side L4 opposite to each other in the column direction, and the third side L3 and the fourth side L4 have a first width D1 in the column direction;
  • the orthographic projection of the first electrode structure Pix on the substrate has a fifth side L5 and a sixth side L6 opposite to each other in the column direction, and the fifth side L5 and the sixth side L6 have a second width D2 in the column direction;
  • the ratio of the first width D1 to the second width D2 may be 0.05 to 0.06, for example, 0.05, 0.054, 0.055, 0.058, 0.06, etc. Therefore, the width of the first conductive line 11 may be determined according to the size of the pixel electrode in the Array stage, and the capacitance increase of the storage capacitor Cst may be determined.
  • FIG15 is a structural layout diagram of a display panel according to another embodiment of the present disclosure
  • FIG16a is a structural layout diagram of the first conductive layer in FIG15
  • FIG16b is a structural layout diagram of a repeating unit of the first conductive layer in FIG15
  • FIG17 is a stacked layout diagram of the first conductive layer and the second conductive layer.
  • the first conductive layer 1 may further include a second conductive line 12 and a third conductive line 13, and the orthographic projections of the second conductive line 12 and the third conductive line 13 on the substrate may extend along the row direction, and the second conductive line 12 and the third conductive line 13 may extend to the non-display area to connect to the common electrode line, so that the second conductive line 12 and the third conductive line 13 form a partial structure of the common electrode Vcom.
  • the first pixel driving circuit P1 and the second pixel driving circuit P2 adjacent to each other in the first direction X can form a repeating unit Q.
  • the second conductive line 12 and the third conductive line 13 are located between the first gate signal line Gate11 and the second gate signal line Gate22, and the orthographic projection of the second conductive line 12 on the substrate intersects with the orthographic projection of one end of the first electrode portion Pix1 away from the first bending portion Pix3 on the substrate; the orthographic projection of the third conductive line 13 on the substrate intersects with the orthographic projection of one end of the second electrode portion Pix2 away from the first bending portion Pix3 on the substrate.
  • the second conductive line 12 overlaps with the first electrode structure Pix on the side of the first electrode structure Pix close to the first gate signal line Gate1
  • the third conductive line 13 overlaps with the first electrode structure Pix on the side of the first electrode structure Pix of the pixel unit close to the second gate signal line Gate2.
  • the second conductive line 12 and the third conductive line 13 are arranged on both sides of the pixel unit in the column direction, and a double conductive line is formed to overlap the pixel electrode Vpixel, thereby increasing the capacitance that can be increased. That is, the pixel space can be used to fully increase the capacitance increase of the storage capacitor Cst.
  • the first gate signal line Gate11 is a gate signal line in the first pixel driving circuit P1
  • the second gate signal line Gate22 is a gate signal line in the second pixel driving circuit P2.
  • the second conductive line 12 and the third conductive line 13 may have the same structure, and the orthographic projections of the second conductive line 12 and the third conductive line 13 on the base substrate may be symmetrical about the orthographic projection axis of the first bending portion Pix3 on the base substrate.
  • the orthographic projections of the second conductive line 12 and the third conductive line 13 on the substrate have a seventh side L7 and an eighth side L8 opposite to each other in the column direction, the seventh side L7 is located on the side of the eighth side L8 close to the orthographic projection of the corresponding gate signal line on the substrate, and the seventh side L7 and the eighth side L8 have a third width D3 in the column direction;
  • the orthographic projection of the main body of the gate signal line on the substrate has a first side L1 and a second side L2 opposite to each other in the column direction, the first side L1 is located on the side of the second side L2 away from the orthographic projection of the corresponding first electrode structure Pix on the substrate, and the seventh side L7 has a fourth distance d4 from the second side L2 of the orthographic projection of the corresponding gate signal line on the substrate in the column direction.
  • a certain space can be reserved for the second conductive line 12 and the third conductive line 13 by reducing the width of the gate signal line Gate in the column direction, so that the first electrode structure Pix can be extended to both sides along the column direction, so that the two ends of the first electrode structure Pix in the column direction overlap with the second conductive line 12 and the third conductive line 13 respectively, thereby increasing the storage capacitor Cst, and the capacitance of the storage capacitor Cst that can be increased is larger.
  • the fourth distance d4 is limited by the process conditions. If the process capability allows, the fourth distance d4 can be as small as possible to increase the width of the second conductive line 12 and the third conductive line 13 in the column direction and increase the overlapping area with the first electrode structure Pix.
  • the seventh side L7 and the eighth side L8 have a third width D3 in the column direction;
  • the orthographic projection of the first electrode structure Pix on the substrate has a fifth side L5 and a sixth side L6 in the column direction, and the fifth side L5 and the sixth side L6 have a second width D2 in the column direction;
  • the ratio of the third width D3 to the second width D2 may be 0.05 to 0.06, for example, 0.05, 0.054, 0.055, 0.058, 0.06, etc.
  • the widths of the second conductive line 12 and the third conductive line 13 may be determined according to the size of the pixel electrode in the Array stage.
  • FIG18 is a structural layout of the third conductive layer in FIG12
  • FIG19 is a structural layout of the third conductive layer in FIG15
  • the third conductive layer 4 may also not include a virtual signal line D-line, that is, no virtual signal line D-line is set in the gap between two adjacent repeating units Q in the row direction.
  • the extension length of the first electrode structure Pix in the second conductive layer 3 in the row direction can be increased, thereby increasing the overlapping area of the first electrode structure Pix and the second electrode structure Com, thereby increasing the capacitance of the storage capacitor Cst.
  • This exemplary embodiment can increase the capacitance of the storage capacitor Cst without affecting the pixel display effect.
  • the third conductive layer 4 includes a virtual signal line D-line. Accordingly, as shown in FIG. 10 , the first electrode structure Pix in the first pixel driving circuit P1 has a fifth distance d5 in the row direction between the orthographic projection of the substrate substrate and the orthographic projection of the first electrode structure Pix in the second pixel driving circuit P2 in the adjacent repeating unit in the row direction. In the structure shown in FIG. 15 , the third conductive layer 4 cancels the virtual signal line D-line. Accordingly, as shown in FIG.
  • the first electrode structure Pix in the first pixel driving circuit P1 has a sixth distance d6 in the horizontal direction between the orthographic projection of the substrate substrate and the orthographic projection of the first electrode structure Pix in the second pixel driving circuit P2 in the adjacent repeating unit.
  • the fifth distance d5 is greater than the sixth distance d6.
  • the third conductive layer 4 includes a virtual signal line D-line.
  • the orthographic projection of the first electrode structure Pix on the substrate substrate and the orthographic projection of the second electrode structure Com on the substrate substrate have a first overlapping area S1, and the first overlapping area S1 is smaller than the second overlapping area S2.
  • the virtual signal line D-line is cancelled in the third conductive layer 4. Under this structure, as shown in FIG.
  • the area of the first electrode structure Pix is increased, and the orthographic projection of the first electrode structure Pix on the substrate substrate and the orthographic projection of the second electrode structure Com on the substrate substrate in the same repeating unit have a second overlapping area S2, and the first overlapping area S1 is smaller than the second overlapping area S2, that is, when the size of the second electrode structure Com in the fourth conductive layer 5 remains unchanged, the size of the first electrode structure Pix of the second conductive layer 3 is increased by canceling the virtual signal line D-line of the third conductive layer 4, thereby increasing the overlapping area of the first electrode structure Pix and the second electrode structure Com, thereby increasing the storage capacitor Cst.
  • the ratio of the first overlapping area S1 to the second overlapping area S2 may be 0.77 to 0.79, for example, 0.77, 0.775, 0.78, 0.785, 0.79, etc.
  • the solution of improving screen jitter by increasing the capacitance of the storage capacitor Cst is shown in Table 2.
  • the capacitance of the storage capacitor Cst increases, it does not significantly increase the load of the display panel. Since the product uses low-frequency drive, the overall power consumption of the product decreases.
  • the storage capacitor Cst is connected in parallel with the liquid crystal capacitor Clc, and the capacitance of Clc is small, and the actual change of Cst has little effect on the overall loading of the screen. It can be seen that the present disclosure can improve the jitter phenomenon of the display panel during low-frequency drive by increasing the capacitance of the storage capacitor Cst, and will not significantly increase the load of the display panel.
  • the present disclosure also provides a display device, which includes the display panel described in any of the above embodiments of the present disclosure.

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Abstract

一种显示面板，显示面板包括依次层叠的衬底基板、第一导电层(1)和有源层(2)，第一导电层(1)包括多条栅极信号线，栅极信号线包括主体部和多个增设部，主体部在衬底基板的正投影沿第一方向延伸，多个增设部在第一方向上间隔分布且在第二方向上连接于主体部的一侧，增设部用于形成驱动晶体管的栅极；有源层(2)包括多个有源结构，多个有源结构与多个增设部对应设置，多个有源结构在衬底基板的正投影彼此分离，有源结构包括彼此分离的多个有源部，有源部用于形成驱动晶体管的沟道区；其中，一个增设部对应多个有源部，且增设部在衬底基板的正投影覆盖与其对应的多个有源部在衬底基板的正投影。

Description

一种显示面板及显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示面板及显示装置。
背景技术
近些年LCD显示产品展现出多元化趋势，穿戴产品衍生出低频低功耗需求，然而使用低刷新频率会导致显示面板存在抖动、闪烁(Flicker)风险。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于克服上述现有技术的不足，提供一种显示面板及显示装置。
根据本公开的一个方面，提供一种显示面板，所述显示面板包括沿第一方向和第二方向阵列分布的多个像素驱动电路，所述像素驱动电路包括驱动晶体管，所述驱动晶体管的栅极连接栅极信号线，所述第一方向与所述第二方向相交；所述显示面板还包括：衬底基板；第一导电层，位于所述衬底基板的一侧，所述第一导电层包括：多条栅极信号线，所述栅极信号线包括主体部和多个增设部，所述主体部在所述衬底基板的正投影沿所述第一方向延伸，所述多个增设部在所述第一方向上间隔分布且在所述第二方向上连接于所述主体部的一侧，所述增设部用于形成所述驱动晶体管的栅极；有源层，位于所述第一导电层背离所述衬底基板的一侧，所述有源层包括：多个有源结构，与所述多个增设部对应设置，所述多个有源结构在所述衬底基板的正投影彼此分离，所述有源结构包括彼此分离的多个有源部，所述有源部用于形成所述驱动晶体管的沟道区；其中，一个所述增设部对应多个所述有源部，且所述增设部在 所述衬底基板的正投影覆盖与其对应的多个所述有源部在所述衬底基板的正投影。
在本公开的示例性实施例中，所述多个有源部包括第一有源部和第二有源部，所述第一有源部和所述第二有源部在所述第一方向上间隔设置；其中，所述增设部在所述衬底基板的正投影覆盖与其对应的所述第一有源部在所述衬底基板的正投影和所述第二有源部在所述衬底基板的正投影。
在本公开的示例性实施例中，所述驱动晶体管的第一极连接像素电极；所述第一方向为行方向，所述第二方向为列方向；所述显示面板还包括：第二导电层，位于所述有源层背离所述衬底基板的一侧，所述第二导电层包括：多个第一电极结构，与所述多个增设部一一对应，所述第一电极结构用于形成所述像素电极；其中，所述多个像素驱动电路包括第一像素驱动电路和第二像素驱动电路，所述第一像素驱动电路和所述第二像素驱动电路在所述行方向上依次交替分布，且所述第一像素驱动电路位于同一列，所述第二像素驱动电路位于同一列；所述第一像素驱动电路中的栅极信号线为第一栅极信号线，所述第二像素驱动电路中的栅极信号线为第二栅极信号线；本行所述第一栅极信号线、第二栅极信号线在所述衬底基板的正投影分别位于本行第一电极结构在所述衬底基板的正投影在列方向的两侧；本行第一栅极信号线中的增设部位于对应主体部与上一行第二栅极信号线的主体部之间，上一行第二栅极信号线中的增设部位于对应主体部与本行第一栅极信号线的主体部之间。
在本公开的示例性实施例中，所述增设部在所述衬底基板的正投影覆盖与其对应的所述有源结构在所述衬底基板的正投影。
在本公开的示例性实施例中，所述有源结构在所述衬底基板的正投影的边沿与所述增设部在所述衬底基板的正投影的边沿之间的距离大于等于2.5μm。
在本公开的示例性实施例中，所述主体部在所述衬底基板的正投影具有在列方向上相对的第一侧边和第二侧边，所述第一侧边位于所述第二侧边远离对应第一电极结构在所述衬底基板的正投影的一侧，所述第一侧边和所述第二侧边之间具有第一距离；所述第一电极结构在所述衬 底基板的正投影和与其对应的第二侧边之间具有第二距离，所述第二距离大于等于2.5μm，且所述第一距离大于所述第二距离。
在本公开的示例性实施例中，所述像素驱动电路还包括存储电容，所述存储电容的第一极连接所述像素电极，第二极连接公共电极；所述显示面板还包括：第四导电层，位于所述第二导电层背离所述衬底基板的一侧，所述第四导电层包括：多个第二电极结构，各所述第二电极结构彼此连接形成网格结构，所述第二电极结构在所述衬底基板的正投影与所述第一电极结构在所述衬底基板的正投影部分交叠；其中，所述第一电极结构还用于形成所述存储电容的第一极，所述第二电极结构还用于形成所述存储电容的第二极。
在本公开的示例性实施例中，所述第一电极结构包括第一电极部和第二电极部，所述第一电极部的延伸方向与所述第二电极部的延伸方向相交；所述第一电极部的延伸方向与所述列方向具有第一夹角，所述第二电极部的延伸方向与所述列方向具有第二夹角，所述第一夹角与所述第二夹角相同，且所述第一电极部和所述第二电极部的延伸长度相同，且连接于第一弯折部。
在本公开的示例性实施例中，所述第一导电层还包括：第一导电线，在所述衬底基板的正投影沿所述行方向延伸，所述第一导电线连接所述第二电极结构，所述第一导电线在所述衬底基板的正投影与所述第一弯折部在所述衬底基板的正投影至少部分交叠。
在本公开的示例性实施例中，所述第一导电线在所述衬底基板的正投影覆盖所述第一弯折部在所述衬底基板的正投影。
在本公开的示例性实施例中，所述第一导电线在所述衬底基板的正投影具有在列方向上具有相对的第三侧边和第四侧边，所述第三侧边与所述第四侧边在所述列方向具有第一宽度；所述第一电极结构在衬底基板的正投影在所述列方向具有相对的第五侧边和第六侧边，所述第五侧边和所述第六侧边在所述列方向具有第二宽度；所述第一宽度与所述第二宽度之比为0.05～0.06。
在本公开的示例性实施例中，所述显示面板包括多个重复单元，所述重复单元包括在行方向相邻的所述第一像素驱动电路和所述第二像素 驱动电路；所述第一导电层还包括：第二导电线，在所述衬底基板的正投影沿所述行方向延伸，所述第二导电线连接所述第二电极结构；第三导电线，在所述衬底基板的正投影沿所述行方向延伸，所述第三导电线连接所述第二电极结构；其中，同一重复单元中，所述第二导电线和所述第三导电线位于所述第一栅极信号线和所述第二栅极信号线之间，所述第二导电线在所述衬底基板的正投影与所述第一电极部远离所述第一弯折部的一端在所述衬底基板的正投影相交；所述第三导电线在所述衬底基板的正投影与所述第二电极部远离所述第一弯折部的一端在所述衬底基板的正投影相交。
在本公开的示例性实施例中，所述第二导电线和所述第三导电线在所衬底基板的正投影均具有在列方向相对的第七侧边和第八侧边，所述第七侧边与所述第八侧边在所述列方向上具有第三宽度；所述第一电极结构在衬底基板的正投影在所述列方向具有相对的第五侧边和第六侧边，所述第五侧边和所述第六侧边在所述列方向具有第二宽度；所述第三宽度与所述第二宽度之比为0.05～0.06。
在本公开的示例性实施例中，同一重复单元中的所述第一电极结构在所述衬底基板的正投影与所述第二电极结构在所述衬底基板的正投影具有第二交叠面积S2；在行方向相邻的任意两个重复单元中，第一像素驱动电路中的第一电极结构在所述衬底基板的正投影和相邻重复单元中的第二像素驱动电路中的第一电极在所述衬底基板的正投影之间在所述水平方向上具有第六距离。
在本公开的示例性实施例中，所述显示面板还包括：第三导电层，位于所述第二导电层背离所述衬底基板的一侧，所述第三导电层包括：虚拟信号线，在所述衬底基板的正投影沿列方向延伸，且位于行方向相邻的两个重复单元在所述衬底基板的正投影之间；其中，同一重复单元中，所述第一电极结构在所述衬底基板的正投影与所述第二电极结构在所述衬底基板的正投影具有第一交叠面积S1，所述第一交叠面积小于所述第二交叠面积S2；第一像素驱动电路中的第一电极结构在所述衬底基板的正投影与行方向相邻重复单元中的第二像素驱动电路中的第一电极结构在所述衬底基板的正投影之间在所述行方向上具有第五距离，所述 第五距离大于所述第六距离。
在本公开的示例性实施例中，所述第二交叠面积与所述第一交叠面积之比为0.77～0.79。
在本公开的示例性实施例中，所述驱动晶体管的第一极连接数据信号端；所述有源结构还包括：第一子有源部，与所述第一有源部对应设置且连接于所述第一有源部的一侧，所述第一子有源部用于形成所述驱动晶体管的第一极；第二子有源部，与所述第二有源部对应设置且连接于所述第二有源部远离所述第一有源部的一侧，所述第二子有源部用于形成所述驱动晶体管的第二极；第三子有源部，连接于与其对应的所述第一有源部和所述第二有源部之间；所述显示面板还包括：第三导电层，位于所述第二导电层背离所述衬底基板的一侧，所述第三导电层包括：第一导电部，在所述衬底基板的正投影覆盖所述第一子有源部在所述衬底基板的正投影，且所述第一导电部与所述第一子有源部电连接，以连接所述驱动晶体管的第一极；第二导电部，在所述衬底基板的正投影覆盖所述第二子有源部在所述衬底基板的正投影，且所述第二导电部与所述第二子有源部电连接，以连接所述驱动晶体管的第二极；第三导电部，与所述第三子有源部一一对应设置，所述第三导电部位于所述第一导电部和所述第二导电部之间，所述第三导电部在所述衬底基板的正投影覆盖对应所述第三子有源部在所述衬底基板的正投影。
在本公开的示例性实施例中，所述第三导电层还包括：数据信号线，在所述衬底基板的正投影沿所述列方向延伸，所述数据信号线连接所述第一导电部，以连接所述驱动晶体管的第一极；其中，所述显示面板包括多个重复单元，所述重复单元包括在行方向相邻的所述第一像素驱动电路和所述第二像素驱动电路；本行重复单元中的第一像素驱动电路与上一行重复单元中的第二像素驱动电路复用同一所述数据信号线。
在本公开的示例性实施例中，所述第二导电层还包括：备用导电部，位于相邻所述第一像素驱动电路和所述第二像素驱动电路之间；其中，所述备用导电部在所述衬底基板的正投影位于对应所述数据信号线在所述衬底基板的正投影内。
根据本公开的另一个方面，还提供一种显示装置，包括本公开任意 实施例所述的显示面板。
本公开提供的显示面板，栅极信号线的增设部在第二方向上突出于主体部的一侧，用于形成驱动晶体管的栅极，从而驱动晶体管的栅极为一整体结构。多个有源部均用于形成驱动晶体管的栅极，并且增设部在衬底基板的正投影覆盖与其对应的多个有源部在衬底基板的正投影，从而使得驱动晶体管形成多栅结构，换言之，本公开驱动晶体管为多栅结构且多个栅极为一体结构，通过该方式可以提升驱动晶体管对关态漏电流的抑制能力，从而减小驱动晶体管的关态漏电流，由此可以减轻显示面板在低频驱动时的屏幕闪烁现象。并且，本公开驱动晶体管的栅极为一整体的多栅结构，其相比于现有技术中的栅极分离的多栅结构，可以进一步提升对于关态漏电流的抑制能力，对于减轻显示面板在低频驱动下的屏闪现象效果更好。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为根据本公开一种实施方式的像素驱动电路的电路结构示意图；
图2为根据本公开该一种实施方式的显示面板的结构版图；
图3为图2中第一导电层的结构版图；
图4为图2中有源层的结构版图；
图5为第一导电层和有源层的叠层版图；
图6为图2中第二导电层的结构版图；
图7为图2中第三导电层的结构版图；
图8为图2中第四导电层的结构版图；
图9为第一导电层和有源层在行方向上重叠的结构示意图；
图10为图2中完整第一电极结构的结构示意图；
图11a为图2中完整第二电极结构的结构示意图；
图11b为第一导电层和第三导电层的叠层版图；
图12为根据本公开另一种实施方式的显示面板的结构版图；
图13为图12中第一导电层的结构版图；
图14为第一导电层和第二导电层的叠层版图；
图15为根据本公开再一种实施方式的显示面板的结构版图；
图16a为图15中第一导电层的结构版图；
图16b为图15中第一导电层的一个重复单元的结构版图；
图17为第一导电层和第二导电层的叠层版图；
图18为图12中第三导电层的结构版图；
图19为图15中第三导电层的结构版图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流可以流过漏电极、沟道区域以及源电极。沟道区域是指电流主要流过的区域。
第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源 电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
LCD显示产品展现出多元化趋势，不同的产品都在寻求性能上的提升。针对穿戴产品，例如智能手表、手环等，越来越趋向于轻巧便捷，因此低功耗成为其性能提升的方向。显示行业为应对这一趋势，考虑到其显示需求的特性，推出低频低功耗的解决方案，通过降低屏幕刷新频率达到低功耗的效果。
市面上大部分显示产品的刷新频率为60Hz，原因是人眼能捕捉的最快电子影像的速度就是60帧。降低屏幕刷新率会影像人眼视觉效果，出现画面不流畅，卡顿等体验。智能手表、手环等穿戴产品画面简单，且不存在画面快速切换，可接受刷新频率降低，但发明人发现，频率降低意味着屏幕每行驱动时间增加，驱动时间变长会引起像素间更大的耦合和漏电，屏幕存在Flicker风险。
具体而言，当像素电压随着正负帧变化进行反转，ΔVp耦合、ΔVp漏电不一致时，像素的亮度随着帧的变换而变化，从而使人眼感受到闪烁。低频状态下，由于一帧保持时间增加，像素电极Vpixel上漏电量增加，屏幕闪烁会加重。像素的亮度会随着帧的变换而变化，从而使人眼感受到闪烁。
Figure PCTCN2022128358-appb-000001
Figure PCTCN2022128358-appb-000002
式中：△Vp为像素电极由于Gate/Data的开启或者关闭导致的电容耦合效应而改变的值，Cgs为TFT栅极与像素电极电容，Cst为公共电极与像素电极间电容，Clc为液晶电容，VGH和VGL分别为TFT的开启和关闭电压。
由上述公式(1)、(2)可知：ΔVp漏电与Ioff、帧频f frame、Cst有关，Ioff下降则ΔVp漏电减少；帧频f frame降低，则ΔVp漏电增加；Cst升高则ΔVp漏电减少。
由此，发明人提出通过增加存储电容和降低关态漏电流的技术方案 来解决低频驱动下屏幕Flicker问题，下面结合附图对本公开技术方案进行具体介绍。
图1为根据本公开一种实施方式的像素驱动电路的电路结构示意图。该像素驱动电路可以包括驱动晶体管T和存储电容Cst，驱动晶体管T的栅极连接栅极驱动信号端Gate，第一极连接数据信号端Vdata，第二极连接像素电极Vpixel。存储电容Cst的第一极连接像素电极Vpixel，第二极连接公共电极Vcom。
本公开实施方式提供了一种显示面板，图2为根据本公开该一种实施方式的显示面板的结构版图，图3为图2中第一导电层的结构版图，图4为图2中有源层的结构版图，图5为第一导电层和有源层的叠层版图，如图2～图5所示，该显示面板包括沿第一方向X和第二方向Y阵列分布的多个像素驱动电路，像素驱动电路用于驱动发光器件发光，发光器件例如可以为液晶，相应地，本公开所述的显示面板可以为液晶显示面板，第一方向X与第二方向Y相交。显示面板可以还包括：衬底基板、第一导电层1和有源层2，其中，第一导电层1位于衬底基板的一侧，第一导电层1可以包括多条栅极信号线Gate，栅极信号线Gate包括主体部G0和多个增设部G1，主体部G0在衬底基板的正投影沿第一方向X延伸，多个增设部G1在第一方向X上间隔分布且在第二方向Y上连接于主体部G0的一侧，增设部G1用于形成驱动晶体管T的栅极；有源层2位于第一导电层1的一侧，有源层2可以包括多个有源结构AC，多个有源结构AC在衬底基板的正投影彼此分离，有源结构AC包括多个彼此分离的有源部，有源部用于形成驱动晶体管T的沟道区；其中，一个增设部G1对应多个有源部，且增设部G1在衬底基板的正投影覆盖与其对应的多个有源部在衬底基板的正投影。
本公开提供的显示面板，栅极信号线Gate的增设部G1在第二方向Y上突出于主体部G0的一侧，用于形成驱动晶体管T的栅极，从而驱动晶体管T的栅极为一整体结构。多个有源部均用于形成驱动晶体管T的栅极，并且增设部G1在衬底基板的正投影覆盖与其对应的多个有源部在衬底基板的正投影，从而使得驱动晶体管T形成多栅结构，换言之，本公开驱动晶体管T为多栅结构且多个栅极为一体结构，通过该方式可 以提升驱动晶体管T对关态漏电流的抑制能力，从而减小驱动晶体管T的关态漏电流，由此可以减轻显示面板在低频驱动时的屏幕闪烁现象。并且，本公开驱动晶体管T的栅极为一整体的多栅结构，其相比于现有技术中的栅极分离的多栅结构，可以进一步提升对于关态漏电流的抑制能力，对于减轻显示面板在低频驱动下的屏闪现象效果更好。
如图2～图5所示，在示例性实施例中，第一方向X可以为行方向，第二方向Y可以为列方向。此外，应该理解的，本公开有源层2可以是位于第一导电层1背离衬底基板1的一侧，形成底栅结构的驱动晶体管T；或者有源层2也可以位于第一导电层1和衬底基板之间，形成顶栅结构的驱动晶体管T。本公开仅以底栅结构为例进行示例性说明，不应理解为对本公开的限制。
栅极信号线Gate可以用于提供图1中的栅极驱动信号端Gate，栅极信号线Gate的主体部G0在衬底基板的正投影沿第一方向X延伸，栅极信号线Gate的增设部G1在第二方向Y上位于主体部G0的一侧，并且同一栅极信号线Gate上的各个增设部G1可以在第二方向Y上位于主体部G0的同一侧。栅极信号线Gate的增设部G1可用于形成驱动晶体管T的栅极。
应该理解的，本公开所述的某一结构A沿C方向延伸是指，A可以包括主要部分和与主要部分连接的次要部分，主要部分为线、线段或条形状体，主要部分沿C方向伸展，且主要部分沿C方向伸展的长度大于次要部分沿其他方向伸展的长度。
多个有源结构AC在衬底基板的正投影彼此分离，表明多个有源结构AC在有源层2间隔分布。一个有源结构AC上包括多个彼此独立的有源部，有源部用于形成驱动晶体管T的沟道区，由此一个有源结构AC形成驱动晶体管T的多个沟道区。
应该理解的，本公开所述的某一结构A与另一结构B在衬底基板的正投影彼此分离，表明结构A在衬底基板的正投影与结构B在衬底基板的正投影没有重叠区域，亦即结构A与结构B为相互独立的结构。
本公开增设部G1在衬底基板的正投影覆盖有源部在衬底基板的正投影，增设部G1可包括多个子结构，并且各子结构与各有源部一一对 应，子结构在衬底基板的正投影可以覆盖对应有源部在衬底基板的正投影，相应地，增设部G1的子结构即形成驱动晶体管T的栅极，因此，一个增设部G1在衬底基板的正投影覆盖与其对应的多个有源部在衬底基板的正投影，表明一个增设部G1形成了驱动晶体管T的多个栅极，进一步而言是一个整体结构的增设部G1形成了驱动晶体管T的多个栅极。本公开通过将驱动晶体管T形成多栅结构来增大驱动晶体管T的沟道长度，从而减小驱动晶体管T的关态漏电流。
具体而言，根据驱动晶体管T输出电流公式I＝(μWCox/2L)(Vgs-Vth) 2，其中，μ为载流子迁移率，Cox为单位面积栅极电容量，W为驱动晶体管T沟道的宽度，L驱动晶体管T沟道的长度，Vgs为驱动晶体管T栅源电压差，Vth为驱动晶体管T阈值电压。可以看出，本公开通过形成多栅结构的驱动晶体管，增大了驱动晶体管T的沟道长度L，从而降低了驱动晶体管T的关态漏电流，由此可以降低显示面板在低频驱动时的闪烁、抖动现象。
应该理解的是，本公开所述的某一结构A在衬底基板的正投影覆盖另一结构B在衬底基板的正投影可以理解为，B在衬底基板平面的投影的轮廓完全位于A在同一平面内投影的轮廓的内部。
如图4、图5所示，在示例性实施例中，多个有源部可以包括多个第一有源部AC1和多个第二有源部AC2，第一有源部AC1和第二有源部AC2在第一方向X上间隔设置；其中，一个增设部G1对应一个第一有源部AC1和一个第二有源部AC2，且增设部G1在衬底基板的正投影覆盖与其对应的第一有源部AC1在衬底基板的正投影和第二有源部AC2在衬底基板的正投影。具体地，一个有源结构AC包括第一有源部AC1和第二有源部AC2，即一个有源结构AC包括两个沟道区。第一有源部AC1和第二有源部AC2在第一方向X上间隔设置，即第一有源部AC1和第二有源部AC2在第一方向X上分开设置。一个增设部G1对应一个第一有源部AC1和一个第二有源部AC2，即一个增设部G1对应两个沟道区，即一个增设部G1形成驱动晶体管T的两个栅极，即本示例性实施例中的晶体管为双栅结构，并且两个栅极之间没有镂空结构。
值得注意的是，本公开通过形成双栅结构的驱动晶体管T来提升驱 动晶体管T的沟道长度，相比于同等沟道长度的单栅结构的驱动晶体管T结构，本公开驱动晶体管T具有双栅结构能够进一步提升驱动晶体管T对于关态漏电流的抑制能力，即有利于进一步减小显示面板的低频驱动抖动问题。示例性的，表1示例性给出了本公开的一仿真对比结果，从表1可以看出，通过增加驱动晶体管T的沟道长度，本公开双栅结构的驱动晶体管T可以将关态漏电流减小至1.43pA，显著小于沟道长度小的驱动单栅结构的驱动晶体管T的关态漏电流。并且，在沟道长度相同的情况下，单栅结构的驱动晶体管T的关态漏电流为1.53pA，其明显大于本公开中双栅结构的驱动晶体管T的关态漏电流，因此，通过形成双栅结构来提升驱动晶体管T的沟道长度的结构可以进一步提升对于关态漏电流的抑制能力，即能够进一步减小驱动晶体管T的关态漏电流，从而进一步减轻屏幕抖动现象。
表1
TFT类型 单栅一字型 双栅一字型 单栅一字型
W/L(μm) 4/2.9 6.5/(2.9+2.9) 6.5/5.8
Ioff(pA) 2.86 1.43 1.53
如图2、图5所示，在示例性实施例中，增设部G1在衬底基板的正投影可以覆盖与其对应的有源结构AC在衬底基板的正投影。即有源结构AC在衬底基板的正投影完全位于对应增设部G1在衬底基板的正投影内，换言之，增设部G1在衬底基板的正投影的边沿要超出对应有源结构AC在衬底基板的正投影的边沿一定距离。示例性的，有源结构AC在衬底基板的正投影的边沿与增设部G1在衬底基板的正投影的边沿之间的距离可以大于等于2.5μm，例如可以为2.5μm，2.6μm，2.7μm，2.8μm等。由此可以使得栅极信号线Gate在入光侧完全遮挡入射光，可以阻挡入射光线照射到有源结构AC，从而避免光线对有源结构AC的干扰。本示例性实施例中，增设部G1、有源结构AC在衬底基板的正投影均可以为矩形，有源结构AC在衬底基板的正投影的边沿与增设部G1在衬底基板的正投影的边沿之间的距离可以理解为，有源结构AC在衬底基板的正投影形成的矩形的侧边与包裹在其外围的增设部G1在衬底基板的正投影形成的矩形侧边在行方向或列方向上之间的距离。在其他 实施例中，有源结构AC、增设部G1在衬底基板的正投影还可以为其他结构，例如可以为圆形、椭圆形等，此时，有源结构AC在衬底基板的正投影的边沿由多个离散的节点组成，任一节点K与有源结构AC在衬底基板的中心的连线与增设部G1在衬底基板的正投影的边沿形成交点M，节点K与交点M之间的距离即为有源结构AC在衬底基板的正投影的边沿与增设部G1在衬底基板的正投影的边沿之间的距离。
可以理解的，有源结构AC可以包括经导体化处理后的导体部和未经导体化处理的半导体部(有源部)，其中的半导体部用于形成晶体管的沟道区，导体部例如可以用于连接晶体管的源漏电极。如图2所示，在示例性实施例中，有源层2中的有源结构AC还可以包括第一子有源部AC-1、第二子有源部AC-2和第三子有源部AC-3，其中的第一子有源部AC-1与第一有源部AC1对应设置且连接于第一有源部AC1的一侧，第一子有源部AC-1可以用于形成驱动晶体管T的第一极。第二子有源部AC-2与第二有源部AC2对应设置且连接于第二有源部AC2远离第一有源部AC1的一侧，第二子有源部AC-2可以用于形成驱动晶体管T的第二极，第三子有源部AC-3连接于与其对应的第一有源部AC1和第二有源部AC2之间。本示例性实施例可以对第一子有源部AC-1～第三子有源部AC-3进行导体化，使得第一子有源部AC-1～第三子有源部AC-3均为导体结构。可以理解的，本公开驱动晶体管为双栅结构，其相当于两个晶体管，并且两个晶体管通过导体化的第三子有源部AC-3进行连接，换言之，第三子有源部AC-3既作为其中一个晶体管的第一极又作为另一晶体管的第二极。
本公开显示面板除了包括第一导电层1和有源层2外，还可以包括第二导电层3、第三导电层4和第四导电层5，第一导电层1、有源层2、第二导电层3、第三导电层4和第四导电层5在衬底基板的一侧依次层叠设置，上述功能层之间可以设置有绝缘层，例如，在第一导电层1和有源层2之间可具有栅绝缘层。图6为图2中第二导电层的结构版图，图7为图2中第三导电层的结构版图，图8为图2中第四导电层的结构 版图，图9为第一导电层和有源层在行方向上重叠的结构示意图。
如图6所示，在示例性实施例中，第二导电层3可以包括多个第一电极结构Pix，第一电极结构Pix与增设部G1一一对应设置，即一个增设部G1对应一个第一电极结构Pix，第一电极结构Pix可以用于形成像素电极Vpixel以及存储电容Cst的第一电极。本示例性实施例中，第一电极结构Pix可以为电极块，示例性的，图10为图2中完整第一电极结构的结构示意图，如图10所示，第一电极结构Pix可以包括第一电极部Pix1和第二电极部Pix2，第一电极部Pix1的延伸方向与第二电极部Pix2的延伸方向相交，且第一电极部Pix1和第二电极部Pix2相交于第一弯折部Pix3。如图10所示，第一电极部Pix1和第二电极部Pix2可以均偏离列方向一定角度延伸，从而在第一弯折部Pix3处连接。本示例性实施例中，第一电极部Pix1的延伸方向与列方向可以具有第一夹角α，第二电极部Pix2的延伸方向与列方向可以具有第二夹角β，第一夹角α可以与第二夹角β相同，并且第一电极部Pix1的延伸长度可以与第二电极部Pix2的延伸长度相同，由此而使得第一弯折部Pix3位于第一电极结构Pix在第二方向Y的中间位置，即第一电极部Pix1和第二电极部Pix2在第一电极结构Pix沿列方向的中间位置相交于一弯折部Pix3。值得注意的是，本示例性实施例中所述的第一电极部Pix1的延伸长度与第二电极部Pix2的延伸长度相同，其可以是第一电极部Pix1的延伸长度与第二电极部Pix2的延伸长度完全相同，也可以是第一电极部Pix1的延伸长度与第二电极部Pix2的延伸长度非常接近，例如，第一电极部Pix1的延伸长度与第二电极部Pix2的延伸长度的比值在0.8～1.2之间，或者又例如，第一电极部Pix1的延伸长度与第二电极部Pix2的延伸长度的差值绝对值在设定的冗余范围内，这些均可以认为第一电极部Pix1的延伸长度与第二电极部Pix2的延伸长度相同。应该理解的，在其他实施例中，第一电极结构Pix还可以为其他结构，例如可以为狭缝电极等。
如图6所示，在示例性实施例中，第二导电层3还可以包括备用导电部30，备用导电部30位于在第一方向X上相邻的两个第一电极结构Pix之间，即备用导电部30分布于第一方向X上相邻的两个第一电极结构Pix之间的间隙内，并且备用导电部30与第一电极结构Pix分离，亦 即备用导电部30和第一电极结构Pix不连接。备用导电部30可以与第三导电层4的数据信号线Data一一对应设置，并且备用导电部30在衬底基板的正投影可以与数据信号线Data在衬底基板的正投影的延伸方向相同且在延伸方向上至少部分交叠，例如数据信号线Data在衬底基板的正投影可以覆盖备用导电部30在衬底基板的正投影。备用导电部30可通过过孔连接第三导电层4的数据信号线Data，从而备用导电部30成为数据信号线Data的并联结构，这样在产品的使用过程中，即便数据信号线Data局部断裂，依然可以通过与其连接的备用导电部30进行数据信号传输，从而不会因为数据信号线Data的断裂而造成显示面板无法使用，一定程度上提升了显示面板的使用寿命和可靠性。
此外，在第三导电层4包括虚拟信号线D-line时，可以在对应虚拟信号线D-line的位置也设置备用导电部30，例如，虚拟信号线D-line在衬底基板的正投影可以覆盖与其对应的备用导电部30在衬底基板的正投影。
在示例性实施例中，可以将虚拟信号线D-line连接非显示区的公共电极线，从而虚拟信号线D-line与公共电极等电位。
如图9所示，在示例性实施例中，多个像素驱动电路可以包括第一像素驱动电路P1和第二像素驱动电路P2，第一像素驱动电路P1和第二像素驱动电路P2在行方向上依次交替分布，且第一像素驱动电路P1位于同一列，第二像素驱动电路P2位于同一列；第一像素驱动电路P1中的栅极信号线为第一栅极信号线Gate1，第二像素驱动电路P2中的栅极信号线为第二栅极信号线Gate2；本行第一栅极信号线Gate1、第二栅极信号线Gate2在衬底基板的正投影分别位于本行第一电极结构Pix在衬底基板的正投影的在列方向的两侧；本行第一栅极信号线Gate1中的增设部位于对应主体部靠近上一行第二栅极信号线Gate2的一侧，上一行第二栅极信号线Gate2中的增设部位于对应主体部靠近本行第一栅极信号线Gate1的一侧。由此，本行的第一像素驱动电路P1中的栅极结构与上一行的第二像素驱动电路P2中的栅极结构在行方向上依次交替分布。
如图7所示，在示例性实施例中，第三导电层4可以包括数据信号 线Data，数据信号线Data在衬底基板的正投影可以沿第二方向Y延伸，数据信号线Data可用于提供图1中的数据信号端Vdata。第三导电层4还可以包括第一导电部31、第二导电部32和第三导电部33，其中，第一导电部31在衬底基板的正投影可以覆盖第一子有源部AC-1在衬底基板的正投影，且第一导电部31与第一子有源部AC-1电连接，以连接驱动晶体管T的第一极。第二导电部32在衬底基板的正投影可以覆盖第二子有源部AC-2在衬底基板的正投影，且第二导电部32与第二子有源部AC-2电连接，以连接驱动晶体管T的第二极。第三导电部33与第三子有源部AC-3一一对应设置，第三导电部33位于第一导电部31和第二导电部32之间，第三导电部33在衬底基板的正投影覆盖对应第三子有源部AC-3在衬底基板的正投影，并且第三导电部33与第一导电部31和第二导电部32均不连接。
在示例性实施例中，相邻的两个像素单元可以复用同一数据信号线Data。示例性的，如图2所示，本公开多个像素驱动电路可以包括第一像素驱动电路P1和第二像素驱动电路P2，第一像素驱动电路P1和第二像素驱动电路P2在第一方向X上依次间隔分布，即在第一方向X上相邻的两个第一像素驱动电路P1之间具有一个第二像素驱动电路P2，换言之，在第一方向X上相邻的两个相邻的第二像素驱动电路P2之间具有一个第一像素驱动电路P1。在第一方向X上相邻的第一像素驱动电路P1和第二像素驱动电路P2可以构成一个重复单元Q，并且在第二方向Y上相邻的两个重复单元Q可以复用同一数据信号线Data，具体地，本行重复单元Q中的第一像素驱动电路P1可以与上一行重复单元Q中的第二像素驱动电路P2复用同一数据信号线Data。通过复用数据信号线Data，可以减少数据信号线Data的布设数量，有利于优化版图空间，提高版图的空间利用率。
如图2、图7所示，在示例性实施例中，第三导电层4还可以包括虚拟信号线D-line，虚拟信号线D-line在衬底基板的正投影的延伸方向可以与数据信号线Data在衬底基板的延伸方向相同，虚拟信号线D-line可以位于在第一方向X上相邻的两个重复单元Q之间的间隙内，从而在同一重复单元Q内的第一像素驱动电路P1和第二像素驱动电路P2之间 的间隙内分布有数据信号线Data，在行方向相邻的两个重复单元Q之间的间隙内分布有虚拟信号线D-line，通过设置虚拟信号线D-line可以提升显示面板的显示均一性。
如图8所示，在示例性实施例中，第四导电层5可以包括第二电极结构Com，第二电极结构Com可以用于形成公共电极Vcom以及存储电容Cst的第二电极。图11a为图2中完整第二电极结构的结构示意图，如图8、图11a所示，第二电极结构Com可以包括狭缝电极，具体地，狭缝电极可以包括狭缝部Com1和位于相邻狭缝部Com1之间的条状电极部，条状电极部可以包括多个第一条状部Com2和多个第二条状部Com3，第一条状部Com2的延伸方向与第二条状部Com3的延伸方向相交，并且第一条状部Com2和第二条状部Com3在第二弯折部Com4处连接。与第一电极结构Pix中的第一弯折部Pix3类似，第二弯折部Com4可以位于第二电极结构Com在列方向的中间位置，并且第二弯折部Com4和第一弯折部Pix3在衬底基板的正投影可以重合。当然，在其他实施例中，第二电极结构Com还可以为其他结构，例如可以为电极块等。
第二电极结构Com在衬底基板的正投影与第一电极结构Pix在衬底基板的正投影具有交叠部，因为第一电极结构Pix可以形成存储电容Cst的第一极，第二电极结构Com可以形成存储电容Cst的第二极，因此，第一电极结构Pix与第二电极结构Com在衬底基板的正投影的交叠面积决定了存储电容Cst的大小。在示例性实施例中，可以增加第一电极结构Pix在衬底基板的正投影面积来提升第一端电极结构与第二电极结构Com的交叠面积，从而增大存储电容Cst，具体可参见后续实施例的介绍。
可以理解的，显示面板可以包括显示区和非显示区，非显示区围绕于显示区，本公开可以在非显示区设置公共电极线，第二电极结构Com可以延伸至非显示区与公共电极线进行连接。
图11b为第一导电层和第三导电层的叠层版图，如图11b所示，在示例性实施例中，栅极信号线Gate的主体部G0在衬底基板的正投影具有在列方向上相对的第一侧边L1和第二侧边L2，第一侧边L1位于第二 侧边L2远离对应第一电极结构Pix在衬底基板的正投影的一侧，第一侧边L1和第二侧边L2之间具有第一距离d1；第一电极结构Pix在衬底基板的正投影和与其对应的第二侧边L2之间具有第二距离d2，第二距离d2大于等于2.5μm，且第一距离d1大于第二距离d2。本示例性实施例通过将栅极信号线与第一电极结构Pix在列方向的距离设置为大于等于2.5μm，可以防止像素电极与栅极信号线之间因为距离过近而产生较大的栅极与像素电极电容Cgs，由此可以避免公式(1)中的△vp增大而引起的flicker不良现象。
图12为根据本公开另一种实施方式的显示面板的结构版图，图13为图12中第一导电层的结构版图，图14为第一导电层和第二导电层的叠层版图。如图12、图14所示，在示例性实施例中，第一导电层1还可以包括第一导电线11，第一导电线11在衬底基板的正投影可以沿行方向延伸，第一导电线11可以由显示区延伸至非显示区，并连接非显示区的公共电极线，第一导电线11在衬底基板的正投影与第一弯折部Pix3在衬底基板的正投影至少部分交叠。其中，第一导电线11连接公共电极线，因此第一导电线11构成公共电极Vcom的一部分，由此通过将第一导电线11与第一弯折部Pix3进行交叠，从而增加像素电极Vpixel与公共电极Vcom的交叠面积而增大存储电容Cst。如上文所述，第一弯折部Pix3可以位于第一电极结构Pix在列方向的中间位置，由此本示例性实施例即是在第一电极结构Pix在列方向的中间位置形成第一导电线11来提升公共电极Vcom与像素电极Vpixel的交叠面积，从而增大存储电容Cst。本示例性实施例中，通过在第一电极结构Pix在列方向的中间位置形成第一导电线11，该位置与第一导电层1的其他结构(包括栅极信号线Gate)之间的距离较远，因此不会影响显示面板在Array阶段产品的设计参数。
如图12、图14所示，在示例性实施例中，第一导电线11在衬底基板的正投影可以覆盖第一弯折部Pix3在衬底基板的正投影，这样在不影响像素开口率的情况下可以充分利用像素空间提升第一导电线11在列方向的宽度，从而增加第一导电线11与像素电极Vpixel之间的交叠量， 进而增大存储电容Cst的增加量。
如图14所示，在示例性实施例中，第一导电线11在衬底基板的正投影具有在列方向上具有相对的第三侧边L3和第四侧边L4，第三侧边L3与第四侧边L4在列方向具有第一宽度D1；第一电极结构Pix在衬底基板的正投影在列方向具有相对的第五侧边L5和第六侧边L6，第五侧边L5和第六侧边L6在列方向具有第二宽度D2；第一宽度D1与第二宽度D2之比可以为0.05～0.06，例如可以为0.05，0.054，0.055，0.058，0.06等。由此，可以在Array阶段根据像素电极的尺寸来确定第一导电线11的宽度，确定出存储电容Cst的电容增加量。
图15为根据本公开再一种实施方式的显示面板的结构版图，图16a为图15中第一导电层的结构版图，图16b为图15中第一导电层的一个重复单元的结构版图，图17为第一导电层和第二导电层的叠层版图。如图15、图16a所示，在示例性实施例中，第一导电层1还可以包括第二导电线12和第三导电线13，第二导电线12、第三导电线13在衬底基板的正投影均可以沿行方向延伸，并且第二导电线12、第三导电线13均可以延伸至非显示区连接公共电极线，从而第二导电线12、第三导电线13形成公共电极Vcom的部分结构。如上文所述，在第一方向X上相邻的第一像素驱动电路P1和第二像素驱动电路P2可以构成一个重复单元Q，如图16b所示，在同一重复单元Q中，第二导电线12和第三导电线13位于第一栅极信号线Gate11和第二栅极信号线Gate22之间，第二导电线12在衬底基板的正投影与第一电极部Pix1远离第一弯折部Pix3的一端在衬底基板的正投影相交；第三导电线13在衬底基板的正投影与第二电极部Pix2远离第一弯折部Pix3的一端在衬底基板的正投影相交。换言之，第二导电线12在第一电极结构Pix靠近第一栅极信号线Gate1的一侧与第一电极结构Pix交叠，第三导电线13在像素单元的第一电极结构Pix靠近第二栅极信号线Gate2的一侧与第一电极结构Pix交叠。相当于在像素电极Vpixel在列方向的两端形成与像素电极Vpixel交叠的第二导电线12和第三导电线13，由此来增加公共电极Vcom与像素电极Vpixel的交叠面积，从而增大存储电容Cst。本示例性实施例通过在像素 单元在列方向的两侧设置第二导电线12和第三导电线13，通过形成双导电线来与像素电极Vpixel进行交叠，由此可增加的电容量较大，即能够利用像素空间充分增大存储电容Cst的电容增加量。第一栅极信号线Gate11为第一像素驱动电路P1中的栅极信号线，第二栅极信号线Gate22为第二像素驱动电路P2中的栅极信号线。
本示例性实施例中，第二导电线12和第三导电线13可具有相同的结构，并且第二导电线12和第三导电线13在衬底基板的正投影可以关于第一弯折部Pix3在衬底基板的正投影轴对称。
如图17所示，在示例性实施例中，第二导电线12和第三导电线13在所衬底基板的正投影均具有在列方向相对的第七侧边L7和第八侧边L8，第七侧边L7位于第八侧边L8靠近对应栅极信号线在衬底基板的正投影的一侧，且第七侧边L7与第八侧边L8在列方向上具有第三宽度D3；栅极信号线的主体部在衬底基板的正投影具有在列方向上相对的第一侧边L1和第二侧边L2，第一侧边L1位于第二侧边L2远离对应第一电极结构Pix在衬底基板的正投影的一侧，第七侧边L7与对应栅极信号线在衬底基板的正投影的第二侧边L2在列方向上具有第四距离d4。本示例性实施例中，可以通过减小栅极信号线Gate在列方向的宽度来给第二导电线12和第三导电线13预留一定空间，从而可以将第一电极结构Pix沿列方向向两侧延伸，使得第一电极结构Pix在列方向的两端与所设置的第二导电线12和第三导电线13分别交叠，由此来增大存储电容Cst，由此可增加的存储电容Cst的电容量更大。可以理解的，第四距离d4受限于工艺条件，在工艺能力允许的情况下，第四距离d4可以尽量小，以增大第二导电线12和第三导电线13在列方向的宽度，增大其与第一电极结构Pix的交叠面积。
如图17所述，在示例性实施例中，第七侧边L7与第八侧边L8在列方向上具有第三宽度D3；第一电极结构Pix在衬底基板的正投影在列方向具有相对的第五侧边L5和第六侧边L6，第五侧边L5和第六侧边L6在列方向具有第二宽度D2；第三宽度D3与第二宽度D2之比可以为0.05～0.06，例如可以为0.05，0.054，0.055，0.058，0.06等。从而可以在Array阶段根据像素电极的尺寸来确定第二导电线12和第三导电线13 的宽度。
图18为图12中第三导电层的结构版图，图19为图15中第三导电层的结构版图，如图18、图19所示，在示例性实施例中，第三导电层4还可以不包括虚拟信号线D-line，即在行方向相邻的两个重复单元Q的间隙内不设置虚拟信号线D-line，在此基础上，因为该间隙的存在，可以增加第二导电层3中第一电极结构Pix在行方向的延伸长度，从而提升第一电极结构Pix于第二电极结构Com的交叠面积，由此来增大存储电容Cst的电容量。本示例性实施例可以在不影响像素显示效果的情况下增大存储电容Cst的电容量。
参考图2和图15，在图2所示版图结构中，第三导电层4包含有虚拟信号线D-line，相应地，如图10所示，第一像素驱动电路P1中的第一电极结构Pix在衬底基板的正投影与行方向相邻重复单元中的第二像素驱动电路P2中的第一电极结构Pix在衬底基板的正投影之间在行方向上具有第五距离d5。在图15所示结构中，第三导电层4取消虚拟信号线D-line，相应地，如图17所示，在行方向相邻的任意两个重复单元中，第一像素驱动电路P1中的第一电极结构Pix在衬底基板的正投影和相邻重复单元中的第二像素驱动电路P2中的第一电极结构Pix在衬底基板的正投影之间在水平方向上具有第六距离d6。第五距离d5大于第六距离d6。
继续参考图2和图15，在图2所示版图结构中，第三导电层4包含有虚拟信号线D-line，此结构下，如图10所示，同一重复单元中，第一电极结构Pix在衬底基板的正投影与第二电极结构Com在衬底基板的正投影具有第一交叠面积S1，第一交叠面积S1小于第二交叠面积S2。在图15所示版图结构中，第三导电层4取消虚拟信号线D-line，此结构下，如图17所示，第一电极结构Pix的面积被增加，同一重复单元中的第一电极结构Pix在衬底基板的正投影与第二电极结构Com在衬底基板的正投影具有第二交叠面积S2，第一交叠面积S1小于第二交叠面积S2，即在第四导电层5中的第二电极结构Com的尺寸不变的情况下，通过取消第三导电层4的虚拟信号线D-line来提升第二导电层3的第一电极结构 Pix的尺寸，从而增加第一电极结构Pix和第二电极结构Com的交叠面积，由此而增大了存储电容Cst。在示例性实施例中，第一交叠面积S1与第二交叠面积S2之比可以为0.77～0.79，例如可以为0.77，0.775，0.78,0.785，0.79等。
值得注意的是，本公开上述实施例通过增加存储电容Cst的电容量来改善屏幕抖动的方案中，如表2所示，虽然存储电容Cst的电容量增加，但是并不会显著增加显示面板的负载。由于产品使用了低频驱动，产品的整体功耗下降。通过图1的像素等效电路图可知，存储电容Cst与液晶电容Clc并联，且Clc电容较小，实际Cst的变化对屏幕整体loading影响较小。可见，本公开通过增加存储电容Cst的电容量，可以改善显示面板在低频驱动时的抖动现象，并且还不会显著增加显示面板的负载。
表2
Figure PCTCN2022128358-appb-000003
此外，本公开还提供一种显示装置，该显示装置包括本公开上述任意实施例所述的显示面板。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (20)

  1. 一种显示面板，其中，所述显示面板包括沿第一方向和第二方向阵列分布的多个像素驱动电路，所述像素驱动电路包括驱动晶体管，所述驱动晶体管的栅极连接栅极信号线，所述第一方向与所述第二方向相交；所述显示面板还包括：
    衬底基板；
    第一导电层，位于所述衬底基板的一侧，所述第一导电层包括：
    多条栅极信号线，所述栅极信号线包括主体部和多个增设部，所述主体部在所述衬底基板的正投影沿所述第一方向延伸，所述多个增设部在所述第一方向上间隔分布且在所述第二方向上连接于所述主体部的一侧，所述增设部用于形成所述驱动晶体管的栅极；
    有源层，位于所述第一导电层的一侧，所述有源层包括：
    多个有源结构，与所述多个增设部对应设置，所述多个有源结构在所述衬底基板的正投影彼此分离，所述有源结构包括彼此分离的多个有源部，所述有源部用于形成所述驱动晶体管的沟道区；
    其中，一个所述增设部对应多个所述有源部，且所述增设部在所述衬底基板的正投影覆盖与其对应的多个所述有源部在所述衬底基板的正投影。
  2. 根据权利要求1所述的显示面板，其中，所述多个有源部包括第一有源部和第二有源部，所述第一有源部和所述第二有源部在所述第一方向上间隔设置；
    其中，所述增设部在所述衬底基板的正投影覆盖与其对应的所述第一有源部在所述衬底基板的正投影和所述第二有源部在所述衬底基板的正投影。
  3. 根据权利要求2所述的显示面板，其中，所述驱动晶体管的第一极连接像素电极；所述第一方向为行方向，所述第二方向为列方向；
    所述显示面板还包括：
    第二导电层，位于所述有源层背离所述衬底基板的一侧，所述第二导电层包括：
    多个第一电极结构，与所述多个增设部一一对应，所述第一电极结 构用于形成所述像素电极；
    其中，所述多个像素驱动电路包括第一像素驱动电路和第二像素驱动电路，所述第一像素驱动电路和所述第二像素驱动电路在所述行方向上依次交替分布，且所述第一像素驱动电路位于同一列，所述第二像素驱动电路位于同一列；
    所述第一像素驱动电路中的栅极信号线为第一栅极信号线，所述第二像素驱动电路中的栅极信号线为第二栅极信号线；
    本行所述第一栅极信号线、第二栅极信号线在所述衬底基板的正投影分别位于本行第一电极结构在所述衬底基板的正投影在列方向的两侧；
    本行第一栅极信号线中的增设部位于对应主体部与上一行第二栅极信号线的主体部之间，上一行第二栅极信号线中的增设部位于对应主体部与本行第一栅极信号线的主体部之间。
  4. 根据权利要求3所述的显示面板，其中，所述增设部在所述衬底基板的正投影覆盖与其对应的所述有源结构在所述衬底基板的正投影。
  5. 根据权利要求4所述的显示面板，其中，所述有源结构在所述衬底基板的正投影的边沿与所述增设部在所述衬底基板的正投影的边沿之间的距离大于等于2.5μm。
  6. 根据权利要求4所述的显示面板，其中，所述主体部在所述衬底基板的正投影具有在列方向上相对的第一侧边和第二侧边，所述第一侧边位于所述第二侧边远离对应第一电极结构在所述衬底基板的正投影的一侧，所述第一侧边和所述第二侧边之间具有第一距离；
    所述第一电极结构在所述衬底基板的正投影和与其对应的第二侧边之间具有第二距离，所述第二距离大于等于2.5μm，且所述第一距离大于所述第二距离。
  7. 根据权利要求3所述的显示面板，其中，所述像素驱动电路还包括存储电容，所述存储电容的第一极连接所述像素电极，第二极连接公共电极；所述显示面板还包括：
    第四导电层，位于所述第二导电层背离所述衬底基板的一侧，所述第四导电层包括：
    多个第二电极结构，各所述第二电极结构彼此连接形成网格结构， 所述第二电极结构在所述衬底基板的正投影与所述第一电极结构在所述衬底基板的正投影部分交叠；
    其中，所述第一电极结构还用于形成所述存储电容的第一极，所述第二电极结构还用于形成所述存储电容的第二极。
  8. 根据权利要求7所述的显示面板，其中，所述第一电极结构包括第一电极部和第二电极部，所述第一电极部的延伸方向与所述第二电极部的延伸方向相交；
    所述第一电极部的延伸方向与所述列方向具有第一夹角，所述第二电极部的延伸方向与所述列方向具有第二夹角，所述第一夹角与所述第二夹角相同，且所述第一电极部和所述第二电极部的延伸长度相同，且连接于第一弯折部。
  9. 根据权利要求8所述的显示面板，其中，所述第一导电层还包括：
    第一导电线，在所述衬底基板的正投影沿所述行方向延伸，所述第一导电线连接所述第二电极结构，所述第一导电线在所述衬底基板的正投影与所述第一弯折部在所述衬底基板的正投影至少部分交叠。
  10. 根据权利要求9所述的显示面板，其中，所述第一导电线在所述衬底基板的正投影覆盖所述第一弯折部在所述衬底基板的正投影。
  11. 根据权利要求8所述的显示面板，其中，所述第一导电线在所述衬底基板的正投影具有在列方向上具有相对的第三侧边和第四侧边，所述第三侧边与所述第四侧边在所述列方向具有第一宽度；
    所述第一电极结构在衬底基板的正投影在所述列方向具有相对的第五侧边和第六侧边，所述第五侧边和所述第六侧边在所述列方向具有第二宽度；
    所述第一宽度与所述第二宽度之比为0.05～0.06。
  12. 根据权利要求8所述的显示面板，其中，所述显示面板包括多个重复单元，所述重复单元包括在行方向相邻的所述第一像素驱动电路和所述第二像素驱动电路；
    所述第一导电层还包括：
    第二导电线，在所述衬底基板的正投影沿所述行方向延伸，所述第二导电线连接所述第二电极结构；
    第三导电线，在所述衬底基板的正投影沿所述行方向延伸，所述第三导电线连接所述第二电极结构；
    其中，同一重复单元中，所述第二导电线和所述第三导电线位于所述第一栅极信号线和所述第二栅极信号线之间，
    所述第二导电线在所述衬底基板的正投影与所述第一电极部远离所述第一弯折部的一端在所述衬底基板的正投影相交；
    所述第三导电线在所述衬底基板的正投影与所述第二电极部远离所述第一弯折部的一端在所述衬底基板的正投影相交。
  13. 根据权利要求12所述的显示面板，其中，所述第二导电线和所述第三导电线在所衬底基板的正投影均具有在列方向相对的第七侧边和第八侧边，所述第七侧边与所述第八侧边在所述列方向上具有第三宽度；所述第一电极结构在衬底基板的正投影在所述列方向具有相对的第五侧边和第六侧边，所述第五侧边和所述第六侧边在所述列方向具有第二宽度；
    所述第三宽度与所述第二宽度之比为0.05～0.06。
  14. 根据权利要求9或12所述的显示面板，其中，同一重复单元中的所述第一电极结构在所述衬底基板的正投影与所述第二电极结构在所述衬底基板的正投影具有第二交叠面积；
    在行方向相邻的任意两个重复单元中，第一像素驱动电路中的第一电极结构在所述衬底基板的正投影和相邻重复单元中的第二像素驱动电路中的第一电极在所述衬底基板的正投影之间在所述水平方向上具有第六距离。
  15. 根据权利要求14所述的显示面板，其中，所述显示面板还包括：
    第三导电层，位于所述第二导电层背离所述衬底基板的一侧，所述第三导电层包括：
    虚拟信号线，在所述衬底基板的正投影沿列方向延伸，且位于行方向相邻的两个重复单元在所述衬底基板的正投影之间；
    其中，同一重复单元中，所述第一电极结构在所述衬底基板的正投影与所述第二电极结构在所述衬底基板的正投影具有第一交叠面积，所述第一交叠面积小于所述第二交叠面积；
    第一像素驱动电路中的第一电极结构在所述衬底基板的正投影与行方向相邻重复单元中的第二像素驱动电路中的第一电极结构在所述衬底基板的正投影之间在所述行方向上具有第五距离，所述第五距离大于所述第六距离。
  16. 根据权利要求15所述的显示面板，其中，所述第二交叠面积与所述第一交叠面积之比为0.77～0.79。
  17. 根据权利要求3所述的显示面板，其中，所述驱动晶体管的第一极连接数据信号端；
    所述有源结构还包括：
    第一子有源部，与所述第一有源部对应设置且连接于所述第一有源部的一侧，所述第一子有源部用于形成所述驱动晶体管的第一极；
    第二子有源部，与所述第二有源部对应设置且连接于所述第二有源部远离所述第一有源部的一侧，所述第二子有源部用于形成所述驱动晶体管的第二极；
    第三子有源部，连接于与其对应的所述第一有源部和所述第二有源部之间；
    所述显示面板还包括：
    第三导电层，位于所述第二导电层背离所述衬底基板的一侧，所述第三导电层包括：
    第一导电部，在所述衬底基板的正投影覆盖所述第一子有源部在所述衬底基板的正投影，且所述第一导电部与所述第一子有源部电连接，以连接所述驱动晶体管的第一极；
    第二导电部，在所述衬底基板的正投影覆盖所述第二子有源部在所述衬底基板的正投影，且所述第二导电部与所述第二子有源部电连接，以连接所述驱动晶体管的第二极；
    第三导电部，与所述第三子有源部一一对应设置，所述第三导电部位于所述第一导电部和所述第二导电部之间，所述第三导电部在所述衬底基板的正投影覆盖对应所述第三子有源部在所述衬底基板的正投影。
  18. 根据权利要求17所述的显示面板，其中，
    所述第三导电层还包括：
    数据信号线，在所述衬底基板的正投影沿所述列方向延伸，所述数据信号线连接所述第一导电部，以连接所述驱动晶体管的第一极；
    其中，所述显示面板包括多个重复单元，所述重复单元包括在行方向相邻的所述第一像素驱动电路和所述第二像素驱动电路；
    本行重复单元中的第一像素驱动电路与上一行重复单元中的第二像素驱动电路复用同一所述数据信号线。
  19. 根据权利要求18所述的显示面板，其中，
    所述第二导电层还包括：
    备用导电部，位于相邻所述第一像素驱动电路和所述第二像素驱动电路之间；
    其中，所述备用导电部在所述衬底基板的正投影位于对应所述数据信号线在所述衬底基板的正投影内。
  20. 一种显示装置，其中，包括权利要求1-19任一项所述的显示面板。
PCT/CN2022/128358 2022-10-28 2022-10-28 一种显示面板及显示装置 WO2024087198A1 (zh)

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CN104730781A (zh) * 2015-03-27 2015-06-24 京东方科技集团股份有限公司 Ads阵列基板及其制作方法、显示装置
CN112885850A (zh) * 2021-01-29 2021-06-01 合肥京东方卓印科技有限公司 显示面板、显示装置
CN114093898A (zh) * 2021-11-25 2022-02-25 京东方科技集团股份有限公司 阵列基板、显示面板及显示装置
US20220310023A1 (en) * 2020-08-31 2022-09-29 Chengdu Boe Optoelectronics Technology Co., Ltd. Display substrate, method for manufacturing the same, and display device
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CN104730781A (zh) * 2015-03-27 2015-06-24 京东方科技集团股份有限公司 Ads阵列基板及其制作方法、显示装置
US20220310023A1 (en) * 2020-08-31 2022-09-29 Chengdu Boe Optoelectronics Technology Co., Ltd. Display substrate, method for manufacturing the same, and display device
CN112885850A (zh) * 2021-01-29 2021-06-01 合肥京东方卓印科技有限公司 显示面板、显示装置
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