WO2024087166A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2024087166A1
WO2024087166A1 PCT/CN2022/128241 CN2022128241W WO2024087166A1 WO 2024087166 A1 WO2024087166 A1 WO 2024087166A1 CN 2022128241 W CN2022128241 W CN 2022128241W WO 2024087166 A1 WO2024087166 A1 WO 2024087166A1
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Prior art keywords
electrode
coupled
transistor
line
sub
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PCT/CN2022/128241
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English (en)
French (fr)
Inventor
袁粲
袁志东
吴刘
丁录科
李永谦
许程
周丹丹
张大成
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280003844.4A priority Critical patent/CN118266081A/zh
Priority to PCT/CN2022/128241 priority patent/WO2024087166A1/zh
Priority to PCT/CN2023/071892 priority patent/WO2024087402A1/zh
Priority to PCT/CN2023/071888 priority patent/WO2024087401A1/zh
Priority to CN202380008169.9A priority patent/CN118284975A/zh
Priority to CN202380008165.0A priority patent/CN118266020A/zh
Publication of WO2024087166A1 publication Critical patent/WO2024087166A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate and a display device.
  • An object of the present disclosure is to provide a display substrate and a display device.
  • a first aspect of the present disclosure provides a display substrate, comprising: a base substrate, and a plurality of data lines and a plurality of sub-pixels disposed on the base substrate; the sub-pixels include a sub-pixel driving circuit and a light-emitting element; the sub-pixel driving circuit includes a driving transistor and a data writing transistor, and the light-emitting element includes a first electrode;
  • the second electrode of the driving transistor is coupled to the corresponding first electrode through a first connection structure;
  • the first electrode of the data writing transistor is coupled to the corresponding data line through a second connection structure;
  • the first connection structure and the second connection structure are both located in the non-opening area of the sub-pixel, and the orthographic projection of the first connection structure on the base substrate and the orthographic projection of the second connection structure on the base substrate are arranged along a first direction;
  • the orthographic projection of the second connection structure on the base substrate is arranged along a second direction with the opening area of the sub-pixel, and the second direction intersects with the first direction.
  • the first connection structure includes: a second conductive connection portion, a first via structure, a fifth conductive connection portion and a second via structure;
  • the second conductive connection portion is coupled to the second electrode of the driving transistor, the second conductive connection portion is coupled to the fifth conductive connection portion through the first via structure, and the fifth conductive connection portion is coupled to the corresponding first electrode through the second via structure.
  • the second connection structure includes: a fourth conductive connection portion and a third via structure; the fourth conductive connection portion is coupled to the first electrode of the data writing transistor, and the fourth conductive connection portion is coupled to the corresponding data line through the third via structure.
  • the display substrate further includes a first organic layer and a second organic layer stacked in sequence in a direction away from the base substrate, the first via structure penetrates the first organic layer, and the second via structure penetrates the second organic layer;
  • the second conductive connection portion is located between the first organic layer and the base substrate, and the fifth conductive connection portion is located between the first organic layer and the second organic layer.
  • the third via structure passes through the first organic layer, and the fourth conductive connection portion is located between the first organic layer and the base substrate.
  • the display substrate further includes: a first passivation layer and a second passivation layer; the first passivation layer is located between the first organic layer and the second passivation layer, and the second passivation layer is located between the first passivation layer and the second organic layer;
  • the first via structure and the third via structure both penetrate the first passivation layer, and the second via structure penetrates the second passivation layer; the fifth conductive connection portion is located between the first passivation layer and the second passivation layer.
  • the display substrate further includes: an auxiliary electrode, a third connection structure and a second electrode layer; the auxiliary electrode is coupled to the second electrode layer through the third connection structure;
  • the third connection structure is located in the non-opening area of the sub-pixel, and the orthographic projection of the third connection structure on the base substrate is arranged along a first direction with the orthographic projection of the first connection structure on the base substrate.
  • the display substrate further includes: an auxiliary electrode, a third connection structure and a second electrode layer; the auxiliary electrode is coupled to the second electrode layer through the third connection structure;
  • the third connection structure is located in the non-opening area of the sub-pixel, and the orthographic projection of the third connection structure on the base substrate is at least partially offset from the orthographic projection of the first connection structure on the base substrate.
  • the display substrate further comprises a second organic layer and a pixel defining layer which are sequentially stacked in a direction away from the base substrate;
  • the third connection structure includes: a fourth via structure, a connection pattern and a fifth via structure; the auxiliary electrode is located between the second organic layer and the base substrate, at least a portion of the second electrode layer is located on a side of the pixel defining layer facing away from the base substrate, at least a portion of the connection pattern is located between the second organic layer and the pixel defining layer, the fourth via structure penetrates the second organic layer, and the fifth via structure penetrates the pixel defining layer;
  • connection pattern is coupled to the auxiliary electrode through the fourth via structure, and the connection pattern is coupled to the second electrode layer through the fifth via structure.
  • the plurality of sub-pixels are divided into a plurality of repeating units distributed in an array, each repeating unit includes two sub-units arranged along a first direction, and each sub-unit includes a plurality of the sub-pixels arranged along the first direction;
  • the orthographic projection of the auxiliary electrode on the base substrate is located between the orthographic projections of the two sub-units on the base substrate.
  • the display substrate further includes a power line and a power compensation line;
  • the sub-pixel driving circuit further includes a light emitting control transistor; a first electrode of the light emitting control transistor is coupled to the power supply compensation line, and a second electrode of the light emitting control transistor is coupled to the first electrode of the driving transistor;
  • the power compensation line is coupled to the power line through a sixth via structure, and the sixth via structure is located in a non-opening area of the sub-pixel.
  • the display substrate further includes a first organic layer
  • the power compensation line is located between the first organic layer and the base substrate
  • the power line is located on a side of the first organic layer facing away from the base substrate
  • the sixth via structure penetrates the first organic layer
  • an orthographic projection of the power line on the base substrate and an orthographic projection of the repeating unit on the base substrate are alternately arranged along the first direction.
  • the display substrate further includes: a plurality of light emitting control lines, a power supply line, an initialization signal line, a reference signal line, a plurality of first scanning lines, a plurality of second scanning lines, a plurality of third scanning lines and a plurality of partition control lines;
  • the sub-pixel driving circuit further includes: a compensation transistor, a reset transistor, a light emitting control transistor, a write control transistor and a storage capacitor;
  • the gate of the data writing transistor is coupled to the corresponding first scanning line, and the second electrode of the data writing transistor is coupled to the first electrode of the writing control transistor;
  • the second electrode of the write control transistor is coupled to the gate of the drive transistor, and the gate of the write control transistor is coupled to the corresponding partition control line;
  • the gate of the compensation transistor is coupled to the corresponding second scan line, the first electrode of the compensation transistor is coupled to the reference signal line, and the second electrode of the compensation transistor is coupled to the first electrode of the write control transistor;
  • the gate of the reset transistor is coupled to the corresponding third scan line, the first electrode of the reset transistor is coupled to the initialization signal line, and the second electrode of the reset transistor is coupled to the second electrode of the drive transistor;
  • the gate of the light emitting control transistor is coupled to the corresponding light emitting control line, the first electrode of the light emitting control transistor is coupled to the power line, and the second electrode of the light emitting control transistor is coupled to the first electrode of the driving transistor;
  • the first plate of the storage capacitor is coupled to the gate of the driving transistor, and the second plate of the storage capacitor is coupled to the second electrode of the driving transistor.
  • a second aspect of the present disclosure provides a display device, comprising the above-mentioned display substrate.
  • FIG1 is a circuit diagram of a sub-pixel driving circuit provided in an embodiment of the present disclosure.
  • FIG2 is a schematic diagram of a circuit structure of a repeating unit provided in an embodiment of the present disclosure
  • FIG3 is a schematic diagram of the resistance-capacitance equivalent of a partition control line provided by an embodiment of the present disclosure
  • FIG4 is a driving timing diagram provided by an embodiment of the present disclosure.
  • FIG5 is a schematic diagram of the layout of the active layer and the first gate metal layer of the repeating unit provided in an embodiment of the present disclosure
  • FIG6 is a schematic diagram of a layout in which a second gate metal layer is added on the basis of FIG5 ;
  • FIG7 is a schematic diagram of the layout of the second gate metal layer in FIG6 ;
  • FIG8 is a schematic diagram of a layout in which a first source/drain metal layer is added on the basis of FIG6 ;
  • FIG9 is a schematic diagram of the layout of via holes formed on the interlayer insulating layer in FIG8 ;
  • FIG10 is a schematic diagram of the layout of the first source and drain metal layer in FIG8 ;
  • FIG11 is a schematic diagram of a layout in which a second source/drain metal layer is added on the basis of FIG8 ;
  • FIG12 is a schematic diagram of the layout of via holes formed on the first organic layer in FIG11;
  • FIG13 is a schematic diagram of the layout of via holes formed on the first passivation layer in FIG11;
  • FIG14 is a schematic diagram of the layout of the second source/drain metal layer in FIG11 ;
  • FIG15 is a schematic diagram of a layout in which a first electrode layer is added on the basis of FIG11;
  • FIG16 is a schematic diagram of the layout of via holes formed on the second passivation layer in FIG15 ;
  • FIG17 is a schematic diagram of the layout of via holes formed on the second organic layer in FIG15 ;
  • FIG18 is a schematic diagram of the layout of the first electrode layer in FIG15 ;
  • FIG19 is a schematic diagram of a layout in which a first pixel defining layer is added to the layout in FIG15;
  • FIG20 is a schematic diagram of the layout of the first pixel definition layer in FIG19;
  • FIG21 is a schematic diagram of a layout in which a second pixel defining layer opening is added based on FIG19;
  • FIG22 is a schematic diagram of the layout of the openings of the second pixel definition layer in FIG21;
  • FIG23 is a schematic diagram of a layout in which a second pixel defining layer opening is added based on FIG19;
  • FIG24 is a schematic cross-sectional view along the A1A2 direction in FIG23 .
  • an embodiment of the present disclosure provides a display substrate, comprising: a base substrate, and a plurality of data lines DA and a plurality of sub-pixels disposed on the base substrate; the sub-pixels include a sub-pixel driving circuit and a light-emitting element EL; the sub-pixel driving circuit includes a driving transistor DRT and a data writing transistor T1, and the light-emitting element EL includes a first electrode;
  • the second electrode of the driving transistor DRT is coupled to the corresponding first electrode through a first connection structure 81; the first electrode of the data writing transistor T1 is coupled to the corresponding data line DA through a second connection structure 82;
  • the first connection structure 81 and the second connection structure 82 are both located in the non-opening area 61 of the sub-pixel, and the orthographic projection of the first connection structure 81 on the base substrate and the orthographic projection of the second connection structure 82 on the base substrate are arranged along a first direction;
  • the orthographic projection of the second connection structure 82 on the base substrate is arranged along a second direction with the opening area 60 of the sub-pixel, and the second direction intersects with the first direction.
  • the plurality of data lines DA are arranged along the first direction, and the data line DA includes at least a portion extending along the second direction.
  • the plurality of sub-pixels are distributed in an array, and the plurality of sub-pixels are divided into a plurality of sub-pixel columns, and each sub-pixel included in each sub-pixel column is respectively coupled to a corresponding data line DA.
  • the sub-pixel includes a sub-pixel driving circuit and a light-emitting element
  • the sub-pixel driving circuit is coupled to a first electrode included in the light-emitting element, and is used to provide a driving signal to the first electrode of the light-emitting element to drive the light-emitting element to emit light.
  • the data line DA and the first electrode are both located on the side of the sub-pixel driving circuit facing away from the substrate.
  • a thicker insulating layer is provided between the data line DA and the first electrode of the data writing transistor T1
  • a thicker insulating layer is also provided between the first electrode and the second electrode of the driving transistor DRT. Therefore, the first connection structure 81 and the second connection structure 82 both include a deeper via structure.
  • the first connection structure 81 and the second connection structure 82 are avoided from occupying the space of the opening area, thereby ensuring the aperture ratio of the display substrate and avoiding the first connection structure 81 and the second connection structure 82 from affecting the flatness of the light-emitting element.
  • the orthographic projection of the first connection structure 81 on the base substrate is arranged along the first direction with the orthographic projection of the second connection structure 82 on the base substrate; the orthographic projection of the second connection structure 82 on the base substrate is arranged along the second direction with the opening area of the sub-pixel; the first connection structure 81 and the second connection structure 82 are both located on the same side of the opening area along the second direction, and the first connection structure 81 and the second connection structure 82 occupy a smaller space in the second direction, so that the first connection structure 81 and the second connection structure 82 can be centrally shielded, so that the size of the opening area in the second direction can be optimized, thereby effectively improving the aperture ratio of the display substrate and improving the service life of the display substrate.
  • the first connection structure 81 includes: a second conductive connection portion 52 , a first via structure, a fifth conductive connection portion 55 and a second via structure;
  • the second conductive connection portion 52 is coupled to the second electrode of the driving transistor DRT, the second conductive connection portion 52 is coupled to the fifth conductive connection portion 55 through the first via structure, and the fifth conductive connection portion 55 is coupled to the corresponding first electrode (the first electrode layer 42 includes multiple first electrodes) through the second via structure.
  • the first via structure includes a seventeenth via Via17 and a twentieth via Via20.
  • the second via structure includes a twenty-fourth via Via24 and a twenty-sixth via Via26.
  • the second conductive connection portion 52 is made of the first source-drain metal layer in the display substrate, and the fifth conductive connection portion 55 is made of the second source-drain metal layer in the display substrate.
  • the second connection structure 82 includes: a fourth conductive connection portion 54 and a third via structure; the fourth conductive connection portion 54 is coupled to the first electrode of the data writing transistor T1, and the fourth conductive connection portion 54 is coupled to the corresponding data line DA through the third via structure.
  • the third via structure includes a sixteenth via Via16 and a nineteenth via Via19.
  • the fourth conductive connection portion 54 is made of the first source-drain metal layer in the display substrate.
  • the display substrate includes the following layers stacked sequentially on the base substrate 70 in a direction away from the base substrate 70: a buffer layer 71, an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, an interlayer insulating layer ILD, a first source-drain metal layer, a first organic layer Resin1, a first passivation layer PVX1, a second source-drain metal layer, a second passivation layer PVX2, a second organic layer Resin2, a first electrode layer 42, a first pixel defining layer PDL1, a second pixel defining layer PDL2, a light-emitting functional layer, a second electrode layer 43, and an encapsulation layer.
  • the second electrode layer 43 receives a negative power signal VSS.
  • the display substrate further includes a first organic layer and a second organic layer sequentially stacked in a direction away from the base substrate, the first via structure penetrates the first organic layer, and the second via structure penetrates the second organic layer;
  • the second conductive connection portion 52 is located between the first organic layer and the base substrate, and the fifth conductive connection portion 55 is located between the first organic layer and the second organic layer.
  • the first organic layer and the second organic layer are both thicker insulating layers, so the first via structure and the second via structure are both deeper via structures.
  • the above-mentioned first connection structure 81 is arranged to be located in the non-opening area of the sub-pixel, so that the first via structure and the second via structure are both located in the non-opening area, avoiding the first via structure and the second via structure from occupying the space of the opening area, ensuring the opening ratio of the display substrate, and avoiding the first via structure and the second via structure from affecting the flatness of the light-emitting element.
  • the third via structure penetrates the first organic layer, and the fourth conductive connection portion 54 is located between the first organic layer and the base substrate.
  • the first organic layer is a thicker insulating layer, so the third via structure is a deeper via structure.
  • the second connection structure 82 is arranged to be located in the non-opening area of the sub-pixel, so that the third via structure is located in the non-opening area, avoiding the third via structure occupying the space of the opening area, ensuring the opening ratio of the display substrate, and avoiding the third via structure from affecting the flatness of the light-emitting element.
  • the orthographic projection of the first connecting structure 81 on the base substrate is arranged along the first direction with the orthographic projection of the second connecting structure 82 on the base substrate, and the orthographic projection of the second connecting structure 82 on the base substrate is arranged along the second direction with the opening area of the sub-pixel; so that the orthographic projection of the first via structure on the base substrate, the orthographic projection of the second via structure on the base substrate, and the orthographic projection of the third via structure on the base substrate are all located on the same side of the opening area along the second direction, and the first via structure, the second via structure and the third via structure occupy a smaller space in the second direction, so that the size of the opening area in the second direction can be optimized, thereby effectively improving the opening ratio of the display substrate and improving the service life of the display substrate.
  • the display substrate further includes: a first passivation layer and a second passivation layer; the first passivation layer is located between the first organic layer and the second passivation layer, and the second passivation layer is located between the first passivation layer and the second organic layer;
  • the first via structure and the third via structure both penetrate the first passivation layer, and the second via structure penetrates the second passivation layer; the fifth conductive connection portion 55 is located between the first passivation layer and the second passivation layer.
  • the display substrate further includes a first passivation layer and a second passivation layer, and the fifth conductive connection portion 55 is located between the first passivation layer and the second passivation layer, so that the conductive performance of the fifth conductive connection portion 55 can be better guaranteed.
  • the display substrate further includes: an auxiliary electrode 40 , a third connection structure 83 and a second electrode layer 43 ; the auxiliary electrode 40 is coupled to the second electrode layer 43 via the third connection structure 83 ;
  • the third connection structure 83 is located in the non-opening area 61 of the sub-pixel, and the orthographic projection of the third connection structure 83 on the base substrate is arranged along a first direction with the orthographic projection of the first connection structure 81 on the base substrate.
  • the display substrate includes a plurality of auxiliary electrodes 40 arranged along the first direction, and the auxiliary electrode 40 includes at least a portion extending along the second direction.
  • the third connection structure 83 includes a deeper via structure capable of penetrating the thicker insulating layer.
  • the third connection structure 83 is avoided from occupying the space of the opening area 60, thereby ensuring the aperture ratio of the display substrate and avoiding the third connection structure 83 from affecting the flatness of the light-emitting element.
  • the orthographic projection of the third connecting structure 83 on the base substrate is arranged along the first direction with the orthographic projection of the first connecting structure 81 on the base substrate, so that the first connecting structure 81 and the third connecting structure 83 are both located on the same side of the opening area 60 along the second direction, and the first connecting structure 81 and the third connecting structure 83 occupy a smaller space in the second direction, so that the size of the opening area 60 in the second direction can be optimized, thereby effectively improving the aperture ratio of the display substrate and improving the service life of the display substrate.
  • the display substrate further includes: an auxiliary electrode 40 , a third connection structure 83 and a second electrode layer; the auxiliary electrode 40 is coupled to the second electrode layer 43 via the third connection structure 83 ;
  • the third connection structure 83 is located in the non-opening area of the sub-pixel, and the orthographic projection of the third connection structure 83 on the base substrate is at least partially offset from the orthographic projection of the first connection structure 81 on the base substrate.
  • the layout space of the non-opening area can be better utilized, thereby reducing the layout difficulty of the first connecting structure 81 and the third connecting structure 83.
  • the display substrate further includes a second organic layer and a pixel defining layer sequentially stacked in a direction away from the base substrate;
  • the third connection structure 83 includes: a fourth via structure, a connection pattern 41 and a fifth via structure; the auxiliary electrode 40 is located between the second organic layer and the base substrate, at least a portion of the second electrode layer is located on a side of the pixel defining layer facing away from the base substrate, at least a portion of the connection pattern 41 is located between the second organic layer and the pixel defining layer, the fourth via structure penetrates the second organic layer, and the fifth via structure penetrates the pixel defining layer;
  • connection pattern 41 is coupled to the auxiliary electrode 40 through the fourth via structure, and the connection pattern 41 is coupled to the second electrode layer through the fifth via structure.
  • the pixel defining layer includes a first pixel defining layer and a second pixel defining layer stacked, the first pixel defining layer is located between the base substrate and the second pixel defining layer. At least a portion of the second electrode layer is located on a side of the second pixel defining layer that is away from the base substrate, and at least a portion of the connection pattern 41 is located between the second organic layer and the first pixel defining layer.
  • the fourth via structure includes a twenty-fifth via Via25 and a twenty-seventh via Via27.
  • the fifth via structure includes a twenty-eighth via Via28 and a twenty-ninth via Via29.
  • connection pattern 41 is arranged in the same layer as the first electrode layer 42.
  • the connection pattern 41 can be made of the same material as the first electrode layer, such as indium tin oxide material, or different materials can be used as long as the performance of conductive connection can be met.
  • the second electrode layer is coupled to the plurality of auxiliary electrodes 40 through the connection pattern 41 , thereby effectively reducing the voltage drop of the second electrode layer.
  • the plurality of sub-pixels are divided into a plurality of repeating units distributed in an array, each repeating unit includes two sub-units arranged along a first direction, and each sub-unit includes a plurality of the sub-pixels arranged along the first direction;
  • the orthographic projection of the auxiliary electrode 40 on the base substrate is located between the orthographic projections of the two sub-units on the base substrate.
  • the display substrate includes a plurality of repeating units, the plurality of repeating units are arranged in an array, and can be divided into a plurality of columns of repeating units arranged in sequence along the first direction, and each column of repeating units includes a plurality of repeating units arranged along the second direction.
  • the repeating unit includes a plurality of sub-pixels arranged along the first direction, for example: the repeating unit includes six sub-pixels arranged along the first direction, and the six sub-pixels include BRGBRG arranged along the first direction, where B represents a blue sub-pixel, R represents a red sub-pixel, and G represents a green sub-pixel.
  • a group of BRG represents a sub-unit.
  • the multiple sub-pixels included in the multiple repeating units are distributed in an array, and the multiple sub-pixels can be divided into multiple columns of sub-pixels, and the multiple columns of sub-pixels correspond one-to-one to the multiple data lines DA included in the display substrate.
  • the above arrangement of the orthographic projection of the auxiliary electrode 40 on the base substrate is located between the orthographic projections of the two sub-units on the base substrate, which makes better use of the layout drop and reduces the difficulty of the layout of the auxiliary electrode 40 .
  • the display substrate further includes a power line VDD and a power compensation line 30 ;
  • the sub-pixel driving circuit further includes a light emitting control transistor T_em; a first electrode of the light emitting control transistor T_em is coupled to the power supply compensation line 30, and a second electrode of the light emitting control transistor T_em is coupled to a first electrode of the driving transistor DRT;
  • the power compensation line 30 is coupled to the power line VDD through a sixth via structure, and the sixth via structure is located in a non-opening area of the sub-pixel.
  • the plurality of power lines VDD are arranged along the first direction, and the power line VDD includes at least a portion extending along the second direction.
  • the power lines VDD and the repeating unit columns are alternately arranged.
  • the sixth via structure includes an eighteenth via Via18 and a twenty-first via Via21.
  • the display substrate further includes a first organic layer
  • the power compensation line 30 is located between the first organic layer and the base substrate
  • the power line VDD is located on a side of the first organic layer facing away from the base substrate
  • the sixth via structure penetrates the first organic layer.
  • the sixth via structure is arranged in the non-opening area of the sub-pixel, which avoids the sixth connection structure occupying the space of the opening area, ensures the aperture ratio of the display substrate, and avoids the sixth connection structure affecting the flatness of the light-emitting element.
  • an orthographic projection of the power line VDD on the base substrate and an orthographic projection of the repeating unit on the base substrate are alternately arranged along the first direction.
  • the display substrate further includes: a plurality of light emitting control lines EM, a power line VDD, an initialization signal line Vini, a reference signal line Vref, a plurality of first scanning lines G1, a plurality of second scanning lines G2, a plurality of third scanning lines G3 and a plurality of partition control lines;
  • the sub-pixel driving circuit further includes: a compensation transistor T2, a reset transistor T3, a light emitting control transistor T_em, a write control transistor T_com and a storage capacitor Cst;
  • the gate of the data writing transistor T1 is coupled to the corresponding first scanning line G1, and the second electrode of the data writing transistor T1 is coupled to the first electrode of the writing control transistor T_com;
  • the second electrode of the write control transistor T_com is coupled to the gate of the drive transistor DRT, and the gate of the write control transistor T_com is coupled to the corresponding partition control line;
  • the gate of the compensation transistor T2 is coupled to the corresponding second scan line G2, the first electrode of the compensation transistor T2 is coupled to the reference signal line Vref, and the second electrode of the compensation transistor T2 is coupled to the first electrode of the write control transistor T_com;
  • the gate of the reset transistor T3 is coupled to the corresponding third scan line G3, the first electrode of the reset transistor T3 is coupled to the initialization signal line Vini, and the second electrode of the reset transistor T3 is coupled to the second electrode of the drive transistor DRT;
  • the gate of the light emitting control transistor T_em is coupled to the corresponding light emitting control line EM, the first electrode of the light emitting control transistor T_em is coupled to the power line VDD, and the second electrode of the light emitting control transistor T_em is coupled to the first electrode of the driving transistor DRT;
  • the first plate Cst1 of the storage capacitor Cst is coupled to the gate of the driving transistor DRT, and the second plate Cst2 of the storage capacitor Cst is coupled to the second electrode of the driving transistor DRT.
  • the initialization signal line Vini includes a plurality of first initial portions 21 and a plurality of second initial portions 22, the plurality of first initial portions 21 are arranged along the second direction, the plurality of second initial portions 22 are arranged along the first direction, the first initial portion 21 includes at least a portion extending along the first direction, the second initial portion 22 includes at least a portion extending along the second direction, the first initial portion 21 is coupled to each of the second initial portions 22, respectively, so that the initialization signal line Vini forms a grid structure, thereby effectively reducing the voltage drop of the initialization signal line Vini.
  • the active layer is used to form a channel portion, a first electrode and a second electrode included in each of the transistors.
  • the first gate metal layer is used to form the gate of each of the transistors, the first branch line 111 and the second initial portion 22 .
  • the second gate metal layer is used for the second substrate of the storage capacitor Cst.
  • the first source-drain metal layer is used to form some conductive connection parts, the reference signal line Vref, the first scan line G1, the second scan line G2, the third scan line G3, the light emitting control line EM and the first initial part 21.
  • the reference signal line Vref, the second scan line G2, the first scan line G1, the second branch line 112, the light emitting control line EM, the power supply compensation line 30, the third scan line G3 and the first initial part 21 coupled to the same repeating unit are arranged in sequence along the second direction.
  • the reference signal line Vref, the first scan line G1, the second scan line G2, the third scan line G3 and the light emitting control line EM all include at least a portion extending along the first direction.
  • the second source-drain metal layer is used to form the power line VDD, the data line DA, some conductive connection parts and the auxiliary electrode 40.
  • the second source-drain metal layer can effectively reduce the load of the signal line and provide technical support for medium and large-sized display products.
  • the auxiliary electrode 40 includes at least a portion extending along the second direction, and the auxiliary electrode 40 is coupled to the second electrode layer through a connection pattern 41 made of indium tin oxide material, thereby effectively reducing the voltage drop of the second electrode layer.
  • the first source-drain metal layer and the second source-drain metal layer are far apart, which can effectively reduce the parasitic capacitance between the first source-drain metal layer and the second source-drain metal layer, thereby meeting the load requirements of medium and large-sized display products and providing support for high refresh rates.
  • the sub-pixel driving circuit includes: a data writing transistor T1 , a writing control transistor T_com, a driving transistor DRT, a compensation transistor T2 , a reset transistor T3 , a light emitting control transistor T_em, a storage capacitor Cst and an intrinsic capacitor C1 of the light emitting element EL.
  • a via hole formed on the interlayer insulating layer is illustrated.
  • the gate of the compensation transistor T2 is coupled to the corresponding second scanning line G2 through the second via hole Via2, and the first electrode of the compensation transistor T2 is coupled to the reference signal line Vref through the first via hole Via1.
  • the gate of the data writing transistor T1 is coupled to the corresponding first scanning line G1 through the third via hole Via3.
  • the first electrode of the data writing transistor T1 is coupled to the fourth conductive connection portion 54 through the ninth via hole Via9.
  • the gate of the write control transistor T_com is coupled to the partition control line G_com through the fourth via Via4, the second electrode of the write control transistor T_com is coupled to the first conductive connection part 51 through the fifth via Via5, the first conductive connection part 51 is coupled to the gate of the driving transistor DRT through the sixth via Via6, and the gate of the driving transistor DRT is reused as the first electrode plate Cst1 of the storage capacitor Cst.
  • the second electrode of the driving transistor DRT is coupled to the second conductive connection portion 52 through the seventh via Via7.
  • the second conductive connection portion 52 is coupled to the second plate Cst2 of the storage capacitor Cst through the eighth via Via8.
  • the second plate Cst2 of the storage capacitor Cst is coupled to the third conductive connection portion 53 through the tenth via Via10, and the third conductive connection portion 53 is coupled to the second electrode of the reset transistor T3 through the fifteenth via Via15.
  • the gate of the light emitting control transistor T_em is coupled to the corresponding light emitting control line EM through an eleventh via hole Via11, and the first electrode of the light emitting control transistor T_em is coupled to the power line VDD through a twelfth via hole Via12.
  • the gate of the reset transistor T3 is coupled to the third scan line G3 through the fourteenth via hole Via14 , and the first electrode of the reset transistor T3 is coupled to the first initial portion 21 through the thirteenth via hole Via13 .
  • the first branch line 111 is coupled to the second branch line 112 through the twenty-second via hole Via22.
  • the first initial portion 21 is coupled to the second initial portion 22 through the twenty-third via hole Via23.
  • a via hole formed on the first organic layer is shown.
  • a via hole formed on the first passivation layer is shown.
  • the second conductive connection portion 52 is coupled to the fifth conductive connection portion 55 through the seventeenth via hole Via17 and the twentieth via hole Via20 in sequence.
  • the fourth conductive connection portion 54 is coupled to the data line DA through the sixteenth via hole Via16 and the nineteenth via hole Via19 in sequence.
  • the power compensation line 30 is coupled to the power line VDD once through the eighteenth via hole Via18 and the twenty-first via hole Via21.
  • a via hole formed on the second passivation layer is shown.
  • a via hole formed on the second organic layer is shown.
  • the fifth conductive connection portion 55 is sequentially coupled to the corresponding first electrode in the first electrode layer 42 through the twenty-fourth via hole Via24 and the twenty-sixth via hole Via26.
  • the auxiliary electrode 40 is sequentially coupled to the connection pattern 41 through the twenty-fifth via hole Via25 and the twenty-seventh via hole Via27.
  • the connection pattern 41 is sequentially coupled to the second electrode layer through the twenty-eighth via hole Via28 and the twenty-ninth via hole Via29.
  • an opening region 60 of a sub-pixel and a non-opening region 61 located near the opening region 60 are schematically illustrated.
  • the data writing transistor T1 , the compensation transistor T2 , and the reset transistor T3 all include a dual-gate structure, which can effectively reduce leakage current.
  • the write control transistor T_com includes a single gate structure.
  • the writing control transistor T_com adopts a single-gate structure design, which is conducive to saving layout area.
  • the embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.
  • the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane, etc.
  • the display device includes an organic light emitting diode display device, but is not limited thereto.
  • the first connection structure and the second connection structure are avoided from occupying the space of the opening area, the aperture ratio of the display substrate is ensured, and the first connection structure and the second connection structure are avoided from affecting the flatness of the light-emitting element.
  • the orthographic projection of the first connection structure on the base substrate is arranged along the first direction with the orthographic projection of the second connection structure on the base substrate;
  • the orthographic projection of the second connection structure on the base substrate is arranged along the second direction with the opening area of the sub-pixel;
  • the first connection structure and the second connection structure are both located on the same side of the opening area along the second direction, and the first connection structure and the second connection structure occupy a smaller space in the second direction, so that the size of the opening area in the second direction can be optimized, thereby effectively improving the aperture ratio of the display substrate and improving the service life of the display substrate.
  • the display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when including the above-mentioned display substrate, which will not be described in detail here.
  • an embodiment of the present disclosure provides a display substrate, comprising: a base substrate, and a plurality of repeating units and a plurality of data lines DA disposed on the base substrate, wherein the plurality of repeating units are divided into a plurality of repeating unit columns;
  • Each repeating unit includes a plurality of sub-pixels, each of which includes a sub-pixel driving circuit, wherein the sub-pixel driving circuit includes a data writing transistor T1, a writing control transistor T_com and a driving transistor DRT; a first electrode of the data writing transistor T1 is coupled to the corresponding data line DA, a second electrode of the data writing transistor T1 is coupled to a first electrode of the writing control transistor T_com, and a second electrode of the writing control transistor T_com is coupled to a gate of the driving transistor DRT;
  • the display substrate also includes: multiple control areas (such as control area 1 to control area X) and multiple partition control lines G_com; the control area includes at least one column of repeating units; the partition control line G_com is respectively coupled to the gate of the write control transistor T_com included in each repeating unit column in the corresponding control area.
  • the display substrate includes a plurality of repeating units, and the plurality of repeating units are distributed in an array.
  • the repeating unit includes a plurality of sub-pixels arranged along a first direction, for example, the repeating unit includes six sub-pixels arranged along the first direction, and the six sub-pixels include BRGBRG arranged along the first direction, where B represents a blue sub-pixel, R represents a red sub-pixel, and G represents a green sub-pixel.
  • the multiple sub-pixels included in the multiple repeating units are distributed in an array, and the multiple sub-pixels can be divided into multiple columns of sub-pixels, and the multiple columns of sub-pixels correspond one-to-one to the multiple data lines DA included in the display substrate.
  • the sub-pixel includes a sub-pixel driving circuit and a light-emitting element EL, wherein the sub-pixel driving circuit is coupled to the light-emitting element EL and is configured to provide a driving signal to the light-emitting element EL to drive the light-emitting element EL to emit light.
  • the sub-pixel driving circuit is coupled to the light-emitting element EL and is configured to provide a driving signal to the light-emitting element EL to drive the light-emitting element EL to emit light.
  • the sub-pixel driving circuit includes a data writing transistor T1, a writing control transistor T_com and a driving transistor DRT; the first electrode of the data writing transistor T1 is coupled to the corresponding data line DA, the second electrode of the data writing transistor T1 is coupled to the first electrode of the writing control transistor T_com, and the second electrode of the writing control transistor T_com is coupled to the gate of the driving transistor DRT; when the data writing transistor T1 and the writing control transistor T_com are both turned on, the data signal transmitted by the data line DA can be written into the gate of the driving transistor DRT; when one of the data writing transistor T1 and the writing control transistor T_com is turned off, the data signal cannot be transmitted to the gate of the driving transistor DRT.
  • the display substrate further includes a plurality of control areas and a plurality of partition control lines G_com, wherein the plurality of control areas correspond to the plurality of partition control lines G_com one by one.
  • the partition control lines G_com are respectively coupled to the gates of the write control transistors T_com included in each repeating unit column in the corresponding control area, and are used to control the conduction or cutoff of the write control transistors T_com included in each repeating unit column in the corresponding control area.
  • the display substrate provided in the embodiment of the present disclosure includes a plurality of control areas, each of which includes at least one column of repeating units, and the partition control line G_com is respectively coupled to the gate of the write control transistor T_com included in each repeating unit column in the corresponding control area.
  • Each partition control line G_com can control whether all the write control transistors T_com in the corresponding control area are turned on, so as to achieve the effect of controlling whether the area achieves a high refresh rate.
  • the display substrate includes X control areas.
  • the control signals transmitted by the first partition control line G_com ⁇ 1> and the Mth partition control line G_com ⁇ M> are both at the effective level VGH, and all the write control transistors T_com included in the first control area corresponding to the first partition control line G_com ⁇ 1> are turned on, and all the write control transistors T_com included in the Mth control area corresponding to the Mth partition control line G_com ⁇ M> are turned on, so that the first control area and the Mth control area can be areas that can achieve normal refresh, and when the display substrate is scanned line by line, the high refresh operation of the first control area and the Mth control area can be achieved.
  • the control signal transmitted by the Hth partition control line G_com ⁇ H> is at the non-effective level VGL, and all the write control transistors T_com included in the Hth control area corresponding to the Hth partition control line G_com ⁇ H> are turned off, and when the display substrate is scanned line by line, the Hth control area cannot achieve the high refresh operation, so that the Hth control area is not refreshed in the Nth frame, and its display screen is not updated in the Nth frame, and the saved data is provided to the high refresh area, so as to achieve the effect of partition high refresh.
  • M and H are both positive integers greater than 1 and less than X.
  • the partition selection is performed for the N+1 frame by controlling the level of the control signal transmitted by the partition control line G_com. It is worth noting that the blanking period is located at the beginning or end of each frame display period.
  • the control signals transmitted by the first partition control line G_com ⁇ 1> and the Hth partition control line G_com ⁇ H> are both at the effective level VGH, and all the write control transistors T_com included in the first control area corresponding to the first partition control line G_com ⁇ 1> are turned on, and all the write control transistors T_com included in the Hth control area corresponding to the Hth partition control line G_com ⁇ H> are turned on.
  • the control signal transmitted by the Mth partition control line G_com ⁇ M> is a non-valid level VGL, and all the write control transistors T_com included in the Mth control area corresponding to the corresponding Mth partition control line G_com ⁇ M> are cut off.
  • the Mth control area cannot implement high refresh operation, so that the Mth control area is not refreshed in the Mth frame, and its display screen is not updated in the Mth frame, and the saved data is provided to the high refresh area, thereby achieving the effect of partitioned high refresh.
  • the control signal transmitted by the partition control line G_com can be adjusted immediately when the Nth frame ends and the blanking period begins.
  • a large-size display substrate can also well realize the high refresh rate function of the display substrate.
  • brackets in FIG. 4 represent row numbers, such as: G1 ⁇ 1> represents the first scan line in the first row, G2 ⁇ 1> represents the second scan line in the first row, G3 ⁇ 1> represents the third scan line in the first row, and EM ⁇ 1> represents the light emitting control line in the first row.
  • the partition control line G_com includes: a control bus 10 and at least one control branch line 11 ;
  • the control branch line 11 is respectively coupled to the gates of the write control transistors T_com included in a corresponding column of repeating units in the corresponding control area; the control bus 10 is coupled to the at least one control branch line 11 .
  • control branch line 11 included in the partition control line G_com corresponds to the repetitive unit column included in the corresponding control area.
  • the control branch line 11 is respectively coupled to the gate of each write control transistor T_com included in a corresponding column of repetitive unit columns in the corresponding control area to control each write control transistor T_com included in the corresponding column of repetitive unit columns to be turned on or off.
  • control bus 10 and each control branch line 11 are coupled respectively.
  • control bus 10 and each control branch line 11 form an integrated structure.
  • the display substrate also includes a driving chip, and the control bus 10 and the driving chip are located on the same side of the display substrate.
  • the control bus 10 is coupled to the driving chip, receives the control signal provided by the driving chip, and transmits the received control signal to each control branch 11 coupled thereto, thereby controlling whether the write control transistor T_com in the corresponding control area is turned on.
  • the partition control line G_com by setting the partition control line G_com to include the control bus 10 and the control branch line 11, not only can the transmission of the control signal be better realized, but also the layout difficulty of the partition control line G_com can be reduced, thereby ensuring the reliability of the coupling between the partition control line G_com and the gate of the write control transistor T_com.
  • the control branch 11 includes: a first branch 111 and multiple second branches 112; the second branch 112 includes at least a portion extending along the first direction, and the multiple second branches 112 are arranged along the second direction; the first branch 111 includes at least a portion extending along the second direction, the first branch 111 is respectively coupled to the multiple second branches 112, and the first branch 111 is coupled to the control bus 10; the first direction intersects with the second direction; the second branch 112 is respectively coupled to the gates of each write control transistor T_com included in the corresponding repetitive unit.
  • the first direction includes a horizontal direction
  • the second direction includes a vertical direction
  • the control branch line 11 corresponds to the repetitive unit column one by one, and the control branch line 11 includes a plurality of second branches 112, which correspond to a plurality of repetitive units included in the corresponding repetitive unit column one by one.
  • the repetitive unit includes a plurality of sub-pixels arranged along the first direction, and the sub-pixels include a sub-pixel driving circuit, and the sub-pixel driving circuit includes a write control transistor T_com.
  • the second branch line 112 is respectively coupled to the gate of each write control transistor T_com included in the corresponding repetitive unit.
  • the second branch line 112 is respectively coupled to the gates of the six write control transistors T_com included in the corresponding repetitive unit to control the conduction and cutoff of the six write control transistors T_com.
  • the first branch line 111 included in the control branch line 11 is located in the middle area of the corresponding repeating unit column, that is, in the repeating unit column corresponding to the first branch line 111, the number of sub-pixels located on both sides of the first branch line 111 along the first direction is the same.
  • the number of sub-pixels located on the left and right sides of the corresponding first branch line 111 in the repeating unit is three.
  • the orthographic projection of the first branch line 111 on the substrate substrate and the orthographic projection of each second branch line 112 on the substrate substrate respectively form an overlapping area, and the first branch line 111 is coupled to the corresponding second branch line 112 through a via in the corresponding overlapping area.
  • control branch line 11 is arranged to include: a first branch line 111 and multiple second branches 112; not only can the transmission of the control signal be better realized, but also the layout difficulty of the control branch line 11 can be reduced, thereby ensuring the reliability of the coupling between the control branch line 11 and the gate of the write control transistor T_com.
  • the second branches 112 adjacent to each other along the first direction are coupled.
  • the second branches 112 located in the same row along the first direction are sequentially connected.
  • the second branches 112 located in the same row along the first direction form an integrated structure.
  • the second branches 112 adjacent to each other along the first direction are disconnected.
  • the second branches 112 adjacent to each other along the first direction are coupled in the same control area, so that in the same control area, the control branches 11 can form a grid structure, which is beneficial to reducing the overall load of the partition control line G_com and reducing the voltage drop of the partition control line G_com.
  • the second branches 112 adjacent to each other along the first direction are independent of each other.
  • the display substrate further includes a plurality of power lines VDD, and the orthographic projection of the second branch line 112 on the base substrate does not overlap with the orthographic projection of the power line VDD on the base substrate.
  • the plurality of power lines VDD are arranged along the first direction, and the power line VDD includes at least a portion extending along the second direction.
  • the power lines VDD and the repeating unit columns are alternately arranged.
  • the display substrate further includes a plurality of power compensation lines 30, the plurality of power compensation lines 30 are arranged along the second direction, and the power compensation lines 30 include at least a portion extending along the first direction.
  • the power compensation lines 30 are respectively coupled to the plurality of power lines VDD, and the power compensation lines 30 and the power lines VDD together form a grid structure to reduce the voltage drop of the power line VDD.
  • the orthographic projection of the power compensation line 30 on the substrate has an overlapping area with the orthographic projection of the power line VDD on the substrate, and the power compensation line 30 and the power line VDD are coupled through a via in the overlapping area.
  • the second branches 112 adjacent to each other along the first direction are arranged to be independent of each other, and the orthographic projection of the second branch line 112 on the base substrate does not overlap with the orthographic projection of the power line VDD on the base substrate, so that the control branch line 11 is formed into a non-grid structure and can avoid the power line VDD.
  • This not only reduces the risk of short circuit between the control branch line 11 and the power line VDD, but also reduces the parasitic capacitance formed between the control branch line 11 and the power line VDD.
  • the orthographic projection of the data line DA on the base substrate and the orthographic projection of the second branch line 112 on the base substrate have a first overlapping region, and the areas of the first overlapping regions formed by the data lines DA are the same.
  • the data lines DA and sub-pixel columns in the display substrate are alternately arranged along the first direction.
  • the data lines DA include at least a portion extending along the second direction.
  • the data line DA and the second branch line 112 are disposed in different layers.
  • the total area of the first overlapping regions formed between each data line DA and a plurality of second branch lines 112 is the same.
  • the loads of the data lines DA connected to the sub-pixels of various colors in the display substrate are made the same, thereby better ensuring the uniformity of the display image of the display substrate.
  • the first branch line 111 is made of a first gate metal layer in a display substrate
  • the second branch line 112 is made of a first source/drain metal layer in a display substrate.
  • the display substrate includes the following layers stacked on the base substrate 70 in sequence in a direction away from the base substrate 70: a buffer layer 71, an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, an interlayer insulating layer ILD, a first source-drain metal layer, a first organic layer Resin1, a first passivation layer PVX1, a second source-drain metal layer, a second passivation layer PVX2, a second organic layer Resin2, a first electrode layer 42, a first pixel defining layer PDL1, a second pixel defining layer PDL2, a light-emitting functional layer, a second electrode layer 43, and an encapsulation layer.
  • FIG. 24 also illustrates a first connection structure 81, a second connection structure 82, and a third connection structure 83.
  • the second electrode layer 43 receives a negative power supply signal VSS.
  • the first branch line 111 can be formed in the same patterning process as other structures in the display substrate made of the first gate metal layer, thereby effectively simplifying the manufacturing process of the display substrate.
  • the second branch line 112 can be formed in the same patterning process as other structures in the display substrate made of the first source-drain metal layer, thereby effectively simplifying the manufacturing process of the display substrate.
  • the partition control line G_com is designed in parallel inside the control area, and its equivalent resistance is small, and the first branch line 111 is made of the first gate metal layer in the display substrate, and the square resistance of the first gate metal layer is large, and the influence on the parasitic resistance is small.
  • first branch line 111 is made of the first gate metal layer in the display substrate
  • second branch line 112 is made of the first source and drain metal layer in the display substrate, which effectively reduces the parasitic capacitance formed between the partition control line G_com and the structure made of the second source and drain metal layer, thereby optimizing the load of the partition control line G_com and achieving the effect of partition control optimization.
  • the display substrate further includes: a plurality of first scan lines G1 , a plurality of second scan lines G2 , a plurality of third scan lines G3 , a plurality of light emitting control lines EM , a power line VDD , a reference signal line Vref and an initialization signal line Vini ;
  • the sub-pixel driving circuit further includes: a compensation transistor T2, a reset transistor T3, a light emitting control transistor T_em and a storage capacitor Cst;
  • the gate of the data writing transistor T1 is coupled to the corresponding first scanning line G1;
  • the gate of the compensation transistor T2 is coupled to the corresponding second scan line G2, the first electrode of the compensation transistor T2 is coupled to the reference signal line Vref, and the second electrode of the compensation transistor T2 is coupled to the first electrode of the write control transistor T_com;
  • the gate of the reset transistor T3 is coupled to the corresponding third scan line G3, the first electrode of the reset transistor T3 is coupled to the initialization signal line Vini, and the second electrode of the reset transistor T3 is coupled to the second electrode of the drive transistor DRT;
  • the gate of the light emitting control transistor T_em is coupled to the corresponding light emitting control line EM, the first electrode of the light emitting control transistor T_em is coupled to the power line VDD, and the second electrode of the light emitting control transistor T_em is coupled to the first electrode of the driving transistor DRT;
  • the first plate Cst1 of the storage capacitor Cst is coupled to the gate of the driving transistor DRT, and the second plate Cst2 of the storage capacitor Cst is coupled to the second electrode of the driving transistor DRT.
  • the initialization signal line Vini includes a plurality of first initial portions 21 and a plurality of second initial portions 22, the plurality of first initial portions 21 are arranged along the second direction, the plurality of second initial portions 22 are arranged along the first direction, the first initial portion 21 includes at least a portion extending along the first direction, the second initial portion 22 includes at least a portion extending along the second direction, the first initial portion 21 is coupled to each of the second initial portions 22, respectively, so that the initialization signal line Vini forms a grid structure, thereby effectively reducing the voltage drop of the initialization signal line Vini.
  • the active layer is used to form a channel portion, a first electrode and a second electrode included in each of the transistors.
  • the first gate metal layer is used to form the gate of each of the transistors, the first branch line 111 and the second initial portion 22 .
  • the second gate metal layer is used for the second substrate of the storage capacitor Cst.
  • the first source-drain metal layer is used to form some conductive connection parts, the reference signal line Vref, the first scan line G1, the second scan line G2, the third scan line G3, the light emitting control line EM and the first initial part 21.
  • the reference signal line Vref, the second scan line G2, the first scan line G1, the second branch line 112, the light emitting control line EM, the power supply compensation line 30, the third scan line G3 and the first initial part 21 coupled to the same repeating unit are arranged in sequence along the second direction.
  • the reference signal line Vref, the first scan line G1, the second scan line G2, the third scan line G3 and the light emitting control line EM all include at least a portion extending along the first direction.
  • the second source-drain metal layer is used to form the power line VDD, the data line DA, some conductive connection parts and the auxiliary electrode 40.
  • the auxiliary electrode 40 includes at least a portion extending along the second direction, and the auxiliary electrode 40 is coupled to the second electrode layer through a connection pattern 41 made of indium tin oxide material, thereby effectively reducing the voltage drop of the second electrode layer.
  • the sub-pixel driving circuit includes: a data writing transistor T1 , a writing control transistor T_com, a driving transistor DRT, a compensation transistor T2 , a reset transistor T3 , a light emitting control transistor T_em, a storage capacitor Cst and an intrinsic capacitor C1 of the light emitting element EL.
  • a via hole formed on the interlayer insulating layer is illustrated.
  • the gate of the compensation transistor T2 is coupled to the corresponding second scanning line G2 through the second via hole Via2, and the first electrode of the compensation transistor T2 is coupled to the reference signal line Vref through the first via hole Via1.
  • the gate of the data writing transistor T1 is coupled to the corresponding first scanning line G1 through the third via hole Via3.
  • the first electrode of the data writing transistor T1 is coupled to the fourth conductive connection portion 54 through the ninth via hole Via9.
  • the gate of the write control transistor T_com is coupled to the partition control line G_com through the fourth via Via4, the second electrode of the write control transistor T_com is coupled to the first conductive connection part 51 through the fifth via Via5, the first conductive connection part 51 is coupled to the gate of the driving transistor DRT through the sixth via Via6, and the gate of the driving transistor DRT is reused as the first electrode plate Cst1 of the storage capacitor Cst.
  • the second electrode of the driving transistor DRT is coupled to the second conductive connection portion 52 through the seventh via Via7.
  • the second conductive connection portion 52 is coupled to the second plate Cst2 of the storage capacitor Cst through the eighth via Via8.
  • the second plate Cst2 of the storage capacitor Cst is coupled to the third conductive connection portion 53 through the tenth via Via10, and the third conductive connection portion 53 is coupled to the second electrode of the reset transistor T3 through the fifteenth via Via15.
  • the gate of the light emitting control transistor T_em is coupled to the corresponding light emitting control line EM through an eleventh via hole Via11, and the first electrode of the light emitting control transistor T_em is coupled to the power line VDD through a twelfth via hole Via12.
  • the gate of the reset transistor T3 is coupled to the third scan line G3 through the fourteenth via hole Via14 , and the first electrode of the reset transistor T3 is coupled to the first initial portion 21 through the thirteenth via hole Via13 .
  • the first branch line 111 is coupled to the second branch line 112 through the twenty-second via hole Via22.
  • the first initial portion 21 is coupled to the second initial portion 22 through the twenty-third via hole Via23.
  • a via hole formed on the first organic layer is shown.
  • a via hole formed on the first passivation layer is shown.
  • the second conductive connection portion 52 is coupled to the fifth conductive connection portion 55 through the seventeenth via hole Via17 and the twentieth via hole Via20 in sequence.
  • the fourth conductive connection portion 54 is coupled to the data line DA through the sixteenth via hole Via16 and the nineteenth via hole Via19 in sequence.
  • the power compensation line 30 is coupled to the power line VDD once through the eighteenth via hole Via18 and the twenty-first via hole Via21.
  • a via hole formed on the second passivation layer is schematically shown.
  • a via hole formed on the second organic layer is schematically shown.
  • the fifth conductive connection portion 55 is sequentially coupled to the corresponding first electrode in the first electrode layer 42 through the twenty-fourth via hole Via24 and the twenty-sixth via hole Via26.
  • the auxiliary electrode 40 is sequentially coupled to the connection pattern 41 through the twenty-fifth via hole Via25 and the twenty-seventh via hole Via27.
  • the connection pattern 41 is sequentially coupled to the second electrode layer through the twenty-eighth via hole Via28 and the twenty-ninth via hole Via29.
  • an opening region 60 of a pixel and a non-opening region 61 located near the opening region 60 are schematically illustrated.
  • the data writing transistor T1 , the compensation transistor T2 , and the reset transistor T3 all include a dual-gate structure, which can effectively reduce leakage current.
  • the write control transistor T_com includes a single gate structure.
  • the writing control transistor T_com adopts a single-gate structure design, which is conducive to saving layout area.
  • the embodiment of the present disclosure further provides a method for driving a display substrate, which is used to drive the display substrate provided by the above embodiment.
  • the driving method includes:
  • the partition control signals transmitted by at least some of the partition control lines G_com in the display substrate are at an effective level
  • the write control transistors T_com coupled to the at least some of the partition control lines G_com are turned on, and the plurality of sub-pixels are scanned row by row to achieve row-by-row writing of data signals;
  • the levels of the partition control signals transmitted by the multiple partition control lines G_com change, so that the write control transistor T_com coupled to the partition control line G_com that transmits the partition control signal of the effective level is turned on, and the multiple sub-pixels are scanned row by row to realize the writing of data signals row by row.
  • the control signals transmitted by the first partition control line G_com ⁇ 1> and the Mth partition control line G_com ⁇ M> in the display substrate are both at the effective level VGH, and correspondingly all the write control transistors T_com included in the first control area corresponding to the first partition control line G_com ⁇ 1> are turned on, and all the write control transistors T_com included in the Mth control area corresponding to the Mth partition control line G_com ⁇ M> are turned on.
  • the first control area and the Mth control area are areas where normal refresh can be achieved, and when the display substrate is scanned line by line, high refresh operation of the first control area and the Mth control area can be achieved.
  • the levels of partition control signals transmitted by the multiple partition control lines G_com change, so that the control signals transmitted by the first partition control line G_com ⁇ 1> and the Hth partition control line G_com ⁇ H> are both at the effective level VGH, and correspondingly all the write control transistors T_com included in the first control area corresponding to the first partition control line G_com ⁇ 1> are turned on, and all the write control transistors T_com included in the Hth control area corresponding to the Hth partition control line G_com ⁇ H> are turned on, so that the first control area and the Hth control area can be ensured to be areas where normal refresh can be achieved, and when the display substrate is scanned line by line, high refresh operation of the first control area and the Hth control area can be achieved.
  • every two rows of sub-pixel driving circuits or every four rows of sub-pixel driving circuits can be controlled to simultaneously achieve reset and compensation according to actual needs.
  • each partition control line G_com can be used to control whether all the write control transistors T_com in the corresponding control area are turned on, so as to achieve the effect of controlling whether the area achieves a high refresh frequency, so that a large-size display substrate can also well realize the high refresh rate function of the display substrate.
  • the driving method further includes:
  • a blanking period the blanking period is located at the beginning or end of each frame display period; during the blanking period, the levels of the partition control signals transmitted by the plurality of partition control lines are adjusted.
  • the control signal transmitted by the partition control line G_com is immediately adjusted.
  • the embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.
  • the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane, etc.
  • the display device includes an organic light emitting diode display device, but is not limited thereto.
  • the display substrate provided in the above embodiment includes a plurality of control areas, each control area includes at least one column of repeating units, and the partition control lines are respectively coupled to the gates of the write control transistors included in each column of repeating units in the corresponding control area.
  • Each partition control line can control whether all the write control transistors in the corresponding control area are turned on, so as to achieve the effect of controlling whether the area achieves a high refresh rate.
  • a large-size display substrate can also well achieve the high refresh rate function of the display substrate.
  • the display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when including the above-mentioned display substrate, which will not be described in detail here.
  • the signal line extends along a certain direction means that: the signal line includes a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along a certain direction, and the length of the main part extending along the certain direction is greater than the length of the secondary part extending along other directions.
  • the "same layer" in the embodiment of the present disclosure may refer to a film layer on the same structural layer.
  • a film layer on the same layer may be a film layer for forming a specific pattern formed by the same film forming process, and then the film layer is patterned by the same mask through a single composition process to form a layer structure.
  • a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.
  • each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments.
  • the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiment.

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Abstract

本公开提供一种显示基板和显示装置。所述显示基板，包括：衬底基板，以及设置于衬底基板上的多条数据线和多个子像素；子像素包括子像素驱动电路和发光元件；子像素驱动电路包括驱动晶体管和数据写入晶体管，发光元件包括第一电极；驱动晶体管的第二极通过第一连接结构与对应的第一电极耦接；数据写入晶体管的第一极通过第二连接结构与对应的数据线耦接；第一连接结构和第二连接结构均位于子像素的非开口区，第一连接结构在衬底基板上的正投影，与第二连接结构在衬底基板上的正投影沿第一方向排列；第二连接结构在衬底基板上的正投影与子像素的开口区沿第二方向排列，第二方向与第一方向相交。

Description

显示基板和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板和显示装置。
背景技术
随着显示技术的不断发展，显示产品的应用范围越来越广泛，高分辨率高刷新频率的显示产品越来越受到人们青睐。而中大尺寸的显示产品由于受到负载大的限制，无法很好的实现高刷新频率的产品功能。
发明内容
本公开的目的在于提供一种显示基板和显示装置。
为了实现上述目的，本公开提供如下技术方案：
本公开的第一方面提供一种显示基板，包括：衬底基板，以及设置于所述衬底基板上的多条数据线和多个子像素；所述子像素包括子像素驱动电路和发光元件；所述子像素驱动电路包括驱动晶体管和数据写入晶体管，所述发光元件包括第一电极；
所述驱动晶体管的第二极通过第一连接结构与对应的所述第一电极耦接；所述数据写入晶体管的第一极通过第二连接结构与对应的所述数据线耦接；
所述第一连接结构和所述第二连接结构均位于所述子像素的非开口区，所述第一连接结构在所述衬底基板上的正投影，与所述第二连接结构在所述衬底基板上的正投影沿第一方向排列；
所述第二连接结构在所述衬底基板上的正投影与所述子像素的开口区沿第二方向排列，所述第二方向与所述第一方向相交。
可选的，所述第一连接结构包括：第二导电连接部，第一过孔结构，第五导电连接部和第二过孔结构；
所述第二导电连接部与所述驱动晶体管的第二极耦接，所述第二导电连接部通过所述第一过孔结构与所述第五导电连接部耦接，所述第五导电连接 部通过所述第二过孔结构与对应的所述第一电极耦接。
可选的，所述第二连接结构包括：第四导电连接部和第三过孔结构；所述第四导电连接部与所述数据写入晶体管的第一极耦接，所述第四导电连接部通过所述第三过孔结构与对应的所述数据线耦接。
可选的，所述显示基板还包括沿远离所述衬底基板的方向依次层叠设置的第一有机层和第二有机层，所述第一过孔结构贯穿所述第一有机层，所述第二过孔结构贯穿所述第二有机层；
所述第二导电连接部位于所述第一有机层与所述衬底基板之间，所述第五导电连接部位于第一有机层和所述第二有机层之间。
可选的，所述第三过孔结构贯穿所述第一有机层，所述第四导电连接部位于所述第一有机层与所述衬底基板之间。
可选的，所述显示基板还包括：第一钝化层和第二钝化层；所述第一钝化层位于所述第一有机层和所述第二钝化层之间，所述第二钝化层位于所述第一钝化层和所述第二有机层之间；
所述第一过孔结构和所述第三过孔结构均贯穿所述第一钝化层，所述第二过孔结构贯穿所述第二钝化层；所述第五导电连接部位于所述第一钝化层和所述第二钝化层之间。
可选的，所述显示基板还包括：辅助电极，第三连接结构和第二电极层；所述辅助电极通过所述第三连接结构与所述第二电极层耦接；
所述第三连接结构位于所述子像素的非开口区，所述第三连接结构在所述衬底基板上的正投影，与所述第一连接结构在所述衬底基板上的正投影沿第一方向排列。
可选的，所述显示基板还包括：辅助电极，第三连接结构和第二电极层；所述辅助电极通过所述第三连接结构与所述第二电极层耦接；
所述第三连接结构位于所述子像素的非开口区，所述第三连接结构在所述衬底基板上的正投影，与所述第一连接结构在所述衬底基板上的正投影至少部分错开。
可选的，所述显示基板还包括沿远离所述衬底基板的方向依次层叠设置的第二有机层和像素界定层；
所述第三连接结构包括：第四过孔结构，连接图形和第五过孔结构；所述辅助电极位于所述第二有机层与所述衬底基板之间，所述第二电极层的至少部分位于所述像素界定层背向所述衬底基板的一侧，所述连接图形的至少部分位于所述第二有机层与所述像素界定层之间，所述第四过孔结构贯穿所述第二有机层，所述第五过孔结构贯穿所述像素界定层；
所述连接图形通过所述第四过孔结构与所述辅助电极耦接，所述连接图形通过所述第五过孔结构与所述第二电极层耦接。
可选的，所述多个子像素划分为呈阵列分布的多个重复单元，每个重复单元包括沿第一方向排列的两个子单元，每个子单元包括沿所述第一方向排列的多个所述子像素；
所述辅助电极在所述衬底基板上的正投影，位于所述两个子单元在所述衬底基板上的正投影之间。
可选的，所述显示基板还包括电源线和电源补偿线；
所述子像素驱动电路还包括发光控制晶体管；所述发光控制晶体管的第一极与所述电源补偿线耦接，所述发光控制晶体管的第二极与所述驱动晶体管的第一极耦接；
所述电源补偿线通过第六过孔结构与所述电源线耦接，所述第六过孔结构位于所述子像素的非开口区。
可选的，所述显示基板还包括第一有机层，所述电源补偿线位于所述第一有机层和所述衬底基板之间，所述电源线位于所述第一有机层背向所述衬底基板的一侧，所述第六过孔结构贯穿所述第一有机层。
可选的，所述电源线在所述衬底基板上的正投影，与所述重复单元在所述衬底基板上的正投影沿所述第一方向交替设置。
可选的，所述显示基板还包括：多条发光控制线，电源线，初始化信号线，基准信号线，多条第一扫描线，多条第二扫描线，多条第三扫描线和多条分区控制线；
所述子像素驱动电路还包括：补偿晶体管，复位晶体管，发光控制晶体管，写入控制晶体管和存储电容；
所述数据写入晶体管的栅极与对应的所述第一扫描线耦接，所述数据写 入晶体管的第二极与所述写入控制晶体管的第一极耦接；
所述写入控制晶体管的第二极与所述驱动晶体管的栅极耦接，所述写入控制晶体管的栅极与对应的所述分区控制线耦接；
所述补偿晶体管的栅极与对应的所述第二扫描线耦接，所述补偿晶体管的第一极与所述基准信号线耦接，所述补偿晶体管的第二极与所述写入控制晶体管的第一极耦接；
所述复位晶体管的栅极与对应的所述第三扫描线耦接，所述复位晶体管的第一极与所述初始化信号线耦接，所述复位晶体管的第二极与所述驱动晶体管的第二极耦接；
所述发光控制晶体管的栅极与对应的所述发光控制线耦接，所述发光控制晶体管的第一极与所述电源线耦接，所述发光控制晶体管的第二极与所述驱动晶体管的第一极耦接；
所述存储电容的第一极板与所述驱动晶体管的栅极耦接，所述存储电容的第二极板与所述驱动晶体管的第二极耦接。
基于上述显示基板的技术方案，本公开的第二方面提供一种显示装置，包括上述显示基板。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为本公开实施例提供的子像素驱动电路的电路图；
图2为本公开实施例提供的重复单元的电路结构示意图；
图3为本公开实施例提供的分区控制线的阻容等效示意图；
图4为本公开实施例提供的驱动时序图；
图5为本公开实施例提供的重复单元的有源层和第一栅金属层的布局示意图；
图6为在图5的基础上增加第二栅金属层的布局示意图；
图7为图6中第二栅金属层的布局示意图；
图8为在图6的基础上增加第一源漏金属层的布局示意图；
图9为图8中层间绝缘层上形成的过孔的布局示意图；
图10为图8中第一源漏金属层的布局示意图；
图11为在图8的基础上增加第二源漏金属层的布局示意图；
图12为图11中第一有机层上形成的过孔的布局示意图；
图13为图11中第一钝化层上形成的过孔的布局示意图；
图14为图11中第二源漏金属层的布局示意图；
图15为在图11的基础上增加第一电极层的布局示意图；
图16为图15中第二钝化层上形成的过孔的布局示意图；
图17为图15中第二有机层上形成的过孔的布局示意图；
图18为图15中第一电极层的布局示意图；
图19为图15中的基础上增加第一像素界定层的布局示意图；
图20为图19中第一像素界定层的布局示意图；
图21为图19的基础上增加第二像素界定层开口的布局示意图；
图22为图21中第二像素界定层开口的布局示意图；
图23为图19的基础上增加第二像素界定层开口的布局示意图；
图24为图23中沿A1A2方向的截面示意图。
具体实施方式
为了进一步说明本公开实施例提供的显示基板和显示装置，下面结合说明书附图进行详细描述。
由于中大尺寸的显示产品受到负载大的限制，无法很好的实现高刷新频率的产品功能，因此，需要添加金属层和较厚的绝缘层进行布线，以降低负载的影响。而增加较厚的绝缘层就需要在该绝缘层上形成较深过孔，该较深的过孔会影响发光功能层的平坦度，进而使得显示产品的开口率降低，影响显示产品寿命。
请参阅图1，图2，图5，图23和图24，本公开实施例提供了一种显示基板，包括：衬底基板，以及设置于所述衬底基板上的多条数据线DA和多个 子像素；所述子像素包括子像素驱动电路和发光元件EL；所述子像素驱动电路包括驱动晶体管DRT和数据写入晶体管T1，所述发光元件EL包括第一电极；
所述驱动晶体管DRT的第二极通过第一连接结构81与对应的所述第一电极耦接；所述数据写入晶体管T1的第一极通过第二连接结构82与对应的所述数据线DA耦接；
所述第一连接结构81和所述第二连接结构82均位于所述子像素的非开口区61，所述第一连接结构81在所述衬底基板上的正投影，与所述第二连接结构82在所述衬底基板上的正投影沿第一方向排列；
所述第二连接结构82在所述衬底基板上的正投影与所述子像素的开口区60沿第二方向排列，所述第二方向与所述第一方向相交。
示例性的，所述多条数据线DA沿所述第一方向排列，所述数据线DA包括沿所述第二方向延伸的至少部分。所述多个子像素呈阵列分布，所述多个子像素划分为多列子像素列，每列子像素列中包括的各子像素与对应的数据线DA分别耦接。
示例性的，所述子像素包括子像素驱动电路和发光元件，所述子像素驱动电路与所述发光元件包括的第一电极耦接，用于向所述发光元件的第一电极提供驱动信号，以驱动发光元件发光。
示例性的，所述数据线DA和所述第一电极均位于所述子像素驱动电路背向所述衬底基板的一侧。所述数据线DA与所述数据写入晶体管T1的第一极之间具有较厚的绝缘层，所述第一电极与所述驱动晶体管DRT的第二极之间同样具有较厚的绝缘层，因此，所述第一连接结构81和所述第二连接结构82均包括较深的过孔结构。
根据上述显示基板的具体结构，本公开实施例提供的显示基板中，通过设置所述第一连接结构81和所述第二连接结构82均位于所述子像素的非开口区，避免了所述第一连接结构81和所述第二连接结构82占用开口区的空间，保证了显示基板的开口率，避免了第一连接结构81和第二连接结构82对发光元件的平坦度产生影响。
而且，本公开实施例提供的显示基板中，通过设置所述第一连接结构81 在所述衬底基板上的正投影，与所述第二连接结构82在所述衬底基板上的正投影沿第一方向排列；所述第二连接结构82在所述衬底基板上的正投影与所述子像素的开口区沿第二方向排列；使得所述第一连接结构81和所述第二连接结构82均位于所述开口区沿所述第二方向的同一侧，且使得所述第一连接结构81和所述第二连接结构82在所述第二方向上占用较小的空间，能够对所述第一连接结构81和所述第二连接结构82集中遮挡，从而使得所述开口区在所述第二方向上的尺寸能够最优化，有效提升了显示基板的开口率，提升了显示基板的使用寿命。
如图8至图18，图23和图24所示，在一些实施例中，所述第一连接结构81包括：第二导电连接部52，第一过孔结构，第五导电连接部55和第二过孔结构；
所述第二导电连接部52与所述驱动晶体管DRT的第二极耦接，所述第二导电连接部52通过所述第一过孔结构与所述第五导电连接部55耦接，所述第五导电连接部55通过所述第二过孔结构与对应的所述第一电极(第一电极层42包括多个第一电极)耦接。
示例性的，所述第一过孔结构包括第十七过孔Via17和第二十过孔Via20。所述第二过孔结构包括第二十四过孔Via24和第二十六过孔Via26。所述第二导电连接部52采用所述显示基板中的第一源漏金属层制作，所述第五导电连接部55采用所述显示基板中的第二源漏金属层制作。
如图8至图18，图23和图24所示，在一些实施例中，所述第二连接结构82包括：第四导电连接部54和第三过孔结构；所述第四导电连接部54与所述数据写入晶体管T1的第一极耦接，所述第四导电连接部54通过所述第三过孔结构与对应的所述数据线DA耦接。
示例性的，所述第三过孔结构包括第十六过孔Via16和第十九过孔Via19。所述第四导电连接部54采用所述显示基板中的第一源漏金属层制作。
如图24所示，在一些实施例中，所述显示基板包括沿远离所述衬底基板70的方向依次层叠设置于所述衬底基板70上的：缓冲层71，有源层，第一栅极绝缘层，第一栅金属层，第二栅极绝缘层，第二栅金属层，层间绝缘层ILD，第一源漏金属层，第一有机层Resin1，第一钝化层PVX1，第二源漏金 属层，第二钝化层PVX2，第二有机层Resin2，第一电极层42，第一像素界定层PDL1，第二像素界定层PDL2，发光功能层，第二电极层43，封装层。所述第二电极层43接收负电源信号VSS。
如图8至图18，图23和图24所示，在一些实施例中，所述显示基板还包括沿远离所述衬底基板的方向依次层叠设置的第一有机层和第二有机层，所述第一过孔结构贯穿所述第一有机层，所述第二过孔结构贯穿所述第二有机层；
所述第二导电连接部52位于所述第一有机层与所述衬底基板之间，所述第五导电连接部55位于第一有机层和所述第二有机层之间。
所述第一有机层和所述第二有机层均为较厚的绝缘层，因此所述第一过孔结构和所述第二过孔结构均为较深的过孔结构。上述设置所述第一连接结构81位于所述子像素的非开口区，使得所述第一过孔结构和所述第二过孔结构均位于所述非开口区，避免了所述第一过孔结构和所述第二过孔结构占用开口区的空间，保证了显示基板的开口率，避免了所述第一过孔结构和所述第二过孔结构对发光元件的平坦度产生影响。
如图8至图18，图23和图24所示，在一些实施例中，所述第三过孔结构贯穿所述第一有机层，所述第四导电连接部54位于所述第一有机层与所述衬底基板之间。
所述第一有机层为较厚的绝缘层，因此所述第三过孔结构为较深的过孔结构。上述设置所述第二连接结构82位于所述子像素的非开口区，使得所述第三过孔结构位于所述非开口区，避免了所述第三过孔结构占用开口区的空间，保证了显示基板的开口率，避免了所述第三过孔结构对发光元件的平坦度产生影响。
上述实施例提供的显示基板中，通过设置所述第一连接结构81在所述衬底基板上的正投影，与所述第二连接结构82在所述衬底基板上的正投影沿第一方向排列，以及所述第二连接结构82在所述衬底基板上的正投影与所述子像素的开口区沿第二方向排列；使得所述第一过孔结构在所述衬底基板上的正投影，所述第二过孔结构在所述衬底基板上的正投影，以及所述第三过孔结构在所述衬底基板上的正投影均位于所述开口区沿所述第二方向的同一 侧，且使得所述第一过孔结构，所述第二过孔结构和所述第三过孔结构在所述第二方向上占用较小的空间，从而使得所述开口区在所述第二方向上的尺寸能够最优化，有效提升了显示基板的开口率，提升了显示基板的使用寿命。
如图8至图18，图23和图24所示，在一些实施例中，所述显示基板还包括：第一钝化层和第二钝化层；所述第一钝化层位于所述第一有机层和所述第二钝化层之间，所述第二钝化层位于所述第一钝化层和所述第二有机层之间；
所述第一过孔结构和所述第三过孔结构均贯穿所述第一钝化层，所述第二过孔结构贯穿所述第二钝化层；所述第五导电连接部55位于所述第一钝化层和所述第二钝化层之间。
上述实施例提供的显示基板中，通过设置所述显示基板还包括第一钝化层和第二钝化层，所述第五导电连接部55位于所述第一钝化层和所述第二钝化层之间，能够更好的保证所述第五导电连接部55的导电性能。
如图8至图18，图23和图24所示，在一些实施例中，所述显示基板还包括：辅助电极40，第三连接结构83和第二电极层43；所述辅助电极40通过所述第三连接结构83与所述第二电极层43耦接；
所述第三连接结构83位于所述子像素的非开口区61，所述第三连接结构83在所述衬底基板上的正投影，与所述第一连接结构81在所述衬底基板上的正投影沿第一方向排列。
示例性的，所述显示基板包括的多条辅助电极40沿所述第一方向排列，所述辅助电极40包括沿所述第二方向延伸的至少部分。
示例性的，所述辅助电极40与所述第二电极层之间具有较厚的绝缘层，所述第三连接结构83包括能够贯穿较厚绝缘层的较深过孔结构。
上述实施例提供的显示基板中，通过设置所述第三连接结构83位于所述子像素的非开口区61，避免了所述第三连接结构83占用开口区60的空间，保证了显示基板的开口率，避免了第三连接结构83对发光元件的平坦度产生影响。
而且，上述实施例提供的显示基板中，通过设置所述第三连接结构83在所述衬底基板上的正投影，与所述第一连接结构81在所述衬底基板上的正投 影沿第一方向排列使得所述第一连接结构81和所述第三连接结构83均位于所述开口区60沿所述第二方向的同一侧，且使得所述第一连接结构81和所述第三连接结构83在所述第二方向上占用较小的空间，从而使得所述开口区60在所述第二方向上的尺寸能够最优化，有效提升了显示基板的开口率，提升了显示基板的使用寿命。
如图8至图18，图23和图24所示，在一些实施例中，所述显示基板还包括：辅助电极40，第三连接结构83和第二电极层；所述辅助电极40通过所述第三连接结构83与所述第二电极层43耦接；
所述第三连接结构83位于所述子像素的非开口区，所述第三连接结构83在所述衬底基板上的正投影，与所述第一连接结构81在所述衬底基板上的正投影至少部分错开。
上述实施例提供的显示基板中，通过设置所述第三连接结构83在所述衬底基板上的正投影，与所述第一连接结构81在所述衬底基板上的正投影至少部分错开，能够更好的利用非开口区的布局空间，降低所述第一连接结构81和所述第三连接结构83的布局难度。
如图8至图18，图23和图24所示，在一些实施例中，所述显示基板还包括沿远离所述衬底基板的方向依次层叠设置的第二有机层和像素界定层；
所述第三连接结构83包括：第四过孔结构，连接图形41和第五过孔结构；所述辅助电极40位于所述第二有机层与所述衬底基板之间，所述第二电极层的至少部分位于所述像素界定层背向所述衬底基板的一侧，所述连接图形41的至少部分位于所述第二有机层与所述像素界定层之间，所述第四过孔结构贯穿所述第二有机层，所述第五过孔结构贯穿所述像素界定层；
所述连接图形41通过所述第四过孔结构与所述辅助电极40耦接，所述连接图形41通过所述第五过孔结构与所述第二电极层耦接。
示例性的，所述像素界定层包括层叠设置的第一像素界定层和第二像素界定层，所述第一像素界定层位于所述衬底基板和所述第二像素界定层之间。所述第二电极层的至少部分位于所述第二像素界定层背向所述衬底基板的一侧，所述连接图形41的至少部分位于所述第二有机层与所述第一像素界定层之间。
示例性的，所述第四过孔结构包括第二十五过孔Via25和第二十七过孔Via27。所述第五过孔结构包括第二十八过孔Via28和第二十九过孔Via29。
示例性的，所述连接图形41与所述第一电极层42同层设置，示例性的，所述连接图形41可以采用和第一电极层相同的材料制作，比如使用氧化铟锡材料制作，也可以采用不同的材料，能满足导电连接的性能即可。
上述实施例提供的显示基板中，通过设置所述第二电极层通过连接图形41与多条辅助电极40耦接，有效降低了所述第二电极层的压降。
如图21所示，在一些实施例中，所述多个子像素划分为呈阵列分布的多个重复单元，每个重复单元包括沿第一方向排列的两个子单元，每个子单元包括沿所述第一方向排列的多个所述子像素；
所述辅助电极40在所述衬底基板上的正投影，位于所述两个子单元在所述衬底基板上的正投影之间。
示例性的，所述显示基板包括多个重复单元，所述多个重复单元呈阵列分布，能够划分为沿所述第一方向依次排列的多列重复单元列，每列重复单元列包括沿所述第二方向排列的多个重复单元。所述重复单元包括沿第一方向排列的多个子像素，例如：所述重复单元包括沿第一方向排列的六个子像素，该六个子像素包括沿第一方向排列的BRGBRG，B代表蓝色子像素，R代表红色子像素，G代表绿色子像素。一组BRG代表一个子单元。
示例性的，所述多个重复单元包括的多个子像素呈阵列分布，该多个子像素能够划分为多列子像素列，所述多列子像素列与所述显示基板包括的多条数据线DA一一对应。
上述设置所述辅助电极40在所述衬底基板上的正投影，位于所述两个子单元在所述衬底基板上的正投影之间，更好的利用了布局空降，降低了所述辅助电极40的布局难度。
如图8至图18，图23和图24所示，在一些实施例中，所述显示基板还包括电源线VDD和电源补偿线30；
所述子像素驱动电路还包括发光控制晶体管T_em；所述发光控制晶体管T_em的第一极与所述电源补偿线30耦接，所述发光控制晶体管T_em的第二极与所述驱动晶体管DRT的第一极耦接；
所述电源补偿线30通过第六过孔结构与所述电源线VDD耦接，所述第六过孔结构位于所述子像素的非开口区。
示例性的，所述多条电源线VDD沿所述第一方向排列，所述电源线VDD包括沿所述第二方向延伸的至少部分。沿所述第一方向，所述电源线VDD与所述重复单元列交替设置。
示例性的，所述第六过孔结构包括第十八过孔Via18和第二十一过孔Via21。
在一些实施例中，所述显示基板还包括第一有机层，所述电源补偿线30位于所述第一有机层和所述衬底基板之间，所述电源线VDD位于所述第一有机层背向所述衬底基板的一侧，所述第六过孔结构贯穿所述第一有机层。
上述设置所述第六过孔结构位于所述子像素的非开口区，避免了所述第六连接结构占用开口区的空间，保证了显示基板的开口率，避免了第六连接结构对发光元件的平坦度产生影响。
在一些实施例中，所述电源线VDD在所述衬底基板上的正投影，与所述重复单元在所述衬底基板上的正投影沿所述第一方向交替设置。
如图1，图2，图8至图18，图23和图24所示，在一些实施例中，所述显示基板还包括：多条发光控制线EM，电源线VDD，初始化信号线Vini，基准信号线Vref，多条第一扫描线G1，多条第二扫描线G2，多条第三扫描线G3和多条分区控制线；
所述子像素驱动电路还包括：补偿晶体管T2，复位晶体管T3，发光控制晶体管T_em，写入控制晶体管T_com和存储电容Cst；
所述数据写入晶体管T1的栅极与对应的所述第一扫描线G1耦接，所述数据写入晶体管T1的第二极与所述写入控制晶体管T_com的第一极耦接；
所述写入控制晶体管T_com的第二极与所述驱动晶体管DRT的栅极耦接，所述写入控制晶体管T_com的栅极与对应的所述分区控制线耦接；
所述补偿晶体管T2的栅极与对应的所述第二扫描线G2耦接，所述补偿晶体管T2的第一极与所述基准信号线Vref耦接，所述补偿晶体管T2的第二极与所述写入控制晶体管T_com的第一极耦接；
所述复位晶体管T3的栅极与对应的所述第三扫描线G3耦接，所述复位 晶体管T3的第一极与所述初始化信号线Vini耦接，所述复位晶体管T3的第二极与所述驱动晶体管DRT的第二极耦接；
所述发光控制晶体管T_em的栅极与对应的所述发光控制线EM耦接，所述发光控制晶体管T_em的第一极与所述电源线VDD耦接，所述发光控制晶体管T_em的第二极与所述驱动晶体管DRT的第一极耦接；
所述存储电容Cst的第一极板Cst1与所述驱动晶体管DRT的栅极耦接，所述存储电容Cst的第二极板Cst2与所述驱动晶体管DRT的第二极耦接。
示例性的，所述初始化信号线Vini包括多个第一初始部21和多个第二初始部22，所述多个第一初始部21沿所述第二方向排列，所述多个第二初始部22沿所述第一方向排列，所述第一初始部21包括沿所述第一方向延伸的至少部分，所述第二初始部22包括沿所述第二方向延伸的至少部分，所述第一初始部21与各所述第二初始部22分别耦接，使得所述初始化信号线Vini形成为网格状结构，从而有效降低所述初始化信号线Vini的压降。
如图5所示，示例性的，所述有源层用于形成各所述晶体管包括的沟道部分，第一电极和第二电极。
如图5所示，示例性的，所述第一栅金属层用于形成各所述晶体管的栅极，所述第一支线111和所述第二初始部22。
如图7所示，示例性的，所述第二栅金属层用于所述存储电容Cst的第二基板。
如图10所示，示例性的，所述第一源漏金属层用于形成一些导电连接部，所述基准信号线Vref，所述第一扫描线G1，所述第二扫描线G2，所述第三扫描线G3，所述发光控制线EM和所述第一初始部21。同一个重复单元耦接的所述基准信号线Vref，所述第二扫描线G2，所述第一扫描线G1，所述第二支线112，发光控制线EM，所述电源补偿线30，所述第三扫描线G3和所述第一初始部21分沿所述第二方向依次排列。
示例性的，所述基准信号线Vref，所述第一扫描线G1，所述第二扫描线G2，所述第三扫描线G3和所述发光控制线EM均包括沿所述第一方向延伸的至少部分。
如图14所示，示例性的，所述第二源漏金属层用于形成所述电源线VDD， 所述数据线DA，一些导电连接部和辅助电极40。采用所述第二源漏金属层制作信号线能够有效降低所述信号线的负载，为中、大尺寸显示产品提供技术支持。示例性的，所述辅助电极40包括沿所述第二方向延伸的至少部分，所述辅助电极40通过采用氧化铟锡材料制作的连接图形41与第二电极层耦接，从而有效降低所述第二电极层的压降。
由于第一源漏金属层与第二源漏金属层之间具有第一有机层和第一钝化层，因此第一源漏金属层与第二源漏金属层之间相距较远，这样能够有效降低第一源漏金属层和第二源漏金属层之间的寄生电容，从而满足中、大尺寸显示产品的负载需求，为高刷新频率提供支持。
如图1所示，示例性的，所述子像素驱动电路包括：数据写入晶体管T1，写入控制晶体管T_com，驱动晶体管DRT，补偿晶体管T2，复位晶体管T3，发光控制晶体管T_em，存储电容Cst和发光元件EL的本征电容C1。
如图9所示，示意了形成在层间绝缘层上的过孔。如图5至图10所示，所述补偿晶体管T2的栅极通过第二过孔Via2与对应的所述第二扫描线G2耦接，所述补偿晶体管T2的第一极通过第一过孔Via1与所述基准信号线Vref耦接。
所述数据写入晶体管T1的栅极通过第三过孔Via3与对应的所述第一扫描线G1耦接。所述数据写入晶体管T1的第一极通过第九过孔Via9与第四导电连接部54耦接。
所述写入控制晶体管T_com的栅极通过第四过孔Via4与分区控制线G_com耦接，所述写入控制晶体管T_com的第二极通过第五过孔Via5与第一导电连接部51耦接，第一导电连接部51通过第六过孔Via6与驱动晶体管DRT的栅极耦接，驱动晶体管DRT的栅极复用为存储电容Cst的第一极板Cst1。
驱动晶体管DRT的第二极通过第七过孔Via7与第二导电连接部52耦接。第二导电连接部52通过第八过孔Via8与存储电容Cst的第二极板Cst2耦接。存储电容Cst的第二极板Cst2通过第十过孔Via10与第三导电连接部53耦接，第三导电连接部53通过第十五过孔Via15与复位晶体管T3的第二极耦接。
所述发光控制晶体管T_em的栅极通过第十一过孔Via11与对应的所述发光控制线EM耦接，所述发光控制晶体管T_em的第一极通过第十二过孔Via12与所述电源线VDD耦接。
所述复位晶体管T3的栅极通过第十四过孔Via14与第三扫描线G3耦接，所述复位晶体管T3的第一极通过第十三过孔Via13与第一初始部21耦接。
第一支线111通过第二十二过孔Via22与第二支线112耦接。第一初始部21通过第二十三过孔Via23与第二初始部22耦接。
如图12所示，示意了形成在第一有机层上的过孔。如图13所示，示意了形成在第一钝化层上的过孔。
如图11至图14所示，第二导电连接部52依次通过第十七过孔Via17和第二十过孔Via20与第五导电连接部部55耦接。第四导电连接部54依次通过第十六过孔Via16和第十九过孔Via19与数据线DA耦接。电源补偿线30一次通过第十八过孔Via18和第二十一过孔Via21与电源线VDD耦接。
如图16所示，示意了形成在第二钝化层上的过孔。如图17所示，示意了形成在第二有机层上的过孔。
如图15至图22所示，第五导电连接部55依次通过第二十四过孔Via24和第二十六过孔Via26与第一电极层42中对应的第一电极耦接。辅助电极40依次通过第二十五过孔Via25和第二十七过孔Via27与连接图形41耦接。连接图形41依次通过第二十八过孔Via28和第二十九过孔Via29与第二电极层耦接。
如图23所示，示意了子像素的开口区60，以及位于开口区60附近的非开口区61。
如图1所示，在一些实施例中，所述数据写入晶体管T1，所述补偿晶体管T2和所述复位晶体管T3均包括双栅结构，这样能够有效降低漏电流。
如图1所示，在一些实施例中，所述写入控制晶体管T_com包括单栅结构。
由于所述数据写入晶体管T1连接在所述数据线DA和所述写入控制晶体管T_com之间，当所述写入控制晶体管T_com关闭时，能够将所述数据写入晶体管T1的漏电途经关闭。所述写入控制晶体管T_com采用单栅结构设计， 有利于节省版图面积。
本公开实施例还提供了一种显示装置，包括上述实施例提供的显示基板。
需要说明的是，所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板等。
示例性的，所述显示装置包括有机发光二极管显示装置，但不仅限于此。
上述实施例提供的显示基板中，通过设置所述第一连接结构和所述第二连接结构均位于所述子像素的非开口区，避免了所述第一连接结构和所述第二连接结构占用开口区的空间，保证了显示基板的开口率，避免了第一连接结构和第二连接结构对发光元件的平坦度产生影响。
而且，上述实施例提供的显示基板中，通过设置所述第一连接结构在所述衬底基板上的正投影，与所述第二连接结构在所述衬底基板上的正投影沿第一方向排列；所述第二连接结构在所述衬底基板上的正投影与所述子像素的开口区沿第二方向排列；使得所述第一连接结构和所述第二连接结构均位于所述开口区沿所述第二方向的同一侧，且使得所述第一连接结构和所述第二连接结构在所述第二方向上占用较小的空间，从而使得所述开口区在所述第二方向上的尺寸能够最优化，有效提升了显示基板的开口率，提升了显示基板的使用寿命。
本公开实施例提供的显示装置在包括上述显示基板时，同样具有上述有益效果，此处不再赘述。
请参阅图1，图2，图3，图5，图21，本公开实施例提供了一种显示基板，包括：衬底基板，以及设置于所述衬底基板上的多个重复单元和多条数据线DA，所述多个重复单元划分为多列重复单元列；
每个重复单元包括多个子像素，所述子像素包括子像素驱动电路，所述子像素驱动电路包括数据写入晶体管T1，写入控制晶体管T_com和驱动晶体管DRT；所述数据写入晶体管T1的第一极与对应的所述数据线DA耦接，所述数据写入晶体管T1的第二极与所述写入控制晶体管T_com的第一极耦接，所述写入控制晶体管T_com的第二极与所述驱动晶体管DRT的栅极耦接；
所述显示基板还包括：多个控制区(如控制区1至控制区X)和多条分 区控制线G_com；所述控制区包括至少一列重复单元列；所述分区控制线G_com与对应的控制区中各重复单元列包括的写入控制晶体管T_com的栅极分别耦接。
示例性的，所述显示基板包括多个重复单元，所述多个重复单元呈阵列分布。所述重复单元包括沿第一方向排列的多个子像素，例如：所述重复单元包括沿第一方向排列的六个子像素，该六个子像素包括沿第一方向排列的BRGBRG，B代表蓝色子像素，R代表红色子像素，G代表绿色子像素。
示例性的，所述多个重复单元包括的多个子像素呈阵列分布，该多个子像素能够划分为多列子像素列，所述多列子像素列与所述显示基板包括的多条数据线DA一一对应。
示例性的，所述子像素包括子像素驱动电路和发光元件EL，所述子像素驱动电路与所述发光元件EL耦接，用于为所述发光元件EL提供驱动信号，以驱动所述发光元件EL发光。
示例性的，所述子像素驱动电路包括数据写入晶体管T1，写入控制晶体管T_com和驱动晶体管DRT；所述数据写入晶体管T1的第一极与对应的所述数据线DA耦接，所述数据写入晶体管T1的第二极与所述写入控制晶体管T_com的第一极耦接，所述写入控制晶体管T_com的第二极与所述驱动晶体管DRT的栅极耦接；在所述数据写入晶体管T1和所述写入控制晶体管T_com均导通的情况下，能够将所述数据线DA传输的数据信号写入所述驱动晶体管DRT的栅极；在所述数据写入晶体管T1和所述写入控制晶体管T_com中有一个截止的情况下，所述数据信号无法传输至所述驱动晶体管DRT的栅极。
示例性的，所述显示基板还包括多个控制区和多条分区控制线G_com，所述多个控制区域与所述多条分区控制线G_com一一对应。所述分区控制线G_com与对应的控制区中各重复单元列包括的写入控制晶体管T_com的栅极分别耦接，用于控制对应的控制区中各重复单元列包括的写入控制晶体管T_com的导通或截止。
根据上述显示基板的具体结构可知，本公开实施例提供的显示基板中，包括多个控制区，每个控制区包括至少一列重复单元列，所述分区控制线G_com与对应的控制区中各重复单元列包括的写入控制晶体管T_com的栅极 分别耦接。通过每条分区控制线G_com能够控制对应的控制区中的全部写入控制晶体管T_com是否导通，以实现控制该区域是否实现高刷新频率的效果。
更详细地说，如图3和图4所示，以显示基板包括X个控制区为例。
在第N帧显示时段：第一条分区控制线G_com<1>和第M条分区控制线G_com<M>传输的控制信号均为有效电平VGH，相应的第一条分区控制线G_com<1>对应的第一控制区中包括的全部写入控制晶体管T_com均导通，第M条分区控制线G_com<M>对应的第M控制区中包括的全部写入控制晶体管T_com均导通，这样能够保证第一控制区和第M控制区为能够实现正常刷新的区域，在对显示基板进行逐行扫描时，能够实现第一控制区和第M控制区的高刷新操作。第H条分区控制线G_com<H>传输的控制信号为非有效电平VGL，相应的第H条分区控制线G_com<H>对应的第H控制区中包括的全部写入控制晶体管T_com均截止，在对显示基板进行逐行扫描时，第H控制区无法实现高刷新操作，使得第H控制区在第N帧不刷新，其显示画面在第N帧内不更新，将节省的数据量提供给高刷区域，达到分区高刷的效果。值得注意，M和H均为大于1，小于X的正整数。
在消隐时段，通过控制分区控制线G_com传输的控制信号的电平，为N+1帧进行分区选择。值得注意，所述消隐时段位于每帧显示时段的起始或末尾。
在第N+1帧显示时段：第一条分区控制线G_com<1>和第H条分区控制线G_com<H>传输的控制信号均为有效电平VGH，相应的第一条分区控制线G_com<1>对应的第一控制区中包括的全部写入控制晶体管T_com均导通，第H条分区控制线G_com<H>对应的第H控制区中包括的全部写入控制晶体管T_com均导通，这样能够保证第一控制区和第H控制区为能够实现正常刷新的区域，在对显示基板进行逐行扫描时，能够实现第一控制区和第H控制区的高刷新操作。第M条分区控制线G_com<M>传输的控制信号为非有效电平VGL，相应的第M条分区控制线G_com<M>对应的第M控制区中包括的全部写入控制晶体管T_com均截止，在对显示基板进行逐行扫描时，第M控制区无法实现高刷新操作，使得第M控制区在第M帧不刷新，其显示画面在第M帧内不更新，将节省的数据量提供给高刷区域，达到分区高刷的效果。
值得注意，考虑到分区控制线G_com的负载较大，可以在第N帧结束时， 进入消隐时段时，立即对分区控制线G_com传输的控制信号进行调整。
本公开实施例提供的显示基板中，通过设置所述控制区和分区控制线G_com，使得大尺寸显示基板同样能够很好的实现显示基板的高刷新率功能。
需要说明，图4中括号内部代表的行数，如：G1<1>代表第一行第一扫描线，G2<1>代表第一行第二扫描线，G3<1>代表第一行第三扫描线，EM<1>代表第一行发光控制线。
如图3，图5，图8，图11，图15，图19和图21所示，在一些实施例中，所述分区控制线G_com包括：控制总线10和至少一条控制支线11；
所述控制支线11与对应的控制区中对应的一列重复单元列包括的各写入控制晶体管T_com的栅极分别耦接；所述控制总线10与所述至少一条控制支线11耦接。
示例性的，所述分区控制线G_com包括的控制支线11与其对应的控制区中包括的重复单元列一一对应。所述控制支线11与对应的控制区中对应的一列重复单元列包括的各写入控制晶体管T_com的栅极分别耦接，以控制对应的一列重复单元列包括的各写入控制晶体管T_com导通或截止。
示例性的，在同一条分区控制线G_com中，控制总线10和各条控制支线11分别耦接。示例性的，在同一条分区控制线G_com中，控制总线10和各条控制支线11形成为一体结构。
示例性的，所述显示基板还包括驱动芯片，所述控制总线10与所述驱动芯片位于所述显示基板的同一侧，所述控制总线10与所述驱动芯片耦接，接收所述驱动芯片提供的控制信号，并将接收到的控制信号传输至其耦接的各控制支线11，进而控制相应控制区中的写入控制晶体管T_com是否导通。
上述实施例提供的显示基板中，通过设置所述分区控制线G_com包括所述控制总线10和所述控制支线11，不仅能够更好的实现控制信号的传输，还能够降低所述分区控制线G_com的布局难度，保证所述分区控制线G_com与所述写入控制晶体管T_com的栅极耦接的信赖性。
如图3，图5，图8，图11，图15，图19和图21所示，在一些实施例中，所述控制支线11包括：第一支线111和多条第二支线112；所述第二支线112包括沿第一方向延伸的至少部分，所述多条第二支线112沿第二方向 排列；所述第一支线111包括沿所述第二方向延伸的至少部分，所述第一支线111分别与所述多条第二支线112耦接，所述第一支线111与所述控制总线10耦接；所述第一方向与所述第二方向相交；所述第二支线112与对应的重复单元包括的各写入控制晶体管T_com的栅极分别耦接。
示例性的，所述第一方向包括水平方向，所述第二方向包括竖直方向。
示例性的，在所述控制区中，所述控制支线11与所述重复单元列一一对应，所述控制支线11包括的多条第二支线112，与对应的重复单元列中包括的多个重复单元一一对应。所述重复单元包括沿所述第一方向排列的多个子像素，所述子像素包括的子像素驱动电路，所述子像素驱动电路包括写入控制晶体管T_com。所述第二支线112与对应的重复单元包括的各写入控制晶体管T_com的栅极分别耦接。示例性的，所述第二支线112与对应的重复单元包括的六个写入控制晶体管T_com的栅极分别耦接，以控制该六个写入控制晶体管T_com的导通和截止。
示例性的，所述控制支线11包括的第一支线111位于对应的重复单元列的中间区域，即所述第一支线111对应的重复单元列中，沿所述第一方向位于所述第一支线111两侧的子像素的数量相同。例如：沿所述第一方向，所述重复单元中位于对应的所述第一支线111左侧和右侧的子像素的数量均为三个。
示例性的，在同一条控制支线11中，所述第一支线111在所述衬底基板上的正投影，与各所述第二支线112在所述衬底基板上的正投影分别形成交叠区域，所述第一支线111在对应的交叠区域通过过孔与对应的所述第二支线112耦接。
上述实施例提供的显示基板中，通过设置所述控制支线11包括：第一支线111和多条第二支线112；不仅能够更好的实现控制信号的传输，还能够降低所述控制支线11的布局难度，保证所述控制支线11与所述写入控制晶体管T_com的栅极耦接的信赖性。
在一些实施例中，在同一个控制区中，沿第一方向相邻的所述第二支线112相耦接。
示例性的，在同一个控制区中，沿第一方向位于同一行的各所述第二支 线112依次首位相连。示例性的，在同一个控制区中，沿第一方向位于同一行的各所述第二支线112形成为一体结构。
示例性的，相邻的控制区中，沿所述第一方向相邻的第二支线112之间断开。
上述实施例提供的显示基板中，通过设置在同一个控制区中，沿第一方向相邻的所述第二支线112相耦接，使得在同一个控制区中，所述控制支线11能够形成网格状结构，有利于降低所述分区控制线G_com整体的负载，降低所述分区控制线G_com的压降。
在一些实施例中，在同一个控制区中，沿第一方向相邻的所述第二支线112相互独立。
如图11所示，在一些实施例中，所述显示基板还包括多条电源线VDD，所述第二支线112在所述衬底基板上的正投影，与所述电源线VDD在所述衬底基板上的正投影不交叠。
示例性的，所述多条电源线VDD沿所述第一方向排列，所述电源线VDD包括沿所述第二方向延伸的至少部分。沿所述第一方向，所述电源线VDD与所述重复单元列交替设置。
示例性的，所述显示基板还包括多条电源补偿线30，所述多条电源补偿线30沿所述第二方向排列，所述电源补偿线30包括沿所述第一方向延伸的至少部分。所述电源补偿线30与所述多条电源线VDD分别耦接，所述电源补偿线30和所述电源线VDD共同形成网格状结构，以降低电源线VDD的压降。
示例性的，所述电源补偿线30在所述衬底基板上的正投影，与所述电源线VDD在所述衬底基板上的正投影具有交叠区域，所述电源补偿线30与所述电源线VDD在该交叠区域通过过孔耦接。
上述实施例提供的显示基板中，通过设置沿第一方向相邻的所述第二支线112相互独立，以及所述第二支线112在所述衬底基板上的正投影，与所述电源线VDD在所述衬底基板上的正投影不交叠，使得所述控制支线11形成为非网格状结构，且能够避开所述电源线VDD，这样不仅能够降低控制支线11与电源线VDD之间发生短路的风险，还降低了所述控制支线11与电源线VDD之间形成的寄生电容。
如图11所示，在一些实施例中，所述数据线DA在所述衬底基板上的正投影与所述第二支线112在所述衬底基板上的正投影具有第一交叠区域，各所述数据线DA形成的所述第一交叠区域的面积相同。
示例性的，所述数据线DA与显示基板中的子像素列沿所述第一方向交替设置。所述数据线DA包括沿所述第二方向延伸的至少部分。
示例性的，所述数据线DA与所述第二支线112异层设置。各所述数据线DA与多条第二支线112之间形成的第一交叠区域的面积总和相同。
上述实施例提供的显示基板中，通过设置各所述数据线DA与多条第二支线112之间形成的第一交叠区域的面积总和相同，使得显示基板中各种颜色的子像素连接的数据线DA的负载相同，更好的保证了显示基板的显示画面均一性。
在一些实施例中，所述第一支线111采用显示基板中的第一栅金属层制作，所述第二支线112采用显示基板中的第一源漏金属层制作。
如图24所示，在一些实施例中，所述显示基板包括沿远离所述衬底基板70的方向依次层叠设置于所述衬底基板70上的：缓冲层71，有源层，第一栅极绝缘层，第一栅金属层，第二栅极绝缘层，第二栅金属层，层间绝缘层ILD，第一源漏金属层，第一有机层Resin1，第一钝化层PVX1，第二源漏金属层，第二钝化层PVX2，第二有机层Resin2，第一电极层42，第一像素界定层PDL1，第二像素界定层PDL2，发光功能层，第二电极层43，封装层。图24中还示意了第一连接结构81，第二连接结构82和第三连接结构83。所述第二电极层43接收负电源信号VSS。
上述实施例提供的显示基板中，通过设置所述第一支线111采用所述第一栅金属层制作，使得所述第一支线111能够与所述显示基板中采用所述第一栅金属层制作的其它结构在同一次构图工艺中形成，从而有效简化了显示基板的制作工艺流程。
上述实施例提供的显示基板中，通过设置所述第二支线112采用所述第一源漏金属层制作，使得所述第二支线112能够与所述显示基板中采用所述第一源漏金属层制作的其它结构在同一次构图工艺中形成，从而有效简化了显示基板的制作工艺流程。
上述实施例提供的显示基板中，通过设置所述分区控制线G_com包括所述控制总线10和所述控制支线11，以及设置所述控制支线11包括所述第一支线111和所述多条第二支线112，使得所述分区控制线G_com在控制区内部为并联设计，其等效电阻较小，且所述所述第一支线111采用显示基板中的第一栅金属层制作，所述第一栅金属层的方块电阻较大，对寄生电阻影响较小。而且，所述第一支线111采用显示基板中的第一栅金属层制作，所述第二支线112采用显示基板中的第一源漏金属层制作，有效降低了分区控制线G_com与采用第二源漏金属层制作的结构之间形成的寄生电容，从而优化了分区控制线G_com的负载，达到了分区控制优化的效果。
如图1，图5，图6，图7，图11，图15，图19和图21所示，在一些实施例中，所述显示基板还包括：多条第一扫描线G1，多条第二扫描线G2，多条第三扫描线G3，多条发光控制线EM，电源线VDD，基准信号线Vref和初始化信号线Vini；
所述子像素驱动电路还包括：补偿晶体管T2，复位晶体管T3，发光控制晶体管T_em和存储电容Cst；
所述数据写入晶体管T1的栅极与对应的所述第一扫描线G1耦接；
所述补偿晶体管T2的栅极与对应的所述第二扫描线G2耦接，所述补偿晶体管T2的第一极与所述基准信号线Vref耦接，所述补偿晶体管T2的第二极与所述写入控制晶体管T_com的第一极耦接；
所述复位晶体管T3的栅极与对应的所述第三扫描线G3耦接，所述复位晶体管T3的第一极与所述初始化信号线Vini耦接，所述复位晶体管T3的第二极与所述驱动晶体管DRT的第二极耦接；
所述发光控制晶体管T_em的栅极与对应的所述发光控制线EM耦接，所述发光控制晶体管T_em的第一极与所述电源线VDD耦接，所述发光控制晶体管T_em的第二极与所述驱动晶体管DRT的第一极耦接；
所述存储电容Cst的第一极板Cst1与所述驱动晶体管DRT的栅极耦接，所述存储电容Cst的第二极板Cst2与所述驱动晶体管DRT的第二极耦接。
示例性的，所述初始化信号线Vini包括多个第一初始部21和多个第二初始部22，所述多个第一初始部21沿所述第二方向排列，所述多个第二初 始部22沿所述第一方向排列，所述第一初始部21包括沿所述第一方向延伸的至少部分，所述第二初始部22包括沿所述第二方向延伸的至少部分，所述第一初始部21与各所述第二初始部22分别耦接，使得所述初始化信号线Vini形成为网格状结构，从而有效降低所述初始化信号线Vini的压降。
如图5所示，示例性的，所述有源层用于形成各所述晶体管包括的沟道部分，第一电极和第二电极。
如图5所示，示例性的，所述第一栅金属层用于形成各所述晶体管的栅极，所述第一支线111和所述第二初始部22。
如图7所示，示例性的，所述第二栅金属层用于所述存储电容Cst的第二基板。
如图10所示，示例性的，所述第一源漏金属层用于形成一些导电连接部，所述基准信号线Vref，所述第一扫描线G1，所述第二扫描线G2，所述第三扫描线G3，所述发光控制线EM和所述第一初始部21。同一个重复单元耦接的所述基准信号线Vref，所述第二扫描线G2，所述第一扫描线G1，所述第二支线112，发光控制线EM，所述电源补偿线30，所述第三扫描线G3和所述第一初始部21分沿所述第二方向依次排列。
示例性的，所述基准信号线Vref，所述第一扫描线G1，所述第二扫描线G2，所述第三扫描线G3和所述发光控制线EM均包括沿所述第一方向延伸的至少部分。
如图14所示，示例性的，所述第二源漏金属层用于形成所述电源线VDD，所述数据线DA，一些导电连接部和辅助电极40。示例性的，所述辅助电极40包括沿所述第二方向延伸的至少部分，所述辅助电极40通过采用氧化铟锡材料制作的连接图形41与第二电极层耦接，从而有效降低所述第二电极层的压降。
如图1所示，示例性的，所述子像素驱动电路包括：数据写入晶体管T1，写入控制晶体管T_com，驱动晶体管DRT，补偿晶体管T2，复位晶体管T3，发光控制晶体管T_em，存储电容Cst和发光元件EL的本征电容C1。
如图9所示，示意了形成在层间绝缘层上的过孔。如图5至图10所示，所述补偿晶体管T2的栅极通过第二过孔Via2与对应的所述第二扫描线G2耦 接，所述补偿晶体管T2的第一极通过第一过孔Via1与所述基准信号线Vref耦接。
所述数据写入晶体管T1的栅极通过第三过孔Via3与对应的所述第一扫描线G1耦接。所述数据写入晶体管T1的第一极通过第九过孔Via9与第四导电连接部54耦接。
所述写入控制晶体管T_com的栅极通过第四过孔Via4与分区控制线G_com耦接，所述写入控制晶体管T_com的第二极通过第五过孔Via5与第一导电连接部51耦接，第一导电连接部51通过第六过孔Via6与驱动晶体管DRT的栅极耦接，驱动晶体管DRT的栅极复用为存储电容Cst的第一极板Cst1。
驱动晶体管DRT的第二极通过第七过孔Via7与第二导电连接部52耦接。第二导电连接部52通过第八过孔Via8与存储电容Cst的第二极板Cst2耦接。存储电容Cst的第二极板Cst2通过第十过孔Via10与第三导电连接部53耦接，第三导电连接部53通过第十五过孔Via15与复位晶体管T3的第二极耦接。
所述发光控制晶体管T_em的栅极通过第十一过孔Via11与对应的所述发光控制线EM耦接，所述发光控制晶体管T_em的第一极通过第十二过孔Via12与所述电源线VDD耦接。
所述复位晶体管T3的栅极通过第十四过孔Via14与第三扫描线G3耦接，所述复位晶体管T3的第一极通过第十三过孔Via13与第一初始部21耦接。
第一支线111通过第二十二过孔Via22与第二支线112耦接。第一初始部21通过第二十三过孔Via23与第二初始部22耦接。
如图12所示，示意了形成在第一有机层上的过孔。如图13所示，示意了形成在第一钝化层上的过孔。
如图11至图14所示，第二导电连接部52依次通过第十七过孔Via17和第二十过孔Via20与第五导电连接部部55耦接。第四导电连接部54依次通过第十六过孔Via16和第十九过孔Via19与数据线DA耦接。电源补偿线30一次通过第十八过孔Via18和第二十一过孔Via21与电源线VDD耦接。
如图16所示，示意了形成在第二钝化层上的过孔。如图17所示，示意 了形成在第二有机层上的过孔。
如图15至图22所示，第五导电连接部55依次通过第二十四过孔Via24和第二十六过孔Via26与第一电极层42中对应的第一电极耦接。辅助电极40依次通过第二十五过孔Via25和第二十七过孔Via27与连接图形41耦接。连接图形41依次通过第二十八过孔Via28和第二十九过孔Via29与第二电极层耦接。
如图23所示，示意了像素的开口区60，以及位于开口区60附近的非开口区61。
如图1所示，在一些实施例中，所述数据写入晶体管T1，所述补偿晶体管T2和所述复位晶体管T3均包括双栅结构，这样能够有效降低漏电流。
如图1所示，在一些实施例中，所述写入控制晶体管T_com包括单栅结构。
由于所述数据写入晶体管T1连接在所述数据线DA和所述写入控制晶体管T_com之间，当所述写入控制晶体管T_com关闭时，能够将所述数据写入晶体管T1的漏电途经关闭。所述写入控制晶体管T_com采用单栅结构设计，有利于节省版图面积。
本公开实施例还提供了一种显示基板的驱动方法，用于驱动上述实施例提供的显示基板，所述驱动方法包括：
在第N帧显示时段中，显示基板中多条分区控制线G_com中的至少部分分区控制线G_com传输的分区控制信号处于有效电平，所述至少部分分区控制线G_com耦接的写入控制晶体管T_com导通，对所述多个子像素进行逐行扫描，实现逐行写入数据信号；
在第N+1帧显示时段中，所述多条分区控制线G_com传输的分区控制信号的电平发生变化，使传输有效电平的分区控制信号的分区控制线G_com耦接的写入控制晶体管T_com导通，对所述多个子像素进行逐行扫描，实现逐行写入数据信号。
以显示基板包括X个控制区为例。
示例性的，在第N帧显示时段中，显示基板中第一条分区控制线G_com<1>和第M条分区控制线G_com<M>传输的控制信号均为有效电平VGH，相应的第 一条分区控制线G_com<1>对应的第一控制区中包括的全部写入控制晶体管T_com均导通，第M条分区控制线G_com<M>对应的第M控制区中包括的全部写入控制晶体管T_com均导通，这样能够保证第一控制区和第M控制区为能够实现正常刷新的区域，在对显示基板进行逐行扫描时，能够实现第一控制区和第M控制区的高刷新操作。在第N+1帧显示时段中，多条分区控制线G_com传输的分区控制信号的电平发生变化，使第一条分区控制线G_com<1>和第H条分区控制线G_com<H>传输的控制信号均为有效电平VGH，相应的第一条分区控制线G_com<1>对应的第一控制区中包括的全部写入控制晶体管T_com均导通，第H条分区控制线G_com<H>对应的第H控制区中包括的全部写入控制晶体管T_com均导通，这样能够保证第一控制区和第H控制区为能够实现正常刷新的区域，在对显示基板进行逐行扫描时，能够实现第一控制区和第H控制区的高刷新操作。
在对显示基板进行逐行扫描以写入数据信号时，可以根据实际需要，控制每两行子像素驱动电路或者每四行子像素驱动电路同时实现复位、补偿。
采用本公开实施例提供的驱动方法驱动显示基板时，通过每条分区控制线G_com能够控制对应的控制区中的全部写入控制晶体管T_com是否导通，以实现控制该区域是否实现高刷新频率的效果，使得大尺寸显示基板同样能够很好的实现显示基板的高刷新率功能。
在一些实施例中，所述驱动方法还包括：
消隐时段，所述消隐时段位于每帧显示时段的起始或末尾；在所述消隐时段，调整所述多条分区控制线传输的分区控制信号的电平。
示例性的，在第N帧结束时，进入第N+1帧的消隐时段时，立即对分区控制线G_com传输的控制信号进行调整。
本公开实施例还提供了一种显示装置，包括上述实施例提供的显示基板。
需要说明的是，所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板等。
示例性的，所述显示装置包括有机发光二极管显示装置，但不仅限于此。
上述实施例提供的显示基板中，包括多个控制区，每个控制区包括至少 一列重复单元列，所述分区控制线与对应的控制区中各重复单元列包括的写入控制晶体管的栅极分别耦接。通过每条分区控制线能够控制对应的控制区中的全部写入控制晶体管是否导通，以实现控制该区域是否实现高刷新频率的效果。上述实施例提供的显示基板中，通过设置所述控制区和分区控制线，使得大尺寸显示基板同样能够很好的实现显示基板的高刷新率功能。
本公开实施例提供的显示装置在包括上述显示基板时，同样具有上述有益效果，此处不再赘述。
需要说明，信号线沿某方向延伸是指：信号线包括主要部分和与所述主要部分连接的次要部分，所述主要部分是线、线段或条形状体，所述主要部分沿某方向延展，且所述主要部分沿某方向延展的长度大于次要部分沿其它方向伸展的长度。
需要说明的是，本公开实施例的“同层”可以指的是处于相同结构层上的膜层。或者例如，处于同层的膜层可以是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的。这些特定图形还可能处于不同的高度或者具有不同的厚度。
在本公开各方法实施例中，所述各步骤的序号并不能用于限定各步骤的先后顺序，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，对各步骤的先后变化也在本公开的保护范围之内。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其 他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种显示基板，包括：衬底基板，以及设置于所述衬底基板上的多条数据线和多个子像素；所述子像素包括子像素驱动电路和发光元件；所述子像素驱动电路包括驱动晶体管和数据写入晶体管，所述发光元件包括第一电极；
    所述驱动晶体管的第二极通过第一连接结构与对应的所述第一电极耦接；所述数据写入晶体管的第一极通过第二连接结构与对应的所述数据线耦接；
    所述第一连接结构和所述第二连接结构均位于所述子像素的非开口区，所述第一连接结构在所述衬底基板上的正投影，与所述第二连接结构在所述衬底基板上的正投影沿第一方向排列；
    所述第二连接结构在所述衬底基板上的正投影与所述子像素的开口区沿第二方向排列，所述第二方向与所述第一方向相交。
  2. 根据权利要求1所述的显示基板，其中，所述第一连接结构包括：第二导电连接部，第一过孔结构，第五导电连接部和第二过孔结构；
    所述第二导电连接部与所述驱动晶体管的第二极耦接，所述第二导电连接部通过所述第一过孔结构与所述第五导电连接部耦接，所述第五导电连接部通过所述第二过孔结构与对应的所述第一电极耦接。
  3. 根据权利要求2所述的显示基板，其中，所述第二连接结构包括：第四导电连接部和第三过孔结构；所述第四导电连接部与所述数据写入晶体管的第一极耦接，所述第四导电连接部通过所述第三过孔结构与对应的所述数据线耦接。
  4. 根据权利要求3所述的显示基板，其中，所述显示基板还包括沿远离所述衬底基板的方向依次层叠设置的第一有机层和第二有机层，所述第一过孔结构贯穿所述第一有机层，所述第二过孔结构贯穿所述第二有机层；
    所述第二导电连接部位于所述第一有机层与所述衬底基板之间，所述第五导电连接部位于第一有机层和所述第二有机层之间。
  5. 根据权利要求4所述的显示基板，其中，所述第三过孔结构贯穿所述 第一有机层，所述第四导电连接部位于所述第一有机层与所述衬底基板之间。
  6. 根据权利要求5所述的显示基板，其中，所述显示基板还包括：第一钝化层和第二钝化层；所述第一钝化层位于所述第一有机层和所述第二钝化层之间，所述第二钝化层位于所述第一钝化层和所述第二有机层之间；
    所述第一过孔结构和所述第三过孔结构均贯穿所述第一钝化层，所述第二过孔结构贯穿所述第二钝化层；所述第五导电连接部位于所述第一钝化层和所述第二钝化层之间。
  7. 根据权利要求1所述的显示基板，其中，所述显示基板还包括：辅助电极，第三连接结构和第二电极层；所述辅助电极通过所述第三连接结构与所述第二电极层耦接；
    所述第三连接结构位于所述子像素的非开口区，所述第三连接结构在所述衬底基板上的正投影，与所述第一连接结构在所述衬底基板上的正投影沿第一方向排列。
  8. 根据权利要求1所述的显示基板，其中，所述显示基板还包括：辅助电极，第三连接结构和第二电极层；所述辅助电极通过所述第三连接结构与所述第二电极层耦接；
    所述第三连接结构位于所述子像素的非开口区，所述第三连接结构在所述衬底基板上的正投影，与所述第一连接结构在所述衬底基板上的正投影至少部分错开。
  9. 根据权利要求7或8所述的显示基板，其中，所述显示基板还包括沿远离所述衬底基板的方向依次层叠设置的第二有机层和像素界定层；
    所述第三连接结构包括：第四过孔结构，连接图形和第五过孔结构；所述辅助电极位于所述第二有机层与所述衬底基板之间，所述第二电极层的至少部分位于所述像素界定层背向所述衬底基板的一侧，所述连接图形的至少部分位于所述第二有机层与所述像素界定层之间，所述第四过孔结构贯穿所述第二有机层，所述第五过孔结构贯穿所述像素界定层；
    所述连接图形通过所述第四过孔结构与所述辅助电极耦接，所述连接图形通过所述第五过孔结构与所述第二电极层耦接。
  10. 根据权利要求9所述的显示基板，其中，所述多个子像素划分为呈 阵列分布的多个重复单元，每个重复单元包括沿第一方向排列的两个子单元，每个子单元包括沿所述第一方向排列的多个所述子像素；
    所述辅助电极在所述衬底基板上的正投影，位于所述两个子单元在所述衬底基板上的正投影之间。
  11. 根据权利要求10所述的显示基板，其中，所述显示基板还包括电源线和电源补偿线；
    所述子像素驱动电路还包括发光控制晶体管；所述发光控制晶体管的第一极与所述电源补偿线耦接，所述发光控制晶体管的第二极与所述驱动晶体管的第一极耦接；
    所述电源补偿线通过第六过孔结构与所述电源线耦接，所述第六过孔结构位于所述子像素的非开口区。
  12. 根据权利要求11所述的显示基板，其中，所述显示基板还包括第一有机层，所述电源补偿线位于所述第一有机层和所述衬底基板之间，所述电源线位于所述第一有机层背向所述衬底基板的一侧，所述第六过孔结构贯穿所述第一有机层。
  13. 根据权利要求11所述的显示基板，其中，所述电源线在所述衬底基板上的正投影，与所述重复单元在所述衬底基板上的正投影沿所述第一方向交替设置。
  14. 根据权利要求1所述的显示基板，其中，所述显示基板还包括：多条发光控制线，电源线，初始化信号线，基准信号线，多条第一扫描线，多条第二扫描线，多条第三扫描线和多条分区控制线；
    所述子像素驱动电路还包括：补偿晶体管，复位晶体管，发光控制晶体管，写入控制晶体管和存储电容；
    所述数据写入晶体管的栅极与对应的所述第一扫描线耦接，所述数据写入晶体管的第二极与所述写入控制晶体管的第一极耦接；
    所述写入控制晶体管的第二极与所述驱动晶体管的栅极耦接，所述写入控制晶体管的栅极与对应的所述分区控制线耦接；
    所述补偿晶体管的栅极与对应的所述第二扫描线耦接，所述补偿晶体管的第一极与所述基准信号线耦接，所述补偿晶体管的第二极与所述写入控制 晶体管的第一极耦接；
    所述复位晶体管的栅极与对应的所述第三扫描线耦接，所述复位晶体管的第一极与所述初始化信号线耦接，所述复位晶体管的第二极与所述驱动晶体管的第二极耦接；
    所述发光控制晶体管的栅极与对应的所述发光控制线耦接，所述发光控制晶体管的第一极与所述电源线耦接，所述发光控制晶体管的第二极与所述驱动晶体管的第一极耦接；
    所述存储电容的第一极板与所述驱动晶体管的栅极耦接，所述存储电容的第二极板与所述驱动晶体管的第二极耦接。
  15. 一种显示装置，包括如权利要求1～14中任一项所述的显示基板。
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