WO2024087153A1 - 半导体器件的质量改善方法、装置及高能粒子束光刻设备 - Google Patents

半导体器件的质量改善方法、装置及高能粒子束光刻设备 Download PDF

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WO2024087153A1
WO2024087153A1 PCT/CN2022/128194 CN2022128194W WO2024087153A1 WO 2024087153 A1 WO2024087153 A1 WO 2024087153A1 CN 2022128194 W CN2022128194 W CN 2022128194W WO 2024087153 A1 WO2024087153 A1 WO 2024087153A1
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particle beam
energy particle
pixel
grayscale
adjusted
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PCT/CN2022/128194
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English (en)
French (fr)
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张洁
张启华
简维廷
洪流
袁元
张勇为
蒋军浩
汪俊亮
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袁元
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Priority to PCT/CN2022/128194 priority Critical patent/WO2024087153A1/zh
Publication of WO2024087153A1 publication Critical patent/WO2024087153A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
    • H01J37/317—Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers

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  • the embodiments of the present application relate to the field of semiconductor processing technology, and in particular, to a method and device for improving the quality of semiconductor devices and a high-energy particle beam lithography device.
  • the high-energy particle beam in this application can be an ion beam, electron beam, laser beam, X-ray, etc., among which the experiment uses a high-energy particle beam.
  • High-energy particle beams have a smaller wavelength than ordinary optical systems, which can improve the resolution of layout transfer and are suitable for making smaller devices. For example, due to wavelength limitations, DUV lithography machines are only suitable for making devices with feature sizes greater than 7nm; for the production of devices below 7nm, EUV must be introduced. High-energy particle beams have a smaller wavelength than EUV.
  • the present application provides a method and device for improving the quality of semiconductor devices and a high-energy particle beam lithography device, which can complete the processing of semiconductor devices without making integrated circuit masks, thereby improving processing efficiency.
  • the technical solution is as follows:
  • an embodiment of the present application provides a method for improving the quality of a semiconductor device, comprising:
  • the integrated circuit layout includes several layers of integrated circuit sub-layouts, and each layer of the integrated circuit sub-layout corresponds to a pattern of one or more material layers of the target semiconductor device;
  • the high-energy particle beam processing parameters corresponding to the first pixel to be adjusted and the high-energy particle beam processing parameters corresponding to the second pixel to be adjusted are obtained, and the high-energy particle beam processing parameters corresponding to the first pixel to be adjusted and the high-energy particle beam processing parameters corresponding to the second adjustment pixel with the same coordinates are added to obtain the combined high-energy particle beam processing parameters corresponding to each combined engraving coordinate;
  • a preset grayscale value adjustment strategy adjust the grayscale value of the first pixel to be adjusted and the grayscale value of the second pixel to be adjusted in the grayscale image of the i-1th to jth layers;
  • the high-energy particle beam processing parameters corresponding to each pixel in the grayscale image are obtained;
  • Each corresponding material layer is sequentially manufactured on the target substrate, and according to the high-energy particle beam processing parameters corresponding to each pixel point in the grayscale image, the high-energy particle beam lithography equipment is controlled to emit a high-energy particle beam and act on the corresponding material layer on the target substrate, and the pattern corresponding to the grayscale image is engraved on the corresponding material layer on the target substrate to obtain the target semiconductor device; wherein, after engraving the j-th material layer, before setting the j+1-th material layer, the method also includes the following steps: according to the combined high-energy particle beam processing parameters corresponding to each of the combined engraving coordinates, the high-energy particle beam lithography equipment is controlled to emit a high-energy particle beam and act on each of the combined engraving coordinates of the j-th material layer, and the j to i-1-th material layers are combined and engraved at each of the combined engraving coordinates.
  • an embodiment of the present application provides a semiconductor device quality improvement device, comprising:
  • a first acquisition module is used to acquire an integrated circuit layout corresponding to a target semiconductor device; wherein the integrated circuit layout includes a plurality of layers of integrated circuit sub-layouts, each layer of the integrated circuit sub-layout corresponds to a pattern of one or more material layers of the target semiconductor device;
  • a layout conversion module used to convert several layers of the integrated circuit sub-layouts into several layers of grayscale images in a preset format
  • a pixel recognition module configured to obtain, based on the grayscale images of the plurality of layers and a preset pixel recognition strategy, a first pixel to be adjusted in the grayscale images of the i-th to j-th layers, and a second pixel to be adjusted in the grayscale images of the i-1-th layer having the same coordinates as the first pixel to be adjusted;
  • a second acquisition module is used to acquire the high-energy particle beam processing parameters corresponding to the first pixel to be adjusted and the high-energy particle beam processing parameters corresponding to the second pixel to be adjusted according to the corresponding relationship between the preset high-energy particle beam processing parameters and the grayscale value, and add the high-energy particle beam processing parameters corresponding to the first pixel to be adjusted and the high-energy particle beam processing parameters corresponding to the second adjustment pixel with the same coordinates to acquire the combined high-energy particle beam processing parameters corresponding to each combined engraving coordinate;
  • a grayscale value adjustment module used for adjusting the grayscale values of the first to-be-adjusted pixel points and the second to-be-adjusted pixel points in the grayscale images of the i-1th to jth layers according to a preset grayscale value adjustment strategy;
  • a third acquisition module is used to acquire the high-energy particle beam processing parameter corresponding to each pixel point in the grayscale image according to the corresponding relationship between the preset high-energy particle beam processing parameter and the grayscale value;
  • a processing control module is used to sequentially manufacture each corresponding material layer on the target substrate, and control the high-energy particle beam lithography equipment to emit a high-energy particle beam and act on the corresponding material layer on the target substrate according to the high-energy particle beam processing parameters corresponding to each pixel point in the grayscale image, and engrave the pattern corresponding to the grayscale image to the corresponding material layer on the target substrate to obtain the target semiconductor device; wherein, after engraving the j-th material layer and before setting the j+1-th material layer, the step of controlling the high-energy particle beam lithography equipment to emit a high-energy particle beam and act on each of the combined engraving coordinates of the j-th material layer according to the combined high-energy particle beam processing parameters corresponding to each of the combined engraving coordinates, and combined engraving the j to i-1-th material layers at each of the combined engraving coordinates.
  • an embodiment of the present application provides a high-energy particle beam lithography device, comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the steps of the semiconductor device quality improvement method as described in the first aspect are implemented.
  • the integrated circuit sub-layout is converted into several layers of grayscale images, and the high-energy particle beam processing parameters corresponding to each pixel are obtained according to the grayscale value of each pixel in the grayscale image. Then, each corresponding material layer is sequentially manufactured on the target substrate, and the high-energy particle beam lithography equipment is controlled to emit a high-energy particle beam to act on the corresponding material layer according to the high-energy particle beam processing parameters corresponding to each pixel in the grayscale image, and the pattern corresponding to the grayscale image is engraved on the corresponding material layer, and finally the target semiconductor device is obtained.
  • This method of processing semiconductor devices without manufacturing multiple mask plates can greatly save costs, improve engraving accuracy, and can flexibly modify the integrated circuit layout to improve processing efficiency.
  • a preset pixel point recognition strategy is used to identify the first pixel points to be adjusted that can be combined and engraved from the grayscale images of the i-th to j-th layers, and to identify the second pixel points to be adjusted that can be engraved together with the first pixel points to be adjusted from the grayscale images of the i-1-th layer, and then based on the preset grayscale value adjustment strategy, the grayscale values of the first pixel points to be adjusted and the second pixel points to be adjusted are adjusted, so that when engraving the i-1-th to j-th material layers, the pattern composed of the second pixel points to be adjusted and the pattern composed of the first pixel points to be engraved will not be engraved.
  • the pattern composed of the first pixel points to be adjusted and the pattern composed of the second pixel points to be engraved are combined and engraved together to the corresponding j-th to i-1-th material layers, thereby further improving the processing efficiency of semiconductor devices.
  • FIG1 is a schematic flow chart of a method for improving the quality of a semiconductor device provided by an embodiment of the present application
  • FIG. 2 is a schematic diagram of a flow chart of S103 in a method for improving the quality of a semiconductor device provided by an embodiment of the present application;
  • FIG3 is a schematic diagram of a grayscale image corresponding to a layout of an integrated circuit of four MOS tubes connected in parallel provided by an embodiment of the present application;
  • FIG. 4 is a schematic diagram of a flow chart of S105 in a method for improving the quality of a semiconductor device provided by an embodiment of the present application;
  • FIG5 is a schematic flow chart of S105 in a method for improving the quality of a semiconductor device provided by another embodiment of the present application.
  • FIG. 6 is a flow chart of S107 in a method for improving the quality of a semiconductor device provided by an embodiment of the present application
  • FIG7 is a schematic structural diagram of a semiconductor device quality improvement device provided by an embodiment of the present application.
  • FIG8 is a schematic diagram of the structure of a high-energy particle beam lithography device provided in one embodiment of the present application.
  • first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other.
  • first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information.
  • the words "if"/"if” as used herein may be interpreted as "at the time of" or "when” or "in response to determination".
  • FIG. 1 is a flow chart of a method for improving the quality of a semiconductor device provided by an embodiment of the present application.
  • the method comprises the following steps:
  • S101 Obtain an integrated circuit layout corresponding to a target semiconductor device; wherein the integrated circuit layout includes several layers of integrated circuit sub-layouts, and each layer of the integrated circuit sub-layout corresponds to a pattern of one or more material layers of the target semiconductor device.
  • the executor of the semiconductor device quality improvement method may be a high-energy particle beam lithography device, or a component in the high-energy particle beam lithography device, such as a processor or microprocessor inside the device; in another optional embodiment, the executor of the semiconductor device quality improvement method may be an external device that establishes a data connection with the high-energy particle beam lithography device, or a component in the external device.
  • the execution body of the semiconductor device quality improvement method is a high-energy particle beam lithography device.
  • the high-energy particle beam lithography equipment obtains the integrated circuit layout corresponding to the target semiconductor device.
  • the target semiconductor device may be any type of semiconductor device, and its specific type is not limited herein.
  • the integrated circuit layout refers to mapping the circuit design circuit diagram or circuit description language to the physical description level.
  • the integrated circuit layout includes relevant physical information such as the device type, device size, relative position between devices, and connection relationship between each device of the integrated circuit.
  • the integrated circuit layout includes several layers of integrated circuit sub-layouts, and each layer of the integrated circuit sub-layout corresponds to the pattern of a material layer of the target semiconductor device.
  • the material layer includes but is not limited to an active layer, an insulating layer, a polysilicon gate layer, a metal layer, and the like.
  • S102 Converting the plurality of layers of the integrated circuit sub-layouts into a plurality of layers of grayscale images in a preset format.
  • the high-energy particle beam lithography equipment converts the several layers of the integrated circuit sub-layouts into several layers of grayscale images in a preset format.
  • the preset format is a TIF format.
  • the preset format may be other image formats that can be recognized and processed by a high-energy particle beam lithography device.
  • the grayscale value of the pixel in the grayscale image is 0 to 255, where a grayscale value of 0 indicates that the pixel has a lower brightness, and the human body subjectively perceives it as black, and a grayscale value of 255 indicates that the pixel has a higher brightness, and the human body subjectively perceives it as white.
  • S103 Based on the grayscale images of several layers and a preset pixel recognition strategy, obtain a first pixel to be adjusted in the grayscale images of the i-j layers and a second pixel to be adjusted in the grayscale images of the i-1th layer with the same coordinates as the first pixel to be adjusted.
  • the high-energy particle beam lithography equipment can obtain the pixel points corresponding to the positions of the through holes in the i-j grayscale images through a preset pixel point recognition strategy, that is, the first pixel points to be adjusted.
  • the high-energy particle beam lithography equipment also needs to obtain the second pixel point to be adjusted in the grayscale image of the i-1 layer with the same coordinates as the first pixel point to be adjusted.
  • step S103 includes steps S1031 to S1032, which are specifically as follows:
  • S1031 Obtain target pixel points in the grayscale image corresponding to each layer of the integrated circuit sub-layout and the coordinates of the target pixel points in the grayscale image; wherein the target pixel points are pixel points whose grayscale values are lower than a preset threshold.
  • the target pixel is a pixel whose grayscale value is lower than a preset threshold value, wherein the preset threshold value is related to the correspondence between the preset high-energy particle beam processing parameter and the grayscale value, and can be set according to actual conditions, and is not limited here.
  • FIG 3 is a schematic diagram of a grayscale image corresponding to a layout of an integrated circuit of four MOS tubes connected in parallel according to an embodiment of the present application.
  • the integrated circuit layout in Figure 3 includes an active layer, a polysilicon gate layer, a metal layer, and an insulating layer (not shown) on the active layer and the polysilicon gate layer.
  • the target pixel points with the same coordinates exist in the grayscale images of the i-j layers, then these target pixel points are the first pixel points to be adjusted in the grayscale images of the i-j layers, and the high-energy particle beam lithography equipment obtains the first pixel point to be adjusted in the grayscale images of the i-j layers and the second pixel point to be adjusted in the grayscale image of the i-1 layer with the same coordinates as the first pixel point to be adjusted.
  • the correspondence between the preset high-energy particle beam processing parameters and the grayscale values can be preset and stored in the high-energy particle beam lithography equipment. In another optional embodiment, the correspondence between the preset high-energy particle beam processing parameters and the grayscale values can be preset and stored in the cloud or host computer, and then downloaded to the high-energy particle beam lithography equipment when used.
  • the corresponding relationship between the high-energy particle beam processing parameters and the grayscale value is also different.
  • the corresponding relationship between the high-energy particle beam processing parameters and the grayscale value can be found according to the identification of the semiconductor device, or the corresponding relationship between the high-energy particle beam processing parameters and the grayscale value can be found according to the material identification of the material layer.
  • a third-party semiconductor device design manufacturer can upload the designed semiconductor device identification or material identification to the cloud, and configure the corresponding relationship between the high-energy particle beam processing parameters and the grayscale value, so that the high-energy particle beam lithography equipment can control the high-energy particle beam lithography equipment to complete the processing of more types of semiconductor devices and meet more third-party customer needs.
  • the high-energy particle beam lithography equipment obtains the high-energy particle beam processing parameters corresponding to the first pixel to be adjusted and the high-energy particle beam processing parameters corresponding to the second pixel to be adjusted according to the corresponding relationship between the preset high-energy particle beam processing parameters and the grayscale value.
  • the high-energy particle beam lithography equipment adds the high-energy particle beam processing parameters corresponding to the first pixel point to be adjusted and the high-energy particle beam processing parameters corresponding to the second adjustment pixel point with the same coordinates to obtain the combined high-energy particle beam processing parameters corresponding to each combined engraving coordinate.
  • the coordinates of the first pixel to be adjusted in the i-j layer are (x1, y1), (x2, y2), ..., (xn, yn)
  • the high-energy particle beam processing parameters corresponding to the first pixel to be adjusted with coordinates (x1, y1) in the i-j layer are added to the high-energy particle beam processing parameters corresponding to the second pixel to be adjusted with coordinates (x1, y1) in the i-1 layer, where (x1, y1) is a combined engraving coordinate
  • the high-energy particle beam processing parameters obtained by adding are the combined high-energy particle beam processing parameters corresponding to the combined engraving coordinates (x1, y1).
  • the high-energy particle beam processing parameters corresponding to each combined engraving coordinate (x1, y1), (x2, y2), ..., (xn, yn) can be obtained.
  • S105 According to a preset grayscale value adjustment strategy, adjust the grayscale values of the first to-be-adjusted pixel points and the grayscale values of the second to-be-adjusted pixel points in the grayscale images of the i-1 to j layers.
  • step S105 includes step S1051, which is specifically as follows:
  • S1051 setting the grayscale value of the first pixel to be adjusted and the grayscale value of the second pixel to be adjusted in the grayscale image corresponding to the integrated circuit sub-layout of the i-1 to j layers to the highest value.
  • the high-energy particle beam lithography equipment sets the grayscale value of the first pixel to be adjusted and the grayscale value of the second pixel to be adjusted in the grayscale image corresponding to the integrated circuit sub-layout of the i-1 to j layers to the maximum value, i.e., 255, so that when engraving the corresponding pattern in the grayscale image corresponding to the integrated circuit sub-layout of the i-1 to j layers, the pattern composed of the first pixel to be adjusted and the pattern composed of the second pixel to be adjusted will not be engraved.
  • step S105 includes step S1052, which is as follows:
  • S1052 Obtain a first grayscale value corresponding to the lowest high-energy particle beam processing parameter, and set the grayscale value of the first pixel to be adjusted and the grayscale value of the second pixel to be adjusted in the grayscale image corresponding to the integrated circuit sub-layout of the i-1 to j layers to the first grayscale value.
  • the high-energy particle beam lithography equipment first obtains a first grayscale value corresponding to the lowest high-energy particle beam processing parameter.
  • the high-energy particle beam processing parameters include the high-energy particle beam acceleration voltage and/or the high-energy particle beam action time.
  • the grayscale value corresponding to the high-energy particle beam acceleration voltage being 0 or the high-energy particle beam action time being 0 is the first grayscale value.
  • the first grayscale value will also be different and is not necessarily 255, and its specific value is not limited here.
  • the high-energy particle beam lithography equipment sets the grayscale values of the first pixel to be adjusted and the second pixel to be adjusted in the grayscale image corresponding to the integrated circuit sub-layout of the i-1 to j layers to the first grayscale value, so that when engraving the corresponding pattern in the grayscale image corresponding to the integrated circuit sub-layout of the i-1 to j layers, the pattern composed of the first pixel to be adjusted and the pattern composed of the second pixel to be adjusted will not be engraved.
  • the high-energy particle beam processing parameters include the high-energy particle beam acceleration voltage and/or the high-energy particle beam action time.
  • the high-energy particle beam lithography equipment obtains the high-energy particle beam processing parameters corresponding to each pixel in the grayscale image according to the correspondence between the preset high-energy particle beam processing parameters and the grayscale value, which are as follows:
  • the high-energy particle beam lithography device obtains the high-energy particle beam acceleration voltage corresponding to each pixel in the grayscale image according to the grayscale value of the pixel in the grayscale image.
  • the high-energy particle beam acceleration voltage of the high-energy particle beam lithography device is higher.
  • the high-energy particle beam acceleration voltage of the high-energy particle beam lithography device is lower. The higher the high-energy particle beam acceleration voltage, the higher the kinetic energy of the emitted high-energy particle beam, so that in the same amount of time, more material can be carved away to obtain deeper material grooves.
  • the high-energy particle beam lithography device obtains the high-energy particle beam action time corresponding to each pixel in the grayscale image according to the grayscale value of the pixel in the grayscale image.
  • the high-energy particle beam action time of the high-energy particle beam lithography device is longer.
  • the high-energy particle beam action time of the high-energy particle beam lithography device is shorter. The longer the high-energy particle beam action time, the more material can be engraved and deeper material grooves can be obtained when other control conditions remain unchanged.
  • the high-energy particle beam lithography device obtains the grayscale mean value of all pixels in the grayscale image.
  • the high-energy particle beam acceleration voltage of the high-energy particle beam lithography device is made higher.
  • the high-energy particle beam action time corresponding to each pixel in the grayscale image is obtained when the high-energy particle beam acceleration voltage remains unchanged.
  • the grayscale value of the pixel in the grayscale image is smaller, the high-energy particle beam action time of the high-energy particle beam lithography device is made longer.
  • the high-energy particle beam action time of the high-energy particle beam lithography device is made shorter.
  • S107 Making each corresponding material layer on the target substrate in sequence, and controlling the high-energy particle beam lithography equipment to emit a high-energy particle beam and act on the corresponding material layer on the target substrate according to the high-energy particle beam processing parameters corresponding to each pixel point in the grayscale image, and engraving the pattern corresponding to the grayscale image to the corresponding material layer on the target substrate to obtain the target semiconductor device; wherein, after engraving the j-th material layer, before setting the j+1-th material layer, the step of: controlling the high-energy particle beam lithography equipment to emit a high-energy particle beam and act on each of the combined engraving coordinates of the j-th material layer according to the combined high-energy particle beam processing parameters corresponding to each of the combined engraving coordinates, and combined engraving the j to i-1-th material layers at each of the combined engraving coordinates.
  • the grayscale values of the second pixel to be adjusted in the i-1 layer of material and the second pixel to be adjusted in the i-j layers are adjusted based on the preset pixel recognition strategy and grayscale value adjustment strategy in steps S103 to S105, when the high-energy particle beam lithography equipment emits a high-energy particle beam to act on the i-1 to j layers of material on the target substrate, only patterns other than the pattern composed of the second pixel to be adjusted in the i-1 layer of grayscale image will be engraved into the i-1 layer of material, and patterns other than the pattern composed of the first pixel to be adjusted in the i-j layer of grayscale image will be engraved into the corresponding i-j layers of material.
  • the high-energy particle beam lithography equipment controls the high-energy particle beam lithography equipment to emit a high-energy particle beam to act on each of the merged engraving coordinates of the jth material layer according to the merged high-energy particle beam processing parameters corresponding to each of the merged engraving coordinates, and merges and engraves the j to i-1 material layers at each of the merged engraving coordinates.
  • the above-mentioned merged engraving method can effectively reduce the time for processing semiconductor devices and improve processing efficiency.
  • the material layers are pre-processed material layers, and the high-energy particle beam lithography equipment sequentially places each corresponding material layer on the target substrate by controlling the mechanical equipment.
  • the material layer is a material layer deposited by controlling a high-energy particle beam lithography device.
  • the step of sequentially manufacturing each corresponding material layer on the target substrate includes steps S1071 to S1072 as follows:
  • S1071 Acquire the material gas corresponding to the material layer and the deposition area corresponding to the material layer on the target substrate.
  • the material gas may be one gas or multiple gases, which may be different according to the differences of the material layers.
  • each material layer includes multiple materials. For example, a layer of silicon oxide is first plated on the surface of single crystal silicon, and then a layer of tantalum is plated on the surface of the silicon oxide. Accordingly, multiple material gases are also required when preparing such material layers.
  • S1072 Control the high-energy particle beam lithography equipment to spray the material gas in the deposition area, so that the material gas is decomposed and deposited in the deposition area, thereby completing the production of the material layer.
  • the material gas is sprayed in the deposition area through the gas injection device in the high-energy particle beam lithography equipment, and the focused high-energy particle beam is emitted to decompose the material gas at the same time, so that the decomposed material gas is deposited in the deposition area to complete the production of the material layer.
  • the above method can complete the laying of material layers and the engraving of graphics by controlling a high-energy particle beam lithography device, thereby realizing the processing of semiconductor devices, which can not only reduce costs but also have a higher degree of automation.
  • the high-energy particle beam lithography equipment can also control the high-energy particle beam to polish the material layer according to a preset optimized thickness range and/or a preset optimized flatness range, so that the current thickness and/or current flatness of the material layer are respectively within the preset optimized thickness range and the preset optimized flatness range, thereby further improving the subsequent engraving effect and optimizing the processing of semiconductor devices.
  • the preset optimized thickness range is 1 nm to 500 nm
  • the preset optimized flatness range is 0.5 nm to 5 nm.
  • the high-energy particle beam lithography equipment Before controlling the high-energy particle beam lithography equipment to emit a high-energy particle beam and act on the corresponding material layer on the target substrate, the high-energy particle beam lithography equipment can control the electromagnetic lens to perform miniaturization of the high-energy particle beam according to a preset engraving size threshold, so that the pixel size of the high-energy particle beam engraving is smaller than the engraving size threshold.
  • the integrated circuit sub-layout is converted into several layers of grayscale images, and the high-energy particle beam processing parameters corresponding to each pixel are obtained according to the grayscale value of each pixel in the grayscale image. Then, each corresponding material layer is sequentially manufactured on the target substrate, and the high-energy particle beam lithography equipment is controlled to emit a high-energy particle beam to act on the corresponding material layer according to the high-energy particle beam processing parameters corresponding to each pixel in the grayscale image, and the pattern corresponding to the grayscale image is engraved on the corresponding material layer, and finally the target semiconductor device is obtained.
  • This method of processing semiconductor devices without manufacturing multiple mask plates can greatly save costs, improve engraving accuracy, and can flexibly modify the integrated circuit layout to improve processing efficiency.
  • a preset pixel point recognition strategy is used to identify the first pixel points to be adjusted that can be combined and engraved from the grayscale images of the i-th to j-th layers, and to identify the second pixel points to be adjusted that can be engraved together with the first pixel points to be adjusted from the grayscale images of the i-1-th layer, and then based on the preset grayscale value adjustment strategy, the grayscale values of the first pixel points to be adjusted and the second pixel points to be adjusted are adjusted, so that when engraving the i-1-th to j-th material layers, the pattern composed of the second pixel points to be adjusted and the pattern composed of the first pixel points to be engraved will not be engraved.
  • the pattern composed of the first pixel points to be adjusted and the pattern composed of the second pixel points to be engraved are combined and engraved together to the corresponding j-th to i-1-th material layers, thereby further improving the processing efficiency of semiconductor devices.
  • FIG. 7 is a schematic diagram of the structure of a semiconductor device quality improvement device provided by an embodiment of the present application.
  • the device can be implemented as all or part of a high-energy particle beam lithography device through software, hardware, or a combination of both.
  • the device 7 includes a first acquisition module 71, a layout conversion module 72, a pixel point recognition module 73, a second acquisition module 74, a gray value adjustment module 75, a third acquisition module 76, and a processing control module 77:
  • a first acquisition module 71 is used to acquire an integrated circuit layout corresponding to a target semiconductor device; wherein the integrated circuit layout includes a plurality of layers of integrated circuit sub-layouts, each layer of the integrated circuit sub-layout corresponds to a pattern of one or more material layers of the target semiconductor device;
  • a layout conversion module 72 used to convert the several layers of the integrated circuit sub-layouts into several layers of grayscale images in a preset format
  • a pixel recognition module 73 is used to obtain, based on the grayscale images of the plurality of layers and a preset pixel recognition strategy, a first pixel to be adjusted in the grayscale images of the i-th to j-th layers and a second pixel to be adjusted in the grayscale image of the i-1-th layer having the same coordinates as the first pixel to be adjusted;
  • the second acquisition module 74 is used to acquire the high-energy particle beam processing parameters corresponding to the first pixel to be adjusted and the high-energy particle beam processing parameters corresponding to the second pixel to be adjusted according to the corresponding relationship between the preset high-energy particle beam processing parameters and the grayscale value, and add the high-energy particle beam processing parameters corresponding to the first pixel to be adjusted and the high-energy particle beam processing parameters corresponding to the second adjustment pixel with the same coordinates to acquire the combined high-energy particle beam processing parameters corresponding to each combined engraving coordinate;
  • a grayscale value adjustment module 75 configured to adjust the grayscale values of the first to-be-adjusted pixel points and the second to-be-adjusted pixel points in the grayscale images of the i-1 to j layers according to a preset grayscale value adjustment strategy;
  • a third acquisition module 76 is used to acquire the high-energy particle beam processing parameter corresponding to each pixel in the grayscale image according to the corresponding relationship between the preset high-energy particle beam processing parameter and the grayscale value;
  • the processing control module 77 is used to sequentially manufacture each corresponding material layer on the target substrate, and control the high-energy particle beam lithography equipment to emit a high-energy particle beam and act on the corresponding material layer on the target substrate according to the high-energy particle beam processing parameters corresponding to each pixel point in the grayscale image, and engrave the pattern corresponding to the grayscale image to the corresponding material layer on the target substrate to obtain the target semiconductor device; wherein, after engraving the j-th material layer, before setting the j+1-th material layer, it also includes the step of: according to the combined high-energy particle beam processing parameters corresponding to each of the combined engraving coordinates, controlling the high-energy particle beam lithography equipment to emit a high-energy particle beam and act on each of the combined engraving coordinates of the j-th material layer, and combined engraving the j to i-1-th material layers at each of the combined engraving coordinates.
  • the semiconductor device quality improvement device provided in the above embodiment only uses the division of the above functional modules as an example when executing the semiconductor device quality improvement method.
  • the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.
  • the semiconductor device quality improvement device provided in the above embodiment and the semiconductor device quality improvement method belong to the same concept, and the implementation process thereof is detailed in the method embodiment, which will not be repeated here.
  • the high-energy particle beam lithography device 8 may include: a processor 80, a memory 81, and a computer program 82 stored in the memory 81 and executable on the processor 80, such as a semiconductor device processing control program; when the processor 80 executes the computer program 82, the steps in the above-mentioned method embodiments are implemented, such as steps S101 to S107 shown in Figure 1.
  • the processor 80 may include one or more processing cores.
  • the processor 80 uses various interfaces and lines to connect various parts in the high-energy particle beam lithography device 8, and executes various functions and processes data of the high-energy particle beam lithography device 8 by running or executing instructions, programs, code sets or instruction sets stored in the memory 81, and calling the data in the memory 81.
  • the processor 80 can be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA).
  • DSP digital signal processing
  • FPGA field-programmable gate array
  • PDA programmable logic array
  • the processor 80 can integrate one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), and a modem.
  • the CPU mainly processes the operating system, user interface, and application programs; the GPU is responsible for rendering and drawing the content to be displayed on the touch screen; and the modem is used to process wireless communication. It can be understood that the above-mentioned modem may not be integrated into the processor 80, but implemented by a single chip.
  • the memory 81 may include a random access memory (RAM) or a read-only memory (ROM).
  • the memory 81 includes a non-transitory computer-readable storage medium.
  • the memory 81 may be used to store instructions, programs, codes, code sets or instruction sets.
  • the memory 81 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch instructions, etc.), instructions for implementing the above-mentioned various method embodiments, etc.; the data storage area may store data involved in the above-mentioned various method embodiments, etc.
  • the memory 81 may also be optionally at least one storage device located away from the aforementioned processor 80.

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Abstract

一种半导体器件的质量改善方法、装置及高能粒子束光刻设备，该方法通过预设的像素点识别策略，从第i至j层灰度图片中识别出可以合并雕刻的第一待调整像素点以及从第i-1层灰度图片中识别出与第一待调整像素点坐标相同的可一同雕刻的第二待调整像素点，再基于预设的灰度值调整策略，调整第一待调整像素点和第二待调整像素点的灰度值，使得在雕刻第i-1层至j层材料层时不会雕刻第二待调整像素点组成的图案和第一待雕刻像素点组成的图案，最后在雕刻第j层材料层之后，再一同合并雕刻上述图案至相应的第j至i-1层材料层，最终得到目标半导体器件。相对于现有技术，该方法能够有效提高半导体器件的加工效率，降低加工成本。

Description

半导体器件的质量改善方法、装置及高能粒子束光刻设备 技术领域
本申请实施例涉及半导体加工技术领域，尤其涉及一种半导体器件的质量改善方法、装置及高能粒子束光刻设备。
背景技术
在传统的半导体加工技术领域中，往往都是基于集成电路掩膜版与光刻技术的结合，实现将集成电路版图转移至硅基材上，进而完成半导体器件的制造。
但是，随着对半导体器件的尺寸要求越来越高，支撑光刻技术的光源系统(如EUV光刻机)的制造和集成电路掩膜版的制作变得越发艰难，使用集成电路掩膜版也会使半导体器件的制造成本巨大，并且，若对集成电路版图进行修改或微调，则需要再重新制作掩膜版，致使加工效率低下。
本申请中的高能粒子束可以是离子束、电子束、激光束、X射线等，其中实验用到的是高能高能粒子束。高能粒子束拥有比普通光学系统更小的波长，可以提升版图转移的分辨率，适合于制作更小尺寸的器件。比如DUV光刻机因为波长的限制，只适用于制作特征尺寸大于7nm的器件；对于7nm以下的器件制作，必须要引入EUV。而高能粒子束拥有比EUV更小的波长。
发明内容
本申请实施例提供了一种半导体器件的质量改善方法、装置及高能粒子束光刻设备，可以在不制作集成电路掩膜版完成半导体器件的加工处理，提高加工效率，所述技术方案如下:
第一方面，本申请实施例提供了一种半导体器件的质量改善方法，包括：
获取目标半导体器件对应的集成电路版图；其中，所述集成电路版图包括若干层集成电路子版图，每一层集成电路子版图分别对应所述目标半导体器件一层或多层材料层的图案；
将若干层所述集成电路子版图分别转化为预设格式的若干层灰度图片；
基于若干层所述灰度图片和预设的像素点识别策略，获取第i至j层所述灰度图片中的第一待调整像素点，以及第i-1层所述灰度图片中与所述第一待调整像素点坐标相同的第二待调整像素点；
根据预设的高能粒子束加工参数与灰度值之间的对应关系，获取所述第一待调整像素点对应的高能粒子束加工参数和第二待调整像素点对应的高能粒子束加工参数，将坐标相同的所述第一待调整像素点对应的高能粒子束加工参数和所述第二调整像素点对应的高能粒子束 加工参数相加，获取各个合并雕刻坐标处对应的合并高能粒子束加工参数；
根据预设的灰度值调整策略，调整第i-1至j层所述灰度图片中的所述第一待调整像素点的灰度值和所述第二待调整像素点的灰度值；
根据预设的高能粒子束加工参数与灰度值之间的对应关系，获取所述灰度图片中各像素点对应的高能粒子束加工参数；
在目标基材上依次制作相应的每一层所述材料层，并分别根据所述灰度图片中各像素点对应的高能粒子束加工参数，控制高能粒子束光刻设备发射高能粒子束并作用于所述目标基材上相应的材料层，雕刻所述灰度图片对应的图案至所述目标基材上相应的材料层，得到所述目标半导体器件；其中，在雕刻完第j层所述材料层之后，设置第j+1层所述材料层之前还包括步骤：根据各个所述合并雕刻坐标处对应的合并高能粒子束加工参数，控制所述高能粒子束光刻设备发射高能粒子束作用于第j层所述材料层的各个所述合并雕刻坐标处，在各个所述合并雕刻坐标处合并雕刻第j至i-1层所述材料层。
第二方面，本申请实施例提供了一种半导体器件的质量改善装置，包括：
第一获取模块，用于获取目标半导体器件对应的集成电路版图；其中，所述集成电路版图包括若干层集成电路子版图，每一层集成电路子版图分别对应所述目标半导体器件一层或多层材料层的图案；
版图转化模块，用于将若干层所述集成电路子版图分别转化为预设格式的若干层灰度图片；
像素点识别模块，用于基于若干层所述灰度图片和预设的像素点识别策略，获取第i至j层所述灰度图片中的第一待调整像素点，以及第i-1层所述灰度图片中与所述第一待调整像素点坐标相同的第二待调整像素点；
第二获取模块，用于根据预设的高能粒子束加工参数与灰度值之间的对应关系，获取所述第一待调整像素点对应的高能粒子束加工参数和第二待调整像素点对应的高能粒子束加工参数，将坐标相同的所述第一待调整像素点对应的高能粒子束加工参数和所述第二调整像素点对应的高能粒子束加工参数相加，获取各个合并雕刻坐标处对应的合并高能粒子束加工参数；
灰度值调整模块，用于根据预设的灰度值调整策略，调整第i-1至j层所述灰度图片中的所述第一待调整像素点的灰度值和所述第二待调整像素点的灰度值；
第三获取模块，用于根据预设的高能粒子束加工参数与灰度值之间的对应关系，获取所述灰度图片中各像素点对应的高能粒子束加工参数；
加工控制模块，用于在目标基材上依次制作相应的每一层所述材料层，并分别根据所述 灰度图片中各像素点对应的高能粒子束加工参数，控制高能粒子束光刻设备发射高能粒子束并作用于所述目标基材上相应的材料层，雕刻所述灰度图片对应的图案至所述目标基材上相应的材料层，得到所述目标半导体器件；其中，在雕刻完第j层所述材料层之后，设置第j+1层所述材料层之前还包括步骤：根据各个所述合并雕刻坐标处对应的合并高能粒子束加工参数，控制所述高能粒子束光刻设备发射高能粒子束作用于第j层所述材料层的各个所述合并雕刻坐标处，在各个所述合并雕刻坐标处合并雕刻第j至i-1层所述材料层。
第三方面，本申请实施例提供了一种高能粒子束光刻设备，包括：处理器、存储器以及存储在所述存储器中并可在所述处理器上运行的计算机程序，所述处理器执行所述计算机程序时实现如第一方面所述的半导体器件的质量改善方法的步骤。
本申请实施例中，通过将集成电路子版图转化为若干层灰度图片，根据灰度图片中各像素点的灰度值，获取各像素点对应的高能粒子束加工参数，再在目标基材上依次制作相应的每一层材料层，分别根据灰度图片中各像素点对应的高能粒子束加工参数，控制高能粒子束光刻设备发射高能粒子束作用于相应的材料层，雕刻灰度图片对应的图案至相应的材料层，最终得到所述目标半导体器件，这种不需要制造多张掩膜版就可以加工半导体器件的方式，能够大幅节约成本，提高雕刻精度，而且可以灵活地修改集成电路版图，提高加工效率。并且，在本申请实施例中，还通过预设的像素点识别策略，从第i层至j层灰度图片中识别出可以合并雕刻第一待调整像素点以及从第i-1层灰度图片中识别出与第一待调整像素点坐标相同的可一同雕刻的第二待调整像素点，再基于预设的灰度值调整策略，调整第一待调整像素点和第二待调整像素点的灰度值，使得在雕刻第i-1层至j层材料层时不会雕刻第二待调整像素点组成的图案和第一待雕刻像素点组成的图案，最后在雕刻第j层材料层之后，设置第j+1层材料层之前，再一同合并雕刻第一待调整像素点组成的图案和第二待雕刻像素点组成的图案至相应的第j至i-1层材料层，从而更进一步地提高了半导体器件的加工效率。
为了更好地理解和实施，下面结合附图详细说明本申请的技术方案。
附图说明
图1为本申请一个实施例提供的半导体器件的质量改善方法的流程示意图；
图2为本申请一个实施例提供的半导体器件的质量改善方法中S103的流程示意图；
图3为本申请一个实施例提供的四个MOS管并联集成电路版图对应的灰度图片的示意图；
图4为本申请一个实施例提供的半导体器件的质量改善方法中S105的流程示意图；
图5为本申请另一个实施例提供的半导体器件的质量改善方法中S105的流程示意图；
图6为本申请一个实施例提供的半导体器件的质量改善方法中S107的流程示意图；
图7为本申请一个实施例提供的半导体器件的质量改善装置的结构示意图；
图8为本申请一个实施例提供的高能粒子束光刻设备的结构示意图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
在本申请使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。在本申请和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
应当理解，尽管在本申请可能采用术语第一、第二、第三等来描述各种信息，但这些信息不应限于这些术语。这些术语仅用来将同一类型的信息彼此区分开。例如，在不脱离本申请范围的情况下，第一信息也可以被称为第二信息，类似地，第二信息也可以被称为第一信息。取决于语境，如在此所使用的词语“如果”/“若”可以被解释成为“在……时”或“当……时”或“响应于确定”。
请参阅图1，为本申请一个实施例提供的半导体器件的质量改善方法的流程示意图，所述方法包括如下步骤：
S101：获取目标半导体器件对应的集成电路版图；其中，所述集成电路版图包括若干层集成电路子版图，每一层集成电路子版图分别对应所述目标半导体器件一层或多层材料层的图案。
在一个可选的实施例中，所述半导体器件的质量改善方法的执行主体可以为高能粒子束光刻设备，也可以为高能粒子束光刻设备中的组成部件，例如其内部的处理器或微处理器等；在另一个可选的实施例中，所述半导体器件的质量改善方法的执行主体可以为与高能粒子束光刻设备建立数据连接的外部设备，也可以为外部设备中的组成部件。
在本申请实施例中，所述半导体器件的质量改善方法的执行主体为高能粒子束光刻设备。
具体地，高能粒子束光刻设备获取目标半导体器件对应的集成电路版图。
其中，所述目标半导体器件可以为任意类型的半导体器件，对于其具体类型在此不进行限定。
所述集成电路版图是指将电路设计电路图或电路描述语言映射到物理描述层面，集成电路版图中包括集成电路的器件类型、器件尺寸、器件之间的相对位置以及各个器件之间的连接关系等相关物理信息。
所述集成电路版图中包括若干层集成电路子版图，每一层集成电路子版图分别对应目标半导体器件一层材料层的图案。
在本申请实施例中，所述材料层包括但不仅限于有源层、绝缘层、多晶硅栅极层和金属层等。
S102：将若干层所述集成电路子版图分别转化为预设格式的若干层灰度图片。
高能粒子束光刻设备将若干层所述集成电路子版图分别转化为预设格式的若干层灰度图片。
在一个可选的实施例中，所述预设格式为TIF格式，在其他可选的实施例中，所述预设格式可以为高能粒子束光刻设备可识别处理的其他图片格式。
所述灰度图片中像素点的灰度值为0至255，灰度值为0表示像素点亮度较低，人体主观视觉感受其为黑色，灰度值为255表示像素点亮度较高，人体主观视觉感受其为白色。
S103：基于若干层所述灰度图片和预设的像素点识别策略，获取第i至j层所述灰度图片中的第一待调整像素点，以及第i-1层所述灰度图片中与所述第一待调整像素点坐标相同的第二待调整像素点。
若第i至j层所述集成电路子版图中相同位置处均存在通孔，那么对应的第i至j层所述灰度图片中通孔位置处的灰度值均会比较低，因而高能粒子束光刻设备可以通过预设的像素点识别策略，获取第i至j所述灰度图片中通孔位置处对应的像素点，也即第一待调整像素点。
由于第i至j层所述集成电路子版图中相同位置处均存在通孔，因此可以将第i-1层所述集成电路子版图中通孔下方的图案与通孔一同合并雕刻，故，高能粒子束光刻设备还需获取第i-1层所述灰度图片中与所述第一待调整像素点坐标相同的第二待调整像素点。
在一个可选的实施例中，为对像素点进行准确地识别，请参阅图2，步骤S103包括步骤S1031～S1032，具体如下：
S1031：获取每一层所述集成电路子版图对应的灰度图片中的目标像素点以及所述目标像素点在所述灰度图片中的坐标；其中，所述目标像素点为灰度值低于预设阈值的像素点。
所述目标像素点为灰度值低于预设阈值的像素点。其中，所述预设阈值与预设的高能粒子束加工参数与灰度值之间的对应关系相关，可以根据实际情况进行设定，在此不进行限定。
请参阅图3，其为本申请一个实施例提供四个MOS管并联集成电路版图对应的灰度图片的示意图。图3中集成电路版图包括有源层、多晶硅栅极层、金属层和在有源层、多晶硅栅 极层上的绝缘层(图未示出)，在金属层、绝缘层以及多晶硅栅极层中就存在灰度值低于预设阈值的目标像素点。
S1032：当第i至j层所述灰度图片中均存在坐标相同的所述目标像素点时，得到第i至j层所述灰度图片中的第一待调整像素点，并获取第i-1层所述灰度图片中与第一待调整像素点坐标相同的第二待调整像素点。
若第i至j层所述灰度图片中均存在坐标相同的所述目标像素点，那么这些目标像素点即为第i至j层所述灰度图片中的第一待调整像素点，高能粒子束光刻设备获取第i至j层所述灰度图片中的第一待调整像素点以及第i-1层所述灰度图片中与第一待调整像素点坐标相同的第二待调整像素点。
S104：根据预设的高能粒子束加工参数与灰度值之间的对应关系，获取所述第一待调整像素点对应的高能粒子束加工参数和第二待调整像素点对应的高能粒子束加工参数，将坐标相同的所述第一待调整像素点对应的高能粒子束加工参数和所述第二调整像素点对应的高能粒子束加工参数相加，获取各个合并雕刻坐标处对应的合并高能粒子束加工参数。
在一个可选的实施例中，所述预设的高能粒子束加工参数与灰度值之间的对应关系可以预先设置并存储在所述高能粒子束光刻设备中。在另一个可选的实施例中，所述预设的高能粒子束加工参数与灰度值之间的对应关系可以预先设置并存储在云端或上位机中，在使用时再下载至所述高能粒子束光刻设备中。
根据半导体器件类型的不同或者材料层的材料差异，相应的高能粒子束加工参数与灰度值之间的对应关系也不同。在所述高能粒子束光刻设备、云端或上位机中，可以根据半导体器件的标识，查找相应的高能粒子束加工参数与灰度值之间的对应关系，也可以根据材料层的材料标识，查找相应的高能粒子束加工参数与灰度值之间的对应关系。
在一个可选的实施例中，第三方半导体器件设计厂家可以将设计的半导体器件标识或材料标识上传至所述云端中，并配置相应的高能粒子束加工参数与灰度值之间的对应关系，从而能够使得高能粒子束光刻设备能够控制高能粒子束光刻设备完成更多类型的半导体器件的加工，满足更多的第三方客户需求。
高能粒子束光刻设备根据预设的高能粒子束加工参数与灰度值之间的对应关系，获取所述第一待调整像素点对应的高能粒子束加工参数和第二待调整像素点对应的高能粒子束加工参数。
之后，高能粒子束光刻设备将坐标相同的所述第一待调整像素点对应的高能粒子束加工参数和所述第二调整像素点对应的高能粒子束加工参数相加，获取各个合并雕刻坐标处对应的合并高能粒子束加工参数。
例如：第i至j层中第一待调整像素点的坐标为(x1，y1)、(x2，y2)，…，(xn，yn)，那么就将第i至j层中坐标为(x1，y1)的第一待调整像素点对应的高能粒子束加工参数与第i-1层中坐标为(x1，y1)的第二待调整像素点对应的高能粒子束加工参数相加，这里(x1，y1)即为一个合并雕刻坐标处，相加得到的高能粒子束加工参数即为合并雕刻坐标处(x1，y1)对应的合并高能粒子束加工参数。按照上述相同的方式，可以获取各个合并雕刻坐标处(x1，y1)、(x2，y2)，…，(xn，yn)对应的高能粒子束加工参数。
S105：根据预设的灰度值调整策略，调整第i-1至j层所述灰度图片中的所述第一待调整像素点的灰度值和所述第二待调整像素点的灰度值。
在一个可选的实施例中，请参阅图4，步骤S105包括步骤S1051，具体如下：
S1051：将第i-1至j层所述集成电路子版图对应的灰度图片中所述第一待调整像素点的灰度值和所述第二待调整像素点的灰度值均设置为最高值。
高能粒子束光刻设备将第i-1至j层所述集成电路子版图对应的灰度图片中所述第一待调整像素点的灰度值和第二待调整像素点的灰度值均设置为最高值，即255，从而使得在雕刻所述第i-1至j层所述集成电路子版图对应的灰度图片中相应图案时，不会雕刻到所述第一待调整像素点组成的图案和第二待调整像素点组成的图案。
在另一个可选的实施例中，请参阅图5，步骤S105包括步骤S1052，具体如下：
S1052：获取最低的高能粒子束加工参数对应的第一灰度值，将第i-1至j层所述集成电路子版图对应的灰度图片中所述第一待调整像素点的灰度值和所述第二待调整像素点的灰度值均设置为第一灰度值。
高能粒子束光刻设备先获取最低的高能粒子束加工参数对应的第一灰度值。
其中，高能粒子束加工参数包括高能粒子束加速电压和/或高能粒子束作用时间，在本申请实施例中，高能粒子束加速电压为0或高能粒子束作用时间为0时对应的灰度值为第一灰度值。
由于高能粒子束加工参数与灰度值之间对应关系的不同，第一灰度值也会不同，并不一定是255，对于其具体数值在此不进行限定。
之后，高能粒子束光刻设备将所述第i-1至j层所述集成电路子版图对应的灰度图片中，所述第一待调整像素点和第二待调整像素点的灰度值均设置为所述第一灰度值，从而也能够使得在雕刻所述第i至j层所述集成电路子版图对应的灰度图片中的相应图案时，不会雕刻到所述第一待调整像素点组成的图案和第二待调整像素点组成的图案。
S106：根据预设的高能粒子束加工参数与灰度值之间的对应关系，获取所述灰度图片中各像素点对应的高能粒子束加工参数。
在本申请实施例中，所述高能粒子束加工参数包括高能粒子束加速电压和/或高能粒子束作用时间，为更精准地对半导体器件进行加工，高能粒子束光刻设备根据预设的高能粒子束加工参数与灰度值之间的对应关系，获取所述灰度图片中各像素点对应的高能粒子束加工参数，具体如下：
高能粒子束光刻设备根据所述灰度图片中像素点的灰度值，获取所述灰度图片中各像素点对应的高能粒子束加速电压，当所述灰度图片中像素点的灰度值越小时，使所述高能粒子束光刻设备的高能粒子束加速电压越高，当所述灰度图片中像素点的灰度值越大时，使所述高能粒子束光刻设备的高能粒子束加速电压越低。高能粒子束加速电压越高，发射出的高能粒子束的动能越高，因而在相同的时间内，能够雕刻掉更多的材料，得到更深的材料沟壑。
或者，高能粒子束光刻设备根据所述灰度图片中像素点的灰度值，获取所述灰度图片中各像素点对应的高能粒子束作用时间，当所述灰度图片中像素点的灰度值越小时，使所述高能粒子束光刻设备的高能粒子束作用时间越长，当所述灰度图片中像素点的灰度值越大时，使所述高能粒子束光刻设备的高能粒子束作用时间越短。高能粒子束作用时间越长，在其他控制条件不变的情况下，也能够雕刻掉更多的材料，得到更深的材料沟壑。
或者，高能粒子束光刻设备获取所述灰度图片中所有像素点的灰度均值，当所述灰度均值越小时，使所述高能粒子束光刻设备的所述高能粒子束加速电压越高，并根据所述灰度图片中像素点的灰度值，获取在所述高能粒子束加速电压不变的情况下所述灰度图片中各像素点对应的高能粒子束作用时间，当所述灰度图片中像素点的灰度值越小时，使所述高能粒子束光刻设备的高能粒子束作用时间越长，当所诉灰度图片中像素点的灰度值越大时，使所述高能粒子束光刻设备的高能粒子束作用时间越短。通过高能粒子束加速电压与高能粒子束作用时间的配合，能够加快半导体器件的制作过程，提高制作效率。
S107：在目标基材上依次制作相应的每一层所述材料层，并分别根据所述灰度图片中各像素点对应的高能粒子束加工参数，控制高能粒子束光刻设备发射高能粒子束并作用于所述目标基材上相应的材料层，雕刻所述灰度图片对应的图案至所述目标基材上相应的材料层，得到所述目标半导体器件；其中，在雕刻完第j层所述材料层之后，设置第j+1层所述材料层之前还包括步骤：根据各个所述合并雕刻坐标处对应的合并高能粒子束加工参数，控制所述高能粒子束光刻设备发射高能粒子束作用于第j层所述材料层的各个所述合并雕刻坐标处，在各个所述合并雕刻坐标处合并雕刻第j至i-1层所述材料层。
由于在步骤S103至S105中基于预设的像素点识别策略和灰度值调整策略对i-1层材料中的第二待调整像素点和第i至j层的第二待调整像素点的灰度值均进行了调整，因此，在高能粒子束光刻设备发射高能粒子束作用于目标基材上的第i-1至j层材料层时，只会雕刻第i-1 层灰度图片中除第二待调整像素点组成的图案以外的其他图案至第i-1层材料层中，雕刻第i至j层灰度图片中除第一待调整像素点组成的图案以外的其他图案至相应的第i至j层材料层。
进而，在高能粒子束光刻设备雕刻完第j层材料层后，设置第j+1层材料层之前，需要对未雕刻的图案进行合并雕刻，具体地：高能粒子束光刻设备根据各个所述合并雕刻坐标处对应的合并高能粒子束加工参数，控制所述高能粒子束光刻设备发射高能粒子束作用于第j层所述材料层的各个所述合并雕刻坐标处，在各个所述合并雕刻坐标处合并雕刻第j至i-1层所述材料层，通过上述合并雕刻的方式能够有效降低加工半导体器件的时间，提高加工效率。
在一个可选的实施例中，上述材料层为预先加工好的材料层，高能粒子束光刻设备通过控制机械设备在目标基材上依次放置相应的每一层所述材料层。
在另一个可选的实施例中，所述材料层为通过控制高能粒子束光刻设备沉积的材料层，具体地，请参阅图6，所述在目标基材上依次制作相应的每一层所述材料层包括步骤S1071～S1072，如下：
S1071：获取所述材料层对应的材料气体和所述材料层在所述目标基材上对应的沉积区域。
所述材料气体可以为一种气体或多种气体，根据材料层的差异性而不同。
在某些实施例中，为了使聚焦高能粒子束能够在材料层上雕刻出更好地图形效果，每一层材料层中包括多种材料，例如，在单晶硅的表面先镀上一层氧化硅，再在氧化硅的表面镀一层钽，那么相应的在制备这样的材料层时也需要多种材料气体。
S1072：控制所述高能粒子束光刻设备在所述沉积区域喷射所述材料气体，使所述材料气体分解后沉积在所述沉积区域，完成所述材料层的制作。
由于聚焦高能粒子束能分解金属蒸汽或气相绝缘材料等，因而通过所述高能粒子束光刻设备中的气体喷射装置在所述沉积区域喷射所述材料气体，同时发射聚焦高能粒子束分解材料气体，使分解后的材料气体沉积在沉积区域，完成材料层的制作。
上述方式通过控制一台高能粒子束光刻设备，就能完成材料层的铺设和图形的雕刻，实现半导体器件的加工，不仅能够减低成本，而且自动化程度更高。
在一个可选的实施例中，每在目标基材上设置完一层所述材料层后，高能粒子束光刻设备还可以根据预设的优化厚度范围和/或预设的优化平整度范围，控制所述高能粒子束对所述材料层进行打磨，使所述材料层的当前厚度和/或当前平整度分别在所述预设的优化厚度范围和预设的优化平整度范围之内，从而进一步提高后续的雕刻效果，优化半导体器件的加工。
可选的，所述预设的优化厚度范围为1nm至500nm，所述预设的优化平整度范围为0.5nm～5nm。
在另一个可选的实施例中，由于不同器件的性质和用途的不同，因而对于雕刻的加工精 度要求不同，在控制高能粒子束光刻设备发射高能粒子束并作用于目标基材上相应的材料层之前，高能粒子束光刻设备可以根据预设的雕刻尺寸阈值，控制电磁透镜进行所述高能粒子束微缩，使所述高能粒子束雕刻像素点尺寸小于所述雕刻尺寸阈值。
本申请实施例中，通过将集成电路子版图转化为若干层灰度图片，根据灰度图片中各像素点的灰度值，获取各像素点对应的高能粒子束加工参数，再在目标基材上依次制作相应的每一层材料层，分别根据灰度图片中各像素点对应的高能粒子束加工参数，控制高能粒子束光刻设备发射高能粒子束作用于相应的材料层，雕刻灰度图片对应的图案至相应的材料层，最终得到所述目标半导体器件，这种不需要制造多张掩膜版就可以加工半导体器件的方式，能够大幅节约成本，提高雕刻精度，而且可以灵活地修改集成电路版图，提高加工效率。并且，在本申请实施例中，还通过预设的像素点识别策略，从第i层至j层灰度图片中识别出可以合并雕刻第一待调整像素点以及从第i-1层灰度图片中识别出与第一待调整像素点坐标相同的可一同雕刻的第二待调整像素点，再基于预设的灰度值调整策略，调整第一待调整像素点和第二待调整像素点的灰度值，使得在雕刻第i-1层至j层材料层时不会雕刻第二待调整像素点组成的图案和第一待雕刻像素点组成的图案，最后在雕刻第j层材料层之后，设置第j+1层材料层之前，再一同合并雕刻第一待调整像素点组成的图案和第二待雕刻像素点组成的图案至相应的第j至i-1层材料层，从而更进一步地提高了半导体器件的加工效率。
请参阅图7，图7为本申请一个实施例提供的半导体器件的质量改善装置的结构示意图。该装置可以通过软件、硬件或两者的结合实现成为高能粒子束光刻设备的全部或一部分。该装置7包括第一获取模块71、版图转化模块72、像素点识别模块73、第二获取模块74、灰度值调整模块75、第三获取模块76和加工控制模块77：
第一获取模块71，用于获取目标半导体器件对应的集成电路版图；其中，所述集成电路版图包括若干层集成电路子版图，每一层集成电路子版图分别对应所述目标半导体器件一层或多层材料层的图案；
版图转化模块72，用于将若干层所述集成电路子版图分别转化为预设格式的若干层灰度图片；
像素点识别模块73，用于基于若干层所述灰度图片和预设的像素点识别策略，获取第i至j层所述灰度图片中的第一待调整像素点，以及第i-1层所述灰度图片中与所述第一待调整像素点坐标相同的第二待调整像素点；
第二获取模块74，用于根据预设的高能粒子束加工参数与灰度值之间的对应关系，获取所述第一待调整像素点对应的高能粒子束加工参数和第二待调整像素点对应的高能粒子束加工参数，将坐标相同的所述第一待调整像素点对应的高能粒子束加工参数和所述第二调整像 素点对应的高能粒子束加工参数相加，获取各个合并雕刻坐标处对应的合并高能粒子束加工参数；
灰度值调整模块75，用于根据预设的灰度值调整策略，调整第i-1至j层所述灰度图片中的所述第一待调整像素点的灰度值和所述第二待调整像素点的灰度值；
第三获取模块76，用于根据预设的高能粒子束加工参数与灰度值之间的对应关系，获取所述灰度图片中各像素点对应的高能粒子束加工参数；
加工控制模块77，用于在目标基材上依次制作相应的每一层所述材料层，并分别根据所述灰度图片中各像素点对应的高能粒子束加工参数，控制高能粒子束光刻设备发射高能粒子束并作用于所述目标基材上相应的材料层，雕刻所述灰度图片对应的图案至所述目标基材上相应的材料层，得到所述目标半导体器件；其中，在雕刻完第j层所述材料层之后，设置第j+1层所述材料层之前还包括步骤：根据各个所述合并雕刻坐标处对应的合并高能粒子束加工参数，控制所述高能粒子束光刻设备发射高能粒子束作用于第j层所述材料层的各个所述合并雕刻坐标处，在各个所述合并雕刻坐标处合并雕刻第j至i-1层所述材料层。
需要说明的是，上述实施例提供的半导体器件的质量改善装置在执行半导体器件的质量改善方法时，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将设备的内部结构划分为不同的功能模块，以完成以上描述的全部或者部分功能。另外，上述实施例提供的半导体器件的质量改善装置与半导体器件的质量改善方法属于同一构思，其体现实现过程详见方法实施例，这里不再赘述。
请参见图8，其为本申请一个实施例提供的高能粒子束光刻设备的结构示意图。如图8示，所述高能粒子束光刻设备8可以包括：处理器80、存储器81以及存储在所述存储器81并可以在所述处理器80上运行的计算机程序82，例如：半导体器件的加工控制程序；所述处理器80执行所述计算机程序82时实现上述各方法实施例中的步骤，例如图1所示的步骤S101至S107。
其中，所述处理器80可以包括一个或多个处理核心。处理器80利用各种接口和线路连接所述高能粒子束光刻设备8内的各个部分，通过运行或执行存储在存储器81内的指令、程序、代码集或指令集，以及调用存储器81内的数据，执行高能粒子束光刻设备8的各种功能和处理数据，可选的，处理器80可以采用数字信号处理(Digital Signal Processing,DSP)、现场可编程门阵列(Field-Programmable Gate Array，FPGA)、可编程逻辑阵列(Programble Logic Array，PLA)中的至少一个硬件形式来实现。处理器80可集成中央处理器(Central Processing Unit，CPU)、图像处理器(Graphics Processing Unit，GPU)和调制解调器等中的一种或几种的组合。其中，CPU主要处理操作系统、用户界面和应用程序等；GPU用于负责触摸显示屏 所需要显示的内容的渲染和绘制；调制解调器用于处理无线通信。可以理解的是，上述调制解调器也可以不集成到处理器80中，单独通过一块芯片进行实现。
其中，存储器81可以包括随机存储器(Random Access Memory，RAM)，也可以包括只读存储器(Read-Only Memory)。可选的，该存储器81包括非瞬时性计算机可读介质(non-transitory computer-readable storage medium)。存储器81可用于存储指令、程序、代码、代码集或指令集。存储器81可包括存储程序区和存储数据区，其中，存储程序区可存储用于实现操作系统的指令、用于至少一个功能的指令(比如触控指令等)、用于实现上述各个方法实施例的指令等；存储数据区可存储上面各个方法实施例中涉及到的数据等。存储器81可选的还可以是至少一个位于远离前述处理器80的存储装置。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述或记载的部分，可以参见其它实施例的相关描述。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
本发明并不局限于上述实施方式，如果对本发明的各种改动或变形不脱离本发明的精神和范围，倘若这些改动和变形属于本发明的权利要求和等同技术范围之内，则本发明也意图包含这些改动和变形。

Claims (10)

  1. 一种半导体器件的质量改善方法，其特征在于，包括步骤：
    获取目标半导体器件对应的集成电路版图；其中，所述集成电路版图包括若干层集成电路子版图，每一层集成电路子版图分别对应所述目标半导体器件一层或多层材料层的图案；
    将若干层所述集成电路子版图分别转化为预设格式的若干层灰度图片；
    基于若干层所述灰度图片和预设的像素点识别策略，获取第i至j层所述灰度图片中的第一待调整像素点，以及第i-1层所述灰度图片中与所述第一待调整像素点坐标相同的第二待调整像素点；
    根据预设的高能粒子束加工参数与灰度值之间的对应关系，获取所述第一待调整像素点对应的高能粒子束加工参数和第二待调整像素点对应的高能粒子束加工参数，将坐标相同的所述第一待调整像素点对应的高能粒子束加工参数和所述第二调整像素点对应的高能粒子束加工参数相加，获取各个合并雕刻坐标处对应的合并高能粒子束加工参数；
    根据预设的灰度值调整策略，调整第i-1至j层所述灰度图片中的所述第一待调整像素点的灰度值和所述第二待调整像素点的灰度值；
    根据预设的高能粒子束加工参数与灰度值之间的对应关系，获取所述灰度图片中各像素点对应的高能粒子束加工参数；
    在目标基材上依次制作相应的每一层所述材料层，并分别根据所述灰度图片中各像素点对应的高能粒子束加工参数，控制高能粒子束光刻设备发射高能粒子束并作用于所述目标基材上相应的材料层，雕刻所述灰度图片对应的图案至所述目标基材上相应的材料层，得到所述目标半导体器件；其中，在雕刻完第j层所述材料层之后，设置第j+1层所述材料层之前还包括步骤：根据各个所述合并雕刻坐标处对应的合并高能粒子束加工参数，控制所述高能粒子束光刻设备发射高能粒子束作用于第j层所述材料层的各个所述合并雕刻坐标处，在各个所述合并雕刻坐标处合并雕刻第j至i-1层所述材料层。
  2. 根据权利要求1所述的半导体器件的质量改善方法，其特征在于，所述基于若干层所述灰度图片和预设的像素点识别策略，获取第i至j层所述灰度图片中的第一待调整像素点，以及第i-1层所述灰度图片中与所述第一待调整像素点坐标相同的第二待调整像素点，包括步骤：
    获取每一层所述集成电路子版图对应的灰度图片中的目标像素点以及所述目标像素点在所述灰度图片中的坐标；其中，所述目标像素点为灰度值低于预设阈值的像素点；
    当第i至j层所述灰度图片中均存在坐标相同的所述目标像素点时，得到第i至j层所述 灰度图片中的第一待调整像素点，并获取第i-1层所述灰度图片中与第一待调整像素点坐标相同的第二待调整像素点。
  3. 根据权利要求1所述的半导体器件的质量改善方法，其特征在于，所述根据预设的灰度值调整策略，调整第i-1至j层所述灰度图片中的所述第一待调整像素点的灰度值和所述第二待调整像素点的灰度值，包括步骤：
    将第i-1至j层所述集成电路子版图对应的灰度图片中所述第一待调整像素点的灰度值和所述第二待调整像素点的灰度值均设置为最高值；
    或者，
    获取最低的高能粒子束加工参数对应的第一灰度值，将第i-1至j层所述集成电路子版图对应的灰度图片中所述第一待调整像素点的灰度值和所述第二待调整像素点的灰度值均设置为第一灰度值。
  4. 根据权利要求1至3任一项所述的半导体器件的质量改善方法，其特征在于，
    所述高能粒子束加工参数包括高能粒子束加速电压和/或高能粒子束作用时间，
    根据预设的高能粒子束加工参数与灰度值之间的对应关系，获取所述灰度图片中各像素点对应的高能粒子束加工参数，包括步骤：
    根据所述灰度图片中像素点的灰度值，获取所述灰度图片中各像素点对应的高能粒子束加速电压，当所述灰度图片中像素点的灰度值越小时，使所述高能粒子束光刻设备的高能粒子束加速电压越高，当所述灰度图片中像素点的灰度值越大时，使所述高能粒子束光刻设备的高能粒子束加速电压越低；
    或，
    根据所述灰度图片中像素点的灰度值，获取所述灰度图片中各像素点对应的高能粒子束作用时间，当所述灰度图片中像素点的灰度值越小时，使所述高能粒子束光刻设备的高能粒子束作用时间越长，当所述灰度图片中像素点的灰度值越大时，使所述高能粒子束光刻设备的高能粒子束作用时间越短；
    或，
    获取所述灰度图片中所有像素点的灰度均值，当所述灰度均值越小时，使所述高能粒子束光刻设备的所述高能粒子束加速电压越高，并根据所述灰度图片中像素点的灰度值，获取在所述高能粒子束加速电压不变的情况下所述灰度图片中各像素点对应的高能粒子束作用时间，当所述灰度图片中像素点的灰度值越小时，使所述高能粒子束光刻设备的高能粒子束作用时间越长，当所诉灰度图片中像素点的灰度值越大时，使所述高能粒子束光刻设备的高能粒子束作用时间越短。
  5. 根据权利要求1所述的半导体器件的质量改善方法，其特征在于，所述在目标基材上依次制作相应的每一层所述材料层，包括步骤：
    获取所述材料层对应的材料气体和所述材料层在所述目标基材上对应的沉积区域；
    控制所述高能粒子束光刻设备在所述沉积区域喷射所述材料气体，使所述材料气体分解后沉积在所述沉积区域，完成所述材料层的制作。
  6. 根据权利要求1所述的半导体器件的质量改善方法，其特征在于，所述在目标基材上依次制作相应的每一层所述材料层，包括步骤：
    根据预设的优化厚度范围和/或预设的优化平整度范围，控制所述高能粒子束对所述材料层进行打磨，使所述材料层的当前厚度和/或当前平整度分别在所述预设的优化厚度范围和预设的优化平整度范围之内。
  7. 根据权利要求6所述的半导体器件的质量改善方法，其特征在于：所述预设的优化厚度范围为1nm至500nm之间，所述预设的优化平整度范围为0.5nm～5nm。
  8. 根据权利要求1所述的半导体器件的质量改善方法，其特征在于，所述控制高能粒子束光刻设备发射高能粒子束并作用于所述目标基材上相应的材料层之前，包括步骤：
    根据预设的雕刻尺寸阈值，控制电磁透镜进行所述高能粒子束微缩，使所述高能粒子束雕刻像素点尺寸小于所述雕刻尺寸阈值。
  9. 一种半导体器件的质量改善装置，其特征在于，包括：
    第一获取模块，用于获取目标半导体器件对应的集成电路版图；其中，所述集成电路版图包括若干层集成电路子版图，每一层集成电路子版图分别对应所述目标半导体器件一层或多层材料层的图案；
    版图转化模块，用于将若干层所述集成电路子版图分别转化为预设格式的若干层灰度图片；
    像素点识别模块，用于基于若干层所述灰度图片和预设的像素点识别策略，获取第i至j层所述灰度图片中的第一待调整像素点，以及第i-1层所述灰度图片中与所述第一待调整像素点坐标相同的第二待调整像素点；
    第二获取模块，用于根据预设的高能粒子束加工参数与灰度值之间的对应关系，获取所述第一待调整像素点对应的高能粒子束加工参数和第二待调整像素点对应的高能粒子束加工参数，将坐标相同的所述第一待调整像素点对应的高能粒子束加工参数和所述第二调整像素点对应的高能粒子束加工参数相加，获取各个合并雕刻坐标处对应的合并高能粒子束加工参数；
    灰度值调整模块，用于根据预设的灰度值调整策略，调整第i-1至j层所述灰度图片中的 所述第一待调整像素点的灰度值和所述第二待调整像素点的灰度值；
    第三获取模块，用于根据预设的高能粒子束加工参数与灰度值之间的对应关系，获取所述灰度图片中各像素点对应的高能粒子束加工参数；
    加工控制模块，用于在目标基材上依次制作相应的每一层所述材料层，并分别根据所述灰度图片中各像素点对应的高能粒子束加工参数，控制高能粒子束光刻设备发射高能粒子束并作用于所述目标基材上相应的材料层，雕刻所述灰度图片对应的图案至所述目标基材上相应的材料层，得到所述目标半导体器件；其中，在雕刻完第j层所述材料层之后，设置第j+1层所述材料层之前还包括步骤：根据各个所述合并雕刻坐标处对应的合并高能粒子束加工参数，控制所述高能粒子束光刻设备发射高能粒子束作用于第j层所述材料层的各个所述合并雕刻坐标处，在各个所述合并雕刻坐标处合并雕刻第j至i-1层所述材料层。
  10. 一种高能粒子束光刻设备，其特征在于，包括：处理器、存储器以及存储在所述存储器中并可在所述处理器上运行的计算机程序，其特征在于，所述处理器执行所述计算机程序时实现如权利要求1至8任一项所述方法的步骤。
PCT/CN2022/128194 2022-10-28 2022-10-28 半导体器件的质量改善方法、装置及高能粒子束光刻设备 WO2024087153A1 (zh)

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