WO2024077416A1 - 半导体器件的加工控制方法及高能粒子束光刻设备 - Google Patents

半导体器件的加工控制方法及高能粒子束光刻设备 Download PDF

Info

Publication number
WO2024077416A1
WO2024077416A1 PCT/CN2022/124110 CN2022124110W WO2024077416A1 WO 2024077416 A1 WO2024077416 A1 WO 2024077416A1 CN 2022124110 W CN2022124110 W CN 2022124110W WO 2024077416 A1 WO2024077416 A1 WO 2024077416A1
Authority
WO
WIPO (PCT)
Prior art keywords
particle beam
energy particle
grayscale
integrated circuit
pixel
Prior art date
Application number
PCT/CN2022/124110
Other languages
English (en)
French (fr)
Inventor
张启华
简维廷
洪流
袁元
张勇为
蒋军浩
张洁
张洋
Original Assignee
袁元
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 袁元 filed Critical 袁元
Priority to PCT/CN2022/124110 priority Critical patent/WO2024077416A1/zh
Publication of WO2024077416A1 publication Critical patent/WO2024077416A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
    • H01J37/317—Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers

Definitions

  • the embodiments of the present application relate to the field of semiconductor processing technology, and in particular to a processing control method for a semiconductor device and a high-energy particle beam lithography device.
  • the high-energy particle beam in this application can be an ion beam, electron beam, laser beam, X-ray, etc., among which the experiment uses a high-energy focused ion beam.
  • High-energy particle beams have a smaller wavelength than ordinary optical systems, which can improve the resolution of layout transfer and are suitable for making smaller devices. For example, due to wavelength limitations, DUV lithography machines are only suitable for making devices with feature sizes greater than 7nm; for the production of devices below 7nm, EUV must be introduced. High-energy particle beams have a smaller wavelength than EUV.
  • the embodiment of the present application provides a method for controlling the processing of a semiconductor device and a high-energy particle beam lithography device, which can complete the processing of the semiconductor device without making an integrated circuit mask, thereby improving the processing efficiency.
  • the technical solution is as follows:
  • an embodiment of the present application provides a method for controlling a process of a semiconductor device, comprising:
  • the integrated circuit layout includes several layers of integrated circuit sub-layouts, and each layer of the integrated circuit sub-layout corresponds to a pattern of one or more material layers of the target semiconductor device;
  • the high-energy particle beam processing parameters corresponding to each pixel in the grayscale image are obtained;
  • Each corresponding material layer is manufactured on the target substrate in sequence, and according to the high-energy particle beam processing parameters corresponding to each pixel point in the grayscale image, the high-energy particle beam lithography equipment is controlled to emit a high-energy particle beam and act on the corresponding material layer on the target substrate, and the pattern corresponding to the integrated circuit sub-layout is engraved on the corresponding material layer on the target substrate to obtain the target semiconductor device.
  • the high-energy particle beam processing parameters include high-energy particle beam acceleration voltage and/or high-energy particle beam action time.
  • the high-energy particle beam processing parameters corresponding to each pixel point in the grayscale image are obtained, including the steps of:
  • the high-energy particle beam acceleration voltage corresponding to each pixel point in the grayscale image is obtained, when the grayscale value of the pixel point in the grayscale image is smaller, the high-energy particle beam acceleration voltage of the high-energy particle beam lithography device is higher, and when the grayscale value of the pixel point in the grayscale image is larger, the high-energy particle beam acceleration voltage of the high-energy particle beam lithography device is lower;
  • the high-energy particle beam action time corresponding to each pixel point in the grayscale image is obtained, when the grayscale value of the pixel point in the grayscale image is smaller, the high-energy particle beam action time of the high-energy particle beam lithography device is longer, and when the grayscale value of the pixel point in the grayscale image is larger, the high-energy particle beam action time of the high-energy particle beam lithography device is shorter;
  • the grayscale mean of all pixels in the grayscale image is obtained.
  • the grayscale mean is smaller, the high-energy particle beam acceleration voltage of the high-energy particle beam lithography device is higher.
  • the high-energy particle beam action time corresponding to each pixel in the grayscale image is obtained when the high-energy particle beam acceleration voltage remains unchanged.
  • the grayscale value of the pixel in the grayscale image is smaller, the high-energy particle beam action time of the high-energy particle beam lithography device is longer.
  • the grayscale value of the pixel in the grayscale image is larger, the high-energy particle beam action time of the high-energy particle beam lithography device is shorter.
  • the steps include:
  • target pixel points in the grayscale image corresponding to each layer of the integrated circuit sub-layout and the coordinates of the target pixel points in the grayscale image; wherein the target pixel points are pixel points whose grayscale values are lower than a preset threshold;
  • the pixel points to be adjusted in the grayscale images corresponding to the integrated circuit sub-layouts of the i-th to j-th layers are obtained;
  • the grayscale values of the pixels to be adjusted in the grayscale images corresponding to the integrated circuit sub-layouts of the i-th to j-th layers are reset according to a preset adjustment strategy.
  • the step of resetting the grayscale values of pixels to be adjusted in the grayscale images corresponding to the integrated circuit sub-layouts of the i-th to j-th layers according to a preset adjustment strategy comprises the following steps:
  • the grayscale value of the pixel to be adjusted in the grayscale image corresponding to the integrated circuit sub-layout of the i-th to j-th layers is set to the first grayscale value.
  • the step of sequentially manufacturing each corresponding material layer on the target substrate, and controlling a high-energy particle beam lithography device to emit a high-energy particle beam and act on the corresponding material layer on the target substrate according to the high-energy particle beam processing parameters corresponding to each pixel point in the grayscale image, and engraving a pattern corresponding to the integrated circuit sub-pattern to the corresponding material layer on the target substrate to obtain the target semiconductor device comprises the following steps:
  • the high-energy particle beam lithography equipment is controlled to emit a high-energy particle beam to act on the coordinates of the pixel to be adjusted in the jth material layer, and penetrate the i-jth to j-th material layers at the coordinates of the pixel to be adjusted.
  • the step of resetting the grayscale values of pixels to be adjusted in the grayscale images corresponding to the integrated circuit sub-layouts of the i-th to j-th layers according to a preset adjustment strategy comprises the following steps:
  • the grayscale value of the pixel to be adjusted in the grayscale image corresponding to the integrated circuit sub-layout of the i-th to j-1-th layer is set to the highest value, or the first grayscale value corresponding to the lowest high-energy particle beam processing parameter is obtained, and the grayscale value of the pixel to be adjusted in the grayscale image corresponding to the integrated circuit sub-layout of the i-th to j-1-th layer is set to the first grayscale value;
  • the grayscale value of the pixel to be adjusted in the grayscale image corresponding to the integrated circuit sub-layout of the j-th layer is set to the second grayscale value.
  • the step of sequentially manufacturing each corresponding material layer on the target substrate, and controlling a high-energy particle beam lithography device to emit a high-energy particle beam and act on the corresponding material layer on the target substrate according to the high-energy particle beam processing parameters corresponding to each pixel point in the grayscale image, and engraving a pattern corresponding to the integrated circuit sub-pattern to the corresponding material layer on the target substrate to obtain the target semiconductor device comprises the following steps:
  • a j-th material layer is arranged on the target substrate, and the high-energy particle beam lithography equipment is controlled to emit a high-energy particle beam to act on the j-th material layer, and a pattern corresponding to the j-th integrated circuit sub-layout is engraved to the j-th material layer, and the j-th to i-th material layers are penetrated at the coordinates of the pixel point to be adjusted.
  • the step of sequentially manufacturing each corresponding material layer on the target substrate comprises the steps of:
  • the high-energy particle beam lithography equipment is controlled to spray the material gas in the deposition area, so that the material gas is decomposed and deposited in the deposition area, thereby completing the production of the material layer.
  • the step of sequentially manufacturing each corresponding material layer on the target substrate comprises the steps of:
  • the high-energy particle beam is controlled to polish the material layer so that the current thickness and/or the current flatness of the material layer are respectively within the preset optimized thickness range and the preset optimized flatness range.
  • an embodiment of the present application provides a high-energy particle beam lithography device, comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the steps of the semiconductor device processing control method as described in the first aspect are implemented.
  • an integrated circuit layout corresponding to a target semiconductor device is obtained; wherein the integrated circuit layout includes several layers of integrated circuit sub-layouts, each layer of the integrated circuit sub-layout corresponds to a pattern of one or more material layers of the target semiconductor device; the several layers of the integrated circuit sub-layouts are respectively converted into grayscale images of a preset format; according to the correspondence between the preset high-energy particle beam processing parameters and the grayscale value, the high-energy particle beam processing parameters corresponding to each pixel in the grayscale image are obtained; each corresponding layer of the material layer is sequentially manufactured on the target substrate, and according to the high-energy particle beam processing parameters corresponding to each pixel in the grayscale image, the high-energy particle beam lithography equipment is controlled to emit a high-energy particle beam and act on the corresponding material layer on the target substrate, and the pattern corresponding to the integrated circuit sub-layout is engraved to the corresponding material layer on the target substrate, so that the target semiconductor device is obtained, so that there is no need to
  • FIG1 is a schematic flow chart of a method for controlling a semiconductor device according to an embodiment of the present application
  • FIG. 2 is a schematic diagram of a flow chart of step S104 in a method for controlling a semiconductor device processing according to an embodiment of the present application;
  • FIG3 is a schematic flow chart of a method for controlling a semiconductor device according to another embodiment of the present application.
  • FIG4 is a schematic diagram of a grayscale image corresponding to a layout of an integrated circuit of four MOS tubes connected in parallel provided by an embodiment of the present application;
  • FIG5 is a schematic diagram of a flow chart of step S207 in a method for controlling a semiconductor device processing according to another embodiment of the present application;
  • FIG6 is a schematic flow chart of a method for controlling a semiconductor device according to another embodiment of the present application.
  • FIG. 7 is a schematic flow chart of S305 in a semiconductor device processing control method provided in another embodiment of the present application.
  • FIG8 is a flow chart of S307 in a semiconductor device processing control method provided in another embodiment of the present application.
  • FIG9 is a schematic diagram of the structure of a high-energy particle beam lithography device provided in one embodiment of the present application.
  • first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other.
  • first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information.
  • the words "if"/"if” as used herein may be interpreted as "at the time of" or "when” or "in response to determination".
  • FIG. 1 is a flow chart of a method for controlling a semiconductor device according to an embodiment of the present application. The method comprises the following steps:
  • S101 Obtain an integrated circuit layout corresponding to a target semiconductor device; wherein the integrated circuit layout includes several layers of integrated circuit sub-layouts, and each layer of the integrated circuit sub-layout corresponds to a pattern of one or more material layers of the target semiconductor device.
  • the executor of the processing control method of the semiconductor device may be a high-energy particle beam lithography device, or a component in the high-energy particle beam lithography device, such as a processor or microprocessor inside the device; in another optional embodiment, the executor of the processing control method of the semiconductor device may be an external device that establishes a data connection with the high-energy particle beam lithography device, or a component in the external device.
  • the execution subject of the semiconductor device processing control method is a high-energy particle beam lithography device.
  • the high-energy particle beam lithography equipment obtains the integrated circuit layout corresponding to the target semiconductor device.
  • the target semiconductor device may be any type of semiconductor device, and its specific type is not limited herein.
  • the integrated circuit layout refers to mapping the circuit design circuit diagram or circuit description language to the physical description level.
  • the integrated circuit layout includes relevant physical information such as the device type, device size, relative position between devices, and connection relationship between each device of the integrated circuit.
  • the integrated circuit layout includes several layers of integrated circuit sub-layouts, and each layer of the integrated circuit sub-layout corresponds to the pattern of a material layer of the target semiconductor device.
  • the material layer includes but is not limited to an active layer, an insulating layer, a polysilicon gate layer, a metal layer, and the like.
  • the high-energy particle beam lithography equipment converts the integrated circuit sub-layouts of the plurality of layers into grayscale images of a preset format.
  • the preset format is a TIF format, and in other optional embodiments, the preset format may be other image formats that can be recognized and processed by the high-energy particle beam.
  • the grayscale value of the pixel in the grayscale image is 0 to 255, where a grayscale value of 0 indicates that the pixel has a lower brightness, and the human body subjectively perceives it as black, and a grayscale value of 255 indicates that the pixel has a higher brightness, and the human body subjectively perceives it as white.
  • the correspondence between the preset high-energy particle beam processing parameters and the grayscale values can be preset and stored in the high-energy particle beam lithography equipment. In another optional embodiment, the correspondence between the preset high-energy particle beam processing parameters and the grayscale values can be preset and stored in the cloud or host computer, and then downloaded to the high-energy particle beam lithography equipment when used.
  • the corresponding relationship between the high-energy particle beam processing parameters and the grayscale value is also different.
  • the corresponding relationship between the high-energy particle beam processing parameters and the grayscale value can be found according to the identification of the semiconductor device, or the corresponding relationship between the high-energy particle beam processing parameters and the grayscale value can be found according to the material identification of the material layer.
  • a third-party semiconductor device design manufacturer can upload the designed semiconductor device identification or material identification to the cloud, and configure the corresponding relationship between the high-energy particle beam processing parameters and the grayscale value, so that the high-energy particle beam lithography equipment can control the high-energy particle beam lithography equipment to complete the processing of more types of semiconductor devices and meet more third-party customer needs.
  • the high-energy particle beam processing parameters include the high-energy particle beam acceleration voltage and/or the high-energy particle beam action time.
  • the high-energy particle beam lithography equipment obtains the high-energy particle beam processing parameters corresponding to each pixel in the grayscale image according to the correspondence between the preset high-energy particle beam processing parameters and the grayscale value, which are as follows:
  • the high-energy particle beam lithography device obtains the high-energy particle beam acceleration voltage corresponding to each pixel in the grayscale image according to the grayscale value of the pixel in the grayscale image.
  • the high-energy particle beam acceleration voltage of the high-energy particle beam lithography device is higher.
  • the high-energy particle beam acceleration voltage of the high-energy particle beam lithography device is lower. The higher the high-energy particle beam acceleration voltage, the higher the kinetic energy of the emitted high-energy particle beam, so that in the same amount of time, more material can be carved away to obtain deeper material grooves.
  • the high-energy particle beam lithography device obtains the high-energy particle beam action time corresponding to each pixel in the grayscale image according to the grayscale value of the pixel in the grayscale image.
  • the high-energy particle beam action time of the high-energy particle beam lithography device is longer.
  • the high-energy particle beam action time of the high-energy particle beam lithography device is shorter. The longer the high-energy particle beam action time, the more material can be engraved and deeper material grooves can be obtained when other control conditions remain unchanged.
  • the high-energy particle beam lithography device obtains the grayscale mean value of all pixels in the grayscale image.
  • the high-energy particle beam acceleration voltage of the high-energy particle beam lithography device is made higher.
  • the high-energy particle beam action time corresponding to each pixel in the grayscale image is obtained when the high-energy particle beam acceleration voltage remains unchanged.
  • the grayscale value of the pixel in the grayscale image is smaller, the high-energy particle beam action time of the high-energy particle beam lithography device is made longer.
  • the high-energy particle beam action time of the high-energy particle beam lithography device is made shorter.
  • each corresponding material layer is manufactured on the target substrate in sequence, and according to the high-energy particle beam processing parameters corresponding to each pixel point in the grayscale image, the high-energy particle beam lithography equipment is controlled to emit a high-energy particle beam and act on the corresponding material layer on the target substrate, and the pattern corresponding to the integrated circuit sub-layout is engraved on the corresponding material layer on the target substrate to obtain the target semiconductor device.
  • the material layer is a pre-processed material layer, and each corresponding material layer is placed on the target substrate in sequence by controlling a mechanical device.
  • the material layer is a material layer deposited by controlling a high-energy particle beam lithography device.
  • the step of sequentially manufacturing each corresponding material layer on the target substrate includes steps S1041 to S1042, as follows:
  • the material gas may be one gas or multiple gases, which may be different according to the differences of the material layers.
  • each material layer includes multiple materials. For example, a layer of silicon oxide is first plated on the surface of single crystal silicon, and then a layer of tantalum is plated on the surface of the silicon oxide. Accordingly, multiple material gases are also required when preparing such material layers.
  • S1042 Control the high-energy particle beam lithography equipment to spray the material gas in the deposition area, so that the material gas is decomposed and deposited in the deposition area, thereby completing the production of the material layer.
  • the material gas is sprayed in the deposition area through the gas injection device in the high-energy particle beam lithography equipment, and the high-energy particle beam is emitted to decompose the material gas at the same time, so that the decomposed material gas is deposited in the deposition area to complete the production of the material layer.
  • the above method can complete the laying of material layers and the engraving of patterns by controlling a high-energy particle beam lithography device, thereby realizing the processing of semiconductor devices, which can not only reduce costs but also have a higher degree of automation.
  • the high-energy particle beam lithography equipment can also control the high-energy particle beam to polish the material layer according to a preset optimized thickness range and/or a preset optimized flatness range, so that the current thickness and/or current flatness of the material layer are respectively within the preset optimized thickness range and the preset optimized flatness range, thereby further improving the subsequent engraving effect and optimizing the processing of semiconductor devices.
  • the preset optimized thickness range is 1 nm to 500 nm
  • the preset optimized flatness range is 0.5 nm to 5 nm.
  • the high-energy particle beam lithography equipment Before controlling the high-energy particle beam lithography equipment to emit a high-energy particle beam and act on the corresponding material layer on the target substrate, the high-energy particle beam lithography equipment can control the electromagnetic lens to perform the high-energy particle beam miniaturization according to a preset engraving size threshold, so that the pixel size of the high-energy particle beam engraving is smaller than the engraving size threshold.
  • an integrated circuit layout corresponding to a target semiconductor device is obtained; wherein the integrated circuit layout includes several layers of integrated circuit sub-layouts, each layer of the integrated circuit sub-layout corresponds to a pattern of one or more material layers of the target semiconductor device; the several layers of the integrated circuit sub-layouts are respectively converted into grayscale images of a preset format; according to the correspondence between the preset high-energy particle beam processing parameters and the grayscale value, the high-energy particle beam processing parameters corresponding to each pixel in the grayscale image are obtained; each corresponding layer of the material layer is sequentially manufactured on the target substrate, and according to the high-energy particle beam processing parameters corresponding to each pixel in the grayscale image, the high-energy particle beam lithography equipment is controlled to emit a high-energy particle beam and act on the corresponding material layer on the target substrate, and the pattern corresponding to the integrated circuit sub-layout is engraved on the corresponding material layer on the target substrate to obtain the target semiconductor device, so that there is no need to manufacture multiple mask
  • FIG. 3 is a flow chart of a method for controlling the processing of semiconductor devices provided by another embodiment of the present application, including steps S201 to S207, wherein steps S201 to S202 and S206 are respectively the same as steps S101 to S102 and S103, and are specifically as follows:
  • S201 Obtain an integrated circuit layout corresponding to a target semiconductor device; wherein the integrated circuit layout includes several layers of integrated circuit sub-layouts, and each layer of the integrated circuit sub-layout corresponds to a pattern of one or more material layers of the target semiconductor device.
  • S203 Obtain target pixel points in the grayscale image corresponding to each layer of the integrated circuit sub-layout and the coordinates of the target pixel points in the grayscale image; wherein the target pixel points are pixel points whose grayscale values are lower than a preset threshold.
  • the grayscale image corresponding to the integrated circuit sub-layout there may be some target pixels whose grayscale values are lower than a preset threshold, indicating that the coordinates of the target pixels in the corresponding material layer need to be penetrated by the high-energy particle beam.
  • the preset threshold is related to the corresponding relationship between the preset high-energy particle beam processing parameters and the grayscale value, and can be set according to actual conditions, and is not limited here.
  • FIG 4 is a schematic diagram of a grayscale image corresponding to a layout of an integrated circuit of four MOS tubes connected in parallel according to an embodiment of the present application.
  • the integrated circuit layout in Figure 4 includes an active layer, a polysilicon gate layer, a metal layer, and an insulating layer (not shown) on the active layer and the polysilicon gate layer.
  • target pixels with the same coordinates in the grayscale images corresponding to the integrated circuit sub-layouts of the i-th to j-th layers, then these target pixels are the pixels to be adjusted.
  • engraving is not performed at the coordinates of the pixels to be adjusted when engraving the corresponding material layer.
  • the integrated circuit sub-layout has n layers in total, 1 ⁇ i ⁇ j ⁇ n.
  • S205 reset the grayscale values of the pixels to be adjusted in the grayscale images corresponding to the integrated circuit sub-layouts of the i-th to j-th layers according to a preset adjustment strategy.
  • the grayscale value of the pixel to be adjusted in the grayscale image corresponding to the integrated circuit sub-layout of the i-th to j-th layers is set to the highest value, i.e., 255, so that when engraving the pattern corresponding to the integrated circuit sub-layout of the i-th to j-th layers, the pattern composed of the pixel to be adjusted will not be engraved.
  • the high-energy particle beam lithography equipment first obtains a first grayscale value corresponding to the lowest high-energy particle beam processing parameter.
  • the high-energy particle beam processing parameters include the high-energy particle beam acceleration voltage and/or the high-energy particle beam action time.
  • the grayscale value corresponding to the high-energy particle beam acceleration voltage being 0 or the high-energy particle beam action time being 0 is the first grayscale value.
  • the first grayscale value will also be different and is not necessarily 255, and its specific value is not limited here.
  • the high-energy particle beam lithography equipment sets the grayscale values of the pixels to be adjusted in the grayscale images corresponding to the integrated circuit sub-layouts of the i-th to j-th layers to the first grayscale values, thereby ensuring that when engraving the patterns corresponding to the integrated circuit sub-layouts of the i-th to j-th layers, the patterns composed of the pixels to be adjusted will not be engraved.
  • each corresponding material layer is manufactured on the target substrate in sequence, and according to the high-energy particle beam processing parameters corresponding to each pixel point in the grayscale image, the high-energy particle beam lithography equipment is controlled to emit a high-energy particle beam and act on the corresponding material layer on the target substrate, and the pattern corresponding to the integrated circuit sub-layout is engraved on the corresponding material layer on the target substrate to obtain the target semiconductor device.
  • Step S207 is performed in the same manner as step S104, that is, each time a material layer is provided, a pattern corresponding to the integrated circuit sub-layout is engraved on the material layer, and finally a target semiconductor device is obtained.
  • step S207 includes steps S2071 to S2072, and the specific difference process is as follows:
  • S2071 fabricating the i-j material layers in sequence on the target substrate, and controlling the high-energy particle beam lithography equipment to emit a high-energy particle beam to act on the i-j material layers according to the high-energy particle beam processing parameters corresponding to each pixel point in the grayscale image corresponding to the i-j integrated circuit sub-layout, respectively, to engrave all patterns corresponding to the i-j integrated circuit sub-layout except the pattern composed of the pixel points to be adjusted onto the corresponding i-j material layers.
  • the high-energy particle beam lithography equipment After the high-energy particle beam lithography equipment lays down each material layer (the i-th to j-th layers), the high-energy particle beam lithography equipment is controlled to emit a high-energy particle beam to act on the material layer according to the high-energy particle beam processing parameters corresponding to each pixel point in the grayscale image corresponding to the integrated circuit sub-layout of this layer, and all patterns corresponding to the integrated circuit sub-layout of this layer, except for the pattern composed of the pixel points to be adjusted, are engraved on the material layer.
  • the engraving of the layers other than the i-th to j-th material layers is the same as the engraving in step S104 and will not be described in detail.
  • the high-energy particle beam lithography equipment After the high-energy particle beam lithography equipment has engraved all patterns corresponding to the j-th layer of the integrated circuit sub-layout except the pattern composed of the pixel points to be adjusted to the j-th layer of the material layer, the high-energy particle beam lithography equipment is controlled to emit a high-energy particle beam to act on the coordinates of the pixel points to be adjusted in the j-th layer of the material layer according to the coordinates of the pixel points to be adjusted, and penetrate the i-j layer of the material layer at the coordinates of the pixel points to be adjusted.
  • the high-energy particle beam processing parameters that penetrate each material layer can be obtained according to experiments and pre-stored in the high-energy particle beam lithography equipment.
  • the corresponding high-energy particle beam processing parameters can be found according to the identification of the material layer, thereby obtaining the high-energy particle beam processing parameters that penetrate the i-th to j-th layers.
  • the target pixel points in the grayscale image corresponding to each layer of the integrated circuit sub-layout and the coordinates of the target pixel points by obtaining the target pixel points in the grayscale image corresponding to each layer of the integrated circuit sub-layout and the coordinates of the target pixel points, the target pixel points with the same coordinates that exist in the grayscale images corresponding to the integrated circuit sub-layouts from the i to j layers, that is, the pixel points to be adjusted, are obtained, and then the grayscale values of the pixel points to be adjusted are reset through the adjustment strategy, so that when the patterns corresponding to the integrated circuit sub-layouts from the i to j layers are engraved to the i to j layers of material layers respectively, the patterns composed of the pixel points to be adjusted will not be engraved.
  • the high-energy particle beam lithography equipment is controlled to emit a high-energy particle beam to act on the coordinates of the pixel points to be adjusted in the j layer of material layer according to the coordinates of the pixel points to be adjusted, and penetrate the i to j layers of material layers at the coordinates of the pixel points to be adjusted, so as to realize combined engraving, thereby effectively improving the processing efficiency of semiconductor devices.
  • FIG. 6 is a flow chart of a semiconductor device processing control method provided in another embodiment of the present application, including steps S301 to S307, wherein steps S301 to S304 and S306 are respectively the same as steps S201 to S204 and S206, and are specifically as follows:
  • S301 Obtain an integrated circuit layout corresponding to a target semiconductor device; wherein the integrated circuit layout includes several layers of integrated circuit sub-layouts, and each layer of the integrated circuit sub-layout corresponds to a pattern of one or more material layers of the target semiconductor device.
  • S303 Obtain target pixel points in the grayscale image corresponding to each layer of the integrated circuit sub-layout and the coordinates of the target pixel points in the grayscale image; wherein the target pixel points are pixel points whose grayscale values are lower than a preset threshold.
  • S305 reset the grayscale values of the pixels to be adjusted in the grayscale images corresponding to the integrated circuit sub-layouts of the i-th to j-th layers according to a preset adjustment strategy.
  • the adjustment strategy preset in step S305 is different from the adjustment strategy preset in step S205, specifically:
  • step S305 when the grayscale value of the pixel to be adjusted in the grayscale image corresponding to the integrated circuit sub-layout of the i-th to j-1-th layer is set, it is the same as step S205, except that the grayscale value of the pixel to be adjusted in the grayscale image corresponding to the integrated circuit sub-layout of the j-th layer is set separately in step S305.
  • Step S305 includes steps S3051 to S3054:
  • S3051 Set the grayscale value of the pixel to be adjusted in the grayscale image corresponding to the integrated circuit sub-layout of the i to j-1 layers to the highest value, or obtain the first grayscale value corresponding to the lowest high-energy particle beam processing parameter, and set the grayscale value of the pixel to be adjusted in the grayscale image corresponding to the integrated circuit sub-layout of the i to j-1 layers to the first grayscale value.
  • S3052 Obtain target high-energy particle beam processing parameters that penetrate the i-th to j-th material layers.
  • the high-energy particle beam processing parameters penetrating each material layer can be obtained according to experiments and pre-stored in the high-energy particle beam lithography equipment.
  • the corresponding high-energy particle beam processing parameters can be found according to the identification of the material layer, thereby obtaining the high-energy particle beam processing parameters penetrating the i-j layers.
  • S3053 Acquire a second grayscale value according to the corresponding relationship between the target high-energy particle beam processing parameter and the preset high-energy particle beam processing parameter and the grayscale value.
  • the high-energy particle beam lithography equipment obtains the second grayscale value according to the corresponding relationship between the preset high-energy particle beam processing parameters and the grayscale value and the target high-energy particle beam processing parameters.
  • S3054 Setting the grayscale value of the pixel to be adjusted in the grayscale image corresponding to the integrated circuit sub-layout of the j-th layer to the second grayscale value.
  • the high-energy particle beam lithography equipment sets the grayscale value of the pixel to be adjusted in the grayscale image corresponding to the integrated circuit sub-layout of the jth layer to the second grayscale value. This allows the high-energy particle beam equipment to control the high-energy particle beam to act on the coordinates of the pixel in the jth material layer according to the target high-energy particle beam processing parameters corresponding to the second grayscale value when engraving the jth material layer. This allows the high-energy particle beam to penetrate the i to jth material layers at the coordinates of the pixel.
  • the pattern composed of the pixel to be adjusted can be engraved to the i-j material layers at the same time, thereby reducing the engraving steps and further improving the processing efficiency.
  • each corresponding material layer is manufactured on the target substrate in sequence, and according to the high-energy particle beam processing parameters corresponding to each pixel point in the grayscale image, the high-energy particle beam lithography equipment is controlled to emit a high-energy particle beam and act on the corresponding material layer on the target substrate, and the pattern corresponding to the integrated circuit sub-layout is engraved on the corresponding material layer on the target substrate to obtain the target semiconductor device.
  • step S307 includes steps S3071 to S3072, which are specifically as follows:
  • S3071 fabricate i to j-1th material layers on the target substrate in sequence, and control the high-energy particle beam lithography equipment to emit a high-energy particle beam to act on the i to j-1th material layers according to the high-energy particle beam processing parameters corresponding to each pixel point in the grayscale image corresponding to the i to j-1th integrated circuit sub-layout, and engrave all patterns corresponding to the i to j-1th integrated circuit sub-layout except the pattern composed of the pixel points to be adjusted to the corresponding i to j-1th material layers.
  • the high-energy particle beam lithography equipment After the high-energy particle beam lithography equipment lays down each material layer (the i-th to j-1-th layers), the high-energy particle beam lithography equipment is controlled to emit a high-energy particle beam to act on the material layer according to the high-energy particle beam processing parameters corresponding to each pixel point in the grayscale image corresponding to the integrated circuit sub-layout of this layer, and all patterns corresponding to the integrated circuit sub-layout of this layer, except for the pattern composed of the pixel points to be adjusted, are engraved on the material layer.
  • S3072 Arrange the jth material layer on the target substrate, control the high-energy particle beam lithography equipment to emit a high-energy particle beam to act on the jth material layer, engrave the pattern corresponding to the jth integrated circuit sub-layout to the jth material layer, and penetrate the j to i material layers at the coordinates of the pixel point to be adjusted.
  • the grayscale value of the pixel to be adjusted is set to the second grayscale value in the grayscale image corresponding to the j-th layer of the integrated circuit sub-layout, when the high-energy particle beam lithography equipment is engraving the coordinates of the pixel to be adjusted in the j-th layer of the material layer, it will emit a high-energy particle beam to act on the coordinates of the pixel to be adjusted according to the target high-energy particle beam processing parameters corresponding to the second grayscale value, so that the high-energy particle beam penetrates the j to i layers of the material layer at the coordinates.
  • the engraving of the layers other than the i-th to j-th material layers is the same as the engraving in step S104 and will not be described in detail.
  • the target pixel points in the grayscale image corresponding to each layer of the integrated circuit sub-layout and the coordinates of the target pixel points are obtained, and then the grayscale values of the pixel points to be adjusted in the i to j-1 layers and the grayscale values of the pixel points to be adjusted in the j layer are reset respectively through the adjustment strategy, so that when the patterns corresponding to the integrated circuit sub-layouts of the i to j-1 layers are engraved to the i to j-1 layers of the material layer respectively, the patterns composed of the pixel points to be adjusted will not be engraved.
  • the high-energy particle beam lithography equipment is controlled to emit a high-energy particle beam to act on the coordinates of the pixel points to be adjusted, and penetrate the i to j layers of the material layer at the coordinates of the pixel points to be adjusted, so as to realize the combined engraving of the pattern corresponding to the j layer of the integrated circuit sub-layout and the pattern composed of the pixel points to be adjusted in the i to j-1 layers, thereby further improving the processing efficiency of the semiconductor device.
  • the high-energy particle beam lithography device 9 may include: a processor 90, a memory 91, and a computer program 92 stored in the memory 91 and executable on the processor 90, such as a semiconductor device processing control program; when the processor 90 executes the computer program 92, the steps in the above-mentioned method embodiments are implemented, such as steps S101 to S104 shown in Figure 1.
  • the processor 90 may include one or more processing cores.
  • the processor 90 uses various interfaces and lines to connect various parts in the high-energy particle beam lithography device 9, and executes various functions and processes data of the high-energy particle beam lithography device 9 by running or executing instructions, programs, code sets or instruction sets stored in the memory 91, and calling the data in the memory 91.
  • the processor 90 can be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA).
  • DSP digital signal processing
  • FPGA field-programmable gate array
  • PDA programmable logic array
  • the processor 90 can integrate one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), and a modem.
  • the CPU mainly processes the operating system, user interface, and application programs; the GPU is responsible for rendering and drawing the content to be displayed on the touch display screen; and the modem is used to process wireless communication. It can be understood that the above-mentioned modem may not be integrated into the processor 90, but implemented by a single chip.
  • the memory 91 may include a random access memory (RAM) or a read-only memory (ROM).
  • the memory 91 includes a non-transitory computer-readable storage medium.
  • the memory 91 may be used to store instructions, programs, codes, code sets or instruction sets.
  • the memory 91 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch instructions, etc.), instructions for implementing the above-mentioned various method embodiments, etc.; the data storage area may store data involved in the above-mentioned various method embodiments, etc.
  • the memory 91 may also be optionally at least one storage device located away from the aforementioned processor 90.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Inorganic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Analytical Chemistry (AREA)
  • Electron Beam Exposure (AREA)

Abstract

本发明涉及一种半导体器件的加工控制方法及高能粒子束光刻设备，所述半导体器件的加工控制方法包括：获取目标半导体器件对应的集成电路版图；将若干层集成电路子版图分别转化为预设格式的灰度图片；根据预设的高能粒子束加工参数与灰度值之间的对应关系，获取灰度图片中各像素点对应的高能粒子束加工参数；在目标基材上依次制作相应的每一层材料层，并分别根据灰度图片中各像素点对应的高能粒子束加工参数，控制高能粒子束光刻设备发射高能粒子束并作用于目标基材上相应的材料层，雕刻集成电路子版图对应的图案至所述目标基材上相应的材料层，得到目标半导体器件。相对于现有技术，本申请无需用到集成电路掩膜版，提升了雕刻效果和加工效率，降低了生产成本。

Description

半导体器件的加工控制方法及高能粒子束光刻设备 技术领域
本申请实施例涉及半导体加工技术领域，尤其涉及一种半导体器件的加工控制方法及高能粒子束光刻设备。
背景技术
在传统的半导体加工技术领域中，往往都是基于集成电路掩膜版与光刻技术的结合，实现将集成电路版图转移至硅基材上，进而完成半导体器件的制造。
但是，随着对半导体器件的尺寸要求越来越高，支撑光刻技术的光源系统(如EUV光刻机)的制造和集成电路掩膜版的制作变得越发艰难，使用集成电路掩膜版也会使半导体器件的制造成本巨大，并且，若对集成电路版图进行修改或微调，则需要再重新制作掩膜版，致使加工效率低下。
本申请中的高能粒子束可以是离子束、电子束、激光束、X射线等，其中实验用到的是高能聚焦离子束。高能粒子束拥有比普通光学系统更小的波长，可以提升版图转移的分辨率，适合于制作更小尺寸的器件。比如DUV光刻机因为波长的限制，只适用于制作特征尺寸大于7nm的器件；对于7nm以下的器件制作，必须要引入EUV。而高能粒子束拥有比EUV更小的波长。
发明内容
本申请实施例提供了一种半导体器件的加工控制方法及高能粒子束光刻设备，可以在不制作集成电路掩膜版完成半导体器件的加工处理，提高加工效率，所述技术方案如下:
第一方面，本申请实施例提供了一种半导体器件的加工控制方法，包括：
获取目标半导体器件对应的集成电路版图；其中，所述集成电路版图包括若干层集成电路子版图，每一层集成电路子版图分别对应所述目标半导体器件一层或多层材料层的图案；
将若干层所述集成电路子版图分别转化为预设格式的灰度图片；
根据预设的高能粒子束加工参数与灰度值之间的对应关系，获取所述灰度图片中各像素点对应的高能粒子束加工参数；
在目标基材上依次制作相应的每一层所述材料层，并分别根据所述灰度图片中各像素点对应的高能粒子束加工参数，控制高能粒子束光刻设备发射高能粒子束并作用于所述目标基材上相应的材料层，雕刻所述集成电路子版图对应的图案至所述目标基材上相应的材料层，得到所述目标半导体器件。
可选的，所述高能粒子束加工参数包括高能粒子束加速电压和/或高能粒子束作用时间，
根据预设的高能粒子束加工参数与灰度值之间的对应关系，获取所述灰度图片中各像素点对应的高能粒子束加工参数，包括步骤：
根据所述灰度图片中像素点的灰度值，获取所述灰度图片中各像素点对应的高能粒子束加速电压，当所述灰度图片中像素点的灰度值越小时，使所述高能粒子束光刻设备的高能粒子束加速电压越高，当所述灰度图片中像素点的灰度值越大时，使所述高能粒子束光刻设备的高能粒子束加速电压越低；
或，
根据所述灰度图片中像素点的灰度值，获取所述灰度图片中各像素点对应的高能粒子束作用时间，当所述灰度图片中像素点的灰度值越小时，使所述高能粒子束光刻设备的高能粒子束作用时间越长，当所述灰度图片中像素点的灰度值越大时，使所述高能粒子束光刻设备的高能粒子束作用时间越短；
或，
获取所述灰度图片中所有像素点的灰度均值，当所述灰度均值越小时，使所述高能粒子束光刻设备的所述高能粒子束加速电压越高，并根据所述灰度图片中像素点的灰度值，获取在所述高能粒子束加速电压不变的情况下所述灰度图片中各像素点对应的高能粒子束作用时间，当所述灰度图片中像素点的灰度值越小时，使所述高能粒子束光刻设备的高能粒子束作用时间越长，当所诉灰度图片中像素点的灰度值越大时，使所述高能粒子束光刻设备的高能粒子束作用时间越短。
可选的，所述将若干层所述集成电路子版图分别转化为预设格式的灰度图片之后，包括步骤：
获取每层所述集成电路子版图对应的灰度图片中的目标像素点以及所述目标像素点在所述灰度图片中的坐标；其中，所述目标像素点为灰度值低于预设阈值的像素点；
当第i至j层所述集成电路子版图对应的灰度图片中均存在坐标相同的目标像素点时，得到第i至j层所述集成电路子版图对应的灰度图片中的待调整像素点；
根据预设的调整策略重新设置第i至j层所述集成电路子版图对应的灰度图片中的待调整像素点的灰度值。
可选的，所述根据预设的调整策略重新设置第i至j层所述集成电路子版图对应的灰度图片中的待调整像素点的灰度值，包括步骤：
将第i至j层所述集成电路子版图对应的灰度图片中所述待调整像素点的灰度值设置为最高值；
或者，
获取最低的高能粒子束加工参数对应的第一灰度值；
将所述第i至j层所述集成电路子版图对应的灰度图片中所述待调整像素点的灰度值设置为所述第一灰度值。
可选的，所述在目标基材上依次制作相应的每一层所述材料层，并分别根据所述灰度图片中各像素点对应的高能粒子束加工参数，控制高能粒子束光刻设备发射高能粒子束并作用于所述目标基材上相应的材料层，雕刻所述集成电路子版图对应的图案至所述目标基材上相应的材料层，得到所述目标半导体器件，包括步骤：
在所述目标基材上依次制作第i至j层材料层，分别根据所述第i至j层所述集成电路子版图对应的灰度图片中各像素点对应的高能粒子束加工参数，控制所述高能粒子束光刻设备发射高能粒子束作用于第i至j层材料层上，雕刻所述第i至j层所述集成电路子版图对应的除所述待调整像素点组成的图案以外的所有图案至相应的第i至j层材料层；
根据所述待调整像素点的坐标，控制所述高能粒子束光刻设备发射高能粒子束作用于第j层材料层中所述待调整像素点的坐标处，在所述待调整像素点的坐标处穿透第i至j层材料层。
可选的，所述根据预设的调整策略重新设置第i至j层所述集成电路子版图对应的灰度图片中的待调整像素点的灰度值，包括步骤：
将第i至j-1层所述集成电路子版图对应的灰度图片中所述待调整像素点的灰度值设置为最高值，或者，获取最低的高能粒子束加工参数对应的第一灰度值，将所述第i至j-1层所述集成电路子版图对应的灰度图片中所述待调整像素点的灰度值设置为所述第一灰度值；
获取穿透所述第i至j层材料层的目标高能粒子束加工参数；
根据所述目标高能粒子束加工参数和所述预设的高能粒子束加工参数与灰度值之间的对应关系，获取第二灰度值；
将第j层所述集成电路子版图对应的灰度图片中所述待调整像素点的灰度值设置为所述第二灰度值。
可选的，所述在目标基材上依次制作相应的每一层所述材料层，并分别根据所述灰度图片中各像素点对应的高能粒子束加工参数，控制高能粒子束光刻设备发射高能粒子束并作用于所述目标基材上相应的材料层，雕刻所述集成电路子版图对应的图案至所述目标基材上相应的材料层，得到所述目标半导体器件，包括步骤：
在所述目标基材上依次制作第i至j-1层材料层，分别根据所述第i至j-1层所述集成电路子版图对应的灰度图片中各像素点对应的高能粒子束加工参数，控制所述高能粒子束光刻 设备发射高能粒子束作用于第i至j-1层材料层上，雕刻所述第i至j-1层所述集成电路子版图对应的除所述待调整像素点组成的图案以外的所有图案至相应的第i至j-1层材料层；
在所述目标基材上设置第j层材料层，控制所述高能粒子束光刻设备发射高能粒子束作用于第j层材料层上，雕刻所述第j层所述集成电路子版图对应的图案至第j层材料层，并在所述待调整像素点的坐标处穿透所述第j至i层材料层。
可选的，所述在目标基材上依次制作相应的每一层所述材料层，包括步骤：
获取所述材料层对应的材料气体和所述材料层在所述目标基材上对应的沉积区域；
控制所述高能粒子束光刻设备在所述沉积区域喷射所述材料气体，使所述材料气体分解后沉积在所述沉积区域，完成所述材料层的制作。
可选的，所述在目标基材上依次制作相应的每一层所述材料层，包括步骤：
根据预设的优化厚度范围和/或预设的优化平整度范围，控制所述高能粒子束对所述材料层进行打磨，使所述材料层的当前厚度和/或当前平整度分别在所述预设的优化厚度范围和预设的优化平整度范围之内。
第二方面，本申请实施例提供了一种高能粒子束光刻设备，包括：处理器、存储器以及存储在所述存储器中并可在所述处理器上运行的计算机程序，所述处理器执行所述计算机程序时实现如第一方面所述的半导体器件的加工控制方法的步骤。
本申请实施例中，通过获取目标半导体器件对应的集成电路版图；其中，所述集成电路版图包括若干层集成电路子版图，每一层集成电路子版图分别对应所述目标半导体器件一层或多层材料层的图案；将若干层所述集成电路子版图分别转化为预设格式的灰度图片；根据预设的高能粒子束加工参数与灰度值之间的对应关系，获取所述灰度图片中各像素点对应的高能粒子束加工参数；在目标基材上依次制作相应的每一层所述材料层，并分别根据所述灰度图片中各像素点对应的高能粒子束加工参数，控制高能粒子束光刻设备发射高能粒子束并作用于所述目标基材上相应的材料层，雕刻所述集成电路子版图对应的图案至所述目标基材上相应的材料层，得到所述目标半导体器件，使得不需要制作多张掩膜版，就可以直接根据集成电路子版图对应的灰度图片中各像素点的灰度值，自动调节高能粒子束加工参数完成图案雕刻，得到半导体器件，这种方式能够大幅节约成本，提高雕刻精度，而且可以灵活地修改集成电路版图，提高加工效率。
为了更好地理解和实施，下面结合附图详细说明本申请的技术方案。
附图说明
图1为本申请一个实施例提供的半导体器件的加工控制方法的流程示意图；
图2为本申请一个实施例提供的半导体器件的加工控制方法中S104的流程示意图；
图3为本申请另一个实施例提供的半导体器件的加工控制方法的流程示意图；
图4为本申请一个实施例提供的四个MOS管并联集成电路版图对应的灰度图片的示意图；
图5为本申请另一个实施例提供的半导体器件的加工控制方法中S207的流程示意图；
图6为本申请其他实施例提供的半导体器件的加工控制方法的流程示意图；
图7为本申请其他实施例提供的半导体器件的加工控制方法中S305的流程示意图；
图8为本申请其他实施例提供的半导体器件的加工控制方法中S307的流程示意图；
图9为本申请一个实施例提供的高能粒子束光刻设备的结构示意图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
在本申请使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。在本申请和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
应当理解，尽管在本申请可能采用术语第一、第二、第三等来描述各种信息，但这些信息不应限于这些术语。这些术语仅用来将同一类型的信息彼此区分开。例如，在不脱离本申请范围的情况下，第一信息也可以被称为第二信息，类似地，第二信息也可以被称为第一信息。取决于语境，如在此所使用的词语“如果”/“若”可以被解释成为“在……时”或“当……时”或“响应于确定”。
请参阅图1，为本申请一个实施例提供的半导体器件的加工控制方法的流程示意图，所述方法包括如下步骤：
S101：获取目标半导体器件对应的集成电路版图；其中，所述集成电路版图包括若干层集成电路子版图，每一层集成电路子版图分别对应所述目标半导体器件一层或多层材料层的图案。
在一个可选的实施例中，所述半导体器件的加工控制方法的执行主体可以为高能粒子束光刻设备，也可以为高能粒子束光刻设备中的组成部件，例如其内部的处理器或微处理器等； 在另一个可选的实施例中，所述半导体器件的加工控制方法的执行主体可以为与高能粒子束光刻设备建立数据连接的外部设备，也可以为外部设备中的组成部件。
在本申请实施例中，所述半导体器件的加工控制方法的执行主体为高能粒子束光刻设备。
具体地，高能粒子束光刻设备获取目标半导体器件对应的集成电路版图。
其中，所述目标半导体器件可以为任意类型的半导体器件，对于其具体类型在此不进行限定。
所述集成电路版图是指将电路设计电路图或电路描述语言映射到物理描述层面，集成电路版图中包括集成电路的器件类型、器件尺寸、器件之间的相对位置以及各个器件之间的连接关系等相关物理信息。
所述集成电路版图中包括若干层集成电路子版图，每一层集成电路子版图分别对应目标半导体器件一层材料层的图案。
在本申请实施例中，所述材料层包括但不仅限于有源层、绝缘层、多晶硅栅极层和金属层等。
S102：将若干层所述集成电路子版图分别转化为预设格式的灰度图片。
高能粒子束光刻设备将若干层所述集成电路子版图分别转化为预设格式的灰度图片。在一个可选的实施例中，所述预设格式为TIF格式，在其他可选的实施例中，所述预设格式可以为高能粒子束可识别处理的其他图片格式。
所述灰度图片中像素点的灰度值为0至255，灰度值为0表示像素点亮度较低，人体主观视觉感受其为黑色，灰度值为255表示像素点亮度较高，人体主观视觉感受其为白色。
S103：根据预设的高能粒子束加工参数与灰度值之间的对应关系，获取所述灰度图片中各像素点对应的高能粒子束加工参数。
在一个可选的实施例中，所述预设的高能粒子束加工参数与灰度值之间的对应关系可以预先设置并存储在所述高能粒子束光刻设备中。在另一个可选的实施例中，所述预设的高能粒子束加工参数与灰度值之间的对应关系可以预先设置并存储在云端或上位机中，在使用时再下载至所述高能粒子束光刻设备中。
根据半导体器件类型的不同或者材料层的材料差异，相应的高能粒子束加工参数与灰度值之间的对应关系也不同。在所述高能粒子束光刻设备、云端或上位机中，可以根据半导体器件的标识，查找相应的高能粒子束加工参数与灰度值之间的对应关系，也可以根据材料层的材料标识，查找相应的高能粒子束加工参数与灰度值之间的对应关系。
在一个可选的实施例中，第三方半导体器件设计厂家可以将设计的半导体器件标识或材料标识上传至所述云端中，并配置相应的高能粒子束加工参数与灰度值之间的对应关系，从 而能够使得高能粒子束光刻设备能够控制高能粒子束光刻设备完成更多类型的半导体器件的加工，满足更多的第三方客户需求。
在本申请实施例中，所述高能粒子束加工参数包括高能粒子束加速电压和/或高能粒子束作用时间，为更精准地对半导体器件进行加工，高能粒子束光刻设备根据预设的高能粒子束加工参数与灰度值之间的对应关系，获取所述灰度图片中各像素点对应的高能粒子束加工参数，具体如下：
高能粒子束光刻设备根据所述灰度图片中像素点的灰度值，获取所述灰度图片中各像素点对应的高能粒子束加速电压，当所述灰度图片中像素点的灰度值越小时，使所述高能粒子束光刻设备的高能粒子束加速电压越高，当所述灰度图片中像素点的灰度值越大时，使所述高能粒子束光刻设备的高能粒子束加速电压越低。高能粒子束加速电压越高，发射出的高能粒子束的动能越高，因而在相同的时间内，能够雕刻掉更多的材料，得到更深的材料沟壑。
或者，高能粒子束光刻设备根据所述灰度图片中像素点的灰度值，获取所述灰度图片中各像素点对应的高能粒子束作用时间，当所述灰度图片中像素点的灰度值越小时，使所述高能粒子束光刻设备的高能粒子束作用时间越长，当所述灰度图片中像素点的灰度值越大时，使所述高能粒子束光刻设备的高能粒子束作用时间越短。高能粒子束作用时间越长，在其他控制条件不变的情况下，也能够雕刻掉更多的材料，得到更深的材料沟壑。
或者，高能粒子束光刻设备获取所述灰度图片中所有像素点的灰度均值，当所述灰度均值越小时，使所述高能粒子束光刻设备的所述高能粒子束加速电压越高，并根据所述灰度图片中像素点的灰度值，获取在所述高能粒子束加速电压不变的情况下所述灰度图片中各像素点对应的高能粒子束作用时间，当所述灰度图片中像素点的灰度值越小时，使所述高能粒子束光刻设备的高能粒子束作用时间越长，当所诉灰度图片中像素点的灰度值越大时，使所述高能粒子束光刻设备的高能粒子束作用时间越短。通过高能粒子束加速电压与高能粒子束作用时间的配合，能够加快半导体器件的制作过程，提高制作效率。
S104：在目标基材上依次制作相应的每一层所述材料层，并分别根据所述灰度图片中各像素点对应的高能粒子束加工参数，控制高能粒子束光刻设备发射高能粒子束并作用于所述目标基材上相应的材料层，雕刻所述集成电路子版图对应的图案至所述目标基材上相应的材料层，得到所述目标半导体器件。
在一个可选的实施例中，所述材料层为预先加工好的材料层，通过控制机械设备在目标基材上依次放置相应的每一层所述材料层。
在另一个可选的实施例中，所述材料层为通过控制高能粒子束光刻设备沉积的材料层，具体地，请参阅图2，所述在目标基材上依次制作相应的每一层所述材料层包括步骤 S1041～S1042，如下：
S1041：获取所述材料层对应的材料气体和所述材料层在所述目标基材上对应的沉积区域。
所述材料气体可以为一种气体或多种气体，根据材料层的差异性而不同。
在某些实施例中，为了使高能粒子束能够在材料层上雕刻出更好地图形效果，每一层材料层中包括多种材料，例如，在单晶硅的表面先镀上一层氧化硅，再在氧化硅的表面镀一层钽，那么相应的在制备这样的材料层时也需要多种材料气体。
S1042：控制所述高能粒子束光刻设备在所述沉积区域喷射所述材料气体，使所述材料气体分解后沉积在所述沉积区域，完成所述材料层的制作。
由于高能粒子束能分解金属蒸汽或气相绝缘材料等，因而通过所述高能粒子束光刻设备中的气体喷射装置在所述沉积区域喷射所述材料气体，同时发射高能粒子束分解材料气体，使分解后的材料气体沉积在沉积区域，完成材料层的制作。
上述方式通过控制一台高能粒子束光刻设备，就能完成材料层的铺设和图形的雕刻，实现半导体器件的加工，不仅能够减低成本，而且自动化程度更高。
在一个可选的实施例中，每在目标基材上制作完一层所述材料层后，高能粒子束光刻设备还可以根据预设的优化厚度范围和/或预设的优化平整度范围，控制所述高能粒子束对所述材料层进行打磨，使所述材料层的当前厚度和/或当前平整度分别在所述预设的优化厚度范围和预设的优化平整度范围之内，从而进一步提高后续的雕刻效果，优化半导体器件的加工。
可选的，所述预设的优化厚度范围为1nm至500nm，所述预设的优化平整度范围为0.5nm～5nm。
在另一个可选的实施例中，由于不同器件的性质和用途的不同，因而对于雕刻的加工精度要求不同，在控制高能粒子束光刻设备发射高能粒子束并作用于目标基材上相应的材料层之前，高能粒子束光刻设备可以根据预设的雕刻尺寸阈值，控制电磁透镜进行所述高能粒子束微缩，使所述高能粒子束雕刻像素点尺寸小于所述雕刻尺寸阈值。
本申请实施例中，通过获取目标半导体器件对应的集成电路版图；其中，所述集成电路版图包括若干层集成电路子版图，每一层集成电路子版图分别对应所述目标半导体器件一层或多层材料层的图案；将若干层所述集成电路子版图分别转化为预设格式的灰度图片；根据预设的高能粒子束加工参数与灰度值之间的对应关系，获取所述灰度图片中各像素点对应的高能粒子束加工参数；在目标基材上依次制作相应的每一层所述材料层，并分别根据所述灰度图片中各像素点对应的高能粒子束加工参数，控制高能粒子束光刻设备发射高能粒子束并作用于所述目标基材上相应的材料层，雕刻所述集成电路子版图对应的图案至所述目标基材上相应的材料层，得到所述目标半导体器件，使得不需要制作多张掩膜版，就可以直接根据 集成电路子版图对应的灰度图片中各像素点的灰度值，自动调节高能粒子束加工参数完成图案雕刻，得到半导体器件，这种方式能够大幅节约成本，提高雕刻精度，而且可以灵活地修改集成电路版图，提高加工效率。
为提高半导体器件的加工效率，请参阅图3，其为本申请另一个实施例提供的半导体器件的加工控制方法的流程示意图，包括步骤S201～S207，其中步骤S201～S202，S206分别与步骤S101～S102，S103相同，具体如下：
S201：获取目标半导体器件对应的集成电路版图；其中，所述集成电路版图包括若干层集成电路子版图，每一层集成电路子版图分别对应所述目标半导体器件一层或多层材料层的图案。
S202：将若干层所述集成电路子版图分别转化为预设格式的灰度图片。
S203：获取每层所述集成电路子版图对应的灰度图片中的目标像素点以及所述目标像素点在所述灰度图片中的坐标；其中，所述目标像素点为灰度值低于预设阈值的像素点。
在集成电路子版图对应的灰度图片中可能存在某些目标像素点的灰度值低于预设阈值，从而表明对应的材料层中目标像素点的坐标处需要被高能粒子束穿透。
所述预设阈值与预设的高能粒子束加工参数与灰度值之间的对应关系相关，可以根据实际情况进行设定，在此不进行限定。
请参阅图4，其为本申请一个实施例提供四个MOS管并联集成电路版图对应的灰度图片的示意图。图4中集成电路版图包括有源层、多晶硅栅极层、金属层和在有源层、多晶硅栅极层上的绝缘层(图未示出)，在金属层、绝缘层以及多晶硅栅极层中就存在灰度值低于预设阈值的目标像素点。
S204：当第i至j层所述集成电路子版图对应的灰度图片中均存在坐标相同的目标像素点时，得到第i至j层所述集成电路子版图对应的灰度图片中的待调整像素点。
若第i至j层所述集成电路子版图对应的灰度图片中均存在坐标相同的目标像素点，那么这些目标像素点就是待调整像素点，通过调整待调整像素点的灰度值，从而使得在雕刻对应的材料层时，不在待调整像素点的坐标处进行雕刻。
其中，所述集成电路子版图共有n层，1≤i＜j≤n。
S205：根据预设的调整策略重新设置第i至j层所述集成电路子版图对应的灰度图片中的待调整像素点的灰度值。
在一个可选的实施例中，将第i至j层所述集成电路子版图对应的灰度图片中所述待调整像素点的灰度值设置为最高值，即255，从而使得在雕刻所述第i至j层所述集成电路子版图 对应的图案时，不会雕刻到所述待调整像素点组成的图案。
在另一个可选的实施例中，高能粒子束光刻设备先获取最低的高能粒子束加工参数对应的第一灰度值。
高能粒子束加工参数包括高能粒子束加速电压和/或高能粒子束作用时间，在本申请实施例中，高能粒子束加速电压为0或高能粒子束作用时间为0时对应的灰度值为第一灰度值。
由于高能粒子束加工参数与灰度值之间对应关系的不同，第一灰度值也会不同，并不一定是255，对于其具体数值在此不进行限定。
之后，高能粒子束光刻设备将所述第i至j层所述集成电路子版图对应的灰度图片中，所述待调整像素点的灰度值均设置为所述第一灰度值，从而也能够使得在雕刻所述第i至j层所述集成电路子版图对应的图案时，不会雕刻到所述待调整像素点组成的图案。
S206：根据预设的高能粒子束加工参数与灰度值之间的对应关系，获取所述灰度图片中各像素点对应的高能粒子束加工参数。
S207：在目标基材上依次制作相应的每一层所述材料层，并分别根据所述灰度图片中各像素点对应的高能粒子束加工参数，控制高能粒子束光刻设备发射高能粒子束并作用于所述目标基材上相应的材料层，雕刻所述集成电路子版图对应的图案至所述目标基材上相应的材料层，得到所述目标半导体器件。
步骤S207与步骤S104的执行方式是相同的，都是每设置一层材料层，在该材料层上完成集成电路子版图对应的图案的雕刻，最终得到目标半导体器件。
但是，由于在本实施例中，在雕刻第i至j层材料层时，均没有雕刻待调整像素点组成的图案，因此本步骤与步骤S104存在区别，请参阅图5，步骤S207包括步骤S2071～S2072，具体区别过程如下：
S2071：在所述目标基材上依次制作第i至j层材料层，分别根据所述第i至j层所述集成电路子版图对应的灰度图片中各像素点对应的高能粒子束加工参数，控制所述高能粒子束光刻设备发射高能粒子束作用于第i至j层材料层上，雕刻所述第i至j层所述集成电路子版图对应的除所述待调整像素点组成的图案以外的所有图案至相应的第i至j层材料层。
高能粒子束光刻设备每铺设一层材料层(第i至j层)后，根据该层集成电路子版图对应的灰度图片中各像素点对应的高能粒子束加工参数，控制所述高能粒子束光刻设备发射高能粒子束作用于该层材料层上，雕刻该层集成电路子版图对应的除所述待调整像素点组成的图案以外的所有图案至该层材料层。
对于第i至j层材料层以外的层次的雕刻，与步骤S104中的雕刻无差异，不再赘述。
S2072：根据所述待调整像素点的坐标，控制所述高能粒子束光刻设备发射高能粒子束作 用于第j层材料层中所述待调整像素点的坐标处，在所述待调整像素点的坐标处穿透第i至j层材料层。
高能粒子束光刻设备在雕刻完第j层集成电路子版图对应的除所述待调整像素点组成的图案以外的所有图案至第j层材料层后，再根据所述待调整像素点的坐标，控制所述高能粒子束光刻设备发射高能粒子束作用于第j层材料层中所述待调整像素点的坐标处，在所述待调整像素点的坐标处穿透第i至j层材料层。
其中，所述穿透每层材料层的高能粒子束加工参数可以根据实验获取并预存储在高能粒子束光刻设备中，根据材料层的标识能够查找到对应的高能粒子束加工参数，从而获取到穿透第i至j层的高能粒子束加工参数。
本实施例中，通过获取每层集成电路子版图对应的灰度图片中的目标像素点以及目标像素点的坐标，从而获取到第i至j层所述集成电路子版图对应的灰度图片中均存在的坐标相同的目标像素点，也即待调整像素点，再通过调整策略重新设置待调整像素点的灰度值，从而使得在雕刻所述第i至j层所述集成电路子版图对应的图案分别至第i至j层材料层时，不会雕刻到待调整像素点组成的图案，最后在雕刻完第j层材料层后，统一根据待调整像素点的坐标，控制所述高能粒子束光刻设备发射高能粒子束作用于第j层材料层中所述待调整像素点的坐标处，在所述待调整像素点的坐标处穿透第i至j层材料层，实现合并雕刻，有效地提高了半导体器件的加工效率。
为进一步提高半导体器件的加工效率，请参阅图6，其为本申请其他实施例提供的半导体器件的加工控制方法的流程示意图，包括步骤S301～S307，其中步骤S301～S304、S306分别与步骤S201～S204，S206相同，具体如下：
S301：获取目标半导体器件对应的集成电路版图；其中，所述集成电路版图包括若干层集成电路子版图，每一层集成电路子版图分别对应所述目标半导体器件一层或多层材料层的图案。
S302：将若干层所述集成电路子版图分别转化为预设格式的灰度图片。
S303：获取每层所述集成电路子版图对应的灰度图片中的目标像素点以及所述目标像素点在所述灰度图片中的坐标；其中，所述目标像素点为灰度值低于预设阈值的像素点。
S304：当第i至j层所述集成电路子版图对应的灰度图片中均存在坐标相同的目标像素点时，得到第i至j层所述集成电路子版图对应的灰度图片中的待调整像素点。
S305：根据预设的调整策略重新设置第i至j层所述集成电路子版图对应的灰度图片中的待调整像素点的灰度值。
步骤S305中预设的调整策略与步骤S205中预设的调整策略的存在不同，具体地：
步骤S305中在设置第i至j-1层所述集成电路子版图对应的灰度图片中所述待调整像素点的灰度值时，与步骤S205相同，区别点在于步骤S305中单独设置第j层所述集成电路子版图对应的灰度图片中所述待调整像素点的灰度值，请参阅图7，步骤S305包括步骤S3051～S3054：
S3051：将第i至j-1层所述集成电路子版图对应的灰度图片中所述待调整像素点的灰度值设置为最高值，或者，获取最低的高能粒子束加工参数对应的第一灰度值，将所述第i至j-1层所述集成电路子版图对应的灰度图片中所述待调整像素点的灰度值设置为所述第一灰度值。
S3052：获取穿透所述第i至j层材料层的目标高能粒子束加工参数。
穿透每层材料层的高能粒子束加工参数可以根据实验获取，并预存储在高能粒子束光刻设备中，根据材料层的标识能够查找到对应的高能粒子束加工参数，从而获取到穿透第i至j层的高能粒子束加工参数。
S3053：根据所述目标高能粒子束加工参数和所述预设的高能粒子束加工参数与灰度值之间的对应关系，获取第二灰度值。
高能粒子束光刻设备根据所述预设的高能粒子束加工参数与灰度值之间的对应关系和目标高能粒子束加工参数，获取到第二灰度值。
S3054：将第j层所述集成电路子版图对应的灰度图片中所述待调整像素点的灰度值设置为所述第二灰度值。
高能粒子束光刻设备将第j层所述集成电路子版图对应的灰度图片中所述待调整像素点的灰度值设置为所述第二灰度值，这就使得在雕刻第j层材料层时，高能粒子束设备若判断某一像素点的灰度值为第二灰度值，则根据第二灰度值对应的目标高能粒子束加工参数，控制高能粒子束作用于在第j层材料层中该像素点的坐标处，进而使得高能粒子束在所述该像素点的坐标处穿透第i至j层材料层。
通过单独设置第j层所述集成电路子版图对应的灰度图片中所述待调整像素点的灰度值，能够使得在雕刻第j层所述集成电路子版图对应的图案时，同时雕刻待调整像素点组成的图案至第i至j层材料层，减少了雕刻步骤，进一步提高加工效率。
S306：根据预设的高能粒子束加工参数与灰度值之间的对应关系，获取所述灰度图片中各像素点对应的高能粒子束加工参数。
S307：在目标基材上依次制作相应的每一层所述材料层，并分别根据所述灰度图片中各像素点对应的高能粒子束加工参数，控制高能粒子束光刻设备发射高能粒子束并作用于所述目标基材上相应的材料层，雕刻所述集成电路子版图对应的图案至所述目标基材上相应的材 料层，得到所述目标半导体器件。
在本申请实施例中，请参阅图8，步骤S307包括步骤S3071～S3072，具体如下：
S3071：在所述目标基材上依次制作第i至j-1层材料层，分别根据所述第i至j-1层所述集成电路子版图对应的灰度图片中各像素点对应的高能粒子束加工参数，控制所述高能粒子束光刻设备发射高能粒子束作用于第i至j-1层材料层上，雕刻所述第i至j-1层所述集成电路子版图对应的除所述待调整像素点组成的图案以外的所有图案至相应的第i至j-1层材料层。
高能粒子束光刻设备每铺设一层材料层(第i至j-1层)后，根据该层集成电路子版图对应的灰度图片中各像素点对应的高能粒子束加工参数，控制所述高能粒子束光刻设备发射高能粒子束作用于该层材料层上，雕刻该层集成电路子版图对应的除所述待调整像素点组成的图案以外的所有图案至该层材料层。
S3072：在所述目标基材上设置第j层材料层，控制所述高能粒子束光刻设备发射高能粒子束作用于第j层材料层上，雕刻所述第j层所述集成电路子版图对应的图案至第j层材料层，并在所述待调整像素点的坐标处穿透所述第j至i层材料层。
由于在第j层集成电路子版图对应的灰度图片中，待调整像素点的灰度值设置为了第二灰度值，因而高能粒子束光刻设备在雕刻第j层材料层中待调整像素点的坐标处时，会根据第二灰度值对应的目标高能粒子束加工参数，发射高能粒子束作用于待调整像素点的坐标处，从而使得在坐标处高能粒子束穿透所述j至i层材料层。
对于第i至j层材料层以外的层次的雕刻，与步骤S104中的雕刻无差异，不再赘述。
本实施例中，通过获取每层集成电路子版图对应的灰度图片中的目标像素点以及目标像素点的坐标，从而获取到第i至j层所述集成电路子版图对应的灰度图片中均存在的坐标相同的目标像素点，也即待调整像素点，再通过调整策略分别重新设置第i至j-1层待调整像素点的灰度值和第j层待调整像素点的灰度值，从而使得在雕刻所述第i至j-1层所述集成电路子版图对应的图案分别至第i至j-1层材料层时，不会雕刻到待调整像素点组成的图案，最后在雕刻完第j层材料层时，根据待调整像素点的坐标和灰度值，控制所述高能粒子束光刻设备发射高能粒子束作用于所述待调整像素点的坐标处，在所述待调整像素点的坐标处穿透第i至j层材料层，实现第j层集成电路子版图对应的图案与第i至j-1层中待调整像素点组成的图案的合并雕刻，进一步提高了半导体器件的加工效率。
请参见图9，其为本申请一个实施例提供的高能粒子束光刻设备的结构示意图。如图9示，所述高能粒子束光刻设备9可以包括：处理器90、存储器91以及存储在所述存储器91并可以在所述处理器90上运行的计算机程序92，例如：半导体器件的加工控制程序；所述处理器90执行所述计算机程序92时实现上述各方法实施例中的步骤，例如图1所示的步骤 S101至S104。
其中，所述处理器90可以包括一个或多个处理核心。处理器90利用各种接口和线路连接所述高能粒子束光刻设备9内的各个部分，通过运行或执行存储在存储器91内的指令、程序、代码集或指令集，以及调用存储器91内的数据，执行高能粒子束光刻设备9的各种功能和处理数据，可选的，处理器90可以采用数字信号处理(Digital Signal Processing,DSP)、现场可编程门阵列(Field-Programmable Gate Array，FPGA)、可编程逻辑阵列(Programble Logic Array，PLA)中的至少一个硬件形式来实现。处理器90可集成中央处理器(Central Processing Unit，CPU)、图像处理器(Graphics Processing Unit，GPU)和调制解调器等中的一种或几种的组合。其中，CPU主要处理操作系统、用户界面和应用程序等；GPU用于负责触摸显示屏所需要显示的内容的渲染和绘制；调制解调器用于处理无线通信。可以理解的是，上述调制解调器也可以不集成到处理器90中，单独通过一块芯片进行实现。
其中，存储器91可以包括随机存储器(Random Access Memory，RAM)，也可以包括只读存储器(Read-Only Memory)。可选的，该存储器91包括非瞬时性计算机可读介质(non-transitory computer-readable storage medium)。存储器91可用于存储指令、程序、代码、代码集或指令集。存储器91可包括存储程序区和存储数据区，其中，存储程序区可存储用于实现操作系统的指令、用于至少一个功能的指令(比如触控指令等)、用于实现上述各个方法实施例的指令等；存储数据区可存储上面各个方法实施例中涉及到的数据等。存储器91可选的还可以是至少一个位于远离前述处理器90的存储装置。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述或记载的部分，可以参见其它实施例的相关描述。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
本发明并不局限于上述实施方式，如果对本发明的各种改动或变形不脱离本发明的精神和范围，倘若这些改动和变形属于本发明的权利要求和等同技术范围之内，则本发明也意图包含这些改动和变形。

Claims (10)

  1. 一种半导体器件的加工控制方法，其特征在于，包括步骤：
    获取目标半导体器件对应的集成电路版图；其中，所述集成电路版图包括若干层集成电路子版图，每一层集成电路子版图分别对应所述目标半导体器件一层或多层材料层的图案；
    将若干层所述集成电路子版图分别转化为预设格式的灰度图片；
    根据预设的高能粒子束加工参数与灰度值之间的对应关系，获取所述灰度图片中各像素点对应的高能粒子束加工参数；
    在目标基材上依次制作相应的每一层所述材料层，并分别根据所述灰度图片中各像素点对应的高能粒子束加工参数，控制高能粒子束光刻设备发射高能粒子束并作用于所述目标基材上相应的材料层，雕刻所述集成电路子版图对应的图案至所述目标基材上相应的材料层，得到所述目标半导体器件。
  2. 根据权利要求1所述的半导体器件的加工控制方法，其特征在于，
    所述高能粒子束加工参数包括高能粒子束加速电压和/或高能粒子束作用时间，
    根据预设的高能粒子束加工参数与灰度值之间的对应关系，获取所述灰度图片中各像素点对应的高能粒子束加工参数，包括步骤：
    根据所述灰度图片中像素点的灰度值，获取所述灰度图片中各像素点对应的高能粒子束加速电压，当所述灰度图片中像素点的灰度值越小时，使所述高能粒子束光刻设备的高能粒子束加速电压越高，当所述灰度图片中像素点的灰度值越大时，使所述高能粒子束光刻设备的高能粒子束加速电压越低；
    或，
    根据所述灰度图片中像素点的灰度值，获取所述灰度图片中各像素点对应的高能粒子束作用时间，当所述灰度图片中像素点的灰度值越小时，使所述高能粒子束光刻设备的高能粒子束作用时间越长，当所述灰度图片中像素点的灰度值越大时，使所述高能粒子束光刻设备的高能粒子束作用时间越短；
    或，
    获取所述灰度图片中所有像素点的灰度均值，当所述灰度均值越小时，使所述高能粒子束光刻设备的所述高能粒子束加速电压越高，并根据所述灰度图片中像素点的灰度值，获取在所述高能粒子束加速电压不变的情况下所述灰度图片中各像素点对应的高能粒子束作用时间，当所述灰度图片中像素点的灰度值越小时，使所述高能粒子束光刻设备的高能粒子束作用时间越长，当所诉灰度图片中像素点的灰度值越大时，使所述高能粒子束光刻设备的高能 粒子束作用时间越短。
  3. 根据权利要求1所述的半导体器件的加工控制方法，其特征在于，所述将若干层所述集成电路子版图分别转化为预设格式的灰度图片之后，包括步骤：
    获取每层所述集成电路子版图对应的灰度图片中的目标像素点以及所述目标像素点在所述灰度图片中的坐标；其中，所述目标像素点为灰度值低于预设阈值的像素点；
    当第i至j层所述集成电路子版图对应的灰度图片中均存在坐标相同的目标像素点时，得到第i至j层所述集成电路子版图对应的灰度图片中的待调整像素点；
    根据预设的调整策略重新设置第i至j层所述集成电路子版图对应的灰度图片中的待调整像素点的灰度值。
  4. 根据权利要求3所述的半导体器件的加工控制方法，其特征在于，所述根据预设的调整策略重新设置第i至j层所述集成电路子版图对应的灰度图片中的待调整像素点的灰度值，包括步骤：
    将第i至j层所述集成电路子版图对应的灰度图片中所述待调整像素点的灰度值设置为最高值；
    或者，
    获取最低的高能粒子束加工参数对应的第一灰度值；
    将所述第i至j层所述集成电路子版图对应的灰度图片中所述待调整像素点的灰度值设置为所述第一灰度值。
  5. 根据权利要求4所述的半导体器件的加工控制方法，其特征在于，所述在目标基材上依次制作相应的每一层所述材料层，并分别根据所述灰度图片中各像素点对应的高能粒子束加工参数，控制高能粒子束光刻设备发射高能粒子束并作用于所述目标基材上相应的材料层，雕刻所述集成电路子版图对应的图案至所述目标基材上相应的材料层，得到所述目标半导体器件，包括步骤：
    在所述目标基材上依次制作第i至j层材料层，分别根据所述第i至j层所述集成电路子版图对应的灰度图片中各像素点对应的高能粒子束加工参数，控制所述高能粒子束光刻设备发射高能粒子束作用于第i至j层材料层上，雕刻所述第i至j层所述集成电路子版图对应的除所述待调整像素点组成的图案以外的所有图案至相应的第i至j层材料层；
    根据所述待调整像素点的坐标，控制所述高能粒子束光刻设备发射高能粒子束作用于第j层材料层中所述待调整像素点的坐标处，在所述待调整像素点的坐标处穿透第i至j层材料层。
  6. 根据权利要求3所述的半导体器件的加工控制方法，其特征在于，所述根据预设的调 整策略重新设置第i至j层所述集成电路子版图对应的灰度图片中的待调整像素点的灰度值，包括步骤：
    将第i至j-1层所述集成电路子版图对应的灰度图片中所述待调整像素点的灰度值设置为最高值，或者，获取最低的高能粒子束加工参数对应的第一灰度值，将所述第i至j-1层所述集成电路子版图对应的灰度图片中所述待调整像素点的灰度值设置为所述第一灰度值；
    获取穿透所述第i至j层材料层的目标高能粒子束加工参数；
    根据所述目标高能粒子束加工参数和所述预设的高能粒子束加工参数与灰度值之间的对应关系，获取第二灰度值；
    将第j层所述集成电路子版图对应的灰度图片中所述待调整像素点的灰度值设置为所述第二灰度值。
  7. 根据权利要求6所述的半导体器件的加工控制方法，其特征在于，所述在目标基材上依次制作相应的每一层所述材料层，并分别根据所述灰度图片中各像素点对应的高能粒子束加工参数，控制高能粒子束光刻设备发射高能粒子束并作用于所述目标基材上相应的材料层，雕刻所述集成电路子版图对应的图案至所述目标基材上相应的材料层，得到所述目标半导体器件，包括步骤：
    在所述目标基材上依次制作第i至j-1层材料层，分别根据所述第i至j-1层所述集成电路子版图对应的灰度图片中各像素点对应的高能粒子束加工参数，控制所述高能粒子束光刻设备发射高能粒子束作用于第i至j-1层材料层上，雕刻所述第i至j-1层所述集成电路子版图对应的除所述待调整像素点组成的图案以外的所有图案至相应的第i至j-1层材料层；
    在所述目标基材上设置第j层材料层，控制所述高能粒子束光刻设备发射高能粒子束作用于第j层材料层上，雕刻所述第j层所述集成电路子版图对应的图案至第j层材料层，并在所述待调整像素点的坐标处穿透所述第j至i层材料层。
  8. 根据权利要求1所述的半导体器件的加工控制方法，其特征在于，所述在目标基材上依次制作相应的每一层所述材料层，包括步骤：
    获取所述材料层对应的材料气体和所述材料层在所述目标基材上对应的沉积区域；
    控制所述高能粒子束光刻设备在所述沉积区域喷射所述材料气体，使所述材料气体分解后沉积在所述沉积区域，完成所述材料层的制作。
  9. 根据权利要求1所述的半导体器件的加工控制方法，其特征在于，所述在目标基材上依次制作相应的每一层所述材料层，包括步骤：
    根据预设的优化厚度范围和/或预设的优化平整度范围，控制所述高能粒子束对所述材料层进行打磨，使所述材料层的当前厚度和/或当前平整度分别在所述预设的优化厚度范围和预 设的优化平整度范围之内。
  10. 一种高能粒子束光刻设备，其特征在于，包括：处理器、存储器以及存储在所述存储器中并可在所述处理器上运行的计算机程序，其特征在于，所述处理器执行所述计算机程序时实现如权利要求1至9任一项所述方法的步骤。
PCT/CN2022/124110 2022-10-09 2022-10-09 半导体器件的加工控制方法及高能粒子束光刻设备 WO2024077416A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/124110 WO2024077416A1 (zh) 2022-10-09 2022-10-09 半导体器件的加工控制方法及高能粒子束光刻设备

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/124110 WO2024077416A1 (zh) 2022-10-09 2022-10-09 半导体器件的加工控制方法及高能粒子束光刻设备

Publications (1)

Publication Number Publication Date
WO2024077416A1 true WO2024077416A1 (zh) 2024-04-18

Family

ID=90668484

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/124110 WO2024077416A1 (zh) 2022-10-09 2022-10-09 半导体器件的加工控制方法及高能粒子束光刻设备

Country Status (1)

Country Link
WO (1) WO2024077416A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110033441A (zh) * 2019-03-22 2019-07-19 无锡中微掩模电子有限公司 一种无损、高精度掩模图形的分层提取方法
US20210327678A1 (en) * 2018-09-19 2021-10-21 Asml Netherlands B.V. Particle beam apparatus, defect repair method, lithographic exposure process and lithographic system
CN114089607A (zh) * 2021-11-29 2022-02-25 上海华力微电子有限公司 一种深度加速集成电路版图光刻工艺热点检查的方法
CN114927410A (zh) * 2022-02-24 2022-08-19 珠海洪启科技合伙企业(有限合伙) 半导体器件的加工控制方法、装置及高能粒子束光刻设备

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210327678A1 (en) * 2018-09-19 2021-10-21 Asml Netherlands B.V. Particle beam apparatus, defect repair method, lithographic exposure process and lithographic system
CN110033441A (zh) * 2019-03-22 2019-07-19 无锡中微掩模电子有限公司 一种无损、高精度掩模图形的分层提取方法
CN114089607A (zh) * 2021-11-29 2022-02-25 上海华力微电子有限公司 一种深度加速集成电路版图光刻工艺热点检查的方法
CN114927410A (zh) * 2022-02-24 2022-08-19 珠海洪启科技合伙企业(有限合伙) 半导体器件的加工控制方法、装置及高能粒子束光刻设备

Similar Documents

Publication Publication Date Title
WO2022252707A1 (zh) 半导体器件的加工控制方法、装置及高能粒子束光刻设备
US7562334B2 (en) Method for manufacturing a photomask
US20210292883A1 (en) Method and device for controlling stretching of mask, and stretching system
US9430607B2 (en) Electron beam drawing apparatus, electron beam drawing method, and storage medium
WO2011080873A1 (ja) パターン計測条件設定装置
US20140065548A1 (en) Lithography apparatus and article manufacturing method using same
TW201421171A (zh) 決定遮罩圖案及曝光條件的方法、儲存媒體、和電腦
US20170257540A1 (en) Image measurement system and controller
WO2024077416A1 (zh) 半导体器件的加工控制方法及高能粒子束光刻设备
WO2024077586A1 (zh) 半导体器件的加工控制方法及高能粒子束光刻设备
WO2024087153A1 (zh) 半导体器件的质量改善方法、装置及高能粒子束光刻设备
WO2024092550A1 (zh) 半导体器件的质量改善方法、装置及高能粒子束光刻设备
WO2023202002A1 (zh) 半导体器件的加工控制方法及高能粒子束光刻设备
US20070130560A1 (en) Method of determining photo mask, method of manufacturing semiconductor device, and computer program product
CN105223773B (zh) 一种光掩模图案透光强度修正的方法
JP2013183048A (ja) 電子線照射量決定方法
US20190179226A1 (en) Photolithography plate and mask correction method
JP2009271174A (ja) マスクパターン作成方法及びパターン形成方法
JP2010079063A (ja) パターン形成不良領域算出方法およびパターンレイアウト評価方法
US8539392B2 (en) Method for compensating proximity effects of particle beam lithography processes
KR20080018039A (ko) 오프 그리드 방지를 위한 ｏｐｃ 처리방법
KR20190045942A (ko) 디포커스 검출 방법
US11599017B2 (en) Optical proximity correction method and method of fabricating mask including the same
CN115223883B (zh) 应用于关键尺寸量测的调光系统及调光方法
WO2024065980A1 (zh) 检测方法及装置、存储介质及电子设备