WO2024084994A1 - プリント配線板 - Google Patents

プリント配線板 Download PDF

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Publication number
WO2024084994A1
WO2024084994A1 PCT/JP2023/036476 JP2023036476W WO2024084994A1 WO 2024084994 A1 WO2024084994 A1 WO 2024084994A1 JP 2023036476 W JP2023036476 W JP 2023036476W WO 2024084994 A1 WO2024084994 A1 WO 2024084994A1
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WO
WIPO (PCT)
Prior art keywords
copper layer
hole
layer
printed wiring
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/036476
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English (en)
French (fr)
Japanese (ja)
Inventor
宏介 三浦
耕司 新田
将一郎 酒井
良雄 岡
隆 春日
賀人 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Sumitomo Electric Printed Circuits Inc
Original Assignee
Sumitomo Electric Industries Ltd
Sumitomo Electric Printed Circuits Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd, Sumitomo Electric Printed Circuits Inc filed Critical Sumitomo Electric Industries Ltd
Priority to CN202380070350.2A priority Critical patent/CN119999344A/zh
Priority to JP2024551483A priority patent/JPWO2024084994A1/ja
Publication of WO2024084994A1 publication Critical patent/WO2024084994A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Definitions

  • Patent Document 1 JP2017-037990A (Patent Document 1) describes a printed wiring board.
  • the printed wiring board described in Patent Document 1 has an inner resin layer, an inner circuit, an organic adhesive layer, an organic insulating resin layer, an outer copper layer, and an outer circuit.
  • the inner resin layer has a first main surface.
  • the inner circuit is disposed on the first main surface.
  • the organic adhesive layer is disposed on the first main surface so as to cover the inner circuit.
  • the organic insulating resin layer has a second main surface and a third main surface. The third main surface is the opposite surface to the second main surface.
  • the organic insulating resin layer is disposed on the organic adhesive layer so that the second main surface faces the organic adhesive layer. Through holes are formed in the organic adhesive layer and the organic insulating resin layer to expose the inner circuit.
  • the outer copper layer is a copper layer formed by electroless plating.
  • the outer copper layer is disposed on the inner circuit exposed from the through hole, on the inner wall surface of the through hole, and on the third main surface surrounding the through hole.
  • the outer circuit is a copper layer formed by electrolytic plating.
  • the outer circuit is disposed on the outer copper layer. In this way, the outer circuit and the inner circuit are electrically connected in the printed wiring board described in Patent Document 1.
  • the printed wiring board of the present disclosure comprises an insulating layer having a first main surface and a second main surface, a first copper layer disposed on the first main surface, a second copper layer disposed on the second main surface, and a third copper layer, a through hole is formed in the insulating layer and the first copper layer leading to the second copper layer, the third copper layer is disposed on the second copper layer inside the through hole, on the inner wall surface of the through hole, and on the first copper layer around the through hole, a single copper layer is disposed on the inner wall surface of the through hole, and the single copper layer is the third copper layer.
  • FIG. 1 is a cross-sectional view of a printed wiring board 100 .
  • FIG. 2 is a diagram showing the manufacturing process of the printed wiring board 100.
  • FIG. 3 is a cross-sectional view illustrating the preparation step S1.
  • FIG. 4 is a cross-sectional view illustrating the first etching step S2.
  • FIG. 5 is a cross-sectional view illustrating the hole making step S3.
  • FIG. 6 is a cross-sectional view illustrating the resist pattern forming step S5.
  • FIG. 7 is a cross-sectional view illustrating the electrolytic plating step S6.
  • FIG. 8 is a cross-sectional view illustrating the resist pattern removing step S7.
  • FIG. 9 is a cross-sectional view of printed wiring board 100A.
  • FIG. 1 is a cross-sectional view of a printed wiring board 100 .
  • FIG. 2 is a diagram showing the manufacturing process of the printed wiring board 100.
  • FIG. 3 is a cross-sectional view illustrating the preparation
  • FIG. 10 is a cross-sectional view of the printed wiring board 200.
  • FIG. 11 is a manufacturing process diagram of the printed wiring board 200.
  • FIG. 12 is a cross-sectional view illustrating the preparation step S11.
  • FIG. 13 is a cross-sectional view illustrating the first hole making step S12.
  • FIG. 14 is a cross-sectional view illustrating the first resist pattern forming step S13.
  • FIG. 15 is a cross-sectional view illustrating the first electrolytic plating step S14.
  • FIG. 16 is a cross-sectional view illustrating the first resist pattern removing step S15.
  • FIG. 17 is a cross-sectional view illustrating the first etching step S16.
  • FIG. 18 is a cross-sectional view illustrating the insulating layer attaching step S17.
  • FIG. 12 is a cross-sectional view illustrating the preparation step S11.
  • FIG. 13 is a cross-sectional view illustrating the first hole making step S12.
  • FIG. 14 is a cross
  • FIG. 19 is a cross-sectional view illustrating the second hole making step S18.
  • FIG. 20 is a cross-sectional view illustrating the second resist pattern forming step S19.
  • FIG. 21 is a cross-sectional view illustrating the second electrolytic plating step S20.
  • FIG. 22 is a cross-sectional view illustrating the second resist pattern removing step S21.
  • etching may be performed to remove foreign matter and oxide films (hereinafter referred to as foreign matter, etc.) on the surface of the inner circuit.
  • This etching must be a weak process to avoid excessive erosion of the inner circuit, and foreign matter, etc., remains on the surface of the inner circuit. If foreign matter, etc., remains on the surface of the inner circuit, the adhesion between the inner circuit and the outer copper layer decreases, and the outer circuit together with the outer copper layer may peel off from the inner circuit, leading to a break in the wiring.
  • a blind via hole is a hole that electrically or physically connects the outermost circuit of a printed wiring board to one or more inner layer circuits by copper plating or the like.
  • a blind via hole does not penetrate all the way to the outermost circuit on the opposite side.
  • a printed wiring board comprises an insulating layer having a first main surface and a second main surface, a first copper layer disposed on the first main surface, a second copper layer disposed on the second main surface, and a third copper layer, wherein a through hole is formed in the insulating layer and the first copper layer leading to the second copper layer, and the third copper layer is disposed on the second copper layer inside the through hole, on the inner wall surface of the through hole and on the first copper layer around the through hole, and a single copper layer is disposed on the inner wall surface of the through hole, the single copper layer being the third copper layer.
  • the printed wiring board (1) above makes it possible to prevent breaks in blind via holes.
  • the thickness of the third copper layer on the first copper layer may be at least 0.4 times the thickness of the insulating layer and at most 0.6 times the minimum width of the through hole on the first main surface.
  • the printed wiring board (2) above makes it possible to easily connect the third copper layer formed on the first copper layer around the through hole and the third copper layer formed on the second copper layer exposed from the through hole.
  • the thickness of the third copper layer on the first copper layer may be 0.8 times or more the thickness of the insulating layer and 0.45 times or less the minimum width of the through hole on the first main surface.
  • the printed wiring board (3) above makes it easier to connect the third copper layer formed on the first copper layer around the through hole and the third copper layer formed on the second copper layer exposed from the through hole.
  • the concentration of palladium in the region of the third copper layer extending from the interface between the insulating layer and the third copper layer to a depth of 10 nm and in the region of the third copper layer extending from the interface between the second copper layer and the third copper layer to a depth of 10 nm may be 0.5 mass percent or less.
  • the third copper layer may be an electrolytically plated copper layer.
  • a printed wiring board includes a first insulating layer having a first main surface, a first copper layer disposed on the first main surface, an adhesive layer disposed on the first main surface so as to cover the first copper layer, a second insulating layer having a second main surface and a third main surface and disposed on the adhesive layer so that the second main surface faces the adhesive layer, a second copper layer disposed on the third main surface, and a third copper layer, wherein a through hole leading to the first copper layer is formed in the second insulating layer, the second copper layer, and the adhesive layer, and the third copper layer is disposed on the first copper layer inside the through hole, on the inner wall surface of the through hole, and on the second copper layer around the through hole, and a single copper layer is disposed on the inner wall surface of the through hole, and the single copper layer is the third copper layer.
  • the printed wiring board (6) above makes it possible to prevent breaks in blind via holes.
  • the thickness of the third copper layer on the second copper layer may be 0.4 times or more the sum of the thickness of the second insulating layer and the thickness of the adhesive layer between the first copper layer and the second insulating layer, and may be 0.6 times or less the minimum width of the through hole on the third main surface.
  • the printed wiring board (7) above makes it possible to easily connect the third copper layer formed on the second copper layer around the through hole and the third copper layer formed on the first copper layer exposed from the through hole.
  • the thickness of the third copper layer on the second copper layer may be 0.8 times or more the sum of the thickness of the second insulating layer and the thickness of the adhesive layer between the first copper layer and the second insulating layer, and may be 0.45 times or less the minimum width of the through hole on the third main surface.
  • the printed wiring board (8) above makes it easier to connect the third copper layer formed on the second copper layer around the through hole and the third copper layer formed on the first copper layer exposed from the through hole.
  • the concentration of palladium in the region of the third copper layer extending from the interface between the second insulating layer and the third copper layer to a depth of 10 nm and in the region of the third copper layer extending from the interface between the first copper layer and the third copper layer to a depth of 10 nm may be 0.5 mass percent or less.
  • the third copper layer may be an electrolytically plated copper layer.
  • the printed wiring board according to the first embodiment is designated as a printed wiring board 100.
  • FIG. 1 is a cross-sectional view of a printed wiring board 100. As shown in FIG. 1, the printed wiring board 100 has an insulating layer 10, a first copper layer 11, a second copper layer 12, and a third copper layer 20.
  • the material of the insulating layer 10 has electrical insulation and flexibility.
  • the material of the insulating layer 10 is, for example, polyimide. However, the material of the insulating layer 10 is not limited to this.
  • the insulating layer 10 has a first main surface 10a and a second main surface 10b.
  • the first main surface 10a and the second main surface 10b are surfaces perpendicular to the thickness direction of the insulating layer 10 and constitute the front and back surfaces of the insulating layer 10.
  • the second main surface 10b is the surface opposite to the first main surface 10a.
  • the thickness of the insulating layer 10 is defined as thickness T1.
  • the thickness T1 is, for example, 12.5 ⁇ m or more and 100 ⁇ m or less.
  • the thickness T1 is the average value measured at any 10 points on the cross-sectional photograph.
  • the first copper layer 11 is made of copper or a copper alloy.
  • the first copper layer 11 is disposed on the first main surface 10a.
  • the second copper layer 12 is made of copper or a copper alloy.
  • the second copper layer 12 is disposed on the second main surface 10b.
  • Through holes 13 are formed in the insulating layer 10 and the first copper layer 11.
  • the through holes 13 penetrate the insulating layer 10 and the first copper layer 11 in the thickness direction.
  • the shape of the through holes 13 in a plan view is, for example, circular. However, the planar shape of the through holes 13 is not limited to this.
  • the opening diameter of the through holes 13, for example, becomes smaller as it approaches the second main surface 10b.
  • the width of the through holes 13 on the first main surface 10a is width W1.
  • Width W1 is, for example, 25 ⁇ m or more and 250 ⁇ m or less.
  • the third copper layer 20 is made of copper or a copper alloy.
  • the third copper layer 20 may be a copper layer formed by electrolytic plating (electrolytically plated copper layer).
  • a single copper layer is disposed on the inner wall surface of the through hole 13.
  • the single copper layer referred to here is the third copper layer 20.
  • a single copper layer is disposed on the inner wall surface of the through hole 13 means that two or more copper layers are not continuously laminated on the inner wall surface of the through hole 13.
  • a resin layer or an adhesive layer for example, is formed on the surface opposite the inner wall surface of the third copper layer 20.
  • a metal layer other than copper is laminated on the surface opposite the inner wall surface of the third copper layer 20.
  • the third copper layer 20 is disposed on the second copper layer 12 exposed inside the through hole 13, on the inner wall surface of the through hole 13, and on the first copper layer 11 around the through hole 13.
  • the third copper layer 20 is also disposed on the first copper layer 11 other than the periphery of the through hole 13.
  • the third copper layer 20 constitutes the wiring of the printed wiring board 100.
  • the wiring of the printed wiring board 100 is electrically connected to the second copper layer 12 exposed inside the through hole 13.
  • the thickness of the third copper layer 20 on the first copper layer 11 is defined as thickness T2.
  • Thickness T2 may be 0.4 times or more than thickness T1 and 0.6 times or less than width W1. Thickness T2 is the average value of measurements taken at any 10 points on the cross-sectional photograph. Thickness T2 may be 0.8 times or more than thickness T1 and 0.45 times or less than width W1. Thickness T2 is, for example, 10 ⁇ m or more and 45 ⁇ m or less.
  • Width W1 here is the minimum width of the through hole 13 on the first main surface 10a. "Minimum width of the through hole 13 on the first main surface 10a" refers to the diameter of the inscribed circle of the shape of the through hole 13 in a plan view on the first main surface 10a.
  • Palladium is not present at the interface between the insulating layer 10 and the third copper layer 20 constituting the inner wall surface of the through hole 13 and the interface between the second copper layer 12 and the third copper layer 20, or palladium unintentionally mixed into the plating layer bath is inevitably attached. That is, the palladium concentration in the region of the third copper layer 20 from the interface between the insulating layer 10 (the inner wall surface of the through hole 13) and the third copper layer 20 to a depth of 10 nm is 0.5 mass percent or less. In addition, the palladium concentration in the region of the third copper layer 20 from the interface between the second copper layer 12 and the third copper layer 20 exposed inside the through hole 13 to a depth of 10 nm is 0.5 mass percent or less.
  • Palladium is not present at the interface between the first copper layer 11 and the third copper layer 20, and the palladium concentration in the region of the third copper layer 20 from the interface between the first copper layer 11 and the third copper layer 20 to a depth of 10 nm is 0.5 mass percent or less.
  • the palladium concentration in the third copper layer 20 region is measured, for example, by energy dispersive X-ray spectroscopy analysis of a cross section of the hole cut with a focused ion beam.
  • FIG. 2 is a manufacturing process diagram of the printed wiring board 100.
  • the manufacturing method of the printed wiring board 100 includes a preparation process S1, a first etching process S2, a hole drilling process S3, a desmearing process S4, a resist pattern forming process S5, an electrolytic plating process S6, a resist pattern removing process S7, and a second etching process S8.
  • FIG. 3 is a cross-sectional view illustrating the preparation step S1.
  • an insulating layer 10 is prepared in the preparation step S1 in the preparation step S1.
  • the insulating layer 10 prepared in the preparation step S1 has a first copper layer 11 disposed over the entire surface of the first main surface 10a, and a second copper layer 12 disposed over the entire surface of the second main surface 10b.
  • the insulating layer 10 prepared in the preparation step S1 does not have a through hole 13 formed therein.
  • the first etching step S2 is performed after the preparation step S1.
  • FIG. 4 is a cross-sectional view illustrating the first etching step S2. As shown in FIG. 4, in the first etching step S2, etching is performed to form a portion of the through hole 13 in the first copper layer 11.
  • the hole making step S3 is performed after the first etching step S2.
  • FIG. 5 is a cross-sectional view illustrating the hole making step S3. As shown in FIG. 5, for example, by irradiating a laser beam, a portion of the through hole 13 in the insulating layer 10 is formed.
  • the desmear process S4 is carried out after the hole drilling process S3.
  • foreign matter and the like on the surface of the second copper layer 12 exposed inside the through hole 13 is removed by etching.
  • the resist pattern forming process S5 is performed after the desmear process S4.
  • the etching in the desmear process S4 is performed weakly so as not to excessively erode the second copper layer 12 exposed inside the through hole 13. Therefore, after the desmear process S4 and before the resist pattern forming process S5, foreign matter may remain on the surface of the second copper layer 12 exposed inside the through hole 13.
  • FIG. 6 is a cross-sectional view illustrating the resist pattern forming process S5.
  • a resist pattern 30 is formed in the resist pattern forming process S5.
  • the resist pattern 30 is formed, for example, by applying a dry film resist onto the first copper layer 11, and exposing and developing the applied dry film resist. Since the dry film resist is developed using an alkaline solution, some of the foreign matter remaining on the surface of the second copper layer 12 exposed inside the through hole 13 is removed at this time.
  • FIG. 7 is a cross-sectional view illustrating the electrolytic plating process S6. As shown in FIG. 7, in the electrolytic plating process S6, electrolytic plating is performed to form a third copper layer 20 on the first copper layer 11 exposed from the opening of the resist pattern 30 and on the second copper layer 12 exposed inside the through hole 13.
  • the third copper layer 20 on the first copper layer 11 around the through hole 13 grows, it extends along the inner wall surface of the through hole 13.
  • the third copper layer 20 on the second copper layer 12 exposed inside the through hole 13 grows, it also extends along the inner wall surface of the through hole 13. Therefore, the third copper layer 20 extending from the first copper layer 11 around the through hole 13 along the inner wall surface of the through hole 13 and the third copper layer 20 extending from the second copper layer 12 exposed inside the through hole 13 along the inner wall surface of the through hole 13 are integrated, and the third copper layer 20 is also formed on the inner wall surface of the through hole 13.
  • the resist pattern removal process S7 is performed after the electrolytic plating process S6.
  • FIG. 8 is a cross-sectional view illustrating the resist pattern removal process S7. As shown in FIG. 8, in the resist pattern removal process S7, the resist pattern 30 is removed. The second etching process S8 is performed after the resist pattern removal process S7. In the second etching process S8, the first copper layer 11 that was under the resist pattern 30 is removed. This results in the formation of the printed wiring board 100 having the structure shown in FIG. 1.
  • the effects of the printed wiring board 100 will be described below in comparison with a comparative example.
  • the printed wiring board according to the comparative example is designated as printed wiring board 100A.
  • FIG. 9 is a cross-sectional view of printed wiring board 100A.
  • printed wiring board 100A further has electrolessly plated copper layer 40.
  • Electrolessly plated copper layer 40 is a copper layer formed by electroless plating. Electrolessly plated copper layer 40 is disposed on first copper layer 11, on the inner wall surface of through hole 13, and on second copper layer 12 exposed inside through hole 13. Except for these points, the configuration of printed wiring board 100A is the same as the configuration of printed wiring board 100.
  • the method for manufacturing the printed wiring board 100A further includes an electroless plating step S9.
  • the electroless plating step S9 is performed after the desmear step S4 and before the resist pattern forming step S5.
  • a palladium catalyst is applied to the first copper layer 11, the inner wall surface of the through hole 13, and the second copper layer 12 exposed inside the through hole 13, and then electroless plating is performed to form an electroless plated copper layer 40.
  • resist pattern 30 is formed on electrolessly plated copper layer 40 on first copper layer 11.
  • third copper layer 20 is formed on electrolessly plated copper layer 40.
  • second etching step S8 electrolessly plated copper layer 40 and first copper layer 11 that were under resist pattern 30 are removed. Except for these points, the method for manufacturing printed wiring board 100A is the same as the method for manufacturing printed wiring board 100.
  • the manufacturing method for printed wiring board 100A includes electroless plating step S9, palladium remains at the interface between insulating layer 10 (the inner wall surface of through hole 13) and electrolessly plated copper layer 40, and at the interface between second copper layer 12 exposed inside through hole 13 and electrolessly plated copper layer 40.
  • the second copper layer 12 exposed inside the through hole 13 is covered with the electroless plated copper layer 40 when the resist pattern formation process S5 and the electrolytic plating process S6 are performed, and therefore the above-mentioned foreign matter, etc. are not removed by the development in the resist pattern formation process S5 and the degreasing process before the electrolytic plating process S6 is performed.
  • Palladium remaining at the interface between the insulating layer 10 (the inner wall surface of the through hole 13) and the electrolessly plated copper layer 40, and at the interface between the second copper layer 12 exposed inside the through hole 13 and the electrolessly plated copper layer 40, and foreign matter between the second copper layer 12 exposed inside the through hole 13 and the electrolessly plated copper layer 40, may cause the third copper layer 20 to peel off together with the electrolessly plated copper layer 40, resulting in a break in the wire.
  • the electroless plating step S9 since the electroless plating step S9 is not performed, no palladium remains at the interface between the insulating layer 10 (the inner wall surface of the through hole 13) and the third copper layer 20, and at the interface between the second copper layer 12 exposed inside the through hole 13 and the third copper layer 20.
  • foreign matter and the like on the surface of the second copper layer 12 exposed inside the through hole 13 is also removed by the development in the resist pattern formation step S5 and the degreasing treatment before the electrolytic plating step S6. In this way, with the printed wiring board 100, it is possible to prevent the third copper layer 20 from peeling off due to palladium or foreign matter, causing a break in the blind via hole.
  • thickness T2 is less than 0.4 times thickness T1
  • the growth of third copper layer 20 is insufficient, and it becomes difficult to connect the third copper layer 20 extending from the first copper layer 11 around through hole 13 along the inner wall surface of through hole 13 to the third copper layer 20 extending from the second copper layer 12 exposed inside through hole 13 along the inner wall surface of through hole 13.
  • thickness T2 is more than 0.6 times width W1
  • the third copper layer on the first copper layer 11 around through hole 13 blocks the upper end of through hole 13, and the growth of third copper layer 20 on the second copper layer 12 exposed inside through hole 13 may be insufficient.
  • thickness T2 0.4 times or more than thickness T1 and 0.6 times or less than width W1
  • Samples 1 to 8 are prepared. In Samples 1 to 8, the ratio of thickness T2 to thickness T1 and the ratio of thickness T2 to width W1 are changed. Details of Samples 1 to 8 are shown in Table 1. In Samples 1, 2, and 4 to 6, thickness T2 is 0.4 times or more than thickness T1 and 0.6 times or less than width W1. On the other hand, in Sample 3, thickness T2 is less than 0.4 times thickness T1 and more than 0.6 times width W1. In Sample 7, thickness T2 is less than 0.4 times thickness T1, and in Sample 8, thickness T2 is more than 0.6 times width W1.
  • the defect rate in Table 1 is the percentage of improperly formed blind via holes in each sample. As shown in Table 1, the defect rates for samples 1, 2, and 4 to 6 are lower than the defect rates for samples 3, 7, and 8.
  • thickness T2 is 0.8 times or more than thickness T1, while in sample 6, thickness T2 is 0.4 times or more and less than 0.8 times thickness T1.
  • the defect rate in sample 1 is lower than the defect rate in sample 6.
  • thickness T2 is 0.45 times or less than width W1, while in sample 5, thickness T2 is more than 0.45 times and less than 0.6 times width W1.
  • the defect rate in sample 2 is lower than the defect rate in sample 5.
  • the third copper layer 20 extending from the first copper layer 11 around the through hole 13 along the inner wall surface of the through hole 13 and the third copper layer 20 extending from the second copper layer 12 exposed inside the through hole 13 along the inner wall surface of the through hole 13 are more easily connected, making it possible to more appropriately form the third copper layer 20 on the inner wall surface of the through hole 13.
  • the printed wiring board according to the second embodiment is designated as printed wiring board 200.
  • FIG. 10 is a cross-sectional view of the printed wiring board 200.
  • the printed wiring board 200 has a first insulating layer 50, a first copper layer 51, an adhesive layer 60, a second insulating layer 70, a second copper layer 71, and a third copper layer 80.
  • the constituent material of the first insulating layer 50 has electrical insulating properties and flexibility.
  • the constituent material of the first insulating layer 50 is, for example, polyimide. However, the constituent material of the first insulating layer 50 is not limited to this.
  • the first insulating layer 50 has a first main surface 50a.
  • the first main surface 50a is a surface perpendicular to the thickness direction of the first insulating layer 50, and constitutes either the front or back surface of the first insulating layer 50.
  • the material of the first copper layer 51 is copper or a copper alloy.
  • the first copper layer 51 is disposed on the first principal surface 50a.
  • a fourth copper layer 52 may be interposed between the first copper layer 51 and the first principal surface 50a.
  • the first copper layer 51 is an electrolytically plated copper layer.
  • the adhesive layer 60 is disposed on the first main surface 50a so as to cover the first copper layer 51 (and the fourth copper layer 52).
  • the material constituting the adhesive layer 60 is an adhesive.
  • the material constituting the adhesive layer 60 is, for example, an epoxy-based adhesive.
  • the material of the second insulating layer 70 has electrical insulation properties and flexibility.
  • the material of the second insulating layer 70 is, for example, polyimide. However, the material of the second insulating layer 70 is not limited to this.
  • the second insulating layer 70 has a second main surface 70a and a third main surface 70b.
  • the second main surface 70a and the third main surface 70b are surfaces perpendicular to the thickness direction of the second insulating layer 70 and constitute the front and back surfaces of the second insulating layer 70.
  • the third main surface 70b is the opposite surface to the second main surface 70a.
  • the second insulating layer 70 is disposed on the adhesive layer 60 so that the second main surface 70a faces the adhesive layer 60.
  • the second copper layer 71 is made of copper or a copper alloy.
  • the second copper layer 71 is disposed on the third main surface 70b.
  • a through hole 72 is formed in the adhesive layer 60, the second insulating layer 70, and the second copper layer 71.
  • the through hole 72 penetrates the adhesive layer 60, the second insulating layer 70, and the second copper layer 71 in the thickness direction.
  • the first copper layer 51 is exposed from the through hole 72.
  • the width of the through hole 72 on the third main surface 70b is width W2.
  • the width W2 here is the minimum value of the width of the through hole 72 on the third main surface 70b.
  • the minimum value of the width of the through hole 72 on the third main surface 70b refers to the diameter of the inscribed circle of the shape of the through hole 72 in a plan view on the third main surface 70b.
  • the width W2 is, for example, 25 ⁇ m or more and 250 ⁇ m or less.
  • the sum of the thickness of the second insulating layer 70 and the thickness of the adhesive layer 60 between the first copper layer 51 and the second insulating layer 70 is thickness T3.
  • the thickness T3 is, for example, 12.5 ⁇ m or more and 250 ⁇ m or less.
  • the thickness T3 is the average value of measurements taken at 10 arbitrary points on the cross-sectional photograph.
  • the shape of the through hole 72 in plan view is, for example, circular. However, the planar shape of the through hole 72 is not limited to this.
  • the third copper layer 80 is disposed on the first copper layer 51 exposed inside the through hole 72, on the inner wall surface of the through hole 72, and on the second copper layer 71 around the through hole 72.
  • the third copper layer 80 is also disposed on the second copper layer 71 outside the periphery of the through hole 72.
  • the constituent material of the third copper layer 80 is copper or a copper alloy.
  • the third copper layer 80 may be an electrolytically plated copper layer.
  • the palladium concentration in the region of the third copper layer 80 from the interface between the first copper layer 51 and the third copper layer 80 exposed inside the through hole 72 to a depth of 10 nm is 0.5 mass percent or less.
  • the palladium concentration in the region of the third copper layer 80 from the interface between the second insulating layer 70 (the inner wall surface of the through hole 72) and the third copper layer 80 to a depth of 10 nm is 0.5 mass percent or less.
  • the palladium concentration in the region of the third copper layer 80 from the interface between the second copper layer 71 and the third copper layer 80 to a depth of 10 nm is 0.5 mass percent or less.
  • the palladium concentration in the region of the third copper layer 80 is measured, for example, by energy dispersive X-ray spectroscopy analysis of a cross section of the hole cut with a focused ion beam.
  • Thickness T4 is the average value of measurements taken at any 10 points on the cross-sectional photograph. Thickness T4 may be 0.4 times or more than thickness T3 and 0.6 times or less than width W2. Thickness T4 may be 0.8 times or more than thickness T3 and 0.45 times or less than width W2. Thickness T4 is, for example, 10 ⁇ m or more and 45 ⁇ m or less.
  • the printed wiring board 200 may further include a fifth copper layer 53, a sixth copper layer 54, an adhesive layer 61, a third insulating layer 73, a seventh copper layer 74, and an eighth copper layer 81.
  • a through hole 55 may be formed in the first insulating layer 50, the fourth copper layer 52, and the fifth copper layer 53. The through hole 55 penetrates the first insulating layer 50, the fourth copper layer 52, and the fifth copper layer 53 in the thickness direction.
  • the fourth principal surface 50b is a surface perpendicular to the thickness direction of the first insulating layer 50, and is the surface opposite to the first principal surface 50a.
  • the fifth copper layer 53 is disposed on the fourth principal surface 50b.
  • the material of the fifth copper layer 53 is copper or a copper alloy.
  • the sixth copper layer 54 is disposed on the fifth copper layer 53.
  • the material of the sixth copper layer 54 is copper or a copper alloy.
  • the sixth copper layer 54 is an electrolytically plated copper layer.
  • the first copper layer 51 and the sixth copper layer 54 are connected to each other on the inner wall surface of the through hole 55.
  • the adhesive layer 61 is disposed on the fourth main surface 50b so as to cover the fifth copper layer 53 and the sixth copper layer 54.
  • the material constituting the adhesive layer 61 is an adhesive.
  • the material constituting the adhesive layer 61 is, for example, an epoxy-based adhesive.
  • the material of the third insulating layer 73 has electrical insulation properties and flexibility.
  • the material of the third insulating layer 73 is, for example, polyimide. However, the material of the third insulating layer 73 is not limited to this.
  • the third insulating layer 73 has a fifth main surface 73a and a sixth main surface 73b.
  • the fifth main surface 73a and the sixth main surface 73b are surfaces perpendicular to the thickness direction of the third insulating layer 73, and form the front and back surfaces of the third insulating layer 73.
  • the sixth main surface 73b is the opposite surface to the fifth main surface 73a.
  • the third insulating layer 73 is disposed on the adhesive layer 61 so that the fifth main surface 73a faces the adhesive layer 61.
  • the seventh copper layer 74 is made of copper or a copper alloy.
  • the seventh copper layer 74 is disposed on the sixth main surface 73b.
  • a through hole 75 is formed in the adhesive layer 61, the third insulating layer 73, and the seventh copper layer 74.
  • the through hole 75 penetrates the adhesive layer 61, the third insulating layer 73, and the seventh copper layer 74 in the thickness direction.
  • the sixth copper layer 54 is exposed from the through hole 75.
  • the width of the through hole 75 on the sixth main surface 73b is width W3.
  • the width W3 here is the minimum value of the width of the through hole 75 on the sixth main surface 73b.
  • the "minimum value of the width of the through hole 75 on the sixth main surface 73b" refers to the diameter of the inscribed circle of the shape of the through hole 75 in a plan view on the sixth main surface 73b.
  • the width W3 is, for example, 25 ⁇ m or more and 250 ⁇ m or less.
  • the sum of the thickness of the third insulating layer 73 and the thickness of the adhesive layer 61 between the sixth copper layer 54 and the third insulating layer 73 is thickness T5.
  • the shape of the through hole 75 in a plan view is, for example, circular. However, the planar shape of the through hole 75 is not limited to this.
  • the thickness T5 is, for example, 12.5 ⁇ m or more and 250 ⁇ m or less.
  • the thickness T5 is the average value measured at 10 arbitrary points on the cross-sectional photograph.
  • the eighth copper layer 81 is disposed on the sixth copper layer 54 exposed inside the through hole 75, on the inner wall surface of the through hole 75, and on the seventh copper layer 74 around the through hole 75.
  • the eighth copper layer 81 is also disposed on the seventh copper layer 74 outside the periphery of the through hole 75.
  • the constituent material of the eighth copper layer 81 is copper or a copper alloy.
  • the eighth copper layer 81 may be an electrolytically plated copper layer.
  • the thickness of the eighth copper layer 81 on the seventh copper layer 74 is defined as thickness T6.
  • Thickness T6 may be 0.4 times or more than thickness T5 and 0.6 times or less than width W3.
  • Thickness T6 may be 0.8 times or more than thickness T5 and 0.45 times or less than width W3.
  • Thickness T6 is, for example, 10 ⁇ m or more and 45 ⁇ m or less.
  • the palladium concentration in the region of the eighth copper layer 81 from the interface between the sixth copper layer 54 and the eighth copper layer 81 exposed inside the through hole 75 to a depth of 10 nm is 0.5 mass percent or less.
  • the palladium concentration in the region of the eighth copper layer 81 from the interface between the third insulating layer 73 (the inner wall surface of the through hole 75) and the eighth copper layer 81 to a depth of 10 nm is 0.5 mass percent or less.
  • the palladium concentration in the region of the eighth copper layer 81 from the interface between the seventh copper layer 74 and the eighth copper layer 81 to a depth of 10 nm is 0.5 mass percent or less.
  • the palladium concentration in the region of the eighth copper layer 81 is measured, for example, by energy dispersive X-ray spectroscopy analysis of a cross section of the hole cut with a focused ion beam.
  • the printed wiring board 200 shown in FIG. 10 has circuits formed on both sides of the first insulating layer 50, and includes two through holes (through hole 72 and through hole 75) that connect to each other, but the printed wiring board of the present disclosure is not limited to this. It may also be in the form of a combination of multiple single-sided boards, and the circuit may include two or more layers, three or more layers, or six or more layers.
  • FIG. 11 is a manufacturing process diagram of printed wiring board 200.
  • the manufacturing method of printed wiring board 200 includes a preparation process S11, a first hole drilling process S12, a first resist pattern forming process S13, a first electrolytic plating process S14, a first resist pattern removing process S15, and a first etching process S16.
  • the method for manufacturing the printed wiring board 200 further includes an insulating layer attachment process S17, a second hole drilling process S18, a second resist pattern formation process S19, a second electrolytic plating process S20, a second resist pattern removal process S21, and a second etching process S22.
  • FIG. 12 is a cross-sectional view illustrating the preparation step S11.
  • a first insulating layer 50 is prepared in the preparation step S11.
  • the first insulating layer 50 prepared in the preparation step S11 has a fourth copper layer 52 disposed on the first main surface 50a and a fifth copper layer 53 disposed on the fourth main surface 50b.
  • no through holes 55 have been formed in the first insulating layer 50, the fourth copper layer 52, and the fifth copper layer 53.
  • FIG. 13 is a cross-sectional view illustrating the first hole drilling process S12. As shown in FIG. 13, in the first hole drilling process S12, a through hole 55 is formed.
  • the through hole 55 is formed, for example, by irradiating a laser beam.
  • FIG. 14 is a cross-sectional view illustrating the first resist pattern forming process S13.
  • a resist pattern 31 is formed on the fourth copper layer 52
  • a resist pattern 32 is formed on the fifth copper layer 53.
  • the resist patterns 31 and 32 are formed, for example, by applying a dry film resist and exposing and developing the applied dry film resist.
  • the first electrolytic plating process S14 is performed after the first resist pattern forming process S13.
  • FIG. 15 is a cross-sectional view illustrating the first electrolytic plating process S14.
  • electrolytic plating is performed to form a first copper layer 51 on the fourth copper layer 52 exposed from the opening of the resist pattern 31, and a sixth copper layer 54 on the fifth copper layer 53 exposed from the opening of the resist pattern 32.
  • the first copper layer 51 and the sixth copper layer 54 grow, the first copper layer 51 and the sixth copper layer 54 are connected to each other and integrated at the through hole 55.
  • the first resist pattern removal process S15 is performed after the first electrolytic plating process S14.
  • FIG. 16 is a cross-sectional view illustrating the first resist pattern removal process S15. As shown in FIG. 16, in the first resist pattern removal process S15, resist patterns 31 and 32 are removed.
  • the first etching step S16 is performed after the first resist pattern removal step S15.
  • FIG. 17 is a cross-sectional view illustrating the first etching step S16. As shown in FIG. 17, in the first etching step S16, the fourth copper layer 52 that was under the resist pattern 31 and the fifth copper layer 53 that was under the resist pattern 32 are removed by etching.
  • FIG. 18 is a cross-sectional view illustrating the insulating layer attachment step S17.
  • the second insulating layer 70 and the third insulating layer 73 are attached.
  • an uncured adhesive layer 60 is applied to the first main surface 50a so as to cover the first copper layer 51 and the fourth copper layer 52
  • an uncured adhesive layer 61 is applied to the fourth main surface 50b so as to cover the fifth copper layer 53 and the sixth copper layer 54.
  • the second insulating layer 70 and the third insulating layer 73 are prepared. At this stage, the second copper layer 71 is disposed on the third main surface 70b, and the seventh copper layer 74 is disposed on the sixth main surface 73b.
  • the second insulating layer 70 is disposed on the adhesive layer 60 so that the second main surface 70a faces the adhesive layer 60
  • the third insulating layer 73 is disposed on the adhesive layer 61 so that the fifth main surface 73a faces the adhesive layer 61.
  • the adhesive layer 60 and the adhesive layer 61 are heated and cured, thereby attaching the second insulating layer 70 and the third insulating layer 73.
  • FIG. 19 is a cross-sectional view illustrating the second hole drilling process S18. As shown in FIG. 19, in the second hole drilling process S18, through holes 72 and 75 are formed by, for example, irradiating laser light.
  • the second resist pattern forming process S19 is performed after the second hole making process S18.
  • FIG. 20 is a cross-sectional view illustrating the second resist pattern forming process S19. As shown in FIG. 20, in the second resist pattern forming process S19, a resist pattern 33 is formed on the second copper layer 71, and a resist pattern 34 is formed on the seventh copper layer 74.
  • the resist patterns 33 and 34 are formed, for example, by applying a dry film resist and exposing and developing the applied dry film resist.
  • the second electrolytic plating process S20 is performed after the second resist pattern forming process S19.
  • FIG. 21 is a cross-sectional view illustrating the second electrolytic plating process S20.
  • electrolytic plating is performed to form a third copper layer 80 on the second copper layer 71 exposed from the opening of the resist pattern 33, on the inner wall surface of the through hole 72, and on the first copper layer 51 exposed inside the through hole 72.
  • an eighth copper layer 81 is formed on the seventh copper layer 74 exposed from the opening of the resist pattern 34, on the inner wall surface of the through hole 75, and on the sixth copper layer 54 exposed inside the through hole 75.
  • the second resist pattern removal process S21 is performed after the second electrolytic plating process S20.
  • FIG. 22 is a cross-sectional view illustrating the second resist pattern removal process S21. As shown in FIG. 22, in the second resist pattern removal process S21, the resist pattern 33 and the resist pattern 34 are removed.
  • the second etching process S22 is performed after the second resist pattern removal process S21. In the second etching process S22, the second copper layer 71 that was under the resist pattern 33 and the seventh copper layer 74 that was under the resist pattern 34 are removed by etching. In this way, the printed wiring board 200 having the structure shown in FIG. 10 is manufactured.
  • the manufacturing method of the printed wiring board 200 since an electroless plating process is not performed, no palladium remains at the interface between the second insulating layer 70 (the inner wall surface of the through hole 72) and the third copper layer 80, and at the interface between the first copper layer 51 exposed inside the through hole 72 and the third copper layer 80.
  • foreign matter and the like on the surface of the first copper layer 51 exposed inside the through hole 72 is removed by a degreasing process before development in the second resist pattern formation process S19 and the second electrolytic plating process S20 are performed.
  • printed wiring board 200 can prevent the third copper layer 80 from peeling off due to palladium, foreign matter, etc., which would cause a break in the blind via hole.
  • printed wiring board 200 can prevent the eighth copper layer 81 from peeling off due to palladium, foreign matter, etc., which would cause a break in the blind via hole.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
PCT/JP2023/036476 2022-10-20 2023-10-06 プリント配線板 Ceased WO2024084994A1 (ja)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001144441A (ja) * 1999-11-05 2001-05-25 Three M Innovative Properties Co 多層両面配線基板とその製造方法
JP2009094191A (ja) * 2007-10-05 2009-04-30 Ube Ind Ltd 多層配線基板の製造方法
EP2566311A1 (en) * 2011-09-02 2013-03-06 Atotech Deutschland GmbH Direct plating method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001144441A (ja) * 1999-11-05 2001-05-25 Three M Innovative Properties Co 多層両面配線基板とその製造方法
JP2009094191A (ja) * 2007-10-05 2009-04-30 Ube Ind Ltd 多層配線基板の製造方法
EP2566311A1 (en) * 2011-09-02 2013-03-06 Atotech Deutschland GmbH Direct plating method

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