WO2024078164A1

WO2024078164A1 - Method and apparatus for measuring signal delay of chip tester, and computer device

Info

Publication number: WO2024078164A1
Application number: PCT/CN2023/115507
Authority: WO
Inventors: 尹通; 董亚明; 金晓彬
Original assignee: 苏州华兴源创科技股份有限公司
Priority date: 2022-10-09
Filing date: 2023-08-29
Publication date: 2024-04-18
Also published as: CN115291090B; CN115291090A

Abstract

A method and apparatus for measuring a signal delay of a chip tester, and a computer device. The method comprises: performing a vector signal test on a target channel, wherein the vector signal test employs a chip tester to generate a test vector signal carrying a timing phase point (S20); once the vector signal test is completed, moving the position of the timing phase point and performing the vector signal test on the target channel again (S30); repeatedly moving the position of the timing phase point and performing the vector signal test on the target channel again, until the number of vector signal tests reaches a preset standard (S40); and once the number of vector signal tests reaches the preset standard, obtaining a level comparison result of said number, and performing a delayed operation on the basis of the level comparison result of said number to obtain a signal delay time (S50).

Description

Chip tester signal delay measurement method, device and computer equipment

Related Applications

This disclosure claims priority to Chinese patent application number 2022112255646, filed on October 9, 2022, entitled “Chip tester signal delay measurement method, device and computer equipment”, the entire text of which is hereby incorporated by reference.

Technical Field

The present disclosure relates to the field of chip testing, and in particular to a chip testing machine signal delay measurement method, device and computer equipment.

Background technique

With the development of chip technology, how to test chips efficiently and accurately has become increasingly important. In the process of chip testing, ATE (Automatic Test Equipment) is usually used for testing. ATE is a chip tester used in the semiconductor industry. The ATE main control chip can generate stimulus timing outputs in a specific format according to a preset script program and send them to the chip to be tested. The chip to be tested is usually placed on the ATE test board (also called a business board) and connected to the ATE main control chip through multiple lines such as connectors and Load Boards. Among them, the load board is a mechanical and circuit interface board that can connect the test equipment to the device under test. The stimulus timing output issued by ATE is usually transmitted in the form of a Pattern (vector signal), so this link is generally called Pattern testing.

However, ATE generally measures multiple chips to be tested at the same time when performing chip testing. Among them, the chips to be tested may be located on the same test board or on different test boards. Even if they are located on the same test board, due to the different connection lines at various positions on the board, the signal channel established between each chip to be tested and the ATE main control chip may have a length deviation in the actual signal transmission path. If they are located on different test boards, this deviation will be even greater. The path length deviation between each channel will cause the signal sent by the ATE main control chip to arrive at the chip to be tested at an inconsistent time, which will reduce the Pattern time margin. In some high-speed applications, inconsistent signal delivery or reading time will also cause timing logic errors, which will in turn affect the entire Pattern test, generate errors, and cause great interference to chip testing.

Therefore, it is necessary to provide a method for determining the signal delay time caused by line deviation between channels.

Summary of the invention

According to various embodiments of the present application, a chip tester signal delay measurement method, apparatus and computer equipment are provided.

In a first aspect, an embodiment of the present disclosure provides a method for measuring signal delay of a chip tester, the method comprising:

Performing a vector signal test on the target channel; the vector signal test uses the chip tester to generate a test vector signal with timing phase points;

The vector signal test on the target channel includes: sending the test vector signal to the target channel; obtaining a reflected vector signal of the test vector signal; comparing the level at the timing phase point in the reflected vector signal with a preset comparison level, and recording the level comparison result;

After the vector signal test is completed, the position of the timing phase point is moved, and the vector signal test is performed on the target channel again;

Repeatingly moving the position of the timing phase point and re-performing a vector signal test on the target channel until the number of vector signal tests reaches a preset standard;

When the number of times of the vector signal test reaches a preset standard, the level comparison results of the number of times are obtained, and a delay operation is performed based on the level comparison results of the number of times to obtain a signal delay time.

In one of the embodiments, after recording the level comparison result, the method further includes:

Performing binary processing on the level comparison result to obtain data to be processed;

The data to be processed are accumulated; the result of the data accumulation is used to perform a delay operation when the number of times the vector signal is tested reaches a preset standard to obtain the signal delay time.

In one embodiment, the binary processing of the level comparison result to obtain the data to be processed includes:

The level of the timing phase point is compared with a preset comparison level, and the data to be processed is obtained based on the comparison result.

In one of the embodiments, before performing a vector signal test on a target channel, the method further includes:

Determine the measurement mode. Different measurement modes correspond to the number of vector signal tests.

A preset standard for the number of times the vector signal test is performed is determined according to the measurement mode.

In one of the embodiments, the measurement mode includes: a group consisting of a performance mode test, a balance mode test, and a fast mode test;

The number of tests in the performance mode, the number of tests in the balanced mode, and the number of tests in the fast mode decrease in sequence;

The test accuracy of the performance mode, the test accuracy of the balanced mode, and the test accuracy of the fast mode decrease in sequence;

The timing phase point shift interval of the performance mode, the timing phase point shift interval of the balance mode, and the timing phase point shift interval of the fast mode increase in sequence.

In one embodiment, moving the position of the timing phase point includes:

Get the current test order;

Calculating the displacement distance according to the current test sequence and the preset moving point step;

The timing phase point is moved by the displacement distance to a target position.

In one embodiment, after obtaining the signal delay time, the method further includes:

Time compensation data is generated according to the signal delay time, and the time compensation data is used by the chip tester to implement signal timing compensation.

changing the length of the target channel;

The signal delay of the changed target channel is measured to obtain the displacement signal delay time;

The displacement difference time compensation data is generated according to the difference between the signal delay time and the displacement signal delay time.

In one embodiment, the moving the position of the timing phase point includes:

Setting the comparison point step, wherein the comparison point step is a fixed time value;

The timing phase point is moved within a period by a distance of the comparison point step.

In one embodiment, performing a delay operation based on the level comparison result of the number of times to obtain a signal delay time includes:

In the level comparison results of the number of times, searching for a timing phase point whose level at the timing phase point is greater than a preset comparison level, to obtain a target timing phase point;

According to the cycle number of the target timing phase point, the basic time is obtained;

Calculate the additional time according to the initial position of the target timing phase point, the number of times, and the size of the comparison point step;

The basic time is added to the additional time to obtain a signal delay time.

In one of the embodiments, it is characterized in that the test vector signal is pre-set with a timing phase point in each cycle, and the position of the timing phase point in each cycle is consistent.

In one embodiment, sending the test vector signal to the target channel includes:

The end of the target channel is set to an open circuit state, and a test vector signal with a timing phase point is sent to the target channel; the target channel is a line channel that sends a signal to a placement point of the chip to be tested.

In a second aspect, the present disclosure further provides a chip tester signal delay measurement device, comprising:

A test module is used to perform a vector signal test on a target channel; the vector signal test uses a test vector signal with a timing phase point generated by the chip tester; the vector signal test on the target channel includes: sending the test vector signal to the target channel; obtaining a reflected vector signal of the test vector signal; comparing the level at the timing phase point in the reflected vector signal with a preset comparison level, and recording the level comparison result;

A timing module, used for moving the position of the timing phase point;

The main control module is used to control the timing module to repeatedly move the position of the timing phase point, and is also used to control the The testing module re-performs the vector signal test on the target channel until the number of the vector signal test reaches a preset standard;

And, a data processing module is used to obtain the level comparison results of the number of times after the number of times of the vector signal test reaches a preset standard, and perform delay calculation based on the level comparison results of the number of times to obtain the signal delay time.

In a third aspect, the present disclosure further provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any of the above methods when executing the computer program.

In a fourth aspect, the present disclosure further provides a chip testing machine, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any of the above-described methods when executing the computer program.

The details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are merely embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on the disclosed drawings without creative work.

FIG1 is a schematic flow chart of a method for measuring signal delay of a chip tester in one embodiment;

FIG2 is a schematic diagram of a process of performing a vector signal test on a target channel in one embodiment;

FIG3 is a schematic diagram of a process flow after step S206 in one embodiment;

FIG4 is a schematic diagram of a flow chart of determining a measurement mode in one embodiment;

FIG5 is a schematic diagram of a process of moving the position of a timing phase point in one embodiment;

FIG6 is a schematic diagram of an accumulation result of data accumulation for data to be processed in one embodiment;

FIG7 is a schematic diagram of a process of performing delay compensation on a line channel after length change in one embodiment;

FIG8 is a schematic structural diagram of a chip tester signal delay measurement device in one embodiment;

FIG9 is a schematic diagram of the structure of a chip tester signal delay compensation measurement system in one embodiment;

FIG10 is a schematic flow chart of a chip tester signal delay compensation measurement method in one embodiment;

FIG11 is a flow chart of a method for implementing timing compensation in one embodiment;

FIG. 12 is a schematic diagram of the internal structure of a computer device in one embodiment.

The components in the accompanying drawings are marked as follows: 70-host computer; 80-programmable logic device center; 602-test module; 604-timing module; 606-main control module; 608-data processing module; 702-main control measurement module; 704-pattern control module; 706-data reading and parsing module; 708-data accumulation and processing module; 710-file generation module; 802-pattern data storage module; 804-output module; 806-receiving and comparing module; 808-comparison data reader/writer; 7041-timing control unit; 7042-level control unit; 8021-timing parameter storage unit; 8022-level parameter storage unit.

Detailed ways

The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present disclosure. On the contrary, they are merely examples of apparatuses and methods consistent with some aspects of the present disclosure as detailed in the appended claims. The terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, product or apparatus that includes a series of elements includes not only those elements, It also includes other elements not explicitly listed, or elements inherent to such process, method, product or device. In the absence of further restrictions, it does not exclude the existence of other identical or equivalent elements in the process, method, product or device including the elements. For example, if the words first, second, etc. are used to indicate names, they do not indicate any specific order.

It should be noted that the connection, connection, etc. described in the present disclosure may be a direct connection through an interface or pins between devices, a connection through leads, or a wireless connection (communication connection).

Generally speaking, when ATE (Automatic Test Equipment), also known as "chip tester") performs chip testing on the device under test (DUT), the length deviation between different lines causes differences in the time it takes for the pattern to reach the chip under test. To solve this problem, an external device can be introduced to measure each line channel in turn to obtain the delay time. However, there are many ATE test channels, and this method is time-consuming and labor-intensive. Not only does it require additional configuration of instruments and equipment based on the ATE model, but the delay time measurement process also has problems such as difficult measurement points, a limited number of single measurement channels, and complicated data recording and calculations that are prone to errors. This results in delay time measurements that are time-consuming, low in precision, and large errors.

To solve the above problem, as shown in FIG1 , a chip tester signal delay measurement method is provided, the method comprising:

Step S20, performing a vector signal test on the target channel; the vector signal test uses a test vector signal with timing phase points generated by the chip tester.

Among them, the target channel is the signal transmission channel between the ATE main control chip and the chip to be tested. Vector signal testing can be achieved through the Pattern test function of ATE itself. Using the Pattern test of ATE, a Pattern (vector signal) can be sent to the target channel, and a timing phase point can be set. The Pattern can be observed at the ATE measurement end, and the level at the timing phase point can be compared with a preset value. The timing phase point can be a point pre-set on the Pattern timeline. The timing phase point can refer to a symbol that represents a certain time point in the system in the timing diagram. It can be used to identify events or state changes that occur at various time points in the system. The timing phase point can be represented by a vertical line or arrow, and cooperates with the messages in the timing diagram to describe the interaction and timing relationship between the various participants in the system.

Specifically, the ATE is instructed to start the Pattern test function and send a test vector signal to the target channel according to a preset instruction. The reflected vector signal is obtained by the ATE to obtain a Pattern test result. The test vector signal includes a specific timing phase point and level. The Pattern test result can be a level comparison result obtained by the ATE through its own comparison function.

It should be noted that since this solution needs to measure the signal arrival time from the ATE main control chip to the chip to be tested on the business board, there may be no chip where the chip to be tested is placed on the business board when performing Pattern testing, and the end of the channel from the ATE main control chip to the chip placed on the business board can be open.

Step S30, after the vector signal test is completed, the position of the timing phase point is moved, and the vector signal test is performed on the target channel again.

Specifically, the position of the timing phase point is changed, and the test vector signal after the timing phase point is changed is sent to the target channel to obtain the pattern test result. In some embodiments, the comparison point step can be set, and the comparison point step is a fixed time value, so that the timing phase point moves the distance of the comparison point step within the cycle. For example, if the comparison point step is set to 20pS (picoseconds), the timing phase point can be moved backward 20pS on the time axis.

Step S40, repeatedly moving the position of the timing phase point and re-performing the vector signal test on the target channel until the number of vector signal tests reaches a preset standard.

The number of vector signal tests may be the number of times the ATE main control chip has performed pattern tests on the target channel. The preset standard may be the number of times the ATE main control chip needs to perform pattern tests according to preset instructions.

Specifically, the position of the timing phase point is moved multiple times, and a pattern test is performed on the target channel after each movement until a preset number of tests is reached.

Step S50, when the number of times of the vector signal test reaches a preset standard, the level comparison results of the number of times are obtained, and a delay operation is performed based on the level comparison results of the number of times to obtain a signal delay time.

The level comparison result of the times may be the level comparison result obtained after performing the vector signal test, for example If the vector signal test is performed 10 times, the level comparison result of the number of times can be the level comparison result of 10 times.

Specifically, after completing the preset number of Pattern tests, the results of the multiple Pattern tests can be comprehensively calculated to obtain the signal delay time. For example, the reflected vector signals of multiple Pattern tests can be combined on a time axis, and the signal delay time can be calculated based on the level results of the timing phase points. In some embodiments, the timing phase points that are higher than the preset comparison level in the level results of the times can be found, and the basic time can be obtained based on the number of cycles where the timing phase point is located, and then the additional time can be obtained by comprehensive calculation based on the initial position of the timing phase point, the number of vector signal tests, and the size of the comparison point step, and the signal delay time can be obtained by adding the basic time and the additional time.

In the technical solution provided by the embodiment of the present disclosure, the target channel is tested for vector signals through the Pattern test function of the ATE itself, and by setting the timing phase point on the vector signal, the timing phase point is moved multiple times and tested, and the signal delay time is calculated according to the test results. In this way, the signal delay time of a large number of channels can be measured using the ATE's own functions without the aid of external instruments and equipment, saving measurement time and cost. In addition, the calculation can be performed after changing the timing phase point multiple times, and the obtained signal delay time error is smaller and the result is more accurate.

In one embodiment, as shown in FIG2 , performing a vector signal test on a target channel includes:

Step S202: Send the test vector signal to the target channel.

Among them, the test vector signal can be a vector signal generated by the Pattern test module of the ATE. The vector signal is usually a signal with size and direction, and the direction of the vector represents the phase or relative position of the signal. The period of the test vector signal can be set to Per. Per is the time unit for vector signal output and comparison. The specific value can be customized in seconds. In some embodiments, the front end outputs a low level for N periods, and the back end outputs a high level for N periods, for a total of 2N periods, where N is a positive integer. Each period in the test vector signal is pre-set with a timing phase point, and the position of the timing phase point in each period is consistent.

Specifically, the end of the target channel is set to an open circuit state, and the ATE main control chip sends a test vector signal with a timing phase point to the target channel. The target channel is a line channel through which the ATE sends a signal to the placement point of the chip to be tested. The end of the target channel can be the end of the connection line between the ATE and the chip to be tested, and the end refers to the end on one side of the chip to be tested. It should be understood that when the end of the target channel is set to an open circuit state, no chip is placed at the end of the line. The open circuit state generally refers to a state in which the circuit is interrupted or disconnected. In the open circuit state, the current cannot pass through the end of the target channel, and the equipment or components after the end of the target channel cannot work normally.

Step S204: obtaining a reflected vector signal of the test vector signal.

Specifically, the reflected vector signal returned by the target channel may be received at the ATE end.

According to the time domain signal reflection principle, a pulse or step signal is sent to the transmission path. When the impedance changes in the transmission path, part of the energy will be reflected and the remaining energy will continue to be transmitted. Since the end of the target channel is set to an open circuit in step S202, an infinitely large resistor can be connected to its end, and the signal sent returns to the original path after reaching the end of the target channel. Since the returned reflected vector signal will meet part of the sent test vector signal, the area where the test vector signal and the reflected vector signal are superimposed and mixed can be observed at the ATE measurement end. For example, when the test vector signal is set to a low level of L and a high level of H, the signal amplitude M=(H-L)/2+L of the superimposed area of the high level and the low level can be observed at the measurement end. Furthermore, the low level of the measurement vector signal can be set to 0, and then the reflected vector signal can be calculated at the measurement end based on the signal amplitude of the superimposed area of the high level and the low level observed by the measured quantity.

Step S206, comparing the level at the timing phase point in the reflected vector signal with a preset comparison level, and recording the level comparison result.

Wherein, if the amplitude of the signal superposition area is set to M, and the preset comparison level is set to X, then M<X<H; wherein, M＝(H-L)/2+L; H is the high level of the measurement vector signal, and L is the low level of the measurement vector signal. Optionally, X＝0.75×(H-L)+L. Further, L can be 0, in which case X＝0.75H.

It should be understood that the reflected vector signal is the same as the highest level of the measured vector signal.

Specifically, the level at the timing phase point can be compared with a preset comparison level through the comparison function of the ATE, and the level comparison result can also be written into a designated memory.

In the above embodiment, a test vector signal with a preset phase point is sent to the channel by ATE, and the level at the phase point in the reflected vector signal is compared with the preset comparison level by using the comparison function of ATE itself, and the comparison result is recorded. In this way, without the help of external instruments and equipment, the pattern test of the target channel can be realized through the ATE's own functional modules, and the level comparison results can be recorded, which simplifies the test process and improves the test efficiency.

In one embodiment, as shown in FIG3 , after recording the level comparison result, the method further includes:

Step S208, performing binary processing on the level comparison result to obtain data to be processed.

Specifically, the level of the timing phase point is compared with the preset comparison level. The level of the timing phase point below the preset comparison level can be recorded as 0, and the level of the timing phase point above the preset comparison level can be recorded as 1. The recorded 0 or 1 forms the data to be processed.

Step S210, accumulating the data to be processed; the result of the data accumulation is used to perform a delay operation when the number of vector signal tests reaches a preset standard to obtain the signal delay time.

Specifically, the data to be processed obtained from the level comparison result of each Pattern test can be accumulated and processed, and the number of Parrern at this time can be recorded. When the Pattern test reaches a preset number of times, the accumulated data is calculated to obtain the signal delay time.

In the above embodiment, the level comparison result of the timing phase point is converted into the form of 0 or 1, which facilitates the storage, accumulation and reading of data, improves the data processing efficiency and reduces the overall measurement time.

In one embodiment, as shown in FIG4 , before performing a vector signal test on a target channel, the method further includes:

Step S12, determining the measurement mode, and different measurement modes correspond to corresponding times of vector signal tests.

Among them, the measurement mode can be a signal delay measurement mode pre-set by the ATE according to the number of times the vector signal test is performed on the channel. For example, according to different measurement requirements, one or more measurement modes such as performance mode, balanced mode, and fast mode can be provided. Among the three measurement modes, the performance mode has the most tests, the smallest timing phase point movement interval, and the highest test accuracy; the balanced mode has a medium number of tests, a medium timing phase point movement interval, and moderate test accuracy and test time; the fast mode has the least number of tests, the largest timing phase point movement interval, and the least test time. That is, the number of tests in the performance mode, the number of tests in the balanced mode, and the number of tests in the fast mode decrease in sequence; the test accuracy of the performance mode, the test accuracy of the balanced mode, and the test accuracy of the fast mode decrease in sequence; the timing phase point movement interval of the performance mode, the timing phase point movement interval of the balanced mode, and the timing phase point movement interval of the fast mode increase in sequence.

Step S14: determining a preset standard for the number of times of the vector signal test according to the measurement mode.

Specifically, due to different measurement modes, the number of tests is usually different, so the preset standard for the number of vector signal tests can be determined according to different measurement modes.

In the above embodiment, according to the different measurement requirements of the chip tester signal delay, a measurement mode adapted to the actual requirements can be determined to avoid the mechanization and fixation of the measurement process and to more efficiently achieve the measurement of the signal delay time.

In one embodiment, as shown in FIG5 , moving the position of the timing phase point includes:

Step S302, obtaining the current test order.

The current test order is the order of the vector signal test that the ATE is currently going to perform in the vector signal test that has been performed by the ATE during the current signal delay measurement process. It should be understood that the signal delay measurement method provided in the embodiment of the present solution includes a process of performing vector signal tests on the target channel multiple times. For example, if the number of vector signal tests is preset to 10 times in the signal delay measurement, then after the first vector signal test, the current test order is 2; after the fourth vector signal test, the current test order is 5.

Step S304, calculating the displacement distance according to the current test order and the preset moving point steps.

The moving point step can be a fixed time value.

Specifically, the displacement distance is obtained by multiplying the current test order by the preset moving point step. For example, if the current test order is 2 and the moving point step is 20 pS (picoseconds), the displacement distance is 40 pS.

Step S306, moving the timing phase point by the displacement distance to a target position.

Specifically, the timing phase point may be moved backward by a displacement distance. For example, when the displacement distance is 40 pS, the timing phase point is moved backward by 40 pS on the time axis. In some other implementations, the timing phase point may also be moved forward by the displacement distance.

In the above embodiment, the moving rule of the timing phase point can be defined by setting the moving point step according to the test order. Then, it can be reused without manual definition and calculation. In this way, the problem of repeatedly confirming the movement of the timing phase point due to different test times is avoided. In addition, according to the pre-defined movement rules, the time difference between the timing phase point and the start of the vector signal test can be reversely obtained according to the test results, so as to further determine the signal time delay.

Fig. 6 is a schematic diagram of the accumulation result of data accumulation for the data to be processed in one embodiment. As shown in Fig. 6, Cycle represents the cycle, which can be used to calculate the row number of the edge; CH0, CH1, CH62, and CH63 represent the numbers of the target channels, and the target channels numbered CH2 to CH61 are omitted between CH1 and CH62 in Fig. 6; N and N+1 represent the number of cycles.

According to the method of moving the timing phase point in steps S304 to S306 and the data accumulated by converting the level comparison results of the timing phase point in steps S208 to S210, performing the delay operation based on the result of the vector signal test in step S50 may include:

The row number and weighted position of the edge are searched in the data accumulated in the target channel, and the signal delay time is calculated according to the row number and the weighted position.

The edge refers to the position where the level of the timing phase point jumps above the preset comparison level. For example, in FIG6 , the position where the number representing the level comparison result changes from 0 to 1 corresponds to the position where the vector signal jumps is the edge. The number of rows is the number of complete cycles before the edge. For example, the edge in FIG6 is in the Nth cycle, and there are N-1 complete cycles before it, then the number of rows is N-1. The weighted position may include an initial weighted bit and a stepping bit. The initial weighted bit is the initial position of the timing phase point in the cycle. The stepping bit is the distance that the timing phase point moves according to the comparison point stepping. The stepping bit can be obtained by the comparison point stepping and the number of tests.

Specifically, the number of rows is multiplied by the period (the basic time can be obtained), and the resulting product is summed with the weighted position (additional time) to obtain the signal delay time.

Specifically, after the signal delay time is obtained, time compensation data can be generated according to actual needs. For example, if the signal delay time obtained in step S50 is 5 nanoseconds, 5 nanoseconds can be used as the time compensation data.

In some other implementations, a compensation file or compensation program may be generated based on the time compensation data. The compensation file or compensation program may be written into the storage module of the chip tester itself or into an external memory, and is used to implement timing compensation of the chip tester signal after being executed by the chip tester, so that the time when the signal reaches the end of the channel meets the actual requirements.

In the above embodiment, time compensation data can be generated by the signal delay time, and further a compensation file can be generated, etc., which can be used by the chip tester to implement timing compensation and timing synchronization of the signal. In this way, the time when the test signal or vector signal sent by the chip tester arrives at the end of the channel can meet the requirements of chip testing.

In one embodiment, as shown in FIG7 , after obtaining the signal delay time, the method further includes:

Step S62, changing the length of the target channel.

Specifically, the length of the target channel can be changed by increasing or decreasing the length of the line between the ATE main control chip and the connection port of the chip to be tested.

Step S64, measuring the signal delay of the modified target channel to obtain the displacement signal delay time.

The displacement signal delay time is the delay time for the signal to reach the end of the channel after the length of the target channel changes.

Specifically, after changing the length of the target channel, steps S20 to S50 are executed, and the displacement signal delay time is obtained by step S50. In some other implementations, steps S30 to S50 may also be executed to obtain the displacement signal delay time. It should be understood that the process of measuring the signal delay of the target channel after the length is changed may be consistent with or inconsistent with the measurement process before the change.

Step S66, generating displacement difference time compensation data according to the difference between the signal delay time and the displacement signal delay time.

According to the principle of time domain reflection, the time length increment of the reflection superposition area is consistent with the end line length increment. Therefore, the signal delay time measured before the target channel length is changed can be compared with the displacement signal measured after the target channel length is changed. The difference can represent the signal delay time caused by the increase or decrease of the target channel length, and the corresponding time compensation data can be generated according to the difference.

In the above embodiment, by measuring the signal delay twice before and after the target channel length is changed, and generating time compensation data according to the difference of the obtained results, the problem of being unable to determine the signal delay time due to the change of the channel line length is avoided.

It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

According to another aspect of the embodiment of the present disclosure, as shown in FIG8 , a chip tester signal delay measurement device is further provided, comprising:

Testing module 602, used to perform vector signal testing on the target channel; the vector signal testing uses a test vector signal with timing phase points generated by the chip tester;

A timing module 604, used to move the position of the timing phase point;

The main control module 606 is used to control the timing module to repeatedly move the position of the timing phase point, and is also used to control the test module to re-perform the vector signal test on the target channel until the number of vector signal tests reaches a preset standard;

The data processing module 608 is used to obtain the level comparison results of the number of times after the number of times of the vector signal test reaches a preset standard, and perform delay calculation based on the level comparison results of the number of times to obtain the signal delay time.

For the specific limitations of the above-mentioned chip tester signal delay measurement device, please refer to the limitations of the above-mentioned chip tester signal delay measurement method, which will not be repeated here. Each module in the above-mentioned chip tester signal delay measurement device can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

FIG9 is a schematic diagram of the structure of a chip tester signal delay compensation measurement system in an embodiment, comprising: a host computer 70 and a programmable logic device center 80. The host computer 70 and the programmable logic device center 80 can communicate via a high-speed serial bus. The programmable logic device center 80 can be an FPGA device. The host computer 70 can be an electronic device including a processor, such as a computer device, an industrial computer including a CPU or an MCU, an electronic device based on an embedded operating system, etc. The host computer 70 can also read an external preset engineering file to obtain measurement information such as measurement-related instructions and parameters.

Wherein, the host computer 70 includes:

The main control measurement module 702 is used to set the preset number of vector signal tests on the target channel according to the measurement mode; it is also used to control the entire measurement process after the signal delay measurement starts until the number of vector signal tests on the target channel reaches the preset number and the measurement is completed.

The pattern control module 704 is used to control the pattern data and instruction delivery, set the cycle and timing phase point, set the output level specification, compare the level amplitude, etc. The pattern control module 704 includes a timing control unit 7041 and a level control unit 7042. The timing control unit 7041 is used to set the initial position of the timing phase point in the pattern and also to move the timing phase point. The level control unit 7042 is used to control the level of the generated pattern.

The data reading and parsing module 706 is used to read the level comparison result in the comparison data reader/writer 808 after each pattern test, and can also be used to perform binary conversion on the level comparison result to obtain data to be processed.

The data accumulation and processing module 708 is used to accumulate and cache the data to be processed, and is also used to process the accumulated and cached data after all pattern tests are completed to obtain signal delay compensation data.

The file generation module 710 is used to generate a delay compensation file according to the signal delay compensation data and save it to the memory of the chip tester.

The programmable logic device center 80 includes:

The Pattern data storage module 802 is used to store data related to the Pattern. The Pattern data storage module 802 includes a timing parameter storage unit 8021 and a level parameter storage unit 8022. The timing parameter storage unit 8021 is used to store the position of the timing phase point in the Pattern. The level parameter storage unit 8022 is used to store the level parameters of the Pattern.

The output module 804 is used to output a test vector signal to a target channel according to the stored Pattern data.

The receiving and comparing module 806 is used to receive the reflected vector signal returned by the target channel, and compare the level at the timing phase point in the reflected vector signal with a preset comparison level to obtain a level comparison result.

The comparison data reader/writer 808 is used to record the level comparison result. The programmable logic device center 80 can store the result into DDR (Double Data Rate, double rate synchronous dynamic random access memory) through the comparison data reader/writer 808, and read back the comparison result of each cycle in this test after the pattern test is completed.

It should be understood that the chip tester signal delay compensation measurement system shown in FIG. 9 can be applied to an ATE chip tester having the system operation environment.

In one embodiment, as shown in FIG. 10 , a chip tester signal delay compensation measurement method is provided, which can be applied to the chip tester signal delay compensation measurement system shown in FIG. 9 , and the measurement method includes:

The host computer 70 downloads a preset engineering file to the chip tester; the preset engineering file includes configuration information such as the content of the pattern to be tested, level parameters, timing parameters, and measurement mode designed according to the time domain reflection principle;

The main control measurement module 702 obtains configuration information and starts measurement; sets the preset number of vector signal tests on the target channel according to the measurement mode in the preset project, moves the timing phase point, and sends the relevant pattern data such as the pattern content to be tested, level parameters, timing parameters, etc. to the pattern control module 704;

The Pattern control module 704 sends the Pattern data of the current vector signal test to the Pattern data storage module 802 of the programmable logic device center 80;

The output module 804 runs the Pattern test and outputs the test vector signal to the target channel according to the Pattern data in the Pattern data storage module 802;

The receiving and comparing module 806 obtains the reflected vector signal data returned by the target channel, and compares the level at the timing phase point in the reflected vector signal with the preset comparison level to obtain a level comparison result;

The comparison data reader 808 records the level comparison result and sends the level comparison result to the data reading and parsing module 706; after the data reading and parsing module 706 reads the level comparison result, it performs binary conversion on the level comparison result to obtain the data to be processed, and the data accumulation and processing module 708 accumulates and caches the data to be processed;

After the number of vector signal tests on the target channel reaches a preset number, the data accumulation and processing module 708 processes the accumulated and cached data to obtain signal delay compensation data;

The file generating module 710 generates a delay compensation file according to the signal delay compensation data.

FIG. 11 is a flow chart of a method for implementing timing compensation in an embodiment, which can be applied to the chip tester signal delay compensation measurement system shown in FIG. 9 . The method includes:

In response to the instruction to start compensation, checking whether the compensation file is legal; wherein the compensation file may be a delay compensation file generated by the file generation module 710 in FIG. 9 according to the signal delay compensation data;

If the compensation file is legal, read the compensation file data;

Applying the compensation file data to the timing control unit 7041;

Before the test starts, the compensation file data is sent to the timing parameter storage unit 8021 of the programmable logic device center 80; the compensation file data is used to compensate the timing parameters to achieve timing compensation and timing synchronization of the signal.

According to another aspect of the embodiment of the present disclosure, a computer device is provided, which may be a terminal, and its internal structure diagram may be shown in FIG12. The computer device includes a processor, a memory, a communication interface, a display screen, and an input device connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores operating The computer device is a computer program and an operating system. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be achieved through WIFI, an operator network, NFC (near field communication) or other technologies. The computer program is executed by the processor to implement the above-mentioned measurement method. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covered on the display screen, or a button, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse, etc.

Those skilled in the art will understand that the structure shown in FIG. 12 is merely a block diagram of a partial structure related to the scheme of the present disclosure, and does not constitute a limitation on the computer device to which the scheme of the present disclosure is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

In one embodiment, a computer device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above method embodiments when executing the computer program.

According to another aspect of an embodiment of the present disclosure, a chip tester is provided, which includes a processor and a memory. The memory includes a non-volatile storage medium and an internal memory, and a computer program is stored in the memory. The processor is used to provide computing and control capabilities, and the processor implements the steps in the above-mentioned method embodiments when executing the computer program. In some other implementations, the memory may also be an external memory.

According to another aspect of an embodiment of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), tape, floppy disk, flash memory or optical memory, etc. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in the embodiments provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic unit, a data processing logic unit based on quantum computing, etc., but is not limited thereto.

The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

The above-mentioned embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the disclosed patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent disclosed herein shall be subject to the attached claims.

Claims

A chip tester signal delay measurement method, characterized in that the method comprises:

Performing a vector signal test on the target channel; the vector signal test uses the chip tester to generate a test vector signal with timing phase points;

The vector signal test on the target channel includes: sending the test vector signal to the target channel; obtaining a reflected vector signal of the test vector signal; comparing the level at the timing phase point in the reflected vector signal with a preset comparison level, and recording the level comparison result;

After the vector signal test is completed, the position of the timing phase point is moved, and the vector signal test is performed on the target channel again;

Repeatingly moving the position of the timing phase point and re-performing a vector signal test on the target channel until the number of vector signal tests reaches a preset standard;

When the number of times of the vector signal test reaches a preset standard, the level comparison results of the number of times are obtained, and a delay operation is performed based on the level comparison results of the number of times to obtain a signal delay time.
The method according to claim 1, characterized in that after recording the level comparison result, it also includes:

Performing binary processing on the level comparison result to obtain data to be processed;

The data to be processed are accumulated; the result of the data accumulation is used to perform a delay operation when the number of times the vector signal is tested reaches a preset standard to obtain the signal delay time.
The method according to claim 2, characterized in that the step of performing binary processing on the level comparison result to obtain the data to be processed comprises:

The level of the timing phase point is compared with a preset comparison level, and the data to be processed is obtained based on the comparison result.
The method according to claim 1, characterized in that before performing a vector signal test on the target channel, it also includes:

Determine the measurement mode. Different measurement modes correspond to the number of vector signal tests.

A preset standard for the number of times the vector signal test is performed is determined according to the measurement mode.
The method according to claim 4, characterized in that the measurement mode comprises: a group consisting of a performance mode test, a balance mode test, and a fast mode test;

The number of tests in the performance mode, the number of tests in the balanced mode, and the number of tests in the fast mode decrease in sequence;

The test accuracy of the performance mode, the test accuracy of the balanced mode, and the test accuracy of the fast mode decrease in sequence;

The timing phase point shift interval of the performance mode, the timing phase point shift interval of the balance mode, and the timing phase point shift interval of the fast mode increase in sequence.
The method according to claim 1, characterized in that the moving the position of the timing phase point comprises:

Get the current test order;

Calculating the displacement distance according to the current test sequence and the preset moving point step;

The timing phase point is moved by the displacement distance to a target position.
The method according to claim 1, characterized in that after obtaining the signal delay time, it also includes:

Time compensation data is generated according to the signal delay time, and the time compensation data is used by the chip tester to implement signal timing compensation.
The method according to claim 1, characterized in that after obtaining the signal delay time, it also includes:

changing the length of the target channel;

The signal delay of the changed target channel is measured to obtain the displacement signal delay time;

The displacement difference time compensation data is generated according to the difference between the signal delay time and the displacement signal delay time.
The method according to claim 1, characterized in that the moving the position of the timing phase point comprises:

Setting the comparison point step, wherein the comparison point step is a fixed time value;

The timing phase point is moved within a period by a distance of the comparison point step.
The method according to claim 9, characterized in that the level comparison result based on the number of times Perform delay calculation to obtain the signal delay time, including:

In the level comparison results of the number of times, searching for a timing phase point whose level at the timing phase point is greater than a preset comparison level, to obtain a target timing phase point;

According to the cycle number of the target timing phase point, the basic time is obtained;

Calculating the additional time according to the initial position of the target timing phase point, the number of times, and the size of the comparison point step;

The basic time is added to the additional time to obtain a signal delay time.
The method according to any one of claims 1 to 10 is characterized in that the test vector signal is pre-set with a timing phase point in each cycle, and the position of the timing phase point in each cycle is consistent.
The method according to any one of claims 1 to 11, characterized in that sending the test vector signal to the target channel comprises:

The end of the target channel is set to an open circuit state, and a test vector signal with a timing phase point is sent to the target channel; the target channel is a line channel that sends a signal to a placement point of the chip to be tested.
A chip tester signal delay measurement device, characterized by comprising:

A test module is used to perform a vector signal test on a target channel; the vector signal test uses a test vector signal with a timing phase point generated by the chip tester; the vector signal test on the target channel includes: sending the test vector signal to the target channel; obtaining a reflected vector signal of the test vector signal; comparing the level at the timing phase point in the reflected vector signal with a preset comparison level, and recording the level comparison result;

A timing module, used for moving the position of the timing phase point;

A main control module, used to control the timing module to repeatedly move the position of the timing phase point, and also used to control the test module to re-perform a vector signal test on the target channel until the number of vector signal tests reaches a preset standard;

And, a data processing module is used to obtain the level comparison results of the number of times after the number of times of the vector signal test reaches a preset standard, and perform delay calculation based on the level comparison results of the number of times to obtain the signal delay time.
A computer device comprises a memory and a processor, wherein the memory stores a computer program, and wherein the processor implements the steps of any one of the methods of claims 1 to 12 when executing the computer program.
A chip testing machine comprises a memory and a processor, wherein the memory stores a computer program, and wherein the processor implements the steps of any one of the methods of claims 1 to 12 when executing the computer program.