CN116629171A - FPGA chip debugging method and device based on synthesized netlist - Google Patents

FPGA chip debugging method and device based on synthesized netlist Download PDF

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Publication number
CN116629171A
CN116629171A CN202310539653.6A CN202310539653A CN116629171A CN 116629171 A CN116629171 A CN 116629171A CN 202310539653 A CN202310539653 A CN 202310539653A CN 116629171 A CN116629171 A CN 116629171A
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fpga
netlist
debugging
core
file
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刘建洋
朱维良
王海力
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Jingwei Qili Beijing Technology Co ltd
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Jingwei Qili Beijing Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

According to the FPGA chip debugging method and device based on the synthesized netlist, the FPGA development software is utilized to synthesize the FPGA engineering file, and the original FPGA synthesized netlist is determined; selecting a data signal and a clock signal of the data signal in the synthesized netlist, determining a constraint file of an FPGA engineering file, automatically generating a register transmission level debugging IP core according to the constraint file, and then comprehensively converting the register transmission level debugging IP core into a second netlist of the FPGA; determining a debugging function module based on the second netlist, inserting the debugging function module into the original FPGA synthetic netlist, generating a code stream file according to the constraint file and the FPGA synthetic netlist inserted with the debugging function module, configuring and operating the FPGA, and debugging the FPGA by using a real-time debugging tool. The technical problem that the module of the problem can not be positioned rapidly and accurately when the working state of the FPGA chip is inconsistent with the expected state is solved, and meanwhile, the debugging process can also influence the normal design of the FPGA is solved.

Description

FPGA chip debugging method and device based on synthesized netlist
Technical Field
The application relates to the field of FPGA design, in particular to an FPGA chip debugging method based on a synthesized netlist.
Background
The debugging of the FPGA chip is a very important step for ensuring the design correctness of the FPGA, and through various debugging methods, engineers can check the design correctness, functions, time sequence, performance and other aspects, and ensure the quality and stability of the FPGA chip.
Common debugging methods in the prior art include emulation debugging, hardware debugging, logic analyzer debugging, slow clock debugging, and cold start and hot start debugging. Simulation debugging is the most basic method in FPGA design. The method can simulate the circuit behavior through simulation software on a computer before the design is actually downloaded to the FPGA for debugging and verification. Through simulation debugging, the design correctness, functions, time sequence, performance and other aspects can be checked. The hardware debugging is to connect the FPGA chip with the actual circuit board and observe and detect the behavior and performance of the chip through various test instruments. Hardware debugging can help engineers locate and solve problems quickly in an actual hardware environment. Logic analyzers are a tool for analyzing and monitoring the behavior of FPGA chips. The circuit can help engineers to capture information such as signal waveform, time sequence and state of the circuit, and the problem can be rapidly positioned and solved. Logic analyzer debugging is commonly used to solve timing problems, clock problems, interface problems, and the like. Slow clock debugging can help engineers observe circuit behavior at lower speeds by slowing down clock frequency, making it easier to locate and solve problems. Slow clock debugging is commonly used to address timing issues, clock synchronization issues, state machine issues, and the like. Cold start and hot start refer to the behavior of an FPGA chip in an initial state and in an operational state. By observing and analyzing the behavior of the FPGA chip in different starting modes, engineers can be helped to locate and solve the problems. Cold-start and hot-start debugging are commonly used to address timing issues, interface issues, state machine issues, and the like.
However, in the debugging method in the prior art, when the working state of the FPGA chip is inconsistent with the expected working state, the module with the problem can not be positioned quickly and accurately, and meanwhile, the debugging process can also influence the normal design of the FPGA.
Disclosure of Invention
In order to solve the problems in the prior art, the embodiment of the application provides an FPGA chip debugging method and device based on a synthesized netlist.
In a first aspect, the present application provides a method for debugging an FPGA chip based on a synthesized netlist, the method comprising:
acquiring an engineering file of the FPGA, and synthesizing the engineering file of the FPGA by utilizing FPGA development software to determine a first netlist of the FPGA; the first netlist is an original FPGA synthetic netlist;
selecting a data signal in the first netlist and a clock signal of the data signal by using a debugging tool, and determining a constraint file of the FPGA engineering file;
obtaining a first IP core according to the constraint file, and comprehensively determining a second netlist of the FPGA based on the first IP core by utilizing FPGA development software; wherein the second netlist is an independent synthesized netlist without I/O; the first IP core is a register transmission level debugging IP core and is used for realizing the debugging functions of FPGA signal capturing, counter statistics and state tracking;
performing instantiation on a second IP core according to the second netlist to determine a debugging function module of the FPGA, and inserting the debugging function module into the first netlist to obtain a third netlist; the second IP core is a debugging IP core in a gate-level form; the functional module comprises a data port and a clock port of the second IP core, and the data port and the clock port are respectively connected with a data signal and a clock signal of the data signal; the third netlist is an FPGA (field programmable gate array) synthesized netlist inserted with a debugging functional module;
generating an FPGA configuration code stream according to the third netlist;
and configuring and operating the FPGA according to the FPGA configuration code stream, and debugging the data signals and the clock signals of the data signals by using a real-time debugging tool.
On the other hand, the embodiment of the application provides an FPGA chip debugging device based on a synthesized netlist, which comprises the following components:
the debugging and inserting module is used for acquiring an engineering file of the FPGA, and synthesizing the FPGA engineering file by utilizing FPGA development software to determine a first netlist of the FPGA; determining a constraint file of the FPGA engineering file according to the data signal in the first netlist and the clock signal of the data signal; obtaining a first IP core according to the constraint file, and comprehensively determining a second netlist of the FPGA based on the first IP core by utilizing FPGA development software; instantiating a second IP core according to the second netlist to determine a debugging functional module, and inserting the debugging functional module into the first netlist to obtain a third netlist;
the first netlist is an original FPGA synthetic netlist; the second netlist is an independent synthesized netlist without I/O; the first IP core is a register transmission level debugging IP core and is used for realizing the debugging functions of FPGA signal capturing, counter statistics and state tracking; the second IP core is a debugging IP core in a gate-level form; the functional module comprises a data port and a clock port of the second IP core, and the data port and the clock port are respectively connected with a data signal and a clock signal of the data signal; the third netlist is an FPGA (field programmable gate array) synthesized netlist inserted with a debugging functional module;
the code stream generation module is used for carrying out layout on the logic circuits of the FPGA according to the third netlist to determine the placed logic circuits; connecting the placed logic circuits according to the third netlist, and determining a design file of the FPGA; generating an FPGA configuration code stream according to the design file of the FPGA; the design files of the FPGA comprise integrated design files for realizing logic circuit layout and connection;
the chip debugging module is used for configuring and running the FPGA based on the FPGA configuration code stream, and debugging the data signals and the clock signals of the data signals by using a real-time debugging tool.
In another aspect, an embodiment of the present application provides an electronic device, including a memory, and a processor, where the memory stores a computer program that can run on the processor, and the method is characterized in that the processor implements the above evaluation method implemented for an algorithm in a chip design when executing the computer program.
In another aspect, an embodiment of the present application provides a computer readable medium having non-volatile program code executable by a processor, where the program code causes the processor to perform the above-mentioned evaluation method implemented for an algorithm in a chip design.
Compared with the prior art, the FPGA chip debugging method and device based on the synthesized netlist provided by the embodiment of the application have the advantages that the FPGA development software is utilized to synthesize the FPGA engineering file, and the original FPGA synthesized netlist is determined; selecting a data signal and a clock signal of the data signal in the synthesized netlist, determining a constraint file of an FPGA engineering file, automatically generating a register transmission level debugging IP core according to the constraint file, and then comprehensively converting the register transmission level debugging IP core into a second netlist of the FPGA; determining a debugging function module based on the second netlist, inserting the debugging function module into the original FPGA synthetic netlist, generating a code stream file according to the constraint file and the FPGA synthetic netlist inserted with the debugging function module, configuring and operating the FPGA, and debugging the FPGA by using a real-time debugging tool. The technical problem that the module of the problem can not be positioned rapidly and accurately when the working state of the FPGA chip is inconsistent with the expected state is solved, and meanwhile, the debugging process can also influence the normal design of the FPGA is solved.
Drawings
FIG. 1 is a flow diagram of a method for debugging an FPGA chip based on a synthesized netlist;
FIG. 2 is a schematic diagram of a constraint file according to an embodiment of the present application;
FIG. 3 is a schematic diagram of an FPGA chip debugging device based on a synthesized netlist.
Detailed Description
In order to solve the technical problem that the module which cannot quickly and accurately locate the problem when the working state of the FPGA chip is inconsistent with the expected working state can also influence the normal design of the FPGA in the debugging process. The embodiment of the application discloses an FPGA chip debugging method and device based on a synthesized netlist.
The terms first, second and the like in the description and in the claims and in the above-described figures, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and are merely illustrative of the manner in which embodiments of the application have been described in connection with the description of the objects having the same attributes. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
The embodiment of the application provides an FPGA chip debugging method based on a synthesized netlist, and FIG. 1 is a flow chart of the FPGA chip debugging method based on the synthesized netlist, and the method comprises the following steps:
s110: determining an original FPGA-synthesized netlist (first netlist)
The embodiment of the application synthesizes the engineering files of the FPGA by adopting self-designed FPGA development software to generate an original FPGA synthesized netlist, and the FPGA development software is also used for controlling the generation flow of the debugging functional module and inserting the generated debugging functional module into the synthesized netlist.
The original FPGA synthesis netlist is an AMV netlist, and is easier to read and understand than a common netlist. The method can be used for verifying the correctness of the design, checking logic and timing problems in the design and optimizing the design performance of the FPGA.
The determination of the AMV netlist is implemented as follows.
Firstly, obtaining a specific FPGA engineering file of a user;
then, the FPGA development software converts the engineering file into a synthesized RTL code, and converts the RTL code into a logic gate-level netlist;
and finally, synthesizing by FPGA development software to obtain an original AMV netlist.
The AMV netlist comprises connection lines and logic relations among all logic elements in the FPGA design, and the connection lines and the logic relations comprise key information for displaying macro units, pins, input/output delays and the like in an FPGA chip, wherein the key information can be read and analyzed by FPGA development software, and various optimization and constraint processing are carried out on the AMV netlist according to the key information.
In the process, the obtained AMV netlist and the constraint file generated based on the AMV netlist are transmitted to a subsequent layout and wiring tool for generating physical layout and connection lines of the FPGA, and finally bit files are generated and then downloaded to an FPGA chip for operation. Helping designers to quickly understand and debug designs.
S120: determining constraint files of FPGA engineering files
The embodiment of the application adopts a self-designed debugging tool, selects Data signals (Data Net and Clock) which need to be observed in the AMV netlist generated in the step S110, wherein the Data signals are usually represented by output pins, the Clock signals are usually represented by input pins, finds the output pins and the input pins which need to be observed, records the names of the output pins and the input pins for storage, and generates constraint files of the FPGA engineering file.
The debug tool may be inserted into a variety of debug modules such as a signal capture module, a counter module, a state machine module, and the like. These modules may be used for a variety of debug purposes such as capture signals, counter statistics, state tracking, etc.
By inserting the debugging modules into the FPGA chip, a designer can know the designed operation condition more deeply, and can adjust and optimize correspondingly aiming at the problem.
In the embodiment of the application, the determination of the constraint file specifically selects the data signal and the clock signal of the data signal in the first AMV netlist through the debugging tool, configures the LA Core of the FPGA, and adds constraint conditions to limit paths of the data signal and the clock signal. And finally, determining constraint files of the FPGA engineering files.
The FPGA in the embodiment of the application comprises 4 LA cores, wherein the LA cores comprise clock frequency, channel number, storage depth and configuration parameters of a trigger of the FPGA;
the constraint file comprises FPGA clock, time sequence, pins and physical related constraints. FIG. 2 is a schematic diagram of a constraint file in an embodiment of the present application, where the embodiment configures a single LA_CORE, including configuration parameters of set_property-debug_core_name and connect_debug_port_name, and configures debug_core and Data Net, respectively.
S130: determining a second netlist of the FPGA
In the embodiment of the application, the second netlist is an independent AIV netlist without I/O. The AIV netlist is a netlist form of FPGA design after technical mapping, RTL level codes of a register transmission level can be converted into a logic netlist suitable for an FPGA device, so that hardware description of the FPGA device is realized, and besides connection lines and logic relations among logic elements are included, the AIV netlist also comprises information such as time sequence constraint and physical constraint.
The constraint information can help the FPGA development software and the debugging tool to conduct more accurate and efficient design, so that a more optimized FPGA design is finally generated. Determining the AIV netlist is an important step in the FPGA design flow in the embodiments of the application, and can be used for functional verification and simulation before synthesis and layout and wiring.
The embodiment of the application determines the specific implementation of the AIV netlist as follows.
Firstly, based on the constraint file obtained in the step S120, a user selects a self-designed register transmission level Debug IP (Debug IP) (first IP core) in FPGA development software according to a function, wherein the Debug IP core is mainly used for realizing Debug functions of FPGA signal capturing, counter statistics and state tracking.
And then, utilizing FPGA development software to comprehensively determine an AIV netlist of the FPGA based on the register transmission level debugging IP core.
S140: obtaining a debug function module and inserting an AMV netlist
First, a debug IP core (second IP core) in a gate level form is selected in FPGA development software based on a user according to a function requirement.
Then, the FPGA development software is utilized to determine a debugging functional module of the FPGA by instantiating the gate-level form debugging IP core based on the AIV netlist obtained in the step 130.
The gate-level type debugging IP core comprises a module for realizing FPGA signal capturing, counter statistics and state tracking, and after instantiation, the debugging functional module comprises a data port and a clock port of the gate-level type debugging IP core.
Finally, the determined debugging function module is inserted into the original integrated AMV netlist to obtain an FPGA integrated netlist (third netlist) inserted with the debugging function module.
In the implementation process, the AIV netlist is further confirmed through Edit, which is an important task in the FPGA design process, and can help engineers modify and debug codes to ensure the correctness and performance of the circuits.
In the embodiment of the application, the circuit of the FPGA is mainly optimized to improve the performance and efficiency of the FPGA, and logic problems exist in the FPGA design through edition correction.
When the edition is confirmed to pass, continuing to generate an FPGA configuration code stream in step S150; if the edition confirmation is not passed, returning to the step S120, reselecting the data signal in the original integrated AMV netlist and the clock signal of the data signal to configure the LA Core of the FPGA, and continuing the subsequent steps after the configuration is completed.
S150: generating FPGA configuration code stream
After obtaining the FPGA synthesized netlist (third netlist) with the inserted debugging function module generated in step S140, generating a code stream of the FPGA based on the third netlist, in the embodiment of the application, the FPGA configuration code stream is mainly generated by Placer, router and Bitgen software, which is specifically implemented as follows:
placing the logic circuit of the FPGA on the basis of the third netlist by using Placer software to determine a placed logic circuit;
connecting the placed logic circuits based on the third netlist by using Router software to determine a design file of the FPGA; the design files of the FPGA comprise integrated design files for realizing logic circuit layout and connection;
and generating an FPGA configuration code stream based on the design file of the FPGA by using Bitgen software.
S160: debugging FPGA
And configuring and running the FPGA based on the FPGA configuration code stream, and debugging the data signals and the clock signals of the data signals by using a Real Time Debug tool.
The Real Time Debug tool of the embodiment of the application is a self-designed Debug tool, comprises a Real-Time monitoring interface which is convenient for a user to Debug, monitors the FPGA in Real Time by connecting hardware module interfaces such as a data port, a clock port and the like, acquires state information, and debugs and Debug the FPGA.
The embodiment of the application provides an FPGA chip debugging device based on a synthesized netlist, and FIG. 3 is a schematic diagram of the FPGA chip debugging device based on the synthesized netlist, and as shown in the figure, the device comprises:
s310: debugging plug-in module
The debugging insertion module is used for obtaining the engineering file of the FPGA, and synthesizing the FPGA engineering file by utilizing FPGA development software to determine a first netlist of the FPGA.
And determining a constraint file of the FPGA engineering file according to the data signals in the first netlist and the clock signals of the data signals.
And obtaining a first IP core according to the constraint file, and comprehensively determining a second netlist of the FPGA based on the first IP core by utilizing FPGA development software.
And instantiating the second IP core according to the second netlist to determine a debugging functional module, and inserting the debugging functional module into the first netlist to obtain a third netlist.
The first netlist is an original FPGA synthetic netlist; the second netlist is an independent synthesized netlist without I/O; the first IP core is a register transmission level debugging IP core and is used for realizing the debugging functions of FPGA signal capturing, counter statistics and state tracking; the second IP core is a debugging IP core in a gate level form.
The functional module comprises a data port and a clock port of the second IP core, wherein the data port and the clock port are respectively connected with a data signal and a clock signal of the data signal; the third netlist is an FPGA synthesis netlist inserted with a debugging function module.
S320: and a code stream generating module:
the code stream generating module lays out the logic circuits of the FPGA according to the third netlist to determine the well-placed logic circuits; connecting the placed logic circuits according to the netlist to determine a design file of the FPGA; and generating an FPGA configuration code stream according to the design file of the FPGA.
The design files of the FPGA comprise integrated design files for realizing the layout of the logic circuit and the connection lines.
S330: chip debugging module:
the chip debugging module is used for configuring and running the FPGA based on the FPGA configuration code stream, and debugging the data signals and clock signals of the data signals by using a real-time debugging tool.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present application without undue burden.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
According to the FPGA chip debugging method based on the synthesized netlist, the FPGA development software is utilized to synthesize the FPGA engineering file, and the original FPGA synthesized netlist is determined; selecting a data signal in the AMV netlist and a clock signal of the data signal, determining a constraint file of an FPGA engineering file, and determining a second netlist of the FPGA based on a register transmission level debugging IP core selected by a user according to functions; determining a debugging function module based on the second netlist, inserting the debugging function module into the AMV netlist, configuring and operating the FPGA according to the constraint file and the code stream file generated by the AMV netlist, and debugging the FPGA by using a real-time debugging tool. The technical problem that the module of the problem can not be positioned rapidly and accurately when the working state of the FPGA chip is inconsistent with the expected state is solved, and meanwhile, the debugging process can also influence the normal design of the FPGA is solved.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the application, and is not meant to limit the scope of the application, but to limit the application to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the application are intended to be included within the scope of the application.

Claims (10)

1. An FPGA chip debugging method based on a synthesized netlist is characterized by comprising the following steps:
acquiring an engineering file of the FPGA, and synthesizing the engineering file of the FPGA by utilizing FPGA development software to determine a first netlist of the FPGA; the first netlist is an original FPGA synthetic netlist;
selecting a data signal in the first netlist and a clock signal of the data signal by using a debugging tool, and determining a constraint file of the FPGA engineering file;
obtaining a first IP core according to the constraint file, and comprehensively determining a second netlist of the FPGA based on the first IP core by utilizing FPGA development software; wherein the second netlist is an independent synthesized netlist without I/O; the first IP core is a register transmission level debugging IP core and is used for realizing the debugging functions of FPGA signal capturing, counter statistics and state tracking;
instantiating a second IP core according to the second netlist to determine a debugging functional module of the FPGA, and inserting the debugging functional module into the first netlist to obtain a third netlist; the second IP core is a debugging IP core in a gate-level form; the functional module comprises a data port and a clock port of the second IP core, and the data port and the clock port are respectively connected with a data signal and a clock signal of the data signal; the third netlist is an FPGA (field programmable gate array) synthesized netlist inserted with a debugging functional module;
generating an FPGA configuration code stream according to the third netlist;
and configuring and operating the FPGA according to the FPGA configuration code stream, and debugging the data signals and the clock signals of the data signals by using a real-time debugging tool.
2. The method for debugging a synthesized netlist based FPGA chip of claim 1, wherein the first netlist includes key information for displaying macro cells, pins, input/output delays, timing information in the FPGA chip.
3. The method for debugging the FPGA chip based on the synthesized netlist according to claim 1, wherein the debugging tool comprises a debugging module of a signal capturing, a counter and a state machine;
the debugging module of the signal capturing, counter and state machine is inserted into the FPGA and used for debugging the tool in real time to realize the debugging functions of the FPGA for capturing signals, counting the counter and tracking the state.
4. The method for debugging the FPGA chip based on the synthesized netlist according to claim 1, wherein the method for determining the constraint file of the FPGA engineering file comprises:
selecting a data signal in a first netlist and a clock signal of the data signal by using a debugging tool to configure the LA Core of the FPGA, and determining a constraint file of an FPGA engineering file;
the FPGA comprises 4 LA cores, wherein the LA cores comprise clock frequency, channel number, storage depth and configuration parameters of a trigger of the FPGA.
5. The method for debugging a synthesized netlist-based FPGA chip of claim 4, wherein the connecting further comprises:
confirming the third netlist through Edit;
if the confirmation is passed, continuing to generate an FPGA configuration code stream;
and if the confirmation is not passed, reselecting the data signals in the first netlist and the clock signals of the data signals to configure the LA Core of the FPGA.
6. The method for debugging the FPGA chip based on the synthesized netlist of claim 1, wherein the constraint file includes a clock, a timing sequence, pins and physical constraint information of the FPGA.
7. The method for debugging an FPGA chip based on a synthesized netlist according to claim 1, wherein the method for generating an FPGA configuration code stream comprises:
placing the logic circuits of the FPGA according to the third netlist to determine the placed logic circuits;
connecting the placed logic circuits according to the third netlist, and determining a design file of the FPGA; the design files of the FPGA comprise integrated design files for realizing logic circuit layout and connection;
and generating an FPGA configuration code stream according to the design file of the FPGA.
8. An FPGA chip debugging apparatus based on a synthesized netlist, the apparatus comprising:
the debugging and inserting module is used for acquiring an engineering file of the FPGA, and synthesizing the FPGA engineering file by utilizing FPGA development software to determine a first netlist of the FPGA; determining a constraint file of the FPGA engineering file according to the data signal in the first netlist and the clock signal of the data signal; obtaining a first IP core according to the constraint file, and comprehensively determining a second netlist of the FPGA based on the first IP core by utilizing FPGA development software; instantiating a second IP core according to the second netlist to determine a debugging functional module, and inserting the debugging functional module into the first netlist to obtain a third netlist; the first netlist is an original FPGA synthetic netlist; the second netlist is an independent synthesized netlist without I/O; the first IP core is a register transmission level debugging IP core and is used for realizing the debugging functions of FPGA signal capturing, counter statistics and state tracking; the second IP core is a debugging IP core in a gate-level form; the functional module comprises a data port and a clock port of the second IP core, and the data port and the clock port are respectively connected with a data signal and a clock signal of the data signal; the third netlist is an FPGA (field programmable gate array) synthesized netlist inserted with a debugging functional module;
the code stream generation module is used for carrying out layout on the logic circuits of the FPGA according to the third netlist to determine the placed logic circuits; connecting the placed logic circuits according to the third netlist, and determining a design file of the FPGA; generating an FPGA configuration code stream according to the design file of the FPGA; the design files of the FPGA comprise integrated design files for realizing logic circuit layout and connection;
the chip debugging module is used for configuring and running the FPGA based on the FPGA configuration code stream, and debugging the data signals and the clock signals of the data signals by using a real-time debugging tool.
9. An electronic device comprising a memory, a processor, the memory having stored thereon a computer program executable on the processor, characterized in that the processor implements the method of any of the preceding claims 1 to 7 when the computer program is executed.
10. A computer readable medium having non-volatile program code executable by a processor, the program code causing the processor to perform the method of any one of claims 1 to 7.
CN202310539653.6A 2023-05-15 2023-05-15 FPGA chip debugging method and device based on synthesized netlist Pending CN116629171A (en)

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CN117407234A (en) * 2023-12-14 2024-01-16 西安智多晶微电子有限公司 FPGA real-time debugging system and method based on VIO

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117407234A (en) * 2023-12-14 2024-01-16 西安智多晶微电子有限公司 FPGA real-time debugging system and method based on VIO
CN117407234B (en) * 2023-12-14 2024-03-19 西安智多晶微电子有限公司 FPGA real-time debugging system and method based on VIO

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