WO2024067735A1 - 测试机、测试系统和测试方法 - Google Patents

测试机、测试系统和测试方法 Download PDF

Info

Publication number
WO2024067735A1
WO2024067735A1 PCT/CN2023/122196 CN2023122196W WO2024067735A1 WO 2024067735 A1 WO2024067735 A1 WO 2024067735A1 CN 2023122196 W CN2023122196 W CN 2023122196W WO 2024067735 A1 WO2024067735 A1 WO 2024067735A1
Authority
WO
WIPO (PCT)
Prior art keywords
test
host
main control
data
control module
Prior art date
Application number
PCT/CN2023/122196
Other languages
English (en)
French (fr)
Inventor
居宁
张晓彤
Original Assignee
北京华峰测控技术股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 北京华峰测控技术股份有限公司 filed Critical 北京华峰测控技术股份有限公司
Publication of WO2024067735A1 publication Critical patent/WO2024067735A1/zh

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2834—Automated test systems [ATE]; using microprocessors or computers

Definitions

  • the present application relates to the field of testing technology, and in particular to a testing machine, a testing system and a testing method.
  • ATE Automatic Test Equipment
  • ATE includes a host, a tester, and a device under test (DUT).
  • the host sends a test sequence to the tester.
  • the tester generates an excitation signal based on the test sequence and sends it to the DUT.
  • the DUT feeds back a response signal to the tester based on the excitation signal.
  • the tester obtains test data based on the response signal and sends it to the host.
  • the host processes the test data and obtains the test results to instruct the handler to classify the DUT.
  • test efficiency decreases.
  • the present application provides a test machine.
  • the test machine includes a plurality of test boards, a main control module and a co-processing module;
  • the main control module is connected to the multiple test boards respectively and is used to connect to the host, receive the test items sent by the host, and send each test sequence in the test items to each of the test boards;
  • the multiple test boards are used to connect at least one device under test, send an excitation signal to the device under test according to the received test sequence, receive a response signal fed back by the device under test based on the excitation signal, obtain test data and send it to the co-processing module;
  • the co-processing modules are connected to the multiple test boards respectively, and are used to process the test data obtained by the test boards, obtain the test results and send them to the host.
  • the co-processing module is used to:
  • Expected data is obtained from the host, and the expected data is compared with the test data obtained by the test board to obtain the test result.
  • the co-processing module is used to:
  • the expected data sent by the main control module is received, where the expected data is sent by the host to the main control module.
  • the co-processing module is used to:
  • the test result is sent to the main control module, so that the main control module sends the test result to the host.
  • the main control module is used to:
  • test configuration includes channel numbers corresponding to each of the test sequences, the channels to which the channel numbers belong are located between the test board and the test stations, and each of the test stations is used to set one of the devices under test;
  • test sequences and the channel number corresponding to the test sequence are sent to the test board corresponding to the channel number.
  • the test board includes a controller and a functional circuit
  • the controller is respectively connected to the main control module and the functional circuit of the same test board, and is used to receive the test sequence sent by the main control module and the channel label corresponding to the test sequence, control the functional circuit to generate an excitation signal according to the received test sequence, and send the excitation signal generated by the functional circuit to the device under test set at the test station corresponding to the channel label.
  • the controller is further connected to the co-processing module, and is used to receive a response signal fed back by the device under test based on the excitation signal, obtain test data, and send the test data to the co-processing module.
  • test board is used to:
  • test data When the test data needs to be processed, the test data is sent to the co-processing module so that the co-processing module processes the test data to obtain a test result;
  • test data When the test data does not need to be processed, the test data is sent to the main control module, so that the main control module sends the test data to the host; or,
  • test data are sent to the co-processing module and the main control module respectively, so that the co-processing module processes the test data that needs to be processed to obtain a test result, and the main control module sends the test data that does not need to be processed to the host.
  • the testing machine further comprises:
  • the data interaction module is respectively connected to the plurality of test boards and used to connect to the server, and is used to upload the test data obtained by the test boards to the server.
  • the testing machine further comprises:
  • a clock module connected to the main control module, for providing a clock signal
  • the calibration module is respectively connected to the clock module and the main control module, and is used to provide a calibration signal.
  • the testing machine further comprises:
  • the system monitoring module is connected to the plurality of test boards respectively and is used to connect to the host, and is used to monitor each of the test boards and provide feedback to the host.
  • the present application provides a test system, which includes a host and a test machine as provided in the first aspect.
  • the present application provides a testing method.
  • the testing method comprises:
  • the test data is processed to obtain a test result and sent to the host.
  • test machine includes multiple test boards, a main control module and a co-processing module, and the service functions implemented by each test board are different.
  • the main control module is respectively connected to multiple test boards and used to connect to the host, receive the test items sent by the host, and send each test sequence in the test item to each test board.
  • Multiple test boards are used to connect at least one device under test, send an excitation signal to the device under test according to the received test sequence, and receive a response signal fed back by the device under test based on the excitation signal, obtain test data and send it to the co-processing module.
  • the co-processing module is respectively connected to multiple test boards, and is used to process the test data obtained by the test board, obtain test results and send them to the host.
  • the test data is processed inside the test machine, which can reduce the data processing amount of the host and the processing time of the data on the one hand, and shorten the feedback path of the test data and reduce the transmission time of the data on the other hand.
  • the test efficiency is improved.
  • FIG1 is a schematic diagram of the structure of a testing machine in one embodiment
  • FIG2 is a schematic diagram of information interaction during a test in the prior art
  • FIG3 is a schematic diagram of information interaction during a test process in one embodiment
  • FIG. 4 is a schematic flow chart of a testing method in one embodiment.
  • test machine 100, host, 200, device under test, 210, carrier board, 300, server, 400, test machine.
  • spatially relative terms such as “under,” “beneath,” “below,” “under,” “above,” “above,” and the like, may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as “under other elements” or “under it” or “under it” will be oriented as being “above” the other elements or features. Thus, the exemplary terms “under” and “under” may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
  • connection in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if there is transmission of electrical signals or data between the connected objects.
  • the test system in the prior art has the problem of low test efficiency.
  • the inventor has found that the reason for this problem is that the existing test machine includes a main control module and at least one test board (instrument).
  • the host sends a test sequence to the main control module, and the main control module forwards the test sequence to the test board.
  • the test board generates an excitation signal according to the received test sequence and sends it to the device under test, and the device under test feeds back a response signal to the test board according to the excitation signal.
  • the test board obtains test data according to the response signal and sends it to the main control module, and the main control module forwards the test data to the host.
  • the host processes the test data (such as comparing the data result with the preset value) to obtain a test result.
  • the test data obtained by the test board will be forwarded to the host through the main control module, and the host will process the test data. Since the test result of a device under test needs to be obtained based on a number of test data, the amount of test data increases significantly as the number of devices under test increases. Since all test data need to be forwarded to the host through the main control module before the host can process the test results, a large amount of test data will cause congestion in the transmission channel, and the transmission time of the entire test data is long, which seriously affects the test efficiency. In addition, all test structures need to be processed by the host to obtain test data, and a large amount of test data forms a blockage in the host, and the processing time of the entire test data is also long, further reducing the test efficiency.
  • the present invention provides a test machine, a test system and a test method.
  • the test data obtained by the test board is processed to obtain the test results and then sent to the host.
  • the test results can be obtained in advance at the test machine, which can shorten the feedback path of the test data.
  • the test machine changes from sending test data to the host to sending test results to the host. Since the amount of test result data is much smaller than the test data, the test result can be sent to the host. Therefore, the data transmission time between the test machine and the host is greatly reduced, thereby improving the test efficiency.
  • the test data of multiple test machines are processed inside each test machine, thereby avoiding the test data of multiple test machines being concentrated on the same host for processing, which can reduce the processing time of test data and further improve the test efficiency.
  • a test machine comprising a plurality of test boards 10, a main control module 20 and a co-processing module 30.
  • Each test board 10 implements different service functions.
  • the main control module 20 is respectively connected to the plurality of test boards 10 and used to connect to the host 100, receive the test items sent by the host 100, and send each test sequence in the test items to each test board 10.
  • the plurality of test boards 10 are used to connect to at least one device under test 200, send an excitation signal to the device under test 200 according to the received test sequence, receive a response signal fed back by the device under test 200 based on the excitation signal, obtain test data and send it to the co-processing module 30.
  • the co-processing module 30 is respectively connected to the plurality of test boards 10, and is used to process the test data obtained by the test board 10, obtain the test results and send them to the host 100.
  • the test board 10 is a circuit board for testing.
  • multiple test boards 10 can be integrated into one, that is, the circuits of multiple test boards 10 implementing different business functions are distributed on the same board.
  • Multiple test boards 10 can also be independent of each other, that is, the circuits of multiple test boards 10 implementing different business functions are distributed on different boards, such as the circuits implementing one business function are distributed on one board to form a circuit board, and the circuits implementing another business function are distributed on another board to form another circuit board.
  • the main control module 20 and the co-processing module 30 may both be processors. In practical applications, the main control module 20 and the co-processing module 30 may be implemented using the same processor or different processors. The number of processors implementing the main control module 20 or the co-processing module 30 may be one or more.
  • the host 100 sends a test item to the main control module 20, and one test item includes multiple test sequences.
  • the main control module 20 sends each test sequence in the test item to the corresponding test board 10, and the test board 10 corresponding to the test sequence can be determined according to at least one of the business function that the test sequence needs to implement, whether the test board 10 is occupied, and the sending time of the test sequence.
  • the test board 10 sends an excitation signal to the device under test 200 according to the received test sequence.
  • the device under test 200 feeds back a response signal based on the received excitation signal.
  • the test board 10 obtains test data according to the received response signal and sends it to the co-processing module 30.
  • the co-processing module 30 processes the test data obtained by the test board 10, obtains the test result and sends it to the host 100.
  • the co-processing module 30 can directly send the test result to the host 100, or first send the test result to the main control module 20, and then the main control module 20 sends the test result to the host 100.
  • the co-processing module 30 is used to send the test result to the main control module 20 , so that the main control module 20 sends the test result to the host 100 .
  • Figure 2 is a schematic diagram of information interaction during the test process in the prior art.
  • the test sequence is first sent from the host to the main control module in the test machine, then from the main control module to the test board in the test machine, and finally from the test board to the device under test to start the test.
  • the test data obtained after the test is completed is first sent from the device under test to the test board, then from the test board to the main control module, and finally from the main control module to the host.
  • FIG3 is a schematic diagram of information exchange during a test in an embodiment.
  • the test sequence is also first sent from the host to the main control module in the test machine, then from the main control module to the test board in the test machine, and finally from the test board to the device under test to start the test.
  • the test board sends the test data to the main control module and the co-processing module in the test machine respectively.
  • the main control module still sends the test data to the host.
  • the co-processing module sends the test data to the host according to the host.
  • the control module receives the expected data, processes the test data to obtain the test results, and sends the test results to the main control module and the host respectively.
  • the present invention advances the processing of test data from the host to the test machine, thereby shortening the feedback path of the test data and reducing the data transmission time. Moreover, by processing the test data by the test machine, the data processing amount of the host can be reduced and the data processing time can be reduced.
  • the above-mentioned test machine includes multiple test boards, a main control module and a co-processing module, and each test board implements different business functions.
  • the main control module is respectively connected to multiple test boards and used to connect to the host, receive the test items sent by the host, and send each test sequence in the test item to each test board.
  • Multiple test boards are used to connect at least one device under test, send an excitation signal to the device under test according to the received test sequence, and receive a response signal fed back by the device under test based on the excitation signal, obtain test data and send it to the co-processing module.
  • the co-processing module is respectively connected to multiple test boards, and is used to process the test data obtained by the test board, obtain test results and send them to the host.
  • test data is processed inside the test machine, which can reduce the data processing amount of the host and the processing time of the data on the one hand, and shorten the feedback path of the test data and reduce the transmission time of the data on the other hand.
  • the test efficiency is improved.
  • the test board 10 can adopt a dedicated test board, and at this time, one test board can complete the measurement of a device under test.
  • the test board 10 can also adopt a universal test board, and at this time, multiple test boards complete the measurement of a device under test together, and different test boards can be combined for measurement according to the difference of the device under test.
  • the multiple test boards include four test boards, namely the first test board, the second test board, the third test board and the fourth test board.
  • the business functions implemented by the four test boards are different, the first test board is a power board, the second test board is a digital circuit board, the third test board is a signal source board, and the fourth test board is an oscilloscope board.
  • the co-processing module 30 is used to obtain expected data from the host 100, and compare the expected data with the test data obtained by the test board 10 to obtain a test result.
  • the expected data is the data used to determine whether the test has passed.
  • the co-processing module 30 is used to receive expected data sent by the main control module 20 , where the expected data is sent by the host 100 to the main control module 20 .
  • the host 100 can directly send the expected data to the co-processing module 30, or first send the expected data to the main control module 20, and then the main control module 20 sends the expected data to the co-processing module 30.
  • the expected data is compared with the test data obtained by the test board 10, for example: if the test data obtained by the test board 10 is greater than or equal to the predicted data, the test is determined to be passed; if the test data obtained by the test board 10 is less than the predicted data, the test is determined to be failed. Alternatively, if the test data obtained by the test board 10 is less than or equal to the predicted data, the test is determined to be passed; if the test data obtained by the test board 10 is greater than the predicted data, the test is determined to be failed.
  • the co-processing module can replace the host to process the test data by acquiring the expected data from the host, such as comparing the expected data with the test data obtained by the test board to obtain the test result.
  • the main control module 20 is used to receive the test configuration sent by the host 100, the test configuration includes channel labels corresponding to each test sequence, the channels to which the channel labels belong are located between the test board 10 and the test station, and each test station is used to set up a device under test 200; each test sequence and the channel label corresponding to the test sequence are sent to the test board 10 corresponding to the channel label.
  • the test configuration is used to control the sending of each test sequence in the test item.
  • the host 100 sends the test items and the test configuration together to the main control module 20.
  • the main control module 20 obtains the channel number corresponding to each test sequence in the test item from the test configuration.
  • the channel to which the channel number belongs is located between the test board 10 and the test station.
  • the test station is used to set the device under test 200.
  • One channel number can correspond the test sequence to the test board 10 and the device under test 200, thereby controlling the main control module 20 to send the test sequence to the test board 10 corresponding to the channel number, and then controlling the test board 10 to send the excitation signal generated according to the test sequence to the test station corresponding to the channel number, that is, the device under test 200.
  • a load board 210 is provided, on which a plurality of test stations are disposed, and a device under test 200 is disposed on the test stations.
  • the test board 10 includes a controller 11 and a functional circuit 12.
  • the controller 11 is connected to the main control module 20 and the functional circuit 12 of the same test board 10, respectively, and is used to receive the test sequence sent by the main control module 20 and the channel number corresponding to the test sequence, control the functional circuit 12 to generate an excitation signal according to the received test sequence, and send the excitation signal generated by the functional circuit 12 to the device under test 200 set at the test station corresponding to the channel number.
  • the controller 11 implements information exchange between the test board 10 and the outside (including between the test boards 10), and the functional circuit 12 implements the service functions of the test board 10.
  • the controller 11 may include a processor and a communication interface.
  • the main control module 20 sends the test sequence and the channel number to the controller 11.
  • the controller 11 controls the functional circuit 12 to generate a corresponding excitation signal according to the test sequence, and sends the excitation signal to the device under test 200 set at the test station corresponding to the channel number.
  • a controller is provided in the main control module, which can realize information interaction between the test board and the outside.
  • the controller 11 is further connected to the co-processing module 30 , and is used to receive a response signal fed back by the device under test 200 based on the excitation signal, obtain test data, and send the test data to the co-processing module 30 .
  • the test board 10 is used to send the test data to the co-processing module 30 when the test data needs to be processed, so that the co-processing module 30 processes the test data to obtain a test result.
  • test board 10 is further used to send the test data to the main control module 20 when the test data does not need to be processed, so that the main control module 20 sends the test data to the host 100.
  • the controller 11 sends the test data that needs to be processed to the co-processing module 30 for processing, obtains the test results and sends them to the host 100, and sends the test data that does not need to be processed to the main control module 20, and the main control module 20 directly sends the test data to the host 100.
  • the test board 10 is used to send test data to the main control module 20 and the co-processing module 30 respectively, so that the main control module 20 sends the test data that does not need to be processed to the host 100, and the co-processing module 30 processes the test data that needs to be processed to obtain the test results.
  • the test machine further includes a data interaction module 40.
  • the data interaction module 40 is respectively connected to a plurality of test boards 10 and is used to connect to the server 300, and is used to upload the test data obtained by the test boards 10 to the server 300.
  • the data interaction module 40 is a processor. In practical applications, the main control module 20, the co-processing module 30 and the data interaction module 40 can be implemented by the same processor or by different processors. The number of processors implementing the data interaction module 40 can be one or more.
  • the test board 10 in addition to sending the test data to the main control module 20 or the co-processing module 30 , the test board 10 also sends the test data to the data interaction module 40 .
  • the data interaction module 40 uploads the test data to the server 300 .
  • test data can be uploaded to the server for easy query.
  • the data interaction module 40 is also connected to the main control module 20 and the co-processing module 30 respectively, and is used to monitor the main control module 20 and the co-processing module 30 .
  • the data interaction module can also monitor the operation status of the main control module and the co-processing module in real time.
  • the test machine further includes a clock module 50.
  • the clock module 50 is connected to the main control module 20 and is used to provide a clock signal.
  • the clock module 50 is also connected to the test board 10 .
  • a clock module is added to provide a clock signal inside the test machine.
  • the test machine further includes a calibration module 60.
  • the calibration module 60 is connected to the clock module 50 and the main control module 20 respectively, and is used to provide a calibration signal.
  • the calibration module 60 is also connected to the test board 10 .
  • a calibration module is added to calibrate the clock inside the test machine.
  • the test machine further includes a system monitoring module 70.
  • the system monitoring module 70 is connected to a plurality of test boards 10 and is used to connect to the host 100, and is used to monitor each test board 10 and feed back to the host 100.
  • the operating status of each test board can be monitored, which is conducive to timely alarm or processing when the test board is abnormal.
  • test system includes a host 100 and a test machine 400 provided in any of the above embodiments.
  • a testing method is also provided, as shown in FIG4 , comprising the following steps:
  • the test machine includes a main control module, and the main control module receives test items sent by the host.
  • the host receives the working mode confirmation signal input by the user on the one hand.
  • the working mode includes software and hardware debugging mode and mass production mode.
  • it loads the user program, which includes test configuration and test items.
  • the host verifies the hardware configuration in the tester and the software configuration in the user program, and confirms the test configuration, such as specifying the number of workstations, workstation numbers, external devices, etc.
  • the tester loads the test configuration and part of the test sequence, waiting for the Start of Test (SOT) signal.
  • SOT Start of Test
  • the tester starts to test the device under test.
  • the tester sends an End of Test (EOT) signal to the host, and the host controls the manipulator to replace the device under test.
  • EOT End of Test
  • S402 Send a stimulus signal to the device under test according to each test sequence in the test item.
  • the test machine also includes multiple test boards.
  • the main control module sends each test sequence in the test item to the corresponding test board.
  • the test board generates an excitation signal according to the received test sequence and sends it to the device under test.
  • test board receives a response signal fed back by the device under test based on the excitation signal to obtain test data.
  • the test machine also includes a co-processing module.
  • the test board sends the test data to the co-processing module.
  • the co-processing module processes the test data, obtains the test results and sends them to the host.

Abstract

本申请涉及一种测试机、测试系统和测试方法。测试机包括多个测试板卡、主控模块和协处理模块，各个测试板卡实现的业务功能不同；主控模块分别连接多个测试板卡并用于连接主机，接收主机发送的测试项，并将测试项中的各个测试序列发送给各个测试板卡；多个测试板卡用于连接至少一个被测器件，根据接收到的测试序列向被测器件发送激励信号，并接收被测器件基于激励信号反馈的响应信号，得到测试数据并发送给协处理模块；协处理模块分别连接多个测试板卡，用于对测试板卡得到的测试数据进行处理，得到测试结果并发送给主机。本申请能够提高测试效率。

Description

测试机、测试系统和测试方法
本申请要求于2022年9月29日提交中国国家知识产权局、申请号202211198633.9、申请名称为“测试机、测试系统和测试方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及测试技术领域，特别是涉及一种测试机、测试系统和测试方法。
背景技术
自动测试设备(Automatic Test Equipment，简称ATE)是半导体产业中检测集成电路(Integrated Circuit，简称IC)功能完整性的设备，应用于集成电路生产制造的最后流程，以确保集成电路生产制造的品质。
ATE包括主机(Host)、测试机(Tester)和被测器件(Device Under Test，简称DUT)。主机将测试序列(test sequence)发送给测试机。测试机根据测试序列生成激励信号，并发送给被测器件。被测器件根据激励信号反馈响应信号给测试机。测试机根据响应信号得到测试数据，并发送给主机。主机对测试数据进行处理，得到测试结果，以指示机械手(Handler)对被测器件进行分类。
然而，随着被测器件的数量增加，测试效率随之下降。
发明内容
基于此，有必要针对上述技术问题，提供一种能够提高测试效率的测试机、测试系统和测试方法。
第一方面，本申请提供了一种测试机。所述测试机包括多个测试板卡、主控模块和协处理模块；
所述主控模块，分别连接所述多个测试板卡并用于连接主机，接收主机发送的测试项，并将所述测试项中的各个测试序列发送给各个所述测试板卡；
所述多个测试板卡，用于连接至少一个被测器件，根据接收到的所述测试序列向所述被测器件发送激励信号，并接收所述被测器件基于所述激励信号反馈的响应信号，得到测试数据并发送给所述协处理模块；
所述协处理模块，分别连接所述多个测试板卡，用于对所述测试板卡得到的测试数据进行处理，得到测试结果并发送给所述主机。
在其中一个实施例中，所述协处理模块用于，
从所述主机获取预期数据，并将所述预期数据与所述测试板卡得到的测试数据进行比较，得到所述测试结果。
在其中一个实施例中，所述协处理模块用于，
接收所述主控模块发送的所述预期数据，所述预期数据是所述主机发送给所述主控模块的。
在其中一个实施例中，所述协处理模块用于，
将所述测试结果发送给所述主控模块，以使所述主控模块将所述测试结果发送给所述主机。
在其中一个实施例中，所述主控模块用于，
接收所述主机发送的测试配置，所述测试配置包括各个所述测试序列对应的通道标号，所述通道标号所属的通道位于所述测试板卡与测试工位之间，每个所述测试工位用于设置一个所述被测器件；
将每个所述测试序列和所述测试序列对应的通道标号发送给所述通道标号对应的测试板卡。
在其中一个实施例中，所述测试板卡包括控制器和功能电路；
所述控制器，分别与所述主控模块、以及同一所述测试板卡的功能电路连接，用于接收所述主控模块发送的测试序列和所述测试序列对应的通道标号，控制所述功能电路根据接收到的所述测试序列生成激励信号，并将所述功能电路生成的激励信号发送给所述通道标号对应的测试工位设置的被测器件。
在其中一个实施例中，所述控制器还与所述协处理模块连接，用于接收所述被测器件基于所述激励信号反馈的响应信号，得到测试数据并发送给所述协处理模块。
在其中一个实施例中，所述测试板卡用于，
当所述测试数据需要处理时，将所述测试数据发送给所述协处理模块，以使所述协处理模块对所述测试数据进行处理，得到测试结果；
当所述测试数据不需要处理时，将所述测试数据发送给所述主控模块，以使所述主控模块将所述测试数据发送给所述主机；或者，
将所述测试数据分别发送给所述协处理模块和所述主控模块，以使所述协处理模块对需要处理的所述测试数据处理得到测试结果，所述主控模块将不需要处理的所述测试数据发送给所述主机。
在其中一个实施例中，所述测试机还包括：
数据交互模块，分别连接所述多个测试板卡并用于连接服务器，用于将所述测试板卡得到的测试数据上传到服务器。
在其中一个实施例中，所述测试机还包括：
时钟模块，与所述主控模块连接，用于提供时钟信号；
校准模块，分别连接所述时钟模块和所述主控模块，用于提供校准信号。
在其中一个实施例中，所述测试机还包括：
系统监控模块，分别连接所述多个测试板卡并用于连接所述主机，用于监控各个所述测试板卡并反馈给所述主机。
在其中一个实施例中，
第二方面，本申请提供了一种测试系统。所述测试系统包括主机和如第一方面提供的测试机。
第三方面，本申请提供了一种测试方法。所述测试方法包括：
接收主机发送的测试项；
根据所述测试项中的各个测试序列向被测器件发送激励信号；
接收所述被测器件基于所述激励信号反馈的响应信号，得到测试数据；
对所述测试数据进行处理，得到测试结果并发送给所述主机。
上述测试机、测试系统和测试方法，测试机包括多个测试板卡、主控模块和协处理模块，各个测试板卡实现的业务功能不同。主控模块分别连接多个测试板卡并用于连接主机，接收主机发送的测试项，并将测试项中的各个测试序列发送给各个的测试板卡。多个测试板卡用于连接至少一个被测器件，根据接收到的测试序列向被测器件发送激励信号，并接收被测器件基于激励信号反馈的响应信号，得到测试数据并发送给协处理模块。协处理模块分别连接多个测试板卡，用于对测试板卡得到的测试数据进行处理，得到测试结果并发送给主机。这样测试数据在测试机内部进行处理，一方面可以减少主机的数据处理量，减少数据的处理时间，另一方面可以缩短测试数据的反馈路径，减少数据的传输时间。综上，测试效率得到提升。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一个实施例中测试机的结构示意图；
图2为现有技术中测试过程中信息交互的示意图；
图3为一个实施例中测试过程中信息交互的示意图；
图4为一个实施例中测试方法的流程示意图。
附图标记说明：
10、测试板卡，11、控制器，12、功能电路；
20、主控模块；
30、协处理模块；
40、数据交互模块；
50、时钟模块；
60、校准模块；
70、系统监控模块；
100、主机，200、被测器件，210、承载板，300、服务器，400、测试机。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
可以理解，本申请所使用的术语“第一”、“第二”等可在本文中用于描述各种元件，但这些元件不受这些术语限制。这些术语仅用于将第一个元件与另一个元件区分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
需要说明的是，当一个元件被认为是“连接”另一个元件时，它可以是直接连接到另一个元件，或者通过居中元件连接另一个元件。此外，以下实施例中的“连接”，如果被连接的对象之间具有电信号或数据的传递，则应理解为“电连接”、“通信连接”等。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应当理解的是，术语“包括/包含”或“具有”等指定所陈述的特征、整体、步骤、操作、组件、部分或它们的组合的存在，但是不排除存在或添加一个或更多个其他特征、整体、步骤、操作、组件、部分或它们的组合的可能性。同时，在本说明书中使用的术语“和/或”包括相关所列项目的任何及所有组合。
正如背景技术所述，现有技术中的测试系统有测试效率低的问题，经发明人研究发现，出现这种问题的原因在于，现有的测试机包括主控模块和至少一个测试板卡(instrument)。主机发送测试序列给主控模块，主控模块将测试序列转发给测试板卡。测试板卡根据接收到的测试序列生成激励信号并发送给被测器件，被测器件根据激励信号反馈响应信号给测试板卡。测试板卡根据响应信号得到测试数据并发送给主控模块，主控模块将测试数据转发给主机。主机对测试数据进行处理(如将数据结果与预设值进行比较)，得到测试结果。
其中，测试板卡得到的测试数据都会经过主控模块转发给主机，由主机对测试数据进行处理。由于一个被测器件的测试结果需要根据若干测试数据得到，因此随着被测器件的数量增加，测试数据的数量大幅增多。又由于所有的测试数据都需要经过主控模块转发给主机，才能由主机处理得到测试结果，因此大量的测试数据会造成传输通道拥堵，整个测试数据的传输时间较长，严重影响到测试效率。并且所有的测试结构都需要经过主机处理测试数据得到，大量的测试数据在主机内形成阻塞，整个测试数据的处理时间也较长，进一步降低测试效率。
基于以上原因，本发明提供了一种测试机、测试系统和测试方法，通过在测试机内增设协处理模块，对测试板卡得到的测试数据进行处理，得到测试结果再发送给主机，这样提前到测试机即可得到测试结果，可以缩短测试数据的反馈路径。测试机从向主机发送测试数据变成向主机发送测试结果，由于测试结果的数据量远小于测试数 据，因此测试机和主机之间的数据传输时间大幅减少，从而提高测试效率。而且多个测试机的测试数据在各个测试机内部进行处理，从而避免多个测试机的测试数据都集中在同一个主机上进行处理，可以减少测试数据的处理时间，进一步提高测试效率。
在一个实施例中，如图1所示，提供了一种测试机，包括多个测试板卡10、主控模块20和协处理模块30。各个测试板卡10实现的业务功能不同。主控模块20分别连接多个测试板卡10并用于连接主机100，接收主机100发送的测试项，并将测试项中的各个测试序列发送给各个测试板卡10。多个测试板卡10用于连接至少一个被测器件200，根据接收到的测试序列向被测器件200发送激励信号，并接收被测器件200基于激励信号反馈的响应信号，得到测试数据并发送给协处理模块30。协处理模块30分别连接多个测试板卡10，用于对测试板卡10得到的测试数据进行处理，得到测试结果并发送给主机100。
其中，测试板卡10是进行测试的电路板。在实际应用中，多个测试板卡10可以集成一体，即多个测试板卡10实现不同业务功能的电路分布在同一个板体上。多个测试板卡10也可以相互独立，即多个测试板卡10实现不同业务功能的电路分布在不同的板体上，如实现一种业务功能的电路分布在一个板体上，形成一个电路板，实现另一种业务功能的电路分布在另一个板体上，形成另一个电路板。
主控模块20和协处理模块30可均为处理器。在实际应用中，主控模块20和协处理模块30可以采用同一个处理器实现，也可以采用不同的处理器实现。实现主控模块20或者协处理模块30的处理器的数量可以为一个，也可以为多个。
具体地，主机100向主控模块20发送测试项，一个测试项包括多个测试序列。主控模块20将测试项中的各个测试序列发送给对应的测试板卡10，测试序列对应的测试板卡10可以根据测试序列需要实现的业务功能、测试板卡10是否占用、测试序列的发送时间中的至少一个进行确定。测试板卡10根据接收到的测试序列向被测器件200发送激励信号。被测器件200基于接收到激励信号反馈响应信号。测试板卡10根据接收到的响应信号得到测试数据，并发送给协处理模块30。协处理模块30对测试板卡10得到的测试数据进行处理，得到测试结果并发送给主机100。在实际应用中，协处理模块30可以直接将测试结果发送给主机100，也可以先将测试结果发送给主控模块20，再由主控模块20将测试结果发送给主机100。
示例性地，协处理模块30用于，将测试结果发送给主控模块20，以使主控模块20将测试结果发送给主机100。
图2为现有技术中测试过程中信息交互的示意图。如图2所示，测试序列先从主机发送到测试机中的主控模块，再从主控模块发送到测试机中的测试板卡，最后从测试板卡发送到被测器件，以开始测试。测试结束得到的测试数据先从被测器件发送到测试板卡，再从测试板卡发送到主控模块，最后从主控模块发送到主机。
图3为一个实施例中测试过程中信息交互的示意图。如图3所示，测试序列也是先从主机发送到测试机中的主控模块，再从主控模块发送到测试机中的测试板卡，最后从测试板卡发送到被测器件，以开始测试。与现有技术不同的是，测试结束得到的测试数据从被测器件发送到测试板卡之后，测试板卡将测试数据分别发送给主控模块和测试机中的协处理模块。主控模块还是将测试数据发送给主机。协处理模块根据主 控模块发送的预期数据，对测试数据处理得到测试结果，并将测试结果分别发送给主控模块和主机。
由此可见，本发明将测试数据的处理从主机提前到测试机内，从而缩短了测试数据的反馈路径，减少了数据的传输时间。而且由测试机处理测试数据，可以减少主机的数据处理量，减少数据的处理时间。
上述测试机中，包括多个测试板卡、主控模块和协处理模块，各个测试板卡实现的业务功能不同。主控模块分别连接多个测试板卡并用于连接主机，接收主机发送的测试项，并将测试项中的各个测试序列发送给各个的测试板卡。多个测试板卡用于连接至少一个被测器件，根据接收到的测试序列向被测器件发送激励信号，并接收被测器件基于激励信号反馈的响应信号，得到测试数据并发送给协处理模块。协处理模块分别连接多个测试板卡，用于对测试板卡得到的测试数据进行处理，得到测试结果并发送给主机。这样测试数据在测试机内部进行处理，一方面可以减少主机的数据处理量，减少数据的处理时间，另一方面可以缩短测试数据的反馈路径，减少数据的传输时间。综上，测试效率得到提升。
示例性地，测试板卡10可以采用专用的测试板卡，此时一个测试板卡即可完成一个被测器件的测量。测试板卡10也可以采用通用的测试板卡，此时多个测试板卡一起完成一个被测器件的测量，可以根据被测器件的不同，组合不同的测试板卡进行测量。例如，多个测试板卡包括四个测试板卡，分别为第一测试板卡、第二测试板卡、第三测试板卡和第四测试板卡。四个测试板卡实现的业务功能各不相同，第一测试板卡为电源板，第二测试板卡为数字电路板，第三测试板卡为信号源板，第四测试板卡为示波器板。
在一个实施例中，协处理模块30用于，从主机100获取预期数据，并将预期数据与测试板卡10得到的测试数据进行比较，得到测试结果。
其中，预期数据为判断测试是否通过的数据。
示例性地，协处理模块30用于，接收主控模块20发送的预期数据，预期数据是主机100发送给主控模块20的。
具体地，主机100可以直接将预期数据发送给协处理模块30，也可以先将预期数据发送给主控模块20，再由主控模块20将预期数据发送给协处理模块30。将预期数据与测试板卡10得到的测试数据进行比较，比如：若测试板卡10得到的测试数据大于或等于预测数据，则判定测试通过；若测试板卡10得到的测试数据小于预测数据，则判定测试不通过。或者，若测试板卡10得到的测试数据小于或等于预测数据，则判定测试通过；若测试板卡10得到的测试数据大于预测数据，则判定测试不通过。
上述实施例中，协处理模块通过从主机获取预期数据，可以替换主机实现对测试数据进行处理，如将预期数据与测试板卡得到的测试数据进行比较，得到测试结果。
在一个实施例中，主控模块20用于，接收主机100发送的测试配置，测试配置包括各个测试序列对应的通道标号，通道标号所属的通道位于测试板卡10与测试工位之间，每个测试工位用于设置一个被测器件200；将每个测试序列和测试序列对应的通道标号发送给通道标号对应的测试板卡10。
其中，测试配置用于控制测试项中各个测试序列的发送。
具体地，主机100将测试项和测试配置一起发送给主控模块20。主控模块20从测试配置中获取测试项中各个测试序列对应的通道标号。通道标号所属的通道位于测试板卡10与测试工位之间，测试工位用于设置被测器件200，一个通道标号即可将测试序列与测试板卡10、被测器件200均对应上，从而控制主控模块20将测试序列发送给通道标号对应的测试板卡10，进而控制测试板卡10将根据测试序列产生的激励信号发送到通道标号对应的测试工位，即被测器件200。
示例性地，如图1所示，提供一承载板(Load Board)210，承载板上设有多个测试工位，被测器件200设置在测试工位上。
在一个实施例中，如图1所示，测试板卡10包括控制器11和功能电路12。控制器11分别与主控模块20、以及同一个测试板卡10的功能电路12连接，用于接收主控模块20发送的测试序列和测试序列对应的通道标号，控制功能电路12根据接收到的测试序列生成激励信号，并将功能电路12生成的激励信号发送给通道标号对应的测试工位设置的被测器件200。
其中，控制器11实现测试板卡10与外部(包括各测试板卡10之间)的信息交互，功能电路12实现测试板卡10的业务功能。在实际应用中，控制器11可以包括处理器和通信接口。
具体地，主控模块20将测试序列和通道标号一起发送给控制器11。控制器11根据测试序列控制功能电路12产生对应的激励信号，并将激励信号发送给通道标号对应的测试工位设置的被测器件200。
上述实施例中，主控模块内设有控制器，可以实现测试板卡与外部的信息交互。
在一个实施例中，控制器11还与协处理模块30连接，用于接收被测器件200基于激励信号反馈的响应信号，得到测试数据并发送给协处理模块30。
在一个实施例中，测试板卡10用于，当测试数据需要处理时，将测试数据发送给协处理模块30，以使协处理模块30对测试数据进行处理，得到测试结果。
在一个实施例中，测试板卡10还用于，当测试数据不需要处理时，将测试数据发送给主控模块20，以使主控模块20将测试数据发送给主机100。
具体地，测试数据有的需要处理，如与预期数据进行比较，有的不需要处理。控制器11将需要处理的测试数据发送给协处理模块30进行处理，得到测试结果发送给主机100，并将不需要处理的测试数据发送给主控模块20，主控模块20将测试数据直接发送给主机100。
在一个实施例中，测试板卡10用于，将测试数据分别发送给主控模块20和协处理模块30，以使主控模块20将不需要处理的测试数据发送给主机100，协处理模块30对需要数据处理的测试数据处理得到测试结果。
在一个实施例中，如图1所示，测试机还包括数据交互模块40。数据交互模块40分别连接多个测试板卡10并用于连接服务器300，用于将测试板卡10得到的测试数据上传到服务器300。
其中，数据交互模块40为处理器。在实际应用中，主控模块20、协处理模块30和数据交互模块40可以采用同一个处理器实现，也可以采用不同的处理器实现。实现数据交互模块40的处理器数量可以为一个，也可以为多个。
具体地，测试板卡10除了将测试数据发送给主控模块20或者协处理模块30之外，还将测试数据发送给数据交互模块40。数据交互模块40将测试数据上传到服务器300。
上述实施例中，通过增设数据交互模块，可以将测试数据上传到服务器，方便进行查询。
示例性地，数据交互模块40还分别连接主控模块20和协处理模块30，用于监控主控模块20和协处理模块30。
上述实施例中，数据交互模块还可以对主控模块和协处理模块的运行情况进行实时监控。
在一个实施例中，如图1所示，测试机还包括时钟模块50。时钟模块50与主控模块20连接，用于提供时钟信号。
示例性地，时钟模块50还与测试板卡10连接。
上述实施例中，通过增设时钟模块，为测试机内部提供时钟信号。
在一个实施例中，如图1所示，测试机还包括校准模块60。校准模块60分别连接时钟模块50和主控模块20，用于提供校准信号。
示例性地，校准模块60还与测试板卡10连接。
上述实施例中，通过增设校准模块，对测试机内部进行时钟校准。
在一个实施例中，如图1所示，测试机还包括系统监控模块70。系统监控模块70分别连接多个测试板卡10并用于连接主机100，用于监控各个测试板卡10并反馈给主机100。
上述实施例中，通过增设系统监控模块，可以监控各个测试板卡的运行状态，有利于测试板卡异常时及时报警或者处理。
基于同样的发明构思，还提供了一种测试系统，如图1所示，测试系统包括主机100和如上述任一实施例提供的测试机400。
基于同样的发明构思，还提供了一种测试方法，如图4所示，包括如下步骤：
S401，接收主机发送的测试项。
具体地，测试机包括主控模块，主控模块接收主机发送的测试项。
在实际应用中，主机一方面接收用户输入的工作模式确认信号，工作模式包括软硬件调试模式和量产模式，另一方面加载用户程序，用户程序包括测试配置和测试项。然后主机对测试机内的硬件配置和用户程序中的软件配置进行校验，并对测试配置进行确认，如指定工位数、工位号、外接设备等。接着测试机加载测试配置和部分测试序列，等待测试启动(Start of Test，简称SOT)信号。测试启动之后，测试机开始对被测器件进行测试。另外，测试机发送测试结束(End of Test，简称EOT)信号给主机，主机控制机械手更换被测器件。
S402，根据测试项中的各个测试序列向被测器件发送激励信号。
具体地，测试机还包括多个测试板卡，主控模块将测试项中的各个测试序列发送给对应的测试板卡，测试板卡根据接收到的测试序列产生激励信号并发送给被测器件。
S403，接收被测器件基于激励信号反馈的响应信号，得到测试数据。
具体地，测试板卡接收被测器件基于激励信号反馈的响应信号，得到测试数据。
S404，对测试数据进行处理，得到测试结果并发送给主机。
具体地，测试机还包括协处理模块，测试板卡将测试数据发送给协处理模块，协处理模块对测试数据进行处理，得到测试结果并发送给主机。
在本说明书的描述中，参考术语“有些实施例”、“其他实施例”、“理想实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性描述不一定指的是相同的实施例或示例。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (13)

  1. 一种测试机，其特征在于，所述测试机包括多个测试板卡、主控模块和协处理模块；
    所述主控模块，分别连接所述多个测试板卡并用于连接主机，接收主机发送的测试项，并将所述测试项中的各个测试序列发送给各个所述测试板卡；
    所述多个测试板卡，用于连接至少一个被测器件，根据接收到的所述测试序列向所述被测器件发送激励信号，并接收所述被测器件基于所述激励信号反馈的响应信号，得到测试数据并发送给所述协处理模块；
    所述协处理模块，分别连接所述多个测试板卡，用于对所述测试板卡得到的测试数据进行处理，得到测试结果并发送给所述主机。
  2. 根据权利要求1所述的测试机，其特征在于，所述协处理模块用于，
    从所述主机获取预期数据，并将所述预期数据与所述测试板卡得到的测试数据进行比较，得到所述测试结果。
  3. 根据权利要求2所述的测试机，其特征在于，所述协处理模块用于，
    接收所述主控模块发送的所述预期数据，所述预期数据是所述主机发送给所述主控模块的。
  4. 根据权利要求1所述的测试机，其特征在于，所述协处理模块用于，
    将所述测试结果发送给所述主控模块，以使所述主控模块将所述测试结果发送给所述主机。
  5. 根据权利要求1所述的测试机，其特征在于，所述主控模块用于，
    接收所述主机发送的测试配置，所述测试配置包括各个所述测试序列对应的通道标号，所述通道标号所属的通道位于所述测试板卡与测试工位之间，每个所述测试工位用于设置一个所述被测器件；
    将每个所述测试序列和所述测试序列对应的通道标号发送给所述通道标号对应的测试板卡。
  6. 根据权利要求5所述的测试机，其特征在于，所述测试板卡包括控制器和功能电路；
    所述控制器，分别与所述主控模块、以及同一所述测试板卡的功能电路连接，用于接收所述主控模块发送的测试序列和所述测试序列对应的通道标号，控制所述功能电路根据接收到的所述测试序列生成激励信号，并将所述功能电路生成的激励信号发送给所述通道标号对应的测试工位设置的被测器件。
  7. 根据权利要求6所述的测试机，其特征在于，所述控制器还与所述协处理模块连接，用于接收所述被测器件基于所述激励信号反馈的响应信号，得到测试数据并发送给所述协处理模块。
  8. 根据权利要求1-7任一项所述的测试机，其特征在于，所述测试板卡用于，
    当所述测试数据需要处理时，将所述测试数据发送给所述协处理模块，以使所述协处理模块对所述测试数据进行处理，得到测试结果；
    当所述测试数据不需要处理时，将所述测试数据发送给所述主控模块，以使所述 主控模块将所述测试数据发送给所述主机；或者，
    将所述测试数据分别发送给所述协处理模块和所述主控模块，以使所述协处理模块对需要处理的所述测试数据处理得到测试结果，所述主控模块将不需要处理的所述测试数据发送给所述主机。
  9. 根据权利要求1-7任一项所述的测试机，其特征在于，所述测试机还包括：
    数据交互模块，分别连接所述多个测试板卡并用于连接服务器，用于将所述测试板卡得到的测试数据上传到服务器。
  10. 根据权利要求1-7任一项所述的测试机，其特征在于，所述测试机还包括：
    时钟模块，与所述主控模块连接，用于提供时钟信号；
    校准模块，分别连接所述时钟模块和所述主控模块，用于提供校准信号。
  11. 根据权利要求1-7任一项所述的测试机，其特征在于，所述测试机还包括：
    系统监控模块，分别连接所述多个测试板卡并用于连接所述主机，用于监控各个所述测试板卡并反馈给所述主机。
  12. 一种测试系统，其特征在于，所述测试系统包括主机和如权利要求1-11任一项所述的测试机。
  13. 一种测试方法，其特征在于，所述方法包括：
    接收主机发送的测试项；
    根据所述测试项中的各个测试序列向被测器件发送激励信号；
    接收所述被测器件基于所述激励信号反馈的响应信号，得到测试数据；
    对所述测试数据进行处理，得到测试结果并发送给所述主机。
PCT/CN2023/122196 2022-09-29 2023-09-27 测试机、测试系统和测试方法 WO2024067735A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211198633.9A CN115421028A (zh) 2022-09-29 2022-09-29 测试机、测试系统和测试方法
CN202211198633.9 2022-09-29

Publications (1)

Publication Number Publication Date
WO2024067735A1 true WO2024067735A1 (zh) 2024-04-04

Family

ID=84205993

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/122196 WO2024067735A1 (zh) 2022-09-29 2023-09-27 测试机、测试系统和测试方法

Country Status (2)

Country Link
CN (1) CN115421028A (zh)
WO (1) WO2024067735A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115421028A (zh) * 2022-09-29 2022-12-02 北京华峰测控技术股份有限公司 测试机、测试系统和测试方法

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103235879A (zh) * 2013-04-17 2013-08-07 中国海洋石油总公司 基于小生境主从式并行遗传算法的双相介质参数反演方法
CN105378493A (zh) * 2013-02-21 2016-03-02 爱德万测试公司 用于支持协议无关器件测试系统中协议重新配置的基于云的基础设施
CN105717439A (zh) * 2016-02-24 2016-06-29 上海东软载波微电子有限公司 芯片测试方法及系统
CN105911462A (zh) * 2015-02-20 2016-08-31 得克萨斯测试公司 用于半导体集成电路器件的功能数字测试的自动测试设备
CN107391245A (zh) * 2017-07-18 2017-11-24 致象尔微电子科技（上海）有限公司 一种多核芯片的软件系统
CN111983532A (zh) * 2020-07-30 2020-11-24 南昌工程学院 石墨烯器件电磁性测试系统及其测试装置
CN112241160A (zh) * 2020-10-20 2021-01-19 广州小鹏汽车科技有限公司 车辆测试方法、装置、车辆检测系统以及测试板卡
CN112697455A (zh) * 2020-12-08 2021-04-23 上海纳恩汽车技术股份有限公司 一种实车自动化测试系统
CN113514759A (zh) * 2021-09-07 2021-10-19 南京宏泰半导体科技有限公司 一种多核测试处理器及集成电路测试系统与方法
CN114564429A (zh) * 2022-02-11 2022-05-31 北京智芯微电子科技有限公司 轻量级智能计算紧耦合结构及其数据处理方法
CN115421028A (zh) * 2022-09-29 2022-12-02 北京华峰测控技术股份有限公司 测试机、测试系统和测试方法

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105378493A (zh) * 2013-02-21 2016-03-02 爱德万测试公司 用于支持协议无关器件测试系统中协议重新配置的基于云的基础设施
CN103235879A (zh) * 2013-04-17 2013-08-07 中国海洋石油总公司 基于小生境主从式并行遗传算法的双相介质参数反演方法
CN105911462A (zh) * 2015-02-20 2016-08-31 得克萨斯测试公司 用于半导体集成电路器件的功能数字测试的自动测试设备
CN105717439A (zh) * 2016-02-24 2016-06-29 上海东软载波微电子有限公司 芯片测试方法及系统
CN107391245A (zh) * 2017-07-18 2017-11-24 致象尔微电子科技（上海）有限公司 一种多核芯片的软件系统
CN111983532A (zh) * 2020-07-30 2020-11-24 南昌工程学院 石墨烯器件电磁性测试系统及其测试装置
CN112241160A (zh) * 2020-10-20 2021-01-19 广州小鹏汽车科技有限公司 车辆测试方法、装置、车辆检测系统以及测试板卡
CN112697455A (zh) * 2020-12-08 2021-04-23 上海纳恩汽车技术股份有限公司 一种实车自动化测试系统
CN113514759A (zh) * 2021-09-07 2021-10-19 南京宏泰半导体科技有限公司 一种多核测试处理器及集成电路测试系统与方法
CN114564429A (zh) * 2022-02-11 2022-05-31 北京智芯微电子科技有限公司 轻量级智能计算紧耦合结构及其数据处理方法
CN115421028A (zh) * 2022-09-29 2022-12-02 北京华峰测控技术股份有限公司 测试机、测试系统和测试方法

Also Published As

Publication number Publication date
CN115421028A (zh) 2022-12-02

Similar Documents

Publication Publication Date Title
WO2024067735A1 (zh) 测试机、测试系统和测试方法
CN1155069C (zh) 控制半导体集成电路测试过程的系统和方法
US6873927B2 (en) Control method of an automatic integrated circuit full testing system
JP5401514B2 (ja) 低減されたインデックスタイムのための検査システム及び方法
US20120131403A1 (en) Multi-chip test system and test method thereof
KR100699866B1 (ko) 로트 및 트레이 확인을 통한 반도체 소자의 연속검사 방법
US20070013362A1 (en) Framework that maximizes the usage of testhead resources in in-circuit test system
US8078424B2 (en) Test apparatus
US20040239359A1 (en) Device test apparatus and test method
JP2021071460A (ja) 自動回路基板試験システム及びその試験方法
US6505138B1 (en) Function-based control interface for integrated circuit tester prober and handler devices
JP3344548B2 (ja) Ｉｃ試験装置
WO2024067742A1 (zh) 测试机、测试控制装置及方法
TWI621191B (zh) 晶圓測試機台的遠端監控方法及系統
CN115237822B (zh) 一种针对晶圆级处理器iic配置接口的地址优化装置
CN112435937B (zh) 晶圆测试的自动化控制系统和方法
TWI676040B (zh) 半導體積體電路測試系統及其半導體積體電路測試裝置
CN116237276A (zh) 芯片测试方法、系统、装置及电子设备
CN112490215B (zh) 集成电路、芯片以及晶圆的功能测试方法
CN218213317U (zh) 测试机及测试系统
JP5319907B2 (ja) ソケット基板上にスイッチ素子を有するテスト装置
US7733112B2 (en) Semiconductor testing circuit and semiconductor testing method
CN110824330A (zh) 半导体集成电路测试系统及其半导体集成电路测试装置
US7478005B2 (en) Technique for testing interconnections between electronic components
TWI637177B (zh) 用於測試半導體元件之系統及方法