WO2024060647A1 - 像素电路、显示面板以及显示装置 - Google Patents

像素电路、显示面板以及显示装置 Download PDF

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Publication number
WO2024060647A1
WO2024060647A1 PCT/CN2023/095018 CN2023095018W WO2024060647A1 WO 2024060647 A1 WO2024060647 A1 WO 2024060647A1 CN 2023095018 W CN2023095018 W CN 2023095018W WO 2024060647 A1 WO2024060647 A1 WO 2024060647A1
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WIPO (PCT)
Prior art keywords
transistor
light
emitting element
signal
electrically connected
Prior art date
Application number
PCT/CN2023/095018
Other languages
English (en)
French (fr)
Inventor
宁雪强
李建雷
黄佩迪
陈杰
李克林
古涛
袁海江
Original Assignee
惠科股份有限公司
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Publication of WO2024060647A1 publication Critical patent/WO2024060647A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0254—Control of polarity reversal in general, other than for liquid crystal displays
    • G09G2310/0256—Control of polarity reversal in general, other than for liquid crystal displays with the purpose of reversing the voltage across a light emitting or modulating element within a pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/046—Dealing with screen burn-in prevention or compensation of the effects thereof

Definitions

  • the present application relates to the field of display technology, and in particular, to a pixel circuit, a display panel having the pixel circuit, and a display device having the display panel.
  • OLED organic light-emitting diode
  • the purpose of this application is to provide a pixel circuit, a display panel and a display device.
  • a first light-emitting element and a second light-emitting element are provided in the pixel circuit.
  • the control unit selectively controls the first light-emitting element and/or the second light-emitting element to emit light.
  • the control unit controls the first light-emitting element or the second light-emitting element to receive the second cathode. voltage, so that the accumulated charge is released when it does not emit light, further extending the display life of the light-emitting unit. Reduce the risk of screen burn-in and improve display quality.
  • the present application provides a pixel circuit, the pixel circuit comprising a light-emitting unit, a driving unit and a control unit, wherein the light-emitting unit comprises a first light-emitting element and a second light-emitting element, the first light-emitting element and the second light-emitting element are electrically connected to the driving unit and the control unit at the same time;
  • the driving unit is used to transmit a data signal for driving the first light-emitting element and/or the second light-emitting element to emit light to the light-emitting unit;
  • the control unit is used to control the first light-emitting element and/or the second light-emitting element to be electrically connected to a first power source;
  • the control unit selectively controls the first light-emitting element and/or the second light-emitting element to emit light.
  • the present application provides a display panel, which includes a plurality of the above-mentioned pixel circuits.
  • the present application provides a display device, which includes the above-mentioned display panel.
  • a control unit is provided in the pixel circuit, the light-emitting unit is provided with a first light-emitting element and a second light-emitting element, and the control unit selectively controls The first light-emitting element and/or the second light-emitting element selectively emit light to improve the display life of the pixel circuit.
  • control unit selectively controls the second end of the first light-emitting element or the second end of the second light-emitting element to be electrically connected to the second power supply to receive the second cathode voltage, and then When the light-emitting unit does not emit light, the accumulated charge is released to further enhance the display life of the light-emitting unit. Reduce the risk of screen burn-in and improve display quality.
  • a master control unit is provided in the display panel to perform block control on several pixel circuits in the display panel.
  • a master control unit is disposed in each display block, and the master control unit is used to control abnormal display phenomena.
  • the pixel circuit switches the light-emitting elements used for display together, further improving the efficiency of controlling the display effect.
  • Figure 1 is a schematic structural diagram of a display device disclosed in an embodiment of the present application.
  • FIG 2 is a schematic structural diagram of the display panel in the display device shown in Figure 1;
  • Figure 3 is a schematic structural diagram of the pixel unit in the display panel shown in Figure 2;
  • Figure 4 is a schematic circuit structure diagram of a pixel circuit disclosed in an embodiment of the present application.
  • Figure 5 is a schematic diagram of the specific circuit structure of the pixel circuit shown in Figure 4.
  • Figure 6 is a schematic diagram of the circuit structure of the control unit in the pixel circuit shown in Figure 5;
  • Figure 7 is a working timing diagram of the pixel circuit shown in Figure 5;
  • Figure 8 is a schematic diagram of another display panel disclosed in the embodiment of the present application.
  • Figure 9 is a timing diagram for the main control unit in the display panel shown in Figure 8 to send control signals;
  • FIG. 10 shows the addresses corresponding to each control unit in the display panel shown in FIG. 8 .
  • connection and “connection” mentioned in this application include direct and indirect connections (connections) unless otherwise specified.
  • the directional terms mentioned in this application such as “up”, “down”, “front”, “back”, “left”, “right”, “inside”, “outside”, “side”, etc., are only Reference is made to the direction of the attached drawings.
  • connection should be understood in a broad sense.
  • it can be a fixed connection or a detachable connection.
  • Ground connection, or integral connection can be a mechanical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium; it can be an internal connection between two components.
  • connection should be understood in a broad sense.
  • it can be a fixed connection or a detachable connection.
  • Ground connection, or integral connection can be a mechanical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium; it can be an internal connection between two components.
  • the specific meanings of the above terms in this application can be understood on a case-by-case basis.
  • the terms “first”, “second”, etc. in the description, claims, and drawings of this application are used to distinguish different objects, rather than describing a specific sequence.
  • the terms “include”, “can include”, “include”, or “can include” used in this application indicate the existence of the corresponding disclosed functions, operations, elements, etc., and do not limit other one or more more Functions, operations, components, etc.
  • the term “comprises” or “comprises” indicates the presence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, but does not exclude the presence or addition of one or more other features, numbers, steps, Operations, elements, parts, or combinations thereof, are intended to cover non-exclusive inclusion.
  • FIG1 is a schematic diagram of the structure of a display device 100 disclosed in an embodiment of the present application.
  • the display device 100 provided in an embodiment of the present application may at least include a display panel 10, a power module 20 and a support frame 30, wherein the display panel 10 is fixed to the support frame 30, and the power module 20 is arranged on the back side of the display panel 10, that is, the non-display surface of the display panel 10, that is, the side of the display panel 10 facing away from the user.
  • the display panel 10 is used to display images
  • the power module 20 is electrically connected to the display panel 10 to provide a power supply voltage for the display panel 10 to display images
  • the support frame 30 provides support and protection for the display panel 10 and the power module 20.
  • the display panel 10 also has a display surface arranged opposite to the non-display surface, that is, the front side of the display panel 10 , that is, the side of the display panel 10 facing the user.
  • the display surface is used to face a user using the display device 100 to display images.
  • FIG. 2 is a schematic structural diagram of the display panel 10 in the display device 100 shown in FIG. 1 .
  • the display panel 10 includes a display area 11 and a non-display area 13 .
  • the display area 11 is used for image display, and the non-display area 13 is arranged around the display area 11 and is not used for image display.
  • the display panel 10 may use liquid crystal material as the display medium, but is not limited thereto.
  • a plurality of scan lines (Scan lines) extending along the first direction F1 and a plurality of data lines (Data lines) extending along the second direction F2 are arranged in a grid shape inside the display panel 10 . line).
  • the first direction F1 and the second direction F2 (see FIG. 5 ) are perpendicular to each other, and the plurality of scanning lines, the plurality of data lines, and the scanning lines and the data lines are insulated from each other.
  • the plurality of scan lines are arranged at intervals along the second direction F2 and are insulated from each other
  • the plurality of data lines are arranged at intervals in the first direction F1 and are insulated from each other
  • the plurality of scan lines are arranged at intervals along the first direction F1 and are insulated from each other.
  • the data lines are insulated from each other.
  • Pixel circuits 40 are provided at the intersections of multiple scan lines and data lines (see FIG. 4 ). Specifically, the pixel circuit 40 is provided between any two adjacent scan lines and any two adjacent data lines, and the pixel circuits 40 located in the same column are electrically connected to the same data line. , the pixel circuits 40 located in the same row are electrically connected to the same scanning line. In the embodiment of the present application, multiple pixel circuits 40 are distributed in an array.
  • FIG. 3 is a schematic structural diagram of the pixel unit in the display panel 10 shown in FIG. 2 .
  • the display panel 10 includes pixel units 15 for display, and each pixel unit 15 corresponds to a pixel circuit 40 .
  • the pixel unit 15 includes multiple rows and multiple columns of sub-pixels, and each row includes a first sub-pixel 152, a second sub-pixel 154 and a third sub-pixel 156 arranged in sequence.
  • Each column contains multiple sub-pixels of the same color, and the sub-pixels in each row and the sub-pixels in each column form a pixel array.
  • the first sub-pixel 152 may be a red sub-pixel
  • the second sub-pixel 154 may be a green sub-pixel
  • the third sub-pixel 156 may be a blue sub-pixel.
  • Color (Blue) sub-pixel, the first sub-pixel 152, the second sub-pixel 154 and the third sub-pixel 156 may not follow the above corresponding principle, and the three may be sub-pixels of other color combinations, this application No specific restrictions are imposed.
  • each sub-pixel includes a first light-emitting element A and a second light-emitting element B.
  • the first sub-pixel 152, the second sub-pixel 154 and the third sub-pixel 156 each include the first light-emitting element A and the second light-emitting element B.
  • both the first light-emitting element A and the second light-emitting element B may be organic light-emitting diodes (OLED). Therefore, the The display panel 10 forms a dual-lamp OLED display.
  • FIG. 4 is a schematic circuit structure diagram of a pixel circuit 40 disclosed in an embodiment of the present application.
  • the pixel circuit 40 includes a control unit 50 , a light emitting unit 60 and a driving unit 70 .
  • the light-emitting unit 60 includes the first light-emitting element A and the second light-emitting element B. Both the first light-emitting element A and the second light-emitting element B are connected with the driving unit 70 and the control unit 70 .
  • the units 50 are electrically connected at the same time.
  • the driving unit 70 is used to transmit the data signal Data used to drive the first light-emitting element A and/or the second light-emitting element B to emit light to the light-emitting unit 60 .
  • the control unit 50 is used to control the first light-emitting element A and/or the second light-emitting element B to be electrically connected to the first power supply ELVSS.
  • the control unit 50 selectively controls the first light-emitting element A and/or the second light-emitting element B to emit light.
  • the color of light emitted by the light-emitting unit 60 may be the color corresponding to the light emitted by the first sub-pixel 152 , the second sub-pixel 154 , or the third sub-pixel 156 , and the present application does not impose any specific limitation thereto.
  • control unit 50 is also used to control the first light-emitting element A or the second light-emitting element B to be electrically connected to the second power supply ELVDD, for the first light-emitting element A or the second light-emitting element B to be electrically connected to the second power supply ELVDD.
  • the second light-emitting element B releases the electric charge accumulated inside it.
  • the first power supply ELVSS may be a low-potential pixel power supply
  • the second power supply ELVDD may be a high-potential pixel power supply, which is not specifically limited in this application.
  • the driving unit 70 includes a data input terminal, a scan input terminal and an output terminal.
  • the data input terminal is electrically connected to the data line, and the driving unit 70 receives the data signal Data through the data line.
  • the scan input terminal is electrically connected to the scan line, and the driving unit 70 receives the scan signal Scan through the scan line.
  • the driving unit 70 selectively controls the power supply signal VDD to be transmitted from the output end to the light-emitting unit 60 according to the received data signal Data and the scan signal Scan.
  • the driving unit 70 may include a first transistor 71 , a second transistor 73 and a storage capacitor 75 .
  • the first transistor 71 and the second transistor 73 each include a control terminal, a first terminal and a second terminal.
  • One end of the storage capacitor 75 is electrically connected to the second end of the first transistor 71
  • the other end of the storage capacitor 75 is electrically connected to the first end of the second transistor 73 .
  • the storage capacitor 75 is used to store image data that controls the light emitting unit 60 to emit light.
  • the control terminal of the first transistor 71 is electrically connected to the scan input terminal, and receives the scan signal Scan from the scan input terminal.
  • the first terminal of the first transistor 71 is electrically connected to the data input terminal, and receives the data signal Data from the data input terminal.
  • the second terminal of the first transistor 71 is electrically connected to the control panel of the second transistor 73 . end.
  • the first transistor 71 is selectively electrically turned on or electrically turned off according to the potential of the received scan signal Scan.
  • the data signal Data is transmitted from the second terminal of the first transistor 71 to the control terminal of the second transistor 73 .
  • the first terminal of the second transistor 73 is used to receive the power signal VDD, and the second terminal of the second transistor 73 is electrically connected to the output terminal.
  • the second transistor 73 is selectively in an on state or an off state according to the data signal Data received by the control terminal. That is, the second transistor 73 is selectively electrically turned on or off according to the potential of the received data signal Data, and then selectively transmits the power signal VDD to the output terminal.
  • the power signal VDD is transmitted to the output terminal. Further, the power signal VDD is transmitted to the light-emitting unit 60 through the output terminal.
  • the first potential may be a high potential
  • the second potential may be a low potential, which is not specifically limited in the present application.
  • the first transistor 71 and the second transistor 73 may be P-type metal-oxide semiconductor (P-Metal-Oxide-Semiconductor, PMOS) transistors, which are not specifically limited in this application.
  • the first terminal may be a drain
  • the second terminal may be a source
  • the control terminal may be a gate.
  • the light-emitting unit 60 may include the first light-emitting element A and the second light-emitting element B.
  • the first ends of the first light-emitting element A and the second light-emitting element B are both electrically connected to the output end, and the second ends of the first light-emitting element A and the second light-emitting element B are electrically connected to the control unit 50 .
  • the first end of the first light-emitting element A and the second light-emitting element B may be an anode, and the second end may be a cathode.
  • the control unit 50 receives the first signal ab and the second signal sw, and controls the first light-emitting element A and/or the first light-emitting element A and/or the first light-emitting element A according to the potential of the received first signal ab and the second signal sw.
  • the second terminal of the second light-emitting element B is electrically connected to the first power source ELVSS, thereby controlling the first light-emitting element A and/or the second light-emitting element B to selectively emit light.
  • the second end of the first light emitting element A is electrically connected to the first power source ELVSS, and receives a first cathode voltage from the first power source ELVSS. At this time, the first light emitting element A is used to emit light.
  • the second end of the second light-emitting element B is electrically connected to the first A power supply ELVSS and receiving a first cathode voltage from the first power supply ELVSS. At this time, the second light-emitting element B is used to emit light.
  • the first light-emitting element A and the second light-emitting element B are both electrically connected to the first power supply ELVSS, and simultaneously receive the first cathode voltage from the first power supply ELVSS. At this time, the first light-emitting element A and the second light-emitting element A Component B is used to emit light.
  • control unit 50 may also control the second terminal of the first light-emitting element A or the second light-emitting element B to be electrically connected to the second power supply ELVDD, and to receive the power from the second power source ELVDD.
  • the second power supply ELVDD receives the second cathode voltage.
  • the first terminal of the first light-emitting element A and/or the second light-emitting element B receives the power signal VDD, and the second terminal receives the second cathode voltage, then the first light-emitting element
  • the electric field formed outside the first light-emitting element A and/or the second light-emitting element B is in the same direction as the electric field formed by the accumulated charges inside the first light-emitting element A and/or the second light-emitting element B. is consumed, thereby increasing the display life of the light-emitting unit 60 and reducing the risk of screen burn-in.
  • the second light-emitting element B when the first signal ab received by the control unit 50 is at the first potential and the second signal sw is at the first potential, the second light-emitting element B
  • the second terminal is electrically connected to the second power supply ELVDD and receives a second cathode voltage from the second power supply ELVDD.
  • the electric field formed outside the second light-emitting element B is in the same direction as the electric field formed by the accumulated charges inside the second light-emitting element B.
  • the electric charges accumulated inside the second light-emitting element B are consumed, thereby improving the second luminescence.
  • the display life of component B reduces the risk of screen burn-in.
  • the second end of the first light-emitting element A is electrically connected to the first and a second power supply ELVDD, and receives a second cathode voltage from the second power supply ELVDD.
  • the electric field formed outside the first light-emitting element A is in the same direction as the electric field formed by the accumulated charges inside the first light-emitting element A.
  • the electric charges accumulated inside the first light-emitting element A are consumed, thereby improving the first luminescence.
  • the display life of component A reduces the risk of screen burn-in.
  • the first light-emitting element A and the second light-emitting element B are electrically connected to all the first power supply ELVSS, and receiving a first cathode voltage from the first power supply ELVSS.
  • the first light-emitting element A and the second light-emitting element B both emit light to supplement the light-emitting brightness of the light-emitting elements, avoid image sticking or screen burn-in problems caused by insufficient light-emitting brightness, and thereby increase the life of the pixel circuit 40 , improve the display effect of the display panel 10 .
  • the potential of the second cathode voltage of the second power supply ELVDD is higher than the potential of the power supply signal VDD.
  • the potential of the first cathode voltage of the first power supply ELVSS should be lower than the potential of the power signal VDD to ensure that the light-emitting element emits light normally.
  • the power signal VDD is used to drive the light-emitting element to emit light, and its voltage value should match the light-emitting brightness of the light-emitting element, which is not specifically limited in this application.
  • the preset switching time for the first signal ab to switch from the first potential to the second potential or from the second potential to the first potential.
  • the preset switching time can be determined according to the specific situation, so The preset switching time may be 1 frame, 10 frames, 100 frames or other values, and is not specifically limited in this application.
  • the switching time for the second signal sw to switch from the first potential to the second potential or from the second potential to the first potential can also be determined according to the actual situation, and is not specifically limited in this application.
  • the first light-emitting element A emits light: the driving unit 70 receives the scan signal Scan at the second potential and the data signal Data at the second potential, thereby causing the first transistor 71 and the second transistor 73 to be in a conductive state. , the power signal VDD is output from the output end to the light-emitting unit 60, and the first ends of the first light-emitting element A and the second light-emitting element B receive the power signal.
  • the control unit 50 receives the first signal ab at a first potential and the second signal sw at a first potential, and then the second terminal of the first light-emitting element A is electrically connected to the first power supply ELVSS.
  • the second terminal of the second light-emitting element B is electrically connected to the second power supply ELVDD to receive the second cathode voltage.
  • the first light-emitting element A emits light
  • the second light-emitting element B releases the charge accumulated inside.
  • the second light-emitting element B emits light: the driving unit 70 receives the scan signal Scan at the second potential and the data signal Data at the second potential, thereby causing the first transistor 71 and the second transistor 73 to be in a conductive state. , the power signal is output from the output end to the light-emitting unit 60, and the first ends of the first light-emitting element A and the second light-emitting element B receive the power signal.
  • the control unit 50 receives the first signal ab at the second potential and the second signal sw at the first potential, and then the second terminal of the second light-emitting element B is electrically connected to the first power supply ELVSS.
  • the second terminal of the first light-emitting element A is electrically connected to the second power supply ELVDD to receive the second cathode voltage.
  • the second light-emitting element B emits light, and the first light-emitting element A releases the charge accumulated inside.
  • the driving unit 70 receives the scan signal Scan at the second potential and the data signal Data at the second potential, thereby causing the first transistor 71 and the third light-emitting element B to emit light.
  • the two transistors 73 are in a conductive state, the power signal is output from the output end to the light-emitting unit 60, and the first ends of the first light-emitting element A and the second light-emitting element B both receive the power signal. .
  • the control unit 50 receives the second signal sw at a second potential, and then the second ends of the first light-emitting element A and the second light-emitting element B are both electrically connected to the first power supply ELVSS. The first cathode voltage is received. At this time, both the first light-emitting element A and the second light-emitting element B emit light.
  • FIG. 6 is a schematic diagram of the circuit structure of the control unit 50 in the pixel circuit 40 shown in FIG. 5 .
  • the control unit 50 includes a conduction selection unit 51, a conduction control unit 53 and a switch unit 55.
  • the conduction control unit 53 is electrically connected to the conduction selection unit 51 and the switch unit 55, and the switch unit is also electrically connected to the first light-emitting element and the second light-emitting element.
  • the conduction selection unit 51 is used to receive the control power signal VDD1 and the first signal ab, and selectively control the conduction control unit 53 to be in the first conduction state or the second conduction state according to the first signal ab.
  • the switch unit 55 receives the second signal sw, and the switch unit 55 controls the second end of the first light-emitting element and/or the second light-emitting element to be turned on to the first power supply according to the conduction state of the conduction selection unit 51 and the potential of the second signal sw. Specifically, the switch unit 55 controls the second end of the first light-emitting element A to be turned on to the first power supply ELVSS, and the second end of the second light-emitting element B to be turned on to the second power supply ELVDD, or,
  • the second ends of the first light-emitting element A and the second light-emitting element B are both connected to the first power supply ELVSS.
  • the conduction selection unit 51 includes a first selection transistor 511 , a second selection transistor 513 , a third selection transistor 515 and a fourth selection transistor 517 .
  • the control terminal of the first selection transistor 511 is used to receive the first signal ab
  • the control terminal of the second selection transistor 513 is used to receive the inverted signal BA of the first signal ab.
  • the first terminal of the first selection transistor 511 and the first terminal of the second selection transistor 513 receive the control power signal VDD1, and the second terminal of the first selection transistor 511 is electrically connected to the third selection transistor 513 at the same time.
  • the first terminal of the transistor 515 and the conduction control unit 53 receive the control power signal VDD1
  • the second terminal of the first selection transistor 511 is electrically connected to the third selection transistor 513 at the same time.
  • the first terminal of the transistor 515 and the conduction control unit 53 The second terminal of the second selection transistor 513 is electrically connected to the first terminal of the fourth selection transistor 517 and the conduction control unit 53 .
  • the control terminal of the third selection transistor 515 is electrically connected to the second terminal of the second selection transistor 513 .
  • the control terminal of the fourth selection transistor 517 is electrically connected to the second terminal of the first selection transistor 511 .
  • Said third option The second terminal of the transistor 515 and the second terminal of the fourth selection transistor 517 are both electrically connected to the first power supply ELVSS.
  • control terminal of the first selection transistor 511 is used to receive the first signal ab, and the first signal ab controls the voltage of the first terminal and the second terminal of the first selection transistor 511.
  • First signal ab controls the voltage of the first terminal and the second terminal of the first selection transistor 511.
  • control terminal of the fourth selection transistor 517 is used to receive the control power signal VDD1 from the second terminal of the first selection transistor 511, and the control power signal VDD1 controls the first The selection transistor 511 is in an on or off state. At the same time, the control power signal VDD1 is selectively transmitted from the second end of the first selection transistor 511 to the conduction control unit 53 .
  • the control terminal of the fourth selection transistor 517 does not receive the control power signal VDD1 and is in a cut-off state.
  • the control power signal VDD1 cannot be transmitted from the second terminal of the first selection transistor 511 to the conduction control unit 53 .
  • the first terminal and the second terminal of the first selection transistor 511 are electrically connected, and the control power signal VDD1 is transmitted from the first terminal to the second terminal.
  • the control terminal of the fourth selection transistor 517 receives the control power signal VDD1 and is in a conductive state.
  • the control power signal VDD1 is transmitted from the second terminal of the first selection transistor 511 to the conduction control unit 53 .
  • control terminal of the second selection transistor 513 is used to receive the inverted signal BA of the first signal ab, and the inverted signal BA controls the first terminal of the second selection transistor 513 and the second terminal are electrically connected or disconnected.
  • the control terminal of the third selection transistor 515 is used to receive the control power signal VDD1 from the second terminal of the second selection transistor 513.
  • the control power signal VDD1 controls the third selection transistor 515.
  • the selection transistor 515 is in an on or off state.
  • the control power signal VDD1 is selectively transmitted from the second end of the second selection transistor 513 to the conduction control unit 53 .
  • the inverted signal BA is at the first potential
  • the first terminal and the second terminal of the second selection transistor 513 are electrically disconnected, and the control power signal VDD1 cannot be transmitted from the third terminal of the second selection transistor 513 . transmitted from one end to the second end.
  • the control terminal of the third selection transistor 515 does not receive the control power signal VDD1 and is in a cut-off state.
  • the control power signal VDD1 cannot be transmitted from the second terminal of the second selection transistor 513 to the conduction control unit 53 .
  • the first terminal and the second terminal of the second selection transistor 513 are electrically conductive, and the control power signal VDD1 is generated from the first terminal of the second selection transistor 513 . end to the second end.
  • the control terminal of the third selection transistor 515 receives the control power signal VDD1 and is in a conductive state. Said control The power supply signal VDD1 is transmitted from the second terminal of the second selection transistor 513 to the conduction control unit 53 .
  • the conduction control unit 53 includes a first conduction transistor 531 and a second conduction transistor 533 .
  • the control terminal of the first pass transistor 531 is electrically connected to the second terminal of the second selection transistor 513
  • the control terminal of the second pass transistor 533 is electrically connected to the first selection transistor 511 .
  • the first terminals of the first pass transistor 531 and the second pass transistor 533 are both electrically connected to the first power supply ELVSS.
  • the second terminals of the first pass transistor 531 and the second pass transistor 533 are both electrically connected to the switch unit 55 .
  • control terminal of the first pass transistor 531 is used to receive the control power signal VDD1 from the second terminal of the second selection transistor 513, and the control power signal VDD1 controls the third A pass transistor 531 is in the on or off state.
  • the control terminal of the second pass transistor 533 is used to receive the control power signal VDD1 from the second terminal of the first selection transistor 511.
  • the control power signal VDD1 controls the second pass transistor 533 to be on or off. Deadline status.
  • control power supply signal VDD1 is always at the first potential
  • first pass transistor 531 or the second pass transistor 533 receives the control power supply signal VDD1
  • the first pass transistor 531 or the second pass transistor 533 The second pass transistor 533 is in a conductive state.
  • the second end of the first pass transistor 531 or the second pass transistor 533 is both conductive to the first power supply ELVSS.
  • the control terminal of the first pass transistor 531 receives the control power signal VDD1 from the second terminal of the second selection transistor 513, the first pass transistor 531 is in a conductive state, so The second pass transistor 533 is in an off state. At this time, the conduction control unit 53 is in the first conduction state.
  • the control terminal of the second conduction transistor 533 When the control terminal of the second conduction transistor 533 receives the control power signal VDD1 from the second terminal of the first selection transistor 511, the first conduction transistor 531 is in an off state, and the second conduction transistor 533 is in an off state.
  • the pass transistor 533 is in a conductive state. At this time, the conduction control unit 53 is in the second conduction state.
  • the switch unit 55 includes a first release transistor 551 , a second release transistor 552 , a third release transistor 554 and a fourth release transistor 556 .
  • the control terminal of the first release transistor 551 is electrically connected to the second terminal of the first pass transistor 531
  • the control terminal of the second release transistor 552 is electrically connected to the second pass transistor 533 .
  • the first terminals of the first release transistor 551 and the second release transistor 552 are both electrically connected to the second power supply ELVDD.
  • the second terminal of the first release transistor 551 is electrically connected to the second terminal of the second pass transistor 533
  • the second terminal of the second release transistor 552 is electrically connected to the first pass transistor.
  • the control end of the third release transistor 554 is used to receive the second signal sw.
  • the first end of the third release transistor 554 is electrically connected to the second end of the second pass transistor 533 and the second pass transistor 533 .
  • the first release transistor 551 Two ends.
  • the second terminal of the third release transistor 554 is electrically connected to the second terminal of the second light-emitting element B.
  • the control terminal of the fourth release transistor 556 receives the second signal sw, and the first terminal of the fourth release transistor 556 is electrically connected to the second terminal of the first pass transistor 531 and the first pass transistor 531 at the same time.
  • the second terminal of the fourth release transistor 556 is electrically connected to the second terminal of the first light-emitting element A.
  • the control terminal of the first release transistor 551 is used to receive the first cathode voltage of the first power supply ELVSS from the second terminal of the first pass transistor 531.
  • the first power supply The first cathode voltage of ELVSS controls the first terminal and the second terminal of the first release transistor 551 to be electrically conductive.
  • the control terminal of the second release transistor 552 is used to receive the first cathode voltage of the first power supply ELVSS from the second terminal of the second pass transistor 533.
  • the first cathode voltage of the first power supply ELVSS is controlled by
  • the first terminal and the second terminal of the second release transistor 552 are electrically conductive.
  • the first cathode voltage is always at the second potential
  • the control terminal of the first release transistor 551 or the second release transistor 552 receives the first cathode voltage
  • the The first release transistor 551 or the second release transistor 552 is in a conductive state.
  • the second cathode voltage of the second power supply ELVDD is transmitted from the first terminal of the first release transistor 551 or the second release transistor 552 to the second terminal.
  • control terminal of the third release transistor 554 receives a second signal sw, and the second signal sw controls the third release transistor 554 to be in an on or off state.
  • the third release transistor 554 when the second signal sw is at the first potential, the third release transistor 554 is in a conductive state. When the second signal sw is at the second potential, the third release transistor 554 is in the off state.
  • control end of the fourth release transistor 556 receives a second signal sw, and the second signal sw controls the fourth release transistor 556 to be in an on or off state.
  • the fourth release transistor 556 when the second signal sw is at the first potential, the fourth release transistor 556 is in a conductive state. When the second signal sw is at the second potential, the fourth release transistor 556 is in the off state.
  • the third release transistor 554 is in a conductive state, and when the conduction control unit 53 is in a first conductive state, the first light-emitting element A is used to emit light.
  • the fourth release transistor 556 is in a conductive state, and when the conduction control unit 53 is in a second conductive state, the second light-emitting element B is used to emit light.
  • the switching unit 55 further includes a first switching transistor 555 and a second switching transistor 553 .
  • the control terminals of the first switching transistor 555 and the second switching transistor 553 are used to receive the second signal sw.
  • the first terminals of the first switching transistor 555 and the second switching transistor 553 are electrically uniform.
  • the second terminal of the first switching transistor 555 is electrically connected to the second terminal of the first light-emitting element A, and the second terminal of the second switching transistor 553 is electrically connected to the second terminal of the second light-emitting element B. Second end.
  • the second signal sw controls the first switching transistor 555 and the second switching transistor 553 to be in an on or off state.
  • both the first switching transistor 555 and the second switching transistor 553 are in a conductive state, and the first switching transistor 555 and the second switching transistor 553
  • the second terminals are both electrically connected to the first power supply ELVSS, so the second terminals of the first light-emitting element A and the second light-emitting element B are both electrically connected to the first power supply ELVSS.
  • the first light-emitting element A and the second light-emitting element B emit light at the same time to supplement the light-emitting brightness of the light-emitting element, avoid image sticking or screen burn-in problems caused by insufficient light-emitting brightness, and thereby improve the pixel circuit 40
  • the service life of the display panel 10 is improved.
  • both the first switching transistor 555 and the second switching transistor 553 are in a cut-off state.
  • the signal inputs of the second ends of the first light-emitting element A and the second light-emitting element B are controlled by a first release transistor 551 , a second release transistor 552 , a third release transistor 554 and a fourth release transistor 556 .
  • the conduction control unit 53 when the conduction control unit 53 is in the first conduction state and the second signal sw is at the first potential, the first release transistor 551 and the third release transistor 554.
  • the fourth release transistor 556 is in the on state, the second release transistor 552 is in the off state, and the first cathode voltage of the first power supply ELVSS is transmitted to the second end of the first light emitting element A,
  • the first light-emitting element A is used to emit light
  • the second cathode voltage of the second power supply ELVDD is transmitted to the second end of the second light-emitting element B;
  • the conduction control unit 53 When the conduction control unit 53 is in the second conduction state and the second signal sw is at the first potential, the second release transistor 552 , the third release transistor 554 , and the fourth release transistor 556 is in the on state, the first release transistor 551 is in the off state, the first cathode voltage of the first power supply ELVSS is transmitted to the second end of the second light emitting element B, and the second light emitting element B is In order to emit light, the second cathode voltage of the second power supply ELVDD is transmitted to the second terminal of the first light-emitting element A.
  • the first switching transistor 555 and the second switching transistor 553 are both in the conduction state, so The first cathode voltage of the first power supply ELVSS is transmitted to the second terminals of the first light-emitting element A and the second light-emitting element B respectively.
  • the transistor 551, the second release transistor 552, the first switch transistor 555, the third release transistor 554, the second switch transistor 553 and the fourth release transistor 556 may be metal-oxide semiconductor field effect transistors (Metal-Oxide-Semiconductor). Field-Effect Transistor, MOSFET), this application does not impose specific restrictions on this.
  • the fourth release transistor 556 may be an N-channel MOS field effect transistor.
  • the first selection transistor 511, the second selection transistor 513, the first release transistor 551, the second release transistor 552, the first switching transistor 555 and the second switching transistor 553 may be P-channel MOS field effect transistors. This application does not impose specific restrictions on this.
  • the first terminal of the four release transistors 556 may be a drain, the second terminal may be a source, and the control terminal may be a gate.
  • the first terminal of the first pass transistor 531, the second pass transistor 533, the first switching transistor 555 and the second switching transistor 553 may be a source, and the second terminal may be a source. Drain, the control terminal can be a gate.
  • control unit 50 controls the light-emitting process of the first light-emitting element A and/or the second light-emitting element B will be described.
  • the first light-emitting element A is used to emit light: when the first signal ab is at the first potential and the second signal sw is at the first potential, the first selection transistor 511 is in the off state, and the second selection transistor 511 is in the off state. Transistor 513 is in a conductive state. Therefore, the fourth selection transistor 517 is in the off state.
  • the control power signal VDD1 is transmitted from the first terminal to the second terminal of the second selection transistor 513 .
  • the control terminals of the third selection transistor 515 and the first conduction transistor 531 receive the control power signal VDD1 from the second terminal of the second selection transistor 513 and are both in a conductive state. Therefore, the first cathode voltage of the first power supply ELVSS is transmitted to the second terminal of the first pass transistor 531 .
  • the control terminal of the fourth release transistor 556 receives the second signal sw at the first potential and is in a conductive state, the first cathode voltage is transmitted from the second terminal of the first conduction transistor 531 to the second terminal of the fourth release transistor 556, and then transmitted to the second terminal of the first light-emitting element A. Further, the first light-emitting element A is used to emit light.
  • the control terminal of the first release transistor 551 receives the first cathode voltage from the second terminal of the first pass transistor 531 and is in the conductive state
  • the second cathode voltage of the second power supply ELVDD is transmitted from the first terminal of the first release transistor 551 to the second terminal. Since the control terminal of the third release transistor 554 receives the second signal sw at the first potential and is in a conductive state, further, the second cathode voltage is transmitted to the third release transistor 554 via the third release transistor 554 .
  • the second end of the second light-emitting element B At this time, the second light-emitting element B does not emit light and releases internal accumulated charges to avoid display afterimages and enhance display life.
  • the second light-emitting element B is used to emit light: when the first signal ab is at the second potential and the second signal sw is at the first potential, the first selection transistor 511 is in a conductive state, and the second The selection transistor 513 is in the off state. Therefore, the third selection transistor 515 is in the off state.
  • the control power signal VDD1 is generated from the first selection The first terminal of transistor 511 passes to the second terminal.
  • the control terminals of the fourth selection transistor 517 and the second conduction transistor 533 receive the control power signal VDD1 from the second terminal of the first selection transistor 511 and are both in a conductive state. Therefore, the first cathode voltage of the first power supply ELVSS is transmitted to the second terminal of the second pass transistor 533 .
  • the control terminal of the third release transistor 554 receives the second signal sw at the first potential and is in a conductive state, the first cathode voltage is transmitted from the second terminal of the second conduction transistor 533 to the second terminal of the third release transistor 554, and then transmitted to the second terminal of the second light-emitting element B. At this time, the second light-emitting element B is used to emit light.
  • the control terminal of the second release transistor 552 receives the first cathode voltage from the second terminal of the second conduction transistor 533 and is in the conduction state, then the second cathode voltage of the second power supply ELVDD is transmitted from the first terminal of the second release transistor 552 to the second terminal. Since the control terminal of the fourth release transistor 556 receives the second signal sw at the first potential and is in a conductive state, further, the second cathode voltage is transmitted to the fourth release transistor 556 through the fourth release transistor 556 . the second end of the first light-emitting element A. At this time, the first light-emitting element A does not emit light and releases internal accumulated charges to avoid display afterimages and enhance display life.
  • the first light-emitting element A and the second light-emitting element B are used to emit light at the same time: when the second signal sw is at the second potential, the first switching transistor 555 and the second switching transistor 553 are both at In the on state, the second terminals of the first switching transistor 555 and the second switching transistor 553 are both electrically connected to the first power supply ELVSS, then the first light-emitting element A and the second light-emitting element A The second terminals of component B are electrically connected to the first power source ELVSS.
  • the first light-emitting element A and the second light-emitting element B emit light at the same time, which is used to supplement the light-emitting brightness of the light-emitting element, avoid image sticking or screen burn-in problems caused by insufficient light-emitting brightness, and thereby improve the pixel circuit
  • the service life is 40 years, which improves the display effect of the display panel 10 .
  • FIG. 7 is an operating timing diagram of the pixel circuit 40 shown in FIG. 5 .
  • the corresponding curves of Scan n and Scan n+1 respectively correspond to the timing of any two adjacent data lines.
  • the curve corresponding to Data is the timing corresponding to the data signal Data
  • the curve corresponding to ab is the first
  • the timing corresponding to signal ab and the curve corresponding to sw are the timing corresponding to the second signal sw.
  • the potential switching of the first signal ab has a preset switching time, that is, the potential of the first signal ab switches once every time the preset switching time passes.
  • the preset switching time may be 200 frames. It is understood that the preset switching time may be determined according to the specific conditions of the display device 100 and is not specifically limited in this application.
  • the pixel circuit 40 is provided with a control unit 50, and the light-emitting unit 60 is provided with a first light-emitting element A and a second light-emitting element B.
  • the first light-emitting element is selectively controlled by the control unit 50.
  • a and/or the The second light-emitting element B selectively emits light to improve the display life of the pixel circuit 40 .
  • control unit 50 selectively controls the first light emitting element A or the second light emitting element B to be electrically connected to the second power source ELVDD to receive the second cathode voltage, thereby releasing the charges accumulated therein when the first light emitting element A or the second light emitting element B does not emit light, thereby further improving the display life of the light emitting unit 60, thereby reducing the risk of screen burn-in and improving display quality.
  • this application also provides a display panel 10 , which includes a plurality of the above-mentioned pixel circuits 40 .
  • FIG8 is a schematic diagram of another display panel 1 disclosed in an embodiment of the present application.
  • the display panel 1 is different from the display panel 10 in that the display panel 1 further includes a general control unit 18, the general control unit 18 is electrically connected to a plurality of the pixel circuits 40, and the general control unit 18 is used to simultaneously control the plurality of pixel circuits 40 to switch to the first light-emitting element A and/or the second light-emitting element B to emit light.
  • the figure shows a display block in the display panel 1 , and the display block includes nine pixel circuits 40 .
  • the pixel circuits 40 in the display panel 1 are controlled in blocks, and the number of pixel circuits included in each display block can be determined according to the actual situation, and this application does not specifically limit this.
  • connection between the total control unit 18 and the pixel circuit 40 can be realized through an integrated circuit bus (Inter-Integrated Circuit, IIC), serial peripheral interface (Serial Peripheral Interface, SPI), etc.
  • IIC Inter-Integrated Circuit
  • SPI Serial Peripheral Interface
  • the display panel 10 includes multiple pixel circuits 40, each pixel circuit 40 includes a control unit 50, and each control unit 50 corresponds to an address.
  • the control signal includes a start segment, a number of address segments and a number of instruction segments, and the start segment includes a start signal at a first potential of 0.5 milliseconds (ms).
  • Each address segment is a 4 microsecond (us) data signal containing the block address.
  • Each command segment is a 2 microsecond (us) data signal containing command information.
  • control signal includes a starting part and several data parts.
  • the starting part does not contain data information.
  • Each data part contains 6 bytes (bits) of data, of which the first 4 bytes (bits) are the corresponding Displays the address of the block, and the last 2 bytes (bits) are the corresponding signal instructions.
  • the signal instruction corresponds to the second signal sw and the first signal ab.
  • the display block controlled by the overall control unit 18 receives a control signal, and the address segment of the control signal identifies the corresponding control unit and then continues to output the instruction segment of the control signal to control the pixel circuit. 40 switches the light-emitting element used to emit light. It can be understood that the pixel circuit 40 that does not correspond to the address segment of the control signal continues to emit light from the light-emitting element originally used to emit light.
  • the time of 1 bit is 1 us. This application does not impose specific restrictions on this.
  • the length of the signal contained in the control signal can be determined according to the actual situation.
  • FIG. 9 is a timing diagram of the control signal issued by the main control unit 18 in the display panel 1 shown in FIG. 8 .
  • FIG. 10 shows the addresses corresponding to each control unit in the display panel 1 shown in FIG. 8 .
  • the starting segment of the control signal is "111111” and the first address segment is 0001.
  • the first command segment is 11, where the first 1 in the first command segment corresponds to the first signal ab being at the first potential, and the second 1 corresponds to the second signal sw being at the first potential.
  • the second address segment is 0010.
  • the second command segment is also 11, where the first 1 in the second command segment corresponds to the first signal ab being at the first potential, and the second 1 indicates that the second signal sw is at the first potential.
  • the third address segment is 0011, and the third instruction segment is 01, where 0 in the third instruction segment corresponds to the first signal ab being at the second potential, and 1 corresponds to the second signal sw being at the first potential.
  • Different control units 50 receive or do not receive the instruction segment according to the received control signal address segment. Specifically, the overall control unit 18 sends the instruction signal corresponding to the address segment to the control unit 50 corresponding to the address segment, thereby controlling the pixel circuit 40 to switch the light-emitting element for light emission.
  • control units 50 of the nine pixel circuits 40 shown in FIG. 8 are sequentially recorded as control unit 1 , control unit 2 to control unit 9 , then the corresponding addresses of the nine control units 50 are as shown in the figure. .
  • the overall control unit 18 is electrically connected to the nine control units 50 of the pixel circuits 40 .
  • the overall control unit 18 can control two or more pixel circuits 40 to switch light-emitting units. 60% of the light-emitting element emits light.
  • abnormal display refers to phenomena such as screen burning and image retention.
  • the overall control unit controls two pixel circuits 40 to switch light-emitting elements at the same time
  • the two pixel circuits in the display area are denoted as a first pixel circuit and a second pixel circuit.
  • the overall control unit 18 when the first light-emitting element A of the first pixel circuit displays abnormality and the second light-emitting element B of the second pixel circuit displays abnormality, at this time, through the overall control unit 18 At the same time, the first pixel circuit and the second pixel circuit are controlled to switch to another light-emitting element for screen display. That is, the first pixel circuit switches to the second light-emitting element B for display, and the second pixel circuit switches to the first light-emitting element A for display. It can be understood that the overall control unit 18 can also control three, four or other numbers of pixel circuits 40 to switch light-emitting elements at the same time, and this application does not specifically limit this.
  • this application also provides a display device 100, which includes the above-mentioned display panel.
  • a control unit 50 is provided in the pixel circuit 40, the display panel and the display device 100 of the present application, and the light-emitting unit 60 is provided with a first light-emitting element A and a second light-emitting element B.
  • the control unit 50 selective control The first light-emitting element A and/or the second light-emitting element B are controlled to selectively emit light, so as to improve the display life of the pixel circuit 40 .
  • control unit 50 selectively controls the first light-emitting element A or the second light-emitting element B to be electrically connected to the second power supply ELVDD to receive the second cathode voltage, and then when it does not emit light The accumulated charge is released when the light emitting unit 60 is used to further increase the display life of the light emitting unit 60 . Reduce the risk of screen burn-in and improve display quality.
  • a general control unit 18 is provided in the display panel to perform block control on a number of pixel circuits 40 in the display panel.
  • a general control unit 18 is provided in each display block. The general control unit 18 is used to switch the light-emitting elements used for display together with the pixel circuits 40 that have abnormal display phenomena, thereby further improving the efficiency of controlling the display effect.

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Abstract

一种像素电路(40)、显示面板(1、10)及显示装置(100)。像素电路(40)包括控制单元(50)、发光单元(60)和驱动单元(70)，控制单元(50)控制发光单元(60)的第一发光元件(A)和/或第二发光元件(B)电性连接至第一电源ELVSS以发光。在像素电路(40)中，设置第一发光元件(A)和第二发光元件(B)，控制单元(50)控制发光单元(60)的一发光元件发光，另一发光元件接收第二阴极电压以释放其内积累的电荷，提升发光单元(60)的显示寿命，降低烧屏的风险。

Description

像素电路、显示面板以及显示装置
本申请要求于2022年09月20日提交中国知识产权局，申请号为202211145865.8，申请名称为“像素电路、显示面板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种像素电路、一种具有该像素电路的显示面板以及一种具有该显示面板的显示装置。
背景技术
随着显示技术的发展，市场对于显示装置的显示效果和品味的要求逐渐提升。现有市场中，有机发光二极管(Organic Light-Emitting Diode，OLED)显示屏大多采用直流驱动的方式。然而，在直流驱动方式下，OLED在空穴传输层与发光层的界面处或发光层与电子传输层的界面处积累未复合的多余载流子。这些未复合的多余载流子的数量积累到一定程度后，会在内部形成内建电场。但是形成的内建电场会导致下一周期的载流子注入困难，进而导致复合率降低，从而影响OLED显示屏的显示品味以及显示寿命。
发明内容
本申请的目的是提供一种像素电路、显示面板及显示装置。像素电路中设置第一发光元件和第二发光元件，控制单元选择性控制第一发光元件和/或第二发光元件发光，同时，控制单元控制第一发光元件或第二发光元件接收第二阴极电压，使其不发光时释放其内积累的电荷，进一步提升发光单元的显示寿命。降低烧屏的风险，提升显示品味。
第一方面，本申请提供了一种像素电路，所述像素电路包括发光单元、驱动单元和控制单元，其中，所述发光单元包括第一发光元件和第二发光元件，所述第一发光元件和所述第二发光元件与所述驱动单元和所述控制单元同时电性连接；所述驱动单元用于向所述发光单元传输用于驱动所述第一发光元件和/或所述第二发光元件发光的数据信号；所述控制单元用于控制所述第一发光元件和/或所述第二发光元件电性连接至第一电源；
所述发光单元在接收到所述数据信号时，所述控制单元选择性控制所述第一发光元件和/或所述第二发光元件发光。
第二方面，本申请提供了一种显示面板，所述显示面板包括若干上述的像素电路。
第三方面，本申请提供了一种显示装置，所述显示装置包括上述的显示面板。
综上所述，在本申请的像素电路、显示面板和显示装置中，所述像素电路中设置控制单元，所述发光单元设置第一发光元件和第二发光元件，所述控制单元选择性控制所述第一发光元件和/或所述第二发光元件选择性发光，以提升所述像素电路的显示寿命。同时，所述控制单元选择性控制所述第一发光元件的第二端或所述第二发光元件的第二端电性连接于至所述第二电源以接收所述第二阴极电压，进而在其不发光时释放其内积累的电荷，进一步提升所述发光单元的显示寿命。降低烧屏的风险，提升显示品味。
此外，在所述显示面板中设置总控制单元，对所述显示面板中的若干像素电路进行区块化控制，在每一个显示区块设置总控制单元，利用总控制单元对出现显示异常现象的像素电路一同切换用于显示的发光元件，进一步提高控制显示效果的效率。
附图说明
为了更清楚地说明本申请实施方式或现有技术中的技术方案，下面将对实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例公开的一种显示装置的结构示意图；
图2为图1所示的显示装置中显示面板的结构示意图；
图3为图2所示的显示面板中像素单元的结构示意图；
图4为本申请实施例公开的一种像素电路的电路结构示意图；
图5为图4所示的像素电路的具体电路结构示意图；
图6为图5所示的像素电路中控制单元的电路结构示意图；
图7为图5所示的像素电路的工作时序图；
图8为本申请实施例公开的另一种显示面板的示意图；
图9为图8所示的显示面板中的总控制单元发出控制信号的时序图；
图10为图8所示的显示面板中各控制单元对应的地址。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的较佳实施方式。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述 的实施方式。相反地，提供这些实施方式的目的是使对本申请的公开内容理解的更加透彻全面。
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本文中为部件所编序号本身，例如“第一”、“第二”等，仅用于区分所描述的对象，不具有任何顺序或技术含义。而本申请所说“连接”、“联接”，如无特别说明，均包括直接和间接连接(联接)。本申请中所提到的方向用语，例如，“上”、“下”、“前”、“后”、“左”、“右”、“内”、“外”、“侧面”等，仅是参考附加图式的方向，因此，使用的方向用语是为了更好、更清楚地说明及理解本申请，而不是指示或暗指所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸地连接，或者一体地连接；可以是机械连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。需要说明的是，本申请的说明书和权利要求书及所述附图中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。此外，本申请中使用的术语“包括”、“可以包括”、“包含”、或“可以包含”表示公开的相应功能、操作、元件等的存在，并不限制其他的一个或多个更多功能、操作、元件等。此外，术语“包括”或“包含”表示存在说明书中公开的相应特征、数目、步骤、操作、元素、部件或其组合，而并不排除存在或添加一个或多个其他特征、数目、步骤、操作、元素、部件或其组合，意图在于覆盖不排他的包含。还需要理解的是，本文中描述的“至少一个”的含义是一个及其以上，例如一个、两个或三个等，而“多个”的含义是至少两个，例如两个或三个等，除非另有明确具体的限定。本申请的说明书和权利要求书及所述附图中的术语“步骤1”、“步骤2”等是用于区别不同对象，而不是用于描述特定顺序。
请参阅图1，图1为本申请实施例公开的一种显示装置100的结构示意图。如图1所示，本申请实施例提供的显示装置100至少可以包括显示面板10、电源模组20和支撑框架30，其中，所述显示面板10固定于支撑框架30，所述电源模组20设置于所述显示面板10的背面，即所述显示面板10的非显示面，也即所述显示面板10背对用户的一侧。所述显示面板10用于显示图像，所述电源模组20与所述显示面板10电性连接，用于为所述显示面板10行图像显示提供电源电压，所述支撑框架30为所述显示面板10和所述电源模组20提供支撑与保护作用。
可以理解的是，所述显示面板10还具有与所述非显示面相对设置的显示面，即所述显示面板10的正面，也即所述显示面板10面对用户的一侧。所述显示面用于面对使用所述显示装置100的用户，以显示图像。
请一并参阅图2，图2为图1所示的显示装置100中显示面板10的结构示意图。如图2所示，所述显示面板10包括显示区11以及非显示区13。其中，所述显示区11用作图像显示，所述非显示区13环绕设置于所述显示区11周围，并不用作图像显示。可以理解，在一些实施方式中，所述显示面板10可以以液晶材料作为显示介质，并不以此为限。
在本申请实施例中，显示面板10的内部互相呈网格状设置有沿着第一方向F1延伸的多条扫描线(Scan line)和沿着第二方向F2延伸的多条数据线(Data line)。其中，所述第一方向F1与第二方向F2(见图5)相互垂直，并且多条扫描线之间、多条数据线之间、以及扫描线与数据线之间均相互绝缘。也即，多条扫描线之间沿着所述第二方向F2间隔排列设置且相互绝缘，多条数据线之间所述第一方向F1间隔排列设置且相互绝缘，多条扫描线与多条数据线之间相互绝缘设置。
多条扫描线和数据线的交叉部均对应设置像素电路40(见图4)。具体为，任意相邻的两条扫描线和任意相邻的两条数据线之间设置有所述像素电路40，位于同一列的所述像素电路40均与同一条所述数据线电性连接，位于同一行的所述像素电路40均与同一条所述扫描线电性连接。本申请实施例中，多个像素电路40呈阵列分布。
请一并参阅图3，图3为图2所示的显示面板10中像素单元的结构示意图。如图3所示，所述显示面板10包括用于显示的像素单元15，每个像素单元15对应一个像素电路40。所述像素单元15包括多行多列子像素，每一行包括依次排列的第一子像素152、第二子像素154和第三子像素156。每一列包含同一颜色的多个子像素，每一行的子像素和每一列的子像素形成了像素阵列。
在本申请具体实施例中，所述第一子像素152可以为红色(Red)子像素，所述第二子像素154可以为绿色(Green)子像素，所述第三子像素156可以为蓝色(Blue)子像素，所述第一子像素152、第二子像素154和第三子像素156也可以不遵循上述的对应原则，三者可为其他颜色组合的子像素，本申请对此不做具体限制。
如图3所示，在本申请实施例中，每个子像素中均包含第一发光元件A和第二发光元件B。具体地，所述第一子像素152、所述第二子像素154和所述第三子像素156均包括所述第一发光元件A和所述第二发光元件B。其中，在示意性实施例中，所述第一发光元件A和所述第二发光元件B均可为有机发光二极管(Organic Light-Emitting Diode，OLED)，因此，所 述显示面板10形成了双灯OLED显示。
请一并参阅图4，图4为本申请实施例公开的一种像素电路40的电路结构示意图。如图4所示，在本申请实施例中，像素电路40包括控制单元50、发光单元60和驱动单元70。其中，所述发光单元60包括所述第一发光元件A和所述第二发光元件B，所述第一发光元件A和所述第二发光元件B均与所述驱动单元70和所述控制单元50同时电性连接。
所述驱动单元70用于向所述发光单元60传输用于驱动所述第一发光元件A和/或所述第二发光元件B发光的数据信号Data。所述控制单元50用于控制所述第一发光元件A和/或所述第二发光元件B电性连接至第一电源ELVSS。所述发光单元60在接收到所述数据信号Data时，所述控制单元50选择性控制所述第一发光元件A和/或所述第二发光元件B发光。
在本申请具体实施例中，所述发光单元60发光的颜色可以为所述第一子像素152、所述第二子像素154或所述第三子像素156对应发光的颜色，本申请不做具体限制。
在本申请实施例中，所述控制单元50还用于控制所述第一发光元件A或所述第二发光元件B电性连接至第二电源ELVDD，用于所述第一发光元件A或所述第二发光元件B释放其内部积累的电荷。
在本申请具体实施例中，所述第一电源ELVSS可以为低电势像素电源，所述第二电源ELVDD可以为高电势像素电源，本申请对此不做具体限制。
请一并参阅图5，图5为图4所示的像素电路40的具体电路结构示意图。如图5所示，在本申请实施例中，所述驱动单元70包括数据输入端、扫描输入端和输出端。所述数据输入端电性连接至所述数据线，所述驱动单元70通过所述数据线接收所述数据信号Data。所述扫描输入端电性连接至所述扫描线，所述驱动单元70通过所述扫描线接收扫描信号Scan。所述驱动单元70根据接收到的所述数据信号Data和所述扫描信号Scan选择性控制电源信号VDD自所述输出端传输至所述发光单元60。
在本申请具体实施例中，所述驱动单元70可以包括第一晶体管71、第二晶体管73和存储电容75。具体地，所述第一晶体管71和所述第二晶体管73均包括控制端、第一端和第二端。所述存储电容75的一端电性连接至所述第一晶体管71的第二端，所述存储电容75的另一端电性连接至所述第二晶体管73的第一端。所述存储电容75用于存储控制所述发光单元60发光的图像数据。
所述第一晶体管71的控制端电性连接至所述扫描输入端，自所述扫描输入端接收所述扫描信号Scan。所述第一晶体管71的第一端电性连接至所述数据输入端，自所述数据输入端接收所述数据信号Data。所述第一晶体管71的第二端电性连接至所述第二晶体管73的控制 端。
所述第一晶体管71根据接收的所述扫描信号Scan的电位选择性电性导通或电性断开。
具体地，当所述第一晶体管71接收的所述扫描信号Scan处于第一电位时，所述第一晶体管71的第一端和所述第一晶体管71的第二端电性断开；当所述第一晶体管71接收的所述扫描信号Scan处于第二电位时，所述第一晶体管71的第一端和所述第一晶体管71的第二端电性导通。此时，所述数据信号Data自所述第一晶体管71的第二端传输至所述第二晶体管73的控制端。
在本申请具体实施例中，所述第二晶体管73的第一端用于接收所述电源信号VDD，所述第二晶体管73的第二端电性连接于所述输出端。所述第二晶体管73根据所述控制端接收的所述数据信号Data，选择性处于导通状态或截止状态。即所述第二晶体管73根据接收的所述数据信号Data的电位选择性电性导通或断开，进而选择性将所述电源信号VDD传输至所述输出端。
具体地，当所述第二晶体管73接收的所述数据信号Data处于第一电位时，所述第二晶体管73的第一端和第二晶体管73的第二端电性断开；当所述第二晶体管73接收的所述数据信号Data处于第二电位时，所述第二晶体管73的第一端和所述第二晶体管73的第二端电性导通。此时，所述电源信号VDD传输至所述输出端。进一步地，所述电源信号VDD通过所述输出端传输至所述发光单元60。
在本申请实施例中，所述第一电位可以为高电位，所述第二电位可以为低电位，本申请对此不做具体限制。
在本申请实施例中，所述第一晶体管71和所述第二晶体管73可为P型金属氧化物半导体(P-Metal-Oxide-Semiconductor，PMOS)晶体管，本申请对此不做具体限制。其中，所述第一端可为漏极，所述第二端可为源极，所述控制端可为栅极。
请继续参阅图5，所述发光单元60可以包括所述第一发光元件A和所述第二发光元件B。其中，所述第一发光元件A和所述第二发光元件B的第一端均电性连接至所述输出端，所述第一发光元件A和所述第二发光元件B的第二端均电性连接至所述控制单元50。其中，所述第一发光元件A和所述第二发光元件B的第一端可以为阳极，第二端可以为阴极。
在本申请实施例中，所述控制单元50接收第一信号ab和第二信号sw，并根据接收的第一信号ab和第二信号sw的电位控制所述第一发光元件A和/或所述第二发光元件B的第二端电性连接至所述第一电源ELVSS，进而控制所述第一发光元件A和/或所述第二发光元件B选择性发光。
在本申请具体实施例中，当所述控制单元50接收的所述第一信号ab处于第一电位，且所述第二信号sw处于第一电位时，所述第一发光元件A的第二端电性连接至所述第一电源ELVSS，并自所述第一电源ELVSS接收第一阴极电压。此时，所述第一发光元件A用于发光。
当所述控制单元50接收的所述第一信号ab处于第二电位，且所述第二信号sw处于第一电位时，所述第二发光元件B的第二端电性连接至所述第一电源ELVSS，并自所述第一电源ELVSS接收第一阴极电压。此时，所述第二发光元件B用于发光。
当所述控制单元50接收的所述第二信号sw处于第二电位时，无论所述第一信号ab处于第一电位或第二电位，此时所述第一发光元件A和所述第二发光元件B的第二端均电性连接至所述第一电源ELVSS，并同时自所述第一电源ELVSS接收第一阴极电压，此时，所述第一发光元件A和所述第二发光元件B均用于发光。
在本申请实施例中，所述控制单元50还可以控制所述第一发光元件A或所述第二发光元件B的第二端电性连接至所述第二电源ELVDD，并自所述第二电源ELVDD接收第二阴极电压。
当所述第一发光元件A和/或所述第二发光元件B的第一端接收到所述电源信号VDD，同时第二端接收到所述第二阴极电压，那么所述第一发光元件A和/或所述第二发光元件B的外部形成的电场与内部累计的电荷形成的电场同向，所述第一发光元件A和/或所述第二发光元件B内部积累的电荷即被消耗掉，从而提高了所述发光单元60的显示寿命，降低了烧屏的风险。
具体地，在本申请实施例中，当所述控制单元50接收的所述第一信号ab处于第一电位，且所述第二信号sw处于第一电位时，所述第二发光元件B的第二端电性连接至所述第二电源ELVDD，并自所述第二电源ELVDD接收第二阴极电压。此时，所述第二发光元件B的外部形成的电场与内部累计的电荷形成的电场同向，所述第二发光元件B内部积累的电荷即被消耗掉，从而提高了所述第二发光元件B的显示寿命，降低了烧屏的风险。
当所述控制单元50接收的所述第一信号ab处于第二电位，且所述第二信号sw处于第一电位时，所述第一发光元件A的第二端电性连接至所述第二电源ELVDD，并自所述第二电源ELVDD接收第二阴极电压。此时，所述第一发光元件A的外部形成的电场与内部累计的电荷形成的电场同向，所述第一发光元件A内部积累的电荷即被消耗掉，从而提高了所述第一发光元件A的显示寿命，降低了烧屏的风险。
当所述控制单元50接收的所述第二信号sw处于第二电位时，无论所述第一信号ab处于第一电位或第二电位，此时所述第一发光元件A和第二发光元件B的第二端均电性连接至所 述第一电源ELVSS，并自所述第一电源ELVSS接收第一阴极电压。此时，所述第一发光元件A和第二发光元件B均发光，以补充发光元件的发光亮度，避免由于发光亮度不足导致的残影或烧屏问题，进而提高所述像素电路40的寿命，提高所述显示面板10的显示效果。
在本申请具体实施例中，可以理解的是，为使发光元件外部形成的电场与内建电场同向，所述第二电源ELVDD的第二阴极电压的电势高于所述电源信号VDD的电势。同时，所述第一电源ELVSS的第一阴极电压的电势应当低于所述电源信号VDD的电势，以保证所述发光元件正常发光。同时，可以理解的是，所述电源信号VDD用于驱动所述发光元件发光，其电压值应当与所述发光元件的发光亮度相匹配，本申请对此不做具体限制。
在本申请实施例中，所述第一信号ab自第一电位切换至第二电位或自第二电位切换至第一电位有预设切换时间，该预设切换时间可以根据具体情况确定，所述预设切换时间可以为1帧，10帧，100帧或其他数值，本申请不做具体限制。
在本申请实施例中，所述第二信号sw自第一电位切换至第二电位或自第二电位切换至第一电位的切换时间也可以根据实际情况确定，本申请不做具体限制。
接下来，将对所述像素电路40的不同发光路径进行阐述。
第一发光元件A发光：所述驱动单元70接收处于第二电位的扫描信号Scan和处于第二电位的数据信号Data，进而使得所述第一晶体管71和所述第二晶体管73处于导通状态，所述电源信号VDD自所述输出端输出至所述发光单元60，所述第一发光元件A和所述第二发光元件B的第一端均接收所述电源信号。所述控制单元50接收处于第一电位的所述第一信号ab和处于第一电位的第二信号sw，进而所述第一发光元件A的第二端电性连接至所述第一电源ELVSS以接收所述第一阴极电压，所述第二发光元件B的第二端电性连接至所述第二电源ELVDD以接收所述第二阴极电压。此时，所述第一发光元件A发光，第二发光元件B释放内部积累的电荷。
第二发光元件B发光：所述驱动单元70接收处于第二电位的扫描信号Scan和处于第二电位的数据信号Data，进而使得所述第一晶体管71和所述第二晶体管73处于导通状态，所述电源信号自所述输出端输出至所述发光单元60，所述第一发光元件A和所述第二发光元件B的第一端均接收所述电源信号。所述控制单元50接收处于第二电位的所述第一信号ab和处于第一电位的第二信号sw，进而所述第二发光元件B的第二端电性连接至所述第一电源ELVSS以接收所述第一阴极电压，所述第一发光元件A的第二端电性连接至所述第二电源ELVDD以接收所述第二阴极电压。此时，所述第二发光元件B发光，第一发光元件A释放内部积累的电荷。
第一发光元件A和第二发光元件B均发光：所述驱动单元70接收处于第二电位的扫描信号Scan和处于第二电位的数据信号Data，进而使得所述第一晶体管71和所述第二晶体管73处于导通状态，所述电源信号自所述输出端输出至所述发光单元60，所述第一发光元件A和所述第二发光元件B的第一端均接收所述电源信号。所述控制单元50接收处于第二电位的所述第二信号sw，进而所述第一发光元件A和所述第二发光元件B的第二端均电性连接至所述第一电源ELVSS以接收所述第一阴极电压。此时，所述第一发光元件A和所述第二发光元件B均发光。
请一并参阅图6，图6为图5所示的像素电路40中控制单元50的电路结构示意图。如图6所示，在本申请实施例中，所述控制单元50包括导通选择单元51、导通控制单元53和开关单元55。所述导通控制单元53与所述导通选择单元51和所述开关单元55均电性连接，所述开关单元还电性连接至所述第一发光元件和所述第二发光元件。所述导通选择单元51用于接收所述控制电源信号VDD1和所述第一信号ab，并根据所述第一信号ab选择性控制所述导通控制单元53处于第一导通状态或第二导通状态。所述开关单元55接收所述第二信号sw，所述开关单元55根据所述导通选择单元51的导通状态和所述第二信号sw的电位控制所述第一发光元件和/或第二发光元件的第二端导通至所述第一电源。具体地，所述开关单元55控制所述第一发光元件A的第二端导通至所述第一电源ELVSS，所述第二发光元件B的第二端导通至所述第二电源ELVDD，或，
驱动所述第二发光元件B的第二端导通至所述第一电源ELVSS，所述第一发光元件A的第二端导通至所述第二电源ELVDD，或，
所述第一发光元件A和所述第二发光元件B的第二端均导通至所述第一电源ELVSS。
如图6所示，在本申请实施例中，所述导通选择单元51包括第一选择晶体管511、第二选择晶体管513、第三选择晶体管515和第四选择晶体管517。其中，所述第一选择晶体管511的控制端用于接收所述第一信号ab，所述第二选择晶体管513的控制端用于接收所述第一信号ab的反相信号BA。所述第一选择晶体管511的第一端和所述第二选择晶体管513的第一端接收控制电源信号VDD1，所述第一选择晶体管511的第二端同时电性连接至所述第三选择晶体管515的第一端和所述导通控制单元53。所述第二选择晶体管513的第二端电性连接至所述第四选择晶体管517的第一端和所述导通控制单元53。其中，第一信号ab的反相信号BA为非a非b。
所述第三选择晶体管515的控制端电性连接至所述第二选择晶体管513的第二端。所述第四选择晶体管517的控制端电性连接至所述第一选择晶体管511的第二端。所述第三选择 晶体管515的第二端和所述第四选择晶体管517的第二端均电性连接至所述第一电源ELVSS。
在本申请实施例中，所述第一选择晶体管511的控制端用于接收所述第一信号ab，所述第一信号ab控制所述第一选择晶体管511的第一端和第二端电性导通或电性断开。
在本申请实施例中，所述第四选择晶体管517的控制端用于自所述第一选择晶体管511的第二端接收所述控制电源信号VDD1，所述控制电源信号VDD1控制所述第一选择晶体管511处于导通或截止状态。同时，所述控制电源信号VDD1选择性自所述第一选择晶体管511的第二端选择性传输至所述导通控制单元53。
当所述第一信号ab处于第一电位时，所述第一选择晶体管511的第一端和第二端电性断开，所述控制电源信号VDD1无法从第一端传输至第二端。此时，所述第四选择晶体管517的控制端未接收到所述控制电源信号VDD1，处于截至状态。所述控制电源信号VDD1无法自所述第一选择晶体管511的第二端传输至所述导通控制单元53。
当所述第一信号ab处于第二电位时，所述第一选择晶体管511的第一端和第二端电性导通，所述控制电源信号VDD1从第一端传输至第二端。此时，所述第四选择晶体管517的控制端接收到所述控制电源信号VDD1，处于导通状态。所述控制电源信号VDD1自所述第一选择晶体管511的第二端传输至所述导通控制单元53。
在本申请实施例中，所述第二选择晶体管513的控制端用于接收所述第一信号ab的反相信号BA，所述反相信号BA控制所述第二选择晶体管513的第一端和第二端电性导通或电性断开。
在本申请实施例中，所述第三选择晶体管515的控制端用于自所述第二选择晶体管513的第二端接收所述控制电源信号VDD1，所述控制电源信号VDD1控制所述第三选择晶体管515处于导通或截止状态。同时，所述控制电源信号VDD1自所述第二选择晶体管513的第二端选择性传输至所述导通控制单元53。
当所述反相信号BA处于第一电位时，所述第二选择晶体管513的第一端和第二端电性断开，所述控制电源信号VDD1无法从所述第二选择晶体管513的第一端传输至第二端。此时，所述第三选择晶体管515的控制端未接收到所述控制电源信号VDD1，处于截至状态。所述控制电源信号VDD1无法自所述第二选择晶体管513的第二端传输至所述导通控制单元53。
当所述反相信号BA处于第二电位时，所述第二选择晶体管513的第一端和第二端电性导通，所述控制电源信号VDD1从所述第二选择晶体管513的第一端传输至第二端。此时，所述第三选择晶体管515的控制端接收到所述控制电源信号VDD1，处于导通状态。所述控 制电源信号VDD1自所述第二选择晶体管513的第二端传输至所述导通控制单元53。
在本申请的实施例中，所述导通控制单元53包括第一导通晶体管531和第二导通晶体管533。所述第一导通晶体管531的控制端电性连接至所述第二选择晶体管513的第二端，所述第二导通晶体管533的控制端电性连接至所述第一选择晶体管511的第二端。所述第一导通晶体管531和所述第二导通晶体管533的第一端均电性连接至所述第一电源ELVSS。所述第一导通晶体管531和所述第二导通晶体管533的第二端均电性连接至所述开关单元55。
在本申请实施例中，所述第一导通晶体管531的控制端用于自所述第二选择晶体管513的第二端接收所述控制电源信号VDD1，所述控制电源信号VDD1控制所述第一导通晶体管531处于导通或截止状态。
所述第二导通晶体管533的控制端用于自第一选择晶体管511的第二端接收所述控制电源信号VDD1，所述控制电源信号VDD1控制所述第二导通晶体管533处于导通或截止状态。
其中，由于所述控制电源信号VDD1始终处于第一电位，故所述第一导通晶体管531或所述第二导通晶体管533接收到控制电源信号VDD1时，所述第一导通晶体管531或所述第二导通晶体管533处于导通状态。此时，所述第一导通晶体管531或所述第二导通晶体管533的第二端均导通至所述第一电源ELVSS。
具体地，当所述第一导通晶体管531的控制端自所述第二选择晶体管513的第二端接收所述控制电源信号VDD1时，所述第一导通晶体管531处于导通状态，所述第二导通晶体管533处于截止状态。此时，所述导通控制单元53处于第一导通状态。
当所述第二导通晶体管533的控制端自所述第一选择晶体管511的第二端接收所述控制电源信号VDD1时，所述第一导通晶体管531处于截止状态，所述第二导通晶体管533处于导通状态。此时，所述导通控制单元53处于第二导通状态。
在本申请实施例中，所述开关单元55包括第一释放晶体管551、第二释放晶体管552、第三释放晶体管554和第四释放晶体管556。所述第一释放晶体管551的控制端电性连接于所述第一导通晶体管531的第二端，所述第二释放晶体管552的控制端电性连接于所述第二导通晶体管533的第二端。所述第一释放晶体管551和所述第二释放晶体管552的第一端均电性连接于所述第二电源ELVDD。所述第一释放晶体管551的第二端电性连接至所述第二导通晶体管533的第二端，所述第二释放晶体管552的第二端电性连接至所述第一导通晶体管531的第二端。
所述第三释放晶体管554的控制端用于接收所述第二信号sw，所述第三释放晶体管554的第一端同时电性连接至所述第二导通晶体管533的第二端和所述第一释放晶体管551的第 二端。所述第三释放晶体管554的第二端电性连接至所述第二发光元件B的第二端。
所述第四释放晶体管556的控制端接收所述第二信号sw，所述第四释放晶体管556的第一端同时电性连接至所述第一导通晶体管531的第二端和所述第二释放晶体管552的第二端。所述第四释放晶体管556的第二端电性连接至所述第一发光元件A的第二端。
在本申请实施例中，所述第一释放晶体管551的控制端用于自所述第一导通晶体管531的第二端接收所述第一电源ELVSS的第一阴极电压，所述第一电源ELVSS的第一阴极电压控制所述第一释放晶体管551的第一端和第二端电性导通。
所述第二释放晶体管552的控制端用于自所述第二导通晶体管533的第二端接收所述第一电源ELVSS的第一阴极电压，所述第一电源ELVSS的第一阴极电压控制所述第二释放晶体管552的第一端和第二端电性导通。
在本实施例中，由于所述第一阴极电压始终处于第二电位，故当所述第一释放晶体管551或所述第二释放晶体管552的控制端接收到所述第一阴极电压时，所述第一释放晶体管551或所述第二释放晶体管552处于导通状态。此时，所述第二电源ELVDD的第二阴极电压自所述第一释放晶体管551或所述第二释放晶体管552的第一端传输至第二端。
在本申请实施例中，所述第三释放晶体管554的控制端接收第二信号sw，所述第二信号sw控制所述第三释放晶体管554处于导通或截止状态。
具体为，当所述第二信号sw处于第一电位时，所述第三释放晶体管554处于导通状态。当所述第二信号sw处于第二电位时，所述第三释放晶体管554处于截止状态。
在本申请实施例中，所述第四释放晶体管556的控制端接收第二信号sw，所述第二信号sw控制所述第四释放晶体管556处于导通或截止状态。
具体为，当所述第二信号sw处于第一电位时，所述第四释放晶体管556处于导通状态。当所述第二信号sw处于第二电位时，所述第四释放晶体管556处于截止状态。相应地，所述第三释放晶体管554处于导通状态，所述导通控制单元53处于第一导通状态时，所述第一发光元件A用于发光。所述第四释放晶体管556处于导通状态，所述导通控制单元53处于第二导通状态时，所述第二发光元件B用于发光。
在本申请实施例中，所述开关单元55还包括第一开关晶体管555和第二开关晶体管553。所述第一开关晶体管555和所述第二开关晶体管553的控制端用于接收所述第二信号sw，所述第一开关晶体管555和所述第二开关晶体管553的第一端均电性连接至所述第一电源ELVSS。所述第一开关晶体管555的第二端电性连接至所述第一发光元件A的第二端，所述第二开关晶体管553的第二端电性连接至所述第二发光元件B的第二端。
在本申请实施例中，所述第二信号sw控制所述第一开关晶体管555和所述第二开关晶体管553处于导通或截止状态。
当所述第二信号sw处于第二电位时，所述第一开关晶体管555和所述第二开关晶体管553均处于导通状态，所述第一开关晶体管555和所述第二开关晶体管553的第二端均电性导通至所述第一电源ELVSS，则所述第一发光元件A和所述第二发光元件B的第二端均电性导通至所述第一电源ELVSS。此时，所述第一发光元件A和所述第二发光元件B同时发光，以补充发光元件的发光亮度，避免由于发光亮度不足导致的残影或烧屏问题，进而提高所述像素电路40的寿命，提高所述显示面板10的显示效果。
当所述第二信号sw处于第一电位时，所述第一开关晶体管555和所述第二开关晶体管553均处于截止状态。所述第一发光元件A和所述第二发光元件B的第二端的信号输入由第一释放晶体管551、第二释放晶体管552、第三释放晶体管554和第四释放晶体管556控制。
在本申请具体实施例中，当所述导通控制单元53处于第一导通状态，且所述第二信号sw处于第一电位时，所述第一释放晶体管551、所述第三释放晶体管554、所述第四释放晶体管556处于导通状态，所述第二释放晶体管552处于截止状态，所述第一电源ELVSS的第一阴极电压传输至所述第一发光元件A的第二端，所述第一发光元件A用于发光，所述第二电源ELVDD的第二阴极电压传输至所述第二发光元件B的第二端；
当所述导通控制单元53处于第二导通状态，且所述第二信号sw处于第一电位时，所述第二释放晶体管552、所述第三释放晶体管554、所述第四释放晶体管556处于导通状态，所述第一释放晶体管551处于截止状态，所述第一电源ELVSS的第一阴极电压传输至所述第二发光元件B的第二端，所述第二发光元件B用于发光，所述第二电源ELVDD的第二阴极电压传输至所述第一发光元件A的第二端。
当所述第二信号sw处于第一电位时，无论所述导通控制单元53处于何种导通状态，所述第一开关晶体管555和所述第二开关晶体管553均处于导通状态，所述第一电源ELVSS的第一阴极电压分别传输至所述第一发光元件A和所述第二发光元件B的第二端。
在本申请实施例中，第一选择晶体管511、第二选择晶体管513、第三选择晶体管515、第四选择晶体管517、第一导通晶体管531、所述第二导通晶体管533、第一释放晶体管551、第二释放晶体管552、第一开关晶体管555、第三释放晶体管554、所述第二开关晶体管553和第四释放晶体管556可为金属-氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)，本申请对此不作具体限制。其中，第三选择晶体管515、第四选择晶体管517、第一导通晶体管531、所述第二导通晶体管533、第三释放晶体管554 和第四释放晶体管556可以为N沟道MOS场效应管。第一选择晶体管511、第二选择晶体管513、第一释放晶体管551、第二释放晶体管552、第一开关晶体管555和所述第二开关晶体管553可以为P沟道MOS场效应管。本申请对此不做具体限制。
在本申请实施例中，第一选择晶体管511、第二选择晶体管513、第三选择晶体管515、第四选择晶体管517、第一释放晶体管551、第二释放晶体管552、第三释放晶体管554和第四释放晶体管556的第一端可为漏极，第二端可为源极，所述控制端可为栅极。
在本申请实施例中，第一导通晶体管531、所述第二导通晶体管533、第一开关晶体管555和所述第二开关晶体管553的第一端可为源极，第二端可为漏极，所述控制端可为栅极。
接下来，就所述控制单元50控制第一发光元件A和/或所述第二发光元件B的发光过程进行阐述。
第一发光元件A用于发光：当所述第一信号ab为处于第一电位，所述第二信号sw处于第一电位时，所述第一选择晶体管511处于截止状态，所述第二选择晶体管513处于导通状态。故，所述第四选择晶体管517处于截至状态。所述控制电源信号VDD1自所述第二选择晶体管513的第一端传输至第二端。
所述第三选择晶体管515和所述第一导通晶体管531的控制端自所述第二选择晶体管513的第二端接收所述控制电源信号VDD1均处于导通状态。故所述第一电源ELVSS的第一阴极电压传输至所述第一导通晶体管531的第二端。
由于所述第四释放晶体管556的控制端接收处于第一电位的所述第二信号sw，处于导通状态，故所述第一阴极电压自所述第一导通晶体管531的第二端传输至所述第四释放晶体管556的第二端，进而传输至所述第一发光元件A的第二端。进一步地，所述第一发光元件A用于发光。
此外，所述第一释放晶体管551的控制端自所述第一导通晶体管531的第二端接收所述第一阴极电压，处于导通状态，则所述第二电源ELVDD的第二阴极电压自所述第一释放晶体管551的第一端传输至第二端。由于所述第三释放晶体管554的控制端接收处于第一电位的所述第二信号sw，处于导通状态，故进一步地，所述第二阴极电压经由所述第三释放晶体管554传输至所述第二发光元件B的第二端。此时，所述第二发光元件B不发光，且释放内部积累的电荷，避免显示残影，增强显示寿命。
第二发光元件B用于发光：当所述第一信号ab为处于第二电位，所述第二信号sw处于第一电位时，所述第一选择晶体管511处于导通状态，所述第二选择晶体管513处于截止状态。故，所述第三选择晶体管515处于截至状态。所述控制电源信号VDD1自所述第一选择 晶体管511的第一端传输至第二端。
所述第四选择晶体管517和所述第二导通晶体管533的控制端自所述第一选择晶体管511的第二端接收所述控制电源信号VDD1进而均处于导通状态。故所述第一电源ELVSS的第一阴极电压传输至所述第二导通晶体管533的第二端。
由于所述第三释放晶体管554的控制端接收处于第一电位的所述第二信号sw，处于导通状态，故所述第一阴极电压自所述第二导通晶体管533的第二端传输至所述第三释放晶体管554的第二端，进而传输至所述第二发光元件B的第二端。此时，所述第二发光元件B用于发光。
此外，所述第二释放晶体管552的控制端自所述第二导通晶体管533的第二端接收所述第一阴极电压，处于导通状态，则所述第二电源ELVDD的第二阴极电压自所述第二释放晶体管552的第一端传输至第二端。由于所述第四释放晶体管556的控制端接收处于第一电位的所述第二信号sw，处于导通状态，故进一步地，所述第二阴极电压经由所述第四释放晶体管556传输至所述第一发光元件A的第二端。此时，所述第一发光元件A不发光，且释放内部积累的电荷，避免显示残影，增强显示寿命。
所述第一发光元件A和所述第二发光元件B同时用于发光：当所述第二信号sw处于第二电位时，所述第一开关晶体管555和所述第二开关晶体管553均处于导通状态，所述第一开关晶体管555和所述第二开关晶体管553的第二端均电性导通至所述第一电源ELVSS，则所述第一发光元件A和所述第二发光元件B的第二端均电性导通至所述第一电源ELVSS。此时，所述第一发光元件A和所述第二发光元件B同时发光，用于补充发光元件的发光亮度，避免由于发光亮度不足导致的残影或烧屏问题，进而提高所述像素电路40的寿命，提高所述显示面板10的显示效果。
请一并参阅图7，图7为图5所示的像素电路40的工作时序图。如图7所示，Scan n和Scan n+1对应曲线分别对应数据线中的任意相邻两条的时序，Data对应的曲线为数据信号Data对应的时序，ab对应的曲线为所述第一信号ab对应的时序，sw对应曲线为所述第二信号sw对应的时序。其中，所述第一信号ab的电位切换具有预设切换时间，即每经过预设切换时间，所述第一信号ab的电位切换一次。
在本申请具体实施例中，所述预设切换时间可以为200帧，可以理解的是，所述预设切换时间可以根据显示装置100的具体情况确定，本申请不做具体限制。
在本申请实施例中，所述像素电路40设置控制单元50，所述发光单元60设置第一发光元件A和第二发光元件B，通过所述控制单元50选择性控制所述第一发光元件A和/或所述 第二发光元件B选择性发光，以提升所述像素电路40的显示寿命。
另一方面，所述控制单元50选择性控制所述第一发光元件A或所述第二发光元件B电性连接于至所述第二电源ELVDD以接收所述第二阴极电压，进而在其不发光时释放其内积累的电荷，进一步提升所述发光单元60的显示寿命。降低烧屏的风险，提升显示品味。
基于同一构思，本申请还提供了一种显示面板10，所述显示面板10包括若干上述的像素电路40。
请一并参阅图8，图8为本申请实施例公开的另一种显示面板1的示意图。在本申请实施例中，所述显示面板1相较于显示面板10的区别在于，所述显示面板1还包括总控制单元18，所述总控制单元18电性连接于若干个所述像素电路40，所述总控制单元18用于同时控制多个像素电路40切换至所述第一发光元件A和/或所述第二发光元件B发光。
如图8所示，图中所示为所述显示面板1中的一个显示区块，该显示区块包括9个像素电路40。可以理解的是，对所述显示面板1中的像素电路40分区块控制，每个显示区块包含的像素电路的数量可以根据实际情况确定，本申请对此不做具体限制。
在本申请具体实施例中，所述总控制单元18与所述像素电路40之间可以通过集成电路总线(Inter-Integrated Circuit，IIC)、串行外设接口(Serial Peripheral Interface，SPI)等实现通讯，如何选择协议可以根据通过实际情况而定，本申请对此不做具体限制。
需要说明的是，在本申请实施例中，所述显示面板10中包含多个像素电路40，每个像素电路40中均包含一个控制单元50，每个控制单元50对应一个地址，当总控制单元18向多个所述控制单元50发送控制信号。所述控制信号包含起始段，若干地址段和若干指令段，起始段包含0.5毫秒(ms)的处于第一电位的起始信号。每个地址段为4微秒(us)的包含区块地址的数据信号。每个指令段为2微秒(us)的包含指令信息的数据信号。
换言之，所述控制信号包含起始部分和若干数据部分，起始部分不包含数据信息，每个数据部分包含6个字节(bit)的数据，其中前4个字节(bit)为对应的显示区块的地址，后2个字节(bit)为对应的信号指令。信号指令即对应第二信号sw和第一信号ab。
在实施例中，所述总控制单元18控制的显示区块接收到控制信号，所述控制信号的地址段识别对应的控制单元后继续输出所述控制信号的指令段，以控制所述像素电路40切换用于发光的发光元件。可以理解的是，与所述控制信号的地址段不对应的像素电路40继续由原先用于发光的发光元件发光。
在本申请实施例中，1bit的时间为1us，本申请对此不做具体限制，控制信号包含信号的长短可以根据实际情况确定。
请一并参阅图9和图10，图9为图8所示的显示面板1中的总控制单元18发出控制信号的时序图。图10为图8所示的显示面板1中各控制单元对应的地址。
如图9所示，所述总控制单元18发送的控制信号的时序图，所述控制信号的起始段为“111111”，第一个地址段为0001。第一个指令段为11，其中，第一个指令段的第一个1对应第一信号ab处于第一电位，第二个1为第二信号sw处于第一电位。第二个地址段为0010。第二个指令段也为11，其中，第二个指令段的第一个1对应第一信号ab处于第一电位，第二个1为第二信号sw处于第一电位。第三个地址段为0011，第三个指令段为01，其中，第三个指令段的0对应第一信号ab处于第二电位，1对应第二信号sw处于第一电位。
不同控制单元50根据接收到的控制信号地址段，相应的接收或不接收指令段。具体为，总控制单元18将与地址段对应的指令信号发送至与地址段对应的控制单元50，进而控制所述像素电路40切换用于发光的发光元件。
如图10所示，将图8中所示的9个像素电路40的控制单元50依次记为控制单元1、控制单元2至控制单元9，则9个控制单元50对应的地址如图所示。
接下来，以每个区块包含9个像素电路为例，对本实施例进行阐述。
在本申请实施例中，所述总控制单元18电性连接于9个所述像素电路40的控制单元50。此时，当所述显示区块内的两个或两个以上的所述像素电路40出现显示异常，所述总控制单元18可以控制两个或两个以上的所述像素电路40切换发光单元60的发光元件发光。其中，可以理解的是，显示异常是指出现烧屏、残影等现象。
为了清楚的阐述总控制单元同时控制两个所述像素电路40切换发光元件，将所述显示区块的其中两个像素电路记为第一像素电路和第二像素电路。
例如，在本申请具体实施中，当所述第一像素电路的第一发光元件A显示异常，所述第二像素电路的第二发光元件B显示异常，此时，通过所述总控制单元18同时控制第一像素电路和第二像素电路切换至另一个发光元件进行画面显示。即所述第一像素电路切换为第二发光元件B进行显示，所述第二像素电路切换为第一发光元件A进行显示。可以理解的是，所述总控制单元18也可以同时控制三个、四个或其他数量个的像素电路40进行发光元件切换，本申请对此不做具体限制。
基于同一构思，本申请还提供了一种显示装置100，所述显示装置100包括上述的显示面板。
在本申请的像素电路40、显示面板和显示装置100中，所述像素电路40中设置控制单元50，所述发光单元60设置第一发光元件A和第二发光元件B，所述控制单元50选择性控 制所述第一发光元件A和/或所述第二发光元件B选择性发光，以提升所述像素电路40的显示寿命。同时，所述控制单元50选择性控制所述第一发光元件A或所述第二发光元件B电性连接于至所述第二电源ELVDD以接收所述第二阴极电压，进而在其不发光时释放其内积累的电荷，进一步提升所述发光单元60的显示寿命。降低烧屏的风险，提升显示品味。
此外，在所述显示面板中设置总控制单元18，对所述显示面板中的若干像素电路40进行区块化控制，在每一个显示区块设置总控制单元18，利用总控制单元18对出现显示异常现象的像素电路40一同切换用于显示的发光元件，进一步提高控制显示效果的效率。
对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”或“一些示例”等的描述意指结合所述实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
应当理解的是，以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种像素电路，包括发光单元和驱动单元，其中，所述像素电路还包括控制单元，其中，所述发光单元包括第一发光元件和第二发光元件，所述第一发光元件和所述第二发光元件与所述驱动单元和所述控制单元同时电性连接；所述驱动单元用于向所述发光单元传输用于驱动所述第一发光元件和/或所述第二发光元件发光的数据信号；所述控制单元用于控制所述第一发光元件和/或所述第二发光元件电性连接至第一电源；
    所述发光单元在接收到所述数据信号时，所述控制单元选择性控制所述第一发光元件和/或所述第二发光元件发光。
  2. 如权利要求1所述的像素电路，其中，所述驱动单元包括第一晶体管、第二晶体管和存储电容，所述存储电容的一端电性连接至所述第一晶体管的第二端，所述存储电容的另一端电性连接至所述第二晶体管的第一端；所述第一晶体管的控制端接收扫描信号，所述第一晶体管的第一端接收所述数据信号，所述第一晶体管的第二端电性连接至所述第二晶体管的控制端；
    所述第二晶体管的第一端用于接收电源信号，所述第二晶体管的第二端电性连接于所述发光单元；
    所述第一晶体管根据接收的所述扫描信号的电位选择性将所述数据信号传输至所述第二晶体管，所述第二晶体管根据接收到的所述数据信号选择性传输所述电源信号至所述发光单元。
  3. 如权利要求2所述的像素电路，其中，当所述第一晶体管接收的所述扫描信号处于第一电位时，所述第一晶体管的第一端和所述第一晶体管的第二端电性断开；当所述第一晶体管接收的所述扫描信号处于第二电位时，所述第一晶体管的第一端和所述第一晶体管的第二端电性导通，所述数据信号传输至所述第二晶体管；
    当所述第二晶体管接收的所述数据信号处于第一电位时，所述第二晶体管的第一端和第二晶体管的第二端电性断开；当所述第二晶体管接收的所述数据信号处于第二电位时，所述第二晶体管的第一端和所述第二晶体管的第二端电性导通，所述电源信号传输至所述发光单元。
  4. 如权利要求2所述的像素电路，其中，所述第一发光元件的第一端和所述第二发光元件的第一端均电性连接至所述第二晶体管的第二端，所述第一发光元件的第二端和所述第二发光元件的第二端均电性连接至所述控制单元；
    所述控制单元接收第一信号和第二信号，并根据所述第一信号和所述第二信号的电位控制所述第一发光元件和/或所述第二发光元件的第二端电性连接至所述第一电源。
  5. 如权利要求4所述的像素电路，其中，所述控制单元还用于控制所述第一发光元件的第二端或所述第二发光元件的第二端电性连接至第二电源，使所述第一发光元件或所述第二发光元件释放其内部积累的电荷。
  6. 如权利要求5所述的像素电路，其中，当所述控制单元接收的所述第一信号处于第一电位，且所述第二信号处于第一电位时，所述第一发光元件的第二端电性连接至所述第一电源，并自所述第一电源接收第一阴极电压，所述第一发光元件用于发光，所述第二发光元件的第二端电性连接至所述第二电源，并自所述第二电源接收第二阴极电压；
    当所述控制单元接收的所述第一信号处于第二电位，且所述第二信号处于第一电位时，所述第二发光元件的第二端电性连接至所述第一电源，并自所述第一电源接收所述第一阴极电压，所述第二发光元件用于发光，所述第一发光元件的第二端电性连接至所述第二电源，并自所述第二电源接收所述第二阴极电压；
    当所述控制单元接收的所述第二信号处于第二电位时，所述第一发光元件和所述第二发光元件的第二端均电性连接至所述第一电源，并同时自所述第一电源接收所述第一阴极电压，所述第一发光元件和所述第二发光元件均用于发光。
  7. 如权利要求5所述的像素电路，其中，所述控制单元包括导通选择单元、导通控制单元和开关单元，所述导通控制单元与所述导通选择单元和所述开关单元均电性连接，所述开关单元还电性连接至所述第一发光元件的第二端和所述第二发光元件的第二端；
    所述导通选择单元用于接收所述第一信号，并根据所述第一信号选择性控制所述导通控制单元处于第一导通状态或第二导通状态；
    所述开关单元接收所述第二信号，所述开关单元根据所述导通选择单元的导通状态和所述第二信号的电位控制所述第一发光元件和/或第二发光元件的第二端电性连接至所述第一电源。
  8. 如权利要求7所述的像素电路，其中，所述导通选择单元包括第一选择晶体管、第二选择晶体管、第三选择晶体管和第四选择晶体管，所述第一选择晶体管的控制端用于接收所述第一信号，所述第二选择晶体管的控制端用于接收反相信号，所述第一晶体管的第一端和所述第二选择晶体管的第一端接收控制电源信号，所述第一选择晶体管的第二端同时电性连接至所述第三选择晶体管的第一端和所述导通控制单元，所述第二选择晶体管的第二端电性连接至所述第四选择晶体管的第一端和所述导通控制单元；
    所述第三选择晶体管的控制端电性连接至所述第二选择晶体管的第二端，所述第四选择晶体管的控制端电性连接至所述第一选择晶体管的第二端，所述第三选择晶体管的第二端和所述第四选择晶体管的第二端均电性连接至所述第一电源。
  9. 如权利要求8所述的像素电路，其中，当所述第一信号处于第一电位时，所述反相信号处于第二电位，所述第一选择晶体管和所述第四选择晶体管均处于截至状态，所述第二选择晶体管和所述第三选择晶体管处于导通状态，所述控制电源信号自所述第二选择晶体管的第二端传输至所述导通控制单元；
    当所述第一信号处于第二电位时，所述反相信号处于第一电位，所述第二选择晶体管和所述第三选择晶体管处于截止状态，所述第一选择晶体管和所述第四选择晶体管均处于导通状态，所述控制电源信号自所述第一选择晶体管的第二端传输至所述导通控制单元。
  10. 如权利要求8所述的像素电路，其中，所述导通控制单元包括第一导通晶体管和第二导通晶体管，所述第一导通晶体管的控制端电性连接至所述第二选择晶体管的第二端，所述第二导通晶体管的控制端电性连接至所述第一选择晶体管的第二端，所述第一导通晶体管和所述第二导通晶体管的第一端均电性连接至所述第一电源，所述第一导通晶体管和所述第二导通晶体管的第二端均电性连接至所述开关单元；
    当所述第一导通晶体管自所述第二选择晶体管接收所述控制电源信号时，所述第一导通晶体管导通，所述第二导通晶体管截止，所述导通控制单元处于第一导通状态；当所述第二导通晶体管自所述第一选择晶体管接收所述控制电源信号时，所述第一导通晶体管截止，所述第二导通晶体管导通，所述导通控制单元处于第二导通状态。
  11. 如权利要求10所述的像素电路，其中，所述开关单元包括第一释放晶体管、第二释放晶体管、第三释放晶体管和第四释放晶体管，所述第一释放晶体管的控制端电性连接于所述第一导通晶体管的第二端，所述第二释放晶体管的控制端电性连接于所述第二导通晶体管的第二端，所述第一释放晶体管和所述第二释放晶体管的第一端均电性连接于所述第二电源，所述第一释放晶体管的第二端电性连接至所述第二导通晶体管的第二端，所述第二释放晶体管的第二端电性连接至所述第一导通晶体管的第二端；
    所述第三释放晶体管的控制端用于接收所述第二信号，所述第三释放晶体管的第一端电性连接至所述第二导通晶体管的第二端和所述第一释放晶体管的第二端，所述第三释放晶体管的第二端电性连接至所述第二发光元件的第二端；
    所述第四释放晶体管的控制端接收所述第二信号，所述第四释放晶体管的第一端同时电性连接至所述第一导通晶体管的第二端和所述第二释放晶体管的第二端，所述第四释放晶体管的第二端电性连接至所述第一发光元件的第二端。
  12. 如权利要求11所述的像素电路，其中，当所述导通控制单元处于第一导通状态，且所述第二信号处于第一电位时，所述第一释放晶体管、所述第三释放晶体管、所述第四释放晶体管处于导通状态，所述第二释放晶体管处于截止状态，所述第一电源的第一阴极电压传 输至所述第一发光元件的第二端，所述第一发光元件用于发光，所述第二电源的第二阴极电压传输至所述第二发光元件的第二端；
    当所述导通控制单元处于第二导通状态，且所述第二信号处于第一电位时，所述第二释放晶体管、所述第三释放晶体管、所述第四释放晶体管处于导通状态，所述第一释放晶体管处于截止状态，所述第一电源的第一阴极电压传输至所述第二发光元件的第二端，所述第二发光元件用于发光，所述第二电源的第二阴极电压传输至所述第一发光元件的第二端。
  13. 如权利要求12所述的像素电路，其中，所述开关单元还包括第一开关晶体管和第二开关晶体管，所述第一开关晶体管的控制端和所述第二开关晶体管的控制端用于接收所述第二信号，所述第一开关晶体管的第一端和所述第二开关晶体管的第一端均电性连接至所述第一电源，所述第一开关晶体管的第二端电性连接至所述第一发光元件的第二端，所述第二开关晶体管的第二端电性连接至所述第二发光元件的第二端；
    当所述第二信号处于第二电位时，所述第一开关晶体管和所述第二开关晶体管均处于导通状态，所述第一电源的第一阴极电压分别传输至所述第一发光元件和所述第二发光元件的第二端。
  14. 一种显示面板，所述显示面板包括像素电路，所述像素电路包括发光单元、驱动单元和控制单元，其中，所述发光单元包括第一发光元件和第二发光元件，所述第一发光元件和所述第二发光元件与所述驱动单元和所述控制单元同时电性连接；所述驱动单元用于向所述发光单元传输用于驱动所述第一发光元件和/或所述第二发光元件发光的数据信号；所述控制单元用于控制所述第一发光元件和/或所述第二发光元件电性连接至第一电源；
    所述发光单元在接收到所述数据信号时，所述控制单元选择性控制所述第一发光元件和/或所述第二发光元件发光。
  15. 如权利要求14所述的显示面板，其中，所述驱动单元包括第一晶体管、第二晶体管和存储电容，所述存储电容的一端电性连接至所述第一晶体管的第二端，所述存储电容的另一端电性连接至所述第二晶体管的第一端；所述第一晶体管的控制端接收扫描信号，所述第一晶体管的第一端接收所述数据信号，所述第一晶体管的第二端电性连接至所述第二晶体管的控制端；所述第二晶体管的第一端用于接收电源信号，所述第二晶体管的第二端电性连接于所述发光单元；所述第一晶体管根据接收的所述扫描信号的电位选择性将所述数据信号传输至所述第二晶体管，所述第二晶体管根据接收到的所述数据信号选择性传输所述电源信号至所述发光单元；
    当所述第一晶体管接收的所述扫描信号处于第一电位时，所述第一晶体管的第一端和所述第一晶体管的第二端电性断开；当所述第一晶体管接收的所述扫描信号处于第二电位时， 所述第一晶体管的第一端和所述第一晶体管的第二端电性导通，所述数据信号传输至所述第二晶体管；
    当所述第二晶体管接收的所述数据信号处于第一电位时，所述第二晶体管的第一端和第二晶体管的第二端电性断开；当所述第二晶体管接收的所述数据信号处于第二电位时，所述第二晶体管的第一端和所述第二晶体管的第二端电性导通，所述电源信号传输至所述发光单元。
  16. 如权利要求15所述的显示面板，其中，所述第一发光元件的第一端和所述第二发光元件的第一端均电性连接至所述第二晶体管的第二端，所述第一发光元件的第二端和所述第二发光元件的第二端均电性连接至所述控制单元；所述控制单元接收第一信号和第二信号，并根据所述第一信号和所述第二信号的电位控制所述第一发光元件和/或所述第二发光元件的第二端电性连接至所述第一电源；所述控制单元还用于控制所述第一发光元件的第二端或所述第二发光元件的第二端电性连接至第二电源，使所述第一发光元件或所述第二发光元件释放其内部积累的电荷；
    当所述控制单元接收的所述第一信号处于第一电位，且所述第二信号处于第一电位时，所述第一发光元件的第二端电性连接至所述第一电源，并自所述第一电源接收第一阴极电压，所述第一发光元件用于发光，所述第二发光元件的第二端电性连接至所述第二电源，并自所述第二电源接收第二阴极电压；
    当所述控制单元接收的所述第一信号处于第二电位，且所述第二信号处于第一电位时，所述第二发光元件的第二端电性连接至所述第一电源，并自所述第一电源接收所述第一阴极电压，所述第二发光元件用于发光，所述第一发光元件的第二端电性连接至所述第二电源，并自所述第二电源接收所述第二阴极电压；
    当所述控制单元接收的所述第二信号处于第二电位时，所述第一发光元件和所述第二发光元件的第二端均电性连接至所述第一电源，并同时自所述第一电源接收所述第一阴极电压，所述第一发光元件和所述第二发光元件均用于发光。
  17. 如权利要求14所述的显示面板，其中，所述显示面板还包括总控制单元，所述总控制单元电性连接于若干个所述像素电路，所述总控制单元用于同时控制多个所述像素电路切换至所述第一发光元件和/或所述第二发光元件发光。
  18. 一种显示装置，所述显示装置包括显示面板，所述显示面板包括像素电路，所述像素电路包括发光单元、驱动单元和控制单元，其中，所述发光单元包括第一发光元件和第二发光元件，所述第一发光元件和所述第二发光元件与所述驱动单元和所述控制单元同时电性连接；所述驱动单元用于向所述发光单元传输用于驱动所述第一发光元件和/或所述第二发光 元件发光的数据信号；所述控制单元用于控制所述第一发光元件和/或所述第二发光元件电性连接至第一电源；
    所述发光单元在接收到所述数据信号时，所述控制单元选择性控制所述第一发光元件和/或所述第二发光元件发光。
  19. 如权利要求18所述的显示装置，其中，所述驱动单元包括第一晶体管、第二晶体管和存储电容，所述存储电容的一端电性连接至所述第一晶体管的第二端，所述存储电容的另一端电性连接至所述第二晶体管的第一端；所述第一晶体管的控制端接收扫描信号，所述第一晶体管的第一端接收所述数据信号，所述第一晶体管的第二端电性连接至所述第二晶体管的控制端；所述第二晶体管的第一端用于接收电源信号，所述第二晶体管的第二端电性连接于所述发光单元；所述第一晶体管根据接收的所述扫描信号的电位选择性将所述数据信号传输至所述第二晶体管，所述第二晶体管根据接收到的所述数据信号选择性传输所述电源信号至所述发光单元；
    当所述第一晶体管接收的所述扫描信号处于第一电位时，所述第一晶体管的第一端和所述第一晶体管的第二端电性断开；当所述第一晶体管接收的所述扫描信号处于第二电位时，所述第一晶体管的第一端和所述第一晶体管的第二端电性导通，所述数据信号传输至所述第二晶体管；
    当所述第二晶体管接收的所述数据信号处于第一电位时，所述第二晶体管的第一端和第二晶体管的第二端电性断开；当所述第二晶体管接收的所述数据信号处于第二电位时，所述第二晶体管的第一端和所述第二晶体管的第二端电性导通，所述电源信号传输至所述发光单元。
  20. 如权利要求19所述的显示装置，其中，所述第一发光元件的第一端和所述第二发光元件的第一端均电性连接至所述第二晶体管的第二端，所述第一发光元件的第二端和所述第二发光元件的第二端均电性连接至所述控制单元；所述控制单元接收第一信号和第二信号，并根据所述第一信号和所述第二信号的电位控制所述第一发光元件和/或所述第二发光元件的第二端电性连接至所述第一电源；所述控制单元还用于控制所述第一发光元件的第二端或所述第二发光元件的第二端电性连接至第二电源，使所述第一发光元件或所述第二发光元件释放其内部积累的电荷；
    当所述控制单元接收的所述第一信号处于第一电位，且所述第二信号处于第一电位时，所述第一发光元件的第二端电性连接至所述第一电源，并自所述第一电源接收第一阴极电压，所述第一发光元件用于发光，所述第二发光元件的第二端电性连接至所述第二电源，并自所述第二电源接收第二阴极电压；
    当所述控制单元接收的所述第一信号处于第二电位，且所述第二信号处于第一电位时，所述第二发光元件的第二端电性连接至所述第一电源，并自所述第一电源接收所述第一阴极电压，所述第二发光元件用于发光，所述第一发光元件的第二端电性连接至所述第二电源，并自所述第二电源接收所述第二阴极电压；
    当所述控制单元接收的所述第二信号处于第二电位时，所述第一发光元件和所述第二发光元件的第二端均电性连接至所述第一电源，并同时自所述第一电源接收所述第一阴极电压，所述第一发光元件和所述第二发光元件均用于发光。
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