WO2024060477A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

Info

Publication number
WO2024060477A1
WO2024060477A1 PCT/CN2023/073775 CN2023073775W WO2024060477A1 WO 2024060477 A1 WO2024060477 A1 WO 2024060477A1 CN 2023073775 W CN2023073775 W CN 2023073775W WO 2024060477 A1 WO2024060477 A1 WO 2024060477A1
Authority
WO
WIPO (PCT)
Prior art keywords
fuse
contact plug
substrate
along
conductive interconnect
Prior art date
Application number
PCT/CN2023/073775
Other languages
English (en)
French (fr)
Inventor
姜立维
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Publication of WO2024060477A1 publication Critical patent/WO2024060477A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure and a method of forming the same.
  • DRAM Dynamic Random Access Memory
  • each storage unit usually includes a transistor and a capacitor.
  • the gate of the transistor is electrically connected to the word line
  • the source is electrically connected to the bit line
  • the drain is electrically connected to the capacitor.
  • the word line voltage on the word line can control the turning on and off of the transistor, so that the memory can be read through the bit line. Data information in the capacitor, or writing data information into the capacitor.
  • the fuse structure can be implemented using capacitors.
  • the capacitor of the fuse structure in the dynamic random access memory is formed synchronously with the gate in the transistor, and the structure is similar to the gate in the transistor. This not only increases the manufacturing complexity of the fuse structure, but also takes up a lot of space. The larger area in the memory unit is not conducive to further shrinking of the size of the semiconductor structure.
  • the breakdown position of the fuse structure is located within the substrate, the breakdown current of the fuse structure is small and misjudgment is prone to occur, thus reducing the electrical performance of the semiconductor structure.
  • the semiconductor structure and its formation method provided by some embodiments of the present disclosure are used to further reduce the size of the semiconductor structure while improving the electrical performance of the semiconductor structure.
  • the present disclosure provides a semiconductor structure including:
  • a substrate including a first doped region
  • a fuse assembly including a contact plug and a fuse structure, the contact plug including a first end electrically connected to the first doped region and a second end extending out of the substrate along a first direction. part, the fuse The structure is located above the second end along the first direction, and the fuse structure includes a fuse electrode and a fuse dielectric layer between the fuse electrode and the contact plug, the The first direction is perpendicular to the top surface of the substrate.
  • the substrate further includes a channel region and a second doping region located on a side of the channel region away from the first doping region along a second direction, the second direction parallel to the top surface of the substrate;
  • the semiconductor structure further includes:
  • the bit line is electrically connected to the second doped region, and the material of the contact plug is the same as that of the bit line, and the contact plug and the bit line are arranged in the same layer.
  • the contact plug extends along the first direction, and the first end of the contact plug extends into the first doped region; or,
  • the contact plug extends along the first direction, and the first end of the contact plug is located on a top surface of the first doped region.
  • the fuse structure extends along the first direction, the fuse structure includes a bottom end connected to the contact plug, and the fuse structure extends along the first direction. The bottom end is opposite the top end of the fuse structure;
  • the width of the bottom end of the fuse structure along the second direction is smaller than the width of the top end of the fuse structure along the second direction, and the second direction is parallel to the top surface of the substrate.
  • the fuse assembly further includes:
  • the first conductive interconnect layer is located on the second end portion of the contact plug, one end of the first conductive interconnect layer is electrically connected to the contact plug, and the other end of the first conductive interconnect layer is connected to the fuse structure.
  • the semiconductor structure further includes:
  • a transistor gate located on the channel region
  • the fuse structure is located at an end of the first conductive interconnect layer away from the transistor gate.
  • a bottom surface of the fuse structure is located above a top surface of the transistor gate.
  • the first conductive interconnect layer includes first and second portions relatively distributed along a second direction
  • the first portion is located on the second end of the contact plug, the second portion extends out of the contact plug in the second direction, and the fuse structure is located on the second portion superior.
  • the fuse structure includes:
  • the main body part extends along the first direction, and the main body part at least partially covers the top surface of the second part;
  • An extension part is connected to the main body part and extends out of the main body part along the first direction.
  • the extension part at least covers the side wall of the second part.
  • it also includes:
  • Peripheral circuit for receiving external control signals
  • the second conductive interconnect layer is located on the top surface of the bit line, one end of the second conductive interconnect layer is electrically connected to the bit line, and the other end is electrically connected to the peripheral circuit, and the second conductive interconnect layer is arranged in the same layer as the first conductive interconnect layer.
  • the projection of the first conductive interconnect layer on the top surface of the substrate completely coincides with the projection of the contact plug on the top surface of the substrate, and the fuse structure The projection of the first conductive interconnect layer on the top surface of the substrate completely coincides with the projection of the first conductive interconnect layer on the top surface of the substrate;
  • the first conductive interconnect layer extends along the first direction, and a bottom surface of the first conductive interconnect layer is in contact and electrically connected to the second end of the contact plug, and the first conductive interconnect layer The top surface of the connecting layer is in contact with the fuse structure.
  • the fuse structure has grooves in it
  • the first conductive interconnect layer extends along the first direction and is embedded in the groove.
  • the fuse structure extends along the first direction, and the fuse structure is embedded within the second end of the contact plug along the first direction.
  • the present disclosure also provides a method for forming a semiconductor structure, including the following steps:
  • a fuse component is formed on the substrate, the fuse component includes a contact plug and a fuse structure, the contact plug includes a first end portion electrically connected to the first doped region, and a fuse structure along a first end portion. Extending out of the second end of the substrate in one direction, the fuse structure is located above the second end along the first direction, and the fuse structure includes a fuse electrode and a fuse electrode located on the fuse. between the wire electrode and the contact plug In the fuse dielectric layer, the first direction is perpendicular to the top surface of the substrate.
  • the substrate further includes a channel region and a second doped region located along a second direction on a side of the channel region away from the first doped region, wherein the second direction is parallel to a top surface of the substrate; the step of forming a fuse assembly on the substrate includes:
  • the fuse structure is formed above the contact plug.
  • the specific steps of forming the fuse structure over the contact plug include:
  • the fuse structure is formed on the first conductive interconnect layer.
  • the first conductive interconnect layer includes a first portion and a second portion relatively distributed along a second direction, the first portion is located on the second end of the contact plug, and the A second portion extends out of the contact plug along the second direction, which is parallel to the top surface of the substrate; the specific method for forming the fuse structure on the first conductive interconnect layer Steps include:
  • the fuse structure is formed on the second part, and the fuse structure at least covers the top surface and side walls of the second part.
  • Some embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, by arranging a contact plug electrically connected to the first doped region, and arranging a fuse structure on the second end of the contact plug protruding from the substrate, so that The breakdown position of the fuse structure is located above the substrate, ensuring a large breakdown current when the fuse dielectric layer in the fuse structure is broken down, reducing the probability of misreading, thereby improving the semiconductor structure electrical properties.
  • the contact plug and fuse structure in some embodiments of the present disclosure have simple structures and do not need to be similar to the transistor gate structure.
  • the fuse assembly occupies an area on the substrate, thereby reducing the size of the memory cell with the fuse assembly, which helps further shrink the size of the semiconductor structure.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor structure in a first embodiment of the present disclosure
  • FIG. 2 is a schematic cross-sectional view of a semiconductor structure in a second embodiment of the present disclosure
  • FIG. 3 is a schematic cross-sectional view of a semiconductor structure in a third embodiment of the present disclosure.
  • FIG. 4 is a schematic cross-sectional view of a semiconductor structure in a fourth embodiment of the present disclosure.
  • FIG. 5 is a schematic cross-sectional view of a semiconductor structure in a fifth embodiment of the present disclosure.
  • FIG. 6 is a flow chart of a method for forming a semiconductor structure in an embodiment of the present disclosure.
  • FIG. 1 is a schematic cross-sectional view of the semiconductor structure in the first embodiment of the specific implementation of the present disclosure.
  • Figure 2 is a schematic cross-sectional view of the semiconductor structure in the second embodiment of the specific implementation of the present disclosure.
  • Figure 3 is a schematic cross-sectional view of the semiconductor structure in the third embodiment of the present disclosure.
  • Figure 4 is a schematic cross-sectional view of the semiconductor structure in the fourth embodiment of the present disclosure.
  • Figure 5 is a schematic cross-sectional view of the semiconductor structure in the third embodiment of the present disclosure.
  • a schematic cross-sectional view of a semiconductor structure in a fifth embodiment of the disclosure is disclosed.
  • the semiconductor structure includes:
  • Substrate 10 the substrate 10 includes a first doped region 11;
  • the fuse assembly includes a contact plug 13 and a fuse structure.
  • the contact plug 13 includes a first end portion electrically connected to the first doped region 11 and extends out of the substrate along a first direction D1.
  • the fuse structure is located above the second end along the first direction D1, and the fuse structure includes a fuse electrode 18, and is located between the fuse electrode 18 and the
  • the first direction D1 is perpendicular to the top surface of the substrate 10 in the fuse dielectric layer 17 between the contact plugs 13 .
  • the semiconductor structure described in this specific embodiment may be, but is not limited to, a DRAM.
  • the following description takes the semiconductor structure as a DRAM as an example.
  • the substrate 10 may be, but is not limited to, a silicon substrate. This specific embodiment will be described by taking the substrate 10 as a silicon substrate as an example. In other embodiments, the substrate 10 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI. .
  • the substrate 10 is a silicon substrate including P-type doping ions, and the first doping region 11 includes N-type doping ions.
  • the substrate 10 further includes an N-type deep well region 19 .
  • the substrate 10 may include a plurality of memory cells arranged in an array in a direction parallel to the top surface of the substrate 10.
  • Each of the memory cells includes a transistor structure and a capacitor structure to form a 1T1C structure, where , the transistor structure serves as a switching device of the memory cell.
  • the top surface of the substrate 10 refers to the surface of the substrate 10 facing the fuse structure.
  • the contact plug 13 for connecting the first doping region 11 and the fuse structure is provided, and the fuse structure is located on the second end portion of the contact plug 13 protruding from the substrate 10, so that when the fuse structure is programmed (i.e., broken down), a voltage is applied to the fuse electrode 18 in the fuse structure to cause the fuse dielectric layer 17 to break down.
  • the breakdown current is much larger than when the breakdown position is located inside the substrate 10, thereby avoiding a reading error caused by an excessively small breakdown current (for example, a reading error means that a first reading value (e.g., "1") is misjudged as a second reading value (e.g., "0") due to an excessively small breakdown current), thereby improving the electrical performance of the semiconductor structure and improving the reliability of the semiconductor structure.
  • a reading error means that a first reading value (e.g., "1") is misjudged as a second reading value (e.g., "0") due to an excessively small breakdown current), thereby improving the electrical performance of the semiconductor structure and improving the reliability of the semiconductor structure.
  • the contact plug 13 with a columnar structure is electrically connected to the first doped region 11, and the fuse structure includes the fuse electrode 18 and the fuse dielectric layer 17 that at least covers the bottom surface and part of the side wall of the fuse electrode 18, which simplifies the structure of the fuse component and reduces the occupied area of the fuse component on the substrate 10, reduces the size of the storage unit, and contributes to further miniaturization of the size of the semiconductor structure and further improvement of the internal integration of the semiconductor structure.
  • the material of the fuse dielectric layer 17 can be an insulating dielectric material such as oxide (such as silicon dioxide).
  • oxide such as silicon dioxide
  • the specific thickness of the fuse dielectric layer 17 can be selected by those skilled in the art according to actual needs. , for example, set according to the required breakdown current.
  • the fuse electrode 18 may be made of the same material as the contact plug 13 , for example, both are conductive materials such as metal tungsten.
  • the substrate 10 further includes a channel region and a second doped region 12 located on the side of the channel region away from the first doped region 11 along the second direction D2, so The second direction D2 is parallel to the top surface of the substrate 10; the semiconductor structure further includes:
  • the bit line 15 is electrically connected to the second doped region 12, and the material of the contact plug 13 is the same as the material of the bit line 15, and the contact plug 13 and the bit line 15 are in the same layer. set up.
  • the first doped region 11 is either the source region or the drain region in the transistor structure in one of the memory cells.
  • the second doped region 12 It is the other one of the source region or the drain region in the transistor structure in the same memory cell.
  • the first doping region 11 and the second doping region 12 have the same type of doping ions, for example, both include N-type doping ions.
  • the first doped region 11 is used as the drain region, and the second doped region 12
  • the source region is taken as an example for description.
  • the material of the contact plug 13 is the same as the material of the bit line 15, and the contact plug 13 and the bit line 15 are arranged in the same layer, so the contact plug 13 and the bit line can be formed simultaneously. 15, thus simplifying the manufacturing process of the semiconductor structure and reducing the manufacturing cost of the semiconductor structure.
  • the material of the contact plug 13 and the material of the bit line 15 are both conductive materials such as metal tungsten.
  • the contact plug 13 extends along the first direction D1, and the first end of the contact plug 13 extends into the first doped region 11; or,
  • the contact plug 13 extends along the first direction D1 , and the first end of the contact plug 13 is located on the top surface of the first doped region 11 .
  • the first end of the contact plug 13 extends into the first doped region 11 , thereby increasing the distance between the contact plug 13 and the first doped region 11 .
  • the contact area between the contact plugs 13 and the first doping region 11 is thereby reduced to further improve the electrical performance of the semiconductor structure.
  • the bit line 15 formed simultaneously with the contact plug 13 also extends along the first direction D1, and the bottom surface of the bit line 13 extends into the second doped region 12.
  • the first end of the contact plug 13 is located on the top surface of the first doped region 11 , so that during etching of the plug used to form the contact plug 13 hole (the contact plug 13 is subsequently formed by filling the plug hole with conductive material), the first doped region 11 can be used as an etching stop layer to avoid plug holes caused by over-etching. Penetrating the first doping region 11 simplifies the manufacturing process of the semiconductor structure and avoids damage to the substrate 10 .
  • the bit line 15 formed simultaneously with the contact plug 13 also extends along the first direction D1, and the bottom surface of the bit line 13 is located on the top surface of the second doped region 12.
  • the contact plug 13 only extends to the inside of the first doped region 11 , as shown in FIG. 1 .
  • the semiconductor structure further includes an isolation structure 20 between adjacent memory cells, and the contact plug 13 extends into the isolation structure 20 and the in the first doped region 11 , and the extension depth of the contact plug 13 in the isolation structure 20 is greater than the extension depth of the contact plug 13 in the first doped region 11 , thereby increasing the The contact area between the contact plug 13 and the substrate 10 not only improves the connection stability between the contact plug 13 and the substrate 10 , but also reduces the contact area between the contact plug 13 and the third substrate 10 . a doped region 11 contact resistance, thereby further improving the performance of the semiconductor structure.
  • the fuse structure extends along the first direction D1, and the fuse structure includes a bottom end connected to the contact plug 13 and a connection with the contact plug 13 along the first direction D1.
  • the bottom end of the fuse structure is opposite the top end of the fuse structure;
  • the width of the bottom end of the fuse structure along the second direction D2 is smaller than the width of the top end of the fuse structure along the second direction D2 , and the second direction D2 is parallel to the top surface of the substrate 10 .
  • the fuse dielectric layer 17 in the fuse structure covers the entire bottom surface and the entire side wall of the fuse electrode 18, so that the top surface of the fuse dielectric layer 17 is in contact with the fuse
  • the top surface of electrode 18 is flush.
  • the width of the bottom end of the fuse structure along the second direction D2 is smaller than the width of the top end of the fuse structure along the second direction D2 means that the fuse dielectric layer 17 and the The width of the whole bottom end of the fuse electrode 18 along the second direction D2 is smaller than the width of its top end along the second direction D2. Designing the size of the bottom end of the fuse structure to be smaller is conducive to breakdown of the fuse dielectric layer 17 through tip discharge, thereby making it easier to breakdown the fuse dielectric layer 17 and making the electrical conductivity of the semiconductor structure Performance is further improved.
  • the fuse assembly further includes:
  • a first conductive interconnection layer 14 is located on the second end of the contact plug 13. One end of the first conductive interconnection layer 14 is electrically connected to the contact plug 13, and the other end is connected to the fuse plug.
  • Silk structure One end of the first conductive interconnection layer 14 is electrically connected to the contact plug 13, and the other end is connected to the fuse plug.
  • the semiconductor structure further includes:
  • the transistor gate 21 is located on the channel region
  • the fuse structure is located at an end of the first conductive interconnection layer 14 away from the transistor gate 21.
  • the memory unit also includes a transistor structure, which includes a transistor gate dielectric layer 23, a transistor gate contact layer 22 located on the transistor gate dielectric layer 23, and a transistor gate contact layer 22 located on the transistor gate contact layer 22.
  • the transistor gate 21 In one example, the material of the transistor gate dielectric layer 23 is an insulating dielectric material such as oxide (such as silicon dioxide), the material of the transistor gate contact layer 22 is a conductive material such as polysilicon, and the transistor gate electrode 21 The material is conductive material such as metal tungsten.
  • the semiconductor structure includes at least two memory cells spaced apart along the second direction D2, and one bit line 15 is connected to two bit lines 15 located on opposite sides of the bit line 15 along the second direction D2. The transistor structures in the memory cells are electrically connected. Locating the fuse structure at an end of the first conductive interconnection layer 14 away from the transistor gate 21 can increase the efficiency of the two memory cells spaced apart along the second direction D2. The distance between fuse structures thereby reduces signal crosstalk between adjacent memory cells.
  • the fuse structure In order to reduce the interaction between the fuse structure and the transistor gate 21 , thereby further improving the electrical performance of the semiconductor structure, in some embodiments, along the first direction D1 , the fuse structure The bottom surface of the wire structure is located above the top surface of the transistor gate 21 .
  • the first conductive interconnect layer 14 includes a first portion and a second portion relatively distributed along the second direction D2;
  • the first part is located on the second end of the contact plug 13, the second part extends out of the contact plug 13 along the second direction D2, and the fuse structure is located on the Part 2 on.
  • the first axis in the first conductive interconnect layer 14 is staggered from the second axis in the contact plug 13 , such as The first axis in the first conductive interconnect layer 14 is offset by a predetermined distance in the second direction D2 relative to the second axis in the contact plug 13 .
  • the first axis refers to an axis passing through the center of the first conductive interconnection layer 14 and extending along the first direction D1
  • the second axis refers to an axis passing through the center of the contact plug 13 and an axis extending along the first direction D1.
  • This specific embodiment bridges the contact plug 13 and the fuse structure through the first conductive interconnection layer 14. On the one hand, it helps to increase the process window for forming the fuse structure, thereby reducing the The manufacturing process of the semiconductor structure is difficult; on the other hand, the manufacturing process of the contact plug 13 can also be made compatible with the manufacturing process of the metal interconnection layer in the semiconductor structure, thereby further simplifying the manufacturing process of the semiconductor structure.
  • the fuse structure includes:
  • the main body part extends along the first direction D1, and the main body part at least partially covers the top surface of the second part;
  • An extension part is connected to the main body part and extends out of the main body part along the first direction D1.
  • the extension part at least covers the side wall of the second part.
  • the main body portion includes the fuse electrode 18 and a
  • the extension part also includes the fuse electrode 18 and the fuse dielectric layer 17 covering the surface of the fuse electrode 18 .
  • connection stability between a conductive interconnect layer 14 and the fuse structure on the other hand, multiple sharp corners can also be formed in the fuse structure (for example, the main body portion and the first conductive interconnect).
  • the included angle at the contact interface of the connecting layer 14 and the sharp angle at the contact interface between the extension part and the first conductive layer 14 are conducive to breakdown of the fuse dielectric layer 17 through tip discharge to further improve the Describe the properties of semiconductor structures.
  • the semiconductor structure further includes:
  • a peripheral circuit for receiving an external control signal
  • the second conductive interconnect layer 16 is located on the top surface of the bit line 15. One end of the second conductive interconnect layer 16 is electrically connected to the bit line 15 and the other end is electrically connected to the peripheral circuit.
  • the two conductive interconnection layers 16 are arranged on the same layer as the first conductive interconnection layer 14 . At this time, the first conductive interconnection layer 14 and the second conductive interconnection layer 16 can be formed simultaneously to further simplify the manufacturing process of the semiconductor structure.
  • the projection of the first conductive interconnect layer 14 on the top surface of the substrate 10 is the same as the projection of the contact plug 13 on the top surface of the substrate 10 .
  • the projection on the top surface of the substrate 10 completely coincides with the projection of the fuse structure on the top surface of the substrate 10 and the projection of the first conductive interconnect layer 14 on the top surface of the substrate 10 ;
  • the first conductive interconnection layer 14 extends along the first direction D1, and the bottom surface of the first conductive interconnection layer 14 is in contact and electrically connected with the second end of the contact plug 13.
  • the top surface of the first conductive interconnect layer 14 is in contact connection with the fuse structure. At this time, the space occupied by the fuse component is further reduced, thereby contributing to further reduction in the size of the semiconductor structure.
  • the fuse structure has grooves
  • the first conductive interconnect layer 14 extends along the first direction D1 and is embedded in the groove. At this time, the contact area between the fuse structure and the first conductive interconnection layer 14 can be further increased, and the size of the semiconductor structure can also be further reduced.
  • the fuse structure extends along the first direction D1 , and the fuse structure is embedded in the contact plug 13 along the first direction D1 .
  • the width of the fuse structure embedded inside the contact plug 13 is smaller than the width of the fuse structure located outside the contact plug 13 (for example, the width along the second direction D2), thereby not only facilitating breakdown of the fuse by tip discharge
  • the silk dielectric layer 17 can further reduce the size of the memory cell and simplify the manufacturing process of the semiconductor structure.
  • FIG. 6 is a flow chart of the method for forming a semiconductor structure in the embodiment of the disclosure. Schematic diagrams of the semiconductor structure formed in this specific embodiment can be seen in Figures 1-5. As shown in Figures 1-6, the method for forming the semiconductor structure includes the following steps:
  • Step S61 forming a substrate 10, which includes a first doped region 11;
  • Step S62 Form a fuse component on the substrate 10.
  • the fuse component includes a contact plug 13 and a fuse structure.
  • the contact plug 13 includes a third electrode electrically connected to the first doped region 11. One end and a second end extending out of the substrate 10 along the first direction D1, the fuse structure is located above the second end along the first direction D1, and the fuse structure Including the fuse electrode 18 and the fuse dielectric layer 17 located between the fuse electrode 18 and the contact plug 13 , the first direction D1 is perpendicular to the top surface of the substrate 10 .
  • the substrate 10 further includes a channel region and a second doped region 12 located on the side of the channel region away from the first doped region 11 along the second direction D2, so The second direction D2 is parallel to the top surface of the substrate 10; the step of forming the fuse component on the substrate 10 includes:
  • the contact plug 13 extending along the first direction D1 is formed above the first doped region 11 , and a bit line extending along the first direction D1 is formed above the second doped region 12 . 15;
  • the fuse structure is formed above the contact plug 13 .
  • conductive materials such as metal tungsten or polysilicon can be deposited on the first doped region 11 at the same time.
  • the contact plug 13 and the bit line 15 are formed simultaneously.
  • the specific steps of forming the fuse structure above the contact plug 13 include:
  • the fuse structure is formed on the first conductive interconnect layer 14 .
  • forming a first conductive interconnect layer 14 on the second end of the contact plug 13 that is electrically connected to the second end includes:
  • a first conductive interconnect layer 14 electrically connected to the second end is formed on the second end of the contact plug 13, and at the same time, a first conductive interconnect layer 14 is formed above the bit line 15 and connected to the bit line 15.
  • a second conductive interconnect layer 16 is electrically connected, and the second conductive interconnect layer 16 is used to electrically connect with a peripheral circuit, and the peripheral circuit is used to receive an external control signal.
  • conductive materials such as metal tungsten or TiN can be deposited on the top surface of the contact plug 13 and the top surface of the bit line 15 at the same time.
  • the first conductive interconnect layer 14 and the second conductive interconnect layer 16 are formed simultaneously.
  • the first conductive interconnect layer 14 includes a first portion and a second portion relatively distributed along the second direction D2, the first portion being located on the second end of the contact plug 13 , the second portion extends out of the contact plug 13 along the second direction D2, which is parallel to the top surface of the substrate 10; on the first conductive interconnect layer 14
  • Specific steps to form the fuse structure include:
  • the fuse structure is formed on the second portion, and the fuse structure at least covers the top surface and sidewalls of the second portion, as shown in FIG. 1 .
  • the first conductive interconnect layer 14 extends along the first direction D1; the specific steps of forming the fuse structure on the first conductive interconnect layer 14 include:
  • the fuse structure is formed covering the top surface and sidewalls of the first conductive interconnect layer 14 as shown in FIG. 2 .
  • the specific steps of forming the fuse structure above the contact plug 13 include:
  • a fuse structure extending along the first direction D1 is formed on the contact plug 13 , and the fuse structure is embedded into the second end of the contact plug 13 along the first direction D1 ,As shown in Figure 4.
  • Some embodiments of this specific embodiment provide a semiconductor structure and a method for forming the same by arranging a contact plug electrically connected to the first doped region, and arranging a fuse structure on the second end of the contact plug protruding from the substrate. , so that the breakdown position of the fuse structure is located above the substrate, ensuring that the When the fuse dielectric layer is broken down, it has a larger breakdown current, which reduces the probability of misreading, thus improving the electrical properties of the semiconductor structure.
  • the contact plug and fuse structure in some embodiments of this embodiment have a simple structure and do not need to be similar to the transistor gate structure. This not only simplifies the manufacturing process of the fuse assembly, reduces the manufacturing cost of the semiconductor structure, but also reduces the cost of the semiconductor structure. The occupied area of the fuse assembly on the substrate is reduced, thereby reducing the size of the memory unit with the fuse assembly, which helps to further shrink the size of the semiconductor structure.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Semiconductor Memories (AREA)

Abstract

本公开涉及一种半导体结构及其形成方法。所述半导体结构包括：衬底，所述衬底内包括第一掺杂区；熔丝组件，包括接触插塞和熔丝结构，所述接触插塞包括与所述第一掺杂区电连接的第一端部、以及沿第一方向延伸出所述衬底的第二端部，所述熔丝结构沿所述第一方向位于所述第二端部上方，且所述熔丝结构包括熔丝电极、以及位于所述熔丝电极与所述接触插塞之间的熔丝介质层，所述第一方向与所述衬底的顶面垂直。本公开改善了半导体结构的电性能，且有助于半导体结构的尺寸进一步微缩。

Description

半导体结构及其形成方法
相关申请引用说明
本申请要求于2022年09月21日递交的中国专利申请号202211152105.X、申请名为“半导体结构及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本公开涉及半导体制造技术领域，尤其涉及一种半导体结构及其形成方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机等电子设备中常用的半导体装置，其由多个存储单元构成，每个存储单元通常包括晶体管和电容器。所述晶体管的栅极与字线电连接、源极与位线电连接、漏极与电容器电连接，字线上的字线电压能够控制晶体管的开启和关闭，从而通过位线能够读取存储在电容器中的数据信息，或者将数据信息写入到电容器中。
熔丝(Fuse)结构作为一次性可编程结构，可以采用电容器实现。但是，动态随机存储器中的熔丝结构的电容器与晶体管中的栅极同步形成，结构也与晶体管中的栅极类似，这不仅增大了熔丝结构的制造复杂度，而且熔丝结构占用了存储单元内较大的面积，不利于半导体结构尺寸的进一步微缩。另外，由于熔丝结构的击穿位置位于衬底内，熔丝结构的击穿电流较小，易出现误判的情况，从而降低了半导体结构的电性能。
因此，如何在改善半导体结构电性能的同时，进一步缩小半导体结构的尺寸，是当前亟待解决的技术问题。
发明内容
本公开一些实施例提供的半导体结构及其形成方法，用于在改善半导体结构电性能的同时，进一步缩小半导体结构的尺寸。
根据一些实施例，本公开提供了一种半导体结构，包括：
衬底，所述衬底内包括第一掺杂区；
熔丝组件，包括接触插塞和熔丝结构，所述接触插塞包括与所述第一掺杂区电连接的第一端部、以及沿第一方向延伸出所述衬底的第二端部，所述熔丝 结构沿所述第一方向位于所述第二端部上方，且所述熔丝结构包括熔丝电极、以及位于所述熔丝电极与所述接触插塞之间的熔丝介质层，所述第一方向与所述衬底的顶面垂直。
在一些实施例中，所述衬底内还包括沟道区、以及沿第二方向位于所述沟道区远离所述第一掺杂区一侧的第二掺杂区，所述第二方向与所述衬底的顶面平行；所述半导体结构还包括：
位线，与所述第二掺杂区电连接，且所述接触插塞的材料与所述位线的材料相同，且所述接触插塞与所述位线同层设置。
在一些实施例中，所述接触插塞沿所述第一方向延伸，且所述接触插塞的所述第一端部延伸至所述第一掺杂区内部；或者，
所述接触插塞沿所述第一方向延伸，且所述接触插塞的所述第一端部位于所述第一掺杂区的顶面上。
在一些实施例中，所述熔丝结构沿所述第一方向延伸，所述熔丝结构包括沿与所述接触插塞连接的底端、以及沿所述第一方向与所述熔丝结构的底端相对的所述熔丝结构的顶端；
所述熔丝结构的底端沿第二方向的宽度小于所述熔丝结构的顶端沿所述第二方向的宽度，所述第二方向与所述衬底的顶面平行。
在一些实施例中，所述熔丝组件还包括：
第一导电互连层，位于所述接触插塞的所述第二端部上，所述第一导电互连层的一端电连接所述接触插塞、另一端连接所述熔丝结构。
在一些实施例中，所述第一导电互连层沿所述第二方向延伸；所述半导体结构还包括：
晶体管栅极，位于所述沟道区上；
在沿所述第二方向上，所述熔丝结构位于所述第一导电互连层远离所述晶体管栅极的一端。
在一些实施例中，在沿所述第一方向上，所述熔丝结构的底面位于所述晶体管栅极的顶面之上。
在一些实施例中，所述第一导电互连层包括沿第二方向相对分布的第一部分和第二部分；
所述第一部分位于所述接触插塞的所述第二端部上，所述第二部分沿所述第二方向延伸出所述接触插塞，且所述熔丝结构位于所述第二部分上。
在一些实施例中，所述熔丝结构包括：
主体部，沿所述第一方向延伸，且所述主体部至少部分覆盖于所述第二部分的顶面上；
延伸部，与所述主体部连接、且沿所述第一方向延伸出所述主体部，所述延伸部至少覆盖于所述第二部分的侧壁上。
在一些实施例中，还包括：
外围电路，用于接收外部控制信号；
第二导电互连层，位于所述位线的顶面上，所述第二导电互连层一端电连接所述位线、另一端电连接所述外围电路，且所述第二导电互连层与所述第一导电互连层同层设置。
在一些实施例中，所述第一导电互连层在所述衬底的顶面上的投影与所述接触插塞在所述衬底的顶面上的投影完全重合，所述熔丝结构在所述衬底的顶面上的投影与所述第一导电互连层在所述衬底的顶面上的投影完全重合；
所述第一导电互连层沿所述第一方向延伸，且所述第一导电互连层的底面与所述接触插塞的所述第二端部接触电连接、所述第一导电互连层的顶面与所述熔丝结构接触连接。
在一些实施例中，所述熔丝结构中具有凹槽；
所述第一导电互连层沿所述第一方向延伸，且嵌入所述凹槽内。
在一些实施例中，所述熔丝结构沿所述第一方向延伸，且所述熔丝结构沿所述第一方向嵌入所述接触插塞的所述第二端部的内部。
根据另一些实施例，本公开还提供了一种半导体结构的形成方法，包括如下步骤：
形成衬底，所述衬底内包括第一掺杂区；
形成熔丝组件于所述衬底上，所述熔丝组件包括接触插塞和熔丝结构，所述接触插塞包括与所述第一掺杂区电连接的第一端部、以及沿第一方向延伸出所述衬底的第二端部，所述熔丝结构沿所述第一方向位于所述第二端部上方，且所述熔丝结构包括熔丝电极、以及位于所述熔丝电极与所述接触插塞之间的 熔丝介质层，所述第一方向与所述衬底的顶面垂直。
在一些实施例中，所述衬底内还包括沟道区、以及沿第二方向位于所述沟道区远离所述第一掺杂区一侧的第二掺杂区，所述第二方向与所述衬底的顶面平行；形成熔丝组件于所述衬底上的步骤包括：
于所述第一掺杂区上方形成沿所述第一方向延伸的所述接触插塞、同时于所述第二掺杂区上方形成沿所述第一方向延伸的位线；
于所述接触插塞上方形成所述熔丝结构。
在一些实施例中，于所述接触插塞上方形成所述熔丝结构的具体步骤包括：
于所述接触插塞的所述第二端部上形成与所述第二端部电连接的第一导电互连层；
于所述第一导电互连层上形成所述熔丝结构。
在一些实施例中，所述第一导电互连层包括沿第二方向相对分布的第一部分和第二部分，所述第一部分位于所述接触插塞的所述第二端部上，所述第二部分沿所述第二方向延伸出所述接触插塞，所述第二方向与所述衬底的顶面平行；于所述第一导电互连层上形成所述熔丝结构的具体步骤包括：
于所述第二部分上形成所述熔丝结构，且所述熔丝结构至少覆盖所述第二部分的顶面和侧壁。
本公开一些实施例提供的半导体结构及其形成方法，通过设置与第一掺杂区电连接的接触插塞、且在接触插塞突出于衬底的第二端部上设置熔丝结构，使得熔丝结构的击穿位置位于所述衬底上方，确保所述熔丝结构中的熔丝介质层被击穿时具有较大的击穿电流，降低了误读的概率，从而改善了半导体结构的电性能。另外，本公开一些实施例中的接触插塞与熔丝结构的结构简单，无需与晶体管栅极结构类似，不仅简化了熔丝组件的制造工艺，降低了半导体结构的制造成本，而且减小了熔丝组件在所述衬底上的占用面积，进而减小了具有熔丝组件的存储单元的尺寸，有助于半导体结构的尺寸进一步微缩。
附图说明
附图1是本公开具体实施方式的第一实施例中半导体结构的截面示意图；
附图2是本公开具体实施方式的第二实施例中半导体结构的截面示意图；
附图3是本公开具体实施方式的第三实施例中半导体结构的截面示意图；
附图4是本公开具体实施方式的第四实施例中半导体结构的截面示意图；
附图5是本公开具体实施方式的第五实施例中半导体结构的截面示意图；
附图6是本公开具体实施方式中半导体结构的形成方法流程图。
具体实施方式
下面结合附图对本公开提供的半导体结构及其形成方法的具体实施方式做详细说明。
本具体实施方式提供了一种半导体结构，附图1是本公开具体实施方式的第一实施例中半导体结构的截面示意图，附图2是本公开具体实施方式的第二实施例中半导体结构的截面示意图，附图3是本公开具体实施方式的第三实施例中半导体结构的截面示意图，附图4是本公开具体实施方式的第四实施例中半导体结构的截面示意图，附图5是本公开具体实施方式的第五实施例中半导体结构的截面示意图。如图1-图5所示，所述半导体结构，包括：
衬底10，所述衬底10内包括第一掺杂区11；
熔丝组件，包括接触插塞13和熔丝结构，所述接触插塞13包括与所述第一掺杂区11电连接的第一端部、以及沿第一方向D1延伸出所述衬底10的第二端部，所述熔丝结构沿所述第一方向D1位于所述第二端部上方，且所述熔丝结构包括熔丝电极18、以及位于所述熔丝电极18与所述接触插塞13之间的熔丝介质层17，所述第一方向D1与所述衬底10的顶面垂直。
本具体实施方式中所述的半导体结构可以是但不限于DRAM，以下以所述半导体结构为DRAM为例进行说明。所述衬底10可以是但不限于硅衬底，本具体实施方式以所述衬底10为硅衬底为例进行说明。在其他实施例中，所述衬底10还可以为氮化镓、砷化镓、碳化镓、碳化硅或SOI等半导体衬底。。举例来说，所述衬底10为包括P型掺杂离子的硅衬底，所述第一掺杂区11包括N型掺杂离子。在一示例中，所述衬底10还包括N型深阱区19。所述衬底10上可以包括沿平行于所述衬底10的顶面的方向呈阵列排布的多个存储单元，每个所述存储单元包括晶体管结构和电容结构，以形成1T1C结构，其中，所述晶体管结构作为所述存储单元的开关器件。本具体实施方式中所述衬底10的顶面是指所述衬底10朝向所述熔丝结构的表面。
本具体实施方式通过设置用于连接所述第一掺杂区11和所述熔丝结构的所述接触插塞13，且所述熔丝结构位于所述接触插塞13凸出于所述衬底10的所述第二端部上，从而使得在对所述熔丝结构进行编程操作(即击穿)时，通过向所述熔丝结构中的所述熔丝电极18施加电压，使得所述熔丝介质层17击穿，此时，由于所述熔丝组件的电流击穿位置(即所述熔丝介质层17的位置)位于所述衬底10的上方，使得击穿电流相较于击穿位置位于所述衬底10内部时大得多，从而避免了因击穿电流过小而导致的读取错误(例如读取错误是指，由于击穿电流过小，将第一读取值(例如“1”)误判为第二读取值(例如“0”))，从而改善了半导体结构的电性能，提高了所述半导体结构的可靠性。另外，本具体实施方式中与所述第一掺杂区11接触电连接的为具有柱状结构的所述接触插塞13，且所述熔丝结构包括所述熔丝电极18、以及至少包覆所述熔丝电极18的底面和部分侧壁的所述熔丝介质层17，简化了所述熔丝组件的结构，并减少了所述熔丝组件在所述衬底10上的占用面积，缩小了所述存储单元的尺寸，有助于所述半导体结构尺寸的进一步微缩、以及所述半导体结构内部集成度的进一步提高。
在一示例中，所述熔丝介质层17的材料可以为氧化物(例如二氧化硅)等绝缘介质材料，所述熔丝介质层17的具体厚度，本领域技术人员可以根据实际需要进行选择，例如根据所需击穿电流的大小进行设置。所述熔丝电极18的材料可以与所述接触插塞13的材料相同，例如均为金属钨等导电材料。
在一些实施例中，所述衬底10内还包括沟道区、以及沿第二方向D2位于所述沟道区远离所述第一掺杂区11一侧的第二掺杂区12，所述第二方向D2与所述衬底10的顶面平行；所述半导体结构还包括：
位线15，与所述第二掺杂区12电连接，且所述接触插塞13的材料与所述位线15的材料相同，且所述接触插塞13与所述位线15同层设置。
具体来说，所述第一掺杂区11为一个所述存储单元内的所述晶体管结构中的源极区或者漏极区中的任一者，相应的，所述第二掺杂区12为同一所述存储单元内的所述晶体管结构中的所述源极区或者所述漏极区中的另一者。所述第一掺杂区11和所述第二掺杂区12具有相同类型的掺杂离子，例如均包括N型掺杂离子。以下以所述第一掺杂区11为所述漏极区，所述第二掺杂区12 为所述源极区为例进行说明。所述接触插塞13的材料与所述位线15的材料相同，且所述接触插塞13与所述位线15同层设置，因而可以同步形成所述接触插塞13和所述位线15，从而简化了所述半导体结构的制程工艺，降低了所述半导体结构的制造成本。在一示例中，所述接触插塞13的材料与所述位线15的材料均为金属钨等导电材料。
在一些实施例中，所述接触插塞13沿所述第一方向D1延伸，且所述接触插塞13的所述第一端部延伸至所述第一掺杂区11内部；或者，
所述接触插塞13沿所述第一方向D1延伸，且所述接触插塞13的所述第一端部位于所述第一掺杂区11的顶面上。
在一示例中，所述接触插塞13的所述第一端部延伸至所述第一掺杂区11内部，从而可以增大所述接触插塞13与所述第一掺杂区11之间的接触面积，从而降低所述接触插塞13与所述第一掺杂区11之间的接触电阻，以进一步改善所述半导体结构的电性能。此时，与所述接触插塞13同步形成的所述位线15也沿所述第一方向D1延伸，且所述位线13的底面延伸至所述第二掺杂区12内部。
在另一示例中，所述接触插塞13的所述第一端部位于所述第一掺杂区11的顶面上，从而使得在刻蚀用于形成所述接触插塞13的插塞孔时(后续通过向所述插塞孔填充导电材料来形成所述接触插塞13)，可以以所述第一掺杂区11作为刻蚀截止层，避免了因为过刻蚀导致插塞孔穿通所述第一掺杂区11，因而在简化所述半导体结构的制程工艺，也避免了对所述衬底10造成损伤。此时，与所述接触插塞13同步形成的所述位线15也沿所述第一方向D1延伸，且所述位线13的底面位于所述第二掺杂区12的顶面上。
在一些实施例中，所述接触插塞13仅延伸至所述第一掺杂区11的内部，如图1所示。在另一些实施例中，如图5所示，所述半导体结构还包括位于相邻所述存储单元之间的隔离结构20，所述接触插塞13延伸至所述隔离结构20内和所述第一掺杂区11内，且所述接触插塞13在所述隔离结构20内的延伸深度大于所述接触插塞13在所述第一掺杂区11内的延伸深度，从而增大所述接触插塞13与所述衬底10的接触面积，不仅提高所述接触插塞13与所述衬底10之间的连接稳定性，而且还能降低所述接触插塞13与所述第一掺杂区11 之间的接触电阻，从而进一步改善所述半导体结构的性能。
在一些实施例中，所述熔丝结构沿所述第一方向D1延伸，所述熔丝结构包括沿与所述接触插塞13连接的底端、以及沿所述第一方向D1与所述熔丝结构的底端相对的所述熔丝结构的顶端；
所述熔丝结构的底端沿第二方向D2的宽度小于所述熔丝结构的顶端沿所述第二方向D2的宽度，所述第二方向D2与所述衬底10的顶面平行。
具体来说，所述熔丝结构中的所述熔丝介质层17包覆所述熔丝电极18的整个底面和整个侧壁，使得所述熔丝介质层17的顶面与所述熔丝电极18的顶面平齐。所述熔丝结构的底端沿所述第二方向D2的宽度小于所述熔丝结构的顶端沿所述第二方向D2的宽度是指，由所述熔丝介质层17和其包覆的所述熔丝电极18构成的整体的底端沿所述第二方向D2的宽度小于其顶端沿所述第二方向D2的宽度。将所述熔丝结构的底端的尺寸设计的较小，有利于通过尖端放电击穿所述熔丝介质层17，从而更加容易击穿所述熔丝介质层17，使得所述半导体结构的电性能进一步提高。
在一些实施例中，所述熔丝组件还包括：
第一导电互连层14，位于所述接触插塞13的所述第二端部上，所述第一导电互连层14的一端电连接所述接触插塞13、另一端连接所述熔丝结构。
在一些实施例中，所述第一导电互连层14沿所述第二方向D2延伸；所述半导体结构还包括：
晶体管栅极21，位于所述沟道区上；
在沿所述第二方向D2上，所述熔丝结构位于所述第一导电互连层14远离所述晶体管栅极21的一端。
具体来说，所述存储单元中还包括晶体管结构，所述晶体管结构包括晶体管栅介质层23、位于晶体管栅介质层23上的晶体管栅接触层22、以及位于所述晶体管栅接触层22上的所述晶体管栅极21。在一示例中，所述晶体管栅介质层23的材料为氧化物(例如二氧化硅)等绝缘介质材料，所述晶体管栅接触层22的材料为多晶硅等导电材料，所述晶体管栅极21的材料为金属钨等导电材料。所述半导体结构中至少包括沿所述第二方向D2间隔排布的两个所述存储单元，且一条所述位线15与位于其沿所述第二方向D2相对两侧的两个所 述存储单元中的晶体管结构电连接。将所述熔丝结构位于所述第一导电互连层14远离所述晶体管栅极21的一端，可以增大沿所述第二方向D2间隔排布的两个所述存储单元中的所述熔丝结构之间的距离，从而减少相邻所述存储单元之间的信号串扰。
为了减少所述熔丝结构与所述晶体管栅极21之间的相互影响，从而进一步改善所述半导体结构的电性能，在一些实施例中，在沿所述第一方向D1上，所述熔丝结构的底面位于所述晶体管栅极21的顶面之上。
在一些实施例中，如图1所示，所述第一导电互连层14包括沿第二方向D2相对分布的第一部分和第二部分；
所述第一部分位于所述接触插塞13的所述第二端部上，所述第二部分沿所述第二方向D2延伸出所述接触插塞13，且所述熔丝结构位于所述第二部分上。
具体来说，如图1所示，在沿所述第一方向D1上，所述第一导电互连层14中的第一轴线与所述接触插塞13中的第二轴线错开，例如所述第一导电互连层14中的所述第一轴线相对于所述接触插塞13中的所述第二轴线沿所述第二方向D2偏移一预设距离。其中，所述第一轴线是指穿过所述第一导电互连层14的中心且沿所述第一方向D1延伸的轴线，所述第二轴线是指贯穿所述接触插塞13的中心且沿所述第一方向D1延伸的轴线。
本具体实施方式通过所述第一导电互连层14桥接所述接触插塞13和所述熔丝结构，一方面，有助于增大形成所述熔丝结构的工艺窗口，从而降低所述半导体结构的制程难度；另一方面，还能够将所述接触插塞13的制程工艺与所述半导体结构中金属互连层的制程工艺兼容，从而进一步简化所述半导体结构的制程工艺。
在一些实施例中，所述熔丝结构包括：
主体部，沿所述第一方向D1延伸，且所述主体部至少部分覆盖于所述第二部分的顶面上；
延伸部，与所述主体部连接、且沿所述第一方向D1延伸出所述主体部，所述延伸部至少覆盖于所述第二部分的侧壁上。
具体来说，所述主体部包括所述熔丝电极18、以及覆盖于所述熔丝电极 18表面的熔丝介质层17，所述延伸部也包括所述熔丝电极18、以及覆盖于所述熔丝电极18表面的熔丝介质层17。通过在所述熔丝结构中设置所述主体部和所述延伸部，一方面，可以增大所述熔丝结构与所述第一导电互连层14之间的接触面积，提高所述第一导电互连层14与所述熔丝结构之间的连接稳定性；另一方面，还可以在所述熔丝结构中形成多个尖角(例如所述主体部与所述第一导电互连层14接触界面处的夹角、所述延伸部与所述第一导电层14接触界面处的尖角)，从而有利于通过尖端放电击穿所述熔丝介质层17，以进一步改善所述半导体结构的性能。
在一些实施例中，所述半导体结构还包括：
外围电路，用于接收外部控制信号；
第二导电互连层16，位于所述位线15的顶面上，所述第二导电互连层16一端电连接所述位线15、另一端电连接所述外围电路，且所述第二导电互连层16与所述第一导电互连层14同层设置。此时，可以同步形成所述第一导电互连层14和所述第二导电互连层16，以进一步简化所述半导体结构的制程工艺。
在另一些实施例中，如图2所示，所述第一导电互连层14在所述衬底10的顶面上的投影与所述接触插塞13在所述衬底10的顶面上的投影完全重合，所述熔丝结构在所述衬底10的顶面上的投影与所述第一导电互连层14在所述衬底10的顶面上的投影完全重合；
所述第一导电互连层14沿所述第一方向D1延伸，且所述第一导电互连层14的底面与所述接触插塞13的所述第二端部接触电连接、所述第一导电互连层14的顶面与所述熔丝结构接触连接。此时，所述熔丝组件所占用的空间进一步缩小，从而有助于所述半导体结构尺寸的进一步微缩。
在另一些实施例中，如图3所示，所述熔丝结构中具有凹槽；
所述第一导电互连层14沿所述第一方向D1延伸，且嵌入所述凹槽内。此时，既能使得所述熔丝结构与所述第一导电互连层14之间的接触面积进一步增大，也能进一步缩小所述半导体结构的尺寸。
在另一些实施例中，如图4所示，所述熔丝结构沿所述第一方向D1延伸，且所述熔丝结构沿所述第一方向D1嵌入所述接触插塞13的所述第二端部的内部。在一示例中，嵌入所述接触插塞13内部的所述熔丝结构的宽度(例如沿 所述第二方向D2的宽度)小于位于所述接触插塞13外部的所述熔丝结构的宽度例如沿所述第二方向D2的宽度)，从而不仅有利于通过尖端放电击穿所述熔丝介质层17，而且还能进一步缩小所述存储单元的尺寸，并简化所述半导体结构的制造工艺。
本具体实施方式还提供了一种半导体结构的形成方法，附图6是本公开具体实施方式中半导体结构的形成方法流程图。本具体实施方式形成的半导体结构的示意图可参见图1-图5。如图1-图6所示，所述半导体结构的形成方法，包括如下步骤：
步骤S61，形成衬底10，所述衬底10内包括第一掺杂区11；
步骤S62，形成熔丝组件于所述衬底10上，所述熔丝组件包括接触插塞13和熔丝结构，所述接触插塞13包括与所述第一掺杂区11电连接的第一端部、以及沿第一方向D1延伸出所述衬底10的第二端部，所述熔丝结构沿所述第一方向D1位于所述第二端部上方，且所述熔丝结构包括熔丝电极18、以及位于所述熔丝电极18与所述接触插塞13之间的熔丝介质层17，所述第一方向D1与所述衬底10的顶面垂直。
在一些实施例中，所述衬底10内还包括沟道区、以及沿第二方向D2位于所述沟道区远离所述第一掺杂区11一侧的第二掺杂区12，所述第二方向D2与所述衬底10的顶面平行；形成熔丝组件于所述衬底10上的步骤包括：
于所述第一掺杂区11上方形成沿所述第一方向D1延伸的所述接触插塞13、同时于所述第二掺杂区12上方形成沿所述第一方向D1延伸的位线15；
于所述接触插塞13上方形成所述熔丝结构。
具体来说，在对所述衬底10进行掺杂，形成所述第一掺杂区11和所述第二掺杂区12之后，可以同时沉积金属钨或者多晶硅等导电材料于所述第一掺杂区11上和所述第二掺杂区12上，以同时形成所述接触插塞13和所述位线15。
在一些实施例中，于所述接触插塞13上方形成所述熔丝结构的具体步骤包括：
于所述接触插塞13的所述第二端部上形成与所述第二端部电连接的第一导电互连层14；
于所述第一导电互连层14上形成所述熔丝结构。
在一些实施例中，于所述接触插塞13的所述第二端部上形成与所述第二端部电连接的第一导电互连层14的步骤包括：
于所述接触插塞13的所述第二端部上形成与所述第二端部电连接的第一导电互连层14、并同时于所述位线15上方形成与所述位线15电连接的第二导电互连层16，所述第二导电互连层16用于与外围电路电连接，所述外围电路用于接收外部控制信号。
具体来说，在形成所述接触插塞13和所述位线15之后，可以同时沉积金属钨或者TiN等导电材料于所述接触插塞13的顶面和所述位线15的顶面，以同时形成所述第一导电互连层14和所述第二导电互连层16。
在一些实施例中，所述第一导电互连层14包括沿第二方向D2相对分布的第一部分和第二部分，所述第一部分位于所述接触插塞13的所述第二端部上，所述第二部分沿所述第二方向D2延伸出所述接触插塞13，所述第二方向D2与所述衬底10的顶面平行；于所述第一导电互连层14上形成所述熔丝结构的具体步骤包括：
于所述第二部分上形成所述熔丝结构，且所述熔丝结构至少覆盖所述第二部分的顶面和侧壁，如图1所示。
在一些实施例中，所述第一导电互连层14沿所述第一方向D1延伸；于所述第一导电互连层14上形成所述熔丝结构的具体步骤包括：
形成包覆所述第一导电互连层14的顶面和侧壁的所述熔丝结构，如图2所示。
在一些实施例中，于所述接触插塞13上方形成所述熔丝结构的具体步骤包括：
于所述接触插塞13上形成沿所述第一方向D1延伸的熔丝结构，所述熔丝结构沿所述第一方向D1嵌入所述接触插塞13的所述第二端部的内部，如图4所示。
本具体实施方式一些实施例提供的半导体结构及其形成方法，通过设置与第一掺杂区电连接的接触插塞、且在接触插塞突出于衬底的第二端部上设置熔丝结构，使得熔丝结构的击穿位置位于所述衬底上方，确保所述熔丝结构中的 熔丝介质层被击穿时具有较大的击穿电流，降低了误读的概率，从而改善了半导体结构的电性能。另外，本具体实施方式一些实施例中的接触插塞与熔丝结构的结构简单，无需与晶体管栅极结构类似，不仅简化了熔丝组件的制造工艺，降低了半导体结构的制造成本，而且减小了熔丝组件在所述衬底上的占用面积，进而减小了具有熔丝组件的存储单元的尺寸，有助于半导体结构的尺寸进一步微缩。
以上所述仅是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本公开原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (17)

  1. 一种半导体结构，包括：
    衬底，所述衬底内包括第一掺杂区；
    熔丝组件，包括接触插塞和熔丝结构，所述接触插塞包括与所述第一掺杂区电连接的第一端部、以及沿第一方向延伸出所述衬底的第二端部，所述熔丝结构沿所述第一方向位于所述第二端部上方，且所述熔丝结构包括熔丝电极、以及位于所述熔丝电极与所述接触插塞之间的熔丝介质层，所述第一方向与所述衬底的顶面垂直。
  2. 根据权利要求1所述的半导体结构，其中，所述衬底内还包括沟道区、以及沿第二方向位于所述沟道区远离所述第一掺杂区一侧的第二掺杂区，所述第二方向与所述衬底的顶面平行；所述半导体结构还包括：
    位线，与所述第二掺杂区电连接，且所述接触插塞的材料与所述位线的材料相同，且所述接触插塞与所述位线同层设置。
  3. 根据权利要求1所述的半导体结构，其中，所述接触插塞沿所述第一方向延伸，且所述接触插塞的所述第一端部延伸至所述第一掺杂区内部；或者，所述接触插塞沿所述第一方向延伸，且所述接触插塞的所述第一端部位于所述第一掺杂区的顶面上。
  4. 根据权利要求1所述的半导体结构，其中，所述熔丝结构沿所述第一方向延伸，所述熔丝结构包括沿与所述接触插塞连接的底端、以及沿所述第一方向与所述熔丝结构的底端相对的所述熔丝结构的顶端；
    所述熔丝结构的底端沿第二方向的宽度小于所述熔丝结构的顶端沿所述第二方向的宽度，所述第二方向与所述衬底的顶面平行。
  5. 根据权利要求2所述的半导体结构，其中，所述熔丝组件还包括：
    第一导电互连层，位于所述接触插塞的所述第二端部上，所述第一导电互连层的一端电连接所述接触插塞、另一端连接所述熔丝结构。
  6. 根据权利要求5所述的半导体结构，其中，所述第一导电互连层沿所述第二方向延伸；所述半导体结构还包括：
    晶体管栅极，位于所述沟道区上；
    在沿所述第二方向上，所述熔丝结构位于所述第一导电互连层远离所述晶体管栅极的一端。
  7. 根据权利要求6所述的半导体结构，其中，在沿所述第一方向上，所述熔丝结构的底面位于所述晶体管栅极的顶面之上。
  8. 根据权利要求5所述的半导体结构，其中，所述第一导电互连层包括沿第二方向相对分布的第一部分和第二部分；
    所述第一部分位于所述接触插塞的所述第二端部上，所述第二部分沿所述第二方向延伸出所述接触插塞，且所述熔丝结构位于所述第二部分上。
  9. 根据权利要求8所述的半导体结构，其中，所述熔丝结构包括：
    主体部，沿所述第一方向延伸，且所述主体部至少部分覆盖于所述第二部分的顶面上；
    延伸部，与所述主体部连接、且沿所述第一方向延伸出所述主体部，所述延伸部至少覆盖于所述第二部分的侧壁上。
  10. 根据权利要求8所述的半导体结构，还包括：
    外围电路，用于接收外部控制信号；
    第二导电互连层，位于所述位线的顶面上，所述第二导电互连层一端电连接所述位线、另一端电连接所述外围电路，且所述第二导电互连层与所述第一导电互连层同层设置。
  11. 根据权利要求5所述的半导体结构，其中，所述第一导电互连层在所述衬底的顶面上的投影与所述接触插塞在所述衬底的顶面上的投影完全重合，所述熔丝结构在所述衬底的顶面上的投影与所述第一导电互连层在所述衬底的顶面上的投影完全重合；
    所述第一导电互连层沿所述第一方向延伸，且所述第一导电互连层的底面与所述接触插塞的所述第二端部接触电连接、所述第一导电互连层的顶面与所述熔丝结构接触连接。
  12. 根据权利要求5所述的半导体结构，其中，所述熔丝结构中具有凹槽；
    所述第一导电互连层沿所述第一方向延伸，且嵌入所述凹槽内。
  13. 根据权利要求1所述的半导体结构，其中，所述熔丝结构沿所述第一方向 延伸，且所述熔丝结构沿所述第一方向嵌入所述接触插塞的所述第二端部的内部。
  14. 一种半导体结构的形成方法，包括如下步骤：
    形成衬底，所述衬底内包括第一掺杂区；
    形成熔丝组件于所述衬底上，所述熔丝组件包括接触插塞和熔丝结构，所述接触插塞包括与所述第一掺杂区电连接的第一端部、以及沿第一方向延伸出所述衬底的第二端部，所述熔丝结构沿所述第一方向位于所述第二端部上方，且所述熔丝结构包括熔丝电极、以及位于所述熔丝电极与所述接触插塞之间的熔丝介质层，所述第一方向与所述衬底的顶面垂直。
  15. 根据权利要求14所述的半导体结构的形成方法，其中，所述衬底内还包括沟道区、以及沿第二方向位于所述沟道区远离所述第一掺杂区一侧的第二掺杂区，所述第二方向与所述衬底的顶面平行；形成熔丝组件于所述衬底上的步骤包括：
    于所述第一掺杂区上方形成沿所述第一方向延伸的所述接触插塞、同时于所述第二掺杂区上方形成沿所述第一方向延伸的位线；
    于所述接触插塞上方形成所述熔丝结构。
  16. 根据权利要求15所述的半导体结构的形成方法，其中，于所述接触插塞上方形成所述熔丝结构的具体步骤包括：
    于所述接触插塞的所述第二端部上形成与所述第二端部电连接的第一导电互连层；
    于所述第一导电互连层上形成所述熔丝结构。
  17. 根据权利要求16所述的半导体结构的形成方法，其中，所述第一导电互连层包括沿第二方向相对分布的第一部分和第二部分，所述第一部分位于所述接触插塞的所述第二端部上，所述第二部分沿所述第二方向延伸出所述接触插塞，所述第二方向与所述衬底的顶面平行；于所述第一导电互连层上形成所述熔丝结构的具体步骤包括：
    于所述第二部分上形成所述熔丝结构，且所述熔丝结构至少覆盖所述第二部分的顶面和侧壁。
PCT/CN2023/073775 2022-09-21 2023-01-30 半导体结构及其形成方法 WO2024060477A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211152105.XA CN117794234A (zh) 2022-09-21 2022-09-21 半导体结构及其形成方法
CN202211152105.X 2022-09-21

Publications (1)

Publication Number Publication Date
WO2024060477A1 true WO2024060477A1 (zh) 2024-03-28

Family

ID=90396869

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/073775 WO2024060477A1 (zh) 2022-09-21 2023-01-30 半导体结构及其形成方法

Country Status (2)

Country Link
CN (1) CN117794234A (zh)
WO (1) WO2024060477A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101101793A (zh) * 2006-07-04 2008-01-09 三星电子株式会社 包括硫族化物材料的一次可编程器件及其操作方法
CN101645449A (zh) * 2008-08-07 2010-02-10 恩益禧电子股份有限公司 半导体器件及其制造方法
CN103915440A (zh) * 2013-01-08 2014-07-09 中芯国际集成电路制造(上海)有限公司 可多次编程器件、半导体器件的制作方法
CN104396014A (zh) * 2012-06-29 2015-03-04 高通股份有限公司 以反熔丝为特征的集成电路器件及其制造方法
US20170069570A1 (en) * 2015-09-08 2017-03-09 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
CN111987100A (zh) * 2019-05-23 2020-11-24 长鑫存储技术有限公司 半导体结构及其制造方法、存储器

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101101793A (zh) * 2006-07-04 2008-01-09 三星电子株式会社 包括硫族化物材料的一次可编程器件及其操作方法
CN101645449A (zh) * 2008-08-07 2010-02-10 恩益禧电子股份有限公司 半导体器件及其制造方法
CN104396014A (zh) * 2012-06-29 2015-03-04 高通股份有限公司 以反熔丝为特征的集成电路器件及其制造方法
CN103915440A (zh) * 2013-01-08 2014-07-09 中芯国际集成电路制造(上海)有限公司 可多次编程器件、半导体器件的制作方法
US20170069570A1 (en) * 2015-09-08 2017-03-09 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
CN111987100A (zh) * 2019-05-23 2020-11-24 长鑫存储技术有限公司 半导体结构及其制造方法、存储器

Also Published As

Publication number Publication date
CN117794234A (zh) 2024-03-29

Similar Documents

Publication Publication Date Title
US7968403B2 (en) Method of fabricating a sleeve insulator for a contact structure
JPH0730077A (ja) 半導体装置およびその製造方法
CN112951769B (zh) 半导体存储器及其形成方法
WO2022160565A1 (zh) 半导体结构及其形成方法
US6642566B1 (en) Asymmetric inside spacer for vertical transistor
JP2005528788A (ja) 信頼性が改善された強誘電体メモリ集積回路
WO2024060477A1 (zh) 半导体结构及其形成方法
US7064366B2 (en) Ferroelectric memory devices having an expanded plate electrode
JPH10209394A (ja) 半導体記憶装置およびその製造方法
WO2022095466A1 (zh) 半导体结构及半导体结构制作方法
KR100781818B1 (ko) 메모리 셀 형성 방법
US5867362A (en) Storage capacitor for DRAM memory cell
US20110057240A1 (en) Semiconductor device and method of manufacturing the same
KR100351888B1 (ko) 반도체소자의 배선구조 및 형성방법
KR20010077260A (ko) 반도체 메모리 장치의 비트 라인 형성 방법
CN219437502U (zh) 半导体器件
US11930631B2 (en) Semiconductor memory device and method of fabricating the same
CN113838852B (zh) 半导体存储装置及其形成方法
US20230413515A1 (en) Semiconductor structure and manufacturing method thereof, memory chip and electronic device
US20220302125A1 (en) Semiconductor memory and forming method thereof
CN218920890U (zh) 半导体器件
US20230413523A1 (en) Semiconductor structure and method for forming semiconductor structure
US20230345711A1 (en) Semiconductor structure and method for forming semiconductor structure
EP4322182A1 (en) Semiconductor device and forming method therefor
WO2024031818A1 (zh) 半导体结构及其形成方法、存储器

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23866783

Country of ref document: EP

Kind code of ref document: A1