WO2024060316A1 - 内建自测试方法和设备 - Google Patents

内建自测试方法和设备 Download PDF

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Publication number
WO2024060316A1
WO2024060316A1 PCT/CN2022/123947 CN2022123947W WO2024060316A1 WO 2024060316 A1 WO2024060316 A1 WO 2024060316A1 CN 2022123947 W CN2022123947 W CN 2022123947W WO 2024060316 A1 WO2024060316 A1 WO 2024060316A1
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data
address
read
compressed
test
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PCT/CN2022/123947
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English (en)
French (fr)
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孙圆圆
王佳
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长鑫存储技术有限公司
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Definitions

  • the present disclosure relates to, but is not limited to, a built-in self-test method and device.
  • Semiconductor memory is the most important component of electronic equipment. Memory plays a vital role in the performance and stability of electronic equipment. Therefore, it is necessary to ensure the reliability of the memory used in these electronic devices, and memory testing is necessary.
  • the present disclosure provides a built-in self-test method.
  • the memory includes multiple storage areas.
  • the method includes:
  • Mask at least one bit of the first initial address to activate multiple storage areas, and record the addresses of the activated multiple storage areas as the first compressed write address
  • Mask at least one bit of the second initial address to activate multiple storage areas, and record the addresses of the activated multiple storage areas as the first compressed read address
  • test data corresponding to multiple storage areas is read according to the first compressed read address, and the test data is compressed during the reading process, so that the compressed data read out by the memory
  • the number of bits is equal to the number of uncompressed data read out from one of the storage areas
  • masking at least one bit of the first initial address specifically includes:
  • a compressed write instruction is obtained, and based on the compressed write instruction, at least one bit of the address itself in the first initial address and its inverted signal are forced to the same specific value to activate corresponding multiple storage areas.
  • masking at least one bit of the second initial address specifically includes:
  • a compressed read instruction is obtained, and based on the compressed read instruction, at least one address bit in the second initial address and its inverted signal are forced to be the same specific value to activate the corresponding plurality of storage areas.
  • each storage area includes multiple storage arrays
  • Writing test data into the corresponding storage area according to the first compressed write address specifically includes:
  • the current word line is turned on according to the current row address, and the current column selection line in the memory array on the current word line is turned on to write test data into the target value of memory cells. , update the next column selection line until test data is written to all memory cells on the current word line.
  • each storage area includes multiple storage arrays
  • Test data corresponding to multiple storage areas according to the first compressed read address specifically including:
  • the current word line is turned on according to the current row address, and the current column selection line in the memory array on the current word line is turned on to read test data into the target value of memory cells. , update the next column selection line until the test data is read out from all memory cells on the current word line.
  • the number of storage areas that are activated simultaneously when writing data is greater than the number of storage areas that are activated simultaneously when reading data.
  • the method before calculating the ideal readout data according to the test data and the compression processing rules, comparing the readout data of the memory and the ideal readout data, and obtaining the test result, the method further includes: include:
  • Mask at least one bit of the third initial address to activate multiple storage areas, and record the addresses of the activated multiple storage areas as second compressed write addresses;
  • Mask at least one bit of the fourth initial address to activate multiple storage areas, and record the addresses of the activated multiple storage areas as second compressed read addresses;
  • test data corresponding to multiple storage areas is read according to the second compressed read address, and the test data is compressed during the reading process, so that the compressed data read out by the memory
  • the number of bits is equal to the number of uncompressed data bits read from one of the storage areas.
  • the memory includes multiple storage areas.
  • the device includes:
  • a writing module used to obtain the first initial address of the storage area to be written data; mask at least one address of the first initial address to activate multiple storage areas, remembering the multiple activated ones
  • the address of the storage area is a first compressed write address; write test data into the corresponding storage area according to the first compressed write address;
  • the reading module is used to obtain the second initial address of the storage area of the data to be read; mask at least one address of the second initial address to activate multiple storage areas, and record the activated ones.
  • the addresses of multiple storage areas are first compressed read addresses; the test data corresponding to multiple storage areas are read according to the first compressed read address, and the test data is read during the readout process.
  • the data is compressed so that the number of compressed data bits read from the memory is equal to the number of uncompressed data bits read from the storage area;
  • An output module is used to calculate ideal readout data according to the test data and preset compression processing rules, compare the readout data of the memory and the ideal readout data, and obtain test results.
  • the write module is configured to obtain a compressed write instruction, and based on the compressed write instruction, force at least one bit of the address itself in the first initial address and its inverted signal to the same specific value, so as to Activate corresponding multiple storage areas.
  • Another embodiment of the present disclosure provides a computer-readable storage medium.
  • Computer-executable instructions are stored in the computer-readable storage medium. When executed by a processor, the computer-executable instructions are used to implement the content involved in the above embodiments. Build self-test methods.
  • the built-in self-test method and device provided by the present disclosure mask at least one address of the first initial address to activate multiple storage areas, and write test data into the activated storage areas to achieve data write compression and shorten the time Data writing time.
  • Mask at least one address of the second initial address to activate multiple storage areas, and read test data from the activated storage areas to achieve data read compression, shorten data read time, and perform readout of the test data. Compression processing to adapt to the number of data readout bits in the memory without changing the structure of the existing memory. By shortening the data writing time and data reading time, the test time can be shortened and the test efficiency can be improved.
  • Figure 1 is a schematic diagram of a memory
  • Figure 2 is a schematic diagram of a storage area in the memory shown in Figure 1;
  • Figure 3 is a flow chart of a built-in self-test method provided by an embodiment of the present disclosure
  • FIG4 is a flow chart of data writing in a built-in self-test method provided by another embodiment of the present disclosure.
  • Figure 5 is a flow chart of data readout in the built-in self-test method provided by yet another embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a built-in self-test device provided by yet another embodiment of the present disclosure.
  • Memory built in self-test is a testing method.
  • the test vector is automatically generated by the built-in memory test logic, rather than generated by an external test machine.
  • the Mbist controller When the Mbist controller receives the instruction to start the test, it will control the memory test module to work.
  • the test vector of the test module is automatically generated internally, and the expected output value of the memory is also calculated.
  • the memory When the memory receives the test vector, it performs read and write operations at equal intervals, traverses all addresses in the memory, accesses all storage units, and finally reads out through the mode register, compares the memory read data with the expected output value of the memory, and records the wrong address to repair the error.
  • An embodiment of the present disclosure provides a built-in self-test method and device, which shortens test time and improves test efficiency by simultaneously reading and writing multiple storage areas and compressing reading and writing in each storage area.
  • a memory 100 includes a plurality of storage areas 110 , an Mbist controller 120 , an address bus 150 , an XOR gate circuit 130 and a DQ circuit 140 .
  • the Mbist controller 120 controls the test module (not shown) to perform the test.
  • the DQ circuit 140 is used to receive test data from the mode register (not shown), and write the test data into each storage area 110 through the address bus. After data is read from each storage area 110, it is output to the XOR gate circuit 130 through the address bus 150, compressed by the XOR gate circuit 130, and then output to another mode register.
  • a memory area 110 includes multiple memory arrays (MAT) 230.
  • Memory arrays in the same row share the same set of word lines 210.
  • Memory arrays in the same column share the same set of column select lines 220 and the same set of bit lines ( Figure not shown).
  • One column selection line 220 controls a unit number of bit lines to enable reading and writing data to a unit number of memory cells when a column selection line is turned on.
  • one embodiment of the present disclosure provides a built-in self-testing method.
  • the testing method includes the following steps:
  • the first initial address of the storage area of the data to be written is obtained.
  • the address of the storage area has 4 bits, is marked with BA ⁇ 3:0>, and the first initial address BA ⁇ 3:0> is 0000 obtained by parsing the test vector.
  • the first initial address includes multiple address bits, by masking at least one bit of the first initial address, and then activating multiple storage areas based on the masked address.
  • a compressed write instruction is obtained, and based on the compressed write instruction, at least one bit of the address itself and its inverted signal in the first initial address are forced to the same specific value to implement at least one bit of the first initial address. Shield to activate corresponding multiple storage areas.
  • a compressed write instruction is obtained, and based on the compressed write instruction, at least one high-bit address in the first initial address itself and its inverted signal are forced to the same specific value to activate corresponding multiple storage areas.
  • the first storage area BA0, the fifth storage area BA4, the ninth storage area BA8 and the 13th storage area BA12 are activated, thereby activating four storage areas simultaneously.
  • the inverted signal BA ⁇ 3>B of the address, the inverted signal BA ⁇ 2>B of the third address, and the inverted signal BA ⁇ 1>B of the second address are set to high level.
  • the first storage area BA0, the third storage area BA2, the fifth storage area BA4, the seventh storage area BA6, the ninth storage area BA8, and the 11th storage area are activated.
  • a storage area BA10, a 13th storage area BA12 and a 15th storage area BA14 enable 8 storage areas to be activated at the same time.
  • the addresses of the multiple activated storage areas are recorded as first compressed write addresses, and test data is written into the corresponding storage areas according to the first compressed write addresses.
  • the same test data is written into the corresponding storage area according to the first compressed write address.
  • the second initial address of the storage area of the data to be read is obtained.
  • the address of the storage area has 4 bits, is marked with BA ⁇ 3:0>, and the second initial address BA ⁇ 3:0> is 0000 obtained by parsing the test vector.
  • the second initial address includes multiple address bits, by masking at least one bit of the second initial address, and then activating multiple storage areas based on the masked address.
  • a compressed read instruction is obtained, and based on the compressed read instruction, at least one bit of the address itself and its inverted signal in the second initial address are forced to the same specific value to implement at least one bit of the second initial address. Shield to activate corresponding multiple storage areas.
  • a compressed read instruction is obtained, and based on the compressed read instruction, at least one high-bit address in the second initial address itself and its inverted signal are forced to the same specific value to activate corresponding multiple storage areas.
  • S104 Read test data corresponding to multiple storage areas according to the first compressed read address, and perform compression processing on the test data during the readout process, so that the number of compressed data bits read out from the memory is equal to one readout from the storage area. The number of bits of uncompressed data.
  • the addresses of the plurality of activated storage areas are recorded as first compressed read addresses, and the test data corresponding to the plurality of storage areas is read according to the first compressed read addresses.
  • the number of bits of uncompressed data read from one storage area is M bits, and when data is only read from one storage area, the number of bits of data read by the memory is M bits.
  • the preset compression processing rules are used to compress the number of read bits in each storage area to M/N bits, so that the memory
  • the number of bits of compressed data read out is equal to the number of bits of uncompressed data read out of a storage area.
  • the preset compression processing rule is that, for each storage array, select one data from the multiple test data read out by turning on the current column selection line of the storage array, group the selected data, and then group the grouped data. The data is XORed, and then the next data is selected from the multiple test data read out from each storage array until the compression of all test data read out from the storage array by opening the current column selection line is completed.
  • 16 storage arrays share a set of word lines.
  • a column selection line When a column selection line is turned on, data is read and written to 8 storage units.
  • the current column selection line in the storage array is opened to read out 8 test data, and 1 test data is selected from the 8 test data.
  • 16 test data can be selected. Divide the 16 test data into two groups. The 8 test data of the first 8 storage arrays are divided into one group. The 8 test data are XOR-processed and then output one bit. The 8 test data of the last 8 storage arrays are divided into two groups. For another group, XOR the 8 test data and output one bit to complete the compression of 16 test data.
  • the number of storage areas that are activated simultaneously when writing data is greater than the number of storage areas that are activated simultaneously when reading data. Reducing the number of storage areas that are activated at the same time when reading data can ensure the quality of the read data and improve the accuracy of the test.
  • S105 Calculate the ideal readout data according to the test data and the preset compression processing rules, compare the readout data of the memory and the ideal readout data, and obtain the test results.
  • the test data is processed using compression processing rules to output ideal read data.
  • the data read from the memory is compared with the ideal read data. If the data read from the memory is the same as the ideal read data, it indicates that the storage function of the tested storage area is normal. If at least one bit of the data read from the memory is different from the ideal read data, it indicates that the storage function of the tested storage area is faulty.
  • At least one bit of the first initial address is masked to activate multiple storage areas, and test data is written into the activated storage areas to achieve data writing compression and shorten data writing time.
  • Mask at least one address of the second initial address to activate multiple storage areas, and read test data from the activated storage areas to achieve data read compression, shorten data read time, and perform readout of the test data. Compression processing to adapt to the number of data readout bits in the memory without changing the structure of the existing memory. By shortening the data writing time and data reading time, the test time can be shortened and the test efficiency can be improved.
  • writing test data to the corresponding storage area according to the first compressed write address specifically includes:
  • the current row address is decoded, and the current word line is opened according to the decoding result.
  • next row address is updated, and the next word line is opened based on the next row address.
  • a storage area there are 16 storage arrays on each word line, and one column select line controls 8 bit lines. Turn on the current word line, turn on the first column select line in the first memory array, write test data to the 8 memory cells on the current word line, turn on the first column select line in the second memory array, Write test data to the 8 memory cells on the current word line, and so on, turn on the first column select line in the 16th memory array, and write test data to the 8 memory cells on the current word line. data, to write test data to the 128 memory cells on the current word line, completing a cycle. Update the next column select line and repeat the above steps until test data is written to all memory cells on the current word line.
  • the fast writing method when writing test data from each activated storage area, the fast writing method is used to write data.
  • reading test data corresponding to multiple storage areas according to the first compressed read address specifically includes:
  • the current row address is decoded, and the current word line is opened according to the decoding result.
  • M memory arrays on each word line. Select the current column selection line from each of the M memory arrays to open, and read out the test data from the target value memory cells on the current word line, completing a cycle.
  • the ideal readout data is calculated based on the test data and preset compression processing rules, and the test results are obtained by comparing the data readout in one cycle with the ideal readout data.
  • next column selection line select the next column selection line from each of the M memory arrays to open, and read out the test data from the target value memory cells on the current word line, complete another cycle, and compare The data read out in one cycle and the ideal readout data are used to obtain the test results. Repeat the above steps until the test data is read from all memory cells on the current word line.
  • next row address is updated, and the next word line is opened based on the next row address.
  • the fast writing method when reading the test data from each activated storage area, the fast writing method is used to read the data. Each time a column selection line is turned on, the data is read from multiple storage units, shortening the data. Read out the time.
  • An embodiment of the present disclosure provides a built-in self-testing method.
  • the testing method includes the following steps:
  • S401 Repeat the execution to write test data to multiple storage areas at the same time to complete the data writing to the memory.
  • S403 Repeat the execution to read the test data from multiple storage areas at the same time to complete writing the data in the memory.
  • the first initial address BA ⁇ 3:0> is 0000
  • the fourth address BA ⁇ 3> and the third address BA ⁇ 2> in the first initial address BA ⁇ 3:0> are set to high level
  • the inverted signal BA ⁇ 3>B of the fourth address and the inverted signal BA ⁇ 2>B of the third address are set to high level.
  • the activated first storage area BA0, the fifth storage area BA4, the ninth storage area BA8 and the 13th storage area BA12 are recorded as the first compressed write address.
  • the first compressed write address is written to the first compressed write address.
  • Test data is written in the storage area BA0, the fifth storage area BA4, the ninth storage area BA8, and the 13th storage area BA12.
  • the next initial address is marked as the third initial address. At least one bit of the third initial address is masked to activate multiple storage areas. The plurality of activated storage areas are recorded as second compressed write addresses, and test data is written into the corresponding storage areas according to the second compressed write addresses.
  • the third initial address BA ⁇ 3:0> is 0001, set the fourth address BA ⁇ 3> and the third address BA ⁇ 2> in the third initial address BA ⁇ 3:0> to high level,
  • the inverted signal BA ⁇ 3>B of the fourth address and the inverted signal BA ⁇ 2>B of the third address are set to high level.
  • the second initial address BA ⁇ 3:0> is 0000
  • the inverted signal BA of the fourth address ⁇ 3>B is set to high level.
  • the activated first storage area BA0 and the ninth storage area BA8 are recorded as the first compressed read address, and the test is read from the first storage area BA0 and the ninth storage area BA8 according to the first compressed read address. data.
  • the current word line is turned on according to the current row address, and the current column selection in the storage array on the current word line is turned on. line to read the test data into the target value memory cells on the current word line, and compress the test data read out from the target value memory cells.
  • the read data is 128 bits.
  • the 128-bit data read out from the first storage area BA0 is compressed to 64 bits according to the preset compression processing rule
  • the 128-bit data read out from the ninth storage area BA8 is compressed to 64 bits according to the preset compression processing rule, so that the number of bits of compressed data read out from the memory is 128 bits.
  • the preset compression processing rules include XOR logical operations.
  • the row address is updated, and the test data of the memory cell on the next word line is read. If there is no data read out of all memory cells on the current word line, the column address is updated, that is, the next column selection line is updated, and the test data of the memory cell on the bit line controlled by the next column selection line is read.
  • S606. Determine whether data reading from all storage areas has been completed. If not, proceed to S607. If yes, end the process.
  • the next initial address is marked as a fourth initial address, and at least one bit of the fourth initial address is masked to activate multiple storage areas.
  • the addresses of the multiple activated storage areas are recorded as second compressed read addresses.
  • the test data corresponding to multiple storage areas is read according to the second compressed read address, and the test data is compressed during the reading process, so that the number of compressed data bits read out from the memory is equal to the number of unused bits read out from one storage area. The number of bits to compress the data.
  • an embodiment of the present disclosure provides a built-in self-test device 700.
  • the memory includes multiple storage areas.
  • the built-in self-test device 700 includes:
  • the writing module 701 is used to obtain the first initial address of the storage area to be written data; mask at least one address of the first initial address to activate multiple storage areas, and record the number of activated multiple storage areas.
  • the address is the first compressed write address; write test data into the corresponding storage area according to the first compressed write address;
  • the readout module 702 is used to obtain the second initial address of the storage area of the data to be read out; mask at least one address of the second initial address to activate multiple storage areas, and record the number of activated multiple storage areas.
  • the address is the first compressed read address; the test data corresponding to the multiple storage areas is read according to the first compressed read address, and the test data is compressed during the readout process, so that the number of compressed data read out from the memory is Equal to the number of bits of uncompressed data read from a storage area;
  • the output module 703 is used to calculate the ideal readout data according to the test data and the preset compression processing rules, compare the readout data of the memory and the ideal readout data, and obtain the test results.
  • the writing module 701 is specifically used to:
  • a compressed write instruction is obtained, and based on the compressed write instruction, at least one bit of the address itself in the first initial address and its inverted signal are forced to the same specific value to activate corresponding multiple storage areas.
  • the readout module 702 is specifically used to:
  • a compressed read instruction is obtained, and based on the compressed read instruction, at least one bit of the address itself in the second initial address and its inverted signal are forced to the same specific value to activate corresponding multiple storage areas.
  • each storage area includes multiple storage arrays, and the writing module 701 is specifically used to:
  • the current word line is turned on according to the current row address, and the current column selection line in the memory array on the current word line is turned on to write test data into the target value of memory cells. , update the next column selection line until test data is written to all memory cells on the current word line.
  • each storage area includes multiple storage arrays, and the readout module 702 is specifically used to:
  • the current word line is turned on according to the current row address, and the current column selection line in the memory array on the current word line is turned on to read test data into the target value of memory cells. , update the next column selection line until the test data is read out from all memory cells on the current word line.
  • the number of storage areas that are activated simultaneously when writing data is greater than the number of storage areas that are activated simultaneously when reading data.
  • the writing module 701 is specifically used to:
  • Mask at least one bit of the third initial address to activate multiple storage areas, and record the addresses of the activated multiple storage areas as the second compressed write address;
  • the readout module 702 is specifically used for:
  • Mask at least one bit of the fourth initial address to activate multiple storage areas, and record the addresses of the activated multiple storage areas as the second compressed read address;
  • test data corresponding to multiple storage areas is read according to the second compressed read address, and the test data is compressed during the reading process, so that the number of compressed data bits read out from the memory is equal to the number of unused bits read out from one storage area.
  • the number of bits to compress the data is not limited to the number of unused bits read out from one storage area.
  • Embodiments of the present disclosure also provide a computer-readable storage medium.
  • Computer instructions are stored in the computer-readable storage medium. When the processor executes the computer instructions, each step in the method in the above embodiment is implemented.
  • Embodiments of the present disclosure also provide a computer program product, which includes computer instructions. When the computer instructions are executed by a processor, each step of the method in the above embodiments is implemented.

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Abstract

一种内建自测试方法和设备，内建自测试方法包括：获取待写入数据的存储区域(110)的第一初始地址，对第一初始地址的至少一位地址进行屏蔽，以激活多个存储区域(S101, S501)；根据第一压缩写地址向对应的存储区域(110)中写入测试数据(S102, S502)；获取待读出数据的存储区域(110)的第二初始地址，对第二初始地址的至少一位地址进行屏蔽，以激活多个存储区域(110)(S103, S601)；根据第一压缩读地址对多个存储区域(110)对应的测试数据进行读取，且在读出过程中对测试数据进行压缩处理(S104, S602)；根据测试数据和预设压缩处理规则计算理想读出数据，比较存储器的读出数据和理想读出数据，获得测试结果(S105)。内建自测试方法和设备能提高测试效率。

Description

内建自测试方法和设备
本申请要求于2022年09月19日提交中国专利局、申请号为202211137932.1、申请名称为“内建自测试方法和设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及但不限于一种内建自测试方法和设备。
背景技术
半导体存储器是电子设备最重要的组成部分，存储器对于电子设备的性能和稳定性都起着至关重要的作用。所以，必须要保证这些电子设备中使用的存储器的可靠性，针对存储器的测试很有必要。
然而，现有的测试方法中，需要访问不同的地址，并对不同的地址都需要执行读写操作，会导致测试的时间比较长，测试效率降低。
发明内容
本公开提供一种内建自测试方法，存储器包括多个存储区域，所述方法包括：
获取待写入数据的存储区域的第一初始地址；
对所述第一初始地址的至少一位地址进行屏蔽，以激活多个所述存储区域，记被激活的多个所述存储区域的地址为第一压缩写地址；
根据所述第一压缩写地址向对应的所述存储区域中写入测试数据；
获取待读出数据的所述存储区域的第二初始地址；
对所述第二初始地址的至少一位地址进行屏蔽，以激活多个所述存储区域，记被激活的多个所述存储区域的地址为第一压缩读地址；
根据所述第一压缩读地址对多个所述存储区域对应的所述测试数据进行读取，且在读出过程中对所述测试数据进行压缩处理，以使所述存储器读出的压缩数据位数等于一个所述存储区域读出的未压缩数据的位数；
根据所述测试数据和预设压缩处理规则计算理想读出数据，比较所述存储器的读出数据和所述理想读出数据，获得测试结果。
在一些实施例中，对所述第一初始地址的至少一位地址进行屏蔽，具 体包括：
获取压缩写指令，并基于所述压缩写指令将所述第一初始地址中至少一位地址本身及其反相信号强制为相同的特定值，以激活对应的多个所述存储区域。
在一些实施例中，对所述第二初始地址的至少一位地址进行屏蔽，具体包括：
获取压缩读指令，并基于所述压缩读指令将所述第二初始地址中至少一位地址本身及其反相信号强制为相同的特定值，以激活对应的多个所述存储区域。
在一些实施例中，每个存储区域包括多个存储阵列；
根据第一压缩写地址向对应的存储区域中写入测试数据，具体包括：
在每个第一压缩写地址对应的存储区域内，根据当前行地址开启当前字线，开启当前字线上的存储阵列内的当前列选择线，以向目标值个存储单元中写入测试数据，更新下一列选择线，直至向当前字线上所有存储单元写入测试数据。
在一些实施例中，每个存储区域包括多个存储阵列；
根据第一压缩读地址对多个存储区域对应的测试数据进行读取，具体包括：
在每个第一压缩读地址对应的存储区域内，根据当前行地址开启当前字线，开启当前字线上的存储阵列内的当前列选择线，以向目标值个存储单元中读出测试数据，更新下一列选择线，直至从当前字线上所有存储单元读出测试数据。
在一些实施例中，在写入数据时同时被激活的存储区域的数量大于在读出数据时同时被激活的存储区域的数量。
在一些实施例中，在根据所述测试数据和所述压缩处理的规则计算理想读出数据，比较所述存储器的读出数据和所述理想读出数据，获得测试结果之前，所述方法还包括：
获取待写入数据的存储区域的第三初始地址；
对所述第三初始地址的至少一位地址进行屏蔽，以激活多个所述存储区域，记被激活的多个所述存储区域的地址为第二压缩写地址；
根据所述第二压缩写地址向对应的所述存储区域中写入测试数据；
获取待读出数据的所述存储区域的第四初始地址；
对所述第四初始地址的至少一位地址进行屏蔽，以激活多个所述存储区域，记被激活的多个所述存储区域的地址为第二压缩读地址；
根据所述第二压缩读地址对多个所述存储区域对应的所述测试数据进行读取，且在读出过程中对所述测试数据进行压缩处理，以使所述存储器读出的压缩数据位数等于一个所述存储区域读出的未压缩数据的位数。
本公开另一实施例提供一种内建自测试装置，存储器包括多个存储区域，所述装置包括：
写入模块，用于获取待写入数据的存储区域的第一初始地址；对所述第一初始地址的至少一位地址进行屏蔽，以激活多个所述存储区域，记被激活的多个所述存储区域的地址为第一压缩写地址；根据所述第一压缩写地址向对应的所述存储区域中写入测试数据；
读出模块，用于获取待读出数据的所述存储区域的第二初始地址；对所述第二初始地址的至少一位地址进行屏蔽，以激活多个所述存储区域，记被激活的多个所述存储区域的地址为第一压缩读地址；根据所述第一压缩读地址对多个所述存储区域对应的所述测试数据进行读取，且在读出过程中对所述测试数据进行压缩处理，以使所述存储器读出的压缩数据位数等于一个所述存储区域读出的未压缩数据的位数；
输出模块，用于根据所述测试数据和预设压缩处理规则计算理想读出数据，比较所述存储器的读出数据和所述理想读出数据，获得测试结果。
在一些实施例中，写入模块，用于获取压缩写指令，并基于所述压缩写指令将所述第一初始地址中至少一位地址本身及其反相信号强制为相同的特定值，以激活对应的多个所述存储区域。
本公开另一实施例提供一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机执行指令，所述计算机执行指令被处理器执行时用于实现上述实施例中所涉及的内建自测试方法。
本公开提供的内建自测试方法和设备，对第一初始地址的至少一位地址进行屏蔽，以激活多个存储区域，并向激活的存储区域中写入测试数据，实现数据写压缩，缩短数据写入时间。对第二初始地址的至少一位地址进 行屏蔽，以激活多个存储区域，并从激活的存储区域中读出测试数据，实现数据读压缩，缩短数据读出时间，并对读出测试数据进行压缩处理，以适应存储器的数据读出位数，无需改变现有存储器的结构。通过缩短数据写入时间和数据读出时间，可以缩短测试时间，提升测试效率。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。
图1为一种存储器的示意图；
图2为图1所示存储器中一个存储区的示意图；
图3为本公开一实施例提供的内建自测试方法的流程图；
图4为本公开另一实施例提供的内建自测试方法中数据写入的流程图；
图5为本公开又一实施例提供的内建自测试方法中数据读出的流程图；
图6为本公开又一实施例提供的内建自测试装置的示意图。
通过上述附图，已示出本公开明确的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本公开构思的范围，而是通过参考特定实施例为本领域技术人员说明本公开的概念。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置和方法的例子。
存储器内建自测试(Memory built in self-test，简称：Mbist)作为一种测试方法，测试向量是由内建的存储器测试逻辑自动产生，而并非由外部测试机台生成。
当Mbist的控制器接收到开始测试的指令后，会控制存储器的测试模块工作，测试模块的测试向量是由内部自动生成，同时也会计算出存储器的输出期待值。存储器接收到测试向量时，以等间隔的执行读写操作，遍历到存储器里所有的地址，访问所有存储单元，最后通过模式寄存器读出， 比较存储器读出数据和存储器的输出期待值，并记录错误的地址，进而修复错误。
由于Mbist需要访问不同的地址，并对不同的地址都需要执行读写操作，会导致测试的时间比较长，测试效率降低。
本公开一实施例提供一种内建自测试方法和设备，通过同时对多个存储区域进行读写以及对每个存储区域内进行压缩读写，实现缩短测试时间，提高测试效率。
如图1所示，一种存储器100包括多个存储区域110、Mbist控制器120、地址总线150、异或门电路130以及DQ电路140。Mbist控制器120接收开始测试的指令后，控制测试模块(图未示出)进行测试。
DQ电路140用于接收模式寄存器(图未示出)测试数据，并将测试数据通过地址总线写入各个存储区域110内。在从各个存储区域110读出数据，经过地址总线150输出到异或门电路130，经过异或门电路130压缩后输出到另一模式寄存器。
如图2所示，一个存储区域110包括多个存储阵列(MAT)230，同一行的存储阵列共用同一组字线210，同一列的存储阵列共用同一组列选择线220和同一组位线(图未示出)。一个列选择线220控制单位数量个位线，实现在一个列选线开启时向单位数量个存储单元中读写数据。
在一些实施例中，一个列选线开启时向8个存储单元中读写数据。
如图3所示，本公开一实施例提供一种内建自测试方法，该测试方法包括如下步骤：
S101、获取待写入数据的存储区域的第一初始地址，对第一初始地址的至少一位地址进行屏蔽，以激活多个存储区域。
其中，通过解析测试向量，获得待写入数据的存储区域的第一初始地址。例如：存储区域的地址有4位，使用BA<3:0>标记，通过解析测试向量获得第一初始地址BA<3:0>为0000。
在一些实施例中，第一初始地址包括多个地址位，通过对第一初始地址的至少一位地址进行屏蔽，再基于屏蔽后的地址激活多个存储区域。
在一些实施例中，获取压缩写指令，并基于压缩写指令将第一初始地址中至少一位地址本身及其反相信号强制为相同的特定值，实现对第一初 始地址的至少一位地址进行屏蔽，以激活对应的多个存储区域。
在一些实施例中，获取压缩写指令，并基于压缩写指令将第一初始地址中至少一位高位地址本身及其反相信号强制为相同的特定值，以激活对应的多个存储区域。
例如：将第一初始地址BA<3:0>中第四位地址BA<3>设置为高电平，第四位地址的反相信号BA<3>B设置为高电平。通过对强制后的第一初始地址进行解码，激活第1个存储区域BA0以及第9个存储区域BA8，实现同时激活两个存储区域。
又例如：将第一初始地址BA<3:0>中第四位地址BA<3>和第三位地址BA<2>设置为高电平，第四位地址的反相信号BA<3>B和第三位地址的反相信号BA<2>B设置为高电平。通过对强制后的第一初始地址进行解码，激活第1个存储区域BA0、第5个存储区域BA4、第9个存储区域BA8以及第13个存储区域BA12，实现同时激活四个存储区域。
又例如：将第一初始地址BA<3:0>中第四位地址BA<3>、第三位地址BA<2>和第二位地址BA<1>设置为高电平，第四位地址的反相信号BA<3>B、第三位地址的反相信号BA<2>B和第二位地址的反相信号BA<1>B设置为高电平。通过对强制后的第一初始地址进行解码，激活第1个存储区域BA0、第3个存储区域BA2、第5个存储区域BA4、第7个存储区域BA6、第9个存储区域BA8、第11个存储区域BA10、第13个存储区域BA12以及第15个存储区域BA14，实现同时激活8个存储区域。
S102、根据第一压缩写地址向对应的存储区域中写入测试数据。
其中，记被激活的多个存储区域的地址为第一压缩写地址，根据第一压缩写地址向对应的存储区域中写入测试数据。
在一些实施例中，根据第一压缩写地址向对应的存储区域中写入相同的测试数据。
S103、获取待读出数据的存储区域的第二初始地址，对第二初始地址的至少一位地址进行屏蔽，以激活多个存储区域。
其中，通过解析测试向量，获得待读出数据的存储区域的第二初始地址。例如：存储区域的地址有4位，使用BA<3:0>标记，通过对解析测试向量获得第二初始地址BA<3:0>为0000。
在一些实施例中，第二初始地址包括多个地址位，通过对第二初始地址的至少一位地址进行屏蔽，再基于屏蔽后的地址激活多个存储区域。
在一些实施例中，获取压缩读指令，并基于压缩读指令将第二初始地址中至少一位地址本身及其反相信号强制为相同的特定值，实现对第二初始地址的至少一位地址进行屏蔽，以激活对应的多个存储区域。
在一些实施例中，获取压缩读指令，并基于压缩读指令将第二初始地址中至少一位高位地址本身及其反相信号强制为相同的特定值，以激活对应的多个存储区域。
S104、根据第一压缩读地址对多个存储区域对应的测试数据进行读取，且在读出过程中对测试数据进行压缩处理，以使存储器读出的压缩数据位数等于一个存储区域读出的未压缩数据的位数。
其中，记被激活的多个存储区域的地址为第一压缩读地址，根据第一压缩读地址对多个存储区域对应的测试数据进行读取。
在一些实施例中，从一个存储区域读出的未压缩数据的位数为M位，且仅从一个存储区域中读出数据时，存储器读出数据的位数为M位。
若同时从N个存储区域中读出数据，在读出过程中对测试数据进行压缩处理时，使用预设压缩处理规则将每个存储区域中读出位数压缩至M/N位，使存储器读出的压缩数据位数等于一个存储区域读出的未压缩数据的位数。
在一些实施例中，预设压缩处理规则为，针对每个存储阵列，从存储阵列开启当前列选择线读出的多个测试数据中选择一个数据，将选择的数据进行分组后，对分组的数据进行异或处理，再从每个存储阵列中读出的多个测试数据中选择下一个数据，直至完成从存储阵列开启当前列选择线读出的所有测试数据的压缩。
例如：一个存储区域中，16个存储阵列共用一组字线，一个列选线开启时向8个存储单元中读写数据。针对16个存储阵列中每个存储阵列，存储阵列中开启当前列选择线读出8个测试数据，从8个测试数据中选择1个测试数据。在16个存储阵列中，可以选择16个测试数据。将16个测试数据分成两组，前8个存储阵列的8个测试数据分为一组，并将8个测试数据进行异或处理后输出一位，后8个存储阵列的8个测试数据分为另 一组，并将8个测试数据进行异或处理后输出一位，完成16个测试数据的压缩。
再从每个存储阵列中读出的8个测试数据中选择下一个测试数据，按照上述同样的规则进行处理，直至完成16×8个测试数据的压缩，最终输出16个测试数据。
在一些实施例中，在写入数据时同时被激活的存储区域的数量大于在读出数据时同时被激活的存储区域的数量。减少在读出数据时同时被激活的存储区域的数量，可以保证读出数据的质量，提高测试的准确性。
S105、根据测试数据和预设压缩处理规则计算理想读出数据，比较存储器的读出数据和理想读出数据，获得测试结果。
其中，使用压缩处理规则对测试数据进行处理输出理想读出数据。将从存储器中读出数据和理想读出数据进行比较，若从存储器中读出数据和理想读出数据相同，则表征所测试的存储区域的存储功能正常。若从存储器中读出数据和理想读出数据至少有一位不相同，则表征所测试的存储区域的存储功能有故障。
在上述技术方案中，对第一初始地址的至少一位地址进行屏蔽，以激活多个存储区域，并向激活的存储区域中写入测试数据，实现数据写压缩，缩短数据写入时间。对第二初始地址的至少一位地址进行屏蔽，以激活多个存储区域，并从激活的存储区域中读出测试数据，实现数据读压缩，缩短数据读出时间，并对读出测试数据进行压缩处理，以适应存储器的数据读出位数，无需改变现有存储器的结构。通过缩短数据写入时间和数据读出时间，可以缩短测试时间，提升测试效率。
在一些实施例中，根据第一压缩写地址向对应的存储区域中写入测试数据，具体包括：
S201、在每个第一压缩写地址对应的存储区域内，根据当前行地址开启当前字线，开启当前字线上的存储阵列内的当前列选择线，以向目标值个存储单元中写入测试数据，更新下一列选择线，直至向当前字线上所有存储单元写入测试数据。
其中，在每个第一压缩写地址对应的存储区域内，对当前行地址进行译码，并根据译码结果开启当前字线。每个字线上有M个存储阵列。从 M个存储阵列中每个存储阵列中选择当前列选择线开启，实现向在当前字线上的目标值个存储单元中写入测试数据，完成一次循环。更新下一列选择线，从M个存储阵列中每个存储阵列中选择下一列选择线开启，实现向在下一列选择线上的目标值个存储单元中写入测试数据，再完成一次循环。重复上述步骤，直至向当前字线上所有存储单元写入测试数据。
在完成当前字线上所有存储单元中写入测试数据，更新下一行地址，根据下一行地址开启下一字线。开启当前字线上的存储阵列内的当前列选择线，以向在下一字线上的目标值个存储单元中写入测试数据，更新下一列选择线，直至向下一字线上所有存储单元写入测试数据。
例如：在一个存储区域中，每个字线上有16个存储阵列，一根列选择线控制8根位线。开启当前字线，开启第1个存储阵列中第一根列选择线，向在当前字线上的8个存储单元中写入测试数据，开启第2个存储阵列中第一根列选择线，向在当前字线上的8个存储单元中写入测试数据，以此类推，开启第16个存储阵列中第一根列选择线，向在当前字线上的8个存储单元中写入测试数据，实现向在当前字线上的128个存储单元中写入测试数据，完成一次循环。更新下一根列选择线，重复上述步骤，直至向当前字线上所有存储单元写入测试数据。
在上述技术方案中，在从每个被激活的存储区域中写入测试数据时，采用快速写方式写入，每次开启一根列选择线时向多个存储单元中写入数据，缩短数据写入时间。
在一些实施例中，根据第一压缩读地址对多个存储区域对应的测试数据进行读取，具体包括：
S301、在每个第一压缩读地址对应的存储区域内，根据当前行地址开启当前字线，开启当前字线上的存储阵列内的当前列选择线，以向在当前字线上的目标值个存储单元中读出测试数据，更新下一列选择线，直至从当前字线上所有存储单元读出测试数据。
其中，在每个第一压缩读地址对应的存储区域内，对当前行地址进行译码，并根据译码结果开启当前字线。每个字线上有M个存储阵列。从M个存储阵列中每个存储阵列中选择当前列选择线开启，实现从在当前字线上的目标值个存储单元中读出测试数据，完成一次循环。
在完成一次循环后，根据测试数据和预设压缩处理规则计算理想读出数据，比较一次循环读出的数据和理想读出数据，获得测试结果。
再更新下一列选择线，从M个存储阵列中每个存储阵列中选择下一列选择线开启，实现从在当前字线上的目标值个存储单元中读出测试数据，再完成一次循环，比较一次循环读出的数据和理想读出数据，获得测试结果。重复上述步骤，直至从当前字线上所有存储单元读出测试数据。
在完成当前字线上所有存储单元中读出测试数据，更新下一行地址，根据下一行地址开启下一字线。开启当前字线上的存储阵列内的当前列选择线，以从在下一字线上的目标值个存储单元中读出测试数据，更新下一列选择线，直至从下一字线上所有存储单元读出测试数据。
在上述技术方案中，在从每个被激活的存储区域中读出测试数据时，采用快速写方式读出，每次开启一根列选择线时从多个存储单元中读出数据，缩短数据读出时间。
本公开一实施例提供一种内建自测试方法，该测试方法包括如下步骤：
S401、重复执行同时向多个存储区域中写入测试数据，完成对存储器的数据写入。
S402、刷新各个存储区域中数据。
S403、重复执行同时从多个存储区域中读出测试数据，完成对存储器中数据写入。
S404、将读出的测试数据和写入的测试数据进行比较，获得测试结果。
其中，如图4所示，在S401中，具体包括如下子步骤：
S501、获取待写入数据的存储区域的第一初始地址，对第一初始地址的至少一位地址进行屏蔽，以激活多个存储区域。
其中，第一初始地址BA<3:0>为0000，将第一初始地址BA<3:0>中第四位地址BA<3>和第三位地址BA<2>设置为高电平，第四位地址的反相信号BA<3>B和第三位地址的反相信号BA<2>B设置为高电平。通过强制后的第一初始地址进行解码，激活第1个存储区域BA0、第5个存储区域BA4、第9个存储区域BA8以及第13个存储区域BA12，实现同时激活四个存储区域。
S502、根据第一压缩写地址向对应的存储区域中写入测试数据。
其中，记被激活的第1个存储区域BA0、第5个存储区域BA4、第9个存储区域BA8以及第13个存储区域BA12为第一压缩写地址，根据第一压缩写地址向第1个存储区域BA0、第5个存储区域BA4、第9个存储区域BA8以及第13个存储区域BA12中写入测试数据。
S503、判断是否完成所有存储区域的数据写入，若是，进入S504，否则，进入S505。
S504、刷新各个存储区域中数据。
S505、获取下一初始地址，并返回S501。
在一些实施例中，将下一初始地址标记为第三初始地址。对第三初始地址的至少一位地址进行屏蔽，以激活多个存储区域。记激活的多个存储区域为第二压缩写地址，根据第二压缩写地址向对应的存储区域中写入测试数据。
例如：第三初始地址BA<3:0>为0001，将第三初始地址BA<3:0>中第四位地址BA<3>和第三位地址BA<2>设置为高电平，第四位地址的反相信号BA<3>B和第三位地址的反相信号BA<2>B设置为高电平。通过强制后的第三初始地址进行解码，激活第2个存储区域BA1、第6个存储区域BA5、第10个存储区域BA9以及第14个存储区域BA13，实现同时激活四个存储区域。
记被激活的第2个存储区域BA1、第6个存储区域BA5、第10个存储区域BA9以及第14个存储区域BA13为第二压缩写地址，根据第二压缩写地址向第2个存储区域BA1、第6个存储区域BA5、第10个存储区域BA9以及第14个存储区域BA13。
其中，如图5所示，在S403中，具体包括如下子步骤：
S601、获取待读出数据的存储区域的第二初始地址，对第二初始地址的至少一位地址进行屏蔽，以激活多个存储区域。
其中，第二初始地址BA<3:0>为0000，将第二初始地址BA<3:0>中第四位地址BA<3>设置为高电平，第四位地址的反相信号BA<3>B设置为高电平。通过强制后的第一初始地址进行解码，激活第1个存储区域BA0以及第9个存储区域BA8，实现同时激活两个存储区域。
S602、根据第一压缩读地址对多个存储区域对应的测试数据进行读取， 且在读出过程中对测试数据进行压缩处理，以使存储器读出的压缩数据位数等于一个存储区域读出的未压缩数据的位数。
其中，记被激活的第1个存储区域BA0以及第9个存储区域BA8为第一压缩读地址，根据第一压缩读地址从第1个存储区域BA0以及第9个存储区域BA8中读出测试数据。
在一些实施例中，在第一压缩读地址从第1个存储区域BA0以及第9个存储区域BA8中，根据当前行地址开启当前字线，开启当前字线上的存储阵列内的当前列选择线，以向在当前字线上的目标值个存储单元中读出测试数据，并对目标值个存储单元读出的测试数据进行压缩处理。
在对一个存储区域中读出数据未压缩时，读出数据为128位。对从第1个存储区域BA0中读出的128位数据按照预设压缩处理规则进行压缩至64位，对从第9个存储区域BA8中读出的128位数据按照预设压缩处理规则进行压缩至64位，使存储器读出的压缩数据位数为128位。
在一些实施例中，预设压缩处理规则包含异或逻辑运算。
S603、在每次从存储区域中读出数据后，将读出的测试数据和写入的测试数据进行比较，获得测试结果。
S604、判断是否完成第一压缩读地址对多个存储区域对应的测试数据进行读取，若否，进入S605，若是，进入S606。
S605、更新行地址或者列地址后，返回S602。
其中，若完成当前字线上所有存储单元的数据读出，更新行地址，读取下一个字线上存储单元的测试数据。若没有当前字线上所有存储单元的数据读出，更新列地址，也就是更新下一列选择线，读取下一列选择线控制的位线上存储单元的测试数据。
S606、判断是否完成所有存储区域的数据读出，若否，进入S607，若是，结束流程。
S607、获取下一初始地址，并返回S601。
在一些实施例中，将下一初始地址标记为第四初始地址，对第四初始地址的至少一位地址进行屏蔽，以激活多个存储区域。其中，记被激活的多个存储区域的地址为第二压缩读地址。根据第二压缩读地址对多个存储区域对应的测试数据进行读取，且在读出过程中对测试数据进行压缩处理， 以使存储器读出的压缩数据位数等于一个存储区域读出的未压缩数据的位数。
如图6所示，本公开一实施例提供一种内建自测试装置700，存储器包括多个存储区域，内建自测试装置700包括：
写入模块701，用于获取待写入数据的存储区域的第一初始地址；对第一初始地址的至少一位地址进行屏蔽，以激活多个存储区域，记被激活的多个存储区域的地址为第一压缩写地址；根据第一压缩写地址向对应的存储区域中写入测试数据；
读出模块702，用于获取待读出数据的存储区域的第二初始地址；对第二初始地址的至少一位地址进行屏蔽，以激活多个存储区域，记被激活的多个存储区域的地址为第一压缩读地址；根据第一压缩读地址对多个存储区域对应的测试数据进行读取，且在读出过程中对测试数据进行压缩处理，以使存储器读出的压缩数据位数等于一个存储区域读出的未压缩数据的位数；
输出模块703，用于根据测试数据和预设压缩处理规则计算理想读出数据，比较存储器的读出数据和理想读出数据，获得测试结果。
在一些实施例中，写入模块701具体用于：
获取压缩写指令，并基于压缩写指令将第一初始地址中至少一位地址本身及其反相信号强制为相同的特定值，以激活对应的多个存储区域。
在一些实施例中，读出模块702具体用于：
获取压缩读指令，并基于压缩读指令将第二初始地址中至少一位地址本身及其反相信号强制为相同的特定值，以激活对应的多个存储区域。
在一些实施例中，每个存储区域包括多个存储阵列，写入模块701具体用于：
在每个第一压缩写地址对应的存储区域内，根据当前行地址开启当前字线，开启当前字线上的存储阵列内的当前列选择线，以向目标值个存储单元中写入测试数据，更新下一列选择线，直至向当前字线上所有存储单元写入测试数据。
在一些实施例中，每个存储区域包括多个存储阵列，读出模块702具体用于：
在每个第一压缩读地址对应的存储区域内，根据当前行地址开启当前字线，开启当前字线上的存储阵列内的当前列选择线，以向目标值个存储单元中读出测试数据，更新下一列选择线，直至从当前字线上所有存储单元读出测试数据。
在一些实施例中，在写入数据时同时被激活的存储区域的数量大于在读出数据时同时被激活的存储区域的数量。
在一些实施例中，写入模块701具体用于：
获取待写入数据的存储区域的第三初始地址；
对第三初始地址的至少一位地址进行屏蔽，以激活多个存储区域，记被激活的多个存储区域的地址为第二压缩写地址；
根据第二压缩写地址向对应的存储区域中写入测试数据；
读出模块702具体用于：
获取待读出数据的存储区域的第四初始地址；
对第四初始地址的至少一位地址进行屏蔽，以激活多个存储区域，记被激活的多个存储区域的地址为第二压缩读地址；
根据第二压缩读地址对多个存储区域对应的测试数据进行读取，且在读出过程中对测试数据进行压缩处理，以使存储器读出的压缩数据位数等于一个存储区域读出的未压缩数据的位数。
本公开实施例还提供一种计算机可读存储介质，计算机可读存储介质中存储有计算机指令，当处理器执行计算机指令时，实现上述实施例中方法中的各个步骤。
本公开实施例还提供一种计算机程序产品，包括计算机指令，该计算机指令被处理器执行时实现上述实施例中方法中的各个步骤。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求书指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精 确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求书来限制。

Claims (10)

  1. 一种内建自测试方法，存储器包括多个存储区域，所述方法包括：
    获取待写入数据的存储区域的第一初始地址；
    对所述第一初始地址的至少一位地址进行屏蔽，以激活多个所述存储区域，记被激活的多个所述存储区域的地址为第一压缩写地址；
    根据所述第一压缩写地址向对应的所述存储区域中写入测试数据；
    获取待读出数据的所述存储区域的第二初始地址；
    对所述第二初始地址的至少一位地址进行屏蔽，以激活多个所述存储区域，记被激活的多个所述存储区域的地址为第一压缩读地址；
    根据所述第一压缩读地址对多个所述存储区域对应的所述测试数据进行读取，且在读出过程中对所述测试数据进行压缩处理，以使所述存储器读出的压缩数据位数等于一个所述存储区域读出的未压缩数据的位数；
    根据所述测试数据和预设压缩处理规则计算理想读出数据，比较所述存储器的读出数据和所述理想读出数据，获得测试结果。
  2. 根据权利要求1所述的内建自测试方法，其中，对所述第一初始地址的至少一位地址进行屏蔽，具体包括：
    获取压缩写指令，并基于所述压缩写指令将所述第一初始地址中至少一位地址本身及其反相信号强制为相同的特定值，以激活对应的多个所述存储区域。
  3. 根据权利要求2所述的内建自测试方法，其中，对所述第二初始地址的至少一位地址进行屏蔽，具体包括：
    获取压缩读指令，并基于所述压缩读指令将所述第二初始地址中至少一位地址本身及其反相信号强制为相同的特定值，以激活对应的多个所述存储区域。
  4. 根据权利要求1至3中任意一项所述的内建自测试方法，其中，每个存储区域包括多个存储阵列；
    根据所述第一压缩写地址向对应的所述存储区域中写入测试数据，具体包括：
    在每个第一压缩写地址对应的所述存储区域内，根据当前行地址开启当前字线，开启当前字线上的所述存储阵列内的当前列选择线，以向目标 值个存储单元中写入所述测试数据，更新下一列选择线，直至向所述当前字线上所有存储单元写入测试数据。
  5. 根据权利要求1至3中任意一项所述的内建自测试方法，其中，每个存储区域包括多个存储阵列；
    根据所述第一压缩读地址对多个所述存储区域对应的所述测试数据进行读取，具体包括：
    在每个第一压缩读地址对应的所述存储区域内，根据当前行地址开启当前字线，开启当前字线上的所述存储阵列内的当前列选择线，以向目标值个存储单元中读出所述测试数据，更新下一列选择线，直至从所述当前字线上所有存储单元读出测试数据。
  6. 根据权利要求1至3中任意一项所述的内建自测试方法，其中，在写入数据时同时被激活的存储区域的数量大于在读出数据时同时被激活的存储区域的数量。
  7. 根据权利要求1至3中任意一项所述的内建自测试方法，其中，在获取待读出数据的所述存储区域的第二初始地址之前，所述方法还包括：
    获取待写入数据的存储区域的第三初始地址；
    对所述第三初始地址的至少一位地址进行屏蔽，以激活多个所述存储区域，记被激活的多个所述存储区域的地址为第二压缩写地址；
    根据所述第二压缩写地址向对应的所述存储区域中写入测试数据；
    相应地，在根据所述测试数据和预设压缩处理规则计算理想读出数据，比较所述存储器的读出数据和所述理想读出数据，获得测试结果之前，所述方法还包括：
    获取待读出数据的所述存储区域的第四初始地址；
    对所述第四初始地址的至少一位地址进行屏蔽，以激活多个所述存储区域，记被激活的多个所述存储区域的地址为第二压缩读地址；
    根据所述第二压缩读地址对多个所述存储区域对应的所述测试数据进行读取，且在读出过程中对所述测试数据进行压缩处理，以使所述存储器读出的压缩数据位数等于一个所述存储区域读出的未压缩数据的位数。
  8. 一种内建自测试装置，存储器包括多个存储区域，所述装置包括：
    写入模块，用于获取待写入数据的存储区域的第一初始地址；对所述 第一初始地址的至少一位地址进行屏蔽，以激活多个所述存储区域，记被激活的多个所述存储区域的地址为第一压缩写地址；根据所述第一压缩写地址向对应的所述存储区域中写入测试数据；
    读出模块，用于获取待读出数据的所述存储区域的第二初始地址；对所述第二初始地址的至少一位地址进行屏蔽，以激活多个所述存储区域，记被激活的多个所述存储区域的地址为第一压缩读地址；根据所述第一压缩读地址对多个所述存储区域对应的所述测试数据进行读取，且在读出过程中对所述测试数据进行压缩处理，以使所述存储器读出的压缩数据位数等于一个所述存储区域读出的未压缩数据的位数；
    输出模块，用于根据所述测试数据和预设压缩处理规则计算理想读出数据，比较所述存储器的读出数据和所述理想读出数据，获得测试结果。
  9. 根据权利要求8所述的内建自测试装置，其中，所述写入模块，具体用于：
    获取压缩写指令，并基于所述压缩写指令将所述第一初始地址中至少一位地址本身及其反相信号强制为相同的特定值，以激活对应的多个所述存储区域。
  10. 一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机执行指令，所述计算机执行指令被处理器执行时用于实现如权利要求1至7任一项所述的内建自测试方法。
PCT/CN2022/123947 2022-09-19 2022-10-09 内建自测试方法和设备 WO2024060316A1 (zh)

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