WO2024055885A1 - Dispositif à semi-conducteur et son procédé de fabrication - Google Patents

Dispositif à semi-conducteur et son procédé de fabrication Download PDF

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Publication number
WO2024055885A1
WO2024055885A1 PCT/CN2023/117298 CN2023117298W WO2024055885A1 WO 2024055885 A1 WO2024055885 A1 WO 2024055885A1 CN 2023117298 W CN2023117298 W CN 2023117298W WO 2024055885 A1 WO2024055885 A1 WO 2024055885A1
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WIPO (PCT)
Prior art keywords
layer
groove
semiconductor device
doped
silicon
Prior art date
Application number
PCT/CN2023/117298
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English (en)
Chinese (zh)
Inventor
苏帅
何林峰
魏巍
张亚文
武龙
侯明辰
冯鹏
韩明涛
李皓天
周瑞
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华为技术有限公司
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Publication of WO2024055885A1 publication Critical patent/WO2024055885A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Definitions

  • the present application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a manufacturing method thereof.
  • semiconductor devices such as high electron mobility transistors, etc.
  • semiconductor devices have been widely used in electronic devices such as mobile phones and tablet computers.
  • Semiconductor devices provided by related technologies often form ohmic contact between the electrode layer and the epitaxial layer through the metal type and ratio of the electrode layer (such as the source layer and the drain layer), the thickness of the epitaxial layer, etc.
  • the resistivity of ohmic contact is high, usually greater than 1 ⁇ mm, which is not conducive to reducing the on-resistance of semiconductor devices.
  • the present application provides a semiconductor device and a preparation method thereof, which realizes ohmic contact between the first electrode layer and the epitaxial layer, reduces the contact resistivity of the ohmic contact, helps to reduce the on-resistance of the semiconductor device, and thereby reduces Power losses in semiconductor devices.
  • the present application provides a semiconductor device, which may include an epitaxial layer, a doping layer, a dielectric layer and a first electrode layer.
  • the epitaxial layer and the dielectric layer can be stacked.
  • the semiconductor device may be provided with a first groove, and a part of the doping layer and the first electrode layer may be stacked inside the first groove. It can be understood that a part of the first electrode may be disposed inside the first groove, and another part of the first electrode may be disposed outside the first groove.
  • the semiconductor device provided by this application forms the ohmic contact between the first electrode layer and the epitaxial layer through the doping layer, which reduces the contact resistivity of the ohmic contact, helps to reduce the on-resistance of the semiconductor device, and thereby reduces the power of the semiconductor device. loss.
  • the doped layer, the epitaxial layer and the first electrode layer are all different, that is, there is a clear boundary between the doped layer and the epitaxial layer, and there is also a clear boundary between the doped layer and the first electrode layer.
  • the material of the doping layer may be any one or more of silicon, silicon oxide, silicon nitride, and silicon oxynitride.
  • the state of the doped layer may be a single crystal state, a polycrystalline state or an amorphous state.
  • the thickness of the doped layer may be 1 nm to 50 nm. Ohmic contact between the first electrode layer and the epitaxial layer can be achieved through the doping layer.
  • the material of the doped layer can also be other materials, and the thickness of the doped layer can also be in other thickness ranges, which is not limited in this application.
  • the thickness of the doped layer from a peak concentration of silicon down to a silicon concentration of 10% may be less than 20 nm.
  • the peak concentration of silicon can be 80%, 70%, 60%, etc. It can be understood that when the concentration of silicon is the peak concentration, the doped layer can correspond to a thickness. In the case of a silicon concentration of 10%, the doped layer can correspond to another thickness. The thickness difference between the two thicknesses may be less than 20 nm, which can reduce the contact resistivity of the ohmic contact between the first electrode layer and the epitaxial layer. Of course, the thickness difference between the two thicknesses will change with the concentration of silicon. This application does not limit the thickness of the doped layer from the peak concentration of silicon to a silicon concentration of 10%.
  • the thickness of the doped layer from a first concentration of silicon to a silicon concentration of 10% may be less than 20 nm.
  • the first concentration may be greater than or equal to 60%.
  • the first concentration may be 70% or 60%, etc.
  • the doped layer may correspond to a thickness.
  • the doped layer can correspond to another thickness.
  • the thickness difference between the two thicknesses may be less than 20 nm, which can reduce the contact resistivity of the ohmic contact between the first electrode layer and the epitaxial layer. Of course, the thickness difference between the two thicknesses will change with the concentration of silicon. This application does not limit the thickness of the doped layer from the first concentration of silicon to the second concentration of silicon.
  • the epitaxial layer may include a channel layer, a barrier layer and a cap layer that are stacked on the surface of the substrate. That is to say, the substrate, channel layer, barrier layer and cap layer are stacked in sequence.
  • the bottom of the first groove may be located at the cap layer, barrier layer or channel layer. That is to say, the bottom of the first groove can be located on the surface or inside the cap layer, on the surface or inside the barrier layer, or can also be located inside the channel layer. Furthermore, it is possible to make the first electrode layer and The cap layer, barrier layer or channel layer forms an ohmic contact.
  • the distance between the bottom of the first groove and the surface of the channel layer may be within 20 nm.
  • the surface of the channel layer may be used to indicate the surface of the channel layer close to the barrier layer.
  • the bottom of the first groove may be located inside the barrier layer or inside the channel layer. Regardless of whether the bottom of the first groove is located at the bottom of the first groove or inside the barrier layer, the distance between the bottom of the first groove and the surface of the channel layer can be within 20 nm.
  • the ohmic contact between the first electrode layer and the barrier layer can be realized, or the ohmic contact between the first electrode layer and the channel layer can be realized, and the contact resistivity of the ohmic contact can be reduced to the greatest extent, and the contact resistivity can be reduced to 0.5 ⁇ . ⁇ mm, while improving the working efficiency of semiconductor devices, it can also reduce the preparation cost of semiconductor devices.
  • the dielectric layer may be provided with a second groove, and the bottom of the second groove may be located on the surface of the capping layer, wherein the surface of the capping layer may be used to indicate that the capping layer is away from the barrier layer. surface.
  • the semiconductor device may further include a second electrode layer, the second electrode layer may be located inside the second groove, and the second electrode layer and the cap layer may form a Schottky contact.
  • the second electrode layer may be a gate layer. Therefore, the gate layer and the cap layer may form a Schottky contact.
  • the material of the first electrode layer may include any one or more of titanium Ti, gold Au, and aluminum Al.
  • the material of the source layer may include any one or more of titanium Ti, gold Au, and aluminum Al.
  • the material of the drain layer may also include any one or more of titanium Ti, gold Au, and aluminum Al.
  • the materials of the source layer and the drain layer can also be of other types, which are not limited in this application.
  • the material of the second electrode layer may include any one or more of titanium Ti, gold Au, and nickel Ni.
  • the material of the second electrode layer can also be of other types, which is not limited in this application.
  • the present application provides a method for manufacturing a semiconductor device, which can be used to prepare the semiconductor device provided by the first aspect and its possible implementations.
  • the preparation method may include: performing photolithography on the epitaxial layer to form a mask layer.
  • the doped layer is formed according to the mask layer.
  • a first electrode layer is formed on the surface of the doped layer, and the first electrode layer is annealed according to a preset annealing temperature.
  • the preset annealing temperature can be 400°C to 800°C.
  • the preparation method provided by this application has a simple process.
  • the contact resistivity of the ohmic contact between the first electrode layer and the epitaxial layer in the prepared semiconductor device is greatly reduced, and the contact resistivity can reach 0.5 ⁇ mm, which improves the working efficiency of the semiconductor device.
  • the manufacturing cost of semiconductor devices can be reduced.
  • photolithography of the epitaxial layer to form a mask layer may include: applying photoresist on the surface of the epitaxial layer, and applying the photoresist to the surface of the epitaxial layer according to the preset baking temperature and preset baking time.
  • the epitaxial layer is baked. Expose the baked epitaxial layer according to the preset exposure time. Use a developing solution and develop the exposed epitaxial layer according to the preset development time to form a mask layer.
  • the preset baking temperature can be 90°C to 120°C.
  • the preset baking time can be 60s to 120s, which can solidify the liquid photoresist on the surface of the epitaxial layer.
  • the preset baking temperature can also be in other temperature ranges, and the preset baking time can also be in other time ranges, which are not limited in this application.
  • the preset exposure time can be 100 ms to 1000 ms, which can transfer the pattern on the mask to the cured photoresist.
  • the preset exposure time can also be in other time ranges, which is not limited in this application.
  • the developer may be a tetramethylammonium hydroxide (TMAH) solution (which may be referred to as a TMAH solution).
  • TMAH tetramethylammonium hydroxide
  • the preset development time can be 30s to 90s, and the pattern on the cured photoresist can be transferred to the epitaxial layer.
  • the developer can also be other solutions, and the preset development time can also be other time ranges, which are not limited in this application.
  • forming the doping layer according to the mask layer may include: forming the doping layer on the surface of the epitaxial layer according to the mask layer. That is to say, the doped layer can be directly formed on the surface of the epitaxial layer according to the mask layer.
  • the preparation method provided by this application may also include: using plasma to process the surface of the epitaxial layer according to a preset processing time. That is to say, after photolithography of the epitaxial layer to form the mask layer, the surface of the epitaxial layer can be processed and then a doped layer can be formed. The surface roughness of the epitaxial layer can be increased, and the contact resistivity of the ohmic contact between the first electrode layer and the epitaxial layer can be further reduced.
  • the preset processing time can be 2min ⁇ 60min.
  • the plasma may include any one or more of hydrogen H 2 , nitrogen N 2 , ammonia NH 3 , chlorine Cl 2 , argon Ar and oxygen O 2 .
  • forming the doped layer according to the mask layer may include etching part of the epitaxial layer according to the mask layer to form a first groove. A deposition process is used to form a doped layer inside the first groove.
  • the epitaxial layer may include a channel layer, a barrier layer and a cap layer stacked on the surface of the substrate, then The cap layer is etched according to the mask layer, the cap layer and the barrier layer can be photolithographed according to the mask layer, or the cap layer, barrier layer and channel layer can be etched according to the mask layer. Therefore, the bottom of the first groove may be located on the surface or inside the cap layer, on the surface or inside the barrier layer, or on the surface or inside the channel layer.
  • the doped layer formed inside the first groove may also be located at different positions in the epitaxial layer depending on the position of the bottom of the first groove.
  • the deposition process can include atomic layer deposition (ALD) process (ALD process for short), plasma enhanced atomic layer deposition (PEALD) process (PEALD process for short), plasma enhanced Chemical vapor deposition (plasma enhanced chemical vapor deposition, PECVD) process (referred to as PECVD process), inductively coupled plasma chemical vapor deposition (ICPCVD) process (referred to as ICPCVD process), low pressure chemical vapor deposition (referred to as ICPCVD process) Any one of the low pressure chemical vapor deposition (LPCVD) process (referred to as LPCVD process), the electron beam evaporation (electronic beam evaporation, EBE) process (referred to as EBE process) and the sputtering deposition process.
  • ALD atomic layer deposition
  • PEALD plasma enhanced atomic layer deposition
  • PECVD plasma enhanced Chemical vapor deposition
  • ICPCVD inductively coupled plasma chemical vapor deposition
  • ICPCVD process low pressure chemical vapor deposition
  • the preparation method provided by this application may further include: forming a dielectric layer on the surface of the epitaxial layer. Photolithography and etching are performed on the dielectric layer to form a second groove. A second electrode layer is formed inside the second groove.
  • the doping layer, the epitaxial layer and the first electrode layer are all different. That is, there is a clear boundary between doped layers and epitaxial layers. There is also a clear demarcation between the doped layer and the first electrode layer.
  • the material of the doping layer may be any one or more of silicon, silicon oxide, silicon nitride, and silicon oxynitride.
  • the state of the doped layer may be a single crystal state, a polycrystalline state or an amorphous state.
  • the thickness of the doped layer may be 1 nm to 50 nm. Ohmic contact between the first electrode layer and the epitaxial layer can be achieved through the doping layer.
  • the material of the doped layer can also be other materials, and the thickness of the doped layer can also be in other thickness ranges, which is not limited in this application.
  • the doped layer is less than 20 nm thick from a peak concentration of silicon down to a silicon concentration of 10%.
  • the peak concentration of silicon can be 80%, 70%, 60%, etc. It can be understood that when the concentration of silicon is the peak concentration, the doped layer can correspond to a thickness. In the case of a silicon concentration of 10%, the doped layer can correspond to another thickness.
  • the thickness difference between the two thicknesses may be less than 20 nm, which can reduce the contact resistivity of the ohmic contact between the first electrode layer and the epitaxial layer. Of course, the thickness difference between the two thicknesses will change with the concentration of silicon. This application does not limit the thickness of the doped layer from the peak concentration of silicon to a silicon concentration of 10%.
  • the doped layer is less than 20 nm thick from a first concentration of silicon down to a silicon concentration of 10%.
  • the first concentration may be greater than or equal to 60%.
  • the first concentration may be 70% or 60%, etc.
  • the doped layer may correspond to a thickness.
  • the doped layer can correspond to another thickness.
  • the thickness difference between the two thicknesses may be less than 20 nm, which can reduce the contact resistivity of the ohmic contact between the first electrode layer and the epitaxial layer. Of course, the thickness difference between the two thicknesses will change with the concentration of silicon. This application does not limit the thickness of the doped layer from the first concentration of silicon to the second concentration of silicon.
  • the present application provides a method for manufacturing a semiconductor device, which can be used to prepare the semiconductor device provided by the first aspect and its possible implementations.
  • the preparation method may include photolithography of the dielectric layer to form a mask layer.
  • the doped layer is formed according to the mask layer.
  • a first electrode layer is formed on the surface of the doped layer, and the first electrode layer is annealed according to a preset annealing temperature.
  • the preset annealing temperature can be 400°C to 800°C.
  • the preparation method provided by this application has a simple process.
  • the contact resistivity of the ohmic contact between the first electrode layer and the epitaxial layer in the prepared semiconductor device is greatly reduced, and the contact resistivity can reach 0.5 ⁇ mm, which improves the working efficiency of the semiconductor device.
  • the manufacturing cost of semiconductor devices can be reduced.
  • performing photolithography on the dielectric layer to form a mask layer may include: applying photoresist on the surface of the dielectric layer, and applying the photoresist on the surface of the dielectric layer according to the preset baking temperature and preset baking time.
  • the medium layer is baked. Expose the baked dielectric layer according to the preset exposure time. Use a developing solution and develop the exposed dielectric layer according to the preset development time to form a mask layer.
  • the preset baking temperature can be 90°C to 120°C.
  • the preset baking time can be 60s to 120s, which can solidify the liquid photoresist on the surface of the epitaxial layer.
  • the preset baking temperature can also be in other temperature ranges, and the preset baking time can also be in other time ranges, which are not limited in this application.
  • the preset exposure time can be 100 ms to 1000 ms, which can transfer the pattern on the mask to the cured photoresist.
  • the preset exposure time can also be in other time ranges, which is not limited in this application.
  • the developer may be a tetramethylammonium hydroxide TMAH solution.
  • the preset development time can be 30s to 90s, and the pattern on the cured photoresist can be transferred to the epitaxial layer.
  • the developer can also be other solutions, and the preset development time can also be other time ranges, which are not limited in this application.
  • forming the doping layer according to the mask layer may include: etching the dielectric layer according to the mask layer to form a first groove.
  • the dielectric layer and part of the epitaxial layer are etched according to the mask layer to form a first groove. That is to say, only the dielectric layer can be etched according to the mask layer, or the dielectric layer and part of the epitaxial layer can be etched according to the mask layer, and the first groove can be formed.
  • a deposition process may be used to form a doped layer inside the first groove.
  • the deposition process may include any one of an ALD process, a PEALD process, a PECVD process, an ICPCVD process, a LPCVD process, an EBE process and a sputtering deposition process.
  • the preparation method provided by this application may also include: using plasma to process the surface of the epitaxial layer according to a preset processing time. That is to say, after photolithography of the epitaxial layer to form the mask layer, the surface of the epitaxial layer can be processed and then a doped layer can be formed. The surface roughness of the epitaxial layer can be increased, and the contact resistivity of the ohmic contact between the first electrode layer and the epitaxial layer can be further reduced.
  • the preset processing time can be 2min ⁇ 60min.
  • the plasma may include any one or more of hydrogen H 2 , nitrogen N 2 , ammonia NH 3 , chlorine Cl 2 , argon Ar and oxygen O 2 .
  • the preparation method provided by this application may further include: performing photolithography and etching on the dielectric layer to form a second groove.
  • a second electrode layer is formed inside the second groove.
  • the doping layer, the epitaxial layer and the first electrode layer are all different. That is, there is a clear boundary between doped layers and epitaxial layers. There is also a clear demarcation between the doped layer and the first electrode layer.
  • the material of the doping layer may be any one or more of silicon, silicon oxide, silicon nitride, and silicon oxynitride.
  • the state of the doped layer may be a single crystal state, a polycrystalline state or an amorphous state.
  • the thickness of the doped layer may be 1 nm to 50 nm. Ohmic contact between the first electrode layer and the epitaxial layer can be achieved through the doping layer.
  • the material of the doped layer can also be other materials, and the thickness of the doped layer can also be in other thickness ranges, which is not limited in this application.
  • the doped layer is less than 20 nm thick from a peak concentration of silicon down to a silicon concentration of 10%.
  • the peak concentration of silicon can be 80%, 70%, 60%, etc. It can be understood that when the concentration of silicon is the peak concentration, the doped layer can correspond to a thickness. In the case of a silicon concentration of 10%, the doped layer can correspond to another thickness.
  • the thickness difference between the two thicknesses may be less than 20 nm, which can reduce the contact resistivity of the ohmic contact between the first electrode layer and the epitaxial layer. Of course, the thickness difference between the two thicknesses will change with the concentration of silicon. This application does not limit the thickness of the doped layer from the peak concentration of silicon to a silicon concentration of 10%.
  • the doped layer is less than 20 nm thick from a first concentration of silicon down to a silicon concentration of 10%.
  • the first concentration may be greater than or equal to 60%.
  • the first concentration may be 70% or 60%, etc.
  • the doped layer may correspond to a thickness.
  • the doped layer can correspond to another thickness.
  • the thickness difference between the two thicknesses may be less than 20 nm, which can reduce the contact resistivity of the ohmic contact between the first electrode layer and the epitaxial layer. Of course, the thickness difference between the two thicknesses will change with the concentration of silicon. This application does not limit the thickness of the doped layer from the first concentration of silicon to the second concentration of silicon.
  • the present application provides an electronic chip, which may include passive devices and the semiconductor device provided by the above-mentioned first aspect and its possible implementations.
  • the passive device can be electrically connected to the semiconductor device.
  • passive components may be resistors, capacitors, etc.
  • the passive components can also be other components, which are not limited in this application.
  • the present application provides an electronic device, which may include a circuit board and the electronic chip provided in the fourth aspect and possible implementations thereof.
  • the electronic chip can be arranged on the circuit board.
  • Figure 1 is a schematic structural diagram of a semiconductor device 1 in an embodiment of the present application.
  • Figure 2 is a schematic structural diagram of groove A in the embodiment of the present application.
  • Figure 3 is another schematic structural diagram of groove A in the embodiment of the present application.
  • Figure 4 is another schematic structural diagram of groove A in the embodiment of the present application.
  • Figure 5 is another schematic structural diagram of groove A in the embodiment of the present application.
  • Figure 6 is another schematic structural diagram of groove A in the embodiment of the present application.
  • Figure 7 is another schematic structural diagram of groove A in the embodiment of the present application.
  • Figure 8 is another schematic structural diagram of the semiconductor device 1 in the embodiment of the present application.
  • Figure 9 is a schematic flow chart of a method for manufacturing the semiconductor device 1 in the embodiment of the present application.
  • Figure 10 is a schematic structural diagram of the mask layer 70 formed by photolithography on the epitaxial layer 20 in the embodiment of the present application;
  • Figure 11 is a schematic flow chart of photolithography of the epitaxial layer 20 to form the mask layer 70 in an embodiment of the present application;
  • Figure 12 is a schematic flow chart of forming the doping layer 30 according to the mask layer 70 in the embodiment of the present application;
  • Figure 13 is a schematic structural diagram of etching the epitaxial layer 20 to form a groove A in an embodiment of the present application
  • Figure 14 is a schematic structural diagram of processing groove A in the embodiment of the present application.
  • Figure 15 is a schematic structural diagram of forming the doping layer 30 according to the mask layer 70 in the embodiment of the present application.
  • Figure 16 is another schematic flow chart of forming the doping layer 30 according to the mask layer 70 in the embodiment of the present application.
  • Figure 17 is a schematic structural diagram of processing the surface of the epitaxial layer 20 in the embodiment of the present application.
  • Figure 18 is a schematic structural diagram of forming the doping layer 30 on the surface of the epitaxial layer 20 in the embodiment of the present application;
  • Figure 19 is a schematic structural diagram of forming the electrode layer 50 on the surface of the doped layer 30 in the embodiment of the present application.
  • Figure 20 is a schematic structural diagram of removing the mask layer 70 in the embodiment of the present application.
  • Figure 21 is another schematic structural diagram of removing the mask layer 70 in the embodiment of the present application.
  • Figure 22 is a schematic flow chart for forming the gate layer 60 in an embodiment of the present application.
  • Figure 23 is a schematic structural diagram of forming the dielectric layer 40 in the embodiment of the present application.
  • Figure 24 is a schematic structural diagram of forming groove B in the embodiment of the present application.
  • Figure 25 is another schematic flow chart of the method of manufacturing the semiconductor device 1 in the embodiment of the present application.
  • Figure 26 is another schematic flow chart of the preparation method of the semiconductor device 1 in the embodiment of the present application.
  • Figure 27 is another schematic flow chart of the preparation method of the semiconductor device 1 in the embodiment of the present application.
  • Figure 28 is a schematic structural diagram of forming the dielectric layer 40 on the surface of the epitaxial layer 20 in the embodiment of the present application;
  • Figure 29 is a schematic flow chart of photolithography of the dielectric layer 40 to form the mask layer 70 in an embodiment of the present application
  • Figure 30 is a schematic structural diagram of the mask layer 70 formed by photolithography on the dielectric layer 40 in the embodiment of the present application;
  • Figure 31 is a schematic structural diagram of etching the dielectric layer 40 and part of the epitaxial layer 20 to form a groove A in an embodiment of the present application;
  • Figure 32 is another schematic structural diagram of removing the mask layer 70 in the embodiment of the present application.
  • Figure 33 is another schematic structural diagram of processing groove A in the embodiment of the present application.
  • Figure 34 is a schematic structural diagram of forming the doping layer 30 inside the groove A in the embodiment of the present application.
  • Figure 35 is a schematic structural diagram of etching the dielectric layer 40 to form a groove A in the embodiment of the present application.
  • Figure 36 is another schematic structural diagram of forming the doping layer 30 inside the groove A in the embodiment of the present application.
  • FIG. 37 is another schematic flow chart of a method for manufacturing the semiconductor device 1 in the embodiment of the present application.
  • At least one (item) refers to one or more, and “plurality” refers to two or more.
  • “And/or” is used to describe the relationship between associated objects, indicating that there can be three relationships. For example, “A and/or B” can mean: only A exists, only B exists, and A and B exist simultaneously. , where A and B can be singular or plural. The character “/” generally indicates that the related objects are in an "or” relationship. “At least one of the following” or similar expressions thereof refers to any combination of these items, including any combination of a single item (items) or a plurality of items (items).
  • At least one of a, b or c can mean: a, b, c, "a and b", “a and c", “b and c", or "a and b and c” ”, where a, b, c can be single or multiple.
  • semiconductor devices such as high electron mobility transistors, etc.
  • semiconductor devices have been widely used in electronic devices such as mobile phones and tablet computers.
  • Semiconductor devices provided by related technologies often form ohmic contact between the electrode layer and the epitaxial layer through the metal type and ratio of the electrode layer (such as the source layer and the drain layer), the thickness of the epitaxial layer, etc.
  • the resistivity of ohmic contacts is higher, usually greater than 1 ⁇ mm, which is not conducive to reducing the on-resistance of semiconductor devices.
  • the semiconductor device 1 may include a substrate 10, an epitaxial layer 20, a doped layer 30, a dielectric layer 40 and an electrode layer (ie, a first electrode layer) 50.
  • the electrode layer 50 may include a source layer 51 and a drain layer 52 .
  • the substrate 10, the epitaxial layer 20 and the dielectric layer 40 may be stacked.
  • the epitaxial layer 20 may include a stacked channel layer 21 , a barrier layer 22 and a cap layer 23 , it can also be considered that the substrate 10 , the channel layer 21 , the barrier layer 22 , the cap layer 23 and the dielectric layer 40 are stacked set up.
  • other layers may be disposed in the epitaxial layer 20 , and/or other layers may be disposed between the substrate 10 , the epitaxial layer 20 and the dielectric layer 40 , which are not limited in the embodiments of the present application.
  • the semiconductor device 1 may be provided with a groove A (ie, a first groove, not marked in FIG. 1 ).
  • the doped layer 30 and a part of the electrode layer 50 may be stacked and disposed in the groove A. That is to say, a part of the electrode layer 50 and the doping layer 30 are stacked and arranged in the groove A, and another part of the electrode layer 50 may be arranged outside the groove A. Therefore, the ohmic contact between the electrode layer 50 and the epitaxial layer 20 can be formed through the doped layer 30 .
  • ohmic contact means that when the electrode layer 50 is in contact with the epitaxial layer 20, a very small contact barrier is formed at the contact interface, or no contact barrier is formed at the contact interface. That is, an ohmic contact has a lower contact resistivity. Ohmic contact can also be called non-rectifying contact.
  • the electrode layer 50 may include a source layer 51 and a drain layer 52. Therefore, the semiconductor device 1 may have two grooves A, one of which is used to place the doping layer 30 and the source layer 51. The other is used to place doped layer 30 and drain layer 52.
  • the lower part of the source layer 51 can be stacked with the doping layer 30 and disposed in a groove A, and the upper part of the source layer 51 can be disposed outside the groove A.
  • the lower part of the drain layer 52 may be stacked with the doping layer 30 and disposed in another groove A, and the upper part of the drain layer 52 may be disposed outside the other groove A.
  • the semiconductor device 1 provided by the embodiment of the present application forms an ohmic contact between the electrode layer 50 and the epitaxial layer 20 through the doping layer 30, which reduces the contact resistivity of the ohmic contact, helps to reduce the on-resistance of the semiconductor device, and thereby reduces the Power losses in semiconductor devices.
  • the dielectric layer 40 may be provided with groove B (ie, the second groove, not marked in FIG. 1 ).
  • the bottom of the groove B may be located on the surface of the capping layer 23 .
  • the surface of the cap layer 23 may be used to indicate the surface of the cap layer 23 facing away from the barrier layer 22 , that is, the upper surface of the cap layer 23 in FIG. 1 .
  • the semiconductor device 1 may further include a gate layer 60 (ie, a second electrode layer), and the gate layer 60 may be located inside the groove B.
  • the gate layer 60 and the cap layer 23 may form a Schottky contact. It should be explained that Schottky contact means that when the gate layer 60 and the cap layer 23 are in contact, the energy band of the cap layer 23 bends at the contact interface, forming a contact barrier (which can be called a Schottky barrier). ). Schottky contact can also be called rectifying contact.
  • the doping layer 30 , the epitaxial layer 20 and the electrode layer 50 are all different. That is to say, there is a clear boundary between the doped layer 30 and the epitaxial layer 20 (which can be the cap layer 23, the barrier layer 22 or the channel layer 21). There are also clear boundaries between the doping layer 30 and the electrode layer 50 (ie, the doping layer 30 and the source layer 51, and the doping layer 30 and the drain layer 52).
  • the material of the substrate 10 may be silicon (silicon) (which may be doped silicon or non-doped silicon), silicon carbide (SiC), sapphire (sapphire), and other materials. any one or more of them.
  • the material of the substrate 1 can also be other materials, which are not limited in the embodiments of this application.
  • epitaxial layer 20 may be a portion grown directly on substrate 10 in a semiconductor device process.
  • the thickness of the channel layer 21 in the epitaxial layer 20 may be 100 nm to 500 nm, and the material of the channel layer 21 may be gallium nitride (gallium nitride). Of course, the thickness of the channel layer 21 can also be in other thickness ranges, and the material of the channel layer 21 can also be other materials, which are not limited in the embodiments of this application.
  • the barrier layer 22 in the channel layer 21 and the epitaxial layer 20 can directly generate two-dimensional electron gas (2DEG), as shown in Figure 1 .
  • 2DEG two-dimensional electron gas
  • physical methods such as quantum confinement can be used to limit the movement of the electron group in one direction to a small range, while a system that can move freely in the other two directions is called a two-dimensional electronic system. Therefore, the electrons with lower density in the two-dimensional electron system can be called two-dimensional electron gas.
  • the channel layer 21 can increase the concentration of the two-dimensional electron gas, increase the current density of the semiconductor device 1 , and thereby increase the output current of the semiconductor device 1 .
  • the barrier layer 22 may be made of aluminum gallium nitride (AlGaN), and the barrier layer 22 may have a thickness of 15 nm to 40 nm. Since the materials of the barrier layer 22 and the channel layer 21 are different, they can form a heterojunction.
  • the barrier layer 22 may be made of aluminum gallium nitride AlGaN, and the channel layer 21 may be made of gallium nitride GaN. Thus, a heterojunction can be formed between the barrier layer 22 and the channel layer 21 . Two-dimensional electron gas can be obtained at the interface of the heterojunction.
  • the material of the barrier layer 22 can also be any one of InAlN (indium aluminum nitride), InGaN (indium gallium nitride), and AlInGaN (aluminum indium gallium nitride). , or any combination of the aforementioned materials (including aluminum gallium nitride AlGaN). Therefore, the thickness of the barrier layer 22 may be 5 nm to 20 nm. Similarly, the barrier layer 22 and the channel layer 21 may form a heterojunction.
  • the material of the barrier layer 22 can be other materials, and the thickness of the barrier layer 22 can also be in other thickness ranges, which are not limited in the embodiments of this application.
  • the material of the cap layer 23 in the epitaxial layer 20 may be GaN, and the thickness of the cap layer 23 may be 1 nm to 5 nm.
  • the cap layer 23 can be used to prevent the barrier layer 22 from being oxidized, thereby protecting the interface of the barrier layer 22 .
  • the material of the capping layer 23 can also be other materials, and the thickness of the capping layer 23 can also be in other thickness ranges, which are not limited in the embodiments of this application.
  • the source layer 51 may be made of any one or more of various materials such as titanium (titanium), gold (aurum), and aluminum (Al). That is to say, the source layer 51 may be made of Ti, Au or Al, or may be made of an alloy of at least two metals among Ti, Au and Al.
  • the material of the drain layer 52 may also be any one or more of various materials such as titanium (Titanium), gold (Au) (aurum), and aluminum (Al).
  • the gate layer 60 may be made of any one or more of various materials such as Ti, Au, and nickel (nickel). That is to say, the gate layer 60 may be made of Ti, Au or Ni, or may be made of an alloy of at least two metals among Ti, Au and Ni.
  • the source layer 51 , the drain layer 52 and the gate layer 60 can also be made of other materials, which are not limited in the embodiments of this application.
  • the source layer 51 and the drain layer 52 are made of the same material, and they are alloys of Ti, Al and Au respectively. Moreover, Ti, Al, Ti, and Au can be stacked in the order, and the corresponding thicknesses are 20nm, 150nm, 30nm, and 50nm respectively.
  • the material of the doping layer 30 may be any one or more of Si, silicon oxide SiO 2 (silicon dioxide), silicon nitride SiN (silicon nitride), and silicon oxynitride SiON (silicon oxynitride). kind.
  • the thickness of the doped layer 30 may be 1 nm to 50 nm.
  • the state of the doped layer 30 may be a single crystal state, a polycrystalline state, or an amorphous state.
  • the doped layer 30 can realize the ohmic contact between the source layer 51 and the epitaxial layer 20 and the ohmic contact between the drain layer 52 and the epitaxial layer 20 .
  • the material of the doped layer 30 can also be other materials, and the thickness of the doped layer 30 can also be in other thickness ranges, which are not limited in the embodiments of this application.
  • the thickness of doped layer 30 may be 5 nm.
  • the material of the doped layer 30 may be Si, and the state may be a polycrystalline state. That is to say, the doped layer 30 may be polycrystalline silicon.
  • the thickness of the doped layer 30 decreases from the peak concentration of silicon (which can be 80%, 70%, 60%, etc.) to the silicon concentration of 10%, which is less than 20 nm. It can be understood that when the concentration of silicon is the peak concentration, the doped layer 30 can correspond to a thickness. In the case where the silicon concentration is 10%, the doped layer 30 may correspond to another thickness. The thickness difference between the two thicknesses can be 20nm. Of course, the thickness difference between the two thicknesses will change with the concentration of silicon. The embodiment of the present application does not limit the thickness of the doped layer 30 from the peak concentration of silicon to a silicon concentration of 10%.
  • the first concentration of silicon in the doped layer 30 can also be set to 60%, and the second concentration of silicon is 10%. Then, the thickness of the doped layer 30 from the first concentration of silicon to the second concentration of silicon may be less than 20 nm.
  • the first concentration and the second concentration of silicon can also be other concentrations respectively, and the thickness of the doping layer 30 from the first concentration of silicon to the second concentration of silicon can also be in other thickness ranges, which are not covered in the embodiments of this application. limited.
  • dielectric layer 40 may include a dielectric layer. Then, the material of the dielectric layer 40 may be SiO 2 or SiN, etc., and the thickness may be 10 nm to 500 nm.
  • the dielectric layer 40 may also include two stacked dielectric layers. Then, one of the dielectric layers may be made of SiO 2 , and the other dielectric layer may be made of SiN. Alternatively, one of the dielectric layers may be made of Al 2 O 3 , and the other dielectric layer may be made of SiN. Of course, the material of the two dielectric layers can be the same, and both can be SiO 2 or SiN. The thickness of the two dielectric layers can be 5 nm to 500 nm respectively. The relative dielectric constant of the dielectric layer 40 can be increased, thereby improving the insulation of the dielectric layer 40 , reducing the quiescent current of the semiconductor device 1 , and reducing the quiescent power consumption of the semiconductor device 1 . Of course, the material of the dielectric layer 40 can also be other materials, and the thickness can also be in other thickness ranges, which are not limited in the embodiments of this application.
  • the bottom of the above-mentioned groove A may be located at the cap layer 23 , the barrier layer 22 or the channel layer 21 .
  • the location of groove A can be introduced with reference to Figures 2 to 7 below. It should be noted that, in order to clearly describe the position of the bottom of the groove A, the electrode layer 50 is not shown in the above-mentioned FIGS. 2 to 7 .
  • the position of the bottom of groove A can be divided into the following situations:
  • Case 1 The bottom of the groove A may be located inside the capping layer 23, as shown in Figure 2.
  • the bottom of groove A is located on the capping layer 23 close to the surface of the dielectric layer 40, as shown in FIG. 3 . That is, the bottom of the groove A may be located inside or on the upper surface of the capping layer 23 .
  • the doped layer 30 and the capping layer 23 can react chemically to form an N-type doped (such as silicon doped) region.
  • the electrode layer 50 reacts chemically with the N-type doped region to form an ohmic contact with low resistivity. That is to say, ohmic contact between the electrode layer 50 and the cap layer 23 is achieved, and the contact resistivity of the ohmic contact is reduced through the doping layer 30 .
  • Case 2 The bottom of the groove A may be located inside the barrier layer 22 , as shown in FIG. 4 .
  • the bottom of the groove A may be located on the surface of the barrier layer 22 close to the capping layer 21, as shown in FIG. 5 . That is, the bottom of the groove A may be located inside or on the upper surface of the barrier layer 22 .
  • the doping layer 30 and the barrier layer 22 can react chemically to form an N-type doped (eg silicon doped) region.
  • the electrode layer 50 reacts chemically with the N-type doped region to form an ohmic contact with low resistivity. That is to say, ohmic contact between the electrode layer 50 and the barrier layer 22 is achieved, and the contact resistivity of the ohmic contact is reduced through the doping layer 30 .
  • Case 3 The bottom of the groove A may be located inside the channel layer 21, as shown in FIG. 6 .
  • the bottom of the groove A may be located on a surface of the channel layer 21 close to the barrier layer 22, as shown in FIG. 7 . That is, the bottom of the groove A may be located inside or on the upper surface of the channel layer 21 .
  • a chemical reaction can occur between the doped layer 30 and the channel layer 21 to form an N-type doped (such as silicon doped) region.
  • the electrode layer 50 reacts chemically with the N-type doped region to form an ohmic contact with low resistivity. That is to say, ohmic contact between the electrode layer 50 and the channel layer 21 is achieved, and the contact resistivity of the ohmic contact is reduced through the doping layer 30 .
  • the distance between the bottom of the groove A and the upper surface of the channel layer 21 is within 10 nm. Then, you can have the following two structures:
  • the bottom of the groove A can be located inside the barrier layer 22 and within a distance of 10 nm from the upper surface of the channel layer 21 , as shown in FIG. 1 .
  • the bottom of the groove A can be located inside the channel layer 21 and within a distance of 10 nm from the upper surface of the channel layer 21, as shown in Figure 8.
  • the above two structures can also realize ohmic contact between the electrode layer 50 and the barrier layer 22 , or realize ohmic contact between the electrode layer 50 and the channel layer 21 , and can minimize the contact resistivity of the ohmic contact.
  • the contact resistivity can be reduced to 0.5 ⁇ mm, which not only improves the working efficiency of the semiconductor device 1, but also reduces the preparation cost of the semiconductor device 1.
  • the semiconductor device 1 provided in the embodiment of the present application can be a field effect transistor, and further can be a high electron mobility transistor (HEMT) or a heterojunction field effect transistor (HFET). Or modulation-doped FET (MODFET).
  • HEMT high electron mobility transistor
  • HFET heterojunction field effect transistor
  • MODFET modulation-doped FET
  • the semiconductor device 1 can also be other types of transistors, which are not limited in the embodiments of this application.
  • the embodiment of the present application provides a method for preparing a semiconductor device 1. As shown in Figure 9, the preparation process 100 can be implemented according to the following steps:
  • Step S101 Perform photolithography on the epitaxial layer 20 to form a mask layer 70, as shown in FIG. 10 .
  • step S101 photolithography is performed on the epitaxial layer 20 to form the mask layer 70 , which can be further implemented as follows:
  • Step S101a1 Coat photoresist on the surface of the epitaxial layer 20 (which may be the capping layer 23 of the epitaxial layer 20), and bake the epitaxial layer 20 coated with photoresist according to the preset baking temperature and preset baking time.
  • the preset baking temperature may be 90°C to 120°C.
  • the preset baking time can be 60 to 120 seconds to solidify the liquid photoresist on the surface of the epitaxial layer 20 .
  • the preset baking temperature can also be in other temperature ranges, and the preset baking time can also be in other time ranges, which are not limited in the embodiments of this application.
  • photoresist is coated on the surface of the epitaxial layer 20, and the epitaxial layer 20 coated with the photoresist is baked for 90 seconds at a baking temperature of 90°C.
  • the photoresist may be Az5214 type photoresist.
  • the photoresist can also be of other types, which is not limited in the embodiments of this application.
  • Step S101a2 Expose the baked epitaxial layer 20 according to the preset exposure time.
  • the preset exposure time can be 100ms to 1000ms, which can transfer the pattern on the mask to the cured photoresist.
  • the preset exposure time can also be in other time ranges, which is not limited in the embodiments of this application.
  • the baked epitaxial layer 20 is exposed for 200 ms.
  • Step S101a3 Use a developer to develop the exposed epitaxial layer 20 according to a preset development time to form a mask layer 70.
  • the developer may be a tetramethylammonium hydroxide (TMAH) solution (which may be referred to as a TMAH solution).
  • TMAH tetramethylammonium hydroxide
  • the developer can also be other solutions, which are not limited in the embodiments of this application.
  • the preset development time may be 30 to 90 s, and the pattern on the cured photoresist may be transferred to the epitaxial layer 20 .
  • a TMAH solution can be used to develop the exposed epitaxial layer 20 for 50 seconds to form a mask layer 70 with a thickness of 1 ⁇ m.
  • the preparation process 100 may also include:
  • Step S102 Forming the doping layer 30 according to the mask layer 70, which can be divided into the following embodiments for introduction:
  • the doped layer 30 is formed according to the following steps:
  • Step S102a1 Etch part of the epitaxial layer 20 according to the mask layer 70 of FIG. 10 to form a groove A, as shown in FIG. 13.
  • a dry etching process or a wet etching process may be used to etch part of the epitaxial layer 20 for 5 to 100 minutes.
  • the dry etching process can include reactive ion etching (RIE) process (RIE process for short), inductively coupled plasma etching (ICP process for short), ion etching (ICP process for short), Any one of the ion beam etching (IBE) process (referred to as the IBE process) and the advanced oxide etch (AOE) process (referred to as the AOE process).
  • RIE reactive ion etching
  • ICP process inductively coupled plasma etching
  • ICP process ion etching
  • AOE advanced oxide etch
  • the ICP process can be used to etch part of the epitaxial layer 20 for 10 minutes, and the part of the epitaxial layer 20 is physically bombarded by the inductively coupled plasma. At the same time, a chemical reaction occurs between the inductively coupled plasma and the epitaxial layer 20 to achieve dual effects. Etching, the etching rate is fast.
  • Step S102a2 Plasma can be used to process the groove A according to the preset processing time.
  • Ar can be used to treat groove A for 10 minutes, which can not only increase the surface roughness of groove A, but also increase the N vacancies on the surface of groove A, further reducing the ohmic resistance of the electrode layer 50 and the epitaxial layer 20 Contact resistivity of the contact.
  • Step S102a3 Use a deposition process to form the doping layer 30 inside the groove A, as shown in Figures 14 and 15.
  • the material, state and thickness of the doping layer 30 can be referred to the above introduction, and will not be described again in the embodiment of the present application.
  • the deposition process may include an atomic layer deposition (ALD) process (ALD process for short), plasma enhanced atomic layer deposition (PEALD) process (PEALD process for short), plasma Volume enhanced chemical vapor deposition (plasma enhanced chemical vapor deposition, PECVD) process (referred to as PECVD process), inductively coupled plasma chemical vapor deposition (inductively coupled plasma chemical vapor deposition, ICPCVD) process (referred to as ICPCVD process), low pressure chemical vapor deposition Any one of the deposition (low pressure chemical vapor deposition, LPCVD) process (referred to as the LPCVD process), the electron beam evaporation (electronic beam evaporation, EBE) process (referred to as the EBE process) and the sputter deposition process.
  • ALD atomic layer deposition
  • PEALD plasma enhanced atomic layer deposition
  • PECVD plasma Volume enhanced chemical vapor deposition
  • ICPCVD inductively coupled plasma chemical vapor deposition
  • ICPCVD inductively
  • a PECVD process is used to deposit polysilicon inside the groove A to form a doped layer 30 with a thickness of 5 nm.
  • the doped layer 30 is formed according to the following steps:
  • Step S102b1 Use plasma to process the surface of the epitaxial layer 20 in Figure 10 according to the preset processing time, as shown in Figure 17. That is to say, after obtaining the structure shown in FIG. 10 , the epitaxial layer 20 may not be etched, but the surface of the epitaxial layer 20 may be directly processed.
  • Step S102b2 According to the mask layer 70, form the doped layer 30 on the surface of the epitaxial layer 20 (which may be the cap layer 23), as shown in FIG. 18.
  • part of the epitaxial layer 20 is etched according to the mask layer 70 to form the groove A, and the groove A is processed to further form the doping layer 30 inside the groove A.
  • part of the epitaxial layer 20 is not etched, but the surface of the epitaxial layer 20 is directly processed, and the doping layer 30 is formed on the surface of the epitaxial layer 20 according to the mask layer 70 .
  • Step S103 Form an electrode layer 50 on the surface of the doped layer 30, and anneal the electrode layer 50 according to a preset annealing temperature.
  • an electrode layer 50 (including a source layer 51 and a drain layer 52 ) can be formed on the surface of the doped layer 30 in FIG. 15 .
  • Mask layer 70 is removed, as shown in Figure 20. Annealing the electrode layer 50 according to the preset annealing temperature can not only achieve ohmic contact between the electrode layer 50 and the epitaxial layer 20 , but also reduce the contact resistivity of the ohmic contact through the doping layer 30 .
  • the electrode layer 50 (including the source electrode) can be formed on the surface of the doped layer 30 in FIG. 18 layer 51 and drain layer 52).
  • Mask layer 70 is removed, as shown in Figure 21. Annealing the electrode layer 50 according to the preset annealing temperature can also achieve ohmic contact between the electrode layer 50 and the epitaxial layer 20 , and the contact resistivity of the ohmic contact can be reduced through the doping layer 30 .
  • the material, state and thickness of the doping layer 30 can be referred to the above introduction, and will not be described again in the embodiment of the present application.
  • the source layer 51 and the drain layer 52 can be annealed using annealing equipment such as an annealing furnace or laser at a preset annealing temperature of 400°C to 800°C.
  • annealing equipment such as an annealing furnace or laser at a preset annealing temperature of 400°C to 800°C.
  • the performance requirements for the annealing equipment are low and the implementation is relatively low.
  • Temperature annealing not only reduces the annealing cost, but is also compatible with the subsequent preparation process of the gate layer 60 .
  • the above two possible implementation methods can use any one of the above deposition processes to deposit metal on the surface of the cap layer 23, and remove the metal on the surface of the mask layer 70 through a stripping process or a dry etching process.
  • Source layer 51 and drain layer 52 are formed.
  • the stripping process refers to that after the capping layer 23 is coated with photoresist, exposed, and developed, the deposited metal is evaporated using a photoresist with a certain pattern as a mask, and then the photoresist is removed. At the same time, the metal deposited on the mask is peeled off to form the source layer 51 and the drain layer 52 .
  • the dry etching process refers to the use of reactive gases and plasma to etch deposited metal. In this embodiment of the present application, a reactive ion etching process may be used to remove metal on the surface of the mask layer 70 to form the source layer 51 and the drain layer 52 .
  • the EBE process is used to sequentially deposit Ti, Al, Ti, and Au on the surface of the doped layer 30 to form the source layer 51 and the drain layer 52 .
  • the thicknesses of Ti, Al, Ti, and Au correspond to 20nm, 150nm, 30nm, and 50nm.
  • the gate layer 60 can also be formed through the following steps:
  • Step S104a1 Form the dielectric layer 40 on the surface of the epitaxial layer 20 (which may be the cap layer 23).
  • the dielectric layer 40 can be formed on the basis of what is shown in Figure 20, as shown in Figure 23; or the dielectric layer 40 can also be formed on the basis of what is shown in Figure 21, which will not be described again here.
  • Step S104a2 Perform photolithography and etching on the dielectric layer 40 to form the groove B.
  • a groove B is formed, as shown in FIG. 24.
  • Step S104a3 Form the gate layer 60 inside the groove B.
  • the gate layer 60 is formed on the basis shown in FIG. 24 , as shown in FIG. 1 .
  • the method for manufacturing the semiconductor device 1 provided by the embodiment of the present application can be implemented through FIG. 25 or FIG. 26 , and the steps are described in detail below.
  • the preparation process 200 can be implemented through the following steps:
  • Step S201 Perform photolithography on the epitaxial layer 20 to form a mask layer 70, as shown in FIG. 10 .
  • Step S202 Etch part of the epitaxial layer 20 according to the mask layer 70 to form a groove A, as shown in FIG. 13 .
  • Step S203 Use plasma to process groove A, as shown in Figure 14.
  • Step S204 Form the doping layer 30 inside the groove A, as shown in FIG. 15 .
  • Step S205 Form an electrode layer 50 on the surface of the doped layer 30, as shown in Figure 19.
  • Step S206 Remove the mask layer 70, as shown in Figure 20.
  • Step S207 Anneal the electrode layer 50 according to the preset annealing temperature.
  • Step S208 Form a dielectric layer 40 on the surface of the epitaxial layer 20, as shown in FIG. 23.
  • Step S209 Perform photolithography and etching on the dielectric layer 40 to form groove B.
  • Step S210 Form the gate layer 60 inside the groove B, as shown in FIG. 1 .
  • step S201 can be referred to the above introduction, and will not be described again in the embodiment of the present application.
  • the preparation process 300 can be implemented through the following steps:
  • Step S301 Perform photolithography on the epitaxial layer 20 to form a mask layer 70, as shown in FIG. 10 .
  • Step S302 Use plasma to process the epitaxial layer 20, as shown in Figure 17.
  • Step S303 According to the mask layer 70, form the doping layer 30 on the surface of the epitaxial layer 20, as shown in FIG. 18.
  • Step S304 Form the electrode layer 50 on the surface of the doped layer 70.
  • Step S305 Remove the mask layer 70, as shown in Figure 21.
  • Step S306 Anneal the electrode layer 50 according to the preset annealing temperature.
  • Step S307 Form the dielectric layer 40 on the surface of the epitaxial layer 20.
  • Step S308 Perform photolithography and etching on the dielectric layer 40 to form the groove B.
  • Step S309 Form the gate layer 60 inside the groove B.
  • step S301 to step S309 can be referred to the above introduction, and will not be described again in the embodiment of the present application.
  • the preparation process 200 part of the epitaxial layer 20 is etched, and then the doped layer 30, the electrode layer 50, the dielectric layer 40 and the gate layer 60 are formed.
  • the preparation process 300 only the epitaxial layer 20 is photolithographed, and then the doping layer 30 , the electrode layer 50 , the dielectric layer 40 and the gate layer 60 are formed.
  • the embodiment of the present application provides another method of preparing a semiconductor device 1.
  • the preparation process 400 can be implemented according to the following steps:
  • Step S401 Perform photolithography on the dielectric layer 40 to form a mask layer 70.
  • the dielectric layer 40 may be formed on the surface of the epitaxial layer 20, as shown in FIG. 28.
  • step S101 photolithography is performed on the dielectric layer 40 to form the mask layer 70 (as shown in Figure 30), which can be further implemented as follows:
  • Step S401a1 Coat photoresist on the surface of the dielectric layer 40, and bake the dielectric layer 40 coated with photoresist according to the preset baking temperature and preset baking time.
  • the dielectric layer 40 coated with photoresist can be baked at a preset baking temperature of 90°C to 120°C and a preset baking time of 60s to 120s, so that the liquid photoresist is on the surface of the dielectric layer 40 solidify.
  • the dielectric layer 40 coated with photoresist can also be baked at other baking temperatures and other baking times, which are not limited by the embodiments of the present application.
  • photoresist Az5214 can be coated on the surface of the dielectric layer 40, and the dielectric layer 40 coated with the photoresist is baked at a baking temperature of 90°C for 90 seconds.
  • Step S401a2 Expose the baked dielectric layer 40 according to the preset exposure time.
  • the baked dielectric layer 40 can be exposed with a preset exposure time of 100 ms to 1000 ms, so that the pattern on the mask can be transferred to the cured photoresist.
  • the preset exposure time can also be in other time ranges, which is not limited in the embodiments of this application.
  • the baked dielectric layer 40 may be exposed for 200 ms.
  • Step S401a3 Use a developer to develop the exposed dielectric layer 40 according to a preset development time to form a mask layer 70, as shown in FIG. 30 .
  • a TMAH solution can be used to develop the exposed dielectric layer 40 with a preset development time of 30 to 90 seconds, and the pattern on the cured photoresist can be transferred to the dielectric layer 40 .
  • the developing solution can also be other solutions, and the preset development time can also be other time ranges, which are not limited in the embodiments of this application.
  • a TMAH solution can be used to develop the exposed dielectric layer 40 for 50 seconds to form a mask layer 70 with a thickness of 1 ⁇ m.
  • Step S402 Forming the doping layer 30 according to the mask layer 70, which can be divided into the following embodiments for introduction:
  • the doped layer 30 may be formed according to the following steps:
  • Step S402a1 Etch the dielectric layer 40 and part of the epitaxial layer 20 according to the mask layer 70 in Figure 30 to form a groove A, as shown in Figure 31 .
  • Step S402a2 Remove the mask layer 70, as shown in Figure 32.
  • Step S402a3 Use plasma to process groove A according to the preset processing time, as shown in Figure 33.
  • Ar can be used to treat groove A for 10 minutes, which can not only increase the surface roughness of groove A, but also increase the N vacancies on the surface of groove A, further reducing the ohmic resistance of the electrode layer 50 and the epitaxial layer 20 Contact resistivity of the contact.
  • Step S402a4 Use a deposition process to form the doping layer 30 inside the groove A, as shown in Figure 34.
  • the material, state, thickness and deposition process of the doping layer 30 can be referred to the above introduction, and will not be described again in the embodiment of the present application.
  • a PECVD process is used to deposit polysilicon inside the groove A to form a doped layer 30 with a thickness of 5 nm.
  • the doping layer 30 may be formed according to the following steps:
  • Step S402b1 Etch the dielectric layer 40 according to the mask layer 70 in Figure 30 to form a groove A, as shown in Figure 35 .
  • Step S402b2 Remove the mask layer 70.
  • Step S402b3 Use plasma to process groove A according to the preset processing time.
  • Ar can be used to treat groove A for 10 minutes, which can not only increase the surface roughness of groove A, but also increase the N vacancies on the surface of groove A, further reducing the ohmic resistance of the electrode layer 50 and the epitaxial layer 20 Contact resistivity of the contact.
  • Step S402b4 Use a deposition process to form the doping layer 30 inside the groove A, as shown in Figure 36.
  • the material, state, thickness and deposition process of the doping layer 30 can be referred to the above introduction, and will not be described again in the embodiment of the present application.
  • a PECVD process is used to deposit polysilicon inside the groove A to form a doped layer 30 with a thickness of 5 nm.
  • step S402a1 to step S402a4 the dielectric layer 40 and part of the epitaxial layer 20 are etched according to the mask layer 70 to form the groove A, the groove A is processed, and further inside the groove A Doped layer 30 is formed.
  • steps S402b1 to S402b4 only the dielectric layer 40 is etched according to the mask layer 70 to form the groove A, the groove A is processed, and the doping layer 30 is further formed inside the groove A.
  • Step S403 Form an electrode layer 50 on the surface of the doped layer 30, and anneal the electrode layer 50 according to a preset annealing temperature.
  • the electrode layer 50 (that is, the source layer 51 and the drain layer 52 are formed) can be formed on the surface of the doped layer 30 in FIG. 34 , as shown in FIG. 23 .
  • Annealing the electrode layer 50 according to the preset annealing temperature can not only achieve ohmic contact between the electrode layer 50 and the epitaxial layer 20 , but also reduce the contact resistivity of the ohmic contact through the doping layer 30 .
  • the electrode layer 50 (that is, the source layer 51 and the drain layer 52 are formed) can be formed on the surface of the doped layer 30 in FIG. 36 .
  • Annealing the electrode layer 50 according to the preset annealing temperature can also achieve ohmic contact between the electrode layer 50 and the epitaxial layer 20 , and the contact resistivity of the ohmic contact can be reduced through the doping layer 30 .
  • the material, state and thickness of the doping layer 30 can be referred to the above introduction, and will not be described again in the embodiment of the present application.
  • the source layer 51 and the drain layer 52 can be annealed using annealing equipment such as an annealing furnace or laser at a preset annealing temperature of 400°C to 800°C.
  • annealing equipment such as an annealing furnace or laser at a preset annealing temperature of 400°C to 800°C.
  • the performance requirements for the annealing equipment are low and the implementation is relatively low.
  • Temperature annealing not only reduces the annealing cost, but is also compatible with the subsequent preparation process of the gate layer 60 .
  • the above two possible implementation methods can use any one of the above deposition processes to deposit metal on the surface of the cap layer 23, and remove the metal on the surface of the mask layer 70 through a stripping process or an etching process to form a source. electrode layer 51 and drain layer 52.
  • the EBE process is used to sequentially deposit Ti, Al, Ti, and Au on the surface of the doped layer 30 to form the source layer 51 and the drain layer 52 .
  • the thicknesses of Ti, Al, Ti, and Au correspond to 20nm, 150nm, 30nm, and 50nm.
  • the gate layer 60 can also be formed through the following steps:
  • Step S404a1 Perform photolithography and etching on the dielectric layer 40 to form groove B.
  • groove B is formed on the basis shown in Fig. 23, as shown in Fig. 24.
  • Step S404a2 Form the gate layer 60 inside the groove B.
  • the gate layer 60 is formed on the basis shown in FIG. 24 , as shown in FIG. 1 .
  • the method for manufacturing the semiconductor device 1 provided by the embodiment of the present application can be implemented through FIG. 37 , and the steps are described in detail below.
  • the preparation process 500 can be implemented through the following steps:
  • Step S501 Form a dielectric layer 40 on the surface of the epitaxial layer 20, as shown in Figure 28.
  • Step S502 Perform photolithography on the dielectric layer 40 to form a mask layer 70, as shown in FIG. 30 .
  • Step S503 Etch the dielectric layer 40 and part of the epitaxial layer 20 according to the mask layer 70 to form a groove A.
  • the dielectric layer 40 is etched according to the mask layer 70 to form the groove A.
  • the groove A formed is as shown in FIG. 31 . If the dielectric layer 40 is etched, the groove A formed is as shown in FIG. 35 .
  • Step S504 Remove the mask layer 70, as shown in Figure 32.
  • Step S505 Use plasma to process groove A, as shown in Figure 33.
  • Step S506 Form the doping layer 30 inside the groove A, as shown in Figure 34 or Figure 36.
  • Step S507 Form an electrode layer 50 on the surface of the doped layer 30, as shown in FIG. 23.
  • Step S508 Anneal the electrode layer 50 according to the preset annealing temperature.
  • Step S509 Perform photolithography and etching on the dielectric layer 40 to form groove B.
  • Step S510 Form the gate layer 60 inside the groove B, as shown in FIG. 1 .
  • step S501 to step S510 can be referred to the above introduction, and will not be repeated in the embodiment of this application. narrate.
  • the size of the sequence numbers of the above-mentioned processes does not mean the order of execution.
  • the execution order of each process should be determined by its functions and internal logic, and should not be used in the embodiments of the present application.
  • the implementation process constitutes any limitation.
  • the embodiment of the present application provides an electronic chip, which may include passive devices and semiconductor devices 1 .
  • the passive device may be electrically connected to the semiconductor device 1 .
  • passive components may be resistors, capacitors, etc.
  • the passive components can also be other components, which are not limited in the embodiments of this application.
  • An embodiment of the present application provides an electronic device, which may include a circuit board and the above-mentioned electronic chip.
  • the electronic chip can be arranged on the circuit board.

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

La présente invention concerne un dispositif à semi-conducteur et son procédé de préparation, qui réalisent un contact ohmique entre une première couche d'électrode et une couche épitaxiale, réduisent la résistivité de contact du contact ohmique, sont favorables à la réduction de la résistance à l'état passant du dispositif à semi-conducteur, et réduisent ainsi la perte de puissance du dispositif à semi-conducteur. Le dispositif à semi-conducteur peut comprendre une couche épitaxiale, une couche dopée, une couche diélectrique et une première couche d'électrode, la couche épitaxiale et la couche diélectrique étant empilées. Le dispositif à semi-conducteur est pourvu d'un premier évidement, une partie de la couche dopée et une partie de la première couche d'électrode pouvant être empilées à l'intérieur du premier évidement.
PCT/CN2023/117298 2022-09-13 2023-09-06 Dispositif à semi-conducteur et son procédé de fabrication WO2024055885A1 (fr)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060226442A1 (en) * 2005-04-07 2006-10-12 An-Ping Zhang GaN-based high electron mobility transistor and method for making the same
US20070284653A1 (en) * 2006-06-08 2007-12-13 Hiroaki Ueno Semiconductor device
JP2008118044A (ja) * 2006-11-07 2008-05-22 Toshiba Corp 電界効果トランジスタ及びその製造方法
US20080128753A1 (en) * 2006-11-30 2008-06-05 Cree, Inc. Transistors and method for making ohmic contact to transistors

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060226442A1 (en) * 2005-04-07 2006-10-12 An-Ping Zhang GaN-based high electron mobility transistor and method for making the same
US20070284653A1 (en) * 2006-06-08 2007-12-13 Hiroaki Ueno Semiconductor device
JP2008118044A (ja) * 2006-11-07 2008-05-22 Toshiba Corp 電界効果トランジスタ及びその製造方法
US20080128753A1 (en) * 2006-11-30 2008-06-05 Cree, Inc. Transistors and method for making ohmic contact to transistors

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