WO2024055589A1 - 相位追踪电路和方法及电子设备 - Google Patents

相位追踪电路和方法及电子设备 Download PDF

Info

Publication number
WO2024055589A1
WO2024055589A1 PCT/CN2023/089748 CN2023089748W WO2024055589A1 WO 2024055589 A1 WO2024055589 A1 WO 2024055589A1 CN 2023089748 W CN2023089748 W CN 2023089748W WO 2024055589 A1 WO2024055589 A1 WO 2024055589A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
phase
clock
frequency
frequency division
Prior art date
Application number
PCT/CN2023/089748
Other languages
English (en)
French (fr)
Inventor
刘览琦
把傲
柯毅
刘德珩
马可铮
Original Assignee
武汉市聚芯微电子有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN202211129272.2A external-priority patent/CN115441866B/zh
Priority claimed from CN202211129085.4A external-priority patent/CN115498999B/zh
Priority claimed from CN202211129145.2A external-priority patent/CN115483928B/zh
Application filed by 武汉市聚芯微电子有限责任公司 filed Critical 武汉市聚芯微电子有限责任公司
Publication of WO2024055589A1 publication Critical patent/WO2024055589A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Definitions

  • the present invention relates to a phase tracking circuit, a phase tracking method, and an electronic device including a phase tracking circuit.
  • NFC near field communication
  • PLM passive load modulation
  • ALM active load modulation
  • an NFC device such as a mobile phone
  • the active load modulation scheme can provide greater signal power and better anti-interference characteristics, but because the carrier signal actively transmitted by the NFC device has a different source than the card reader signal, there may be a phase deviation problem.
  • Embodiments of the present invention provide a phase tracking circuit that can control the signal phase adjustment speed by adjusting at least one of a frequency division ratio and a clock signal, so that the target phase can be quickly and accurately tracked within a large phase difference range. , and can also save power consumption.
  • Embodiments of the present invention also provide a phase tracking method and an electronic device including a phase tracking circuit.
  • a phase tracking circuit may include: a frequency divider for dividing a first clock signal to obtain a carrier signal; a phase detector for comparing the phases of the carrier signal and a reference clock signal , to generate a phase indication signal; a phase tuning module, configured to adjust the phase of the first clock signal based on the phase indication signal, so that the phase of the carrier signal is closer to the phase of the reference clock signal; and a control module configured to control at least one of the operating clock of the phase tuning module and the frequency division ratio of the frequency divider based on the phase indication signal to control the The phase adjustment speed of the phase tuning module.
  • the phase detector is a binary phase detector, and the phase indication signal output by the binary phase detector indicates that the phase of the carrier signal leads or lags behind the phase of the reference clock signal.
  • the phase tuning module includes: a digital loop filter for generating a first clock selection signal based on the phase indication signal; and a first clock selection unit for selecting based on the first clock The signal selects a clock signal from the multi-phase clock signals as the first clock signal.
  • control module includes at least one of a second clock selection unit and a frequency division ratio control unit, and a dynamic detection adjustment unit.
  • the dynamic detection and adjustment unit is configured to detect the phase indication signal generated by the phase detector, and generate a second clock selection signal and/or a frequency division ratio adjustment signal.
  • the second clock selection unit is configured to select one of a plurality of second clock signals as an operating clock of the digital loop filter based on the second clock selection signal.
  • the frequency division ratio control unit is configured to control the frequency division ratio of the frequency divider based on the frequency division ratio adjustment signal.
  • the plurality of second clock signals include one or more frequency-divided signals provided by the frequency divider.
  • the plurality of second clock signals further include the first clock signal provided by the first clock selection unit.
  • the second clock selection signal generated by the dynamic detection adjustment unit Instruct the second clock selection unit to select a clock signal with a higher frequency than the currently selected clock signal from the plurality of second clock signals, and the frequency division ratio adjustment signal generated by the dynamic detection adjustment unit indicates that the frequency division ratio adjustment signal
  • the frequency ratio control unit increases the frequency dividing gear of the frequency divider.
  • the dynamic detection adjustment unit When the phase indication signal indicates that the phase of the carrier signal jumps between being ahead and lagging behind the phase of the reference clock signal and the jump reaches a predetermined number of times, the dynamic detection adjustment unit generates the first The second clock selection signal instructs the second clock selection unit to select a frequency division signal with a lower frequency than the currently selected clock signal from the plurality of second clock signals, and the frequency division ratio generated by the dynamic detection adjustment unit is adjusted. The signal instructs the frequency division ratio control unit to reduce the frequency division gear of the frequency divider.
  • the crossover has a base gear and at least one Higher gear, the basic gear has a basic frequency division ratio N, and the higher gear has a higher frequency division ratio N+x or a lower frequency division ratio Nx, N is a preset positive integer, x is the ratio N The smaller the positive integer and the higher the gear, the greater the value of x.
  • the higher gear has the A higher frequency division ratio N+x
  • the higher gear has the lower frequency division ratio Nx.
  • the carrier signal is the frequency-divided signal with the lowest frequency among multiple frequency-divided signals provided by the frequency divider, and the basic frequency-dividing ratio N makes the frequency of the carrier signal equal to the reference clock.
  • the frequency of the signal is the frequency-divided signal with the lowest frequency among multiple frequency-divided signals provided by the frequency divider, and the basic frequency-dividing ratio N makes the frequency of the carrier signal equal to the reference clock. The frequency of the signal.
  • the multi-phase clock signal includes M clock signals of different phases, where M is an integer greater than one.
  • the first clock selection signal generated by the digital loop filter represents one of M index values to instruct the first clock selection unit to select a corresponding clock signal from the M clock signals of different phases as the first clock signal.
  • the first clock generated by the digital loop filter The selection signal instructs the first clock selection unit to select a clock signal from the multi-phase clock signal that is lagging behind the phase of the currently selected clock signal.
  • the first clock selection signal generated by the digital loop filter indicates that the The first clock selection unit selects a clock signal from the multi-phase clock signals that is ahead of the phase of the currently selected clock signal.
  • the digital loop filter includes: a proportional path, used to generate a first proportional signal that is a first ratio to the phase indication signal; an integration path, used to generate a first proportional signal that is a first ratio to the phase indication signal. a second proportional signal of two proportions, and an integrator is used to integrate the second proportional signal to generate an integral signal; an adder is used to add the first proportional signal and the integral signal to output the sum value of the two; and a remainder unit for performing a remainder operation on the sum value received from the adder with respect to a predetermined value to generate the first clock selection signal representing the remainder.
  • the second clock signal selected by the second clock selection unit is used as an operating clock of the integrator in the integration path, and the predetermined value is equal to the multi-phase clock signal having different phases.
  • the number of clock signals is used as an operating clock of the integrator in the integration path, and the predetermined value is equal to the multi-phase clock signal having different phases. The number of clock signals.
  • the digital loop filter further includes at least one of the following: a first proportional adjustment unit disposed in the proportional path for adjusting the first proportion; and a first proportional adjustment unit disposed in the integral path.
  • the second proportion adjustment unit in is used to adjust the second proportion.
  • the first proportion adjustment unit and the second proportion adjustment unit use the same adjustment coefficient to adjust the first proportion and the second proportion in equal proportions.
  • the phase tracking circuit further includes: a coefficient control unit configured to control at least one of the first ratio and the second ratio based on the coefficient adjustment signal generated by the dynamic detection adjustment unit. Adjustment coefficient.
  • the coefficient adjustment signal generated by the dynamic detection adjustment unit instructs the coefficient control unit to increase The adjustment coefficient is to increase the at least one of the first ratio and the second ratio.
  • the coefficient generated by the dynamic detection adjustment unit The adjustment signal instructs the coefficient control unit to reduce the adjustment coefficient to reduce the at least one of the first ratio and the second ratio.
  • the dynamic detection adjustment unit when the phase indication signal indicates that the phase of the carrier signal is ahead or behind the phase of the reference clock signal for a predetermined period, the dynamic detection adjustment unit first generates the coefficient adjustment signal to increase the at least one of the first ratio and the second ratio until a maximum ratio is reached, and then generate the second clock selection signal to increase the second clock signal selected by the second clock selection unit frequency until it reaches the highest frequency, and then generates the frequency division ratio adjustment signal to increase the frequency division gear of the frequency divider.
  • the dynamic detection adjustment unit When the phase indication signal indicates that the phase of the carrier signal jumps between being ahead and lagging behind the phase of the reference clock signal and the jump reaches a predetermined number of times, the dynamic detection adjustment unit first generates The frequency division ratio adjustment signal is used to reduce the frequency division gear of the frequency divider until it reaches a basic gear, and then the second clock selection signal is generated to reduce the frequency of the second clock signal selected by the second clock selection unit. frequency until a lowest frequency is reached, and then the coefficient adjustment signal is generated to reduce the at least one of the first ratio and the second ratio.
  • the dynamic detection adjustment unit when the phase indication signal indicates that the phase of the carrier signal is ahead or behind the phase of the reference clock signal for a predetermined period, the dynamic detection adjustment unit first generates the coefficient adjustment signal to increase the at least one of the first ratio and the second ratio until a maximum ratio is reached, and then generate the second clock selection signal to increase the the frequency of the second clock signal selected by the second clock selection unit until reaching the highest frequency, and then generating a minimum second clock setting signal to set the frequency of the second clock signal selected by the second clock selection unit to the lowest frequency, And the frequency division ratio adjustment signal is generated to increase the frequency division gear of the frequency divider.
  • the dynamic detection adjustment unit When the phase indication signal indicates that the phase of the carrier signal jumps between being ahead and lagging behind the phase of the reference clock signal and the jump reaches a predetermined number of times, the dynamic detection adjustment unit first generates The frequency division ratio adjustment signal is used to reduce the frequency division gear of the frequency divider until it reaches the basic gear, and when the frequency division gear reaches the basic gear, a maximum second clock setting signal is generated to reduce the frequency division gear.
  • the frequency of the second clock signal selected by the second clock selection unit is set to the highest frequency, and then the second clock selection signal is generated to reduce the frequency of the second clock signal selected by the second clock selection unit until the lowest frequency is reached,
  • the coefficient adjustment signal is then generated to reduce the at least one of the first ratio and the second ratio.
  • a phase tracking method may include: a frequency divider divides a first clock signal to obtain a carrier signal; a phase detector compares the phase of the carrier signal and a reference clock signal to generate a phase indication signal ; The phase tuning module adjusts the phase of the first clock signal based on the phase indication signal, so that the phase of the carrier signal is closer to the phase of the reference clock signal; and the control module controls based on the phase indication signal At least one of the operating clock of the phase tuning module and the frequency division ratio of the frequency divider is used to control the phase adjustment speed of the phase tuning module.
  • the phase tuning module adjusting the phase of the first clock signal based on the phase indication signal includes: using a digital loop filter to generate a first clock selection signal based on the phase indication signal; and using a first The clock selection unit selects one clock signal from multi-phase clock signals as the first clock signal based on the first clock selection signal.
  • control module includes at least one of a second clock selection unit and a frequency division ratio control unit, and a dynamic detection adjustment unit.
  • the dynamic detection and adjustment unit is configured to detect the phase indication signal generated by the phase detector, and generate a second clock selection signal and/or a frequency division ratio adjustment signal.
  • the second clock selection unit is configured to select one of a plurality of second clock signals as an operating clock of the digital loop filter based on the second clock selection signal.
  • the frequency division ratio control unit is configured to control the frequency division ratio of the frequency divider based on the frequency division ratio adjustment signal.
  • the plurality of second clock signals include one or more frequency-divided signals provided by the frequency divider.
  • the plurality of second clock signals further include the first clock selection unit providing of the first clock signal.
  • the second clock selection signal generated by the dynamic detection adjustment unit Instruct the second clock selection unit to select a clock signal with a higher frequency than the currently selected clock signal from the plurality of second clock signals, and the frequency division ratio adjustment signal generated by the dynamic detection adjustment unit indicates that the frequency division ratio adjustment signal
  • the frequency ratio control unit increases the frequency dividing gear of the frequency divider.
  • the dynamic detection adjustment unit When the phase indication signal indicates that the phase of the carrier signal jumps between being ahead and lagging behind the phase of the reference clock signal and the jump reaches a predetermined number of times, the dynamic detection adjustment unit generates the first The second clock selection signal instructs the second clock selection unit to select a frequency division signal with a lower frequency than the currently selected clock signal from the plurality of second clock signals, and the frequency division ratio generated by the dynamic detection adjustment unit is adjusted. The signal instructs the frequency division ratio control unit to reduce the frequency division gear of the frequency divider.
  • the frequency divider has a basic gear and at least one higher gear, the basic gear has a basic frequency division ratio N, and the higher gear has a higher frequency division ratio N+x or a lower frequency division ratio N-x, N is a preset positive integer, x is a positive integer smaller than N and the higher the gear, the greater the value of x.
  • N is a preset positive integer
  • x is a positive integer smaller than N and the higher the gear, the greater the value of x.
  • the first clock selection signal generated by the digital loop filter indicates that the The first clock selection unit selects a clock signal from the multi-phase clock signal that is lagging behind the phase of the currently selected clock signal.
  • the first clock selection signal generated by the digital loop filter indicates the first clock selection unit A clock signal is selected from the multi-phase clock signals that is more advanced in phase than the currently selected clock signal.
  • using a digital loop filter to generate a first clock selection signal based on the phase indication signal includes: using a proportional path to generate a first proportional signal that is in a first proportion to the phase indication signal; using an integral path to generate a second proportional signal that is in a second proportion to the phase indication signal, and the second proportional signal is integrated using an integrator disposed in the integration path to generate an integral signal; an adder is used to calculate the second proportional signal.
  • a proportional signal and the integral signal are An addition operation is performed to output the sum value of the two; and a remainder unit is used to perform a remainder operation on the sum value with respect to a predetermined value to generate the first clock selection signal representing the remainder.
  • the second clock signal selected by the second clock selection unit is used as an operating clock of the integrator in the integration path to control the speed of integrating the second proportional signal, and the predetermined value is equal to The number of clock signals with different phases included in the multi-phase clock signal.
  • using a digital loop filter to generate the first clock selection signal based on the phase indication signal further includes at least one of the following steps: adjusting the first proportional adjustment unit disposed in the proportional path. a first proportion; and adjusting the second proportion using a second proportion adjustment unit disposed in the integral path.
  • the first proportion adjustment unit and the second proportion adjustment unit use the same adjustment coefficient to adjust the first proportion and the second proportion in equal proportions.
  • the method further includes: using a coefficient control unit to control an adjustment coefficient for adjusting at least one of the first ratio and the second ratio based on a coefficient adjustment signal generated by the dynamic detection adjustment unit.
  • the coefficient adjustment signal generated by the dynamic detection adjustment unit instructs the coefficient control unit to increase The adjustment coefficient is to increase the at least one of the first ratio and the second ratio.
  • the coefficient generated by the dynamic detection adjustment unit The adjustment signal instructs the coefficient control unit to reduce the adjustment coefficient to reduce the at least one of the first ratio and the second ratio.
  • the dynamic detection adjustment unit when the phase indication signal indicates that the phase of the carrier signal is ahead or behind the phase of the reference clock signal for a predetermined period, the dynamic detection adjustment unit first generates the coefficient adjustment signal to increase the at least one of the first ratio and the second ratio until a maximum ratio is reached, and then generate the second clock selection signal to increase the second clock signal selected by the second clock selection unit frequency until it reaches the highest frequency, and then generates the frequency division ratio adjustment signal to increase the frequency division gear of the frequency divider.
  • the dynamic detection adjustment unit When the phase indication signal indicates that the phase of the carrier signal jumps between being ahead and lagging behind the phase of the reference clock signal and the jump reaches a predetermined number of times, the dynamic detection adjustment unit first generates The frequency division ratio adjustment signal is used to reduce the frequency division gear of the frequency divider until it reaches a basic gear, and then the second clock selection signal is generated to reduce the second clock signal selected by the second clock selection unit. frequency of the signal until a minimum frequency is reached, and then the coefficient adjustment signal is generated to reduce the at least one of the first ratio and the second ratio.
  • the dynamic detection adjustment unit when the phase indication signal indicates that the phase of the carrier signal is ahead or behind the phase of the reference clock signal for a predetermined period, the dynamic detection adjustment unit first generates the coefficient adjustment signal to increase the at least one of the first ratio and the second ratio until a maximum ratio is reached, and then generate the second clock selection signal to increase the second clock signal selected by the second clock selection unit frequency until the highest frequency is reached, then a minimum second clock setting signal is generated to set the frequency of the second clock signal selected by the second clock selection unit to the lowest frequency, and the frequency division ratio adjustment signal is generated to increase the frequency of the second clock signal selected by the second clock selection unit. Describe the frequency division gear of the frequency divider.
  • the dynamic detection adjustment unit When the phase indication signal indicates that the phase of the carrier signal jumps between being ahead and lagging behind the phase of the reference clock signal and the jump reaches a predetermined number of times, the dynamic detection adjustment unit first generates The frequency division ratio adjustment signal is used to reduce the frequency division gear of the frequency divider until it reaches the basic gear, and when the frequency division gear reaches the basic gear, a maximum second clock setting signal is generated to reduce the frequency division gear.
  • the frequency of the second clock signal selected by the second clock selection unit is set to the highest frequency, and then the second clock selection signal is generated to reduce the frequency of the second clock signal selected by the second clock selection unit until the lowest frequency is reached,
  • the coefficient adjustment signal is then generated to reduce the at least one of the first ratio and the second ratio.
  • a phase tracking circuit may include: a frequency divider for dividing a clock signal to obtain a carrier signal; a phase detector for comparing the phases of the carrier signal and a reference clock signal to determine Generating a phase indication signal; a control module for adjusting a frequency division ratio of the frequency divider based on the phase indication signal; and a phase tuning module for adjusting the phase of the clock signal based on the phase indication signal.
  • the phase detector is a binary phase detector.
  • the binary phase detector When the phase of the carrier signal is ahead of the phase of the reference clock signal, the binary phase detector outputs a first indication signal.
  • the carrier signal When the phase of the signal lags behind the phase of the reference clock signal, the binary phase detector outputs a second indication signal.
  • control module includes: a dynamic detection and adjustment unit for detecting the phase indication signal generated by the phase detector and generating a frequency division ratio adjustment signal; and a frequency division ratio control unit for based on the The frequency division ratio adjustment signal controls the frequency division ratio of the frequency divider.
  • the dynamic detection adjustment The unit when the phase indication signal indicates that the phase of the carrier signal is ahead or behind the phase of the reference clock signal for a predetermined period, the dynamic detection adjustment The unit generates a first frequency division ratio adjustment signal, and the frequency division ratio control unit increases the frequency division gear of the frequency divider in response to the first frequency division ratio adjustment signal until it reaches the highest gear.
  • the phase indication signal indicates that the phase of the carrier signal jumps between being ahead and lagging behind the phase of the reference clock signal and the jump reaches a predetermined number of times
  • the dynamic detection adjustment unit When the phase indication signal indicates that the phase of the carrier signal jumps between being ahead and lagging behind the phase of the reference clock signal and the jump reaches a predetermined number of times, the dynamic detection adjustment unit generates a second The frequency division ratio adjustment signal, the frequency division ratio control unit decreases the frequency division gear of the frequency divider in response to the second frequency division ratio adjustment signal until it reaches the basic gear.
  • the frequency divider has the basic gear and at least one higher gear.
  • the basic gear has a basic frequency division ratio N
  • the higher gear has a higher frequency division ratio N+x or a lower frequency division ratio.
  • Nx is a preset positive integer
  • x is a positive integer smaller than N and the higher the gear, the greater the value of x.
  • the basic frequency division ratio N makes the frequency of the carrier signal equal to the frequency of the reference clock signal.
  • the phase tuning module includes: a digital loop filter, configured to generate a selection indication signal based on the phase indication signal; and a polyphase clock selection unit, configured to generate a selection indication signal from a polyphase signal based on the selection indication signal. Select a clock signal among the clock signals.
  • the multi-phase clock signal includes M clock signals of different phases, where M is an integer greater than one.
  • the selection indication signal generated by the digital loop filter represents one of M index values to instruct the polyphase clock selection unit to select a corresponding clock signal from the M clock signals of different phases.
  • the selection indication signal generated by the digital loop filter when the phase indication signal generated by the phase detector indicates that the phase of the carrier signal is ahead of the phase of the reference clock signal for a predetermined period, the selection indication signal generated by the digital loop filter The multi-phase clock selection unit is instructed to select a clock signal from the multi-phase clock signal that is lagging behind the phase of the currently selected clock signal.
  • the selection indication signal generated by the digital loop filter indicates that the polyphase
  • the clock selection unit selects a clock signal from the multi-phase clock signals that is ahead of the phase of the currently selected clock signal.
  • the digital loop filter includes: a proportional path, used to generate a first proportional signal that is in a first proportion to the phase indication signal; an integration path, used to generate a first proportional signal that is in a first proportion to the phase indication signal.
  • the signal is converted into a second proportional signal of a second proportion, and the second proportional signal is integrated to generate an integral signal;
  • an adder is used to add the first proportional signal and the integral signal to generate Output the sum value of the two; and a remainder unit configured to perform a remainder operation on the sum value received from the adder with respect to a predetermined value to generate the selection indication signal representing the remainder.
  • the predetermined value is equal to the number of clock signals with different phases included in the multi-phase clock signal.
  • the digital loop filter further includes at least one of the following: a first proportional adjustment unit disposed in the proportional path for adjusting the first proportion; and a first proportional adjustment unit disposed in the integral path.
  • the second proportion adjustment unit in is used to adjust the second proportion.
  • the first proportion adjustment unit and the second proportion adjustment unit use the same adjustment coefficient to adjust the first proportion and the second proportion in equal proportions.
  • the phase tracking circuit further includes: a coefficient control unit configured to control an adjustment coefficient for adjusting at least one of the first ratio and the second ratio.
  • a coefficient control unit configured to control an adjustment coefficient for adjusting at least one of the first ratio and the second ratio.
  • the dynamic detection adjustment unit When the phase indication signal indicates that the phase of the carrier signal jumps between being ahead and lagging behind the phase of the reference clock signal and the jump reaches a predetermined number of times, the dynamic detection adjustment unit generates a second Coefficient adjustment signal, the coefficient control unit decreases the adjustment coefficient in response to the second coefficient adjustment signal to reduce at least one of the first ratio and the second ratio until a base ratio is reached.
  • the dynamic detection adjustment unit when the phase indication signal indicates that the phase of the carrier signal is ahead or behind the phase of the reference clock signal for a predetermined period, the dynamic detection adjustment unit first generates the first coefficient adjusting a signal to increase at least one of the first ratio and the second ratio until a maximum ratio is reached, and then generating the first frequency division ratio adjustment signal to increase the frequency division of the frequency divider gear until the highest gear is reached.
  • the dynamic detection adjustment unit When the phase indication signal indicates that the phase of the carrier signal jumps between being ahead and lagging behind the phase of the reference clock signal and the jump reaches a predetermined number of times, the dynamic detection adjustment unit first generates The second frequency division ratio adjustment signal is used to reduce the frequency division gear of the frequency divider until it reaches the basic gear, and then the second coefficient adjustment signal is generated to reduce the first ratio and the second ratio. as stated in at least one until the base ratio is reached.
  • a phase tracking method may include: performing frequency division processing on a clock signal to obtain a carrier signal; comparing the phases of the carrier signal and a reference clock signal to generate a phase indication signal; and based on the phase indication signal.
  • the phase of the clock signal and the frequency division ratio of the frequency division process are adjusted so that the phase of the carrier signal is closer to the phase of the reference clock signal.
  • adjusting the frequency division ratio of the frequency division process based on the phase indication signal includes: when the phase indication signal indicates that the phase of the carrier signal is ahead or lagging behind the phase of the reference clock signal. And when continuing for a predetermined period, the frequency division gear of the frequency division process is increased until it reaches the highest gear; or when the phase indication signal indicates that the phase of the carrier signal is ahead of the phase of the reference clock signal and When there is a jump between further lags and the jump reaches a predetermined number of times, the frequency division gear of the frequency division process is reduced until it reaches the basic gear.
  • the frequency division processing has the basic gear and at least one higher gear.
  • the basic gear has a basic frequency division ratio N, and the higher gear has a higher frequency division ratio N+x or a lower frequency division ratio.
  • N-x N is a preset positive integer
  • x is a positive integer smaller than N and the higher the gear, the greater the value of x.
  • the basic frequency division ratio N makes the frequency of the carrier signal equal to the frequency of the reference clock signal.
  • adjusting the phase of the clock signal based on the phase indication signal includes: generating a selection indication signal based on the phase indication signal; and selecting a clock signal from multi-phase clock signals based on the selection indication signal.
  • the selection indication signal indicates that a phase of the multi-phase clock signal is selected to be lagging behind the currently selected clock signal.
  • the selection indication signal indicates that a phase of the multi-phase clock signal is selected to be further ahead than the currently selected clock signal. clock signal.
  • generating the selection indication signal based on the phase indication signal includes: generating a first ratio signal that is in a first ratio to the phase indication signal; generating a second ratio signal that is in a second ratio to the phase indication signal. ; Integrate the second proportional signal to obtain an integral signal; perform an addition operation on the first proportional signal and the integral signal to obtain their sum; The sum value is subjected to a remainder operation with respect to a predetermined value to generate the selection indication signal.
  • the predetermined value is equal to the number of clock signals with different phases included in the multi-phase clock signal.
  • the method further includes: adjusting at least one of the first ratio and the second ratio based on the phase indication signal.
  • adjusting at least one of the first ratio and the second ratio includes: when the phase indication signal indicates that the phase of the carrier signal is further ahead or lagging than the phase of the reference clock signal and for a predetermined period, increasing at least one of the first ratio and the second ratio until a maximum ratio is reached; or when the phase indication signal indicates that the phase of the carrier signal is greater than the reference clock When the phase of the signal transitions between being more advanced and more lagging and the transition reaches a predetermined number of times, at least one of the first ratio and the second ratio is reduced until a base ratio is reached.
  • the first ratio and the second ratio are first increased.
  • the at least one of the ratios is increased until the maximum ratio is reached, and then the frequency division gear of the frequency division processing is increased until the highest gear is reached.
  • the phase indication signal indicates that the phase of the carrier signal jumps between being ahead and behind the phase of the reference clock signal and the jump reaches a predetermined number of times, the frequency division process is first reduced. frequency gear until reaching the base gear, and then reducing at least one of the first ratio and the second ratio until the base ratio is reached.
  • a phase tracking circuit may include: a frequency divider for dividing a first clock signal to obtain a carrier signal; a phase detector for comparing the phases of the carrier signal and a reference clock signal , to generate a phase indication signal; a phase tuning module, configured to adjust the phase of the first clock signal based on the phase indication signal, so that the phase of the carrier signal is closer to the phase of the reference clock signal; and A control module configured to adjust the operating clock of the phase tuning module based on the phase indication signal to control the phase adjustment speed of the phase tuning module.
  • the phase detector is a binary phase detector.
  • the binary phase detector When the phase of the carrier signal is ahead of the phase of the reference clock signal, the binary phase detector outputs a first indication signal.
  • the carrier signal When the phase of the signal lags behind the phase of the reference clock signal, the binary phase detector outputs a second indication signal.
  • the phase tuning module includes: a digital loop filter for generating a first clock selection signal based on the phase indication signal; and a first clock selection unit for selecting a first clock based on the first clock signal.
  • the signal selects a clock signal from polyphase clock signals as the first clock signal.
  • control module includes: a dynamic detection and adjustment unit for detecting the phase indication signal generated by the phase detector and generating a second clock selection signal; and a second clock selection unit for detecting the phase indication signal generated by the phase detector and generating a second clock selection signal based on the The second clock selection signal selects one from a plurality of second clock signals as the operating clock of the digital loop filter.
  • the plurality of second clock signals include one or more frequency-divided signals provided by the frequency divider.
  • the plurality of second clock signals further include the first clock signal provided by the first clock selection unit.
  • the second clock selection signal generated by the dynamic detection adjustment unit
  • the second clock selection unit is instructed to select a clock signal with a higher frequency than the currently selected clock signal from the plurality of second clock signals.
  • the dynamic detection adjustment unit generates the first The second clock selection signal instructs the second clock selection unit to select a clock signal with a lower frequency than the currently selected clock signal from the plurality of second clock signals.
  • the carrier signal is a frequency-divided signal with the lowest frequency among multiple frequency-divided signals provided by the frequency divider.
  • the multi-phase clock signal includes M clock signals of different phases, where M is an integer greater than one.
  • the first clock selection signal generated by the digital loop filter represents one of M index values to instruct the first clock selection unit to select a corresponding clock signal from the M clock signals of different phases as the first clock signal.
  • the first clock generated by the digital loop filter when the phase indication signal generated by the phase detector indicates that the phase of the carrier signal is ahead of the phase of the reference clock signal for a predetermined period, the first clock generated by the digital loop filter The selection signal instructs the first clock selection unit to select a clock signal from the multi-phase clock signal that is lagging behind the phase of the currently selected clock signal.
  • the phase indication signal generated by the phase detector indicates that the phase of the carrier signal is greater than the phase of the reference clock signal
  • the first clock selection signal generated by the digital loop filter instructs the first clock selection unit to select a clock from the multi-phase clock signal that is more advanced in phase than the currently selected clock signal. Signal.
  • the digital loop filter includes: a proportional path for generating a first proportional signal in a first proportion to the phase indication signal; an integral path for generating a second proportional signal in a second proportion to the phase indication signal, and integrating the second proportional signal using an integrator to generate an integral signal; an adder for adding the first proportional signal and the integral signal to output a sum of the two; and a remainder unit for performing a remainder operation on the sum received from the adder with respect to a predetermined value to generate the first clock selection signal representing the remainder.
  • the second clock signal selected by the second clock selection unit is used as an operating clock of the integrator in the integration path, and the predetermined value is equal to the multi-phase clock signal having different phases.
  • the number of clock signals is used as an operating clock of the integrator in the integration path, and the predetermined value is equal to the multi-phase clock signal having different phases. The number of clock signals.
  • the digital loop filter further includes at least one of the following: a first proportional adjustment unit disposed in the proportional path for adjusting the first proportion; and a first proportional adjustment unit disposed in the integral path.
  • the second proportion adjustment unit in is used to adjust the second proportion.
  • the first proportion adjustment unit and the second proportion adjustment unit use the same adjustment coefficient to adjust the first proportion and the second proportion in equal proportions.
  • the phase tracking circuit further includes: a coefficient control unit configured to control at least one of the first ratio and the second ratio based on the coefficient adjustment signal generated by the dynamic detection adjustment unit. Adjustment coefficient.
  • the coefficient adjustment signal generated by the dynamic detection adjustment unit instructs the coefficient control unit to increase The adjustment coefficient is to increase the at least one of the first ratio and the second ratio until a maximum ratio is reached.
  • the coefficient generated by the dynamic detection adjustment unit The adjustment signal instructs the coefficient control unit to reduce the adjustment coefficient to reduce the at least one of the first ratio and the second ratio until a base ratio is reached.
  • the dynamic detection adjustment The unit first generates the coefficient adjustment signal to increase the at least one of the first ratio and the second ratio until a maximum ratio is reached, and then generates the second clock selection signal to increase the second
  • the clock selection unit selects the frequency of the second clock signal until it reaches the highest frequency.
  • the dynamic detection adjustment unit When the phase indication signal indicates that the phase of the carrier signal jumps between being ahead and lagging behind the phase of the reference clock signal and the jump reaches a predetermined number of times, the dynamic detection adjustment unit first generates The second clock selection signal is used to reduce the frequency of the second clock signal selected by the second clock selection unit until it reaches the lowest frequency, and then the coefficient adjustment signal is generated to reduce the first ratio and the second ratio. at least one of the above until the base ratio is reached.
  • a phase tracking method may include: a frequency divider divides a first clock signal to obtain a carrier signal; a phase detector compares the phase of the carrier signal and a reference clock signal to generate a phase indication signal ; The phase tuning module adjusts the phase of the first clock signal based on the phase indication signal, so that the phase of the carrier signal is closer to the phase of the reference clock signal; and the control module adjusts the phase of the first clock signal based on the phase indication signal.
  • the operating clock of the phase tuning module is adjusted to control the phase adjustment speed of the phase tuning module.
  • the phase tuning module adjusting the phase of the first clock signal based on the phase indication signal includes: using a digital loop filter to generate a first clock selection signal based on the phase indication signal; and using a first The clock selection unit selects one clock signal from multi-phase clock signals as the first clock signal based on the first clock selection signal.
  • control module adjusting the operating clock of the phase tuning module based on the phase indication signal includes: using a dynamic detection adjustment unit to detect the indication signal generated by the phase detector, and generating a second clock selection signal; and A second clock selection unit is used to select one from a plurality of second clock signals as the operating clock of the digital loop filter based on the second clock selection signal.
  • the plurality of second clock signals include one or more frequency-divided signals provided by the frequency divider.
  • the plurality of second clock signals further include the first clock signal provided by the first clock selection unit.
  • the second clock selection signal generated by the dynamic detection adjustment unit
  • the second clock selection unit is instructed to select a clock signal with a higher frequency than the currently selected clock signal from the plurality of second clock signals.
  • the phase When the bit indication signal indicates that the phase of the carrier signal transitions between being ahead and lagging behind the phase of the reference clock signal and the transition reaches a predetermined number of times, the second clock generated by the dynamic detection adjustment unit is selected. The signal instructs the second clock selection unit to select a clock signal with a lower frequency than the currently selected clock signal from the plurality of second clock signals.
  • the carrier signal is a frequency-divided signal with the lowest frequency among multiple frequency-divided signals provided by the frequency divider.
  • the first clock selection signal generated by the digital loop filter indicates that the The first clock selection unit selects a clock signal from the multi-phase clock signal that is lagging behind the phase of the currently selected clock signal.
  • the first clock selection signal generated by the digital loop filter indicates the first clock selection unit A clock signal is selected from the multi-phase clock signals that is more advanced in phase than the currently selected clock signal.
  • using a digital loop filter to generate a first clock selection signal based on the phase indication signal includes: using a proportional path to generate a first proportional signal that is in a first proportion to the phase indication signal; using an integral path to generate a second proportional signal that is in a second proportion to the phase indication signal, and the second proportional signal is integrated using an integrator disposed in the integration path to generate an integral signal; an adder is used to calculate the second proportional signal.
  • a proportional signal and the integral signal are added together to output the sum of the two; and a remainder unit is used to perform a remainder operation on the sum with respect to a predetermined value to generate the first clock selection signal representing the remainder.
  • the second clock signal selected by the second clock selection unit is used as an operating clock of the integrator in the integration path to control the speed of integrating the second proportional signal, and the predetermined value is equal to The number of clock signals with different phases included in the multi-phase clock signal.
  • using a digital loop filter to generate the first clock selection signal based on the phase indication signal further includes at least one of the following steps: adjusting the first proportional adjustment unit disposed in the proportional path. a first proportion; and adjusting the second proportion using a second proportion adjustment unit disposed in the integral path.
  • the first proportion adjustment unit and the second proportion adjustment unit use the same adjustment coefficient to adjust the first proportion and the second proportion in equal proportions.
  • the method further includes: using a coefficient control unit to adjust the The coefficient adjustment signal generated by the entire unit is used to control an adjustment coefficient for adjusting at least one of the first ratio and the second ratio.
  • the coefficient adjustment signal generated by the dynamic detection adjustment unit instructs the coefficient control unit to increase The adjustment coefficient is to increase the at least one of the first ratio and the second ratio until a maximum ratio is reached.
  • the coefficient generated by the dynamic detection adjustment unit The adjustment signal instructs the coefficient control unit to reduce the adjustment coefficient to reduce the at least one of the first ratio and the second ratio until a base ratio is reached.
  • the dynamic detection adjustment unit when the phase indication signal indicates that the phase of the carrier signal is ahead or behind the phase of the reference clock signal for a predetermined period, the dynamic detection adjustment unit first generates the coefficient adjustment signal to increase at least one of the first ratio and the second ratio until a maximum ratio is reached, and then generate the second clock selection signal to increase the second clock selected by the second clock selection unit frequency of the signal until it reaches the highest frequency.
  • the dynamic detection adjustment unit When the phase indication signal indicates that the phase of the carrier signal jumps between being ahead and lagging behind the phase of the reference clock signal and the jump reaches a predetermined number of times, the dynamic detection adjustment unit first generates The second clock selection signal is used to reduce the frequency of the second clock signal selected by the second clock selection unit until it reaches the lowest frequency, and then the coefficient adjustment signal is generated to reduce the first ratio and the second ratio. at least one of the above until the base ratio is reached.
  • an electronic device which may include any one of the above phase tracking circuits.
  • FIG. 1 shows a schematic diagram of a phase tracking circuit according to an embodiment of the present invention.
  • FIG. 2 shows a schematic diagram of a phase tracking circuit according to an embodiment of the present invention.
  • FIG. 3 shows a schematic diagram of a phase tracking circuit according to an embodiment of the present invention.
  • FIG. 4 shows a schematic diagram of a phase tracking circuit according to an embodiment of the present invention.
  • Figure 5 shows a schematic diagram of a digital loop filter according to an embodiment of the present invention.
  • FIG. 6 shows a schematic diagram of an integrated signal in a digital loop filter according to an embodiment of the present invention.
  • FIG. 7 shows a schematic diagram of adjusting the phase by changing the frequency division ratio according to an embodiment of the present invention.
  • Figure 8 shows a schematic diagram of frequency division gear design according to an embodiment of the present invention.
  • Figure 9 shows a flow chart of a phase tracking method according to an embodiment of the present invention.
  • FIG. 10 shows a flow chart of a phase adjustment process of a first clock signal according to an embodiment of the present invention.
  • FIG. 11 shows a flow chart of the frequency adjustment process and/or the frequency division ratio adjustment process of the second clock signal according to an embodiment of the present invention.
  • FIG. 12 shows a flowchart of a process of generating a second clock selection signal and/or a frequency division ratio adjustment signal according to an embodiment of the present invention.
  • FIG. 13 shows a flowchart of a process of generating a first clock selection signal according to an embodiment of the present invention.
  • FIG. 14 shows a flow chart of a process of coefficient adjustment and integration clock frequency adjustment according to an embodiment of the present invention.
  • FIG. 15 shows a flow chart of a process of coefficient adjustment and frequency division gear adjustment according to an embodiment of the present invention.
  • FIG. 16 shows a flow chart of a process of combining coefficient adjustment, integral clock frequency adjustment and frequency division gear adjustment according to an embodiment of the present invention.
  • FIG. 17 shows a flowchart of a process of combining coefficient adjustment, integral clock frequency adjustment and frequency division gear adjustment according to an embodiment of the present invention.
  • Figure 18 shows a schematic diagram of an electronic device according to an embodiment of the present invention.
  • phase tracking technologies for NFC card simulation devices in active load modulation (ALM) mode include technical solutions based on passive matching networks and technical solutions using all-digital phase-locked loops (ADPLL).
  • the adjustment of the passive matching network is not linear.
  • the steps of the phase adjustment are inconsistent at different resistance values, making it difficult to achieve high-precision adjustment within a large phase difference range (such as 0 degrees to 180 degrees). all.
  • resistance adjustment will also change the impedance of the chip, which will have certain adverse effects on wireless communications.
  • the all-digital phase-locked loop has a complex design and high cost.
  • the frequency and phase information generated in the card simulation mode comes entirely from the clock recovered from the card reader signal, and the clock recovered from the card reader signal is often intermittent. of.
  • the magnetic field disappears when the data is at a low level; for example, when the NFC card simulation device itself transmits a signal, an excessively large transmit signal will drown the magnetic field signal of the card reader. Therefore, under the condition of intermittent reference clock, the loop locking speed of the phase-locked loop is very demanding, because there is only a very short time for frequency and phase locking, and this problem is difficult to solve.
  • fast locking means a larger loop bandwidth, which brings more phase noise introduced by the reference clock, which will affect circuit performance.
  • reducing the loop bandwidth can partially improve phase noise performance, it will Difficult to achieve fast locking requirements.
  • phase tracking technology requires fast phase tracking and locking within a large phase difference range, and high tracking accuracy is expected. Furthermore, considering applications in battery-powered portable electronic devices, small power consumption during phase tracking and locking is also expected, which poses challenges to existing phase tracking technologies.
  • FIG. 1 shows a schematic diagram of a phase tracking circuit 100 according to an embodiment of the present invention.
  • the phase tracking circuit 100 includes a frequency divider 110 , a phase detector 120 , a phase tuning module 130 and a control module 140 .
  • the frequency divider 110 can divide the high-frequency clock signal (hereinafter referred to as the first clock signal) to obtain a divided low-frequency clock signal, which can be used as a carrier signal and is compared with the frequency-divided low-frequency clock signal recovered from the magnetic field of the card reader.
  • the clock frequency is the same.
  • the frequency of the high-frequency signal input to the frequency divider 110 may be N times the frequency of the frequency-divided signal output by the frequency divider 110 , where N is the frequency division ratio of the frequency divider 110 . It should be understood that in this application, "high frequency” and “low frequency” are relative concepts that describe the relative magnitude of frequency, but do not limit the absolute magnitude of frequency, that is, the frequency range in any sense.
  • the phase detector 120 may compare the phases of the carrier signal output by the frequency divider 110 and the reference clock signal, and output a phase indication signal.
  • the reference clock signal may be a clock signal recovered from the NFC card reader, and the phase tracking circuit 100 is used to make the phase of the carrier signal track or be close to the phase of the reference clock signal.
  • the phase tuning module 130 can adjust the phase of the first clock signal provided to the frequency divider 110 based on the phase indication signal output by the phase detector 120, so that the phase of the carrier signal output by the frequency divider 110 tracks/is closer to the reference clock signal. phase.
  • the control module 140 may adjust the phase tuning based on the phase indication signal output by the phase detector 120 At least one of the frequency of the operating clock signal of the module 130 (hereinafter referred to as the second clock signal) and the frequency division ratio of the frequency divider 110 thereby controls the phase adjustment speed of the phase tuning module 130, which will be described in further detail below.
  • FIG. 2 illustrate exemplary implementations 100a, 100b, and 100c, respectively, of phase tracking circuit 100.
  • the phase tuning module 130 may include a digital loop filter (DLF) 132 and a first clock selection unit 134, and optionally may also include a coefficient control unit 136.
  • the control module 140 may include a dynamic detection adjustment unit 142 and a second clock selection unit 144.
  • the control module 140 may include a dynamic detection adjustment unit 142 and a frequency division ratio control unit 146 .
  • the control module 140 may include a dynamic detection adjustment unit 142 , a second clock selection unit 144 and a frequency division ratio control unit 146 .
  • the phase tracking circuit 100a shown in FIG. 2, the phase tracking circuit 100b shown in FIG. 3, and the phase tracking circuit 100c shown in FIG. 4 may each be referred to as the phase tracking circuit 100.
  • the phase detector 120 may be a binary phase detector (BBPD).
  • BBPD binary phase detector
  • the phase detector 120 When the phase of the carrier signal (or divided clock signal) is ahead of the phase of the reference clock signal, the phase output by the phase detector 120
  • the indication signal may be a high level "1"; when the phase of the carrier signal lags behind the phase of the reference clock signal, the phase indication signal output by the phase detector 120 may be a low level "-1", or vice versa.
  • the digital loop filter (DLF) 132 can detect the phase indication signal output by the phase detector 120, and based on the relative phase relationship between the indicated carrier signal and the reference clock signal, generate a first clock selection signal to control the first clock selection unit 134 Selects a corresponding clock signal from the multi-phase clock signals.
  • the digital loop filter 132 may instruct the first clock selection unit 134 to select a clock signal with a lagging phase from the multi-phase clock signals; when When the phase detector 120 indicates that the phase of the carrier signal lags behind that of the reference clock signal, the digital loop filter 132 may instruct the first clock selection unit 134 to select a clock signal with a more advanced phase from the multi-phase clock signals.
  • the phase indication signal output by the phase detector 120 indicates that the phase of the carrier signal jumps back and forth between leading and lagging the phase of the reference clock signal, the clock signal selected by the first clock selection unit 134 jumps back and forth between the two signals. change, the overall equivalent is that the phase remains unchanged, thereby achieving a phase locked state.
  • FIG. 5 shows a schematic diagram of a digital loop filter 200 according to an embodiment of the present invention.
  • the loop filter 200 may be used in the digital loop filter 132 in the phase tracking circuit 100 shown in FIGS. 2-4.
  • the digital loop filter 200 may include a proportional path 210 and an integral path 220 , both of which receive the phase indication signal output by the phase detector 120 as inputs at the first input port In-1.
  • the proportional path 210 and the integral path 220 may generate a first proportional signal at a first proportion "a" to the phase indication signal and a second proportional signal at a second proportion "p" to the phase indication signal, respectively.
  • the proportional path 210 may include a first register 212 in which a first proportional coefficient "a" is stored to output a first proportional signal;
  • the integral path 220 may include a second register 222 in which a second proportional coefficient "p" is stored. , to output the second proportional signal.
  • the first proportional signal generated by the proportional path 210 and the second proportional signal generated by the integral path 220 can also be adjusted.
  • the proportional path 210 may include a first proportional adjustment unit such as a multiplier 214 that multiplies the first proportional signal using an adjustment factor to generate an adjusted first proportional signal;
  • the integral path 220 may include a second proportional adjustment unit such as A multiplier 224 multiplies the second proportional signal using the adjustment factor to generate an adjusted second proportional signal.
  • a multiplier 224 multiplies the second proportional signal using the adjustment factor to generate an adjusted second proportional signal.
  • the first proportional adjustment unit 214 and the second proportional adjustment unit 224 may receive the same adjustment factor from the second input port In-2, so as to adjust the first proportional signal and the second proportional signal. Adjust proportionally. In other embodiments, the first proportion adjustment unit 214 and the second proportion adjustment unit 224 may also receive different adjustment factors to perform different adjustments on the first proportion signal and the second proportion signal, or may only set the first proportion. Either one of the adjustment unit 214 and the second proportional adjustment unit 224 adjusts one of the first proportional signal and the second proportional signal.
  • the adjusted second proportional signal may be integrated in the integrator 226 to generate an integrated signal.
  • the integrator 226 may receive the integration clock signal from the third input port In-3 to perform integration processing on the adjusted second proportional signal according to the integration clock.
  • Figure 6 shows a schematic diagram of the integrated signal generated by the integrator 226. As shown in Figure 6, based on the third input port Based on the integrated clock signal received on In-3, the integrator 226 integrates the adjusted second proportional signal “px” or “-px”, where p is the second proportional coefficient and x is the adjustment coefficient.
  • the integral signal When the adjusted second proportional signal is "px”, assuming that p is a positive number (p can also be a negative number), the integral signal gradually increases with the integration period, and the increase step is "px". When the adjusted second proportional signal is "-px”, the integral signal gradually decreases with the integration period, and the decreasing step is "-px”. It can be understood that when the adjusted second proportional signal changes from “px” to "-px”, the integral signal changes from increasing to decreasing; when the adjusted second proportional signal changes from "-px” to "px” , the integral signal changes from decreasing to increasing. It can be understood from FIG. 5 that the increasing or decreasing speed of the integral signal is related to the second proportional coefficient p, the adjustment coefficient x and the frequency of the integral clock signal.
  • the integral signal output by the integrator 226 in the integral path 220 and the first proportional signal output by the proportional path 210 may be added in the adder 232 to obtain their sum. It can be understood that when the phase indication signal output by the phase detector 120 remains unchanged, the integrated signal output by the integrator 226 increases or decreases over time, and the first proportional signal output by the proportional path 210 remains unchanged over time, so that the adder The sum of the 232 output increases or decreases over time.
  • the sum value output by the adder 232 may be subjected to a remainder operation with respect to the predetermined value M in a remainder (Mod) unit 234, thereby generating a first clock selection signal representing the remainder, which is output at the output port Out.
  • a remainder (Mod) unit 234 As the integrated value output by the integrator 226 increases, the remainder value represented by the first clock selection signal output by the remainder unit 234 increases from 0 to 1, then continues to increase until M-1, and then continues to increase to 0 , so the cycle changes. Or, when the integrated value output by the integrator 226 decreases, the remainder value represented by the first clock selection signal output by the remainder unit 234 decreases from 0 to M-1, then decreases to M-2, and continues to decrease to 0. , so the cycle changes.
  • the remainder value represented by the first clock selection signal is used as an index for the first clock selection unit 134 to select a clock signal corresponding to the index value from M clock signals of different phases as the clock signal provided to the frequency divider 110 first clock signal.
  • the proportional path 210 can also be omitted and only the integral path 220 is used.
  • the first clock selection signal including an index value (ie, remainder) can also be generated to select a corresponding clock signal from the multi-phase clock signal. clock signal.
  • the changing speed of the index value represented by the first clock selection signal output by the digital loop filter 200 is, that is, the phase of the first clock signal selected by the first clock selection unit 134 from the multi-phase clock signal.
  • the speed of change depends on the integration speed of integrator 226, that is is the frequency of the integrated clock signal, the values of the first proportional coefficient a and the second proportional coefficient p, and the value of the adjustment coefficient x. Therefore, by adjusting the frequency of the integration clock signal and the value of the adjustment factor x, the phase adjustment speed of the phase tracking circuit 100 can be adjusted, which will be described in further detail below.
  • the first clock selection unit 134 selects one clock signal from M clock signals of different phases based on the first clock selection signal output by the digital loop filter 132 as the third clock signal provided to the frequency divider 110 a clock signal.
  • the M clock signals with different phases can have a phase difference of 360°/M.
  • the phases of the M clock signals can be 0°, 30°, 60°, 90°, 120°, and 150 respectively. °, 180°, 210°, 240°, 270°, 300° and 330°, and of course other phase values evenly distributed within the 360° range.
  • phase detector 120 when the output of the phase detector 120 is "1", it means that the phase of the carrier signal (ie, the frequency-divided signal) provided by the frequency divider 110 is ahead of the phase of the reference clock signal.
  • the remainder represented by the first clock selection signal output by the digital loop filter 132 gradually increases.
  • the remainder value increases by one after a predetermined integration period, so that the first clock selection signal output by the digital loop filter 132 increases by one.
  • a clock selection unit 134 selects a clock signal with a more delayed phase from M (M is an integer greater than 1) clock signals with different phases, so that the phase of the carrier signal provided by the frequency divider 110 also moves backward.
  • the output of the phase detector 120 becomes "-1".
  • the integrated value output by the integrator 226 gradually decreases over time, and the remainder represented by the first clock selection signal output by the digital loop filter 132 also gradually decreases.
  • the remainder value decreases by one after a predetermined integration period, so that the A clock selection unit 134 selects a clock signal with a more advanced phase from M clock signals with different phases, so that the phase of the carrier signal provided by the frequency divider 110 also moves forward.
  • phase detector 120 When the output of the phase detector 120 changes back and forth between "1" and "-1", it indicates that the clock signal selected by the first clock selection unit 134 is one clock signal ahead of the reference clock signal in phase and one phase ahead of the reference clock signal.
  • the lagging clock signal changes back and forth, and the overall equivalent is that the phase of the carrier signal is equal to or closest to the phase of the reference clock signal, thereby achieving a phase lock state.
  • the phase steps between the M clock signals selected by the first clock selection unit 134 are 360°/M.
  • the phase steps between adjacent frequency division signals are ( That is, the phase difference) becomes 360°/(M*N), where N is the frequency division ratio of the frequency divider 110, because the pulse width of the frequency division signal is N times the pulse width of the clock signal before frequency division.
  • N the frequency division ratio of the frequency divider 110
  • the signal frequency of the NFC card reader is 13.56 MHz and the frequency of the polyphase clock signal is 867.84 MHz.
  • other frequency division ratios can also be used.
  • the phase step between polyphase clock signals is 30°, then the phase step of the divided signal becomes 0.46875°, so that accurate phase adjustment and tracking can be achieved.
  • the index value represented by the first clock selection signal increases from 0 to 11, the phase of the clock signal selected by the first clock selection unit 134 is delayed by 330°, and the phase of the divided clock signal is delayed by 5.15625°; then the index The value changes from 11 to 0, the phase of the clock signal selected by the first clock selection unit 134 continues to be delayed by 30°, and the phase of the divided clock signal continues to be delayed by 0.46875°.
  • cyclically increasing the index value can make the phase of the frequency-divided signal continuously move backward; similarly, cyclically decreasing the index value can make the phase of the frequency-divided signal continuously move forward. In this way, the phase of the frequency-divided signal (i.e., carrier signal) can be changed within a wide range.
  • phase adjustment that is, the phase tracking accuracy of the phase tracking circuit 100
  • the speed of adjusting the phase is slow, and the step of each adjustment is 360°/(M*N), so it may take a long time to achieve loop locking, and the higher the phase adjustment accuracy, the lower the accuracy of the phase adjustment for a given phase difference.
  • embodiments of the present invention also speed up the phase adjustment by adjusting the proportional coefficient and integration frequency of the digital loop filter 132, which will be described in further detail below.
  • the dynamic detection adjustment unit 142 may detect the phase indication signal generated by the phase detector 120 and generate a coefficient adjustment signal provided to the coefficient control unit 136 to control the first proportional coefficient of the digital loop filter 132 a and the second proportional coefficient p, and also generate at least one of the second clock selection signal supplied to the second clock selection unit 144 and the frequency division ratio adjustment signal supplied to the frequency division ratio control unit 146 .
  • the second clock selection unit 144 may select one of the plurality of second clock signals as the operating clock of the digital loop filter 132 based on the second clock selection signal, and the frequency division ratio control unit may control the frequency division based on the frequency division ratio adjustment signal.
  • the frequency division ratio of the converter 110 which will be explained in detail below.
  • the coefficient control unit 136 may control the second input port In-2 provided to the digital loop filter 132/200 in response to the coefficient adjustment signal provided by the dynamic detection adjustment unit 142. The size of the adjustment coefficient for adjusting at least one of the first proportional coefficient a and the second proportional coefficient p.
  • the dynamic detection adjustment unit 142 detects that the phase detector 120 indicates that the phase of the carrier signal is larger than the reference clock
  • the phase of the signal is more advanced or lagging (the phase indicator signal is "1" or "-1") and continues for a predetermined number of cycles
  • the unit 142 may generate a coefficient adjustment signal to instruct the coefficient control unit 136 to increase the adjustment coefficient, thereby increasing at least one of the first proportional coefficient a and the second proportional coefficient p, and speeding up the phase adjustment speed. This operation can be repeated until the maximum scaling factor is reached.
  • the dynamic detection adjustment unit 142 detects that the phase detector 120 indicates that the phase of the carrier signal jumps between being further ahead and lagging behind the phase of the reference clock signal (the phase indication signal jumps between "1" and "-1" ) and the jump reaches a predetermined number of times, it can be considered that the phase of the carrier signal has been adjusted to be close to the phase of the reference clock signal.
  • the dynamic detection adjustment unit 142 can generate a coefficient adjustment signal to instruct the coefficient control unit 136 to reduce the adjustment coefficient, thereby Reduce at least one of the first proportional coefficient a and the second proportional coefficient p, and reduce the phase adjustment speed until the lowest proportional coefficient is reached. It can be understood that increasing and decreasing the proportional coefficients a and p can change the phase adjustment speed, but will not affect the phase adjustment accuracy.
  • the second clock selection unit 144 may select a clock signal from a plurality of second clock signals based on the second clock selection signal provided by the dynamic detection adjustment unit 142 as the operating clock of the digital loop filter 132, or more specifically , as the operating clock of the integrator 226 in the digital loop filter 132.
  • the plurality of second clock signals selected by the second clock selection unit 144 may include one or more frequency division signals provided by the frequency divider 110 .
  • the frequency divider 110 can be a multi-stage 2/3 frequency divider, including a cascade structure of multiple 2/3 frequency divider units. Each stage can provide a 2-frequency divider signal or a 3-frequency divider signal, so that the frequency divider Multiple stages of 110 can provide multiple frequency division signals with different frequency division ratios.
  • the frequency division signal provided by the frequency divider 110 to the phase detector 120 as the carrier signal may be the frequency division signal with the maximum frequency division ratio (that is, the lowest frequency), that is, the final frequency division signal of the frequency divider 110 stage output frequency division signal.
  • the plurality of second clock signals selected by the second clock selection unit 144 may also include a first clock signal provided by the first clock selection unit 134, which has a higher frequency than the frequency division signal provided by the frequency divider 110. Frequency of.
  • the plurality of second clock signals selected by the second clock selection unit 144 may also be provided by other circuits. It is understood that the second clock selection unit 144 is not limited to the embodiment described here.
  • the second clock selection unit 144 may also be implemented as a voltage controlled oscillator (VCO), which adjusts the frequency of the output signal according to the voltage signal provided by the dynamic detection adjustment unit 142 .
  • VCO voltage controlled oscillator
  • the phase detector 120 when the phase detector 120 indicates that the phase of the carrier signal is ahead or behind the phase of the reference clock signal (the phase indication signal is "1" or "-1") and continues for a predetermined period period (which may be the same as or different from the predetermined period number used for scaling coefficient adjustment), it can be considered that the phase difference between the carrier signal and the reference clock signal may be larger.
  • the second clock generated by the dynamic detection adjustment unit 142 is selected.
  • the signal may instruct the second clock selection unit 144 to select a higher frequency clock signal, thereby speeding up the integration operation in the digital loop filter 132 so that the digital loop filter 132 can adjust the clock signal selected by the first clock selection unit 134 faster.
  • the phase of the first clock signal when the phase detector 120 indicates that the phase of the carrier signal is ahead or behind the phase of the reference clock signal (the phase indication signal is "1" or "-1") and continues for a predetermined period period (which may be the same as or different from the predetermined period number used for scaling coefficient adjustment), it can be considered that the phase difference
  • This operation may be repeated to continuously increase the frequency of the clock signal selected by the second clock selection unit 144 until the highest frequency is reached.
  • the phase detector 120 indicates that the phase of the carrier signal transitions between leading and lagging the phase of the reference clock signal (the phase indicating signal transitions between "1" and "-1") and the transition reaches a predetermined number of times (which may be the same as or different from the predetermined number of jumps used for scaling coefficient adjustment), it can be considered that the phase of the carrier signal has been adjusted to near the phase of the reference clock signal.
  • the second clock generated by the dynamic detection adjustment unit 142 is selected.
  • the signal may instruct the second clock selection unit 144 to select a lower frequency clock signal, thereby slowing down the integration operation in the digital loop filter 132 so that the digital loop filter 132 adjusts the first clock signal selected by the first clock selection unit 134 .
  • the phase of the clock signal slows down. This operation may be repeated to continuously reduce the frequency of the clock signal selected by the second clock selection unit 144 until the lowest frequency is reached. It can be understood that when the integration frequency increases, the power consumption of the digital loop filter 132 will also increase; when the integration frequency decreases, the power consumption of the digital loop filter 132 will decrease.
  • FIG. 7 schematically shows the influence on the phase of the carrier signal output by the frequency divider 110 when the frequency division ratio N of the frequency divider 110 changes.
  • the high level and the low level respectively correspond to 32 pulses of the high-frequency clock signal before frequency division.
  • the system design frequency division ratio is a frequency division ratio that makes the frequency of the carrier signal equal to the frequency of the reference clock signal. Therefore, the system design frequency division ratio is also called the basic frequency division ratio.
  • the starting point of the next period's frequency division 65 signal is one short/high frequency pulse later than the starting point of the frequency division 64 signal, which is 1/64 of the period of the frequency division 64 signal.
  • the phase lags 360°/64 5.625°; in the next cycle, the phase of the 65-frequency signal lags 11.25° compared to the 64-frequency signal, and so on.
  • the step of advance or lag is (360°*x)/N, and the value of x can be set as needed. Therefore, by changing the frequency division ratio, the phase of the carrier signal can be quickly adjusted, thereby speeding up the phase adjustment speed.
  • the frequency division ratio control unit 146 may control the frequency division ratio of the frequency divider 110 based on the frequency division ratio adjustment signal provided by the dynamic detection adjustment unit 142 .
  • the frequency division ratio of the frequency divider 110 can be set to multiple gears, an example of which is shown in FIG. 8 .
  • Figure 8 shows a total of four gears 0-3, but more or less gears can also be used, such as two gears, three gears, five gears, etc.
  • Gear 0 is also called the basic gear, which corresponds to the basic frequency division ratio N, that is, the frequency division ratio that makes the frequency of the carrier signal equal to the frequency of the reference signal.
  • the frequency division ratio of the frequency divider 110 should be the basic frequency division ratio N.
  • the frequency division ratio of higher gears is N ⁇ x.
  • the frequency division ratio of gear 1 can be N ⁇ 1
  • the frequency division ratio of gear 2 can be N ⁇ 2
  • the frequency division ratio of gear 3 can be N ⁇ 3, and so on.
  • the frequency division ratio of the gear can be N+x to use a larger frequency division ratio so that the phase of the carrier signal lags; when the phase indication signal When the phase of the indicated carrier signal lags behind the phase of the reference clock signal, the frequency division ratio of the gear can be N-x to use a smaller frequency division ratio to advance the phase of the carrier signal.
  • the phase detector 120 when the phase detector 120 indicates that the phase of the carrier signal is ahead or lagging behind the phase of the reference clock signal (the phase indication signal is "1" or "-1") and continues for a predetermined number of cycles (can be compared with (the predetermined number of cycles used for proportional coefficient adjustment and integral clock frequency adjustment is the same or different), indicating that the phase difference between the carrier signal and the reference clock signal is large, at this time the dynamic detection adjustment unit 142 can generate a frequency division ratio adjustment signal to indicate The frequency division ratio control unit 146 increases the frequency division gear of the frequency divider 110 . This operation can be repeated to continuously increase the phase adjustment step of the carrier signal until the highest gear is reached.
  • the phase detector 120 When the phase detector 120 indicates that the phase of the carrier signal transitions between leading and lagging the phase of the reference clock signal (the phase indicating signal transitions between "1" and "-1") and the transition reaches a predetermined number of times (which may be the same as or different from the predetermined number of jumps used for proportional coefficient adjustment and integral clock frequency adjustment), indicating that the phase of the carrier signal has been adjusted to near the phase of the reference clock signal.
  • the dynamic detection adjustment unit 142 can generate The frequency division ratio adjustment signal instructs the frequency division ratio control unit 146 to reduce the frequency division gear of the frequency divider 110 to reduce the phase adjustment step of the carrier signal until the basic gear is reached.
  • the dynamic detection adjustment unit 142 in addition to instructing the frequency division ratio control unit 146 to adjust the frequency division ratio signal to increase or decrease the frequency division gear of the frequency divider 110, the dynamic detection adjustment unit 142 also instructs the frequency division ratio control unit 146 to adjust the current carrier signal phase. status, that is, leading or lagging the phase of the reference clock signal, so the frequency division ratio control unit 146 can control whether the frequency division ratio of the frequency divider 110 in each frequency division gear is N+x or N-x.
  • the following example illustrates the adjustment process of the frequency division gear.
  • divider 110 is at base Basic gear (gear 0)
  • the frequency division ratio is 64 at this time.
  • the dynamic detection adjustment unit 142 detects that the output of the phase detector 120 is “1” and continues for, for example, 4 cycles, it instructs the frequency division ratio control unit 146 to increase the frequency division gear of the frequency divider 110 to gear 1.
  • the frequency dividing ratio of the frequency divider 110 becomes 65.
  • the dynamic detection adjustment unit 142 detects that the output of the phase detector 120 is still "1" and continues for, for example, 4 cycles, it instructs the frequency division ratio control unit 146 to increase the frequency division gear of the frequency divider 110 to Bit 2, at this time the frequency division ratio of the frequency divider 110 becomes 66. This operation can be repeated until the frequency divider 110 reaches the highest gear 3, at which time the frequency division ratio of the frequency divider 110 becomes 67 and the phase adjustment step reaches the maximum.
  • the phase of the carrier signal continuously moves backward. When it becomes lagging behind the phase of the reference clock signal, the output of the phase detector 120 changes from “1” to “-1”.
  • the frequency divider 110 is still Maintain the highest gear 3, but the frequency division ratio changes from 67 to 61, and the phase of the carrier signal moves forward, causing its phase to become ahead of the phase of the reference clock signal, and the output of the phase detector 120 changes from "-1" changes to "1", and the frequency division ratio of the frequency divider 110 changes from 61 to 67.
  • the dynamic detection adjustment unit 142 detects that the output of the phase detector 120 jumps between “1” and “-1” for a predetermined number of times, such as 6 times, it instructs the frequency division ratio control unit 146 to reduce the division ratio of the frequency divider 110 .
  • frequency gear, from gear 3 to gear 2 and the phase adjustment step decreases. This operation can be repeated until the frequency divider 110 reaches the basic gear and the frequency division ratio is 64. At this time, the frequency division ratio no longer affects the phase of the carrier signal, and the frequency of the carrier signal is equal to the reference clock signal.
  • the frequency division ratio N of the frequency divider 110 When the frequency division ratio N of the frequency divider 110 is adjusted, the frequency division signals output by each stage in the frequency divider 110 will be affected, so the second clock selection unit 144 provides it to the integrator 226 in the digital loop filter 132 The frequency of the integrating clock signal is also affected.
  • the function of adjusting the frequency division ratio is to move the phase of the carrier signal forward or backward in larger steps, and the change in the integral clock frequency of the integrator 226 only affects the first output of the first clock selection unit 134.
  • the phase change speed of the clock signal does not affect the phase change direction (eg, increase or decrease) of the first clock signal.
  • the adjustment step of the carrier signal phase by the digital loop filter 132 is much smaller than the adjustment step of the carrier signal phase caused by the change of the frequency division ratio of the frequency divider 110 . Therefore, when adjusting the frequency division ratio of the frequency divider 110, the change in the carrier signal phase adjustment speed caused by the change in the integration clock frequency of the integrator 226 will not have any substantial negative impact on the entire phase adjustment process.
  • phase adjustment speed control implemented by the proportional coefficient adjustment and integration clock frequency adjustment of the digital loop filter 132 and the frequency division ratio adjustment of the frequency divider 110 can be used individually or in combination.
  • the dynamic detection adjustment unit 142 may first be generated to increase at least one of the first proportional coefficient a and the second proportional coefficient p until the maximum proportional coefficient is reached; and then a second clock selection signal may be generated to increase the first proportional coefficient selected by the second clock selection unit 144 .
  • the frequency of the clock signal is adjusted until it reaches the highest frequency; and then the frequency division ratio adjustment signal is regenerated to increase the frequency division gear of the frequency divider 110 .
  • the dynamic detection adjustment unit 142 may generate the frequency component ratio adjustment signal to reduce the frequency divider frequency division gear of 110 until it reaches the basic gear; then generate a second clock selection signal to reduce the frequency of the second clock signal selected by the second clock selection unit 144 until it reaches the lowest frequency; and then generate a coefficient adjustment signal to reduce The at least one of the first proportionality coefficient a and the second proportionality coefficient p is reduced until a base/minimum proportionality coefficient is reached. This process is discussed in further detail below and is only briefly described here.
  • the integral clock frequency when speeding up the phase adjustment speed, first increase the proportional coefficient, then increase the integral clock frequency, and finally increase the frequency division ratio; when reducing the phase adjustment speed, first reduce the frequency division ratio, Then reduce the integration clock frequency and finally reduce the proportional coefficient.
  • the integration clock frequency when the integration clock frequency is increased, the power consumption of the phase tracking circuit 100 will also increase, and the impact of the integration clock frequency on the phase adjustment speed is lower than the impact of the frequency division ratio change on the phase adjustment speed. Therefore, in one embodiment, when the frequency division level is increased, the integral clock frequency can be set to the lowest to save power consumption.
  • the dynamic detection adjustment unit 142 may first generate a coefficient adjustment signal to increase the first proportional coefficient a and At least one of the second proportional coefficients p until the maximum proportional coefficient is reached; then a second clock selection signal is generated to increase the frequency of the second clock signal selected by the second clock selection unit 144 until the highest frequency is reached; and then the frequency component is regenerated ratio adjustment signal to increase the frequency division gear of the frequency divider 110, and when the frequency division gear is increased for the first time, a minimum second clock setting signal is generated to set the frequency of the second clock signal selected by the second clock selection unit 144 to lowest frequency.
  • the dynamic detection adjustment unit 142 may generate the frequency component ratio adjustment signal to reduce the frequency divider
  • the frequency division gear is 110 until the basic gear is reached, and when the basic gear is reached, a maximum second clock setting signal is generated to set the frequency of the second clock signal selected by the second clock selection unit 144 to the highest frequency; then The second clock selection signal is generated to reduce the frequency of the second clock signal selected by the second clock selection unit 144 until reaching the lowest frequency; and then a coefficient adjustment signal is generated to reduce the first proportional system. said at least one of the number a and the second proportional coefficient p until the base/minimum proportional coefficient is reached. In this way, the power consumption of the phase tracking circuit 100 can be saved. This process is discussed in further detail below and is only briefly described here.
  • FIG. 9 shows a flowchart of a phase tracking method 300 according to an embodiment of the present invention.
  • the method 300 may be implemented using the phase tracking circuit 100 described above with reference to FIGS. 1-8 (including, but not limited to, the phase tracking circuit 100a, the phase tracking circuit 100b, and the phase tracking circuit 100c).
  • the phase tracking method 300 may include: step 310, using the frequency divider 110 to divide the first clock signal to obtain a carrier signal; step 320, using the phase detector 120 to compare the carrier signal and the reference clock signal.
  • step 330 the phase tuning module 130 adjusts the phase of the first clock signal based on the phase indication signal, so that the phase of the carrier signal tracks or is closer to the phase of the reference clock signal; and step 340, by
  • the control module 140 controls the operating clock of the phase tuning module 130 based on the phase indication signal, or more specifically, controls at least one of the frequency of the operating clock of the phase tuning module 130 and the frequency division ratio of the frequency divider 110 . That is, in step 340, the control module 140 may control the operating clock of the phase tuning module 130 (eg, executed in the phase tracking circuit 100a shown in FIG. 2) based on the phase indication signal, and control the frequency divider based on the phase indication signal.
  • a frequency division ratio of 110 (for example, implemented in the phase tracking circuit 100b shown in FIG. 3 ), or both the operating clock of the phase tuning module 130 and the frequency division ratio of the frequency divider 110 are controlled based on the phase indication signal (for example, in FIG. 3 Executed in the phase tracking circuit 100c shown in 4).
  • FIG. 10 shows a flowchart of a phase adjustment process of the first clock signal according to an embodiment of the present invention, which can be applied in step 330 of the method 300 shown in FIG. 9 .
  • the digital loop filter 132 may be used to generate a first clock selection signal based on the phase indication signal.
  • the first clock selection unit 134 may be used to select a clock signal from the multi-phase clock signals based on the first clock selection signal as the first clock signal provided to the frequency divider 110.
  • FIG. 11 shows a flow chart of a process of adjusting the operating clock of the phase tuning module 130 and/or the frequency division ratio of the frequency divider 110 based on the phase indication signal according to an embodiment of the present invention, which can be applied to the method shown in FIG. 9 In step 340 of method 300.
  • the dynamic detection adjustment unit 142 is used to detect the phase indication signal generated by the phase detector 120 to generate a second clock selection signal and/or a frequency division ratio adjustment signal. Note that the second clock selection signal and the frequency division ratio adjustment signal may be generated at different times or under different circumstances based on the phase indication signal.
  • the second clock selection unit 144 may be used to select one of the plurality of second clock signals based on the second clock selection signal as the operating clock of the digital loop filter 132 in the phase tuning module 130.
  • the plurality of The second clock signal may include one or more divided frequency signals provided by the frequency divider 110 , or may also include the first clock signal provided by the first clock selection unit 134 .
  • the frequency division ratio control unit 146 may be used to control the frequency division ratio of the frequency divider 110 based on the frequency division ratio adjustment signal.
  • FIG. 12 shows a flow chart of a process of generating a second clock selection signal and/or a frequency division ratio adjustment signal according to an embodiment of the present invention, which can be applied to step 342 shown in FIG. 11 .
  • the dynamic detection adjustment unit 142 may determine whether the phase of the carrier signal jumps between being further ahead and more lagging than the phase of the reference clock signal and jumping based on the phase indication signal generated by the detection phase detector 120 Reach the predetermined number of times.
  • the dynamic detection adjustment unit 142 may generate a second clock selection signal for reducing the frequency of the second clock signal selected by the second clock selection unit 144 , and/or for reducing the frequency of the frequency divider 110 The frequency division ratio control signal of the frequency division gear. Steps 401 and 403 may be repeatedly executed until the second clock selection unit 144 selects the clock signal with the lowest/basic frequency, and/or the frequency division gear of the frequency divider 110 reaches the basic gear.
  • step 405 the dynamic detection adjustment unit 142 may determine whether the phase of the carrier signal is greater than the reference clock signal based on the phase indication signal generated by the detection phase detector 120 The phase is more advanced or lagging and lasts for a predetermined period. If yes, in step 407, the dynamic detection adjustment unit 142 may generate a second clock selection signal for increasing the frequency of the clock signal selected by the second clock selection unit 144, and/or for increasing the frequency of the frequency divider 110. Frequency division ratio control signal of frequency gear. Steps 405 and 407 may be repeatedly executed until the second clock selection unit 144 selects the clock signal with the highest frequency, and/or the frequency division gear of the frequency divider 110 reaches the highest gear.
  • FIG. 13 shows a flowchart of a process of generating a first clock selection signal according to an embodiment of the present invention, which can be applied in step 332 shown in FIG. 10 .
  • the proportional path 210 can be used to generate a first proportional signal that is in a first proportion to the phase indication signal provided by the phase detector 120; in step 514, the integral path 220 can be used to generate a first proportional signal that is in a first proportion to the phase indication signal.
  • the second ratio signal of the two ratios can be used to generate a first proportional signal that is in a first proportion to the phase indication signal.
  • the first proportion or the first proportion signal may be adjusted by the first proportion adjustment unit 214; in step 518, the second proportion or the first proportion signal may be adjusted by the second proportion adjustment unit 224.
  • Two proportional signals are adjusted.
  • the same adjustment coefficient may be used to adjust the first ratio and the second ratio equally in steps 516 and 518 .
  • the coefficient control unit 136 may be used to control the adjustment coefficient for adjusting the first ratio and/or the second ratio based on the coefficient adjustment signal generated by the dynamic detection adjustment unit 142 .
  • the coefficient adjustment signal generated by the dynamic detection adjustment unit 142 may instruct the coefficient control unit 136 to increase the adjustment coefficient to increase the first ratio sum / or a second ratio, when such a sustained period is detected multiple times, this step can be repeated until the maximum ratio is reached.
  • the coefficient adjustment signal generated by the dynamic detection adjustment unit 142 may indicate the coefficient control unit 136 Lower the adjustment factor to reduce the first ratio and/or the second ratio, again this step can be repeated until the minimum/base ratio is reached.
  • the second proportional signal may be integrated using the integrator 226 in the integration path 220 to obtain an integrated signal.
  • the second clock signal selected by the second clock selection unit 144 can be used as the operating clock of the integrator 226 to control the speed of the integration process.
  • the adder 232 may be used to add the first proportional signal and the integral signal to obtain a sum of the two.
  • the remainder unit 234 may be used to perform a remainder operation on the sum value with respect to a predetermined value to generate a first clock selection signal.
  • the predetermined value may be equal to the number of clock signals with different phases to be selected by the first clock selection unit 134.
  • FIG. 14 shows a flowchart of coefficient adjustment and operating clock frequency adjustment of the digital loop filter 132 according to an embodiment of the present invention, which may be performed by, for example, the phase tracking circuit 100a shown in FIG. 2 .
  • step 601 it may be determined based on the phase indication signal whether the phase of the carrier signal jumps between leading and lagging the phase of the reference clock signal for a predetermined number of times. If no hopping occurs or the hopping does not reach a predetermined number of times, it is determined in step 603 whether the phase of the carrier signal is further ahead or lagging behind the phase of the reference clock signal for a predetermined period.
  • step 629 the proportional coefficient and the operating clock of the digital loop filter 132 can be kept unchanged, and then return to step 601 .
  • step 603 If it is determined in step 603 that the phase of the carrier signal leads or lags behind the phase of the reference clock signal by a predetermined period, then the proportional coefficient to be adjusted (the first proportional coefficient a and the first proportional coefficient a and /or whether the second proportional coefficient p) reaches the maximum value. If the maximum value has not been reached, the scale factor to be adjusted of the digital loop filter 132 may be increased in step 607 and then returned to step 601 .
  • the operating clock frequency of the digital loop filter 132 can be determined in step 609, or more precisely, the operating clock frequency of the integrator in the integration path of the digital loop filter 132, that is, the second clock selection Whether the frequency of the second clock signal selected by unit 144 reaches the maximum value. If the maximum frequency has not been reached, the operating clock frequency of the digital loop filter 132 may be increased in step 611, that is, the frequency of the second clock signal selected by the second clock selection unit 144, and then return to step 601. If the frequency of the second clock signal has reached the maximum value, in step 629, the proportional coefficient and the operating clock of the digital loop filter 132 can be kept unchanged, and then return to step 601.
  • step 601 if it is determined in step 601 that the phase of the carrier signal transitions between being more advanced and more lagging than the phase of the reference clock signal and the transition reaches a predetermined number of times, then it may be determined in step 621 that the operation of the digital loop filter 132 Whether the clock frequency, that is, the frequency of the second clock signal selected by the second clock selection unit 144, is the lowest frequency. If it is not the lowest frequency, the operating clock frequency of digital loop filter 132 may be reduced at step 632 and then returned to step 601.
  • step 621 If it is determined in step 621 that the operating clock frequency of the digital loop filter 132 is the lowest frequency, then the proportional coefficient to be adjusted (the first proportional coefficient a and/or the second proportional coefficient a) of the digital loop filter 132 may be determined in step 625 p) is the minimum value. If it is not the minimum value, the proportional coefficient to be adjusted of the digital loop filter 132 may be reduced in step 627 and then returned to step 601. If the proportional coefficient to be adjusted of the digital loop filter 132 is already the minimum value, the proportional coefficient of the digital loop filter and the operating clock can be kept unchanged in step 629, and then return to step 601.
  • the traditional phase adjustment step is 0.46875°. If there is a 180° phase between the carrier signal and the reference clock signal If there is a difference, the phase locking time is generally around 100 ⁇ s. If there is a certain frequency deviation between the carrier signal and the reference clock signal, the phase locking time is more than 100 ⁇ s.
  • the locking time can be greatly accelerated by increasing the proportional coefficient and integral frequency in the digital loop filter 132 in the initial stage of phase tracking. When it is close to locking, the proportional coefficient and integral frequency in the digital loop filter 132 can be reduced until the minimum coefficient and the lowest frequency, so that the locking is more stable.
  • the overall lock time can be shortened to about 3 ⁇ s to 6 ⁇ s.
  • FIG. 15 shows a flow chart for adjusting the coefficients of the digital loop filter 132 and adjusting the frequency division gear of the frequency divider 110 according to an embodiment of the present invention. It can be, for example, the phase shown in FIG. 3
  • the tracking circuit 100b is executed. Referring to FIG. 15 , in step 601 , it may be determined based on the phase indication signal whether the phase of the carrier signal jumps between leading and lagging the phase of the reference clock signal for a predetermined number of times. If no hopping occurs or the hopping does not reach a predetermined number of times, it is determined in step 603 whether the phase of the carrier signal is further ahead or lagging behind the phase of the reference clock signal for a predetermined period.
  • step 629 the proportional coefficient of the digital loop filter 132 and the frequency division gear of the frequency divider 110 can be kept unchanged. change, and then return to step 601.
  • step 603 If it is determined in step 603 that the phase of the carrier signal leads or lags behind the phase of the reference clock signal by a predetermined period, then the proportional coefficient to be adjusted (the first proportional coefficient and/or Whether the second proportional coefficient) reaches the maximum value. If the maximum value has not been reached, the proportional coefficient to be adjusted of the digital loop filter 132 can be increased in step 607 and then returned to step 601 .
  • step 605 If it is determined in step 605 that the proportional coefficient to be adjusted of the digital loop filter 132 has reached the maximum value, then it may be determined in step 613 whether the frequency division gear of the frequency divider 110 has reached the maximum gear. If the maximum gear has not been reached, the frequency division gear of the frequency divider 110 can be increased in step 615, and then return to step 601. If the frequency division gear of the frequency divider 110 has reached the maximum gear, then in step 629, the proportional coefficient of the digital loop filter 132 and the frequency division gear of the frequency divider 110 can be kept unchanged, and then return to step 629. 601.
  • step 601 if it is determined in step 601 that the phase of the carrier signal jumps between being ahead and lagging behind the phase of the reference clock signal and the jump reaches a predetermined number of times, then the frequency dividing file of the frequency divider 110 may be determined in step 617 Is the position in the lowest/basic gear? If the frequency division gear of the frequency divider 110 is not the lowest gear, the frequency division gear of the frequency divider 110 may be reduced in step 619 and then return to step 601.
  • the proportional coefficient to be adjusted (the first proportional coefficient and/or the second proportional coefficient) of the digital loop filter 110 may be determined in step 625 ) is the minimum value. If it is not the minimum value, the proportional coefficient to be adjusted of the digital loop filter 132 may be reduced in step 627 and then returned to step 601. If the proportional coefficient to be adjusted of the digital loop filter 132 is already the minimum value, the proportional coefficient of the digital loop filter 132 and the frequency division gear of the frequency divider 110 can be kept unchanged in step 629, and then return to step 629. 601.
  • the dynamic adjustment of the frequency division ratio can be started in the initial stage of phase tracking, and the phase adjustment step can be increased dozens of times according to the frequency division ratio adjustment gear, thereby greatly accelerating the locking time.
  • the frequency division ratio adjustment gear is reduced until it is deactivated, and the step is restored to 0.46875°, so that the phase adjustment accuracy is not lost.
  • the overall stabilization time can be shortened to less than 10us.
  • FIG. 16 shows a flow chart for adjusting the coefficients and operating clock frequency of the digital loop filter 132 and adjusting the frequency division ratio of the frequency divider 110 according to an embodiment of the present invention, which can be, for example, shown in FIG. 4
  • Phase tracking circuit 100c executes.
  • step 601 it may be determined based on the phase indication signal whether the phase of the carrier signal jumps between leading and lagging the phase of the reference clock signal for a predetermined number of times. If no hopping occurs or the hopping does not reach a predetermined number of times, it is determined in step 603 whether the phase of the carrier signal is further ahead or lagging behind the phase of the reference clock signal for a predetermined period.
  • step 629 the scaling coefficient of the digital loop filter 132 and the operating clock and the frequency division of the frequency divider 110 can be maintained.
  • the ratio/frequency division gear remains unchanged, and then returns to step 601.
  • the proportionality coefficient to be adjusted (the first proportionality coefficient) of the digital loop filter 132 may be determined in step 605 Whether a and/or the second proportional coefficient p) reach the maximum value. If the maximum value has not been reached, the proportional coefficient to be adjusted of the digital loop filter 132 can be increased in step 607 and then returned to step 601 .
  • the operating clock frequency of the digital loop filter 132 may be determined at step 609, or, more precisely, the digital loop filter Whether the operating clock frequency of the integrator in the integration path 132, that is, the frequency of the second clock signal selected by the second clock selection unit 144, reaches the maximum value. If the maximum frequency has not been reached, the operating clock frequency of the digital loop filter 132 may be increased in step 611, that is, the frequency of the second clock signal selected by the second clock selection unit 144, and then return to step 601.
  • step 609 If it is determined in step 609 that the frequency of the second clock signal has reached the maximum value, it may be determined in step 613 whether the frequency division gear of the frequency divider 110 has reached the highest gear. If the highest gear has not been reached, the frequency division gear of the frequency divider 110 can be increased in step 615 and then returned to step 601 . If the highest gear has been reached, the proportional coefficient and operating clock of the digital loop filter 132 and the frequency division ratio/frequency division gear of the frequency divider 110 can be kept unchanged in step 629, and then return to step 601.
  • the frequency division of the frequency divider 110 may be determined in step 617 Whether the gear is the lowest/basic gear. If it is not the lowest gear, the frequency division gear of the frequency divider 110 can be reduced in step 619, and then return to step 601.
  • step 617 If it is determined in step 617 that the frequency division gear of the frequency divider 110 is at the lowest gear, then the operating clock frequency of the digital loop filter 132 can be determined in step 621, that is, the second clock frequency selected by the second clock selection unit 144. The frequency of the clock signal, whether it is the lowest frequency. If it is not the lowest frequency, the operating clock frequency of digital loop filter 132 may be reduced in step 623 and then returned to step 601.
  • the scaling coefficient to be adjusted (the first scaling coefficient a and/or the second scaling factor a) of the digital loop filter 132 may be determined in step 625 Whether the coefficient p) is the minimum value. If it is not the minimum value, the proportional coefficient to be adjusted of the digital loop filter 132 may be reduced in step 627 and then returned to step 601. If the proportional coefficient to be adjusted of the digital loop filter 132 is already the minimum value, the proportional coefficient and the operating clock of the digital loop filter 132 and the frequency division ratio/frequency division gear of the frequency divider 110 can be maintained in step 629 No change, then return to step 601.
  • FIG. 17 shows a flow chart for adjusting the coefficients and operating clock frequency of the digital loop filter 132 and adjusting the frequency division ratio of the frequency divider 110 according to another embodiment of the present invention, which can be, for example, as shown in FIG. 4
  • the phase tracking circuit 100c is executed.
  • the process shown in FIG. 17 includes many steps that are the same as the process shown in FIG. 16 , and a repeated description thereof will be omitted below, and only different steps will be described.
  • step 608 when it is determined in step 605 that the proportional coefficient of the digital loop filter 132 has reached the maximum value, it is determined in step 608 whether the frequency dividing gear of the frequency divider 110 is at the lowest/basic gear and the digital loop filter 132 has reached the maximum value.
  • the operating clock of the integrator 226 in the filter 132 that is, the second clock signal selected by the second clock selection unit 144, is at a non-highest frequency. If yes, then in step 611 Increase the operating clock frequency of the integrator 226 in the digital loop filter 132, and then return to step 601. If not, the flow proceeds to step 613.
  • the frequency division gear of the frequency divider 110 can be increased in step 614, and the frequency division gear of the frequency divider 110 can be increased for the first time.
  • the frequency division gear is raised from the basic gear to gear 1
  • the operating clock of the integrator 226 in the digital loop filter 132 is also selected by the second clock selection unit 144.
  • the second clock signal is placed at the lowest frequency to save power consumption of the digital loop filter 132 during the frequency division ratio adjustment.
  • step 601 when it is determined in step 601 that the jump reaches a predetermined number of times and it is determined in step 617 that the frequency division gear of the frequency divider 110 is not the base/lowest gear, in step 618, the frequency division gear of the frequency divider 110 may be reduced. frequency division gear, and when the frequency division gear of the frequency divider 110 is reduced to the basic/lowest gear, the operating clock of the integrator 226 in the digital loop filter 132, that is, the second clock selection unit 144 selects the second clock signal and places it at the highest frequency.
  • the following steps are the same as the process shown in Figure 16, and will not be described again here.
  • the traditional phase adjustment step is 0.46875°. If there is a 180° phase between the carrier signal and the reference clock signal If there is a difference, the phase locking time is generally around 100 ⁇ s. If there is a certain frequency deviation between the carrier signal and the reference clock signal, the phase locking time is more than 100 ⁇ s.
  • the locking time can be greatly accelerated by increasing the proportional coefficient and integral frequency in the digital loop filter in the initial stage of phase tracking. When approaching locking, the proportional coefficient and integral frequency in the digital loop filter can be reduced until the minimum coefficient and the lowest frequency, making the locking more stable.
  • the overall locking and stabilization time can be within 10 ⁇ s.
  • FIG 18 shows a schematic diagram of an electronic device 700 according to an embodiment of the present invention.
  • the electronic device 700 may include a phase tracking circuit 720 according to an embodiment of the invention.
  • the electronic device 700 may have an NFC module 710, which may operate in a card emulation mode.
  • NFC module 710 can include A phase tracking circuit 720 is included to track the signal phase of the NFC reader.
  • Examples of such electronic devices 700 include, but are not limited to, mobile phones, tablets, portable personal digital assistants, wearable electronic devices, and the like.
  • each component or each step can be decomposed and/or recombined. These decompositions and/or recombinations shall be considered equivalent versions of this application.

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

本发明涉及相位追踪电路和方法及电子设备。一种相位追踪电路可包括：分频器，用于对第一时钟信号进行分频处理以获得载波信号；鉴相器，用于比较所述载波信号和参考时钟信号的相位，以生成相位指示信号；相位调谐模块，用于基于所述相位指示信号来调整所述第一时钟信号的相位，以使得所述载波信号的相位更接近于所述参考时钟信号的相位；以及控制模块，用于基于所述相位指示信号来控制所述相位调谐模块的运行时钟和所述分频器的分频比中的至少一个，以控制所述相位调谐模块的相位调整速度。

Description

相位追踪电路和方法及电子设备 技术领域
本发明涉及相位追踪电路、相位追踪方法、以及包括相位追踪电路的电子设备。
背景技术
在无线通信领域，有时候需要针对接收到的信号进行相位追踪。例如，在近场通信(NFC)场景，由于采用的是幅度调制，因此读卡器需要追踪从NFC卡片读取的信号的相位，当二者的相位差较大时，可能造成幅度信息丢失。读卡器从NFC卡片读取的信号来自NFC卡片进行负载调制产生的信号，NFC卡片一般可采用无源负载调制(PLM)和有源负载调制(ALM)两种方案之一。当采用无源负载调制方案时，由于NFC卡片完全依赖于读卡器提供的射频信号来产生被动读取信号，因此不存在相位差异，但是所产生的被动读取信号的能量较小，通信距离受到限制，而且容易受到干扰。当采用有源负载调制方案时，处于卡模拟角色的NFC装置(例如手机)可以模拟负载调制过程，主动发射与读卡器装置相位一致的载波信号。有源负载调制方案能够提供更大的信号功率和更好的抗干扰特性，但是由于NFC装置主动发射的载波信号与读卡器信号不同源，因此可能存在相位偏差问题。
发明内容
本发明的实施例提供一种相位追踪电路，其能够通过调节分频比和时钟信号中的至少一种来控制信号相位调节速度，从而能够在大的相差范围内快速并且高精度地追踪目标相位，并且还能够节省功耗。本发明的实施例还提供一种相位追踪方法、以及包括相位追踪电路的电子设备。
根据一实施例，一种相位追踪电路可包括：分频器，用于对第一时钟信号进行分频处理以获得载波信号；鉴相器，用于比较所述载波信号和参考时钟信号的相位，以生成相位指示信号；相位调谐模块，用于基于所述相位指示信号来调整所述第一时钟信号的相位，以使得所述载波信号的相位更接近 于所述参考时钟信号的相位；以及控制模块，用于基于所述相位指示信号来控制所述相位调谐模块的运行时钟和所述分频器的分频比中的至少一个，以控制所述相位调谐模块的相位调整速度。
在一示例中，所述鉴相器是二进制鉴相器，所述二进制鉴相器输出的相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位超前或者滞后。
在一示例中，所述相位调谐模块包括：数字环路滤波器，用于基于所述相位指示信号来生成第一时钟选择信号；以及第一时钟选择单元，用于基于所述第一时钟选择信号从多相时钟信号中选择一个时钟信号作为所述第一时钟信号。
在一示例中，所述控制模块包括第二时钟选择单元和分频比控制单元中的至少一个、以及动态检测调整单元。所述动态检测调整单元配置为检测所述鉴相器生成的相位指示信号，并且生成第二时钟选择信号和/或分频比调整信号。所述第二时钟选择单元配置为基于所述第二时钟选择信号从多个第二时钟信号中选择一个作为所述数字环路滤波器的运行时钟。所述分频比控制单元配置为基于所述分频比调整信号来控制所述分频器的分频比。
在一示例中，所述多个第二时钟信号包括所述分频器提供的一个或多个分频信号。
在一示例中，所述多个第二时钟信号还包括所述第一时钟选择单元提供的所述第一时钟信号。
在一示例中，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前或者更滞后并且持续预定周期时，所述动态检测调整单元生成的第二时钟选择信号指示所述第二时钟选择单元从所述多个第二时钟信号中选择一个比当前选择的时钟信号更高频率的时钟信号，所述动态检测调整单元生成的分频比调整信号指示所述分频比控制单元提高所述分频器的分频档位。当所述相位指示信号指示所述载波信号的相位在比所述参考时钟信号的相位更超前和更滞后之间跳变并且所述跳变达到预定次数时，所述动态检测调整单元生成的第二时钟选择信号指示所述第二时钟选择单元从所述多个第二时钟信号中选择一个比当前选择的时钟信号更低频率的分频信号，所述动态检测调整单元生成的分频比调整信号指示所述分频比控制单元降低所述分频器的分频档位。所述分频器具有基础档位以及至少一个 更高档位，所述基础档位具有基础分频比N，所述更高档位具有更高分频比N+x或者更低分频比N-x，N为预设的正整数，x为比N更小的正整数并且档位越高，x的值越大，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前时，所述更高档位具有所述更高分频比N+x，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更滞后时，所述更高档位具有所述更低分频比N-x。
在一示例中，所述载波信号是所述分频器提供的多个分频信号中具有最低频率的分频信号，所述基础分频比N使得所述载波信号的频率等于所述参考时钟信号的频率。
在一示例中，所述多相时钟信号包括M个不同相位的时钟信号，M是大于一的整数。所述数字环路滤波器生成的第一时钟选择信号表示M个索引值中的一个，以指示所述第一时钟选择单元从所述M个不同相位的时钟信号中选择一个对应的时钟信号作为所述第一时钟信号。
在一示例中，当所述鉴相器生成的相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位超前并且持续预定周期时，所述数字环路滤波器生成的第一时钟选择信号指示所述第一时钟选择单元从所述多相时钟信号中选择一个比当前选择的时钟信号相位更滞后的时钟信号。当所述鉴相器生成的相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位滞后并且持续预定周期时，所述数字环路滤波器生成的第一时钟选择信号指示所述第一时钟选择单元从所述多相时钟信号中选择一个比当前选择的时钟信号相位更超前的时钟信号。
在一示例中，所述数字环路滤波器包括：比例路径，用于生成与所述相位指示信号成第一比例的第一比例信号；积分路径，用于生成与所述相位指示信号成第二比例的第二比例信号，并且使用积分器对所述第二比例信号进行积分处理以生成积分信号；加法器，用于对所述第一比例信号和所述积分信号进行加法运算，以输出二者的和值；以及取余单元，用于对从所述加法器接收到的所述和值关于预定值进行取余运算，以生成表示余数的所述第一时钟选择信号。
在一示例中，所述第二时钟选择单元选择的第二时钟信号用作所述积分路径中的积分器的运行时钟，所述预定值等于所述多相时钟信号中包括的具有不同相位的时钟信号的个数。
在一示例中，所述数字环路滤波器还包括以下中的至少一个：设置在所述比例路径中的第一比例调节单元，用于调节所述第一比例；以及设置在所述积分路径中的第二比例调节单元，用于调节所述第二比例。
在一示例中，所述第一比例调节单元和所述第二比例调节单元使用相同的调节系数对所述第一比例和所述第二比例进行等比调节。
在一示例中，所述相位追踪电路还包括：系数控制单元，用于基于所述动态检测调整单元生成的系数调整信号来控制对所述第一比例和所述第二比例中的至少一个进行调节的调节系数。当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前或者更滞后并且持续预定周期时，所述动态检测调整单元生成的系数调整信号指示所述系数控制单元提高所述调节系数以增大所述第一比例和所述第二比例中的所述至少一个。当所述相位指示信号指示所述载波信号的相位在比所述参考时钟信号的相位更超前和更滞后之间跳变并且所述跳变达到预定次数时，所述动态检测调整单元生成的系数调整信号指示所述系数控制单元降低所述调节系数以减小所述第一比例和所述第二比例中的所述至少一个。
在一示例中，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前或者更滞后并且持续预定周期时，所述动态检测调整单元先生成所述系数调整信号以增大所述第一比例和所述第二比例中的所述至少一个，直到达到最大比例，然后生成所述第二时钟选择信号以提高所述第二时钟选择单元选择的第二时钟信号的频率，直到达到最高频率，然后生成所述分频比调整信号以提高所述分频器的分频档位。当所述相位指示信号指示所述载波信号的相位在比所述参考时钟信号的相位更超前和更滞后之间跳变并且所述跳变达到预定次数时，所述动态检测调整单元先生成所述分频比调整信号以降低所述分频器的分频档位，直到达到基础档位，然后生成所述第二时钟选择信号以降低所述第二时钟选择单元选择的第二时钟信号的频率，直到达到最低频率，然后生成所述系数调整信号以减小所述第一比例和所述第二比例中的所述至少一个。
在一示例中，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前或者更滞后并且持续预定周期时，所述动态检测调整单元先生成所述系数调整信号以增大所述第一比例和所述第二比例中的所述至少一个，直到达到最大比例，然后生成所述第二时钟选择信号以提高所 述第二时钟选择单元选择的第二时钟信号的频率，直到达到最高频率，然后生成最小第二时钟设置信号以将所述第二时钟选择单元选择的第二时钟信号的频率设置为最低频率，并且生成所述分频比调整信号以提高所述分频器的分频档位。当所述相位指示信号指示所述载波信号的相位在比所述参考时钟信号的相位更超前和更滞后之间跳变并且所述跳变达到预定次数时，所述动态检测调整单元先生成所述分频比调整信号以降低所述分频器的分频档位，直到达到基础档位，并且在所述分频档位达到基础档位时，生成最大第二时钟设置信号以将所述第二时钟选择单元选择的第二时钟信号的频率设置为最高频率，然后生成所述第二时钟选择信号以降低所述第二时钟选择单元选择的第二时钟信号的频率，直到达到最低频率，然后生成所述系数调整信号以减小所述第一比例和所述第二比例中的所述至少一个。
根据一实施例，一种相位追踪方法可包括：分频器对第一时钟信号进行分频处理以获得载波信号；鉴相器比较所述载波信号和参考时钟信号的相位，以生成相位指示信号；相位调谐模块基于所述相位指示信号来调整所述第一时钟信号的相位，以使得所述载波信号的相位更接近于所述参考时钟信号的相位；以及控制模块基于所述相位指示信号控制所述相位调谐模块的运行时钟和所述分频器的分频比中的至少一个，以控制所述相位调谐模块的相位调整速度。
在一示例中，相位调谐模块基于所述相位指示信号来调整所述第一时钟信号的相位包括：利用数字环路滤波器基于所述相位指示信号来生成第一时钟选择信号；以及利用第一时钟选择单元基于所述第一时钟选择信号从多相时钟信号中选择一个时钟信号作为所述第一时钟信号。
在一示例中，所述控制模块包括第二时钟选择单元和分频比控制单元中的至少一个、以及动态检测调整单元。所述动态检测调整单元配置为检测所述鉴相器生成的相位指示信号，并且生成第二时钟选择信号和/或分频比调整信号。所述第二时钟选择单元配置为基于所述第二时钟选择信号从多个第二时钟信号中选择一个作为所述数字环路滤波器的运行时钟。所述分频比控制单元配置为基于所述分频比调整信号来控制所述分频器的分频比。
在一示例中，所述多个第二时钟信号包括所述分频器提供的一个或多个分频信号。
在一示例中，所述多个第二时钟信号还包括所述第一时钟选择单元提供 的所述第一时钟信号。
在一示例中，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前或者更滞后并且持续预定周期时，所述动态检测调整单元生成的第二时钟选择信号指示所述第二时钟选择单元从所述多个第二时钟信号中选择一个比当前选择的时钟信号更高频率的时钟信号，所述动态检测调整单元生成的分频比调整信号指示所述分频比控制单元提高所述分频器的分频档位。当所述相位指示信号指示所述载波信号的相位在比所述参考时钟信号的相位更超前和更滞后之间跳变并且所述跳变达到预定次数时，所述动态检测调整单元生成的第二时钟选择信号指示所述第二时钟选择单元从所述多个第二时钟信号中选择一个比当前选择的时钟信号更低频率的分频信号，所述动态检测调整单元生成的分频比调整信号指示所述分频比控制单元降低所述分频器的分频档位。所述分频器具有基础档位以及至少一个更高档位，所述基础档位具有基础分频比N，所述更高档位具有更高分频比N+x或者更低分频比N-x，N为预设的正整数，x为比N更小的正整数并且档位越高，x的值越大，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前时，所述更高档位具有所述更高分频比N+x，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更滞后时，所述更高档位具有所述更低分频比N-x。
在一示例中，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位超前并且持续预定周期时，所述数字环路滤波器生成的第一时钟选择信号指示所述第一时钟选择单元从所述多相时钟信号中选择一个比当前选择的时钟信号相位更滞后的时钟信号。当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位滞后并且持续预定周期时，所述数字环路滤波器生成的第一时钟选择信号指示所述第一时钟选择单元从所述多相时钟信号中选择一个比当前选择的时钟信号相位更超前的时钟信号。
在一示例中，利用数字环路滤波器基于所述相位指示信号来生成第一时钟选择信号包括：利用比例路径生成与所述相位指示信号成第一比例的第一比例信号；利用积分路径生成与所述相位指示信号成第二比例的第二比例信号，并且使用设置在所述积分路径中的积分器对所述第二比例信号进行积分处理以生成积分信号；利用加法器对所述第一比例信号和所述积分信号进行 加法运算，以输出二者的和值；以及利用取余单元对所述和值关于预定值进行取余运算，以生成表示余数的所述第一时钟选择信号。
在一示例中，所述第二时钟选择单元选择的第二时钟信号用作所述积分路径中的积分器的运行时钟以控制对所述第二比例信号进行积分的速度，所述预定值等于所述多相时钟信号中包括的具有不同相位的时钟信号的个数。
在一示例中，利用数字环路滤波器基于所述相位指示信号来生成第一时钟选择信号还包括以下步骤中的至少一个：利用设置在所述比例路径中的第一比例调节单元调节所述第一比例；以及利用设置在所述积分路径中的第二比例调节单元调节所述第二比例。
在一示例中，所述第一比例调节单元和所述第二比例调节单元使用相同的调节系数对所述第一比例和所述第二比例进行等比调节。
在一示例中，所述方法还包括：利用系数控制单元基于所述动态检测调整单元生成的系数调整信号来控制对所述第一比例和所述第二比例中的至少一个进行调节的调节系数。当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前或者更滞后并且持续预定周期时，所述动态检测调整单元生成的系数调整信号指示所述系数控制单元提高所述调节系数以增大所述第一比例和所述第二比例中的所述至少一个。当所述相位指示信号指示所述载波信号的相位在比所述参考时钟信号的相位更超前和更滞后之间跳变并且所述跳变达到预定次数时，所述动态检测调整单元生成的系数调整信号指示所述系数控制单元降低所述调节系数以减小所述第一比例和所述第二比例中的所述至少一个。
在一示例中，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前或者更滞后并且持续预定周期时，所述动态检测调整单元先生成所述系数调整信号以增大所述第一比例和所述第二比例中的所述至少一个，直到达到最大比例，然后生成所述第二时钟选择信号以提高所述第二时钟选择单元选择的第二时钟信号的频率，直到达到最高频率，然后生成所述分频比调整信号以提高所述分频器的分频档位。当所述相位指示信号指示所述载波信号的相位在比所述参考时钟信号的相位更超前和更滞后之间跳变并且所述跳变达到预定次数时，所述动态检测调整单元先生成所述分频比调整信号以降低所述分频器的分频档位，直到达到基础档位，然后生成所述第二时钟选择信号以降低所述第二时钟选择单元选择的第二时钟信 号的频率，直到达到最低频率，然后生成所述系数调整信号以减小所述第一比例和所述第二比例中的所述至少一个。
在一示例中，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前或者更滞后并且持续预定周期时，所述动态检测调整单元先生成所述系数调整信号以增大所述第一比例和所述第二比例中的所述至少一个，直到达到最大比例，然后生成所述第二时钟选择信号以提高所述第二时钟选择单元选择的第二时钟信号的频率，直到达到最高频率，然后生成最小第二时钟设置信号以将所述第二时钟选择单元选择的第二时钟信号的频率设置为最低频率，并且生成所述分频比调整信号以提高所述分频器的分频档位。当所述相位指示信号指示所述载波信号的相位在比所述参考时钟信号的相位更超前和更滞后之间跳变并且所述跳变达到预定次数时，所述动态检测调整单元先生成所述分频比调整信号以降低所述分频器的分频档位，直到达到基础档位，并且在所述分频档位达到基础档位时，生成最大第二时钟设置信号以将所述第二时钟选择单元选择的第二时钟信号的频率设置为最高频率，然后生成所述第二时钟选择信号以降低所述第二时钟选择单元选择的第二时钟信号的频率，直到达到最低频率，然后生成所述系数调整信号以减小所述第一比例和所述第二比例中的所述至少一个。
根据一实施例，一种相位追踪电路可包括：分频器，用于对时钟信号进行分频处理以获得载波信号；鉴相器，用于比较所述载波信号和参考时钟信号的相位，以生成相位指示信号；控制模块，用于基于所述相位指示信号来调整所述分频器的分频比；以及相位调谐模块，用于基于所述相位指示信号来调整所述时钟信号的相位。
在一示例中，所述鉴相器是二进制鉴相器，当所述载波信号的相位比所述参考时钟信号的相位超前时，所述二进制鉴相器输出第一指示信号，当所述载波信号的相位比所述参考时钟信号的相位滞后时，所述二进制鉴相器输出第二指示信号。
在一示例中，所述控制模块包括：动态检测调整单元，用于检测所述鉴相器生成的相位指示信号，并且生成分频比调整信号；以及分频比控制单元，用于基于所述分频比调整信号来控制所述分频器的分频比。
在一示例中，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前或者更滞后并且持续预定周期时，所述动态检测调整 单元生成第一分频比调整信号，所述分频比控制单元响应于所述第一分频比调整信号提高所述分频器的分频档位，直到达到最高档位。当所述相位指示信号指示所述载波信号的相位在比所述参考时钟信号的相位更超前和更滞后之间跳变并且所述跳变达到预定次数时，所述动态检测调整单元生成第二分频比调整信号，所述分频比控制单元响应于所述第二分频比调整信号降低所述分频器的分频档位，直到达到基础档位。所述分频器具有所述基础档位以及至少一个更高档位，所述基础档位具有基础分频比N，所述更高档位具有更高分频比N+x或者更低分频比N-x，N为预设的正整数，x为比N更小的正整数并且档位越高，x的值越大，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前时，所述更高档位具有所述更高分频比N+x，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更滞后时，所述更高档位具有所述更低分频比N-x。
在一示例中，所述基础分频比N使得所述载波信号的频率等于所述参考时钟信号的频率。
在一示例中，所述相位调谐模块包括：数字环路滤波器，用于基于所述相位指示信号来生成选择指示信号；以及多相时钟选择单元，用于基于所述选择指示信号从多相时钟信号中选择一个时钟信号。
在一示例中，所述多相时钟信号包括M个不同相位的时钟信号，M是大于一的整数。所述数字环路滤波器生成的选择指示信号表示M个索引值中的一个，以指示所述多相时钟选择单元从所述M个不同相位的时钟信号中选择一个对应的时钟信号。
在一示例中，当所述鉴相器生成的相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位超前并且持续预定周期时，所述数字环路滤波器生成的选择指示信号指示所述多相时钟选择单元从所述多相时钟信号中选择一个比当前选择的时钟信号相位更滞后的时钟信号。当所述鉴相器生成的相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位滞后并且持续预定周期时，所述数字环路滤波器生成的选择指示信号指示所述多相时钟选择单元从所述多相时钟信号中选择一个比当前选择的时钟信号相位更超前的时钟信号。
在一示例中，所述数字环路滤波器包括：比例路径，用于生成与所述相位指示信号成第一比例的第一比例信号；积分路径，用于生成与所述相位指 示信号成第二比例的第二比例信号，并且对所述第二比例信号进行积分处理以生成积分信号；加法器，用于对所述第一比例信号和所述积分信号进行加法运算，以输出二者的和值；以及取余单元，用于对从所述加法器接收到的所述和值关于预定值进行取余运算，以生成表示余数的所述选择指示信号。
在一示例中，所述预定值等于所述多相时钟信号中包括的具有不同相位的时钟信号的个数。
在一示例中，所述数字环路滤波器还包括以下中的至少一个：设置在所述比例路径中的第一比例调节单元，用于调节所述第一比例；以及设置在所述积分路径中的第二比例调节单元，用于调节所述第二比例。
在一示例中，所述第一比例调节单元和所述第二比例调节单元使用相同的调节系数对所述第一比例和所述第二比例进行等比调节。
在一示例中，所述相位追踪电路还包括：系数控制单元，用于控制对所述第一比例和所述第二比例中的至少一个进行调节的调节系数。当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前或者更滞后并且持续预定周期时，所述动态检测调整单元生成第一系数调整信号，所述系数控制单元响应于所述第一系数调整信号提高所述调节系数以增大所述第一比例和所述第二比例中的所述至少一个，直到达到最大比例。当所述相位指示信号指示所述载波信号的相位在比所述参考时钟信号的相位更超前和更滞后之间跳变并且所述跳变达到预定次数时，所述动态检测调整单元生成第二系数调整信号，所述系数控制单元响应于所述第二系数调整信号降低所述调节系数以减小所述第一比例和所述第二比例中的所述至少一个，直到达到基础比例。
在一示例中，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前或者更滞后并且持续预定周期时，所述动态检测调整单元先生成所述第一系数调整信号以增大所述第一比例和所述第二比例中的所述至少一个，直到达到最大比例，然后再生成所述第一分频比调整信号以提高所述分频器的分频档位直到达到最高档位。当所述相位指示信号指示所述载波信号的相位在比所述参考时钟信号的相位更超前和更滞后之间跳变并且所述跳变达到预定次数时，所述动态检测调整单元先生成所述第二分频比调整信号以降低所述分频器的分频档位直到达到基础档位，然后再生成所述第二系数调整信号以减小所述第一比例和所述第二比例中的所述至少 一个，直到达到基础比例。
根据一实施例，一种相位追踪方法可包括：对时钟信号进行分频处理以获得载波信号；比较所述载波信号和参考时钟信号的相位，以生成相位指示信号；基于所述相位指示信号来调整所述时钟信号的相位和所述分频处理的分频比，使得所述载波信号的相位更接近于所述参考时钟信号的相位。
在一示例中，基于所述相位指示信号来调整所述分频处理的分频比包括：当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前或者更滞后并且持续预定周期时，提高所述分频处理的分频档位，直到达到最高档位；或者当所述相位指示信号指示所述载波信号的相位在比所述参考时钟信号的相位更超前和更滞后之间跳变并且所述跳变达到预定次数时，降低所述分频处理的分频档位，直到达到基础档位。所述分频处理具有所述基础档位以及至少一个更高档位，所述基础档位具有基础分频比N，所述更高档位具有更高分频比N+x或者更低分频比N-x，N为预设的正整数，x为比N更小的正整数并且档位越高，x的值越大，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前时，所述更高档位具有所述更高分频比N+x，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更滞后时，所述更高档位具有更低分频比N-x。
在一示例中，所述基础分频比N使得所述载波信号的频率等于所述参考时钟信号的频率。
在一示例中，基于所述相位指示信号来调整所述时钟信号的相位包括：基于所述相位指示信号生成选择指示信号；以及基于所述选择指示信号从多相时钟信号中选择一个时钟信号。当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前时，所述选择指示信号指示从所述多相时钟信号中选择一个比当前选择的时钟信号相位更滞后的时钟信号。当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更滞后时，所述选择指示信号指示从所述多相时钟信号中选择一个比当前选择的时钟信号相位更超前的时钟信号。
在一示例中，基于所述相位指示信号生成选择指示信号包括：生成与所述相位指示信号成第一比例的第一比例信号；生成与所述相位指示信号成第二比例的第二比例信号；对所述第二比例信号进行积分，以获得积分信号；对所述第一比例信号和所述积分信号进行加法运算，以获得二者的和值；将 所述和值关于预定值进行取余运算，以生成所述选择指示信号。
在一示例中，所述预定值等于所述多相时钟信号中包括的具有不同相位的时钟信号的个数。
在一示例中，所述方法还包括：基于所述相位指示信号调整所述第一比例和所述第二比例中的至少一个。
在一示例中，调整所述第一比例和所述第二比例中的至少一个包括：当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前或者更滞后并且持续预定周期时，增大所述第一比例和所述第二比例中的所述至少一个，直到达到最大比例；或者当所述相位指示信号指示所述载波信号的相位在比所述参考时钟信号的相位更超前和更滞后之间跳变并且所述跳变达到预定次数时，减小所述第一比例和所述第二比例中的所述至少一个，直到达到基础比例。
在一示例中，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前或者更滞后并且持续预定周期时，先增大所述第一比例和所述第二比例中的所述至少一个，直到达到最大比例，然后再提高所述分频处理的分频档位直到达到最高档位。当所述相位指示信号指示所述载波信号的相位在比所述参考时钟信号的相位更超前和更滞后之间跳变并且所述跳变达到预定次数时，先降低所述分频处理的分频档位直到达到基础档位，然后再减小所述第一比例和所述第二比例中的所述至少一个，直到达到基础比例。
根据一实施例，一种相位追踪电路可包括：分频器，用于对第一时钟信号进行分频处理以获得载波信号；鉴相器，用于比较所述载波信号和参考时钟信号的相位，以生成相位指示信号；相位调谐模块，用于基于所述相位指示信号来调整所述第一时钟信号的相位，以使得所述载波信号的相位更接近于所述参考时钟信号的相位；以及控制模块，用于基于所述相位指示信号来调整所述相位调谐模块的运行时钟，以控制所述相位调谐模块的相位调整速度。
在一示例中，所述鉴相器是二进制鉴相器，当所述载波信号的相位比所述参考时钟信号的相位超前时，所述二进制鉴相器输出第一指示信号，当所述载波信号的相位比所述参考时钟信号的相位滞后时，所述二进制鉴相器输出第二指示信号。
在一示例中，所述相位调谐模块包括：数字环路滤波器，用于基于所述相位指示信号来生成第一时钟选择信号；以及第一时钟选择单元，用于基于所述第一时钟选择信号从多相时钟信号中选择一个时钟信号作为所述第一时钟信号。
在一示例中，所述控制模块包括：动态检测调整单元，用于检测所述鉴相器生成的相位指示信号，并且生成第二时钟选择信号；以及第二时钟选择单元，用于基于所述第二时钟选择信号从多个第二时钟信号中选择一个作为所述数字环路滤波器的运行时钟。
在一示例中，所述多个第二时钟信号包括所述分频器提供的一个或多个分频信号。
在一示例中，所述多个第二时钟信号还包括所述第一时钟选择单元提供的所述第一时钟信号。
在一示例中，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前或者更滞后并且持续预定周期时，所述动态检测调整单元生成的第二时钟选择信号指示所述第二时钟选择单元从所述多个第二时钟信号中选择一个比当前选择的时钟信号更高频率的时钟信号。当所述相位指示信号指示所述载波信号的相位在比所述参考时钟信号的相位更超前和更滞后之间跳变并且所述跳变达到预定次数时，所述动态检测调整单元生成的第二时钟选择信号指示所述第二时钟选择单元从所述多个第二时钟信号中选择一个比当前选择的时钟信号更低频率的时钟信号。
在一示例中，所述载波信号是所述分频器提供的多个分频信号中具有最低频率的分频信号。
在一示例中，所述多相时钟信号包括M个不同相位的时钟信号，M是大于一的整数。所述数字环路滤波器生成的第一时钟选择信号表示M个索引值中的一个，以指示所述第一时钟选择单元从所述M个不同相位的时钟信号中选择一个对应的时钟信号作为所述第一时钟信号。
在一示例中，当所述鉴相器生成的相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位超前并且持续预定周期时，所述数字环路滤波器生成的第一时钟选择信号指示所述第一时钟选择单元从所述多相时钟信号中选择一个比当前选择的时钟信号相位更滞后的时钟信号。当所述鉴相器生成的相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位 滞后并且持续预定周期时，所述数字环路滤波器生成的第一时钟选择信号指示所述第一时钟选择单元从所述多相时钟信号中选择一个比当前选择的时钟信号相位更超前的时钟信号。
在一示例中，所述数字环路滤波器包括：比例路径，用于生成与所述相位指示信号成第一比例的第一比例信号；积分路径，用于生成与所述相位指示信号成第二比例的第二比例信号，并且使用积分器对所述第二比例信号进行积分处理以生成积分信号；加法器，用于对所述第一比例信号和所述积分信号进行加法运算，以输出二者的和值；以及取余单元，用于对从所述加法器接收到的所述和值关于预定值进行取余运算，以生成表示余数的所述第一时钟选择信号。
在一示例中，所述第二时钟选择单元选择的第二时钟信号用作所述积分路径中的积分器的运行时钟，所述预定值等于所述多相时钟信号中包括的具有不同相位的时钟信号的个数。
在一示例中，所述数字环路滤波器还包括以下中的至少一个：设置在所述比例路径中的第一比例调节单元，用于调节所述第一比例；以及设置在所述积分路径中的第二比例调节单元，用于调节所述第二比例。
在一示例中，所述第一比例调节单元和所述第二比例调节单元使用相同的调节系数对所述第一比例和所述第二比例进行等比调节。
在一示例中，所述相位追踪电路还包括：系数控制单元，用于基于所述动态检测调整单元生成的系数调整信号来控制对所述第一比例和所述第二比例中的至少一个进行调节的调节系数。当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前或者更滞后并且持续预定周期时，所述动态检测调整单元生成的系数调整信号指示所述系数控制单元提高所述调节系数以增大所述第一比例和所述第二比例中的所述至少一个，直到达到最大比例。当所述相位指示信号指示所述载波信号的相位在比所述参考时钟信号的相位更超前和更滞后之间跳变并且所述跳变达到预定次数时，所述动态检测调整单元生成的系数调整信号指示所述系数控制单元降低所述调节系数以减小所述第一比例和所述第二比例中的所述至少一个，直到达到基础比例。
在一示例中，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前或者更滞后并且持续预定周期时，所述动态检测调整 单元先生成所述系数调整信号以增大所述第一比例和所述第二比例中的所述至少一个，直到达到最大比例，然后再生成所述第二时钟选择信号以提高所述第二时钟选择单元选择的第二时钟信号的频率直到达到最高频率。当所述相位指示信号指示所述载波信号的相位在比所述参考时钟信号的相位更超前和更滞后之间跳变并且所述跳变达到预定次数时，所述动态检测调整单元先生成所述第二时钟选择信号以降低所述第二时钟选择单元选择的第二时钟信号的频率直到达到最低频率，然后再生成所述系数调整信号以减小所述第一比例和所述第二比例中的所述至少一个，直到达到基础比例。
根据一实施例，一种相位追踪方法可包括：分频器对第一时钟信号进行分频处理以获得载波信号；鉴相器比较所述载波信号和参考时钟信号的相位，以生成相位指示信号；相位调谐模块基于所述相位指示信号来调整所述第一时钟信号的相位，以使得所述载波信号的相位更接近于所述参考时钟信号的相位；以及控制模块基于所述相位指示信号来调整所述相位调谐模块的运行时钟，以控制所述相位调谐模块的相位调整速度。
在一示例中，相位调谐模块基于所述相位指示信号来调整所述第一时钟信号的相位包括：利用数字环路滤波器基于所述相位指示信号来生成第一时钟选择信号；以及利用第一时钟选择单元基于所述第一时钟选择信号从多相时钟信号中选择一个时钟信号作为所述第一时钟信号。
在一示例中，控制模块基于所述相位指示信号来调整所述相位调谐模块的运行时钟包括：利用动态检测调整单元检测所述鉴相器生成的指示信号，并且生成第二时钟选择信号；以及利用第二时钟选择单元基于所述第二时钟选择信号从多个第二时钟信号中选择一个作为所述数字环路滤波器的运行时钟。
在一示例中，所述多个第二时钟信号包括所述分频器提供的一个或多个分频信号。
在一示例中，所述多个第二时钟信号还包括所述第一时钟选择单元提供的所述第一时钟信号。
在一示例中，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前或者更滞后并且持续预定周期时，所述动态检测调整单元生成的第二时钟选择信号指示所述第二时钟选择单元从所述多个第二时钟信号中选择一个比当前选择的时钟信号更高频率的时钟信号。当所述相 位指示信号指示所述载波信号的相位在比所述参考时钟信号的相位更超前和更滞后之间跳变并且所述跳变达到预定次数时，所述动态检测调整单元生成的第二时钟选择信号指示所述第二时钟选择单元从所述多个第二时钟信号中选择一个比当前选择的时钟信号更低频率的时钟信号。
在一示例中，所述载波信号是所述分频器提供的多个分频信号中具有最低频率的分频信号。
在一示例中，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位超前并且持续预定周期时，所述数字环路滤波器生成的第一时钟选择信号指示所述第一时钟选择单元从所述多相时钟信号中选择一个比当前选择的时钟信号相位更滞后的时钟信号。当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位滞后并且持续预定周期时，所述数字环路滤波器生成的第一时钟选择信号指示所述第一时钟选择单元从所述多相时钟信号中选择一个比当前选择的时钟信号相位更超前的时钟信号。
在一示例中，利用数字环路滤波器基于所述相位指示信号来生成第一时钟选择信号包括：利用比例路径生成与所述相位指示信号成第一比例的第一比例信号；利用积分路径生成与所述相位指示信号成第二比例的第二比例信号，并且使用设置在所述积分路径中的积分器对所述第二比例信号进行积分处理以生成积分信号；利用加法器对所述第一比例信号和所述积分信号进行加法运算，以输出二者的和值；以及利用取余单元对所述和值关于预定值进行取余运算，以生成表示余数的所述第一时钟选择信号。
在一示例中，所述第二时钟选择单元选择的第二时钟信号用作所述积分路径中的积分器的运行时钟以控制对所述第二比例信号进行积分的速度，所述预定值等于所述多相时钟信号中包括的具有不同相位的时钟信号的个数。
在一示例中，利用数字环路滤波器基于所述相位指示信号来生成第一时钟选择信号还包括以下步骤中的至少一个：利用设置在所述比例路径中的第一比例调节单元调节所述第一比例；以及利用设置在所述积分路径中的第二比例调节单元调节所述第二比例。
在一示例中，所述第一比例调节单元和所述第二比例调节单元使用相同的调节系数对所述第一比例和所述第二比例进行等比调节。
在一示例中，所述方法还包括：利用系数控制单元基于所述动态检测调 整单元生成的系数调整信号来控制对所述第一比例和所述第二比例中的至少一个进行调节的调节系数。当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前或者更滞后并且持续预定周期时，所述动态检测调整单元生成的系数调整信号指示所述系数控制单元提高所述调节系数以增大所述第一比例和所述第二比例中的所述至少一个，直到达到最大比例。当所述相位指示信号指示所述载波信号的相位在比所述参考时钟信号的相位更超前和更滞后之间跳变并且所述跳变达到预定次数时，所述动态检测调整单元生成的系数调整信号指示所述系数控制单元降低所述调节系数以减小所述第一比例和所述第二比例中的所述至少一个，直到达到基础比例。
在一示例中，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前或者更滞后并且持续预定周期时，所述动态检测调整单元先生成所述系数调整信号以增大所述第一比例和所述第二比例中的所述至少一个，直到达到最大比例，然后再生成所述第二时钟选择信号以提高所述第二时钟选择单元选择的第二时钟信号的频率直到达到最高频率。当所述相位指示信号指示所述载波信号的相位在比所述参考时钟信号的相位更超前和更滞后之间跳变并且所述跳变达到预定次数时，所述动态检测调整单元先生成所述第二时钟选择信号以降低所述第二时钟选择单元选择的第二时钟信号的频率直到达到最低频率，然后再生成所述系数调整信号以减小所述第一比例和所述第二比例中的所述至少一个，直到达到基础比例。
根据一实施例，还提供一种电子设备，其可以包括上述相位追踪电路中的任意一种。
本发明的上述和其他特征和优点将从下面结合附图对示例性实施例的描述变得显而易见。
附图说明
图1示出根据本发明一实施例的相位追踪电路的示意图。
图2示出根据本发明一实施例的相位追踪电路的示意图。
图3示出根据本发明一实施例的相位追踪电路的示意图。
图4示出根据本发明一实施例的相位追踪电路的示意图。
图5示出根据本发明一实施例的数字环路滤波器的示意图。
图6示出根据本发明一实施例的数字环路滤波器中的积分信号的示意图。
图7示出根据本发明一实施例的通过改变分频比来调整相位的示意图。
图8示出根据本发明一实施例的分频档位设计的示意图。
图9示出根据本发明一实施例的相位追踪方法的流程图。
图10示出根据本发明一实施例的第一时钟信号的相位调节过程的流程图。
图11示出根据本发明一实施例的第二时钟信号的频率调节过程和/或分频比调节过程的流程图。
图12示出根据本发明一实施例的生成第二时钟选择信号和/或分频比调整信号的过程的流程图。
图13示出根据本发明一实施例的生成第一时钟选择信号的过程的流程图。
图14示出根据本发明一实施例的进行系数调节和积分时钟频率调节的过程的流程图。
图15示出根据本发明一实施例的进行系数调节和分频档位调节的过程的流程图。
图16示出根据本发明一实施例的组合使用系数调节、积分时钟频率调节和分频档位调节的过程的流程图。
图17示出根据本发明一实施例的组合使用系数调节、积分时钟频率调节和分频档位调节的过程的流程图。
图18示出根据本发明一实施例的电子设备的示意图。
具体实施方式
下面将参照附图来描述本发明的一些示范性实施例。为了清楚和完整地描述这些示范性实施例，下面的描述提供了一些特定细节。但是应理解，本发明不应被限制到这些示范性实施例的特定细节。而是，可以在没有这些特定细节或者采用其他替代方式的情况下，实施本发明的实施例，而不会偏离权利要求定义的本发明的思想和原理。
目前，用于有源负载调制(ALM)模式下的NFC卡模拟装置的相位追踪技术包括基于无源匹配网络的技术方案和使用全数字锁相环(ADPLL)的技术方案。无源匹配网络的调节并非是线性的，在不同阻值时相位调整的步进不一致，难以在较大的相差范围内(例如0度到180度)实现高精度的调 整。此外，阻值调整也会改变芯片的阻抗，对无线通信产生一定的不利影响。全数字锁相环具有复杂的设计和较高的成本，在卡模拟模式下产生的频率和相位信息完全来自于从读卡器信号恢复的时钟，而从读卡器信号恢复的时钟往往是间断的。例如，当读卡器发射信号时，数据处于低电平时磁场消失；又比如当NFC卡模拟装置本身发射信号时，过大的发射信号将淹没读卡器的磁场信号。因此，在间断的参考时钟条件下，对于锁相环的环路锁定速度要求非常高，因为只有非常短的时间用于频率和相位的锁定，这个问题难以解决。在传统设计中，快速锁定意味着环路带宽更大，带来更多由参考时钟引入的相位噪声，其会影响电路性能；另一方面，降低环路带宽虽然能够部分提升相位噪声性能，但难以达到快速锁定的要求。
理想的相位追踪技术需要在大的相差范围内实现快速的相位追踪和锁定，并且期望有高的追踪精度。此外，考虑到在电池供电的便携式电子设备中的应用，还期望在相位追踪和锁定期间具有小的功耗，这对现有的相位追踪技术提出了挑战。
图1示出根据本发明一实施例的相位追踪电路100的示意图。如图1所示，相位追踪电路100包括分频器110、鉴相器120、相位调谐模块130和控制模块140。
分频器110可以对高频时钟信号(下面称为第一时钟信号)进行分频处理，以获得分频后的低频时钟信号，其可以用作载波信号，并且与从读卡器磁场恢复的时钟频率相同。输入到分频器110的高频信号的频率可以是分频器110输出的分频信号的频率的N倍，其中N是分频器110的分频比。应理解，在本申请中“高频”和“低频”都是相对概念，描述频率的相对大小，但是并不对频率的绝对大小即频率范围进行任何意义上的限定。
鉴相器120可以比较分频器110输出的载波信号和参考时钟信号的相位，并且输出相位指示信号。这里，参考时钟信号可以是从NFC读卡器恢复的时钟信号，相位追踪电路100用于使载波信号的相位追踪或接近于参考时钟信号的相位。
相位调谐模块130可以基于鉴相器120输出的相位指示信号来调整提供给分频器110的第一时钟信号的相位，使得分频器110输出的载波信号的相位追踪/更接近于参考时钟信号的相位。
控制模块140可以基于鉴相器120输出的相位指示信号来调整相位调谐 模块130的运行时钟信号(下面称为第二时钟信号)的频率和分频器110的分频比中的至少一个，从而控制相位调谐模块130的相位调整速度，这将在下面进一步详细描述。
图2、图3和图4分别示出相位追踪电路100的示例性实施方式100a、100b和100c。在图2所示的相位追踪电路100a中，相位调谐模块130可包括数字环路滤波器(DLF)132和第一时钟选择单元134，并且可选地还可以包括系数控制单元136。控制模块140可包括动态检测调整单元142和第二时钟选择单元144。在图3所示的相位追踪电路100b中，控制模块140可包括动态检测调整单元142和分频比控制单元146。在图4所示的相位追踪电路100c中，控制模块140可包括动态检测调整单元142、第二时钟选择单元144以及分频比控制单元146。在下文中，为了描述方便，也可以将图2所示的相位追踪电路100a、图3所示的相位追踪电路100b和图4所示的相位追踪电路100c每个都称为相位追踪电路100。
在一实施例中，鉴相器120可以是二进制鉴相器(BBPD)，当载波信号(或者称为分频时钟信号)的相位比参考时钟信号的相位超前时，鉴相器120输出的相位指示信号可以是高电平“1”；当载波信号的相位比参考时钟信号的相位滞后时，鉴相器120输出的相位指示信号可以是低电平“-1”，或者反之亦可。当鉴相器120的使能信号关断时(例如EN＝0，未示出)，鉴相器120可以输出“0”。
数字环路滤波器(DLF)132可以检测鉴相器120输出的相位指示信号，并且基于其指示的载波信号和参考时钟信号的相对相位关系，生成第一时钟选择信号来控制第一时钟选择单元134从多相时钟信号中选择相应的时钟信号。例如，当鉴相器120指示载波信号的相位比参考时钟信号的相位超前时，数字环路滤波器132可以指示第一时钟选择单元134从多相时钟信号中选择相位更滞后的时钟信号；当鉴相器120指示载波信号的相位比参考时钟信号的相位滞后时，数字环路滤波器132可以指示第一时钟选择单元134从多相时钟信号中选择相位更超前的时钟信号。当鉴相器120输出的相位指示信号指示载波信号的相位在比参考时钟信号的相位超前和滞后之间来回跳变时，第一时钟选择单元134选择的时钟信号在两个信号之间来回跳变，总体等效为相位不变，从而实现相位锁定状态。
图5示出根据本发明一实施例的数字环路滤波器200的示意图，数字环 路滤波器200可以用于图2-4所示的相位追踪电路100中的数字环路滤波器132。
参照图5，数字环路滤波器200可包括比例路径210和积分路径220，二者在第一输入端口In-1处接收鉴相器120输出的相位指示信号作为输入。比例路径210和积分路径220可以分别生成与相位指示信号成第一比例“a”的第一比例信号和与相位指示信号成第二比例“p”的第二比例信号。例如，比例路径210可包括第一寄存器212，其中存储有第一比例系数“a”，以输出第一比例信号；积分路径220可包括第二寄存器222，其中存储有第二比例系数“p”，以输出第二比例信号。例如，当鉴相器120的输出为“1”时，比例路径210生成的第一比例信号为“a”，积分路径220生成的第二比例信号为“p”；当鉴相器120的输出从“1”变为“-1”时，第一比例信号产生“-2a”的变化，从“a”变为“-a”，第二比例信号产生“-2p”的变化，从“p”变为“-p”。类似地，当鉴相器120的输出从“-1”变为“1”时，第一比例信号产生“+2a”的变化，从“-a”变为“a”，第二比例信号产生“+2p”的变化，从“-p”变为“p”。
在一实施例中，比例路径210生成的第一比例信号和积分路径220生成的第二比例信号，或者说第一比例系数“a”和第二比例系数“p”，还可以被调整。例如，比例路径210可包括第一比例调节单元例如乘法器214，其使用调整因子与第一比例信号相乘，以生成调整后的第一比例信号；积分路径220可包括第二比例调节单元例如乘法器224，其使用调整因子与第二比例信号相乘，以生成调整后的第二比例信号。在图5所示的实施例中，第一比例调节单元214和第二比例调节单元224可以从第二输入端口In-2接收相同的调整因子，从而对第一比例信号和第二比例信号进行等比调整。在另一些实施例中，第一比例调节单元214和第二比例调节单元224也可以接收不同的调整因子以对第一比例信号和第二比例信号进行不同的调整，或者可以仅设置第一比例调节单元214和第二比例调节单元224中的任何一个以对第一比例信号和第二比例信号之一进行调整。
在积分路径220中，调整后的第二比例信号可以在积分器226中进行积分处理，以生成积分信号。积分器226可以从第三输入端口In-3接收积分时钟信号，以根据积分时钟对调整后的第二比例信号进行积分处理。图6示出了积分器226生成的积分信号的示意图。如图6所示，基于在第三输入端口 In-3上接收到的积分时钟信号，积分器226对调整后的第二比例信号“px”或者“-px”进行积分，其中p是第二比例系数，x是调整系数。当调整后的第二比例信号是“px”时，假设p为正数(p也可以为负数)，积分信号随着积分周期而逐渐递增，并且增大步进为“px”。当调整后的第二比例信号是“-px”时，积分信号随着积分周期而逐渐递减，并且减小步进为“-px”。可以理解，当调整后的第二比例信号从“px”变为“-px”时，积分信号从递增变为递减；当调整后的第二比例信号从“-px”变为“px”时，积分信号从递减变为递增。根据图5可以理解，积分信号的递增或递减速度与第二比例系数p、调整系数x以及积分时钟信号的频率相关。
继续参照图5，积分路径220中的积分器226输出的积分信号和比例路径210输出的第一比例信号可以在加法器232中执行加法处理，获得二者的和值。可以理解，当鉴相器120输出的相位指示信号保持不变时，积分器226输出的积分信号随时间而递增或递减，比例路径210输出的第一比例信号随时间保持不变，从而加法器232输出的和值随时间而递增或递减。
加法器232输出的和值可以在取余(Mod)单元234中关于预定值M进行取余运算，从而生成表示余数的第一时钟选择信号，其在输出端口Out处输出。随着积分器226输出的积分值增大，取余单元234输出的第一时钟选择信号表示的余数值从0增大到1，再继续增大一直到M-1，然后继续增大到0，如此循环变化。或者，当积分器226输出的积分值递减时，取余单元234输出的第一时钟选择信号表示的余数值从0减小到M-1，再减小到M-2，一直减小到0，如此循环变化。这里，第一时钟选择信号表示的余数值用作索引，用于第一时钟选择单元134从M个不同相位的时钟信号中选择一个与索引值对应的时钟信号，作为提供给分频器110的第一时钟信号。
在一些实施例中，也可以省略比例路径210，而仅采用积分路径220，同样也可以生成包含索引值(即余数)的第一时钟选择信号，以用于从多相时钟信号中选择一个对应的时钟信号。但是应理解，通过设置比例路径210，相当于在环路中引入了参考零点，可以避免环路起振而产生噪声。因此，引入比例路径210后，相位追踪电路100可以具有改善的相位噪声性能。
从上面的描述可以理解，数字环路滤波器200输出的第一时钟选择信号表示的索引值的变化速度，也就是第一时钟选择单元134从多相时钟信号中选择的第一时钟信号的相位变化速度，取决于积分器226的积分速度，也就 是积分时钟信号的频率，第一比例系数a和第二比例系数p的值，以及调节系数x的值。因此，通过调节积分时钟信号的频率和调节因子x的值，可以调节相位追踪电路100的相位调整速度，这将在下面进一步详细描述。
返回参照图2-4，第一时钟选择单元134基于数字环路滤波器132输出的第一时钟选择信号从M个不同相位的时钟信号中选择一个时钟信号，作为提供给分频器110的第一时钟信号。这M个不同相位的时钟信号可以具有360°/M的相位差，例如当M＝12时，M个时钟信号的相位可以分别为0°、30°、60°、90°、120°、150°、180°、210°、240°、270°、300°和330°，当然也可以具有在360°范围内均匀分布的其他相位值。
例如，当鉴相器120的输出为“1”时，表示分频器110提供的载波信号(即分频信号)的相位比参考时钟信号的相位超前。此时，随着积分器226输出的积分值逐渐增大，数字环路滤波器132输出的第一时钟选择信号表示的余数逐渐增大，例如在预定积分周期后余数值增大一，使得第一时钟选择单元134从M个(M是大于1的整数)不同相位的时钟信号中选择相位更滞后的时钟信号，从而分频器110提供的载波信号的相位也向后移动。当载波信号的相位变得比参考时钟信号的相位更滞后时，鉴相器120的输出变为“-1”。此时，积分器226输出的积分值随时间逐渐减小，数字环路滤波器132输出的第一时钟选择信号表示的余数也逐渐减小，例如预定积分周期后余数值减小一，使得第一时钟选择单元134从M个不同相位的时钟信号中选择相位更超前的时钟信号，从而分频器110提供的载波信号的相位也向前移动。当鉴相器120的输出在“1”和“-1”之间来回变化时，表明第一时钟选择单元134选择的时钟信号在比参考时钟信号相位超前的一个时钟信号和比参考时钟信号相位滞后的一个时钟信号之间来回变化，总体等效为载波信号的相位等于或最接近于参考时钟信号的相位，从而达到相位锁定状态。
这里，第一时钟选择单元134选择的M个时钟信号之间的相位步进为360°/M，但是当分频器110进行分频处理之后，相邻分频信号之间的相位步进(即相位差)变为360°/(M*N)，其中N是分频器110的分频比，因为分频信号的脉冲宽度是分频前的时钟信号的脉冲宽度的N倍。例如，NFC读卡器的信号频率为13.56MHz，多相时钟信号的频率为867.84MHz，可以采用分频比N＝64的分频器110。当然，也可以采用其他分频比，例如多相时钟信号的频率为542.4MHz时，可以采用N＝40的分频比。
例如，当M＝12时，多相时钟信号之间的相位步进为30°，那么分频后的信号的相位步进变为0.46875°，这样就可以实现精确的相位调整和跟踪。当第一时钟选择信号表示的索引值从0增大到11时，第一时钟选择单元134选择的时钟信号的相位推迟了330°，分频后的时钟信号的相位推迟了5.15625°；然后索引值从11变为0，第一时钟选择单元134选择的时钟信号的相位继续推迟30°，分频后的时钟信号的相位继续推迟0.46875°。这样，循环增大索引值可以使分频信号的相位不断向后移动；类似地，循环减小索引值可以使分频信号的相位不断向前移动。这样，可以在大的范围内改变分频信号(即载波信号)的相位。
这种方案通过采用分频处理，大大提高了相位调节的精度，也就是相位追踪电路100的相位追踪精度。但是，其调整相位的速度较慢，每次调整的步进是360°/(M*N)，因此可能需要较长时间才能实现环路锁定，而且相位调整精度越高，给定相差时所需的相位调整时间越长。为了缩短相位锁定时间，本发明的实施例还通过调整数字环路滤波器132的比例系数和积分频率，来加快相位调整速度，这将在下面进一步详细描述。
继续参照图2-4，动态检测调整单元142可以检测鉴相器120生成的相位指示信号，并且生成提供给系数控制单元136的系数调整信号以控制对数字环路滤波器132的第一比例系数a和第二比例系数p进行调节的调节系数，并且还生成提供给第二时钟选择单元144的第二时钟选择信号和提供给分频比控制单元146的分频比调整信号中的至少一个。第二时钟选择单元144可以基于第二时钟选择信号从多个第二时钟信号中选择一个作为数字环路滤波器132的运行时钟，分频比控制单元可以基于分频比调整信号来控制分频器110的分频比，这将在下面详细说明。
如前所述，可以通过调节数字环路滤波器132中的第一比例系数a和第二比例系数p中的至少一个，优选地至少调节第二比例系数p(因为其通过积分运算能够更快地改变加法器232输出的和值)，可以改变第一时钟选择单元134选择的第一时钟信号的相位调整速度。参照图2-4以及图5，系数控制单元136可以响应于动态检测调整单元142提供的系数调整信号来控制提供到数字环路滤波器132/200的第二输入端口In-2上的、用于对第一比例系数a和第二比例系数p中的至少一个进行调节的调节系数的大小。例如，当动态检测调整单元142检测到鉴相器120指示载波信号的相位比参考时钟 信号的相位更超前或者更滞后(相位指示信号为“1”或“-1”)并且持续预定周期数时，可以认为载波信号和参考时钟信号之间的相位差较大，此时动态检测调整单元142可以生成系数调整信号以指示系数控制单元136提高调节系数，从而增大第一比例系数a和第二比例系数p中的至少一个，加快相位调整速度。可以重复该操作，直到达到最大比例系数。当动态检测调整单元142检测到鉴相器120指示载波信号的相位在比参考时钟信号的相位更超前和更滞后之间跳变(相位指示信号在“1”和“-1”之间跳变)并且跳变达到预定次数时，可以认为载波信号的相位已经被调节到接近于参考时钟信号的相位，此时动态检测调整单元142可以生成系数调整信号以指示系数控制单元136降低调节系数，从而减小第一比例系数a和第二比例系数p中的至少一个，降低相位调整速度，直到达到最低比例系数。可以理解，增大和减小比例系数a和p可以改变相位调整速度，但是并不会影响相位调整精度。
第二时钟选择单元144可以基于动态检测调整单元142提供的第二时钟选择信号来从多个第二时钟信号中选择一个时钟信号，作为数字环路滤波器132的运行时钟，或者更具体而言，作为数字环路滤波器132中的积分器226的运行时钟。这里，第二时钟选择单元144选择的多个第二时钟信号可以包括分频器110提供的一个或多个分频信号。例如，分频器110可以是多级2/3分频器，包括多个2/3分频单元的级联结构，每个级可以提供2分频信号或者3分频信号，从而分频器110的多个级可以提供多个不同分频比的分频信号。在一实施例中，分频器110提供给鉴相器120的作为载波信号的分频信号可以是具有最大分频比(也就是最低频率)的分频信号，也就是分频器110的最终级输出的分频信号。在一实施例中，第二时钟选择单元144选择的多个第二时钟信号还可以包括第一时钟选择单元134提供的第一时钟信号，其比分频器110提供的分频信号具有更高的频率。当然，第二时钟选择单元144选择的多个第二时钟信号也可以由其他电路提供。可以理解，第二时钟选择单元144不限于这里描述的实施例。例如，第二时钟选择单元144也可以实施为压控振荡器(VCO)，其根据动态检测调整单元142提供的电压信号来调整输出信号的频率。
在一实施例中，当鉴相器120指示载波信号的相位比参考时钟信号的相位更超前或者更滞后(相位指示信号为“1”或者“-1”)并且持续预定周 期数时(可以与用于比例系数调整的预定周期数相同或不同)，可以认为载波信号和参考时钟信号之间的相位差可能较大，此时动态检测调整单元142生成的第二时钟选择信号可以指示第二时钟选择单元144选择更高频率的时钟信号，从而可以加快数字环路滤波器132中的积分操作，使得数字环路滤波器132更快地调整第一时钟选择单元134选择的第一时钟信号的相位。可以重复此操作，以不断提高第二时钟选择单元144选择的时钟信号的频率，直到达到最高频率。当鉴相器120指示载波信号的相位在比参考时钟信号的相位更超前和更滞后之间跳变(相位指示信号在“1”和“-1”之间跳变)并且跳变达到预定次数时(可以与用于比例系数调整的预定跳变次数相同或不同)，可以认为载波信号的相位已经被调整到参考时钟信号的相位前后附近，此时动态检测调整单元142生成的第二时钟选择信号可以指示第二时钟选择单元144选择更低频率的时钟信号，从而可以减慢数字环路滤波器132中的积分操作，使得数字环路滤波器132调整第一时钟选择单元134选择的第一时钟信号的相位的速度变慢。可以重复此操作，以不断降低第二时钟选择单元144选择的时钟信号的频率，直到达到最低频率。可以理解，当积分频率增大时，数字环路滤波器132的功耗也会增大；当积分频率减小时，数字环路滤波器132的功耗会降低。
图7示意性示出了分频器110的分频比N变化时对分频器110输出的载波信号的相位的影响。参照图7，假设系统设计的分频比N＝64，此时高电平和低电平分别对应于分频前的高频时钟信号的32个脉冲。这里，系统设计分频比是使得载波信号的频率与参考时钟信号的频率相等的分频比，因此也将系统设计分频比称为基础分频比。当分频比从64变为63时，那么下一周期的63分频信号的起点要比64分频信号的起点提前一个短/高频脉冲，也就是64分频信号的周期的1/64，因此相位提前了360°/64＝5.625°；再下一个周期，63分频信号比64分频信号相位提前了11.25°，以此类推。当分频比从64变为65时，那么下一周期的65分频信号的起点要比64分频信号的起点之后一个短/高频脉冲，也就是64分频信号的周期的1/64，因此相位滞后了360°/64＝5.625°；再下一个周期，65分频信号比64分频信号相位滞后了11.25°，以此类推。可以理解，当分频比从N变为N±x时，相比提前或滞后的步进为(360°*x)/N，可以根据需要设置x的值。因此，通过改变分频比，可以快速调整载波信号的相位，从而加快相位调节速度。
分频比控制单元146可以基于动态检测调整单元142提供的分频比调整信号来控制分频器110的分频比。在一实施例中，可以将分频器110的分频比设置为多个档位，其示例示于图8中。图8示出了0-3一共四个档位，但是也可以采用更多或更少的档位，例如两个档位、三个档位、五个档位等。档位0也称为基础档位，其对应于基础分频比N，也就是使载波信号的频率和参考信号的频率相等的分频比。当达到锁定状态时，分频器110的分频比应为基础分频比N。更高档位的分频比为N±x，档位越高，x的值越大，其中N和x都是正整数，且N大于x。例如，档位1的分频比可以为N±1，档位2的分频比可以为N±2，档位3的分频比可以为N±3，以此类推。当相位指示信号指示载波信号的相位比参考时钟信号的相位超前时，档位的分频比可以为N+x，以使用更大的分频比，使得载波信号的相位滞后；当相位指示信号指示载波信号的相位比参考时钟信号的相位滞后时，档位的分频比可以为N-x，以使用更小的分频比，使得载波信号的相位提前。
在一实施例中，当鉴相器120指示载波信号的相位比参考时钟信号的相位更超前或者更滞后(相位指示信号为“1”或者“-1”)并且持续预定周期数时(可以与用于比例系数调整和积分时钟频率调整的预定周期数相同或者不同)，说明载波信号和参考时钟信号之间的相位差较大，此时动态检测调整单元142可以生成分频比调整信号以指示分频比控制单元146提高分频器110的分频档位。可以重复此操作，以不断提高载波信号的相位调整步进，直到达到最高档位。当鉴相器120指示载波信号的相位在比参考时钟信号的相位更超前和更滞后之间跳变(相位指示信号在“1”和“-1”之间跳变)并且跳变达到预定次数时(可以与用于比例系数调整和积分时钟频率调整的预定跳变次数相同或者不同)，说明载波信号的相位已经被调整到参考时钟信号的相位前后附近，此时动态检测调整单元142可以生成分频比调整信号以指示分频比控制单元146降低分频器110的分频档位，以减小载波信号的相位调整步进，直到达到基础档位。可以理解，动态检测调整单元142除了指示分频比控制单元146分频比调整信号以提高或降低分频器110的分频档位之外，还指示分频比控制单元146当前的载波信号相位状态，即超前还是滞后于参考时钟信号的相位，从而分频比控制单元146可以控制分频器110在每个分频档位的分频比是N+x还是N-x。
下面举例说明分频档位的调整过程。例如，开始时，分频器110处于基 础档位(档位0)，此时分频比为64。当动态检测调整单元142检测到鉴相器120的输出为“1”且持续达到例如4个周期时，其指示分频比控制单元146将分频器110的分频档位提高到档位1，此时分频器110的分频比变为65。当动态检测调整单元142又检测到鉴相器120的输出仍为“1”且持续达到例如4个周期时，其指示分频比控制单元146将分频器110的分频档位提高到档位2，此时分频器110的分频比变为66。可以重复此操作，直到分频器110达到最高档位3，此时分频器110的分频比变为67，相位调整步进达到最大。通过上述操作，载波信号的相位不断向后移动，当其变得比参考时钟信号的相位滞后时，鉴相器120的输出从“1”变为“-1”，此时分频器110仍保持在最高档位3，但是分频比从67变为61，载波信号的相位变为向前移动，导致其相位又变得比参考时钟信号的相位超前，鉴相器120的输出又从“-1”变为“1”，分频器110的分频比从61变为67。当动态检测调整单元142检测到鉴相器120的输出在“1”和“-1”之间跳变达到预定次数例如6次时，其指示分频比控制单元146降低分频器110的分频档位，从档位3变为档位2，相位调整步进减小。可以重复此操作，直到分频器110达到基础档位，分频比为64，此时分频比不再影响载波信号的相位，并且载波信号的频率与参考时钟信号相等。
当调整分频器110的分频比N时，分频器110中的各个级输出的分频信号会受到影响，因此第二时钟选择单元144提供给数字环路滤波器132中的积分器226的积分时钟信号的频率也会受到影响。但是应理解，调整分频比的作用是使载波信号的相位以较大的步进向前或向后移动，而积分器226的积分时钟频率变化仅影响第一时钟选择单元134输出的第一时钟信号的相位变化速度，但是并不会对第一时钟信号的相位变化方向(例如增大或减小)产生影响。而且，数字环路滤波器132对载波信号相位的调整步进要远远小于分频器110的分频比变化导致的载波信号相位调整步进。因此，调整分频器110的分频比时，因积分器226的积分时钟频率变化而产生的载波信号相位调整速度变化，并不会对整个相位调整过程带来任何实质性的负面影响。
上面描述的通过数字环路滤波器132的比例系数调整和积分时钟频率调整以及分频器110的分频比调整实现的相位调整速度控制可以单独或者组合组合使用。在一实施例中，当相位指示信号指示载波信号的相位比参考时钟信号的相位更超前或者更滞后并且持续预定周期时，动态检测调整单元142 可以先生成系数调整信号以增大第一比例系数a和第二比例系数p中的至少一个，直到达到最大比例系数；然后再生成第二时钟选择信号以提高第二时钟选择单元144选择的第二时钟信号的频率，直到达到最高频率；然后再生成分频比调整信号以提高分频器110的分频档位。当相位指示信号指示载波信号的相位在比参考时钟信号的相位更超前和更滞后之间跳变并且跳变达到预定次数时，动态检测调整单元142可以先生成分频比调整信号以降低分频器110的分频档位，直到达到基础档位；然后生成第二时钟选择信号以降低第二时钟选择单元144选择的第二时钟信号的频率，直到达到最低频率；然后再生成系数调整信号以减小第一比例系数a和第二比例系数p中的所述至少一个，直到达到基础/最低比例系数。该过程将在下面进一步详细论述，这里仅简单说明。
简言之，在上面描述的相位调整方法中，当加快相位调整速度时，先提升比例系数，然后提升积分时钟频率，最后提升分频比；当降低相位调整速度时，先降低分频比，然后降低积分时钟频率，最后降低比例系数。本发明人意识到，当提升积分时钟频率时，相位追踪电路100的功耗也会增大，而积分时钟频率对相位调节速度的影响要低于分频比变化对相位调节速度的影响。因此，在一实施例中，当提升分频档位时，可以将积分时钟频率置于最低，以节省功耗。具体而言，当相位指示信号指示载波信号的相位比参考时钟信号的相位更超前或者更滞后并且持续预定周期时，动态检测调整单元142可以先生成系数调整信号以增大第一比例系数a和第二比例系数p中的至少一个，直到达到最大比例系数；然后再生成第二时钟选择信号以提高第二时钟选择单元144选择的第二时钟信号的频率，直到达到最高频率；然后再生成分频比调整信号以提高分频器110的分频档位，并且在首次提高分频档位时，生成最小第二时钟设置信号以将第二时钟选择单元144选择的第二时钟信号的频率设置为最低频率。当相位指示信号指示载波信号的相位在比参考时钟信号的相位更超前和更滞后之间跳变并且跳变达到预定次数时，动态检测调整单元142可以先生成分频比调整信号以降低分频器110的分频档位，直到达到基础档位，并且在达到基础档位时，生成最大第二时钟设置信号以将第二时钟选择单元144选择的第二时钟信号的频率设置为最高频率；然后生成第二时钟选择信号以降低第二时钟选择单元144选择的第二时钟信号的频率，直到达到最低频率；然后再生成系数调整信号以减小第一比例系 数a和第二比例系数p中的所述至少一个，直到达到基础/最低比例系数。这样，可以节省相位追踪电路100的功耗。该过程将在下面进一步详细论述，这里仅简单说明。
图9示出根据本发明一实施例的相位追踪方法300的流程图。方法300可以利用上面参照图1-8描述的相位追踪电路100(包括但不限于相位追踪电路100a、相位追踪电路100b和相位追踪电路100c)来实施。参照图9，相位追踪方法300可包括：步骤310，利用分频器110对第一时钟信号进行分频处理，以获得载波信号；步骤320，利用鉴相器120比较载波信号和参考时钟信号的相位，以生成相位指示信号；步骤330，由相位调谐模块130基于相位指示信号来调整第一时钟信号的相位，使得载波信号的相位追踪或更接近于参考时钟信号的相位；以及步骤340，由控制模块140基于相位指示信号来控制相位调谐模块130的运行时钟，或者更具体而言，控制相位调谐模块130的运行时钟的频率，以及分频器110的分频比中的至少一个。也就是说，在步骤340，控制模块140可以基于相位指示信号来控制相位调谐模块130的运行时钟(例如在图2所示的相位追踪电路100a中执行)，基于相位指示信号来控制分频器110的分频比(例如在图3所示的相位追踪电路100b中执行)，或者基于相位指示信号来控制相位调谐模块130的运行时钟和分频器110的分频比二者(例如在图4所示的相位追踪电路100c中执行)。
图10示出根据本发明一实施例的第一时钟信号的相位调整过程的流程图，其可应用于图9所示的方法300的步骤330中。参照图10，在步骤332，可以利用数字环路滤波器132基于相位指示信号来生成第一时钟选择信号。在步骤334，可以利用第一时钟选择单元134基于第一时钟选择信号从多相时钟信号中选择一个时钟信号，作为提供给分频器110的第一时钟信号。
图11示出根据本发明一实施例的基于相位指示信号来调整相位调谐模块130的运行时钟和/或分频器110的分频比的过程的流程图，其可应用于图9所示的方法300的步骤340中。参照图11，在步骤342，利用动态检测调整单元142检测鉴相器120生成的相位指示信号，以生成第二时钟选择信号和/或分频比调整信号。注意，可以基于相位指示信号，在不同的时间或者不同的情况下生成第二时钟选择信号和分频比调整信号。在步骤344，可以利用第二时钟选择单元144基于第二时钟选择信号从多个第二时钟信号中选择一个作为相位调谐模块130中的数字环路滤波器132的运行时钟。所述多个 第二时钟信号可包括分频器110提供的一个或多个分频信号，或者还可以包括第一时钟选择单元134提供的第一时钟信号。在步骤346，可以利用分频比控制单元146基于分频比调整信号来控制分频器110的分频比。
图12示出根据本发明一实施例的生成第二时钟选择信号和/或分频比调整信号的过程的流程图，其可应用于图11所示的步骤342中。参照图12，在步骤401，动态检测调整单元142可以基于检测鉴相器120生成的相位指示信号确定载波信号的相位是否在比参考时钟信号的相位更超前和更滞后之间跳变并且跳变达到预定次数。如果是，则在步骤403，动态检测调整单元142可以生成用于降低第二时钟选择单元144选择的第二时钟信号的频率的第二时钟选择信号，和/或用于降低分频器110的分频档位的分频比控制信号。可以重复执行步骤401和403，直到第二时钟选择单元144选择最低/基础频率的时钟信号，和/或分频器110的分频档位达到基础档位。
如果在步骤401确定没有发生上述跳变或者跳变未达到预定次数，则在步骤405中动态检测调整单元142可以基于检测鉴相器120生成的相位指示信号确定载波信号的相位是否比参考时钟信号的相位更超前或者更滞后并且持续预定周期。如果是，则可以在步骤407中，动态检测调整单元142可以生成用于提高第二时钟选择单元144选择的时钟信号频率的第二时钟选择信号，和/或用于提高分频器110的分频档位的分频比控制信号。可以重复执行步骤405和407，直到第二时钟选择单元144选择最高频率的时钟信号，和/或分频器110的分频档位达到最高档位。
图13示出根据本发明一实施例的生成第一时钟选择信号的过程的流程图，其可应用于图10所示的步骤332中。参照图13，在步骤512，可以利用比例路径210生成与鉴相器120提供的相位指示信号成第一比例的第一比例信号；在步骤514，可以利用积分路径220生成与相位指示信号成第二比例的第二比例信号。
可选地，在步骤516中，可以由第一比例调节单元214对第一比例或者说第一比例信号进行调整；在步骤518中，可以由第二比例调节单元224对第二比例或者说第二比例信号进行调整。在一实施例中，在步骤516和步骤518中可以使用相同的调节系数对第一比例和第二比例进行等比调整。如前所述，可以利用系数控制单元136基于动态检测调整单元142生成的系数调整信号来控制对第一比例和/或第二比例进行调整的调整系数。例如，当相位 指示信号指示载波信号的相位比参考时钟信号的相位更超前或者更滞后并且持续预定周期时，动态检测调整单元142生成的系数调整信号可以指示系数控制单元136提高调整系数以增大第一比例和/或第二比例，当多次检测到这样的持续周期时可以重复执行该步骤，直到达到最大比例。当相位指示信号指示载波信号的相位在比参考时钟信号的相位更超前和更滞后之间跳变并且所述跳变达到预定次数时，动态检测调整单元142生成的系数调整信号可以指示系数控制单元136降低调整系数以减小第一比例和/或第二比例，同样可以重复执行该步骤直到达到最小/基础比例。
继续参照图13，在步骤520，可以利用积分路径220中的积分器226来对第二比例信号进行积分处理，以获得积分信号。如前所述，可以使用第二时钟选择单元144选择的第二时钟信号作为积分器226的运行时钟，以控制积分处理的速度。然后在步骤522，可以利用加法器232对第一比例信号和积分信号进行加法运算，以获得二者的和值。在步骤524，可以利用取余单元234将所述和值关于预定值进行取余运算，以生成第一时钟选择信号。所述预定值可以等于第一时钟选择单元134要选择的具有不同相位的时钟信号的个数。
图14示出根据本发明一实施例的对数字环路滤波器132进行系数调整和运行时钟频率调整的流程图，其可以由例如图2所示的相位追踪电路100a执行。参照图14，在步骤601，可以基于相位指示信号确定载波信号的相位是否在比参考时钟信号的相位更超前和更滞后之间跳变并且跳变达到预定次数。如果没有发生跳变或者跳变没有达到预定次数，则在步骤603确定载波信号的相位是否比参考时钟信号的相位更超前或者更滞后并且持续预定周期。如果没有检测到载波信号的相位比参考时钟信号的相位更超前或者更滞后达到预定周期，则可以在步骤629，保持数字环路滤波器132的比例系数和运行时钟不变，然后返回到步骤601。
如果在步骤603确定载波信号的相位比参考时钟信号的相位更超前或者更滞后达到预定周期，则可以在步骤605中确定数字环路滤波器132的待调整的比例系数(第一比例系数a和/或第二比例系数p)是否达到最大值。如果尚未达到最大值，则可以在步骤607提高数字环路滤波器132的要调整的比例系数，然后返回到步骤601。
如果在步骤605确定数字环路滤波器132的要调整的比例系数已经达到 最大值，则可以在步骤609确定数字环路滤波器132的运行时钟频率，或者更准确地说，数字环路滤波器132的积分路径中的积分器的运行时钟频率，也就是第二时钟选择单元144选择的第二时钟信号的频率，是否达到了最大值。如果尚未达到最大频率，则可以在步骤611提高数字环路滤波器132的运行时钟频率，也就是第二时钟选择单元144选择的第二时钟信号的频率，然后返回步骤601。如果第二时钟信号的频率已经达到了最大值，则可以在步骤629，保持数字环路滤波器132的比例系数和运行时钟不变，然后返回到步骤601。
另一方面，如果在步骤601确定载波信号的相位在比参考时钟信号的相位更超前和更滞后之间跳变并且跳变达到预定次数，则可以在步骤621确定数字环路滤波器132的运行时钟频率，也就是第二时钟选择单元144选择的第二时钟信号的频率，是否为最低频率。如果不是最低频率，则可以在步骤632降低数字环路滤波器132的运行时钟频率，然后返回到步骤601。
如果在步骤621确定数字环路滤波器132的运行时钟频率是最低频率，则可以在步骤625确定数字环路滤波器132的待调整的比例系数(第一比例系数a和/或第二比例系数p)是否为最小值。如果不是最小值，则可以在步骤627降低数字环路滤波器132的待调整的比例系数，然后返回到步骤601。如果数字环路滤波器132的待调整的比例系数已经是最小值，则可以在步骤629保持数字环路滤波器的比例系数和运行时钟不变，然后返回到步骤601。
利用图14所示的过程，能够在大的相差范围内实现快速并且高精度的相位锁定，并且具有改善的相位噪声性能。例如，以分频比N＝64和多相时钟信号存在30°相差(M＝12)为例，传统的相位调整步进为0.46875°，如果载波信号和参考时钟信号之间存在180°的相位差，则相位锁定时间一般在100μs左右。如果载波信号和参考时钟信号之间存在一定的频率偏差，则相位锁定时间在100μs以上。利用本发明的动态检测调整技术，可以在相位追踪的初始阶段，通过提高数字环路滤波器132中的比例系数和积分频率，大幅加快锁定时间。而在接近锁定时，可以降低数字环路滤波器132中的比例系数和积分频率，直至最小系数和最低频率，使得锁定更稳定。整体锁定时间可以缩短至3μs至6μs左右。
图15示出根据本发明一实施例对数字环路滤波器132进行系数调整并且对分频器110进行分频档位调整的流程图，其可以由例如图3所示的相位 追踪电路100b执行。参照图15，在步骤601，可以基于相位指示信号确定载波信号的相位是否在比参考时钟信号的相位更超前和更滞后之间跳变并且跳变达到预定次数。如果没有发生跳变或者跳变没有达到预定次数，则在步骤603确定载波信号的相位是否比参考时钟信号的相位更超前或者更滞后并且持续预定周期。如果没有检测到载波信号的相位比参考时钟信号的相位更超前或者更滞后达到预定周期，则可以在步骤629，保持数字环路滤波器132的比例系数以及分频器110的分频档位不变，然后返回到步骤601。
如果在步骤603确定载波信号的相位比参考时钟信号的相位更超前或者更滞后达到预定周期，则可以在步骤605确定数字环路滤波器132的待调整的比例系数(第一比例系数和/或第二比例系数)是否达到最大值。如果尚未达到最大值，则可以在步骤607提高数字环路滤波器132的待调整的比例系数，然后返回到步骤601。
如果在步骤605确定数字环路滤波器132的要调整的比例系数已经达到最大值，则可以在步骤613确定分频器110的分频档位是否达到了最大档位。如果尚未达到最大档位，则可以在步骤615提高分频器110的分频档位，然后返回步骤601。如果分频器110的分频档位已经达到了最大档位，则可以在步骤629，保持数字环路滤波器132的比例系数以及分频器110的分频档位不变，然后返回到步骤601。
另一方面，如果在步骤601确定载波信号的相位在比参考时钟信号的相位更超前和更滞后之间跳变并且跳变达到预定次数，则可以在步骤617确定分频器110的分频档位是否在最低/基础档位。如果分频器110的分频档位不是最低档位，则可以在步骤619降低分频器110的分频档位，然后返回到步骤601。
如果在步骤617确定分频器110的分频档位是在最低档位，则可以在步骤625确定数字环路滤波器110的待调整的比例系数(第一比例系数和/或第二比例系数)是否为最小值。如果不是最小值，则可以在步骤627降低数字环路滤波器132的待调整的比例系数，然后返回到步骤601。如果数字环路滤波器132的待调整的比例系数已经是最小值，则可以在步骤629保持数字环路滤波器132的比例系数以及分频器110的分频档位不变，然后返回到步骤601。
利用图15所示的过程，能够在大的相差范围内实现快速并且高精度的 相位锁定，并且具有改善的相位噪声性能。例如，以分频比N＝64和多相时钟信号存在30°相差(M＝12)为例，传统的相位调整步进为0.46875°，如果载波信号和参考时钟信号之间存在180°的相位差，则相位锁定时间一般在100μs左右。如果载波信号和参考时钟信号之间存在一定的频率偏差，则相位锁定时间在100μs以上。利用本发明的动态检测调整技术，可以在相位追踪的初始阶段启动分频比动态调整，根据分频比调整档位数十倍地提升相位调整步进，大幅加快锁定时间。而在接近锁定时降低分频比调整档位，直至停用，将步进恢复至0.46875°，从而不损失相位调整精度。整体稳定时间可以缩短至10us以内。
图16示出根据本发明一实施例的对数字环路滤波器132进行系数调整和运行时钟频率调整以及对分频器110进行分频比调整的流程图，其可以由例如图4所示的相位追踪电路100c执行。参照图16，在步骤601，可以基于相位指示信号确定载波信号的相位是否在比参考时钟信号的相位更超前和更滞后之间跳变并且跳变达到预定次数。如果没有发生跳变或者跳变没有达到预定次数，则在步骤603确定载波信号的相位是否比参考时钟信号的相位更超前或者更滞后并且持续预定周期。如果没有检测到载波信号的相位比参考时钟信号的相位更超前或者更滞后达到预定周期，则可以在步骤629，保持数字环路滤波器132的比例系数和运行时钟以及分频器110的分频比/分频档位不变，然后返回到步骤601。
如果在步骤603确定载波信号的相位比参考时钟信号的相位更超前或者更滞后并且持续达到预定周期，则可以在步骤605中确定数字环路滤波器132的待调整的比例系数(第一比例系数a和/或第二比例系数p)是否达到最大值。如果尚未达到最大值，则可以在步骤607提高数字环路滤波器132的待调整的比例系数，然后返回到步骤601。
如果在步骤605确定数字环路滤波器132的要调整的比例系数已经达到最大值，则可以在步骤609确定数字环路滤波器132的运行时钟频率，或者更准确地说，数字环路滤波器132的积分路径中的积分器的运行时钟频率，也就是第二时钟选择单元144选择的第二时钟信号的频率，是否达到了最大值。如果尚未达到最大频率，则可以在步骤611提高数字环路滤波器132的运行时钟频率，也就是第二时钟选择单元144选择的第二时钟信号的频率，然后返回步骤601。
如果在步骤609中确定第二时钟信号的频率已经达到了最大值，则可以在步骤613中，确定分频器110的分频档位是否已经达到了最高档位。如果尚未达到最高档位，则可以在步骤615中提高分频器110的分频档位，然后返回步骤601。如果已经达到了最高档位，则可以在步骤629中保持数字环路滤波器132的比例系数和运行时钟以及分频器110的分频比/分频档位不变，然后返回到步骤601。
另一方面，如果在步骤601确定载波信号的相位在比参考时钟信号的相位更超前和更滞后之间跳变并且跳变达到预定次数，则可以在步骤617中确定分频器110的分频档位是否为最低/基础档位。如果不是最低档位，则可以在步骤619中降低分频器110的分频档位，然后返回到步骤601。
如果在步骤617中确定分频器110的分频档位在最低档位，则可以在步骤621中确定数字环路滤波器132的运行时钟频率，也就是第二时钟选择单元144选择的第二时钟信号的频率，是否为最低频率。如果不是最低频率，则可以在步骤623中降低数字环路滤波器132的运行时钟频率，然后返回到步骤601。
如果在步骤621中确定数字环路滤波器132的运行时钟频率是最低频率，则可以在步骤625确定数字环路滤波器132的待调整的比例系数(第一比例系数a和/或第二比例系数p)是否为最小值。如果不是最小值，则可以在步骤627降低数字环路滤波器132的待调整的比例系数，然后返回到步骤601。如果数字环路滤波器132的待调整的比例系数已经是最小值，则可以在步骤629保持数字环路滤波器132的比例系数和运行时钟以及分频器110的分频比/分频档位不变，然后返回到步骤601。
图17示出根据本发明另一实施例的对数字环路滤波器132进行系数调整和运行时钟频率调整以及对分频器110进行分频比调整的流程图，其可以由例如图4所示的相位追踪电路100c执行。图17所示的流程包括许多与图16所示的流程相同的步骤，下面将省略对其的重复描述，而仅描述不同的步骤。
参照图17，当在步骤605中确定数字环路滤波器132的比例系数已经达到最大值时，在步骤608中确定是否分频器110的分频档位处于最低/基础档位并且数字环路滤波器132中的积分器226的运行时钟，也就是第二时钟选择单元144选择的第二时钟信号，处于非最高频率。如果是，则在步骤611 中提高数字环路滤波器132中的积分器226的运行时钟频率，然后返回到步骤601。如果不是，则流程进展到步骤613。
当在步骤613中确定分频器110的分频档位未达到最高档位时，可以在步骤614中提高分频器110的分频档位，并且在首次提高分频器110的分频档位时，也就是在将分频档位从基础档位提升到档位1时，还将数字环路滤波器132中的积分器226的运行时钟，也就是第二时钟选择单元144选择的第二时钟信号，置于最低频率，以在分频比调整期间节省数字环路滤波器132的功耗。
另一方面，当在步骤601中确定跳变达到预定次数并且在步骤617中确定分频器110的分频档位不是基础/最低档位时，在步骤618中，可以降低分频器110的分频档位，并且当分频器110的分频档位被降低到基础/最低档位时，还将数字环路滤波器132中的积分器226的运行时钟，也就是第二时钟选择单元144选择的第二时钟信号，置于最高频率。后面的步骤都与图16所示的流程相同，这里不再重复描述。
通过比较图16和图17所示的流程可以理解，其不同之处主要在于，在图17所示的流程中，当应用分频比调节时，数字环路滤波器132中的积分器226的运行时钟频率都被置于最低频率。这样，图17所示的流程与图16所示的流程相比能够节省数字环路滤波器132的功耗。
利用图16和图17所示的过程，能够在大的相差范围内实现快速并且高精度的相位锁定，并且具有改善的相位噪声性能，还可以具有节省的功耗。例如，以分频比N＝64和多相时钟信号存在30°相差(M＝12)为例，传统的相位调整步进为0.46875°，如果载波信号和参考时钟信号之间存在180°的相位差，则相位锁定时间一般在100μs左右。如果载波信号和参考时钟信号之间存在一定的频率偏差，则相位锁定时间在100μs以上。利用本发明的动态检测调整技术，可以在相位追踪的初始阶段，通过提高数字环路滤波器中的比例系数和积分频率，大幅加快锁定时间。而在接近锁定时，可以降低数字环路滤波器中的比例系数和积分频率，直至最小系数和最低频率，使得锁定更稳定。整体锁定和稳定时间可以达到10μs以内。
图18示出根据本发明一实施例的电子设备700的示意图。电子设备700可以包括根据本发明一实施例的相位追踪电路720。例如，电子设备700可以具有NFC模块710，其可以工作在卡模拟模式下。NFC模块710可以包 括相位追踪电路720，以追踪NFC读卡器的信号相位。这样的电子设备700的示例包括但不限于手机、平板、便携式个人数字助理、可穿戴电子设备等。
以上结合具体实施例描述了本申请的基本原理，但是，需要指出的是，在本申请中提及的优点、优势、效果等仅是示例而非限制，不能认为这些优点、优势、效果等是本申请的各个实施例必须具备的。另外，上述公开的具体细节仅是为了示例的作用和便于理解的作用，而非限制，上述细节并不限制本申请为必须采用上述具体的细节来实现。
本申请中涉及的器件、装置、设备、系统的方框图仅作为例示性的例子并且不意图要求或暗示必须按照方框图示出的方式进行连接、布置、配置。如本领域技术人员将认识到的，可以按任意方式连接、布置、配置这些器件、装置、设备、系统。诸如“包括”、“包含”、“具有”等等的词语是开放性词汇，指“包括但不限于”，且可与其互换使用。这里所使用的词汇“或”和“和”指词汇“和/或”，且可与其互换使用，除非上下文明确指示不是如此。这里所使用的词汇“诸如”指词组“诸如但不限于”，且可与其互换使用。
还需要指出的是，在本申请的装置、设备和方法中，各部件或各步骤是可以分解和/或重新组合的。这些分解和/或重新组合应视为本申请的等效方案。
提供所公开的方面的以上描述以使本领域的任何技术人员能够做出或者使用本申请。对这些方面的各种修改对于本领域技术人员而言是非常显而易见的，并且在此定义的一般原理可以应用于其他方面而不脱离本申请的范围。因此，本申请不意图被限制到在此示出的方面，而是按照与在此公开的原理和新颖的特征一致的最宽范围。
为了例示和描述的目的已经给出了以上描述。此外，此描述不意图将本申请的实施例限制到在此公开的形式。尽管以上已经讨论了多个示例方面和实施例，但是本领域技术人员将认识到其某些变型、修改、改变、添加和子组合。

Claims (32)

  1. 一种相位追踪电路，包括：
    分频器，用于对第一时钟信号进行分频处理以获得载波信号；
    鉴相器，用于比较所述载波信号和参考时钟信号的相位，以生成相位指示信号；
    相位调谐模块，用于基于所述相位指示信号来调整所述第一时钟信号的相位，以使得所述载波信号的相位更接近于所述参考时钟信号的相位；以及
    控制模块，用于基于所述相位指示信号来控制所述相位调谐模块的运行时钟和所述分频器的分频比中的至少一个，以控制所述相位调谐模块的相位调整速度。
  2. 如权利要求1所述的相位追踪电路，其中，所述鉴相器是二进制鉴相器，所述二进制鉴相器输出的相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位超前或者滞后。
  3. 如权利要求1所述的相位追踪电路，其中，所述相位调谐模块包括：
    数字环路滤波器，用于基于所述相位指示信号来生成第一时钟选择信号；以及
    第一时钟选择单元，用于基于所述第一时钟选择信号从多相时钟信号中选择一个时钟信号作为所述第一时钟信号。
  4. 如权利要求3所述的相位追踪电路，其中，所述控制模块包括第二时钟选择单元和分频比控制单元中的至少一个、以及动态检测调整单元，
    所述动态检测调整单元配置为检测所述鉴相器生成的相位指示信号，并且生成第二时钟选择信号和/或分频比调整信号，
    所述第二时钟选择单元配置为基于所述第二时钟选择信号从多个第二时钟信号中选择一个作为所述数字环路滤波器的运行时钟，
    所述分频比控制单元配置为基于所述分频比调整信号来控制所述分频器的分频比。
  5. 如权利要求4所述的相位追踪电路，其中，所述多个第二时钟信号包括所述分频器提供的一个或多个分频信号。
  6. 如权利要求5所述的相位追踪电路，其中，所述多个第二时钟信号还包括所述第一时钟选择单元提供的所述第一时钟信号。
  7. 如权利要求4所述的相位追踪电路，其中，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前或者更滞后并且持续预定周期时，所述动态检测调整单元生成的第二时钟选择信号指示所述第二时钟选择单元从所述多个第二时钟信号中选择一个比当前选择的时钟信号更高频率的时钟信号，所述动态检测调整单元生成的分频比调整信号指示所述分频比控制单元提高所述分频器的分频档位，
    当所述相位指示信号指示所述载波信号的相位在比所述参考时钟信号的相位更超前和更滞后之间跳变并且所述跳变达到预定次数时，所述动态检测调整单元生成的第二时钟选择信号指示所述第二时钟选择单元从所述多个第二时钟信号中选择一个比当前选择的时钟信号更低频率的分频信号，所述动态检测调整单元生成的分频比调整信号指示所述分频比控制单元降低所述分频器的分频档位，
    所述分频器具有基础档位以及至少一个更高档位，所述基础档位具有基础分频比N，所述更高档位具有更高分频比N+x或者更低分频比N-x，N为预设的正整数，x为比N更小的正整数并且档位越高，x的值越大，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前时，所述更高档位具有所述更高分频比N+x，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更滞后时，所述更高档位具有所述更低分频比N-x。
  8. 如权利要求7所述的相位追踪电路，其中，所述载波信号是所述分频器提供的多个分频信号中具有最低频率的分频信号，所述基础分频比N使得所述载波信号的频率等于所述参考时钟信号的频率。
  9. 如权利要求7所述的相位追踪电路，其中，所述多相时钟信号包括M 个不同相位的时钟信号，M是大于一的整数，
    所述数字环路滤波器生成的第一时钟选择信号表示M个索引值中的一个，以指示所述第一时钟选择单元从所述M个不同相位的时钟信号中选择一个对应的时钟信号作为所述第一时钟信号。
  10. 如权利要求7所述的相位追踪电路，其中，当所述鉴相器生成的相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位超前并且持续预定周期时，所述数字环路滤波器生成的第一时钟选择信号指示所述第一时钟选择单元从所述多相时钟信号中选择一个比当前选择的时钟信号相位更滞后的时钟信号，
    当所述鉴相器生成的相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位滞后并且持续预定周期时，所述数字环路滤波器生成的第一时钟选择信号指示所述第一时钟选择单元从所述多相时钟信号中选择一个比当前选择的时钟信号相位更超前的时钟信号。
  11. 如权利要求7所述的相位追踪电路，其中，所述数字环路滤波器包括：
    比例路径，用于生成与所述相位指示信号成第一比例的第一比例信号；
    积分路径，用于生成与所述相位指示信号成第二比例的第二比例信号，并且使用积分器对所述第二比例信号进行积分处理以生成积分信号；
    加法器，用于对所述第一比例信号和所述积分信号进行加法运算，以输出二者的和值；以及
    取余单元，用于对从所述加法器接收到的所述和值关于预定值进行取余运算，以生成表示余数的所述第一时钟选择信号。
  12. 如权利要求11所述的相位追踪电路，其中，所述第二时钟选择单元选择的第二时钟信号用作所述积分路径中的积分器的运行时钟，所述预定值等于所述多相时钟信号中包括的具有不同相位的时钟信号的个数。
  13. 如权利要求11所述的相位追踪电路，其中，所述数字环路滤波器还包括以下中的至少一个：
    设置在所述比例路径中的第一比例调节单元，用于调节所述第一比例；以及
    设置在所述积分路径中的第二比例调节单元，用于调节所述第二比例。
  14. 如权利要求13所述的相位追踪电路，其中，所述第一比例调节单元和所述第二比例调节单元使用相同的调节系数对所述第一比例和所述第二比例进行等比调节。
  15. 如权利要求13所述的相位追踪电路，还包括：
    系数控制单元，用于基于所述动态检测调整单元生成的系数调整信号来控制对所述第一比例和所述第二比例中的至少一个进行调节的调节系数，
    其中，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前或者更滞后并且持续预定周期时，所述动态检测调整单元生成的系数调整信号指示所述系数控制单元提高所述调节系数以增大所述第一比例和所述第二比例中的所述至少一个，
    当所述相位指示信号指示所述载波信号的相位在比所述参考时钟信号的相位更超前和更滞后之间跳变并且所述跳变达到预定次数时，所述动态检测调整单元生成的系数调整信号指示所述系数控制单元降低所述调节系数以减小所述第一比例和所述第二比例中的所述至少一个。
  16. 如权利要求15所述的相位追踪电路，其中，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前或者更滞后并且持续预定周期时，所述动态检测调整单元先生成所述系数调整信号以增大所述第一比例和所述第二比例中的所述至少一个，直到达到最大比例，然后生成所述第二时钟选择信号以提高所述第二时钟选择单元选择的第二时钟信号的频率，直到达到最高频率，然后生成所述分频比调整信号以提高所述分频器的分频档位，
    当所述相位指示信号指示所述载波信号的相位在比所述参考时钟信号的相位更超前和更滞后之间跳变并且所述跳变达到预定次数时，所述动态检测调整单元先生成所述分频比调整信号以降低所述分频器的分频档位，直到达到基础档位，然后生成所述第二时钟选择信号以降低所述第二时钟选择单 元选择的第二时钟信号的频率，直到达到最低频率，然后生成所述系数调整信号以减小所述第一比例和所述第二比例中的所述至少一个。
  17. 如权利要求15所述的相位追踪电路，其中，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前或者更滞后并且持续预定周期时，所述动态检测调整单元先生成所述系数调整信号以增大所述第一比例和所述第二比例中的所述至少一个，直到达到最大比例，然后生成所述第二时钟选择信号以提高所述第二时钟选择单元选择的第二时钟信号的频率，直到达到最高频率，然后生成最小第二时钟设置信号以将所述第二时钟选择单元选择的第二时钟信号的频率设置为最低频率，并且生成所述分频比调整信号以提高所述分频器的分频档位，
    当所述相位指示信号指示所述载波信号的相位在比所述参考时钟信号的相位更超前和更滞后之间跳变并且所述跳变达到预定次数时，所述动态检测调整单元先生成所述分频比调整信号以降低所述分频器的分频档位，直到达到基础档位，并且在所述分频档位达到基础档位时，生成最大第二时钟设置信号以将所述第二时钟选择单元选择的第二时钟信号的频率设置为最高频率，然后生成所述第二时钟选择信号以降低所述第二时钟选择单元选择的第二时钟信号的频率，直到达到最低频率，然后生成所述系数调整信号以减小所述第一比例和所述第二比例中的所述至少一个。
  18. 一种相位追踪方法，包括：
    分频器对第一时钟信号进行分频处理以获得载波信号；
    鉴相器比较所述载波信号和参考时钟信号的相位，以生成相位指示信号；
    相位调谐模块基于所述相位指示信号来调整所述第一时钟信号的相位，以使得所述载波信号的相位更接近于所述参考时钟信号的相位；以及
    控制模块基于所述相位指示信号控制所述相位调谐模块的运行时钟和所述分频器的分频比中的至少一个，以控制所述相位调谐模块的相位调整速度。
  19. 如权利要求18所述的方法，其中，相位调谐模块基于所述相位指示信号来调整所述第一时钟信号的相位包括：
    利用数字环路滤波器基于所述相位指示信号来生成第一时钟选择信号；以及
    利用第一时钟选择单元基于所述第一时钟选择信号从多相时钟信号中选择一个时钟信号作为所述第一时钟信号。
  20. 如权利要求19所述的方法，其中，所述控制模块包括第二时钟选择单元和分频比控制单元中的至少一个、以及动态检测调整单元，
    所述动态检测调整单元配置为检测所述鉴相器生成的相位指示信号，并且生成第二时钟选择信号和/或分频比调整信号，
    所述第二时钟选择单元配置为基于所述第二时钟选择信号从多个第二时钟信号中选择一个作为所述数字环路滤波器的运行时钟，
    所述分频比控制单元配置为基于所述分频比调整信号来控制所述分频器的分频比。
  21. 如权利要求20所述的方法，其中，所述多个第二时钟信号包括所述分频器提供的一个或多个分频信号。
  22. 如权利要求21所述的方法，其中，所述多个第二时钟信号还包括所述第一时钟选择单元提供的所述第一时钟信号。
  23. 如权利要求20所述的方法，其中，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前或者更滞后并且持续预定周期时，所述动态检测调整单元生成的第二时钟选择信号指示所述第二时钟选择单元从所述多个第二时钟信号中选择一个比当前选择的时钟信号更高频率的时钟信号，所述动态检测调整单元生成的分频比调整信号指示所述分频比控制单元提高所述分频器的分频档位，
    当所述相位指示信号指示所述载波信号的相位在比所述参考时钟信号的相位更超前和更滞后之间跳变并且所述跳变达到预定次数时，所述动态检测调整单元生成的第二时钟选择信号指示所述第二时钟选择单元从所述多个第二时钟信号中选择一个比当前选择的时钟信号更低频率的分频信号，所述动态检测调整单元生成的分频比调整信号指示所述分频比控制单元降低 所述分频器的分频档位，
    所述分频器具有基础档位以及至少一个更高档位，所述基础档位具有基础分频比N，所述更高档位具有更高分频比N+x或者更低分频比N-x，N为预设的正整数，x为比N更小的正整数并且档位越高，x的值越大，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前时，所述更高档位具有所述更高分频比N+x，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更滞后时，所述更高档位具有所述更低分频比N-x。
  24. 如权利要求23所述的方法，其中，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位超前并且持续预定周期时，所述数字环路滤波器生成的第一时钟选择信号指示所述第一时钟选择单元从所述多相时钟信号中选择一个比当前选择的时钟信号相位更滞后的时钟信号，
    当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位滞后并且持续预定周期时，所述数字环路滤波器生成的第一时钟选择信号指示所述第一时钟选择单元从所述多相时钟信号中选择一个比当前选择的时钟信号相位更超前的时钟信号。
  25. 如权利要求23所述的方法，其中，利用数字环路滤波器基于所述相位指示信号来生成第一时钟选择信号包括：
    利用比例路径生成与所述相位指示信号成第一比例的第一比例信号；
    利用积分路径生成与所述相位指示信号成第二比例的第二比例信号，并且使用设置在所述积分路径中的积分器对所述第二比例信号进行积分处理以生成积分信号；
    利用加法器对所述第一比例信号和所述积分信号进行加法运算，以输出二者的和值；以及
    利用取余单元对所述和值关于预定值进行取余运算，以生成表示余数的所述第一时钟选择信号。
  26. 如权利要求25所述的方法，其中，所述第二时钟选择单元选择的第二时钟信号用作所述积分路径中的积分器的运行时钟以控制对所述第二比 例信号进行积分的速度，所述预定值等于所述多相时钟信号中包括的具有不同相位的时钟信号的个数。
  27. 如权利要求25所述的方法，其中，利用数字环路滤波器基于所述相位指示信号来生成第一时钟选择信号还包括以下步骤中的至少一个：
    利用设置在所述比例路径中的第一比例调节单元调节所述第一比例；以及
    利用设置在所述积分路径中的第二比例调节单元调节所述第二比例。
  28. 如权利要求27所述的方法，其中，所述第一比例调节单元和所述第二比例调节单元使用相同的调节系数对所述第一比例和所述第二比例进行等比调节。
  29. 如权利要求27所述的方法，还包括：
    利用系数控制单元基于所述动态检测调整单元生成的系数调整信号来控制对所述第一比例和所述第二比例中的至少一个进行调节的调节系数，
    其中，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前或者更滞后并且持续预定周期时，所述动态检测调整单元生成的系数调整信号指示所述系数控制单元提高所述调节系数以增大所述第一比例和所述第二比例中的所述至少一个，
    当所述相位指示信号指示所述载波信号的相位在比所述参考时钟信号的相位更超前和更滞后之间跳变并且所述跳变达到预定次数时，所述动态检测调整单元生成的系数调整信号指示所述系数控制单元降低所述调节系数以减小所述第一比例和所述第二比例中的所述至少一个。
  30. 如权利要求29所述的方法，其中，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前或者更滞后并且持续预定周期时，所述动态检测调整单元先生成所述系数调整信号以增大所述第一比例和所述第二比例中的所述至少一个，直到达到最大比例，然后生成所述第二时钟选择信号以提高所述第二时钟选择单元选择的第二时钟信号的频率，直到达到最高频率，然后生成所述分频比调整信号以提高所述分频器的分频 档位，
    当所述相位指示信号指示所述载波信号的相位在比所述参考时钟信号的相位更超前和更滞后之间跳变并且所述跳变达到预定次数时，所述动态检测调整单元先生成所述分频比调整信号以降低所述分频器的分频档位，直到达到基础档位，然后生成所述第二时钟选择信号以降低所述第二时钟选择单元选择的第二时钟信号的频率，直到达到最低频率，然后生成所述系数调整信号以减小所述第一比例和所述第二比例中的所述至少一个。
  31. 如权利要求29所述的方法，其中，当所述相位指示信号指示所述载波信号的相位比所述参考时钟信号的相位更超前或者更滞后并且持续预定周期时，所述动态检测调整单元先生成所述系数调整信号以增大所述第一比例和所述第二比例中的所述至少一个，直到达到最大比例，然后生成所述第二时钟选择信号以提高所述第二时钟选择单元选择的第二时钟信号的频率，直到达到最高频率，然后生成最小第二时钟设置信号以将所述第二时钟选择单元选择的第二时钟信号的频率设置为最低频率，并且生成所述分频比调整信号以提高所述分频器的分频档位，
    当所述相位指示信号指示所述载波信号的相位在比所述参考时钟信号的相位更超前和更滞后之间跳变并且所述跳变达到预定次数时，所述动态检测调整单元先生成所述分频比调整信号以降低所述分频器的分频档位，直到达到基础档位，并且在所述分频档位达到基础档位时，生成最大第二时钟设置信号以将所述第二时钟选择单元选择的第二时钟信号的频率设置为最高频率，然后生成所述第二时钟选择信号以降低所述第二时钟选择单元选择的第二时钟信号的频率，直到达到最低频率，然后生成所述系数调整信号以减小所述第一比例和所述第二比例中的所述至少一个。
  32. 一种电子设备，包括权利要求1-17中的任一项所述的相位追踪电路。
PCT/CN2023/089748 2022-09-16 2023-04-21 相位追踪电路和方法及电子设备 WO2024055589A1 (zh)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
CN202211129272.2A CN115441866B (zh) 2022-09-16 2022-09-16 基于分频加速的相位追踪环路和方法及电子设备
CN202211129272.2 2022-09-16
CN202211129085.4A CN115498999B (zh) 2022-09-16 2022-09-16 基于分频和时钟加速的相位追踪环路和方法及电子设备
CN202211129145.2A CN115483928B (zh) 2022-09-16 2022-09-16 基于时钟加速的相位追踪环路和方法及电子设备
CN202211129145.2 2022-09-16
CN202211129085.4 2022-09-16

Publications (1)

Publication Number Publication Date
WO2024055589A1 true WO2024055589A1 (zh) 2024-03-21

Family

ID=90274213

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/089748 WO2024055589A1 (zh) 2022-09-16 2023-04-21 相位追踪电路和方法及电子设备

Country Status (1)

Country Link
WO (1) WO2024055589A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103297046A (zh) * 2013-05-09 2013-09-11 英特格灵芯片(天津)有限公司 一种锁相环及其时钟产生方法和电路
CN111953340A (zh) * 2019-05-15 2020-11-17 博通集成电路（上海）股份有限公司 频率合成器及其操作方法
US20220173740A1 (en) * 2019-02-27 2022-06-02 Semiblocks B.V. Generator and method for generating a controlled frequency
CN115441866A (zh) * 2022-09-16 2022-12-06 武汉市聚芯微电子有限责任公司 基于分频加速的相位追踪环路和方法及电子设备
CN115483928A (zh) * 2022-09-16 2022-12-16 武汉市聚芯微电子有限责任公司 基于时钟加速的相位追踪环路和方法及电子设备
CN115498999A (zh) * 2022-09-16 2022-12-20 武汉市聚芯微电子有限责任公司 基于分频和时钟加速的相位追踪环路和方法及电子设备

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103297046A (zh) * 2013-05-09 2013-09-11 英特格灵芯片(天津)有限公司 一种锁相环及其时钟产生方法和电路
US20220173740A1 (en) * 2019-02-27 2022-06-02 Semiblocks B.V. Generator and method for generating a controlled frequency
CN111953340A (zh) * 2019-05-15 2020-11-17 博通集成电路（上海）股份有限公司 频率合成器及其操作方法
CN115441866A (zh) * 2022-09-16 2022-12-06 武汉市聚芯微电子有限责任公司 基于分频加速的相位追踪环路和方法及电子设备
CN115483928A (zh) * 2022-09-16 2022-12-16 武汉市聚芯微电子有限责任公司 基于时钟加速的相位追踪环路和方法及电子设备
CN115498999A (zh) * 2022-09-16 2022-12-20 武汉市聚芯微电子有限责任公司 基于分频和时钟加速的相位追踪环路和方法及电子设备

Similar Documents

Publication Publication Date Title
CN101227189B (zh) 频率合成器、自动频率校正电路及频率校正方法
US20080284531A1 (en) Fractional-n synthesized chirp generator
JP3098027B2 (ja) 位相ロック回路及び該位相ロック回路より成る周波数逓倍器
EP2761787B1 (en) Apparatus and method for performing spread-spectrum clock control
CN104104385A (zh) 一种高精度锁相环和锁相方法
CN115498999B (zh) 基于分频和时钟加速的相位追踪环路和方法及电子设备
CN115483928B (zh) 基于时钟加速的相位追踪环路和方法及电子设备
CN115441866B (zh) 基于分频加速的相位追踪环路和方法及电子设备
US8629728B2 (en) VCO control circuit and method thereof, fast locking PLL and method for fast locking PLL
JP2002290233A (ja) Ｐｌｌ回路のモード切替方法及びｐｌｌ回路のモード制御回路
US11303284B1 (en) Low-power fractional analog PLL without feedback divider
JPH09321617A (ja) Ｐｌｌ周波数シンセサイザ
CN101421930A (zh) 配置锁相环电路的方法以及系统
US20170373694A1 (en) Frequency based bias voltage scaling for phase locked loops
EP1916768A1 (en) Device and method for generating a signal with predefined transient at start-up
WO2024055589A1 (zh) 相位追踪电路和方法及电子设备
US10218367B2 (en) Frequency synthesizing device and automatic calibration method thereof
CN110995256B (zh) 一种减少频率锁定时间的锁相环装置及实现方法
KR20070055011A (ko) 전압 제어 발진기의 주파수 대역을 안정적으로 조정하는위상 동기 루프 및 방법
JP2003101410A (ja) 周波数シンセサイザのサイクル・スリップを低減する方法および装置
CN113114237A (zh) 一种能够实现快速频率锁定的环路系统
JPH0758636A (ja) 周波数シンセサイザ
CN116938233B (zh) 锁相环的时钟中心扩频方法和装置
WO2011156622A1 (en) Methods and apparatus for a gray-coded phase rotating frequency divider
CN110061738B (zh) 一种全数字锁相环电路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23864330

Country of ref document: EP

Kind code of ref document: A1