WO2024055409A1 - 存储器及其制造方法、电子设备 - Google Patents

存储器及其制造方法、电子设备 Download PDF

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Publication number
WO2024055409A1
WO2024055409A1 PCT/CN2022/132178 CN2022132178W WO2024055409A1 WO 2024055409 A1 WO2024055409 A1 WO 2024055409A1 CN 2022132178 W CN2022132178 W CN 2022132178W WO 2024055409 A1 WO2024055409 A1 WO 2024055409A1
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Prior art keywords
gate
channel
signal line
substrate
memory
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PCT/CN2022/132178
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English (en)
French (fr)
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戴瑾
朱正勇
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北京超弦存储器研究院
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Publication of WO2024055409A1 publication Critical patent/WO2024055409A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a memory, a manufacturing method thereof, and electronic equipment.
  • NAND flash memory flash memory for short
  • flash memory flash memory for short
  • flash memory can adopt a three-dimensional structure to have higher storage density and lower cost, and has become one of the important development trends in the field of storage technology.
  • a memory, a manufacturing method thereof, and an electronic device are provided.
  • one aspect of the present disclosure provides a memory, including: a substrate and a plurality of memory cells disposed on the substrate, a first read signal line, a second read signal line, a first write signal line and the second write signal line.
  • the memory unit includes: a first transistor and a second transistor located on a side of the first transistor away from the substrate.
  • the first transistor includes: a first gate, a first channel and a storage gate.
  • the first gate is disposed on the substrate and connected to the first read signal line.
  • the first channel is located on a side of the first gate facing away from the substrate and is connected to the second read signal line.
  • the storage gate is located on a side of the first channel away from the first gate.
  • the second transistor includes: a second channel and a second gate.
  • the second channel is located on the surface of the storage gate facing away from the substrate, and is connected to the storage gate and the second writing signal line respectively.
  • the second gate is connected to the first writing signal line.
  • At least one of the second gate and the second channel has a surrounding structure; the second gate surrounds the second channel, or the second channel surrounds the second gate.
  • two ends of the second channel along the direction vertical to the substrate are respectively connected to the storage gate and the second write signal line.
  • the second gate is disposed around the sidewall of the second channel.
  • the geometric center of the orthographic projection of the second channel on the substrate coincides or approximately coincides with the geometric center of the orthographic projection of the storage gate on the substrate.
  • the outer contour of the second channel's orthographic projection on the substrate coincides with or has an interval between the outer contour of the storage gate's orthographic projection on the substrate, and the interval is less than or equal to the first threshold.
  • the second gate is located on a side of the second channel facing away from the storage gate.
  • the second channel surrounds at least part of the sidewall of the second gate.
  • the second gate is also located on a side of the second write signal line facing away from the substrate.
  • the second write signal line is connected to the second read signal line.
  • the number of storage units is multiple. Multiple memory cells are stacked in a direction perpendicular to the substrate to form different layers. A plurality of memory cells located on the same layer are arranged in rows along the first direction and in columns along the second direction, where the first direction and the second direction are parallel to the substrate and intersect. The first read signal line and the first write signal line extend along the first direction, and the second read signal line and the second write signal line extend along the second direction.
  • the first channels in any column of memory cells are distributed in series, and the first channels of each memory cell are connected in sequence to form an integrated structure.
  • multiple columns of memory cells are correspondingly distributed with multiple semiconductor traces; wherein the first channel is a portion of the semiconductor trace located in the channel region, and the second read signal connected to the first channel The line includes the portion of the semiconductor trace located in the connection area.
  • the second read signal line further includes: a metal trace stacked on one side of the semiconductor trace and located in the connection area.
  • the memory further includes: a first insulating layer between the first channel and the first gate, and a second insulating layer between the first channel and the storage gate.
  • the material of the first channel includes polysilicon or a metal oxide semiconductor.
  • the material of the second channel includes a metal oxide semiconductor.
  • multiple rows of memory cells are correspondingly distributed with multiple first metal lines and multiple second metal lines.
  • the first gate electrode and the connected first read signal line are respectively parts of the same first metal line located in different areas.
  • the second gate electrode and the connected first writing signal line are respectively parts of the same second metal line located in different areas.
  • another aspect of the present disclosure provides a memory manufacturing method for manufacturing the memory as described in some of the above embodiments.
  • the manufacturing method includes the following steps:
  • a first gate electrode and a first read signal line connected to the first gate electrode are formed on the substrate.
  • a first channel and a second read signal line connected to the first channel are formed on a side of the first gate facing away from the substrate.
  • a storage gate is formed on a side of the first channel away from the first gate.
  • a second channel and a second gate are respectively formed on a side of the storage gate away from the substrate, as well as a first write signal line connected to the second gate, and a second write signal line connected to the second channel. signal line; wherein the second channel is connected to the storage gate, and at least one of the second gate and the second channel has a surrounding structure; the second gate surrounds the second channel, or the second channel surrounds Second gate.
  • the first gate, the first channel and the storage gate together constitute the first transistor; the second channel and the second gate together constitute the second transistor; the first transistor and the second transistor together constitute the memory unit.
  • forming a first gate on a substrate and a first read signal line connected to the first gate includes the following steps.
  • a first trench extending along a first direction is formed in the substrate.
  • forming a first channel and a second read signal line connected to the first channel on a side of the first gate away from the substrate includes the following steps.
  • Metal traces are formed, and the metal traces are located between adjacent first gate electrodes arranged in the column direction and are insulated from the first gate electrodes.
  • a semiconductor layer is formed on a surface of the metal trace facing away from the substrate and a side of the first gate facing away from the substrate.
  • the semiconductor layer is patterned to form semiconductor traces.
  • the portion of the semiconductor trace located in the channel region forms the first channel.
  • the portion of the semiconductor trace covering the metal trace together with the metal trace constitute a second read signal line.
  • the manufacturing method before forming the first channel and the second read signal line connected to the first channel on the side of the first gate away from the substrate, the manufacturing method further includes: forming a layer covering the first channel. A first insulating layer for the gate.
  • the manufacturing method further includes: forming a second insulating layer covering the first channel and the second read signal line.
  • the storage gate is formed on a surface of the second insulating layer facing away from the first channel.
  • a second channel and a second gate are respectively formed on a side of the storage gate away from the substrate, and a first write signal line connected to the second gate, and the second channel Connecting the second write signal line includes the following steps.
  • a first dielectric layer covering the storage gate is formed.
  • a second dielectric layer covering the conductive initial structure and the first dielectric layer is formed.
  • a channel hole is formed in the second dielectric layer, the conductive initial structure and the first dielectric layer; the axis of the channel hole is perpendicular to the substrate, and the channel hole exposes the storage gate; the conductive initial structure is located outside the channel hole Parts form second gate electrodes and first writing signal lines respectively.
  • a third insulating layer covering the inner wall of the channel hole is formed.
  • a second channel covering the third insulating layer and in contact with the storage gate is formed in the channel hole.
  • a second write signal line is formed on a surface of the second channel away from the storage gate.
  • a second channel and a second gate are respectively formed on a side of the storage gate away from the substrate, and a first write signal line connected to the second gate, and the second channel Connecting the second write signal line includes the following steps.
  • a first dielectric layer covering the storage gate is formed.
  • a second trench extending along the second direction is formed in the first dielectric layer.
  • a second write signal line is formed in the second trench.
  • a channel hole is formed that penetrates the second writing signal line and the first dielectric layer; the axis of the channel hole is perpendicular to the substrate, and the channel hole exposes the storage gate.
  • a second channel is formed on the sidewall and bottom of the channel hole.
  • a third insulating layer covering the second channel and the second writing signal line is formed.
  • a second gate electrode and a first writing signal line are formed on the surface of the third insulating layer away from the second channel, wherein at least part of the second gate electrode is still located in the channel hole.
  • yet another aspect of the present disclosure provides a memory, including:
  • first word line extending along a first direction
  • first bit line extending along a second direction
  • second word line or a second word line extending along the first direction or the second direction.
  • Two bit lines, the first direction and the second direction are arranged crosswise;
  • the first word line, the first bit line, and the second word line are arranged at intervals in a third direction vertical to the substrate; or, the first word line, the first bit line, and the second bit line are arranged in a vertical direction of the substrate.
  • the third direction is set at intervals in sequence;
  • the first word line and the first bit line are intersected to form an intersection point, and a memory unit is provided at the intersection point.
  • the memory unit includes a first transistor and a second transistor stacked on the substrate;
  • the first transistor includes a first gate, a storage gate, and a first semiconductor layer
  • the second transistor includes a second gate and a second semiconductor layer
  • the first gate is a portion of the first word line in the intersection area
  • the first semiconductor layer is a portion of the first first line in the intersection area
  • the storage gate is located in the intersection area above the first semiconductor layer and is isolated from the first semiconductor layer by a dielectric layer; the second gate and the second semiconductor layer are located in the intersection area.
  • the substrate is a substrate containing silicon
  • the first word line is at least partially buried in the substrate; the sidewalls of the first word line are wrapped with a first insulating layer that is isolated from the substrate; the first bit line It is a polysilicon layer stacked with the substrate.
  • a conductive film layer is further provided between the polysilicon layer of the first line and the substrate; the pattern of the conductive film layer corresponds to the pattern of the first line; the conductive film layer has an opening, and the first word line The top is located in the opening and is in contact with the polysilicon layer through the first insulating layer.
  • the conductive film layer is formed through an epitaxial process on a silicon-containing substrate, or the conductive film layer is a film layer containing metal.
  • another aspect of the present disclosure provides an electronic device, including the memory as described in some of the above embodiments.
  • the electronic device includes a smartphone, a computer, a tablet, an artificial intelligence, a wearable device or a smart mobile terminal.
  • Figure 1 is a schematic structural diagram of a memory provided in an embodiment
  • FIG 2 is an equivalent circuit diagram of the memory unit in the memory shown in Figure 1;
  • Figure 3 is a schematic structural diagram of another memory provided in an embodiment
  • Figure 4 is a schematic structural diagram of another memory provided in an embodiment
  • FIG. 5 is an equivalent circuit diagram of the memory unit in the memory shown in Figure 4.
  • Figure 6 is a schematic structural diagram of yet another memory provided in an embodiment
  • Figure 7 is a schematic circuit diagram of a memory provided in an embodiment
  • Figure 8 is a schematic structural diagram of another memory provided in an embodiment
  • Figure 9 is a schematic flow chart of a memory manufacturing method provided in an embodiment
  • Figure 10 is a schematic flowchart of the manufacturing steps of a first gate electrode and a first read signal line provided in an embodiment
  • Figure 11 is a schematic structural diagram of a structure obtained after forming a first insulating layer in an embodiment
  • Figure 12 is a schematic structural diagram of a structure obtained after forming a first channel and a second read signal line in an embodiment
  • Figure 13 is a schematic structural diagram of another structure obtained after forming a first channel and a second read signal line in an embodiment
  • Figure 14 is a schematic flow chart of another memory manufacturing method provided in an embodiment
  • Figure 15 is a schematic structural diagram of a structure obtained after forming a storage gate in an embodiment
  • Figure 16 is a schematic structural diagram of another structure obtained after forming a storage gate in an embodiment
  • Figure 17 is a schematic top view of the relative position distribution between a storage gate, a first read signal line and a second read signal line provided in an embodiment
  • Figure 18 is a schematic flowchart of the manufacturing steps of a second transistor provided in an embodiment
  • Figure 19 is a structural schematic diagram of the structure obtained in the manufacturing steps shown in Figure 18;
  • Figure 20 shows a relative position distribution between the second channel, the second gate and the first writing signal line, as well as the second writing signal line and the second channel and the first writing signal line in an embodiment.
  • Figure 21 is a schematic flow chart of the manufacturing steps of another second transistor provided in an embodiment
  • Figure 22 is a structural schematic diagram of the structure obtained in the manufacturing steps shown in Figure 21;
  • Figure 23 is a schematic structural diagram of a substrate, a first word line, and a first bit line provided in an embodiment
  • Figure 24 is a schematic structural diagram of another substrate, a first word line, and a first bit line provided in an embodiment
  • FIG. 25 is a schematic structural diagram of an electronic device provided in an embodiment.
  • Spatial relational terms such as “under”, “under”, “under”, “below”, “on”, “above”, etc., in This may be used to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as “below” or “under” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” may include both upper and lower orientations. Additionally, the device may be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • NAND flash memory can adopt a three-dimensional structure to have higher storage density and lower cost, and has become one of the important development trends in the field of storage technology.
  • the basic storage unit of NAND flash memory is the storage transistor.
  • the memory transistor includes a floating gate or charge trapping layer disposed between a control gate and a source/drain.
  • a high voltage such as 20V
  • charge injection or charge release can be performed on the floating gate based on the F-N tunneling principle or the thermal injection principle, thereby achieving data storage.
  • the current formed based on F-N tunneling or heat injection is very small, and the programming speed and erasing speed of NAND flash memory are both low.
  • the memory includes: a substrate 10 and one or more memory units SU disposed on the substrate 10. Multiple memory units SU may be arranged in one layer, or stacked in multiple layers in a direction vertical to the substrate.
  • the relative positions between the memory units SU in each layer may be array distribution, honeycomb distribution, or other shapes of distribution.
  • honeycomb distribution can be understood as multiple rows of memory units SU, and the staggered distribution between adjacent rows of memory units SU such that the geometric center of each memory unit SU in a column of memory units SU is not on a straight line, that is, it does not constitute an array distribution.
  • the honeycomb distribution is only used to illustrate the relative position of the geometric center of the storage unit SU, and does not limit the outer contour shape of the storage unit SU itself.
  • the memory unit SU can be understood as a memory unit on a logic circuit, such as 1T1C as a memory unit, or 2T0C as a memory unit SU, which does not limit the wiring characteristics or shape structure characteristics of the memory unit SU.
  • FIG. 1 shows a schematic structural diagram of a longitudinal cross-section of a memory, which can clearly illustrate the structures of the first transistor T1 and the second transistor T2 in the memory unit SU.
  • Figure 1 shows an embodiment of a 2TOC memory cell.
  • the memory cell includes a first transistor T1 for reading data and a second transistor T2 for writing data, which are stacked from bottom to top.
  • the memory also includes: a first read signal line L R1 , a second read signal line L R2 , a first write signal line L W1 and a second write signal line L W2 arranged corresponding to the memory unit SU.
  • the memory unit SU includes: a first transistor T1 located on a substrate 10 and a second transistor T2 located on a side of the first transistor T1 away from the substrate 10 .
  • the first transistor T1 includes: a first gate 11 , a first channel 12 and a storage gate 13 .
  • the first gate 11 is disposed on the substrate 10 and connected to the first read signal line LR1 .
  • the first channel 12 is located on the side of the first gate 11 away from the substrate 10 and is connected to the second read signal line LR2 .
  • the storage gate 13 is located on a side of the first channel 12 away from the first gate 11 . That is, the gate electrode, channel and storage gate electrode (also called back gate) of the first transistor T1 are stacked in sequence in the direction vertical to the substrate.
  • the second transistor T2 includes: a second channel 21 and a second gate 22 .
  • the second channel 21 and the second gate 22 are located on the surface of the storage gate 13 facing away from the substrate 10 and are connected to the storage gate 13 and the second write signal line L W2 respectively.
  • the second gate 22 is connected to the first write signal line L W1 .
  • At least one of the second gate 22 and the second channel 21 has a surrounding structure; the second gate 22 surrounds the second channel 21 , or the second channel 21 surrounds the second gate 22 .
  • the second gate is a gate-all-around structure that surrounds the sidewalls of the second channel, and the sidewalls of the second channel are approximately perpendicular to the substrate.
  • the second channel is a circumferential channel that surrounds the sidewalls of the second gate, and the sidewalls of the second gate are approximately perpendicular to the substrate.
  • the first channel 12 is insulated from the first gate 11 and the storage gate 13 respectively.
  • the second channel 21 is insulated from the second gate 22 .
  • the first channel 12 and the second channel 22 may each be composed of a portion of the corresponding semiconductor layer located at the corresponding gate electrode.
  • the first read signal line L R1 , the second read signal line L R2 , the first write signal line L W1 and the second write signal line L W2 of the plurality of memory units SU can be shared, but each memory unit SU
  • the corresponding storage gates 13 are independent of each other and are not shared or connected.
  • the first read signal lines LR1 of memory cells in the same column are shared.
  • the substrate 10 may be made of semiconductor materials, insulating materials, conductor materials, or any combination of these materials.
  • the substrate 10 may have a single-layer structure or a multi-layer structure.
  • the substrate 10 may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an arsenic Indium oxide (InAs) substrate, indium phosphide (InP) substrate or other III/V semiconductor substrate or II/VI semiconductor substrate.
  • the substrate 10 may be a layered substrate including, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon on insulator (SOI), silicon germanium on insulator, or the like.
  • the substrate 10 is an insulating substrate.
  • the first gate 11 is disposed on the substrate 10, including but not limited to: the first gate 11 is disposed in the substrate 10; that is, the first gate 11 adopts an embedded structure.
  • one embodiment is a 2TOC structure in which the memory unit SU is composed of a first transistor T1 and a second transistor T2.
  • the first transistor T1 adopts a double-gate structure, that is, it includes a first gate 11 and a storage gate 13; wherein, the first gate 11 is used to control the on/off of the first transistor T1, and the storage gate 13 is used to store or release. charge.
  • the storage gate 13 is located on a side of the first channel 12 away from the first gate 11 , and the storage gate 13 is connected to the second write signal line L W2 through the second transistor.
  • a high level or a low level, or different levels, etc. can be input to the storage gate 13 through the second writing signal line L W2 to implement data storage or erasing.
  • the first gate 11 is connected to the first read signal line L R1
  • the first channel 12 is connected to the second read signal line L R2
  • the second gate 22 is connected to the first write signal line L W1 is connected.
  • the first read signal line L R1, the second read signal line L R2, and the first write signal line L W1 are each in a strip shape
  • the first gate 11 is A part of the first read signal line L R1 and the first channel 12 are a part of the second read signal line L R2 . Therefore, in the cross-sectional view of the gate, the first gate 11 and the first read signal line L Signal lines L R1 are marked at the same location.
  • the reference numbers for the first channel 12 and the second read signal line LR2 are also similar and will not be described again here.
  • first gate 11 and the first read signal line L R1 in Figure 1 are marked with the same layer structure
  • first channel 12 and the second read signal line L R2 are marked with the same layer structure
  • second gate electrode 22 marks the same layer structure as the first write signal line L W1 .
  • the above-mentioned storage gate 13, the first channel 12 and the dielectric layer between them can be equivalent to a capacitor, corresponding to the storage capacitor C BG in the logic circuit as shown in Figure 2.
  • the storage gate 13 can A storage capacitor is formed between any adjacent electrode facing the storage gate 13 or as a part of the storage capacitor.
  • the memory unit SU in the embodiment of the present disclosure can realize data storage and erasure by changing the potential of the storage gate 13 .
  • the memory unit SU in the embodiment of the present disclosure can directly write data into the storage gate 13, thereby Has faster programming and erasing speeds.
  • the programming speed (such as data writing or data reading speed) and erasing speed of the memory in the embodiments of the present disclosure can be increased from the microsecond level to the nanosecond level.
  • the writing operation and the reading operation of the storage unit SU can be performed separately.
  • the first write signal line L W1 connected to the second transistor T2 is selected to transmit the control voltage
  • the second write signal line L W2 connected to the second transistor T2 is selected.
  • the data voltage can be directly written into the storage gate 13 after controlling the second transistor T2 to turn on, thereby easily completing the writing operation and achieving a faster speed.
  • the first transistor T1 remains off or on.
  • the second transistor T2 When performing a read operation on the target memory unit SU, the second transistor T2 is turned off. If the storage gate 13 stores a high level (for example, data 1), the first control voltage is applied to the first gate 11 through the first read signal line L R1 , so that the first transistor T1 can be turned on to read through the second The current transmitted by the signal line LR2 reads the data. If the storage gate 13 stores a low level (for example, data 0), the first transistor T1 can be turned off by applying a second control voltage to the first gate 11 through the first read signal line LR1 . For example, the first control voltage and the second control voltage applied by the first read signal line L R1 to the first gate 11 may be the same.
  • the memory unit SU will also perform an erasure operation (ie, a refresh operation).
  • the erasure operation is similar to the write operation. The only difference between the two is the signal transmitted to the storage gate 13 , which is no longer discussed here. Elaborate.
  • the first read signal line L R1 may be a read word line WL_r
  • the second read signal line L R2 may be a read bit line BL_r
  • the first write signal line L R2 may be a read bit line BL_r
  • the input signal line L W1 may be a write word line WL_w
  • the second write signal line L W2 may be a write bit line BL_w.
  • the first write signal line L W1 may be a write bit line BL_w
  • the second write signal line L W2 may be a write word line WL_w.
  • the memory further includes: a first insulation layer 31 between the first channel 12 and the first gate 11 , and a first insulation layer 31 between the first channel 12 and the storage gate 13 . the second insulating layer 32 between them.
  • the first insulating layer 31 and the second insulating layer 32 can effectively reduce the leakage current and ensure the device reliability of the first transistor T1 , including ensuring the storage reliability of the storage gate 13 .
  • the second insulating layer 32 may be a high-k dielectric layer with a dielectric constant greater than 3.9.
  • k refers to the dielectric constant, which measures the material's ability to store electric charge. According to the level of dielectric constant, they are divided into low dielectric (low-k) materials and high dielectric (high-k) materials. Generally, the dielectric constant of low-k materials is lower than 3.0; high-k materials are relative to SiO2. As long as the dielectric constant is greater than the dielectric constant of SiO2, 3.9, they are generally called high-k materials.
  • the second insulating layer 32 between the storage gate 13 and the first channel 12 is a high-k dielectric, but the medium between the first gate and the first channel can be a conventional gate insulating layer.
  • the gate electrode between the second gate electrode and the second channel can be a conventional gate insulating layer and does not have to be a high-k material.
  • the materials of the first insulating layer 31 or the second insulating layer 32 include: aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), hafnium oxynitride (HfON), zirconium oxide (ZrO 2 ), tantalum oxide At least one of (Ta 2 O 5 ), titanium oxide (TiO 2 ) or strontium titanium oxide (SrTiO 3 ).
  • the second transistor T2 uses a low-leakage current transistor to increase the residence time of the floating potential (or charge) on the storage electrode 13, thereby improving the performance of the storage unit SU.
  • the material of the second channel 21 includes a metal oxide semiconductor.
  • the first transistor T1 is a polysilicon transistor
  • the second transistor is a metal oxide transistor.
  • the material of the second channel 21 of the second transistor T2 includes at least one metal oxide semiconductor of indium, gallium, zinc or tin, such as Indium Gallium Zinc Oxide (IGZO).
  • IGZO Indium Gallium Zinc Oxide
  • the second channel 21 of the second transistor T2 can be formed using IGZO or ITO to facilitate reducing the leakage current of the second transistor T2 and ensuring that the second transistor T2 device reliability. But it doesn't stop there.
  • the second transistor T2 adopts the second channel 21.
  • the second transistor T2 may adopt, for example, a full surround type gate structure, or may adopt a full surround type channel structure. This is beneficial to increasing the distribution density of the memory units SU, that is, increasing the storage density of the memory.
  • the relative arrangement between the second gate 22 and the second channel 21 can be implemented in many different ways.
  • a third insulating layer 33 (for example, as shown in FIG. 1 ) may also be disposed between the second channel 21 and the second gate 22 .
  • the second transistor T2 adopts a full-surround gate structure.
  • the two ends of the second channel 21 along the direction perpendicular to the substrate (e.g., the Z direction) are respectively connected to the storage gate 13 and the second write signal line L W2 .
  • the second gate 22 is disposed around the sidewall of the second channel 21; that is, the second gate 22 can be disposed on the peripheral side of the second channel 21.
  • both ends of the second channel 21 along the direction perpendicular to the substrate 10 are connected to the storage gate 13 and the second write signal line L W2 respectively. End surfaces at both ends in the direction perpendicular to the substrate are respectively connected to the storage gate 13 and the second write signal line L W2 . It also includes side walls at both ends of the second channel 21 in the direction perpendicular to the substrate, respectively connected to the storage gate 13 and the second write signal line L W2. The gate 13 and the second write signal line L W2 are connected. Or, only the sidewalls at both ends of the second channel 21 in the direction perpendicular to the substrate are connected to the storage gate 13 and the second write signal line L W2 respectively.
  • the above position distribution of the memory gates 13 on the substrate 10 can be used to define the position distribution of the memory cells SU on the substrate 10 .
  • the geometric center of the orthographic projection of the second channel 21 on the substrate 10 coincides or approximately coincides with the geometric center of the orthographic projection of the storage gate 13 on the substrate 10 .
  • the orthographic outline of the second channel 21 on the substrate 10 coincides with or has an interval between the orthographic outline of the storage gate 13 on the substrate 10 , and the interval is less than or equal to the first threshold.
  • the first threshold can be selected and set according to actual needs, and this is not limited in the embodiments of the present disclosure. In this way, it is helpful to further increase the distribution density of the memory units SU.
  • the second transistor T2 adopts a full surround channel structure.
  • the second channel 21 surrounds at least part of the sidewalls of the second gate 22, or may further surround the bottom of the gate.
  • the storage gate may be directly connected to the second channel 21 .
  • a third insulating layer 33 is formed between the second gate 22 and the second channel 21 .
  • the second write signal line L W2 is connected to the top of the outer side wall of the second channel 21 .
  • the second gate 22 is also located on a side of the second writing signal line L W2 facing away from the substrate 10 .
  • the third insulating layer 33 also covers the surface of the second writing signal line L W2 facing away from the substrate 10 , and the second gate electrode 22 is formed on the surface of the third insulating layer 33 .
  • the second write signal line L W2 may be connected to the second read signal line L R2 . That is, the second write signal line L W2 and the corresponding second read signal line L R2 may be connected to the same data line, such as the bit line BL.
  • the second write signal line L W2 may be connected to the corresponding second read signal line L R2 through the connection line 6 .
  • the second write signal line L W2 and the corresponding second read signal line L R2 may be connected to the same signal terminal. This is beneficial to reducing the number of total signal lines between the storage units SU in the array area of the flash memory, and is beneficial to simplifying the wiring structure of peripheral circuits.
  • each signal line (including the first read signal line L R1 , the second read signal line L R2 , the first write signal line L W1 and the second write signal line L W2 ) can be led out to the edge area of the substrate 10, and their electrical connection is achieved using step wiring.
  • the embodiment of the present disclosure does not elaborate on the lead-out connection of each signal line, and the settings can be selected according to actual needs.
  • the second gate 22 and the first write signal line L W1 are arranged in the same layer and are integrally formed. That is, the second gate 22 and the first write signal line L W1 can use the same conductive material and pass through it once.
  • the patterning process is patterned to facilitate simplifying the memory production process.
  • the materials of the second gate 22 and the first writing signal line L W1 include metal, such as tungsten metal or copper metal.
  • the first gate 11 and the first read signal line L R1 are arranged in the same layer and are integrally formed. That is, the first gate 11 and the first read signal line L R1 can use the same conductive material and pass through it once.
  • the patterning process is patterned to facilitate simplifying the memory production process.
  • the materials of the first gate 11 and the first read signal line L R1 include metal, such as tungsten metal or copper metal.
  • the first gate 11 is a part of the first read signal line LR1 .
  • multiple rows of memory units SU are distributed with multiple first metal lines and multiple second metal lines.
  • the first gate 11 and the connected first read signal line L R1 are respectively parts of the same first metal line located in different regions.
  • the second gate 22 and the connected first writing signal line L W1 are respectively parts of the same second metal line located in different regions. In this way, it can be ensured that the first gate 11 and the connected first read signal line L R1 are linearly arranged, and the second gate 22 and the connected first write signal line L W1 are arranged linearly, thereby facilitating the realization of the third
  • the combination of the two transistors T2 and the first transistor T1 is stacked and effectively improves space utilization.
  • the material of the first channel 12 in the first transistor T1 includes polysilicon or a metal oxide semiconductor.
  • the metal oxide semiconductor is, for example, indium gallium zinc oxide (IGZO) or indium tin oxide (ITO), but is not limited thereto.
  • the material of the first channel 12 in the first transistor T1 is polysilicon.
  • the first channel 12 and the second read signal line L R2 are arranged on the same layer and are integrally formed. That is, the first channel 12 and the second read signal line L R2 can be formed using polysilicon material and patterned through a one-time patterning process, so as to simplify the memory production process.
  • the first channel 12 is a part of the second read signal line LR2 .
  • the multi-column memory unit SU has a plurality of semiconductor traces distributed correspondingly; wherein, the first channel 12 is a portion of the semiconductor trace located in the channel region, and the second read signal line is connected to the first channel 12 LR2 includes the portion of the semiconductor trace located in the connection area.
  • the semiconductor traces are, for example, polysilicon strip traces.
  • connection area may be located between adjacent first channels 12 in the same column, for example.
  • the second read signal line LR2 includes a portion LR21 of the semiconductor trace located in the connection area, and the second read signal line LR2 further includes: Metal trace LR22 on one side of the line and located in the connection area.
  • the semiconductor traces are IGZO strip traces.
  • the second read signal line LR2 is composed of a portion LR21 of the semiconductor trace located in the connection area and a stacked metal trace LR22 .
  • the metal trace LR22 can be used to reduce the resistance of the second read signal line LR2 , so as to increase the read speed of the memory unit SU.
  • the metal trace LR22 is located on a side surface of the semiconductor trace located on the connection area portion LR21 close to the substrate 10 .
  • the memory further includes: a first dielectric layer 4 covering the storage gate 13 and used to isolate the adjacent storage gate 13 and the bottom of the adjacent second channel 21, and/or covering the second gate 21 and It is used to isolate the second dielectric layer 5 between adjacent second gate electrodes 21 and the tops of adjacent second channels 21 .
  • the number and arrangement positions of the first dielectric layer 4 and the second dielectric layer 5 can be selected according to the manufacturing process of the memory.
  • the first dielectric layer 4 may include: a first sub-layer 41 located between adjacent storage gates 13 and a second sub-layer 42 located between the bottoms of adjacent second channels 21 .
  • each dielectric layer can be made of a thin film with excellent insulating properties, such as a silicon oxide layer, a silicon nitride layer or a silicon oxynitride layer.
  • the number of storage units SU is multiple.
  • a plurality of memory units SU are stacked in a direction perpendicular to the substrate to form different layers.
  • Multiple memory units SU located on the same layer may be arranged in rows along the first direction and in columns along the second direction; wherein the first direction and the second direction are parallel to the substrate and intersect.
  • the memory in the embodiment of the present disclosure can adopt a three-dimensional structure to have higher storage density and lower cost per bit (Bit).
  • the memory in the embodiment of the present disclosure can also adopt multi-byte storage with multiple threshold voltages to further reduce the cost per bit.
  • the first direction and the second direction are perpendicular, the first direction is, for example, the Y direction, and the second direction is, for example, the X direction.
  • the direction perpendicular to the substrate 10 is the Z direction.
  • Embodiments of the present disclosure can easily obtain a three-dimensional memory by stacking memory units SU in the Z direction.
  • first read signal line L R1 and the first write signal line L W1 extend along the first direction (for example, the Y direction), and the second read signal line L R2 and the second write signal line L R2 extend along the first direction. Extend in two directions (for example, X direction).
  • the memory in the embodiment of the present disclosure can store character strings, that is, it can be implemented by a group of storage units SU connected in series.
  • multiple memory cells SU in any layer are arranged in an array, for example, arranged in rows along the first direction (i.e., Y direction) and arranged in columns along the second direction (i.e., X direction); here, Rows and columns are only used to describe relative directions, and they can be expressed interchangeably.
  • the first read signal line L R1 is the read word line WL_r
  • the second read signal line L R2 is the read bit line BL_r
  • the first write signal line L W1 is the write word line WL_w
  • the second write signal line L R1 is the read word line WL_r.
  • the equivalent circuit diagram between multiple memory units SU can be as shown in FIG. 7 .
  • any layer of storage units SU multiple storage units SU are arranged in an m ⁇ n matrix, where m is the number of rows and n is the number of columns.
  • the first channels 12 in any column of memory units SU can be connected in series into an integrated structure to realize the series connection of the memory units SU in the column.
  • selection transistors can be respectively provided at both ends of any group of series-connected memory cells SU along the column direction, so that the two selection transistors can communicate with the source line Source Line and the second read signal line L R2 (ie, the read bit Line BL_r) corresponds to the connection.
  • L R2 ie, the read bit Line BL_r
  • any group of serially connected memory cells SU may be connected to the source line Source Line through the first selection transistor ST1 and connected to the second read signal line LR2 through the second selection transistor ST2 .
  • the gate electrode of the first selection transistor ST1 corresponding to each group of memory units SU can be connected to the same first selection signal line SSL
  • the gate electrode of the second selection transistor ST2 corresponding to each group of memory units SU can be connected to the same second selection line.
  • the source line Source Line may provide the reference voltage Vref to the memory unit SU.
  • the logical pages of the memory in the embodiment of the present disclosure may be implemented by storage units SU in the same row.
  • the first gate 11 of the first transistor T1 in any row of memory cells SU can be connected to the same first read signal line L R1 (ie, the read word line WL_r), and the second gate 22 of the second transistor T2 can be connected to the same first read signal line L R1 (ie, read word line WL_r).
  • a first write signal line L W1 ie, write word line WL_w.
  • the number of logical pages in each row of the memory is related to the storage capacity of the storage unit SU, that is, n can be selected and determined according to the storage capacity of the storage unit SU.
  • memory write operations and read operations can be performed in the following ways.
  • the above write operations can be performed sequentially from the next row to the previous row, for example, from the storage unit SU of row i-1 to the storage unit SU of row i, i ⁇ m.
  • a write operation on the storage unit SU in the target row for example, row i
  • then: turn off each transistor corresponding to the storage unit SU outside the target row (number of rows ⁇ i) and the transistors of the storage unit SU in the target row (number of rows i).
  • the above read operation can be performed on any storage unit SU.
  • both the first selection signal line SSL and the second selection signal line DSL provide a high level, and provide a low level to all write word lines WL_w to turn off all second transistors.
  • T2 At this time, if the target storage unit SU stores a high level (for example, data 1), the first control voltage is applied to the first gate 11 of the target storage unit SU by reading the word line WL_r, and the first transistor T1 can be turned on.
  • the target memory unit SU reads the data with the current transmitted through the read bit line BL_r; if the target memory unit SU stores a low level (for example, data 0), apply a second second voltage to the first gate 11 of the target memory unit SU through the read word line WL_r.
  • the first transistor T1 can be turned off.
  • the first control voltage and the second control voltage applied by the read word line WL_r to the first gate 11 may be the same.
  • the second write signal line L W2 is connected to the second read signal line L R2.
  • the second read signal line L W2 is limited to the second read signal line L R2 .
  • the memory will also perform an erasure operation (ie, refresh operation).
  • the erasure operation is similar to the write operation. The only difference between the two is the signal transmitted to the storage gate 13 in the storage unit SU. Here No more details.
  • the memory adopts a three-dimensional structure, that is, the memory units SU can be stacked to form different layers along a direction vertical to the substrate 10 .
  • FIG. 8 an embodiment of the present disclosure illustrates a three-dimensional structure.
  • the plurality of memory units SU are sequentially arranged into the first layer memory unit SU1, the second layer memory unit SU2, the third layer memory unit SU3, etc.; accordingly, each signal line can Add a layer identifier corresponding to the layer where it is located to distinguish it, such as L R1 1, L R1 2, L R1 3, etc.
  • an isolation layer may be formed between the memory units SU of adjacent layers; for example, a first isolation layer 71 is formed between the first-level memory unit SU1 and the second-level memory unit SU2, and the second-level memory unit SU2 and the second-level memory unit SU2 are formed between the first isolation layer 71 and the second-level memory unit SU2.
  • a second isolation layer 72 is formed between the three layers of memory cells SU3. In this way, the first gate electrode 11 in the first layer memory unit SU1 is disposed in the substrate 10, the first gate electrode 11 in the second layer memory unit SU2 can be disposed in the first isolation layer 71, and the third layer memory unit The first gate 11 in SU3 may be disposed within the second isolation layer 72 .
  • the materials of the first isolation layer 71 and the second isolation layer 72 include silicon oxide or other insulating materials.
  • the memory adopts the above structure, which facilitates the realization of three-dimensional storage to increase storage density and at the same time simplifies the manufacturing process of the memory to improve production efficiency and production yield.
  • FIG. 9 another aspect of the present disclosure provides a memory manufacturing method for manufacturing the memory as described in some of the above embodiments.
  • the manufacturing method includes the following steps.
  • S300 Form a first channel and a second read signal line connected to the first channel on the side of the first gate facing away from the substrate.
  • S400 Form a storage gate on a side of the first channel away from the first gate.
  • S500 Form a second channel and a second gate on the surface of the storage gate away from the substrate, and form a first write signal line connected to the second gate.
  • a second write signal line connected to the second channel is formed.
  • the second channel is connected to the storage gate, and at least one of the second gate and the second channel has a surrounding structure; the second gate surrounds the second channel, or the second channel surrounds the second gate.
  • the first gate, the first channel and the storage gate together constitute the first transistor; the second channel and the second gate together constitute the second transistor; the first transistor and the second transistor together constitute the memory unit.
  • the manufacturing method provided by the embodiments of the present disclosure is used to manufacture the memory in some of the foregoing embodiments.
  • the advantages of the foregoing memory are also possessed by the embodiments of the present disclosure and will not be described in detail here.
  • the substrate 10 is an insulating substrate.
  • step S200 forming a first gate on the substrate and a first read signal line connected to the first gate includes steps S201 and S202.
  • step S201 as shown in (a) of FIG. 11, a first trench G1 extending along a first direction (eg, Y direction) is formed in the substrate 10.
  • the first trench G1 is used to accommodate the first gate 11 and the first read signal line L R1 .
  • step S202 as shown in (b) of FIG. 11, conductive material is filled in the first trench G to form the first gate 11 and the first read signal line L R1 .
  • the conductive material may be, for example, doped polysilicon or conductive metal.
  • a first insulating layer 31 is formed on the exposed surfaces of the substrate 10 , the first gate 11 , and the first read signal line L R1 .
  • the material of the first insulating layer 31 please refer to the relevant descriptions in some of the foregoing embodiments, and will not be described in detail here.
  • the first insulating layer 31 can also be formed in other ways. Specifically, as shown in (a) of FIG. 12, the first gate electrode 11 and the first gate electrode 11 are formed in the substrate 10. First read signal line L R1 ; as shown in (b) of Figure 12, part of the substrate 10 is removed from top to bottom to form a groove between adjacent first gate electrodes 11; as shown in Figure 12 As shown in (c), a first insulating layer 31 is formed to cover the exposed surface of the first gate 11 and the exposed surface of the substrate 10 after the groove is formed.
  • the source electrode 14 and the drain electrode 15 are respectively formed on the surface of the portion of the first insulating layer 31 located in the groove of the substrate 10 .
  • the source electrode 14 and the drain electrode 15 fill the aforementioned grooves, and the surfaces of the source electrode 14 and the drain electrode 15 facing away from the substrate 10 may be flush with the upper surface of the first insulating layer 31 located on the top portion of the first gate electrode 11 .
  • a flat semiconductor layer can be formed on the exposed surfaces of the source electrode 14, the drain electrode 15 and the first insulating layer 31, and the semiconductor layer can be patterned to form the first channel 12 and the second read signal line L R2 .
  • the second read signal line LR2 includes a stacked semiconductor trace portion LR21 and a metal trace LR22 , wherein the metal trace LR22 is located close to the semiconductor trace portion LR21 one side of substrate 10 .
  • step S300 is performed to form a first channel and a second read signal line connected to the first channel on the side of the first gate away from the substrate, including steps S310 to S330.
  • S310 Form metal traces.
  • the metal traces are located between adjacent first gates arranged in the column direction and are insulated from the first gates.
  • a first insulating layer 31 is formed on the surface of the first gate 11 away from the substrate 10 , and the metal traces L R22 are formed on the surface of the first insulating layer 31 and fill the adjacent first gate. groove between poles 11.
  • the surface of the metal trace LR22 facing away from the substrate 10 may be flush with the upper surface of the first insulation layer 31 located on the top portion of the first gate 11 .
  • S320 Form a semiconductor layer on the surface of the metal trace facing away from the substrate and on the side of the first gate facing away from the substrate.
  • the semiconductor layer in conjunction with the positional relationship between the metal trace LR22 and the first insulating layer 31 in step S310, the semiconductor layer also covers the remaining exposed surface of the first insulating layer 31 after the metal trace LR22 is formed.
  • the material of the semiconductor layer includes polysilicon or metal oxide semiconductor.
  • the metal oxide semiconductor may be, for example, IGZO or ITO.
  • S330 pattern the semiconductor layer to form semiconductor wiring.
  • the portion of the semiconductor trace located in the channel region forms the first channel.
  • the portion of the semiconductor trace covering the metal trace together with the metal trace constitute a second read signal line.
  • the semiconductor wiring is a strip wiring, for example.
  • the part of the semiconductor trace located in the channel area forms the first channel 12.
  • the part LR21 of the semiconductor trace covering the metal trace LR22 and the metal trace LR22 are stacked to form the second read signal line LR2 .
  • the metal trace LR22 is used to reduce the resistance of the second read signal line LR2 , thereby increasing the read speed of the memory unit SU.
  • step S300 before step S300 is performed to form a first channel and a second read signal line connected to the first channel on the side of the first gate away from the substrate, the The manufacturing method also includes step S210.
  • the first insulating layer 31 covering the first gate electrode 11 is formed.
  • the manufacturing method further includes step S340.
  • a second insulating layer 32 covering the first channel 12 and the second read signal line L R2 is formed.
  • step S400 may also be expressed as S400′.
  • the storage gate 13 is formed on the surface of the second insulating layer 32 away from the first channel 12.
  • the use of the first insulating layer 31 and the second insulating layer 32 can reduce the leakage current and ensure the device reliability of the first transistor T1.
  • the dielectric constant of the first insulating layer 31 or the second insulating layer 32 is greater than 3.9.
  • the materials of the first insulating layer 31 or the second insulating layer 32 include: aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), hafnium oxynitride (HfON), zirconium oxide (ZrO 2 ), tantalum oxide At least one of (Ta 2 O 5 ), titanium oxide (TiO 2 ) or strontium titanium oxide (SrTiO 3 ).
  • forming a storage gate on the side of the first channel away from the first gate in step S400 may include: forming a storage gate material layer covering the second insulating layer 32; patterning the storage gate; The gate material layer forms the storage gate 13 .
  • the orthographic projection of the storage gate 13 on the substrate 10 at least partially overlaps with the orthographic projection of the first gate 11 on the substrate 10 .
  • the position distribution of the memory gates 13 on the substrate 10 is used to define the position distribution of the memory cells SU on the substrate 10 .
  • the storage gate 13 can be formed by first forming a material layer and then patterning, but it is not limited to this.
  • step S400 can also be expressed as: forming a first sub-dielectric layer 41 covering the second insulating layer 32, and the first sub-dielectric layer 41 has a pattern for defining the storage gate 13. Formation position: fill the pattern of the first sub-dielectric layer 41 with storage gate material to form the storage gate 13 .
  • the material of the storage gate 13 includes tungsten metal or copper metal.
  • the location distribution of the memory gates 13 on the substrate 10 can be used to define the location distribution of the memory units SU on the substrate 10 , that is, to define the distribution density of the memory units SU.
  • the first read signal line LR1 extends along the first direction (for example, the Y direction), and the plurality of first read signal lines LR1 are arranged in parallel and spaced apart.
  • the second read signal line LR2 extends along the second direction (for example, the X direction), and a plurality of second read signal lines LR2 are arranged in parallel and spaced apart.
  • the first direction and the second direction intersect, for example vertically.
  • the second transistor T2 adopts the second channel 21.
  • the second transistor T2 may adopt, for example, a full surround type gate structure, or may adopt a full surround type channel structure. This is beneficial to increasing the distribution density of the memory units SU, that is, increasing the storage density of the memory.
  • the relative arrangement between the second gate 22 and the second channel 21 can be implemented in many different ways. That is, corresponding to different structures of the second transistor T2, the manufacturing methods of the corresponding semiconductor structures are different.
  • step S500 a second channel and a second gate are respectively formed on the side of the storage gate away from the substrate, and a first write signal line connected to the second gate is formed. , and forming a second writing signal line connected to the second channel, including the following steps S501 to S507.
  • S502 Form a conductive layer covering the first dielectric layer, and pattern the conductive layer to form a conductive initial structure and expose part of the first dielectric layer.
  • S503 Form a second dielectric layer covering the conductive initial structure and the first dielectric layer.
  • S505 Form a third insulating layer covering the inner wall of the channel hole.
  • S506 Form a second channel covering the third insulating layer and in contact with the storage gate in the channel hole.
  • S507 Form a second write signal line on the surface of the second channel away from the storage gate.
  • step S501 please refer to (a) in FIG. 19 to form a first dielectric layer 4 covering the storage gate 13.
  • the storage gate 13 is formed on the surface of the second insulating layer 32 , and the first dielectric layer 4 also covers the surface of the second insulating layer 32 that is not covered by the storage gate 13 .
  • step S502 please understand with reference to (a) in FIG. 19 , a conductive layer covering the first dielectric layer 4 is formed, and the conductive layer is patterned to form a conductive initial structure and expose part of the first dielectric layer 4 .
  • step S503 please understand with reference to (a) in FIG. 19 , a second dielectric layer 5 covering the conductive initial structure and the first dielectric layer 4 is formed.
  • step S504 please understand in conjunction with Figure 19(a) that a channel hole H is formed in the second dielectric layer 5, the conductive initial structure and the first dielectric layer 4; the axis line of the channel hole H is perpendicular to In the substrate 10, the channel hole H exposes the storage gate 13; the portion of the conductive initial structure located outside the channel hole H forms the second gate 22 and the first write signal line L W1 .
  • step S505 please refer to (b) of FIG. 19 to form a third insulating layer 33 covering the inner wall of the channel hole H.
  • the third insulating layer 33 can be formed by depositing a dielectric film, for example, using an atomic layer deposition (ALD) process.
  • ALD atomic layer deposition
  • step S506 please refer to (b) of FIG. 19 , a second channel 21 covering the sidewalls of the third insulating layer 33 and in contact with the storage gate 12 is formed in the channel hole H.
  • the second channel 21 may be formed by filling semiconductor material.
  • the semiconductor material is, for example, a metal oxide semiconductor such as IGZO or ITO.
  • the semiconductor material can be filled using a deposition process, including but not limited to Atomic Layer Deposition (ALD) or Physical Vapor Deposition (PVD).
  • ALD Atomic Layer Deposition
  • PVD Physical Vapor Deposition
  • step S507 please refer to (c) of FIG. 19, a second write signal line L W2 is formed on the surface of the second channel 21 away from the storage gate 13.
  • the first sub-dielectric layer 41 has been manufactured before forming the storage gate 13, then the first dielectric layer 4 formed in step S501 can be correspondingly expressed as: forming the first sub-dielectric layer 41.
  • the two sub-dielectric layers 42 together form the first dielectric layer 4 by the second sub-dielectric layer 42 and the first sub-dielectric layer 41 .
  • the first dielectric layer 4 and the second dielectric layer 5 may be formed of a thin film with excellent insulating properties such as a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.
  • the conductive layer may be a tungsten metal layer or a copper metal layer.
  • the orthographic relationship between the second channel 21 , the second gate 22 and the first write signal line L W1 on the substrate 10 is as shown in (a) of FIG. 20 .
  • the geometric center of the orthographic projection of the second channel 21 on the substrate 10 may coincide or approximately coincide with the geometric center of the orthographic projection of the storage gate 13 on the substrate 1 .
  • the outer contour of the second channel 21 orthogonally projected on the substrate 10 coincides with or has an interval between the outer contour of the storage gate 13 orthogonally projected on the substrate 10 , and the interval is less than or equal to first threshold.
  • the second gate 22 is disposed around the sidewall of the second channel 21 .
  • the first writing signal line L W1 is connected to the second gate 22 and extends along the first direction (for example, the Y direction).
  • the plurality of first writing signal lines L W1 are arranged in parallel and spaced apart.
  • the orthographic relationship between the second writing signal line L W2 and the second channel 21 and the first writing signal line L W1 on the substrate 10 is for example ( in FIG. 20 b) as shown in the figure.
  • the second writing signal line L W1 extends along a second direction (for example, the X direction); the second direction intersects with the first direction, for example, perpendicularly.
  • a plurality of second writing signal lines L W2 are arranged in parallel and spaced apart.
  • the orthographic projection of the second channel 21 on the substrate 10 is located within the orthographic projection range of the second writing signal line L W2 on the substrate 10 .
  • the second write signal line L W2 may be implemented by performing a molding process on the metal layer.
  • the metal layer may be a tungsten metal layer or a copper metal layer.
  • step S500 a second channel and a second gate are respectively formed on the side of the storage gate away from the substrate to form a first write signal connected to the second gate. line, and forming a second writing signal line connected to the second channel, including the following steps S501' to S507'.
  • S502' form a second trench extending along the second direction in the first dielectric layer.
  • S504' form a channel hole penetrating the second writing signal line and the first dielectric layer; the axis line of the channel hole is perpendicular to the substrate, and the channel hole exposes the storage gate.
  • S506' form a third insulating layer covering the second channel and the second write signal line.
  • S507' form a second gate electrode and a first writing signal line on the surface of the third insulating layer away from the second channel, wherein at least part of the second gate electrode is still located in the channel hole.
  • step S501' please refer to (a) in FIG. 22 to form the first dielectric layer 4 covering the storage gate 13.
  • the storage gate 13 is formed on the surface of the second insulating layer 32 , and the first dielectric layer 4 also covers the surface of the second insulating layer 32 that is not covered by the storage gate 13 .
  • a second trench (not shown) extending along a second direction (eg, X direction) is formed in the first dielectric layer 4, and a second write signal line LW2 is formed in the second trench.
  • step S504' please refer to (b) in FIG. 22 to form a channel hole H penetrating the second write signal line L W2 and the first dielectric layer 4; the axis line of the channel hole H is perpendicular to the liner. On the bottom 10 , the channel hole H exposes the storage gate 13 .
  • step S505' please refer to (c) in FIG. 22 to form a second channel 21 on the sidewall and bottom of the channel hole H.
  • the second channel 21 may be formed by depositing a semiconductor film on the sidewalls and bottom of the channel hole H.
  • the second channel 21 adopts a thin film structure, and the second channel 21 can have grooves.
  • the semiconductor film is, for example, an IGZO or ITO film, which can be formed using an atomic layer deposition (ALD) process. But it doesn't stop there.
  • step S506' please continue to refer to (c) in FIG. 22 to form a third insulating layer 33 covering the second channel 21 and the second write signal line L W2 .
  • the third insulating layer 33 can be formed by depositing a dielectric film, for example, using an atomic layer deposition (ALD) process.
  • ALD atomic layer deposition
  • step S507' referring to (d) of FIG. 22, the second gate 22 and the first write signal line L W1 are formed on the surface of the third insulating layer 33 away from the second channel 21.
  • the first writing signal line L W1 and the second gate electrode 22 have an integrated structure and can extend along the first direction (for example, the Y direction).
  • the second gate 22 may fill the aforementioned groove of the second channel 21 and be isolated from the second channel 21 by the third insulating layer 33; that is, at least part of the second gate 22 is still located in the channel hole H.
  • the second gate 22 is, for example, a T-shaped gate.
  • the memory may adopt a three-dimensional structure, that is, the memory units SU may be stacked in different layers along a direction vertical to the substrate 10 .
  • the manufacturing method further includes: stacking multi-layer memory units SU in a direction vertical to the substrate 10 .
  • the manufacturing of the memory unit SU of any layer can be carried out by referring to the manufacturing of the memory unit SU in some of the foregoing embodiments, and will not be described again.
  • an isolation layer may be formed between memory units SU in adjacent layers. In this way, the first gate 11 and the first read signal line L R1 in the memory cells SU in other layers than the first layer can be formed in the corresponding isolation layers.
  • the above manufacturing method is adopted to facilitate the manufacture of three-dimensional memories, thereby improving the storage density while simplifying the memory manufacturing process, thereby improving production efficiency and production yield.
  • Some embodiments of the present disclosure also provide a memory, including:
  • first word line extending along a first direction
  • first bit line extending along a second direction
  • second word line or a second word line extending along the first direction or the second direction.
  • Two bit lines, the first direction and the second direction are arranged crosswise;
  • the first word line, the first bit line, and the second word line are arranged at intervals in a third direction vertical to the substrate; or, the first word line, the first bit line, and the second bit line are arranged in a vertical direction of the substrate.
  • the third direction is set at intervals in sequence;
  • the first word line and the first bit line are intersected to form an intersection point, and a memory unit is provided at the intersection point.
  • the memory unit includes a first transistor and a second transistor stacked on the substrate;
  • the first transistor includes a first gate, a storage gate, and a first semiconductor layer
  • the second transistor includes a second gate and a second semiconductor layer
  • the first gate is a portion of the first word line in the intersection area
  • the first semiconductor layer is a portion of the first first line in the intersection area
  • the storage gate is located in the intersection area above the first semiconductor layer and is isolated from the first semiconductor layer by a dielectric layer; the second gate and the second semiconductor layer are located in the intersection area.
  • the storage unit is, for example, the storage unit SU in some of the foregoing embodiments.
  • the first word line is, for example, the aforementioned first read signal line L R1
  • the first bit line is, for example, the aforementioned second read signal line L R2
  • the second word line is, for example, the aforementioned first write signal line L W1
  • the second bit line is, for example, the aforementioned second write signal line L W2 .
  • at least part of the first semiconductor layer in the first transistor is used to form the first channel 12
  • at least part of the second semiconductor layer in the second transistor is used to form the second channel 21 .
  • the dielectric layer in the memory gate of the first transistor and the first semiconductor layer is, for example, the aforementioned second insulating layer 32 .
  • the first word line (ie, the first read signal line L R1 ) extends along the first direction (eg, Y direction), and the first bit line (ie, the second read signal line L R2 ) extends along the second direction (for example, the X direction), the second word line (ie, the first write signal line L W1 ) extends along the first direction (for example, the Y direction), and the second bit line (ie, the second write signal line L W1 Line L W2 ) extends along a second direction (eg, X direction).
  • the extending directions of the first word line (ie, the first read signal line L R1 ) and the first bit line (ie, the second read signal line L R2 ) remain unchanged, and the second word line (ie, the second read signal line L R2 ) remains unchanged. That is, the first write signal line L W1 ) extends along the second direction (for example, the X direction), and the second bit line (ie, the second write signal line L W2 ) extends along the first direction (for example, the Y direction), which are also Allowed.
  • the first word line ie, the first read signal line L R1
  • the first bit line ie, the second read signal line L R2
  • the second word line ie, the second read signal line L R2
  • the first writing signal lines L W1 are sequentially arranged at intervals in the third direction (for example, the Z direction) perpendicular to the substrate 10 .
  • a first insulating layer 31 is provided between the first word line (ie, the first read signal line L R1 ) and the first bit line (ie, the second read signal line L R2 );
  • the second insulating layer 32 and the first dielectric layer 4 are disposed in sequence between the two read signal lines L R2 ) and the second word line (that is, the first write signal line L W1 ).
  • the second transistor T2 may adopt, for example, the all-around gate structure such as (Gate-All-Around, GAA for short) as described in some previous embodiments, which will not be described in detail here.
  • the first word line i.e., the first read signal line LR1
  • the first bit line i.e., the second read signal line LR2
  • the second bit line i.e., the second write signal line LR2
  • a third direction e.g., Z direction
  • a first insulating layer 31 is arranged between the first word line (i.e., the first read signal line LR1 ) and the first bit line (i.e., the second read signal line LR2 ); a second insulating layer 32 and a first dielectric layer 4 are sequentially arranged between the first bit line (i.e., the second read signal line LR2 ) and the second bit line (i.e., the second write signal line LR2 ).
  • the second transistor T2 may, for example, adopt a full-around channel structure (Channel-All-Around, referred to as CAA) as described in the previous embodiments, which will not be described in detail here.
  • the first word line i.e., the first read signal line L R1
  • the first bit line i.e., the second read signal line L R2
  • the intersection point is provided with a memory Unit SU.
  • the first gate 11 is the part of the first word line (ie, the first read signal line L R1 ) in the intersection area
  • the first semiconductor layer eg, the first channel 12
  • the second read signal line L R2 is in the intersection region
  • the storage gate 13 is located in the intersection region above the first semiconductor layer to define the formation position of the memory unit SU.
  • the second gate 22 and the second semiconductor layer eg, the second channel 21
  • the memory adopts the above structure, which can effectively increase the distribution density of storage cells in the memory to achieve high-density storage of the memory.
  • the substrate 10 is a substrate containing silicon, and the first word line (eg, the first read signal line L R1 ) is at least partially buried in the substrate 10 .
  • the sidewalls of the first word line (for example, the first read signal line L R1 ) are wrapped with a first insulating layer 31 that is isolated from the substrate 10 ; the first bit line (for example, the second read signal line L R2 ) is formed with
  • the substrate 10 is provided with a stack of polysilicon layers.
  • the first insulating layer 31 may be a high-K dielectric layer, a conventional gate insulating layer or other insulating materials.
  • the sidewalls of the first word line include its top wall and bottom wall.
  • a conductive film layer L' is also disposed between the polysilicon layer of the first bit line (for example, the second read signal line L R2 ) and the substrate 10;
  • the pattern corresponds to the pattern of the first word line;
  • the conductive film layer L′ has an opening, and the top of the first word line is located in the opening and contacts the polysilicon layer through the first insulating layer 31 .
  • the conductive film layer L' is formed by an epitaxial process on the silicon-containing substrate 10, or the conductive film layer L' is a film layer containing metal.
  • the conductive film layer L' is a metal silicide layer, such as cobalt silicide, titanium silicide, zirconium silicide, tantalum silicide, or tungsten silicide.
  • the conductive film layer L' can form a metal trace LR22 , and together with the first bit line form the aforementioned second read signal line LR2 , so as to effectively reduce the resistance of the second read signal line LR2 .
  • Some embodiments of the present disclosure provide an electronic device, including a smart phone, a computer, a tablet, artificial intelligence, a wearable device, or a smart mobile terminal.
  • the electronic device 100 includes a housing 1 , a circuit board 2 disposed in the housing 1 , and a memory 3 integrated on the circuit board 2 .
  • a memory 3 integrated on the circuit board 2 .
  • the electronic device 100 may also include other necessary elements or components, which are not limited in this embodiment of the disclosure.
  • external control devices such as processors or actuators coupled to the memory 3 can also be integrated on the circuit board 2 .
  • the electronic device 100 further includes a processor 40 integrated on the circuit board 2 .
  • the processor 40 is coupled to the memory 3 , and the processor 40 can control the read and write operations of the memory 3 .
  • the memory 3 may be a flash memory, such as a NAND flash memory.
  • the electronic device 100 uses a memory 3, which can have better data storage capabilities when the memory 3 has a three-dimensional structure. Moreover, the memory 3 is manufactured using the structures and manufacturing methods in some of the above embodiments, and can have higher programming speed, erasing speed and higher production yield, thereby effectively optimizing the performance and reliability of the memory 3, thereby ensuring electronic The device 100 has better performance and reliability.

Abstract

本公开涉及半导体技术领域，具体涉及一种存储器及其制造方法、电子设备，用于解决NAND闪存编程速度和擦除速度均较低的技术问题。所述存储器，包括：衬底(10)以及设置于衬底(10)上的存储单元(SU)。存储单元(SU)包括：第一晶体管(T1)及第二晶体管(T2)。第一晶体管(T1)包括：第一栅极(11)、第一沟道(12)和存储栅极(13)。第一栅极(11)设置于衬底(10)上，与第一读取信号线(L R1)相连接。第一沟道(12)位于第一栅极(11)背离衬底(10)的一侧，与第二读取信号线(L R2)相连接。存储栅极(13)位于第一沟道(12)背离第一栅极(11)的一侧。第二晶体管(T2)包括：第二沟道(21)和第二栅极(22)。第二沟道(21)位于存储栅极(13)背离衬底(10)的表面，并分别与存储栅极(13)、第二写入信号线(L W2)相连接。第二栅极(22)与第一写入信号线(L W1)相连接。第二栅极(22)和第二沟道(21)中的至少之一为环绕型结构；第二栅极(22)环绕第二沟道(21)，或者第二沟道(21)环绕第二栅极(22)。本公开用以改善存储器的存储性能。

Description

存储器及其制造方法、电子设备
相关申请的交叉引用
本公开要求于2022年09月16日提交中国专利局、申请号为202211131441.6、发明名称为“存储器及其制备方法、电子设备”的中国专利申请的优先权，所述专利申请的全部内容通过引用结合在本公开中。
技术领域
本公开涉及半导体技术领域，尤其涉及一种存储器及其制造方法、电子设备。
背景技术
随着通讯技术和数字技术的发展，人们持续追求功耗更低、重量更轻和性能更佳的产品。NAND快闪存储器储器(简称闪存)作为一种非易失性存储器，可以采用三维结构以具有更高的存储密度和更低的成本，已成为存储技术领域的重要发展趋势之一。
发明内容
根据本公开的各种实施例，提供一种存储器及其制造方法、电子设备。
根据一些实施例，本公开一方面提供了一种存储器，包括：衬底以及设置于衬底上的多个存储单元、第一读取信号线、第二读取信号线、第一写入信号线和第二写入信号线。存储单元包括：第一晶体管以及位于第一晶体管背离衬底一侧的第二晶体管。第一晶体管包括：第一栅极、第一沟道和存储栅极。第一栅极设置于衬底上，与第一读取信号线相连接。第一沟道位于第一栅极背离衬底的一侧，与第二读取信号线相连接。存储栅极位于第一沟道背离第一栅极的一侧。第二晶体管包括：第二沟道和第二栅极。第二沟道位于存储栅极背离衬底的表面，并分别与存储栅极、第二写入信号线相连接。第二栅极与第一写入信号线相连接。第二栅极和第二沟道中的至少之一为环绕型结构；第二栅极环绕第二沟道，或者第二沟道环绕第二栅极。
根据一些实施例，第二沟道沿垂直衬底的方向的两端分别与存储栅极、第二写入信号线相连接。第二栅极环绕设置于第二沟道的侧壁上。
根据一些实施例，第二沟道在衬底上正投影的几何中心与存储栅极在衬底上正投影的几何中心重合或近似重合。第二沟道在衬底上正投影的外轮廓与存储栅极在衬底上正投影的外轮廓之间重合或具有间隔，且所述间隔小于或等于第一阈值。
根据一些实施例，第二栅极位于第二沟道背离存储栅极的一侧。第二沟道环绕第二栅极的至少部分侧壁。
根据一些实施例，第二栅极还位于第二写入信号线背离衬底的一侧。
根据一些实施例，第二写入信号线与第二读取信号线相连接。
根据一些实施例，存储单元的数量为多个。多个存储单元沿垂直衬底的方向堆叠形成不同层。位于同一层的多个存储单元沿第一方向排布成行，沿第二方向排布成列，其中，第一方向和第二方向平行于衬底且相交。第一读取信号线和第一写入信号线沿第一方向延伸，第二读取信号线和第二写入信号线沿第二方向延伸。
根据一些实施例，任一列存储单元中的第一沟道串联分布，且各存储单元的第一沟道依次连接为一体结构。
根据一些实施例，多列存储单元对应分布有多条半导体走线；其中，第一沟道为半导体走线位于沟道区域的部分，与所述第一沟道相连接的第二读取信号线包括半导体走线位于连接区域的部分。
根据一些实施例，第二读取信号线还包括：层叠于半导体走线一侧且位于连接区域的金属走线。
根据一些实施例，存储器还包括：位于第一沟道和第一栅极之间的第一绝缘层，以及位于第一沟道和存储栅极之间的第二绝缘层。
根据一些实施例，第一沟道的材料包括多晶硅或金属氧化物半导体。第二沟道的材料包括金属氧化物半导体。
根据一些实施例，多行存储单元对应分布有多条第一金属线以及多条第二金属线。第一栅极与相 连接的第一读取信号线分别为同一第一金属线位于不同区域的部分。第二栅极与相连接的第一写入信号线分别为同一第二金属线位于不同区域的部分。
根据一些实施例，本公开另一方面提供了一种存储器的制造方法，用于制造如上一些实施例所述的存储器。所述制造方法包括如下步骤：
提供衬底。于衬底上形成第一栅极，以及与第一栅极相连接的第一读取信号线。
于第一栅极背离衬底的一侧形成第一沟道及与第一沟道相连接的第二读取信号线。
于第一沟道背离第一栅极的一侧形成存储栅极。
于存储栅极背离衬底的一侧分别形成第二沟道和第二栅极，以及与第二栅极相连接的第一写入信号线，与第二沟道相连接的第二写入信号线；其中，第二沟道与存储栅极相连接，第二栅极和第二沟道中的至少之一为环绕型结构；第二栅极环绕第二沟道，或者第二沟道环绕第二栅极。
由上，第一栅极、第一沟道及存储栅极共同构成第一晶体管；第二沟道及第二栅极共同构成第二晶体管；第一晶体管及第二晶体管共同构成存储单元。
根据一些实施例，所述于衬底上形成第一栅极，以及与第一栅极相连接的第一读取信号线，包括如下步骤。
于衬底内形成沿第一方向延伸的第一沟槽。
于第一沟槽内填充导电材料，形成第一栅极及第一读取信号线。
根据一些实施例，所述于第一栅极背离衬底的一侧形成第一沟道及与第一沟道相连接的第二读取信号线，包括如下步骤。
形成金属走线，金属走线位于沿列方向排布的相邻第一栅极之间并与第一栅极绝缘。
于金属走线背离衬底的表面以及第一栅极背离衬底的一侧形成半导体层。
图案化半导体层，形成半导体走线。半导体走线位于沟道区域的部分形成第一沟道。半导体走线覆盖金属走线的部分与金属走线共同构成第二读取信号线。
根据一些实施例，所述于第一栅极背离衬底的一侧形成第一沟道及与第一沟道相连接的第二读取信号线之前，所述制造方法还包括：形成覆盖第一栅极的第一绝缘层。
所述于第一栅极背离衬底的一侧形成第一沟道及与第一沟道相连接的第二读取信号线之后，所述于第一沟道背离第一栅极的一侧形成存储栅极之前，所述制造方法还包括：形成覆盖第一沟道及第二读取信号线的第二绝缘层。存储栅极形成于第二绝缘层背离第一沟道的表面。
根据一些实施例，所述于存储栅极背离衬底的一侧分别形成第二沟道和第二栅极，以及与第二栅极相连接的第一写入信号线，与第二沟道相连接的第二写入信号线，包括如下步骤。
形成覆盖存储栅极的第一介质层。
形成覆盖第一介质层的导电层，并图案化导电层，形成导电初始结构并暴露出部分第一介质层。
形成覆盖导电初始结构及第一介质层的第二介质层。
于第二介质层、导电初始结构及第一介质层中形成沟道孔；沟道孔的轴心线垂直于衬底，沟道孔暴露出存储栅极；导电初始结构位于沟道孔外侧的部分分别形成第二栅极及第一写入信号线。
形成覆盖沟道孔内侧壁的第三绝缘层。
于沟道孔内形成覆盖第三绝缘层且与存储栅极接触的第二沟道。
于第二沟道背离存储栅极的表面形成第二写入信号线。
根据一些实施例，所述于存储栅极背离衬底的一侧分别形成第二沟道和第二栅极，以及与第二栅极相连接的第一写入信号线，与第二沟道相连接的第二写入信号线，包括如下步骤。
形成覆盖存储栅极的第一介质层。于第一介质层内形成沿第二方向延伸的第二沟槽。
于第二沟槽内形成第二写入信号线。
形成贯穿第二写入信号线及第一介质层的沟道孔；沟道孔的轴心线垂直于衬底，沟道孔暴露出存储栅极。
于沟道孔的侧壁及底部形成第二沟道。形成覆盖第二沟道及第二写入信号线的第三绝缘层。
于第三绝缘层背离第二沟道的表面形成第二栅极及第一写入信号线，其中，至少部分第二栅极还 位于沟道孔内。
根据一些实施例，本公开又一方面提供了一种存储器，包括：
在平行于衬底的平面内，沿着第一方向延伸的第一字线，沿着第二方向延伸的第一位线；沿着第一方向或第二方向延伸的第二字线或第二位线，所述第一方向和所述第二方向交叉设置；
所述第一字线、第一位线、第二字线在垂直衬底的第三方向上依次间隔设置；或者，所述第一字线、第一位线、第二位线在垂直衬底的第三方向上依次间隔设置；
所述第一字线、第一位线交叉设置形成交叉点，所述交叉点设置有存储单元，所述存储单元包含叠置于衬底上的第一晶体管和第二晶体管；
所述第一晶体管包含第一栅极、存储栅极、第一半导体层；
所述第二晶体管包含第二栅极、第二半导体层；
所述第一栅极为所述第一字线在所述交叉点区域的部分；
所述第一半导体层为所述第一位线在所述交叉点区域的部分；
所述存储栅极位于所述第一半导体层上方的所述交叉点区域，与所述第一半导体层通过电介质层隔离；所述第二栅极和第二半导体层位于所述交叉点区域。
根据一些实施例，衬底为含有硅的衬底，第一字线至少部分埋入衬底中；第一字线的侧壁包裹有与衬底相隔离的第一绝缘层；第一位线为与衬底叠层设置的多晶硅层。
根据一些实施例，第一位线的多晶硅层与衬底之间还设置有导电膜层；导电膜层的图案与第一位线的图案相对应；导电膜层上具有开口，第一字线的顶部位于所述开口并通过第一绝缘层与多晶硅层接触。
根据一些实施例，导电膜层是通过含硅的衬底进行外延工艺形成，或者导电膜层为含有金属的膜层。
根据一些实施例，本公开又一方面提供了一种电子设备，包括如上一些实施例中所述的存储器。
根据一些实施例，所述电子设备包括智能电话、计算机、平板电脑、人工智能、可穿戴设备或智能移动终端。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为一实施例中提供的一种存储器的结构示意图；
图2为图1所示存储器中存储单元的等效电路图；
图3为一实施例中提供的另一种存储器的结构示意图；
图4为一实施例中提供的另一种存储器的结构示意图；
图5为图4所示存储器中存储单元的等效电路图；
图6为一实施例中提供的又一种存储器的结构示意图；
图7为一实施例中提供的一种存储器的电路示意图；
图8为一实施例中提供的又一种存储器的结构示意图；
图9为一实施例中提供的一种存储器的制造方法的流程示意图；
图10为一实施例中提供的一种第一栅极及第一读取信号线的制造步骤的流程示意图；
图11为一实施例中提供的一种形成第一绝缘层后所得结构的结构示意图；
图12为一实施例中提供的一种形成第一沟道及第二读取信号线后所得结构的结构示意图；
图13为一实施例中提供的另一种形成第一沟道及第二读取信号线后所得结构的结构示意图；
图14为一实施例中提供的另一种存储器的制造方法的流程示意图；
图15为一实施例中提供的一种形成存储栅极后所得结构的结构示意图；
图16为一实施例中提供的另一种形成存储栅极后所得结构的结构示意图；
图17为一实施例中提供的一种存储栅极、第一读取信号线及第二读取信号线之间相对位置分布的俯视示意图；
图18为一实施例中提供的一种第二晶体管的制造步骤的流程示意图；
图19为图18所示制造步骤中所得结构的结构示意图；
图20为一实施例中提供的一种第二沟道、第二栅极及第一写入信号线之间相对位置分布，以及第二写入信号线与第二沟道、第一写入信号线之间相对位置分布的俯视示意图；
图21为一实施例中提供的另一种第二晶体管的制造步骤的流程示意图；
图22为图21所示制造步骤中所得结构的结构示意图；
图23为一实施例中提供的一种衬底及第一字线、第一位线的结构示意图；
图24为一实施例中提供的另一种衬底及第一字线、第一位线的结构示意图；
图25为一实施例中提供的一种电子设备的结构示意图。
具体实施方式
为了便于理解本公开，下面将参照相关附图对本公开进行更全面的描述。附图中给出了本公开的实施例。但是，本公开可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使本公开的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中在本公开的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本公开。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦接”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦接到”其它元件或层时，则不存在居间的元件或层。
空间关系术语例如“在...下”、“在...下方”、“下面的”、“在...之下”、“在...之上”、“上方的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下方”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应当理解的是，术语“包括/包含”或“具有”等指定所陈述的特征、整体、步骤、操作、组件、部分或它们的组合的存在，但是不排除存在或添加一个或更多个其他特征、整体、步骤、操作、组件、部分或它们的组合的可能性。同时，在本说明书中，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本公开的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例，这样可以预期由于例如制造技术和/或容差导致的所示形状的变化。因此，本公开的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造技术导致的形状偏差。图中显示的区实质上是示意性的，它们的形状并不表示器件的区的实际形状，且并不限定本公开的范围。
NAND闪存作为一种非易失性存储器，可以采用三维结构以具有更高的存储密度和更低的成本，已成为存储技术领域的重要发展趋势之一。NAND闪存的基本存储单元为存储晶体管。该存储晶体管包括设置于控制栅极和源/漏极之间的浮动栅极或电荷捕获层。通过向存储晶体管的控制栅极及导电沟道施加高压(例如20V)，可以基于F-N隧穿原理或热注入原理对浮动栅极进行电荷注入或电荷释放，从而实现数据的存储。然而，基于F-N隧穿或热注入形成的电流很小，NAND闪存的编程速度和擦除速度均较低。
基于此，本公开一些实施例提供了一种存储器。请参阅图1，存储器包括：衬底10以及设置于衬 底10上的一个或多个存储单元SU。多个存储单元SU可以排布为一层，或沿垂直衬底的方向堆叠为多层。
示例性地，在含有多层存储单元SU的实施例中，每层中的存储单元SU之间的相对位置可以为阵列分布或蜂窝状分布，或其他造型的分布。此处，蜂窝状分布可以理解为多行存储单元SU，以及相邻行存储单元SU之间错位分布使得一列存储单元SU的每个存储单元SU的几何中心不在一个直线上，即不构成阵列分布。蜂窝状分布仅用于说明存储单元SU的几何中心的相对位置，并不限定存储单元SU本身的外轮廓形状。
示例性地，存储单元SU可以理解为逻辑电路上的存储单元，如，1T1C作为一个存储单元，或2T0C作为一个存储单元SU，并不限定存储单元SU的布线特点或形状构造上的特点。
图1示出了一种存储器纵截面的结构示意图，可以对存储单元SU中第一晶体管T1和第二晶体管T2的结构进行清楚示意。图1示出2T0C存储单元的实施例。
请参阅图1和图2，存储单元包含用于读数据的第一晶体管T1和用于写数据的第二晶体管T2，二者至下而上堆叠设置。存储器还包括：与存储单元SU对应设置的第一读取信号线L R1、第二读取信号线L R2、第一写入信号线L W1和第二写入信号线L W2。
以阵列分布于同一层的存储单元SU为例说明其中一个存储单元SU。参见图1，该纵截面示意图中示出了4个存储单元SU。如图1所示，存储单元SU包括：位于衬底10上的第一晶体管T1以及位于第一晶体管T1背离衬底10一侧的第二晶体管T2。
第一晶体管T1包括：第一栅极11、第一沟道12和存储栅极13。第一栅极11设置于衬底10上，与第一读取信号线L R1相连接。第一沟道12位于第一栅极11背离衬底10的一侧，与第二读取信号线L R2相连接。存储栅极13位于第一沟道12背离第一栅极11的一侧。即，第一晶体管T1的栅极、沟道以及存储栅极(也称背栅)在垂直衬底的方向上依次叠层设置。
第二晶体管T2包括：第二沟道21和第二栅极22。第二沟道21和第二栅极22位于存储栅极13背离衬底10的表面，并分别与存储栅极13、第二写入信号线L W2相连接。第二栅极22与第一写入信号线L W1相连接。第二栅极22和第二沟道21中的至少之一为环绕型结构；第二栅极22环绕第二沟道21，或者第二沟道21环绕第二栅极22。具体的，一些实施例中，第二栅极为环栅结构，环绕第二沟道的侧壁，所述第二沟道的侧壁大约垂直衬底。另一些实施例中，第二沟道为环绕型沟道，环绕所述第二栅极的侧壁，所述第二栅极的侧壁大约垂直所述衬底。
此处，第一沟道12与第一栅极11、存储栅极13分别绝缘。第二沟道21与第二栅极22绝缘。第一沟道12和第二沟道22可以分别由对应半导体层位于对应栅极的部分构成。多个存储单元SU的第一读取信号线L R1、第二读取信号线L R2、第一写入信号线L W1和第二写入信号线L W2可以共用，但是每个存储单元SU对应的存储栅极13是相互独立的，不共用或不相连。
比如，同一列存储单元的第一读取信号线L R1共用。
示例地，衬底10可以采用半导体材料、绝缘材料、导体材料或者它们的材料种类的任意组合构成。衬底10可以为单层结构，也可以为多层结构。例如，衬底10可以是诸如硅(Si)衬底、硅锗(SiGe)衬底、硅锗碳(SiGeC)衬底、碳化硅(SiC)衬底、砷化镓(GaAs)衬底、砷化铟(InAs)衬底、磷化铟(InP)衬底或其它的III/V半导体衬底或II/VI半导体衬底。或者，还例如，衬底10可以是包括诸如Si和SiGe的叠层、Si和SiC的叠层、绝缘体上硅(SOI)或绝缘体上硅锗的层状衬底等。
在一些示例中，衬底10为绝缘衬底。第一栅极11设置于衬底10上，包括但不限于：第一栅极11设置于衬底10内；即：第一栅极11采用埋置结构。
请结合图1～图3理解，在本公开实施例提供的存储器中，其中一个实施例为：存储单元SU由第一晶体管T1和第二晶体管T2共同构成的2T0C结构。第一晶体管T1采用了双栅结构，即包括第一栅极11和存储栅极13；其中，第一栅极11用于控制第一晶体管T1的通断，存储栅极13用于存储或释放电荷。存储栅极13位于第一沟道12背离第一栅极11的一侧，存储栅极13通过第二晶体管与第二写入信号线L W2相连接。通过第二写入信号线L W2可以向存储栅极13写入高电平或低电平，或输入不同的电平等，以实现数据存储或擦除。
此处，基于第一栅极11与第一读取信号线L R1相连接，第一沟道12与第二读取信号线L R2相连接，第二栅极22与第一写入信号线L W1相连接。
在附图1-3所示的实施例中，第一读取信号线L R1、第二读取信号线L R2、第一写入信号线L W1分别为条形，第一栅极11为第一读取信号线L R1的一部分，第一沟道12为第二读取信号线L R2的一部分，因此，在栅极上截图的截面图中，第一栅极11与第一读取信号线L R1标注在相同的位置。第一沟道12为第二读取信号线L R2的附图标记也是类似，此处不赘述。比如，图1中的第一栅极11与第一读取信号线L R1标注了同一层结构，第一沟道12与第二读取信号线L R2标注了同一层结构，第二栅极22与第一写入信号线L W1标注了同一层结构。
上述存储栅极13与第一沟道12以及二者之间的电介质层，可以等效为电容器，对应如图2所示的逻辑电路中的存储电容C BG，当然，该存储栅极13可以与任何一个相邻的与存储栅极13有正对关系的电极之间形成存储电容，或作为存储电容的一部分。与相关技术中存储器的浮动栅极或电荷捕获层相类似，本公开实施例中的存储单元SU可以通过改变存储栅极13的电位，实现数据的存储及擦除。并且，与相关技术中采用F-N隧穿或热注入的方式对浮动栅极进行电荷注入或电荷释放相比，本公开实施例中的存储单元SU可以直接将数据写入存储栅极13中，从而具有更快的编程速度和擦除速度。例如，本公开实施例中存储器的编程速度(例如数据写入或数据读取速度)及擦除速度可以从微秒级别提升至纳秒级别。
值得一提的是，本公开实施例中，存储单元SU的写操作和读操作可以分开进行。
在对目标存储单元SU执行写操作时，通过选择与第二晶体管T2相连接的第一写入信号线L W1传输控制电压，选择与第二晶体管T2相连接的第二写入信号线L W2传输数据电压，便可以在控制第二晶体管T2导通后将数据电压直接写入存储栅极13，从而容易地完成写操作，以具有更快的速度。在该阶段，第一晶体管T1保持关闭或开启。
在对目标存储单元SU执行读操作时，关闭第二晶体管T2。若存储栅极13存储高电平(例如数据1)，通过第一读取信号线L R1向第一栅极11施加第一控制电压，便可以打开第一晶体管T1，以通过第二读取信号线L R2传输的电流读取数据。若存储栅极13存储低电平(例如数据0)，通过第一读取信号线L R1向第一栅极11施加第二控制电压，便可以关闭第一晶体管T1。示例地，第一读取信号线L R1向第一栅极11施加的第一控制电压和第二控制电压可以相同。
此外，在一些示例中，存储单元SU还会被执行擦除操作(即刷新操作)，该擦除操作和写操作类似，二者仅是传输至存储栅极13的信号不同，此处不再详述。
请继续参阅图1和图2，在一些实施例中，第一读取信号线L R1可以为读取字线WL_r，第二读取信号线L R2可以为读取位线BL_r，第一写入信号线L W1可以为写入字线WL_w，第二写入信号线L W2可以为写入位线BL_w。但并不仅限于此，例如，第一写入信号线L W1可以为写入位线BL_w，第二写入信号线L W2可以为写入字线WL_w。
请继续参阅图1，在一些实施例中，存储器还包括：位于第一沟道12和第一栅极11之间的第一绝缘层31，以及位于第一沟道12和存储栅极13之间的第二绝缘层32。如此，利用第一绝缘层31和第二绝缘层32，可以有效降低漏电流，并确保第一晶体管T1的器件可靠性，包括确保存储栅极13的存储可靠性。
示例地，第二绝缘层32可以为高k介电层，介电常数大于3.9。
k指的是介电常数，衡量材料储存电荷能力。按介电常数的高低分为低介电(low-k)材料和高介电(high-k)材料。一般low-k材料介电常数低于3.0；high-k材料是相对于SiO2而言，只要介电常数大于SiO2的介电常数3.9，一般都称为high-k材料。
一般的，存储栅极13与第一沟道12之间的第二绝缘层32为high-k介质，但是第一栅极和第一沟道之间的介质可以为常规的栅极绝缘层，第二栅极与第二沟道之间的栅极可以为常规的栅极绝缘层，不必须是高k材料。
示例地，第一绝缘层31或第二绝缘层32的材料包括：氧化铝(Al 2O 3)、氧化铪(HfO 2)、氮氧化铪(HfON)、氧化锆(ZrO 2)、氧化钽(Ta 2O 5)、氧化钛(TiO 2)或锶钛氧化物(SrTiO 3)中的至 少一种。
在一些实施例中，第二晶体管T2采用低漏电流晶体管，以增加存储电极13上浮动电位(或电荷)的停留时间，从而有利于提升存储单元SU的性能。示例性地，第二沟道21的材料包括金属氧化物半导体。例如，第一晶体管T1为多晶硅晶体管，第二晶体管为金属氧化物晶体管。示例性地，第二晶体管T2的第二沟道21的材料包括铟、镓、锌或锡中至少一种的金属氧化物半导体，例如为铟镓锌氧化物(Indium Gallium Zinc Oxide，简称IGZO)或氧化铟锡(Indium Tin Oxide，简称ITO)；也即，第二晶体管T2的第二沟道21可以采用IGZO或ITO形成，以利于降低第二晶体管T2的漏电流，并确保第二晶体管T2的器件可靠性。但并不仅限于此。
需要说明的是，本公开实施例中，第二晶体管T2采用第二沟道21，第二晶体管T2例如可以采用全环绕型栅极结构，或者可以采用全环绕型沟道结构。从而有利于提高存储单元SU的分布密度，也即提高存储器的存储密度。
基于此，第二栅极22与第二沟道21之间的相对设置，可以有多种不同的实现方式。并且，可以理解，第二沟道21与第二栅极22之间通常还可以设有第三绝缘层33(例如图1中所示)。
在一些示例中，请参阅图1，第二晶体管T2采用了全环绕型栅极结构。第二沟道21沿垂直所述衬底的方向(例如Z方向)的两端分别与存储栅极13、第二写入信号线L W2相连接。第二栅极22环绕设置于第二沟道21的侧壁上；即，第二栅极22可以设置于第二沟道21的周侧。
此处，第二沟道21沿垂直衬底10的方向(例如Z方向)的两端分别与存储栅极13、第二写入信号线L W2相连接，并不仅限于第二沟道21沿垂直所述衬底的方向两端的端面分别与存储栅极13、第二写入信号线L W2相连接，还包括第二沟道21沿垂直所述衬底的方向两端侧壁分别与存储栅极13、第二写入信号线L W2相连接的情况。或者，仅第二沟道21沿垂直所述衬底的方向两端侧壁分别与存储栅极13、第二写入信号线L W2相连接的情况。
上述存储栅极13在衬底10上的位置分布，可以用于限定存储单元SU在衬底10上的位置分布。在一种可能的实施方式中，第二沟道21在衬底10上正投影的几何中心与存储栅极13在衬底10上正投影的几何中心重合或近似重合。第二沟道21在衬底10上正投影的外轮廓与存储栅极13在衬底10上正投影的外轮廓之间重合或具有间隔，且所述间隔小于或等于第一阈值。该第一阈值可以根据实际需求选择设置，本公开实施例对此不作限定。如此，有利于进一步提升存储单元SU的分布密度。
在另一些示例中，请参阅图3，第二晶体管T2采用了全环绕型沟道结构。第二沟道21环绕第二栅极22的至少部分侧壁，或者可以进一步环绕栅极的底部。当所述第二沟道21环绕第二栅极22的底部时，存储栅极可以与第二沟道21直接连接。
第二栅极22与第二沟道21之间形成第三绝缘层33。
此外，示例性地，请继续参阅图3，第二写入信号线L W2与第二沟道21的外侧壁顶部相连接。第二栅极22还位于第二写入信号线L W2背离衬底10的一侧。例如，第三绝缘层33还覆盖第二写入信号线L W2背离衬底10的表面，第二栅极22形成于第三绝缘层33表面。
需要补充的是，在一些实施例中，请参阅图4和图5，第二写入信号线L W2可以与第二读取信号线L R2相连接。即，第二写入信号线L W2可以与对应的第二读取信号线L R2连接为同一条数据线，例如位线BL。示例地，如图4中所示，第二写入信号线L W2可以通过连接线6与对应的第二读取信号线L R2相连接。示例地，第二写入信号线L W2可以与对应的第二读取信号线L R2连接至同一信号端。从而有利于减少快闪存储器中阵列区域的存储单元SU之间的总信号线的数量，以利于简化外围电路的布线结构。
一种实施方式中，在存储器中，各信号线(包括第一读取信号线L R1、第二读取信号线L R2、第一写入信号线L W1和第二写入信号线L W2)均可以引出至衬底10的边缘区域，并采用台阶布线实现其电性连接。本公开实施例对各信号线的引出连接不作详述，根据实际需求选择设置即可。
在一些实施例中，第二栅极22与第一写入信号线L W1同层设置且一体成型，即第二栅极22可以与第一写入信号线L W1采用相同导电材料并通过一次构图工艺图案化形成，以利于简化存储器的生产工艺。示例性地，第二栅极22与第一写入信号线L W1的材料包括金属，例如钨金属或铜金属。
在一些实施例中，第一栅极11与第一读取信号线L R1同层设置且一体成型，即第一栅极11可以与第一读取信号线L R1采用相同导电材料并通过一次构图工艺图案化形成，以利于简化存储器的生产工艺。示例性地，第一栅极11与第一读取信号线L R1的材料包括金属，例如钨金属或铜金属。
进一步的，第一栅极11为第一读取信号线L R1的一部分。
示例性地，多行存储单元SU对应分布有多条第一金属线以及多条第二金属线。第一栅极11与相连接的第一读取信号线L R1分别为同一第一金属线位于不同区域的部分。第二栅极22与相连接的第一写入信号线L W1分别为同一第二金属线位于不同区域的部分。如此，可以确保第一栅极11与相连接的第一读取信号线L R1呈线性设置，第二栅极22与相连接的第一写入信号线L W1呈线性设置，从而利于实现第二晶体管T2与第一晶体管T1的组合堆叠，并有效提高空间利用率。
在一些实施例中，第一晶体管T1中第一沟道12的材料包括多晶硅或金属氧化物半导体。金属氧化物半导体例如为铟镓锌氧化物(Indium Gallium Zinc Oxide，简称IGZO)或氧化铟锡(Indium Tin Oxide，简称ITO)，但并不仅限于此。
在一些实施方式中，如图1、图3和图4中所示，第一晶体管T1中第一沟道12的材料为多晶硅。第一沟道12与第二读取信号线L R2同层设置且一体成型。即，第一沟道12可以与第二读取信号线L R2采用多晶硅材料并通过一次构图工艺图案化形成，以利于简化存储器的生产工艺。
第一沟道12为第二读取信号线L R2的一部分。
示例地，多列存储单元SU对应分布有多条半导体走线；其中，第一沟道12为半导体走线位于沟道区域的部分，与第一沟道12相连接的第二读取信号线L R2包括半导体走线位于连接区域的部分。半导体走线例如为多晶硅条形走线。
此处，匹配第二读取信号线L R2的延伸方向，连接区域例如可以位于同列相邻的第一沟道12之间。
在另一些实施方式中，如图6中所示，第二读取信号线L R2包括半导体走线位于连接区域的部分L R21，且第二读取信号线L R2还包括：层叠于半导体走线一侧且位于连接区域的金属走线L R22。
示例地，半导体走线为IGZO条形走线。第二读取信号线L R2由半导体走线位于连接区域的部分L R21以及层叠的金属走线L R22共同构成。如此，可以利用金属走线L R22降低第二读取信号线L R2的电阻，以利于提高存储单元SU的读取速度。
此外，示例性地，请继续参阅图6，金属走线L R22位于半导体走线位于连接区域部分L R21靠近衬底10的一侧表面。
请结合图1、图3、图4和图6理解，存储器的各导电元件之间通常还设有介质层用于绝缘隔离。例如，存储器还包括：覆盖存储栅极13且用于隔离相邻存储栅极13及相邻第二沟道21底部之间的第一介质层4，和/或，覆盖第二栅极21且用于隔离相邻第二栅极21及相邻第二沟道21顶部之间的第二介质层5等。
此处，第一介质层4和第二介质层5的层数及设置位置，可以根据存储器的制造工艺适应性选择。示例性地，请参阅图4，第一介质层4可以包括：位于相邻存储栅极13之间的第一子层41和位于相邻第二沟道21底部之间的第二子层42。
此外，各层介质层可以选用氧化硅层、氮化硅层或氮氧化硅层等具备优良绝缘性能的薄膜。
需要说明的是，本公开实施例中，存储单元SU的数量为多个。多个存储单元SU沿垂直所述衬底的方向堆叠形成不同层。位于同一层的多个存储单元SU可以沿第一方向排布成行，沿第二方向排布成列；其中，第一方向和第二方向平行于衬底且相交。如此，本公开实施例中的存储器可以采用三维结构，以具有更高的存储密度及较低的每比特(Bit)成本。并且，本公开实施例中的存储器还可以采用多个阈值电压的多字节存储，以进一步降低每比特成本。
示例地，第一方向和第二方向垂直，第一方向例如为Y方向，第二方向例如为X方向。垂直衬底10的方向为Z方向。本公开实施例通过在Z方向堆叠存储单元SU，可以容易地获得三维存储器。
示例地，第一读取信号线L R1和第一写入信号线L W1沿第一方向(例如Y方向)延伸，第二读取信号线L R2和第二写入信号线L R2沿第二方向(例如X方向)延伸。
值得一提的是，本公开实施例中的存储器可以存储字符串，即可以通过串联为一组的存储单元SU 实现。请参阅图7，任一层的多个存储单元SU呈阵列排布，例如沿第一方向(即Y方向)排布成行，沿第二方向(即X方向)排布成列；此处，行与列仅是用于说明相对的方位，二者可以互换表达。以第一读取信号线L R1为读取字线WL_r，第二读取信号线L R2为读取位线BL_r，第一写入信号线L W1为写入字线WL_w，第二写入信号线L W2为写入位线BL_w为例，多个存储单元SU之间的等效电路图可以如图7中所示。
在任一层存储单元SU中，多个存储单元SU呈m×n的矩阵排列，m为行数，n为列数。任一列存储单元SU中的第一沟道12可以串联为一体结构，以实现该列存储单元SU的串联。存储单元SU例如可以以32个或64个为一组进行串联，即m＝32或m＝64。如此，任一组串联的存储单元SU沿列方向的两端可以分别设置选择晶体管，以通过该两个选择晶体管分别与源极线Source Line、第二读取信号线L R2(即读取位线BL_r)对应连接。如图7中所示，任一组串联的存储单元SU可以通过第一选择晶体管ST1与源极线Source Line相连接，通过第二选择晶体管ST2与第二读取信号线L R2相连接。并且，各组存储单元SU对应的第一选择晶体管ST1的栅极可以连接同一条第一选择信号线SSL，各组存储单元SU对应的第二选择晶体管ST2的栅极可以连接同一条第二选择信号线DSL。源极线Source Line可以向存储单元SU提供参考电压Vref。
此外，本公开实施例中存储器的逻辑页可以由同一行的存储单元SU实现。任一行存储单元SU中第一晶体管T1的第一栅极11可以连接同一条第一读取信号线L R1(即读取字线WL_r)，第二晶体管T2的第二栅极22可以连接同一条第一写入信号线L W1(即写入字线WL_w)。并且，本公开实施例中存储器中每一行的逻辑页数与存储单元SU的存储能力有关，即n可以根据存储单元SU的存储能力选择确定。
在此基础上，存储器的写操作和读操作可以采用如下方式进行。
上述写操作可以从下一行到上一行依次执行，例如从i-1行的存储单元SU到i行的存储单元SU依次执行，i≤m。在对目标行(例如i行)存储单元SU执行写操作时，则：关闭目标行以外(行数≠i)对应存储单元SU的各晶体管和目标行(行数＝i)中存储单元SU的第一晶体管T1；以及，对目标行(行数＝i)的写入字线WL_w提供高电平，对目标行以上(行数＞i)的写入字线WL_w提供低电平，对目标行(行数＝i)的写入位线BL_w提供数据电压。从而可以确保写入位线BL_w传输的数据电压写入目标行的存储单元SU中，从而完成写操作。
上述读操作可以对任一存储单元SU执行。在对目标存储单元SU执行读操作时，第一选择信号线SSL和第二选择信号线DSL均提供高电平，并对全部写入字线WL_w提供低电平，以关闭全部的第二晶体管T2；此时，若目标存储单元SU存储高电平(例如数据1)，通过读取字线WL_r向目标存储单元SU的第一栅极11施加第一控制电压，便可以打开第一晶体管T1，以通过读取位线BL_r传输的电流读取数据；若目标存储单元SU存储低电平(例如数据0)，通过读取字线WL_r向目标存储单元SU的第一栅极11施加第二控制电压，便可以关闭第一晶体管T1。示例地，读取字线WL_r向第一栅极11施加的第一控制电压和第二控制电压可以相同。
在一些示例中，第二写入信号线L W2与第二读取信号线L R2相连接，相应在对目标行(例如i行)存储单元SU执行写操作时，受限于第二读取信号线L R2的传输信号，前述写操作可以执行如下：对目标行以下(行数＜i)的所有字线(包括读取字线WL_r和写入字线WL_w)和第一选择信号线SSL提供低电平，以关闭对应存储单元SU的各晶体管；对目标行及以上(行数≥i)的读取字线WL_r提供高电平，以控制对应存储单元SU的第一晶体管T1导通；以及，对目标行(行数＝i)的写入字线WL_w提供高电平，对目标行以上(行数＞i)的写入字线WL_w提供低电平，对目标行(行数＝i)的写入位线BL_w提供数据电压。从而可以确保写入位线BL_w传输的数据电压写入目标行的存储单元SU中，从而完成写操作。
此外，在一些示例中，存储器还会被执行擦除操作(即刷新操作)，该擦除操作和写操作类似，二者仅是传输至存储单元SU中存储栅极13的信号不同，此处不再详述。
在一些实施例中，存储器采用了三维结构，即存储单元SU可以沿垂直衬底10的方向堆叠形成不同层。请参阅图8，本公开实施例示例性的给出了一种三维结构。沿垂直衬底10的方向(例如Z方向)， 多个存储单元SU依次排列为第一层存储单元SU1、第二层存储单元SU2及第三层存储单元SU3等；相应地，各信号线可以对应其所处的层数增加层数标识以作区分，例如L R11、L R12、L R13等。并且，相邻层的存储单元SU之间可以形成有隔离层；例如：第一层存储单元SU1和第二层存储单元SU2之间形成有第一隔离层71，第二层存储单元SU2和第三层存储单元SU3之间形成有第二隔离层72。如此，第一层存储单元SU1中的第一栅极11设置于衬底10内，第二层存储单元SU2中的第一栅极11可以设置于第一隔离层71内，第三层存储单元SU3中的第一栅极11可以设置于第二隔离层72内。
示例地，第一隔离层71及第二隔离层72的材料包括氧化硅或其他绝缘材料。
本公开实施例中，存储器采用如上结构，方便于在实现三维存储以提高存储密度的同时，简化存储器的制造工艺，以提高生产效率及生产良率。
请参阅图9，本公开另一方面提供了一种存储器的制造方法，用于制造如上一些实施例所述的存储器。所述制造方法包括如下步骤。
S100，提供衬底。
S200，于衬底上形成第一栅极，以及与第一栅极相连接的第一读取信号线。
S300，于第一栅极背离衬底的一侧形成第一沟道及与第一沟道相连接的第二读取信号线。
S400，于第一沟道背离第一栅极的一侧形成存储栅极。
S500，于存储栅极背离衬底的表面形成第二沟道和第二栅极，形成与第二栅极相连接的第一写入信号线。形成与第二沟道相连接的第二写入信号线。第二沟道与存储栅极相连接，第二栅极和第二沟道中的至少之一为环绕型结构；第二栅极环绕第二沟道，或者第二沟道环绕第二栅极。
由上，第一栅极、第一沟道及存储栅极共同构成第一晶体管；第二沟道及第二栅极共同构成第二晶体管；第一晶体管及第二晶体管共同构成存储单元。本公开实施例提供的制造方法用于制造前述一些实施例中的存储器，前述存储器所具备的优势，本公开实施例也均具备，此处不再详述。
请参阅图10和图11，在一些实施例，衬底10为绝缘衬底。步骤S200中于衬底上形成第一栅极，以及与第一栅极相连接的第一读取信号线，包括步骤S201和S202。
在步骤S201中，如图11中的(a)图所示，于衬底10内形成沿第一方向(例如Y方向)延伸的第一沟槽G1。此处，第一沟槽G1用于容置第一栅极11及第一读取信号线L R1。
在步骤S202中，如图11中的(b)图所示，于第一沟槽G内填充导电材料，形成第一栅极11及第一读取信号线L R1。此处，导电材料例如可以为掺杂多晶硅或导电金属。
此外，示例性地，请继续参阅图11中的(b)图，于衬底10及第一栅极11、第一读取信号线L R1的裸露表面形成第一绝缘层31。第一绝缘层31的材料可参见前述一些实施例中的相关描述，此处不再详述。
示例性地，请参阅图12，第一绝缘层31还可以有其他的形成方式，具体表现为：如图12中的(a)图所示，于衬底10内形成第一栅极11及第一读取信号线L R1；如图12中的(b)图所示，自上而下去除部分衬底10，以在相邻第一栅极11之间形成凹槽；如图12中的(c)图所示，形成覆盖第一栅极11裸露表面及形成凹槽后衬底10裸露表面的第一绝缘层31。
之后，示例性地，请参阅图12中的(d)图，于第一绝缘层31位于衬底10凹槽内部分的表面分别形成源极14和漏极15。源极14和漏极15填充前述凹槽，源极14和漏极15背离衬底10的表面可以与第一绝缘层31位于第一栅极11顶部部分的上表面平齐。如此，可以于源极14、漏极15及第一绝缘层31裸露表面形成平坦的半导体层，并图案化该半导体层，形成第一沟道12及第二读取信号线L R2。
在一些实施例，请参阅图13，第二读取信号线L R2包括层叠设置的半导体走线部分L R21和金属走线L R22，其中，金属走线L R22位于半导体走线部分L R21靠近衬底10的一侧。
示例性地，请参阅图14，执行步骤S300于第一栅极背离衬底的一侧形成第一沟道及与第一沟道相连接的第二读取信号线，包括步骤S310～S330。
S310，形成金属走线，金属走线位于沿列方向排布的相邻第一栅极之间并与第一栅极绝缘。
此处，如图13中所示，第一栅极11背离衬底10的表面形成有第一绝缘层31，金属走线L R22形成于第一绝缘层31的表面且填充相邻第一栅极11之间的凹槽。金属走线L R22背离衬底10的表面可以 与第一绝缘层31位于第一栅极11顶部部分的上表面平齐。
S320，于金属走线背离衬底的表面以及第一栅极背离衬底的一侧形成半导体层。
此处，结合步骤S310中金属走线L R22与第一绝缘层31之间的位置关系，半导体层还覆盖形成金属走线L R22之后第一绝缘层31的剩余裸露表面。
示例性地，半导体层的材料包括多晶硅或金属氧化物半导体。该金属氧化物半导体例如可以为IGZO或ITO等。
S330，图案化半导体层，形成半导体走线。半导体走线位于沟道区域的部分形成第一沟道。半导体走线覆盖金属走线的部分与金属走线共同构成第二读取信号线。
此处，如图13中所示，半导体走线例如为条形走线。半导体走线位于沟道区域的部分形成第一沟道12，半导体走线覆盖金属走线L R22的部分L R21和金属走线L R22层叠，可以共同构成第二读取信号线L R2，以利用金属走线L R22降低第二读取信号线L R2的电阻，从而提高存储单元SU的读取速度。
请参阅图14和图15，在一些实施例，执行步骤S300于第一栅极背离衬底的一侧形成第一沟道及与第一沟道相连接的第二读取信号线之前，所述制造方法还包括步骤S210。
S210，如图15中所示，形成覆盖第一栅极11的第一绝缘层31。
并且，执行步骤S300之后且执行步骤S400于第一沟道背离第一栅极的一侧形成存储栅极之前，所述制造方法还包括步骤S340。
S340，如图15中所示，形成覆盖第一沟道12及第二读取信号线L R2的第二绝缘层32。
相应地，步骤S400还可以表现为S400’，如图15中所示，于第二绝缘层32背离第一沟道12的表面形成存储栅极13。
本公开实施例中，利用第一绝缘层31和第二绝缘层32可以降低漏电流，并确保第一晶体管T1的器件可靠性。
示例地，第一绝缘层31或第二绝缘层32的介电常数大于3.9。
示例地，第一绝缘层31或第二绝缘层32的材料包括：氧化铝(Al 2O 3)、氧化铪(HfO 2)、氮氧化铪(HfON)、氧化锆(ZrO 2)、氧化钽(Ta 2O 5)、氧化钛(TiO 2)或锶钛氧化物(SrTiO 3)中的至少一种。
示例地，请结合图15理解，步骤S400中于第一沟道背离第一栅极的一侧形成存储栅极，可以包括：形成覆盖第二绝缘层32的存储栅极材料层；图案化存储栅极材料层，形成存储栅极13。
此处，存储栅极13在衬底10上的正投影与第一栅极11在衬底10上的正投影至少部分重叠。存储栅极13在衬底10上的位置分布用于定义存储单元SU在衬底10上的位置分布。
上述实施例中，存储栅极13可以通过先形成材料层再图案化的方式形成，但并不仅限于此。例如，请结合图16理解，步骤S400还可以表现为：形成覆盖第二绝缘层32的第一子介质层41，该第一子介质层41中具有图形，以用于界定存储栅极13的形成位置；在第一子介质层41的图形内填充存储栅极材料，以形成存储栅极13。示例性地，存储栅极13的材料包括钨金属或铜金属。
在形成存储栅极13之后，存储栅极13、第一读取信号线L R1及第二读取信号线L R2在衬底10上的正投影关系例如图17中所示。存储栅极13在衬底10上的位置分布，可以用于限定存储单元SU在衬底10上的位置分布，即限定存储单元SU的分布密度。第一读取信号线L R1沿第一方向(例如Y方向)延伸，多条第一读取信号线L R1平行间隔排布。第二读取信号线L R2沿第二方向(例如X方向)延伸，多条第二读取信号线L R2平行间隔排布。第一方向和第二方向相交，例如垂直。
需要说明的是，本公开实施例中，第二晶体管T2采用第二沟道21，第二晶体管T2例如可以采用全环绕型栅极结构，或者可以采用全环绕型沟道结构。从而有利于提高存储单元SU的分布密度，也即提高存储器的存储密度。基于此，第二栅极22与第二沟道21之间的相对设置，可以有多种不同的实现方式。也即，对应第二晶体管T2的不同结构，相应半导体结构的制造方法不同。
在一些实施例，请参阅图18，步骤S500中于存储栅极背离衬底的一侧分别形成第二沟道和第二栅极，形成与第二栅极相连接的第一写入信号线，以及形成与第二沟道相连接的第二写入信号线，包括如下步骤S501～S507。
S501，形成覆盖存储栅极的第一介质层。
S502，形成覆盖第一介质层的导电层，并图案化导电层，形成导电初始结构并暴露出部分第一介质层。
S503，形成覆盖导电初始结构及第一介质层的第二介质层。
S504，于第二介质层、导电初始结构及第一介质层中形成沟道孔；沟道孔的轴心线垂直于衬底，沟道孔暴露出存储栅极；导电初始结构位于沟道孔外侧的部分形成第二栅极及第一写入信号线。
S505，形成覆盖沟道孔内侧壁的第三绝缘层。
S506，于沟道孔内形成覆盖第三绝缘层且与存储栅极接触的第二沟道。
S507，于第二沟道背离存储栅极的表面形成第二写入信号线。
在步骤S501中，请参阅图19中的(a)图，形成覆盖存储栅极13的第一介质层4。存储栅极13形成于第二绝缘层32表面，第一介质层4还覆盖第二绝缘层32未被存储栅极13覆盖的表面。
在步骤S502中，请结合图19中的(a)图理解，形成覆盖第一介质层4的导电层，并图案化导电层，形成导电初始结构并暴露出部分第一介质层4。
在步骤S503中，请结合图19中的(a)图理解，形成覆盖导电初始结构及第一介质层4的第二介质层5。
在步骤S504中，请结合图19中的(a)图理解，于第二介质层5、导电初始结构及第一介质层4中形成沟道孔H；沟道孔H的轴心线垂直于衬底10，沟道孔H暴露出存储栅极13；导电初始结构位于沟道孔H外侧的部分形成第二栅极22及第一写入信号线L W1。
在步骤S505中，请参阅图19中的(b)图，形成覆盖沟道孔H内侧壁的第三绝缘层33。
此处，第三绝缘层33可以通过沉积介电薄膜的方式形成，例如采用原子层沉积(Atomic Layer Deposition，简称ALD)工艺形成。
在步骤S506中，请参阅图19中的(b)图，于沟道孔H内形成覆盖第三绝缘层33侧壁且与存储栅极12接触的第二沟道21。
此处，第二沟道21可以通过填充半导体材料的方式形成。该半导体材料例如为IGZO或ITO等金属氧化物半导体。
示例性地，半导体材料可以采用沉积工艺填充，包括但不限于原子层沉积(Atomic Layer Deposition，简称ALD)工艺或物理气相沉积(Physical Vapor Deposition，简称PVD)工艺。
在步骤S507中，请参阅图19中的(c)图，于第二沟道21背离存储栅极13的表面形成第二写入信号线L W2。
此处，结合前述一些实施例可知，在一些示例中，形成存储栅极13之前已制造了第一子介质层41，那么步骤S501中所形成的第一介质层4可以对应表现为：形成第二子介质层42，以由第二子介质层42和第一子介质层41共同构成第一介质层4。
此外，示例性地，第一介质层4和第二介质层5可以选用氧化硅层、氮化硅层或氮氧化硅层等具备优良绝缘性能的薄膜形成。示例性地，导电层可以为钨金属层或铜金属层。
在形成第二沟道21之后，第二沟道21、第二栅极22和第一写入信号线L W1在衬底10上的正投影关系例如图20中的(a)图所示。第二沟道21在衬底10上正投影的几何中心可以与存储栅极13在衬底1上正投影的几何中心重合或近似重合。并且，示例性地，第二沟道21在衬底10上正投影的外轮廓与存储栅极13在衬底10上正投影的外轮廓之间重合或具有间隔，且所述间隔小于或等于第一阈值。此外，第二栅极22环绕设置于第二沟道21的侧壁上。第一写入信号线L W1与第二栅极22连接并沿第一方向(例如Y方向)延伸，多条第一写入信号线L W1平行间隔排布。
在形成第二写入信号线L W2之后，第二写入信号线L W2与第二沟道21、第一写入信号线L W1在衬底10上的正投影关系例如图20中的(b)图所示。第二写入信号线L W1沿第二方向(例如X方向)延伸；第二方向与第一方向相交，例如垂直。多条第二写入信号线L W2平行间隔排布。第二沟道21在衬底10上的正投影位于对应第二写入信号线L W2在衬底10上的正投影范围内。
示例性地，第二写入信号线L W2可以通过对金属层执行模压工艺实现。该金属层可以为钨金属层 或铜金属层。
在另一些实施例，请参阅图21，步骤S500中于存储栅极背离衬底的一侧分别形成第二沟道和第二栅极，形成与第二栅极相连接的第一写入信号线，以及形成与第二沟道相连接的第二写入信号线，包括如下步骤S501’～S507’。
S501’，形成覆盖存储栅极的第一介质层。
S502’，于第一介质层内形成沿第二方向延伸的第二沟槽。
S503’，于第二沟槽内形成第二写入信号线。
S504’，形成贯穿第二写入信号线及第一介质层的沟道孔；沟道孔的轴心线垂直于衬底，沟道孔暴露出存储栅极。
S505’，于沟道孔的侧壁及底部形成第二沟道。
S506’，形成覆盖第二沟道及第二写入信号线的第三绝缘层。
S507’，于第三绝缘层背离第二沟道的表面形成第二栅极及第一写入信号线，其中，至少部分第二栅极还位于沟道孔内。
在步骤S501’中，请参阅图22中的(a)图，形成覆盖存储栅极13的第一介质层4。存储栅极13形成于第二绝缘层32表面，第一介质层4还覆盖第二绝缘层32未被存储栅极13覆盖的表面。
在步骤S502’和S503’中，请继续参阅图22中的(a)图，于第一介质层4内形成沿第二方向(例如X方向)延伸的第二沟槽(图中未示出)，并于第二沟槽内形成第二写入信号线L W2。
在步骤S504’中，请参阅图22中的(b)图，形成贯穿第二写入信号线L W2及第一介质层4的沟道孔H；沟道孔H的轴心线垂直于衬底10，沟道孔H暴露出存储栅极13。
在步骤S505’中，请参阅图22中的(c)图，于沟道孔H的侧壁及底部形成第二沟道21。
此处，第二沟道21可以通过于沟道孔H的侧壁及底部沉积半导体薄膜的方式形成。第二沟道21采用薄膜结构，可以使第二沟道21具有凹槽。该半导体薄膜例如为IGZO或ITO薄膜，可以采用原子层沉积(Atomic Layer Deposition，简称ALD)工艺形成。但并不仅限于此。
在步骤S506’中，请继续参阅图22中的(c)图，形成覆盖第二沟道21及第二写入信号线L W2的第三绝缘层33。
此处，第三绝缘层33可以通过沉积介电薄膜的方式形成，例如采用原子层沉积(Atomic Layer Deposition，简称ALD)工艺形成。
在步骤S507’中，请参阅图22中的(d)图，于第三绝缘层33背离第二沟道21的表面形成第二栅极22及第一写入信号线L W1。
此处，第一写入信号线L W1与第二栅极22为一体结构，可以沿第一方向(例如Y方向)延伸。第二栅极22可以填充第二沟道21的前述凹槽，并通过第三绝缘层33与第二沟道21隔离；即，至少部分第二栅极22还位于沟道孔H内。第二栅极22例如为T形栅极。
在一些实施例中，存储器可以采用了三维结构，即存储单元SU可以沿垂直衬底10的方向堆叠呈不同层。请结合图8理解，所述制造方法还包括：沿垂直衬底10的方向堆叠多层存储单元SU。
此处，任一层存储单元SU的制造可以参见前述一些实施例中存储单元SU的制造进行，不再赘述。并且，相邻层的存储单元SU之间可以形成有隔离层。如此，第一层以外其他层存储单元SU中的第一栅极11及第一读取信号线L R1可以形成于对应的隔离层中。
本公开实施例中，采用如上制造方法，方便于制造三维存储器，以在提高存储密度的同时简化存储器的制造工艺，从而提高生产效率及生产良率。
应该理解的是，虽然图18和图21的流程图中的各个步骤按照箭头的指示依次显示但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，其可以以其他的顺序执行。而且，图9、图10、图14、图18和图21中的至少部分步骤可以包括多个子步骤或者多个阶段，这些子步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，其执行顺序也不必然是依次进行，而是可以与其他步骤或者其他步骤的子步骤或者阶段的至少一部分轮流或者交替地执行。
本公开一些实施例还提供了一种存储器，包括：
在平行于衬底的平面内，沿着第一方向延伸的第一字线，沿着第二方向延伸的第一位线；沿着第一方向或第二方向延伸的第二字线或第二位线，所述第一方向和所述第二方向交叉设置；
所述第一字线、第一位线、第二字线在垂直衬底的第三方向上依次间隔设置；或者，所述第一字线、第一位线、第二位线在垂直衬底的第三方向上依次间隔设置；
所述第一字线、第一位线交叉设置形成交叉点，所述交叉点设置有存储单元，所述存储单元包含叠置于衬底上的第一晶体管和第二晶体管；
所述第一晶体管包含第一栅极、存储栅极、第一半导体层；
所述第二晶体管包含第二栅极、第二半导体层；
所述第一栅极为所述第一字线在所述交叉点区域的部分；
所述第一半导体层为所述第一位线在所述交叉点区域的部分；
所述存储栅极位于所述第一半导体层上方的所述交叉点区域，与所述第一半导体层通过电介质层隔离；所述第二栅极和第二半导体层位于所述交叉点区域。
可以理解，本公开实施例中，请参阅图1和图3，存储单元例如为前述一些实施例中的存储单元SU。第一字线例如为前述地第一读取信号线L R1，第一位线例如为前述的第二读取信号线L R2，第二字线例如为前述的第一写入信号线L W1，第二位线例如为前述的第二写入信号线L W2。如此，第一晶体管中的至少部分第一半导体层用于构成第一沟道12，第二晶体管中的至少部分第二半导体层用于构成第二沟道21。第一晶体管中存储栅极与第一半导体层中的电介质层例如为前述的第二绝缘层32。
在一些实施例中，请参阅图1，第一字线(即第一读取信号线L R1)沿第一方向(例如Y方向)延伸，第一位线(即第二读取信号线L R2)沿第二方向(例如X方向)延伸，第二字线(即第一写入信号线L W1)沿第一方向(例如Y方向)延伸，第二位线(即第二写入信号线L W2)沿第二方向(例如X方向)延伸。
在另一些实施例中，第一字线(即第一读取信号线L R1)和第一位线(即第二读取信号线L R2)的延伸方向保持不变，第二字线(即第一写入信号线L W1)沿第二方向(例如X方向)延伸，第二位线(即第二写入信号线L W2)沿第一方向(例如Y方向)延伸，也均是允许的。
在一些实施例中，请继续参阅图1，第一字线(即第一读取信号线L R1)、第一位线(即第二读取信号线L R2)、第二字线(即第一写入信号线L W1)在垂直衬底10的第三方向(例如Z方向)上依次间隔设置。例如，第一字线(即第一读取信号线L R1)与第一位线(即第二读取信号线L R2)之间设置有第一绝缘层31；第一位线(即第二读取信号线L R2)与第二字线(即第一写入信号线L W1)之间依次设置有第二绝缘层32及第一介质层4。本公开实施例中，第二晶体管T2例如可以采用如前一些实施例中所述的全环绕型栅极结构例如(Gate-All-Around，简称GAA)，此处不再详述。
在另一些实施例中，请参阅图3，第一字线(即第一读取信号线L R1)、第一位线(即第二读取信号线L R2)、第二位线(即第二写入信号线L W2)在垂直衬底10的第三方向(例如Z方向)上依次间隔设置。例如，第一字线(即第一读取信号线L R1)与第一位线(即第二读取信号线L R2)之间设置有第一绝缘层31；第一位线(即第二读取信号线L R2)与第二位线(即第二写入信号线L W2)之间依次设置有第二绝缘层32及第一介质层4。本公开实施例中，第二晶体管T2例如可以采用如前一些实施例中所述的全环绕型沟道结构例如(Channel-All-Around，简称CAA)，此处不再详述。
请结合图17理解，第一字线(即第一读取信号线L R1)、第一位线(即第二读取信号线L R2)交叉设置形成交叉点，所述交叉点设置有存储单元SU。示例地，第一栅极11为第一字线(即第一读取信号线L R1)在所述交叉点区域的部分；第一半导体层(例如第一沟道12)为第一位线(即第二读取信号线L R2)在所述交叉点区域的部分；存储栅极13位于第一半导体层上方的所述交叉点区域，以用于限定存储单元SU的形成位置。示例地，请参阅图20，第二栅极22和第二半导体层(例如第二沟道21)位于所述交叉点区域。
本公开实施例中，存储器采用如上结构，可以有效提高存储器内存储单元的分布密度，以实现存储器的高密度存储。
在一些实施例中，请参阅图23，衬底10为含有硅的衬底，第一字线(例如第一读取信号线L R1)至少部分埋入衬底10中。第一字线(例如第一读取信号线L R1)的侧壁包裹有与衬底10相隔离的第一绝缘层31；第一位线(例如第二读取信号线L R2)为与衬底10叠层设置的多晶硅层。
此处，第一绝缘层31可以为高K介电层，也可以为常规栅绝缘层或其他绝缘材料。第一字线(例如第一读取信号线L R1)的侧壁包括其顶壁和底壁。
在一些实施例中，请参阅图24，第一位线(例如第二读取信号线L R2)的多晶硅层与衬底10之间还设置有导电膜层L’；导电膜层L’的图案与第一位线的图案相对应；导电膜层L’上具有开口，第一字线的顶部位于所述开口并通过第一绝缘层31与多晶硅层接触。
在一些实施例，导电膜层L’是通过含硅的衬底10进行外延工艺形成，或者导电膜层L’为含有金属的膜层。
示例地，导电膜层L’为金属硅化物层，例如为硅化钴、硅化钛、硅化锆、硅化钽或硅化钨等。
示例地，导电膜层L’可以构成金属走线L R22，并与第一位线共同构成前述地第二读取信号线L R2，以有效降低第二读取信号线L R2的电阻。
本公开一些实施例提供了一种电子设备，包括智能电话、计算机、平板电脑、人工智能、可穿戴设备或智能移动终端。
例如数据存储设备、影印机、网络设备、家用电器、仪器仪表、手机、电脑等具备数据存储功能的设备。例如图22中所示，该电子设备100包括壳体1以及设置在壳体1内的电路板2、集成在电路板2上的存储器3。存储器3的结构可以参阅上述一些实施例中的相关描述。电子设备100中还可以包括其他必要的的元件或部件，本公开实施例对此不作限定。
在一些实施例中，与存储器3耦接的处理器或执行器等外部控制器件，也可以集成在电路板2上。例如，电子设备100还包括集成在电路板2上的处理器40。处理器40与存储器3耦接，处理器40能够控制存储器3的读写操作。
在一些实施例中，存储器3可以为快闪存储器，例如NAND闪存。
在本公开一些实施例中，电子设备100采用存储器3，能够在该存储器3为三维结构的情况下具有较好的数据存储能力。并且，存储器3采用上述一些实施例中的结构及制造方法制作，能够具有较高的编程速度及擦除速度和较高的生产良率，以有效优化存储器3的性能及可靠性，进而确保电子设备100具有较佳的性能及可靠性。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本公开的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本公开构思的前提下，还可以做出若干变形和改进，这些都属于本公开的保护范围。因此，本公开专利的保护范围应以所附权利要求为准。

Claims (25)

  1. 一种存储器，包括：衬底以及设置于所述衬底上的多个存储单元、第一读取信号线、第二读取信号线、第一写入信号线和第二写入信号线；所述存储单元包括：第一晶体管以及位于所述第一晶体管背离所述衬底一侧的第二晶体管；其中，
    所述第一晶体管包括：
    第一栅极，设置于所述衬底上，与所述第一读取信号线相连接；
    第一沟道，位于所述第一栅极背离所述衬底的一侧，与所述第二读取信号线相连接；
    存储栅极，位于所述第一沟道背离所述第一栅极的一侧；
    所述第二晶体管包括：
    第二沟道，位于所述存储栅极背离所述衬底的一侧，并分别与所述存储栅极、所述第二写入信号线相连接；
    第二栅极，与所述第一写入信号线相连接；所述第二栅极和所述第二沟道中的至少之一为环绕型结构；所述第二栅极环绕所述第二沟道，或者所述第二沟道环绕所述第二栅极。
  2. 根据权利要求1所述的存储器，其中，所述第二沟道沿垂直所述衬底的方向的两端分别与所述存储栅极、所述第二写入信号线相连接；所述第二栅极环绕设置于所述第二沟道的侧壁上。
  3. 根据权利要求2所述的存储器，其中，所述第二沟道在所述衬底上正投影的几何中心与所述存储栅极在所述衬底上正投影的几何中心重合或近似重合；所述第二沟道在所述衬底上正投影的外轮廓与所述存储栅极在所述衬底上正投影的外轮廓之间重合或具有间隔，且所述间隔小于或等于第一阈值。
  4. 根据权利要求1所述的存储器，其中，所述第二栅极位于所述第二沟道背离所述存储栅极的一侧，所述第二沟道环绕所述第二栅极的至少部分侧壁。
  5. 根据权利要求4所述的存储器，其中，所述第二栅极还位于所述第二写入信号线背离所述衬底的一侧。
  6. 根据权利要求1所述的存储器，其中，所述第二写入信号线与所述第二读取信号线相连接。
  7. 根据权利要求1所述的存储器，其中，所述存储单元的数量为多个；多个所述存储单元沿垂直所述衬底的方向堆叠形成不同层；
    位于同一层的多个所述存储单元沿第一方向排布成行，沿第二方向排布成列，其中，所述第一方向和所述第二方向平行于所述衬底且相交；
    所述第一读取信号线和所述第一写入信号线沿所述第一方向延伸；
    所述第二读取信号线和所述第二写入信号线沿所述第二方向延伸。
  8. 根据权利要求7所述的存储器，其中，任一列所述存储单元中的所述第一沟道串联分布，且各所述存储单元的所述第一沟道依次连接为一体结构。
  9. 根据权利要求8所述的存储器，其中，多列所述存储单元对应分布有多条半导体走线；
    其中，所述第一沟道为所述半导体走线位于沟道区域的部分，与所述第一沟道相连接的所述第二读取信号线包括同一所述半导体走线位于连接区域的部分。
  10. 根据权利要求9所述的存储器，其中，所述第二读取信号线还包括：层叠于所述半导体走线一侧且位于所述连接区域的金属走线。
  11. 根据权利要求1所述的存储器，其中，所述存储器还包括：位于所述第一沟道和所述第一栅极之间的第一绝缘层，以及位于所述第一沟道和所述存储栅极之间的第二绝缘层。
  12. 根据权利要求1所述的存储器，其中，所述第一沟道的材料包括多晶硅或金属氧化物半导体；所述第二沟道的材料包括金属氧化物半导体。
  13. 根据权利要求7所述的存储器，其中，多行所述存储单元对应分布有多条第一金属线以及多条第二金属线；
    所述第一栅极与相连接的所述第一读取信号线分别为同一所述第一金属线位于不同区域的部分；
    所述第二栅极与相连接的所述第一写入信号线分别为同一所述第二金属线位于不同区域的部分。
  14. 一种存储器的制造方法，包括：
    提供衬底；
    于所述衬底上形成第一栅极，以及与所述第一栅极相连接的第一读取信号线；
    于所述第一栅极背离所述衬底的一侧形成第一沟道及与所述第一沟道相连接的第二读取信号线；
    于所述第一沟道背离所述第一栅极的一侧形成存储栅极；
    于所述存储栅极背离所述衬底的一侧分别形成第二沟道和第二栅极，以及与所述第二栅极相连接的第一写入信号线，与所述第二沟道相连接的第二写入信号线；其中，所述第二沟道与所述存储栅极相连接，所述第二栅极和所述第二沟道中的至少之一为环绕型结构；所述第二栅极环绕所述第二沟道，或者所述第二沟道环绕所述第二栅极；
    其中，所述第一栅极、所述第一沟道及所述存储栅极共同构成第一晶体管；所述第二沟道及所述第二栅极共同构成第二晶体管；所述第一晶体管及所述第二晶体管共同构成存储单元。
  15. 根据权利要求14所述的存储器的制造方法，其中，所述于所述衬底上形成第一栅极，以及与所述第一栅极相连接的第一读取信号线，包括：
    于所述衬底内形成沿第一方向延伸的第一沟槽；
    于所述第一沟槽内填充导电材料，形成所述第一栅极及所述第一读取信号线。
  16. 根据权利要求14所述的存储器的制造方法，其中，所述于所述第一栅极背离所述衬底的一侧形成第一沟道及与所述第一沟道相连接的第二读取信号线，包括：
    形成金属走线，所述金属走线位于沿列方向排布的相邻所述第一栅极之间并与所述第一栅极绝缘；
    于所述金属走线背离所述衬底的表面以及所述第一栅极背离所述衬底的一侧形成半导体层；
    图案化所述半导体层，形成半导体走线；所述半导体走线位于沟道区域的部分形成所述第一沟道；所述半导体走线覆盖所述金属走线的部分与所述金属走线共同构成所述第二读取信号线。
  17. 根据权利要求14所述的存储器的制造方法，其中，
    所述于所述第一栅极背离所述衬底的一侧形成第一沟道及与所述第一沟道相连接的第二读取信号线之前，所述制造方法还包括：形成覆盖所述第一栅极的第一绝缘层；
    所述于所述第一栅极背离所述衬底的一侧形成第一沟道及与所述第一沟道相连接的第二读取信号线之后，所述于所述第一沟道背离所述第一栅极的一侧形成存储栅极之前，所述制造方法还包括：形成覆盖所述第一沟道及所述第二读取信号线的第二绝缘层；
    其中，所述存储栅极形成于所述第二绝缘层背离所述第一沟道的表面。
  18. 根据权利要求14所述的存储器的制造方法，其中，所述于所述存储栅极背离所述衬底的一侧分别形成第二沟道和第二栅极，以及与所述第二栅极相连接的第一写入信号线，与所述第二沟道相连接的第二写入信号线，包括：
    形成覆盖所述存储栅极的第一介质层；
    形成覆盖所述第一介质层的导电层，并图案化所述导电层，形成导电初始结构并暴露出部分所述第一介质层；
    形成覆盖所述导电初始结构及所述第一介质层的第二介质层；
    于所述第二介质层、所述导电初始结构及所述第一介质层中形成沟道孔；所述沟道孔的轴心线垂直于所述衬底，所述沟道孔暴露出所述存储栅极；所述导电初始结构位于所述沟道孔外侧的部分分别形成所述第二栅极及所述第一写入信号线；
    形成覆盖所述沟道孔内侧壁的第三绝缘层；
    于所述沟道孔内形成覆盖所述第三绝缘层且与所述存储栅极接触的所述第二沟道；
    于所述第二沟道背离所述存储栅极的表面形成所述第二写入信号线。
  19. 根据权利要求14所述的存储器的制造方法，其中，所述于所述存储栅极背离所述衬底的一侧分别形成第二沟道和第二栅极，以及与所述第二栅极相连接的第一写入信号线，与所述第二沟道相连接的第二写入信号线，包括：
    形成覆盖所述存储栅极的第一介质层；
    于所述第一介质层内形成沿第二方向延伸的第二沟槽；
    于所述第二沟槽内形成所述第二写入信号线；
    形成贯穿所述第二写入信号线及所述第一介质层的沟道孔；所述沟道孔的轴心线垂直于所述衬底，所述沟道孔暴露出所述存储栅极；
    于所述沟道孔的侧壁及底部形成第二沟道；
    形成覆盖所述第二沟道及所述第二写入信号线的第三绝缘层；
    于所述第三绝缘层背离所述第二沟道的表面形成所述第二栅极及所述第一写入信号线；其中，至少部分所述第二栅极还位于所述沟道孔内。
  20. 一种存储器，包括：
    在平行于衬底的平面内，沿着第一方向延伸的第一字线，沿着第二方向延伸的第一位线；沿着第一方向或第二方向延伸的第二字线或第二位线，所述第一方向和所述第二方向交叉设置；
    所述第一字线、第一位线、第二字线在垂直衬底的第三方向上依次间隔设置；或者，所述第一字线、第一位线、第二位线在垂直衬底的第三方向上依次间隔设置；
    所述第一字线、第一位线交叉设置形成交叉点，所述交叉点设置有存储单元，所述存储单元包含叠置于衬底上的第一晶体管和第二晶体管；
    所述第一晶体管包含第一栅极、存储栅极、第一半导体层；
    所述第二晶体管包含第二栅极、第二半导体层；
    所述第一栅极为所述第一字线在所述交叉点区域的部分；
    所述第一半导体层为所述第一位线在所述交叉点区域的部分；
    所述存储栅极位于所述第一半导体层上方的所述交叉点区域，与所述第一半导体层通过电介质层隔离；所述第二栅极和第二半导体层位于所述交叉点区域。
  21. 根据权利要求20所述的存储器，其中，所述衬底为含有硅的衬底，所述第一字线至少部分埋入所述衬底中；所述第一字线的侧壁包裹有与所述衬底相隔离的第一绝缘层；
    所述第一位线为与所述衬底叠层设置的多晶硅层。
  22. 根据权利要求21所述的存储器，其中，所述第一位线的多晶硅层与所述衬底之间还设置有导电膜层；所述导电膜层的图案与所述第一位线的图案相对应；所述导电膜层上具有开口，所述第一字线的顶部位于所述开口并通过所述第一绝缘层与所述多晶硅层接触。
  23. 根据权利要求22所述的存储器，其中，所述导电膜层是通过所述含硅的衬底进行外延工艺形成，或者所述导电膜层为含有金属的膜层。
  24. 一种电子设备，包括：如权利要求1～12中任一项所述的存储器，或者，如权利要求20～23中任一项所述的存储器。
  25. 根据权利要求24所述的电子设备，包括智能电话、计算机、平板电脑、人工智能、可穿戴设备或智能移动终端。
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