WO2024082381A1 - 存储单元、存储器和电子设备 - Google Patents

存储单元、存储器和电子设备 Download PDF

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Publication number
WO2024082381A1
WO2024082381A1 PCT/CN2022/134673 CN2022134673W WO2024082381A1 WO 2024082381 A1 WO2024082381 A1 WO 2024082381A1 CN 2022134673 W CN2022134673 W CN 2022134673W WO 2024082381 A1 WO2024082381 A1 WO 2024082381A1
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gate
memory cell
transistor
semiconductor layer
memory
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PCT/CN2022/134673
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English (en)
French (fr)
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戴瑾
朱正勇
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北京超弦存储器研究院
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Publication of WO2024082381A1 publication Critical patent/WO2024082381A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the embodiments of the present application relate to the field of semiconductor technology, and in particular to a storage unit, a memory, and an electronic device.
  • 3D NAND memory includes multiple storage units, and the application of two-transistor zero-capacitor (2T0C) storage unit is becoming more and more widespread.
  • 2T0C two-transistor zero-capacitor
  • the embodiments of the present application provide a storage unit, a memory and an electronic device, which can be used to reduce the size of the storage unit.
  • the technical solution is as follows:
  • an embodiment of the present application provides a memory cell, wherein the memory cell includes a first transistor and a second transistor arranged along a first direction; the first transistor includes a first gate, a first semiconductor layer, and a second gate arranged along the first direction, the first gate extends along a second direction, the first semiconductor layer extends along a third direction, the first direction and the third direction are two directions parallel to a substrate and perpendicular to each other, and the second direction is a direction perpendicular to the substrate; the second transistor includes a third gate and a second semiconductor layer surrounding the third gate, the third gate extends along the second direction, the second semiconductor layer includes a channel and a first electrode and a second electrode connected by the channel, and the second electrode is connected to the second gate.
  • the channel is a horizontal channel.
  • the second semiconductor layer has a first surface, a second surface, a third surface and a fourth surface perpendicular to the substrate, the first surface and the second surface of the second semiconductor layer are perpendicular to the first direction, the second surface of the second semiconductor layer is farther away from the first transistor than the first surface, and the third surface and the fourth surface of the second semiconductor layer are perpendicular to the third direction;
  • the second gate wraps the entire first surface of the second semiconductor layer and a portion of the third surface and the fourth surface of the second semiconductor layer close to the first transistor;
  • a first bit line wraps the entire second surface of the second semiconductor layer and a portion of the third surface and the fourth surface of the second semiconductor layer away from the first transistor.
  • first gate insulating layer between the first gate and the first semiconductor layer
  • second gate insulating layer between the first semiconductor layer and the second gate
  • the first gate, the first gate insulating layer, the first semiconductor layer, the second gate insulating layer and the second gate all have a first surface and a second surface perpendicular to the first direction, and the first surface of the same component is farther away from the second transistor than the second surface
  • the second surface of the first gate is attached to the first surface of the first gate insulating layer
  • the second surface of the first gate insulating layer is attached to the first surface of the first semiconductor layer
  • the second surface of the first semiconductor layer is attached to the first surface of the second gate insulating layer
  • the second surface of the second gate insulating layer is attached to the first surface of the second gate.
  • the material of the second semiconductor layer is a metal oxide semiconductor.
  • the second semiconductor layer has a first connection region connected to a first bit line, a second connection region connected to the second gate, and a gate control region other than the first connection region and the second connection region, and the conductivity of the gate control region is controlled by the third gate.
  • a memory which includes multiple memory cell layers, each memory cell layer includes multiple memory cells described in any one of the above, and the multiple memory cell layers are arranged along the second direction; each memory cell layer includes multiple memory cell columns arranged along the first direction, and the multiple memory cells in each memory cell column are connected in series through their respective first semiconductor layers, and the series-connected first semiconductor layers are used to connect to a second bit line; the first electrodes of each memory cell in each memory cell column are used to connect to the same first bit line; each memory cell in any memory cell layer and the memory cells at corresponding positions in other memory cell layers constitute a memory cell string, the first gate of each memory cell in each memory cell string is used to connect to the same first word line, and the third gate of each memory cell in each memory cell string is used to connect to the same second word line.
  • the first electrodes of each memory cell in a first memory cell column and a second memory cell column adjacent in the first direction are used to be connected to the same first bit line; wherein the first memory cell column and the second memory cell column are mirror-symmetrical, and the memory cells in the first memory cell column and the corresponding memory cells in the second memory cell column are adjacent through their respective second transistors.
  • the same first bit line is located between the first storage cell column and the second storage cell column, and the same first bit line has a first surface and a second surface perpendicular to the first direction; the first electrodes of each storage cell in the first storage cell column are connected to the first surface of the same first bit line, and the first electrodes of each storage cell in the second storage cell column are connected to the second surface of the same first bit line.
  • the first gate of each memory cell in a first memory cell string and a second memory cell string adjacent in the first direction is used to be connected to the same first word line; wherein the first memory cell string and the second memory cell string are mirror-symmetrical, and the memory cells in the first memory cell string and the corresponding memory cells in the second memory cell string are adjacent through their respective first transistors.
  • the first word line extends along the second direction, and the first gate of each memory cell in each memory cell string is a part of the connected first word line.
  • the second word line extends along the second direction
  • the third gate of each memory cell in each memory cell string is a part of the connected second word line.
  • a storage unit comprising: a read transistor and a write transistor, the read transistor comprising a main gate and a back gate, the back gate being connected to a semiconductor layer, a source or a drain of the write transistor;
  • the read transistor and the write transistor are respectively vertical transistors
  • the main gate and the back gate are planar, respectively, and the semiconductor layer of the read transistor is planar; the gate of the write transistor is columnar, and the semiconductor layer of the write transistor is annular, and the annular semiconductor layer surrounds the side surface of the columnar gate.
  • the read transistor and the write transistor are located on a substrate and are adjacently distributed in a plane parallel to the substrate; the main surfaces of the main gate and the planar semiconductor layer are respectively perpendicular to the substrate; and the side surface of the columnar gate is perpendicular to the substrate.
  • the planar semiconductor layer has a first main surface and a second main surface facing each other, and the main gate and the back gate are respectively arranged on the first main surface and the second main surface; the back gate has two main surfaces facing each other, one of which is parallel to and adjacent to the second main surface of the planar semiconductor layer, and the other main surface is in contact with the side surface of the annular semiconductor layer.
  • a memory comprising:
  • each storage cell array in each wire group is distributed on the substrate; and each storage cell includes a read transistor and a write transistor;
  • n read transistors are distributed at intervals on the first conductive line along the first direction
  • n write transistors are distributed at intervals on the second conductive line along the first direction and are connected to the n read transistors in a one-to-one correspondence
  • the area where the first wire corresponds to each read transistor is the semiconductor area of each read transistor; the area where the second wire corresponds to each write transistor is connected to the semiconductor area or the source area or the drain area of each write transistor.
  • the memory further includes:
  • a plurality of first word lines extending in a direction perpendicular to the substrate and arranged at intervals in the first direction;
  • the first word lines are respectively arranged in correspondence with the semiconductor region of each read transistor of the first conductive line and are insulated from the semiconductor region by a dielectric layer.
  • the region of the first word line corresponding to the semiconductor region of each read transistor is the gate region of each read transistor, and the gate region is provided with the main gate of the read transistor.
  • the memory further includes:
  • a plurality of back gates extend in a direction perpendicular to the substrate and are sequentially spaced apart in the first direction; the plurality of back gates are respectively arranged in the semiconductor region of each read transistor and are arranged facing the gate region of each read transistor.
  • the memory further includes:
  • a plurality of wraparound semiconductor layers of a plurality of write transistors respectively extending in a direction perpendicular to the substrate and arranged at intervals in the first direction;
  • a plurality of columnar gates of a plurality of write transistors respectively extending in a direction perpendicular to the substrate and arranged at intervals in the first direction;
  • Each of the surrounding semiconductor layers is arranged around a corresponding columnar gate of a write transistor
  • the side surfaces of the columnar gate and the surrounding semiconductor layer are perpendicular to the substrate;
  • One area of the side surface of each of the surrounding semiconductor layers is connected to the second wire, and another area of the side surface of each of the surrounding semiconductor layers is connected to the back gates of each of the read transistors in a one-to-one correspondence.
  • the main gate, the first conductive line, the back gate, the surrounding semiconductor layer, and the second conductive line belonging to one storage unit are arranged in sequence.
  • the first wire and the second wire are respectively planar structures extending perpendicularly to the substrate and having a set width, the planar structures having a first main surface and a second main surface, the first main surface and the second main surface being side surfaces, and the second main surface of the first wire and the first main surface of the second wire are arranged adjacent to each other;
  • Each of the main grids is disposed on the first main surface of the first wire and is insulated from the first wire;
  • Each of the back gates is disposed on the second main surface of the first conductive line and is insulated from the first conductive line.
  • each of the surrounding semiconductor layers is disposed between the second conductive line and each of the back gates, and each of the surrounding semiconductor layers is disposed on a first main surface of the second conductive line and connected to the first main surface.
  • the arrangement of the storage units in one conductive line group is mirror-symmetric to the arrangement of the storage units corresponding to the adjacent conductive line group and they share the second conductive line;
  • the second main surface of the second conductive line is connected to each surrounding semiconductor layer in each storage unit corresponding to the adjacent conductive line group.
  • a second wire is provided every two first wires, the second wire and two first wires adjacent to the second wire form a wire group, and the second wire is shared by storage units corresponding to the two first wires.
  • an electronic device comprising any of the storage units or memories described above.
  • the novel 2T0C design provided in the present application has a gate of the second transistor that is a vertical structure and is not stacked with the first transistor, which can reduce the size of the memory cell in the direction perpendicular to the substrate and facilitate the manufacture of a compact 3D stack of 2T0C memory cells, thereby simplifying the process and reducing costs.
  • the two transistors in the memory cell are arranged along a first direction parallel to the substrate, which helps to save the space occupied by the memory cell in a direction perpendicular to the substrate, thereby increasing the integration density of the memory cell in a direction perpendicular to the substrate and further increasing the storage density of the memory.
  • FIG1 is a schematic diagram of a three-dimensional structure of a storage unit provided in an embodiment of the present application.
  • FIG2 is a cross-sectional schematic diagram of a storage unit provided in an embodiment of the present application.
  • FIG3 is a cross-sectional schematic diagram of a storage unit provided in an embodiment of the present application.
  • FIG4 is a schematic diagram of a logic circuit applicable to a storage unit provided in an embodiment of the present application.
  • FIG5 is a schematic cross-sectional view of a memory provided by an embodiment of the present application.
  • FIG6 is a cross-sectional schematic diagram of a memory provided in an embodiment of the present application.
  • FIG7 is a schematic diagram of the structure of a storage unit column provided in an embodiment of the present application.
  • FIG8 is a cross-sectional schematic diagram of a storage cell column provided in an embodiment of the present application.
  • FIG9 is a schematic diagram of a logic circuit applicable to a memory cell column provided in an embodiment of the present application.
  • FIG10 is a schematic diagram of a logic circuit applicable to a memory provided in an embodiment of the present application.
  • FIG11 is a schematic diagram of a transistor output characteristic curve provided in an embodiment of the present application.
  • FIG. 12 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application.
  • 200 - storage unit 210 - first transistor; 220 - second transistor; 211 - first gate; 212 - first semiconductor layer; 213 - second gate; 221 - third gate; 222 - second semiconductor layer; 223 - channel; 224 - first electrode; 225 - second electrode; 300 - first bit line.
  • the terms used in the application are only for describing specific embodiments and are not intended to limit the present application.
  • the terms “including”, “comprising”, etc. used in the present application indicate the existence of features, steps, operations and/or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.
  • the terms “connected” and “connected” should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral whole; it can be a mechanical connection, an electrical connection, or can communicate with each other; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements.
  • layer used in the present application refers to a material portion including an area with thickness.
  • the layer can extend horizontally, vertically and/or along a conical surface.
  • the term "substrate” used in this application is a base plate for supporting a memory, and one or more film layers can be prepared on the substrate.
  • the type of substrate can be an insulator substrate, a semiconductor substrate, a conductor substrate, etc.
  • the insulator substrate can include a glass substrate, a quartz substrate, a sapphire substrate, a zirconium oxide substrate, a resin substrate, etc.
  • the semiconductor substrate can include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide or gallium oxide, etc.
  • the conductor substrate can include a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc.
  • the memory includes a plurality of memory cells.
  • the embodiment of the present application provides a 2T0C memory cell with a new structure, which is more conducive to the design of a high-density memory cell in terms of space, and more conducive to industrialized memory cells and 3D memory in terms of process.
  • the memory cell is a memory cell corresponding to the 2T0C logic circuit shown in FIG4.
  • One of the transistors is a read transistor, and the other transistor is a write transistor.
  • Figure 1 shows a schematic diagram of the three-dimensional structure of a storage unit provided in an embodiment of the present application
  • Figures 2 and 3 show schematic diagrams of the cross-section of the storage unit provided in an embodiment of the present application, wherein the cross-section schematic diagram shown in Figure 2 is a schematic diagram of the cross-section observed after the storage unit shown in Figure 1 is cut off according to the a plane in Figure 1, and the cross-section schematic diagram shown in Figure 3 is a schematic diagram of the cross-section corresponding to A-A’ shown in Figure 2.
  • the memory cell 200 provided in the embodiment of the present application includes a first transistor 210 and a second transistor 220 arranged and connected along a first direction in the support surface (such as a substrate or other film layer on the substrate).
  • the first transistor 210 is a read transistor (T1)
  • the second transistor 220 is a write transistor (T2).
  • the first direction and the third direction in Figure 1 intersect and are parallel to the upper surface of the support surface, and the second direction is perpendicular to the support surface.
  • the first direction and the third direction are perpendicular to each other.
  • the first transistor 210 located on the upper surface of the support surface includes a first gate 211, a first semiconductor layer 212 and a second gate 213 arranged in sequence along a first direction.
  • the first gate 211 is connected to a word line to control the on or off of the first transistor 210, and the second gate 213 is a back gate to form a storage capacitor CBG as shown in FIG4.
  • the first semiconductor layer 212 has two main planes, and the two main planes are perpendicular to the support surface.
  • the first gate 211 and the second gate 213 are respectively located on the two main planes of the first semiconductor layer 212 and are insulated from the first semiconductor layer 212 by an insulating layer.
  • the second transistor 220 includes a third gate 221 extending in a direction perpendicular to the support surface, and the third gate 221 has a side wall (or called a side surface) perpendicular to the support surface; the second transistor 220 includes a second semiconductor layer 222 surrounding the side wall of the third gate 221, and the third gate 221 and the second semiconductor layer 222 are insulated by an insulating layer.
  • the second semiconductor layer 222 is a surrounding structure, and the cross section of the second semiconductor layer 222 is annular.
  • the cross section of the second semiconductor layer 222 is circular, square, elliptical, etc.
  • the second semiconductor layer 222 has a side wall perpendicular to the support surface and has two regions spaced apart from each other, one of which is connected to the second gate 213 and the other is connected to the first bit line 300 .
  • the second semiconductor layer 222 includes a channel 223 and a first electrode 224 and a second electrode 225 connected by the channel 223.
  • the first electrode 224 is a region of the second semiconductor layer 222 connected to the first bit line 300
  • the second electrode 225 is a region of the second semiconductor layer 222 connected to the second gate 213.
  • the second electrode 225 is connected to the second gate 213, and the first electrode 224 is used to connect to a first bit line 300.
  • the interval area between the first electrode 224 and the second electrode 225 is a channel area.
  • One of the first electrode 224 and the second electrode 225 can be understood as a source electrode, and the other electrode can be understood as a drain electrode. When determining which one is the source electrode and which one is the drain electrode, it is related to the flow direction of the current in the transistor, and is not limited here.
  • the first bit line 300 can be used to apply voltage to the first electrode 224; the first gate 211 is used to connect to a first word line, and the first word line is used to apply voltage to the first gate 211; the third gate 221 is used to connect to a second word line, and the second word line is used to apply voltage to the third gate 221.
  • the first word line and the second word line both extend in a direction perpendicular to the support surface, and are used to form a storage array with a 3D structure in a three-dimensional space.
  • the structure of the 2T0C in the storage unit 200 is periodically distributed, then the first word line is a word line shared by the plurality of first transistors 210, and the second word line is a word line shared by the plurality of second transistors 220.
  • the first gate 211 is part of the first word line
  • the third gate 221 is part of the second word line.
  • the first gate 211 overlaps with the projection of the first word line on the supporting surface
  • the third gate 221 overlaps with the projection of the second word line on the supporting surface. At this time, the density of the storage unit can be improved.
  • the first semiconductor layer 212 and the first bit line 300 extend along the third direction within the support surface and are distributed at intervals. In this way, the first transistors 210 and the second transistors 220 can be distributed periodically in the third direction. In the third direction, the first semiconductor layers 212 of each first transistor 210 can share a common semiconductor layer, which can also be understood as a semiconductor layer distributed in the third direction.
  • the semiconductor layer has two main surfaces, which are two side surfaces placed on the support surface. There are multiple pairs of gates distributed periodically on the two side surfaces, and each pair of gates is a first gate 211 and a second gate 213 arranged opposite to each other.
  • the first gate 211 and the second gate 213 are respectively arranged on the two side surfaces and insulated from the semiconductor layers on the two side surfaces, thereby forming a plurality of first transistors 210 connected in series, and the first transistor 210 is a transistor with a main gate and a back gate.
  • a first bit line 300 connected to the first electrode 224 of the second transistor 220 can apply a voltage to the second semiconductor layer 222. Since the second semiconductor layer 222 of the second transistor 220 is connected to the second gate 213 of the first transistor 210, the voltage applied to the second semiconductor layer 222 can be written into the second gate 213 of the first transistor 210.
  • the second gate 213 is one of the two gates of the first transistor 210 (back gate). After a voltage (high voltage or low voltage, etc.) is written into the second gate 213, the potential of the second gate 213 can be used to change the threshold voltage of the first transistor 210. By changing the threshold voltage of the first transistor 210, data can be written, for example, multi-bit storage of multiple threshold voltages can be achieved.
  • data writing can be realized by applying voltage through the first bit line 300, without forming a high voltage difference, and without relying on charge tunneling, and the requirements for data writing are relatively low, thereby making data writing easier to implement, which is conducive to increasing the speed of data writing, and thus improving the performance of the memory.
  • the memory cell provided in the embodiment of the present application can lay the foundation for realizing high-speed and high-density memory, and the data writing speed of the memory made using the memory cell is greatly improved compared with the memory in the related art.
  • the gate of the second transistor is a vertical structure and is not stacked with the first transistor, which can facilitate the manufacture of a 3D stack of compact 2T0C memory cells.
  • the size of the memory cell in the direction perpendicular to the substrate can be reduced, and the process can be simplified to reduce costs.
  • the two transistors in the memory cell are arranged along a first direction parallel to the substrate, which helps to save the space occupied by the memory cell in a direction perpendicular to the substrate, thereby increasing the integration density of the memory cell in a direction perpendicular to the substrate and further increasing the storage density of the memory.
  • the memory cell provided in the embodiment of the present application is suitable for the logic circuit shown in Figure 4.
  • the memory cell includes a first transistor (T1) and a second transistor (T2).
  • T1 is a dual-gate transistor
  • the first gate of T1 also referred to as the main gate
  • the second gate of T1 also referred to as the back gate, referred to as BG
  • the back gate of T1 and the channel of T1 and the dielectric layer therebetween can form a capacitor (C BG ) for storing electrical signals.
  • T2 has two electrodes, one of which is a source and the other is a drain.
  • One electrode of T2 is connected to the above-mentioned back gate, and the other electrode is used to connect to a first bit line (W-BL), and the gate of T2 (i.e., the third gate) is used to connect to a second word line (W-WL).
  • W-BL first bit line
  • W-WL second word line
  • the first transistor 210 or the second transistor 220 may be an N-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), or a P-type MOSFET.
  • the first transistor 210 and/or the second transistor 220 is a depletion-type N-type MOSFET.
  • the first gate 211 of the first transistor 210 is used to control the state of the channel of the first transistor 210 (conductive or non-conductive), and can also be called the main control gate; the second gate 213 of the first transistor 210 is used to store data, and can also be called the back gate or storage gate.
  • the data writing in the storage unit 200 is realized by writing a voltage (high voltage or low voltage) on the second gate 213 in the first transistor 210
  • the first transistor 210 can also be called a storage transistor, and the storage transistor also supports data reading, so it can also be called a read transistor.
  • the first transistor 210 is a dual-gate transistor, and the potential on the back gate in such a dual-gate transistor can be used to change the threshold voltage.
  • the function of the second gate 213 in the first transistor 210 is similar to that of the floating gate in a floating gate transistor and the charge trapping layer in a charge trapping transistor.
  • the second transistor 220 is used to write a high voltage or a low voltage into the second gate 213 of the first transistor 210 , so the second transistor 220 may also be referred to as a write transistor.
  • the embodiment of the present application does not limit the specific shapes and sizes of the components in the first transistor 210 and the second transistor 220, and can be flexibly adjusted according to actual needs.
  • the main gate in the first transistor 210 which is the first gate 211 in the two-transistor solution of this application, extends in a direction perpendicular to the substrate, that is, extends along the second direction.
  • the cross-sectional areas of the first gate 211 at different positions may be the same or different, which is related to the actual manufacturing process.
  • the cross-sectional area of the first gate 211 at any position refers to the plane obtained by cutting the first gate 211 at any position using a plane parallel to the substrate.
  • the cross-sectional areas of the first gate 211 at different positions are the same.
  • the gate in the second transistor 220 is the third gate 221 in the two-transistor scheme of the application, extending in a direction perpendicular to the substrate, that is, extending along the second direction.
  • the cross-sectional areas of the third gate 221 at different positions may be the same or different, which is related to the actual preparation process.
  • the cross-sectional area of the third gate 221 at any position refers to the plane obtained by cutting off the third gate 221 from any position using a plane parallel to the substrate.
  • the area of the cross-sectional area of the third gate 221 at a position wrapped by the second semiconductor layer 222 is greater than the area of the cross-sectional area at a position not wrapped by the second semiconductor layer 222.
  • the first transistor 210 and the second transistor 220 are arranged along a first direction, i.e., they are closely arranged in a direction parallel to the substrate and are interconnected.
  • the first transistor 210 and the second transistor 220 belonging to one memory cell 200 are not stacked in a direction perpendicular to the substrate, which is beneficial to saving the space occupied by the memory cell in a direction perpendicular to the substrate, thereby improving the integration density of the memory cell in a direction perpendicular to the substrate, and further improving the storage density of the memory.
  • first transistor 210 and the second transistor 220 are arranged along the first direction, which may mean that the arrangement direction from the first transistor 210 to the second transistor 220 is the first direction, or that the arrangement direction from the second transistor 220 to the first transistor 210 is the first direction.
  • first gate 211, the first semiconductor layer 212, and the second gate 213 are arranged along the first direction, which may mean that the arrangement direction from the first gate 211 to the second gate 213 is the first direction, or that the arrangement direction from the second gate 213 to the first gate 211 is the first direction.
  • the arrangement direction from the first transistor 210 to the second transistor 220 is the first direction
  • the arrangement direction from the first gate 211 to the second gate 213 is the first direction
  • the arrangement direction from the second transistor 220 to the first transistor 210 is the first direction
  • the arrangement direction from the second gate 213 to the first gate 211 is the first direction
  • the first gate 211 in the first transistor 210 is insulated from the first semiconductor layer 212, that is, there is a gate insulating layer (called the first gate insulating layer) between the first gate 211 and the first semiconductor layer 212.
  • the second gate 213 is insulated from the first semiconductor layer 212, that is, there is a gate insulating layer (called the second gate insulating layer) between the second gate 213 and the first semiconductor layer 212.
  • the first transistor 210 and the second transistor 220 are both vertical transistors, and the first gate 211, the first gate insulating layer, and the first semiconductor layer 212 in the first transistor 210 are all perpendicular to the substrate.
  • the first gate 211, the first gate insulating layer, the first semiconductor layer 212, the second gate insulating layer, and the second gate 213 are arranged adjacent to each other in a direction parallel to the substrate (first direction), that is, the various components of the first transistor 210 belonging to a memory cell 200 are not stacked in a direction perpendicular to the substrate.
  • the various components of the first transistor 210 can be regarded as planar.
  • the first gate 211, the first gate insulating layer, the first semiconductor layer 212, the second gate insulating layer, and the second gate 213 all have a first surface and a second surface perpendicular to the first direction, wherein the first surface of the same component is farther away from the second transistor 220 than the second surface.
  • the first surface of the first gate 211 is farther away from the second transistor 220 than the second surface of the first gate 211
  • the first surface of the first gate insulating layer is farther away from the second transistor 220 than the second surface of the first gate insulating layer
  • the first surface of the first semiconductor layer 212 is farther away from the second transistor 220 than the second surface of the first semiconductor layer 212
  • the first surface of the second gate insulating layer is farther away from the second transistor 220 than the second surface of the second gate insulating layer
  • the first surface of the second gate 213 is farther away from the second transistor 220 than the second surface of the second gate 213.
  • the first gate 211, the first gate insulating layer, the first semiconductor layer 212, the second gate insulating layer and the second gate 213 are closely arranged in a direction parallel to the substrate (first direction) and are interconnected. Specifically, the second surface of the first gate 211 is in contact with the first surface of the first gate insulating layer, the second surface of the first gate insulating layer is in contact with the first surface of the first semiconductor layer 212, the second surface of the first semiconductor layer 212 is in contact with the first surface of the second gate insulating layer, and the second surface of the second gate insulating layer is in contact with the first surface of the second gate 213.
  • the first transistor 210 in the memory cell 200 is arranged in such a way that the first gate 211, the first gate insulating layer, the first semiconductor layer 212, the second gate insulating layer and the second gate 213 are closely arranged and interconnected in a direction parallel to the substrate (the first direction), which helps to save the space occupied by the first transistor 210, improve the integration density of the memory cell 200, and further improve the storage density of the memory.
  • the third gate 221 in the second transistor 220 is insulated from the second semiconductor layer 222, that is, there is a gate insulating layer (called the third gate insulating layer) between the third gate 221 and the second semiconductor layer 222. It should be noted that, since the second semiconductor layer 222 surrounds the third gate 221, the third gate insulating layer between the third gate 221 and the second semiconductor layer 222 also surrounds the third gate 221 to ensure insulation between the third gate 221 and the second semiconductor layer 222.
  • the second transistor 220 is a Channel-All-Around (CAA) transistor.
  • CAA Channel-All-Around
  • the second electrode 225 in the second semiconductor layer 222 is embedded in the second gate electrode 213 to achieve connection with the second gate electrode 213; the first electrode 224 in the second semiconductor layer 222 is embedded in a corresponding first bit line 300 to achieve connection with a corresponding first bit line 300. That is, as shown in FIGS. 1 to 3 , the portion of the second semiconductor layer 222 embedded in the second gate electrode 213 is the second electrode 225, the portion of the second semiconductor layer 222 embedded in the corresponding first bit line 300 is the first electrode 224, and the other portions of the second semiconductor layer 222 except the first electrode 224 and the second electrode 225 are the channel 223.
  • the second electrode 225 in the second semiconductor layer 222 is the drain of the second transistor 220, and the first electrode 224 is the source of the second transistor 220; in other embodiments, the first electrode 224 in the second semiconductor layer 222 is the drain of the second transistor 220, and the second electrode 225 is the source of the second transistor 220.
  • the source and drain of the second transistor 220 can be interchanged in some cases. In practical applications, the source and drain of the second transistor 220 can be identified according to the direction of the current.
  • the channel 223 in the second semiconductor layer 222 is a horizontal channel.
  • the channel length direction is in a plane parallel to the substrate, wherein the channel length direction refers to the direction of the conductive path between the first electrode 224 and the second electrode 225.
  • the horizontal channel described in the embodiment of the present application can be understood as a type of non-vertical channel.
  • the channel extends in a plane parallel to the substrate, which can be understood as an embodiment in which the length direction of the channel or the carrier transmission direction is in a plane parallel to the substrate.
  • the channel can be approximately parallel to the substrate, and the error can be within a certain range, such as within 10 degrees. In practical applications, it depends on the relative position between the effective source and drain.
  • the outer contours of the upper and/or lower surfaces of the electrodes in the longitudinal cross-sectional view of the source and drain are on a plane, and the plane is approximately parallel to the main surface of the substrate.
  • the horizontal channel can be a planar channel or a ring channel, depending on factors such as the shape and relative position of the second semiconductor layer 222, the source and drain.
  • the second transistor 220 in the embodiment of the present application is a transistor with a gate extending in a vertical direction and a horizontal channel, which can reduce the size of the memory cell in the direction perpendicular to the substrate, and can facilitate the manufacture of a compact 3D stack of 2T0C memory cells, thereby simplifying the process.
  • the channel 223 in the second semiconductor layer 222 may include at least one channel layer, for example, one channel layer, or two or more channel layers arranged in parallel along the third direction, etc.
  • the sizes of different channel layers may be the same or different, which is related to the actual preparation process.
  • the channel 223 includes two channel layers arranged in parallel along the third direction, the two channel layers have the same length, and the two channel layers have the same width, wherein the width of any channel layer is the size of the second semiconductor layer 222 in the second direction, and the length of any channel layer is the distance between the first electrode 224 and the second electrode 225 in the second semiconductor layer 222 in the first direction.
  • the length of any channel layer can be the length of the L mark in FIG. 2, and the length of the L mark can be regarded as the shortest distance between the first electrode 224 and the second electrode 225 in the second semiconductor layer 222 in the first direction.
  • the conductivity of the channel 223 is different from that of the first electrode 224 and the second electrode 225 to which it is connected.
  • the channel 223 is a metal oxide semiconductor, and the conductivity of the first electrode 224 and the second electrode 225 is higher than that of the metal oxide semiconductor. In practical applications, the conductivity can be tested to distinguish them.
  • the main materials of the first electrode 224 and the second electrode 225 connected to the channel 223 can be the same, and the region with higher conductivity can be achieved by doping.
  • the channel 223 has the same conductivity as the first electrode 224 and the second electrode 225 to which it is connected.
  • the channel 223, the first electrode 224, and the second electrode 225 are all polysilicon or metal oxide semiconductors, and their conductivity can be close to that of a conductor or a semiconductor, and the transistor can be turned off or on by controlling the gate.
  • the channel 223, the first electrode 224, and the second electrode 225 can be formed by a single process under the same process conditions. Therefore, in this embodiment, the channel 223, the first electrode 224, and the second electrode 225 are not particularly clearly distinguished in terms of boundaries, and the concepts of channel and electrode are only proposed from a functional perspective.
  • the second semiconductor layer 222 has a first connection region connected to a first bit line 300, a second connection region connected to the second gate 213, and a gate control region other than the first connection region and the second connection region, wherein the conductivity of the gate control region is controlled by the third gate 221.
  • the gate control region has a stronger conductivity
  • the gate control region has a weaker conductivity.
  • the first connection region, the second connection region, and the gate control region can be made of the same semiconductor material or different semiconductor materials.
  • the first connection region can be functionally referred to as a first electrode
  • the second connection region can be functionally referred to as a second electrode
  • the gate control region can be functionally referred to as a channel.
  • the second semiconductor layer 222 has four outer surfaces perpendicular to the substrate, which are respectively referred to as a first surface, a second surface, a third surface, and a fourth surface, wherein the first surface and the second surface of the second semiconductor layer 222 are perpendicular to a first direction, and the third surface and the fourth surface of the second semiconductor layer 222 are perpendicular to a third direction.
  • the second surface of the second semiconductor layer 222 is farther away from the first transistor 210 than the first surface of the second semiconductor layer 222.
  • the second semiconductor layer 222 shown in FIGS. 1 to 3 is a rectangular annular column with rounded corners
  • the embodiments of the present application are not limited thereto, and the second semiconductor layer 222 may also be prepared into a rectangular annular column with right angles, which is related to the actual preparation process.
  • the four outer surfaces of the second semiconductor layer 222 that are perpendicular to the substrate all include surfaces corresponding to the rounded corners.
  • first surface and the second surface of the second semiconductor layer 222 are perpendicular to the first direction, which may mean that other places except the surface corresponding to the rounded corners are perpendicular to the first direction
  • third surface and the fourth surface of the second semiconductor layer 222 are perpendicular to the third direction, which may mean that other places except the surface corresponding to the rounded corners are perpendicular to the third direction.
  • the second gate 213 wraps the entire first surface of the second semiconductor layer 222 and a portion of the third and fourth surfaces of the second semiconductor layer 222 close to the first transistor 210; a first bit line 300 wraps the entire second surface of the second semiconductor layer 222 and a portion of the third and fourth surfaces of the second semiconductor layer 222 away from the first transistor 210.
  • the two portions of the third surface of the second semiconductor layer 222 that are wrapped by the second gate 213 and the first bit line 300 occupy the entire third surface, or occupy part of the third surface, which is not limited in the embodiment of the present application.
  • the two portions of the fourth surface of the second semiconductor layer 222 that are wrapped by the second gate 213 and the first bit line 300 occupy the entire fourth surface, or occupy part of the fourth surface, which is not limited in the embodiment of the present application.
  • two parts of the third surface of the second semiconductor layer 222 that are wrapped by the second gate 213 and a first bit line 300 occupy part of the third surface
  • two parts of the fourth surface of the second semiconductor layer 222 that are wrapped by the second gate 213 and a first bit line 300 occupy part of the fourth surface, that is, the third surface and the fourth surface of the second semiconductor layer 222 both have partial areas that are not wrapped by the second gate 213 and a first bit line 300.
  • the first semiconductor layer 212 includes a second channel and a third electrode and a fourth electrode connected through the second channel, wherein the third electrode and the fourth electrode are distributed on both sides of the second channel.
  • the conductivity of the second channel is different from that of the third electrode and the fourth electrode to which it is connected.
  • the second channel is a metal oxide semiconductor, and the conductivity of the third electrode and the fourth electrode is higher than that of the metal oxide semiconductor. In practical applications, the conductivity can be tested to distinguish them.
  • the main material of the third electrode and the fourth electrode connected by the second channel can be the same, and the area with higher conductivity can be achieved by doping.
  • the second channel is a horizontal channel, that is, the length direction of the second channel or the carrier transmission direction is in a plane parallel to the substrate.
  • the first transistor 210 in the embodiment of the present application is a transistor with a gate extending in a vertical direction and a horizontal channel, which can reduce the size of the memory cell in the direction perpendicular to the substrate, and can facilitate the manufacture of a compact 3D stack of 2T0C memory cells, simplifying the process.
  • the second channel has the same conductivity as the third electrode and the fourth electrode to which it is connected.
  • the second channel, the third electrode, and the fourth electrode are all polysilicon or metal oxide semiconductors, and their conductivity can be close to that of a conductor or a semiconductor, and the transistor can be turned off or on by controlling the gate.
  • the second channel, the third electrode, and the fourth electrode can be formed by a single process under the same process conditions. Therefore, in this embodiment, the second channel, the third electrode, and the fourth electrode are not particularly clearly distinguished in terms of boundaries. The concepts of channel and electrode are only proposed from a functional perspective.
  • the positions of the third electrode, the second channel, and the fourth electrode in the first semiconductor layer 212 are shown as 1, 2, and 3 in FIG. 2, respectively.
  • the conductivity of the second channel is controlled by the first gate 211.
  • the channel length of the second channel (that is, the length of the conductive path between the third electrode and the fourth electrode) is the size of the first gate 211 in the third direction.
  • the third electrode is the drain of the first transistor 210
  • the fourth electrode is the source of the first transistor 210
  • the fourth electrode is the drain of the first transistor 210
  • the third electrode is the source of the first transistor 210.
  • the source and drain of the first transistor 210 can be interchanged in some cases. In practical applications, when identifying the source and drain, they can be identified according to the direction of the current. The same electrode may be a source or a drain under different current directions.
  • the first semiconductor layer 212 has a third connection region, a fourth connection region, and a second gate control region other than the third connection region and the fourth connection region, wherein the third connection region, the second gate control region, and the fourth connection region are arranged along the third direction.
  • the conductivity of the second gate control region is controlled by the first gate 211. For example, when a large voltage is applied to the first gate 211, the second gate control region has a strong conductivity, and when a small voltage is applied to the first gate 211, the second gate control region has a weak conductivity. By controlling the conductivity of the second gate control region, the first transistor 210 can be turned off or turned on.
  • the third connection region, the fourth connection region, and the second gate control region can be prepared from the same semiconductor material, or from different semiconductor materials.
  • the third connection region can be functionally referred to as a third electrode
  • the fourth connection region can be functionally referred to as a fourth electrode
  • the second gate control region can be functionally referred to as a second channel.
  • the materials of the first gate 211, the second gate 213, the third gate 221 and the first bit line 300 are all conductive materials.
  • the conductive material may refer to an alloy with metal elements as components or an alloy of combined metal elements, etc.
  • the materials of the first gate 211, the second gate 213, the third gate 221 and the first bit line 300 may be the same or different.
  • the material of the first semiconductor layer 212 and the second semiconductor layer 222 is a semiconductor material.
  • the semiconductor material may refer to a single crystal semiconductor material, a polycrystalline semiconductor material, a microcrystalline semiconductor material, or an amorphous semiconductor material, etc.
  • the semiconductor material may include but is not limited to single crystal silicon, polycrystalline silicon, germanium, silicon carbide, gallium arsenide, metal oxide semiconductor, nitride semiconductor, etc.
  • the materials of the first semiconductor layer 212 and the second semiconductor layer 222 may be the same or different.
  • the band gap of a metal oxide semiconductor is above 2eV.
  • a metal oxide semiconductor is used as the material of the semiconductor layer, a transistor with a very small off-state current can be realized.
  • the insulation withstand voltage between the source and the drain is high, so that a transistor with good reliability can be provided, and then a memory with good reliability can be provided.
  • a transistor with a large output voltage and a high withstand voltage can also be provided, and then a memory with a large output voltage and a high withstand voltage can be provided.
  • the material of the second semiconductor layer 222 is a metal oxide semiconductor, so that the second transistor 220 is realized as a transistor with a very small off-state current.
  • the material of the first semiconductor layer 212 can also be a metal oxide semiconductor, so that the first transistor 210 is realized as a transistor with a very small off-state current.
  • the metal oxide semiconductor may include at least one of indium or zinc.
  • the metal oxide semiconductor may also include aluminum, gallium, yttrium or tin, etc.
  • the metal oxide semiconductor may also include one or more of boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.
  • element M may be aluminum, gallium, yttrium or tin, etc., or may be boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc., and a plurality of the above elements may also be combined.
  • a metal oxide semiconductor comprising indium, gallium and zinc may be referred to as indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • the transistor may be referred to as an IGZO MOSFET.
  • the materials of the first gate insulating layer between the first gate 211 and the first semiconductor layer 212, the second gate insulating layer between the second gate 213 and the first semiconductor layer 212, and the third gate insulating layer between the third gate 221 and the second semiconductor layer 222 are all insulating materials. It should be noted that the materials of different gate insulating layers can be the same or different.
  • the insulating material may refer to insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal oxynitrides.
  • the insulating material used as the gate insulating layer may use a high-k (high dielectric constant) material, which can achieve low voltage when the transistor is operating while maintaining the physical thickness.
  • the insulating material with a high dielectric constant may refer to gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium.
  • the embodiment of the present application also provides a memory including a storage unit as shown in Figures 1 to 3. Since the storage unit shown in Figures 1 to 3 can increase the speed of data writing, the memory including the storage unit as shown in Figures 1 to 3 can also increase the speed of data writing.
  • Figures 5 and 6 show two cross-sectional schematic diagrams of the memory provided in the embodiment of the present application. Among them, Figure 5 is a schematic diagram of the cross section observed after the memory is cut off by a plane (not shown) parallel to both the first direction and the third direction, and Figure 6 is a schematic diagram of the cross section corresponding to A-A' in Figure 5. It should be noted that Figures 5 and 6 are only exemplary examples, and the embodiment of the present application is not limited thereto. It should be further noted that, for ease of distinction, in Figures 5 and 6, the same filling method is used to fill the components made of the same type of material, and different filling methods are used to fill the components made of different types of materials.
  • the memory includes a plurality of memory cell layers, each memory cell layer includes a plurality of memory cells 200 as shown in FIGS. 1 to 3, and the plurality of memory cell layers are arranged along the second direction.
  • Each memory cell layer includes a plurality of memory cell columns arranged along the first direction, and the plurality of memory cells 200 in each memory cell column are connected in series through respective first semiconductor layers 212, and the first semiconductor layers 212 connected in series are used to be connected to a second bit line; the first electrodes 224 of the respective memory cells 200 in each memory cell column are used to be connected to the same first bit line 300.
  • Each memory cell 200 in any memory cell layer and the memory cells 200 at corresponding positions in other memory cell layers constitute a memory cell string, and the first gate 211 of each memory cell 200 in each memory cell string is used to be connected to the same first word line, and the third gate 221 of each memory cell 200 in each memory cell string is used to be connected to the same second word line.
  • a plurality of memory cell columns are arranged along a first direction to form a memory cell layer, and a plurality of memory cell layers are arranged along a second direction to form a memory.
  • This memory is a three-dimensional memory with a higher storage density.
  • the first word line and the second bit line can be used in the data reading process, so the first word line can also be called a read word line (abbreviated as WL-r or R-WL), and the second bit line can also be called a read bit line (abbreviated as BL-r or R-BL).
  • the second word line and the first bit line 300 can be used in the data writing process, so the second word line can also be called a write word line (abbreviated as WL-w or W-WL), and the first bit line 300 can also be called a write bit line (abbreviated as BL-w or W-BL).
  • FIG7 shows a schematic diagram of the structure of a storage cell column including two storage cells 200
  • FIG8 shows a schematic diagram of a cross section of the storage cell column shown in FIG7, which is a schematic diagram of a cross section observed after the storage cell column shown in FIG7 is cut according to the plane b in FIG7.
  • FIG7 and FIG8 only take a storage cell column including two storage cells 200 as an example, but the embodiment of the present application is not limited thereto, that is, a storage cell column may also include more than two (e.g., 4, 8, 16) storage cells 200.
  • each memory cell column includes a plurality of memory cells 200, each memory cell 200 includes a first transistor 210 and a second transistor 220 arranged along a first direction; the first transistor 210 includes a first gate 211, a first semiconductor layer 212 and a second gate 213 arranged along the first direction, the first gate 211 extends along the second direction, and the first semiconductor layer 212 extends along the third direction, the first direction and the third direction are two directions parallel to the substrate and perpendicular to each other, and the second direction is a direction perpendicular to the substrate.
  • the second transistor 220 includes a third gate 221 and a second semiconductor layer 222 surrounding the third gate 221, the third gate 221 extends along the second direction, the second semiconductor layer 222 includes a channel 223 and a first electrode 224 and a second electrode 225 connected through the channel 223, and the second electrode 225 is connected to the second gate 213.
  • the first electrode 224 is used to connect to a first bit line 300, and the first bit line 300 is used to apply a voltage to the first electrode 224.
  • the first gate 211 is used to connect to a first word line, and the first word line is used to apply a voltage to the first gate 211; the third gate 221 is used to connect to a second word line, and the second word line is used to apply a voltage to the third gate 221.
  • the introduction of the memory cell 200 is detailed in the embodiments involved in Figures 1 to 3, and will not be repeated here.
  • the memory cell column extends along the third direction and a plurality of memory cells 200 in the memory cell column are connected in series through respective first semiconductor layers 212.
  • One end of the first semiconductor layers 212 connected in series is used to be connected to a second bit line, and the second bit line is used to apply a voltage to the first semiconductor layers 212 connected in series;
  • the other end of the first semiconductor layers 212 connected in series is used to be connected to a source line, and the source line is also used to apply a voltage to the first semiconductor layers 212 connected in series.
  • the first semiconductor layer 212 of each memory cell 200 includes a third electrode, a second channel, and a fourth electrode in sequence, and the memory cells connected in series through the first semiconductor layer 212 share the third electrode or the fourth electrode.
  • the memory cell column further includes a third transistor and a fourth transistor, and the third transistor and the fourth transistor are respectively located at two ends of the plurality of memory cells 200 connected in series; the third transistor and the fourth transistor each include a gate and a semiconductor layer, wherein the semiconductor layers of the third transistor and the fourth transistor each include a source, a channel and a drain.
  • the third transistor and the fourth transistor are connected in series with the plurality of memory cells 200 connected in series through their respective semiconductor layers.
  • the drain of the third transistor in the memory cell column is connected in series with the memory cell 200, the source of the third transistor is used to be connected to the second bit line, the gate of the third transistor is used to be connected to the drain selection line, the drain selection line is used to control the state of the channel of the third transistor, and by controlling the state of the channel of the third transistor, the third transistor can be controlled to be turned off or turned on.
  • the drain of the fourth transistor in the memory cell column is connected in series with the memory cell 200, the gate of the fourth transistor is used to be connected to the source selection line, and the source of the fourth transistor is used to be connected to the source line, wherein the source selection line is used to control the state of the channel of the fourth transistor, and by controlling the state of the channel of the fourth transistor, the fourth transistor can be controlled to be turned off or turned on.
  • the source and drain of the third transistor can be interchanged in some cases, and the source and drain of the fourth transistor can also be interchanged in some cases. In practical applications, the source and drain can be identified according to the direction of the current.
  • the conductivity of the channel in the semiconductor layer of the third transistor is different from that of the source and the drain.
  • the channel is a metal oxide semiconductor, and the conductivity of the source and the drain is higher than that of the metal oxide semiconductor. In practical applications, the conductivity can be tested to distinguish.
  • the main material of the source and the drain can be the same, and the area with higher conductivity can be achieved by doping.
  • the channel in the semiconductor layer of the third transistor has the same conductivity as the source and drain.
  • the channel, source and drain are all polysilicon or metal oxide semiconductors, and their conductivity can be close to that of a conductor or a semiconductor, and the transistor can be turned off or on by controlling the gate.
  • the channel, source and drain can be formed by a single process under the same process conditions. Therefore, in this embodiment, the channel, source and drain are not particularly clearly distinguished in terms of boundaries. The concepts of channel, source and drain are only proposed from a functional perspective.
  • the semiconductor layer of the third transistor has two connection regions and a gate control region other than the two connection regions, wherein the two connection regions are located on both sides of the gate control region in the third direction.
  • the conductivity of the gate control region is controlled by the gate of the third transistor (or the fourth transistor).
  • the two connection regions and the gate control region can be prepared from the same semiconductor material or from different semiconductor materials.
  • the two connection regions can be functionally referred to as a source and a drain, respectively, and the gate control region can be functionally referred to as a channel.
  • first gates 211 of the multiple memory cells 200 in the memory cell column are isolated from each other in the third direction, such as by isolation through a dielectric layer; the second gates 213 of the multiple memory cells 200 are isolated from each other in the third direction, such as by isolation through a dielectric layer; and the second semiconductor layers 222 of the multiple memory cells 200 are isolated from each other in the third direction, such as by isolation through a dielectric layer.
  • the first electrodes 224 of different memory cells 200 in the memory cell column can be used to connect to the same first bit line 300, that is, the first electrodes 224 of multiple memory cells 200 in the memory cell column are used to connect to the same first bit line 300.
  • voltage can be applied to the first electrodes 224 of multiple memory cells 200 in the memory cell column simultaneously through the same first bit line 300, thereby improving the voltage application efficiency and reducing the number of first bit lines 300, which is beneficial to improving the storage density of the memory.
  • the first bit line 300 extends along the third direction.
  • two memory cell columns adjacent in the first direction may be completely identical or mirror-symmetrical, which is not limited in the embodiments of the present application.
  • the two memory cell columns are mirror-symmetrical the corresponding memory cells 200 in the two memory cell columns are adjacent through their respective second transistors 220; or the corresponding memory cells 200 in the two memory cell columns are adjacent through their respective first transistors 210.
  • the corresponding memory cells in the two memory cell columns refer to the memory cells in the same row in the two memory cell columns.
  • the memory cells 200 in the previous memory cell column are memory cells of the first type
  • the corresponding memory cells 200 in the next memory cell column are memory cells of the second type
  • the first type of memory cell refers to the memory cell 200 whose arrangement direction from the first transistor 210 to the second transistor 220 is the first direction
  • the second type of memory cell refers to the memory cell 200 whose arrangement direction from the second transistor 220 to the first transistor 210 is the first direction.
  • the memory cells 200 in the previous memory cell column are second type memory cells
  • the corresponding memory cells 200 in the next memory cell column are first type memory cells.
  • the first electrodes 224 of the plurality of memory cells 200 in different memory cell columns are connected to different first bit lines 300 , so that voltages can be applied to the first electrodes 224 of the plurality of memory cells 200 in different memory cell columns using different first bit lines 300 , thereby improving flexibility in voltage application.
  • the first memory cell column and the second memory cell column For example, if two memory cell columns adjacent in the first direction among the plurality of memory cell columns are mirror-symmetrical, then for each two memory cell columns adjacent in the first direction and whose corresponding memory cells 200 are adjacent through their respective second transistors 220 (referred to as the first memory cell column and the second memory cell column), since the first electrodes 224 of the memory cells 200 in the first memory cell column and the second memory cell column are close to each other, the first electrodes 224 of the memory cells 200 in the first memory cell column and the second memory cell column can share the same first bit line 300, that is, the first electrodes 224 of the memory cells 200 in the first memory cell column and the second memory cell column adjacent in the first direction are used to be connected to the same first bit line 300.
  • the first memory cell column and the second memory cell column are mirror-symmetrical, and the memory cells 200 in the first memory cell column and the corresponding memory cells 200 in the second memory cell column are adjacent through their respective second transistors 220.
  • a voltage can be applied to the first electrodes 224 of the memory cells 200 in the two memory cell columns simultaneously by using one first bit line 300, thereby improving the efficiency of voltage application, reducing the number of first bit lines 300, and improving storage density.
  • the first electrodes 224 of the memory cells 200 in two memory cell columns adjacent to each other and corresponding to each other in the first direction through the respective second transistors 220 are used to connect to the same first bit line 300.
  • the first electrodes 224 of the memory cells 200 in the two memory cell columns are embedded in the same first bit line 300 to achieve connection with the same first bit line 300.
  • the same first bit line 300 is located between the first memory cell column and the second memory cell column, and the same first bit line 300 has a first surface and a second surface perpendicular to the first direction.
  • the first electrodes 224 of each memory cell 200 in the first memory cell column are connected to the first surface of the same first bit line 300, and the first electrodes 224 of each memory cell 200 in the second memory cell column are connected to the second surface of the same first bit line 300.
  • This layout method can not only save the number of first bit lines 300, but also save occupied space, which is conducive to further improving storage density.
  • each memory cell column in the memory provided by the present application can be applicable to the logic circuit shown in FIG9.
  • W-BL is a first bit line commonly connected to the first electrodes of the memory cells in a memory cell column
  • R-BL is a second bit line connected to one end of the first semiconductor layer of the series connection of the memory cells in a memory cell column
  • SSL is a source selection line
  • DSL is a drain selection line
  • R-WL_0 to R-WL_M are first word lines respectively connected to the first gate of each memory cell in a memory cell column
  • W-WL_0 to W-WL_M are second word lines respectively connected to the third gate of each memory cell in a memory cell column.
  • M is the number of memory cells in a memory cell column.
  • Each memory cell 200 in any memory cell layer and each memory cell 200 at a corresponding position in other memory cell layers constitute a memory cell string, and the memory cells 200 at corresponding positions in different layers may refer to memory cells in different layers whose projections on the substrate overlap or approximately overlap.
  • the memory includes a plurality of memory cell strings arranged in an array along a first direction and a third direction, and the second gate 213 in the memory cell 200 in each memory cell string is isolated in the second direction.
  • Two adjacent memory cell strings in the first direction may be completely identical or mirror-symmetrical, which is not limited in the embodiments of the present application. There are two situations in which the two memory cell strings are mirror-symmetrical: the corresponding memory cells 200 in the two memory cell strings are adjacent through their respective first transistors 210; or the corresponding memory cells 200 in the two memory cell strings are adjacent through their respective second transistors 220.
  • the corresponding memory cells in the two memory cell strings refer to the memory cells in the two memory cell strings that are at the same or approximately the same distance from the substrate.
  • the corresponding memory cells 200 in the two memory cell strings are adjacent through their respective second transistors 220, in the arrangement direction of the first direction, the memory cell 200 in the previous memory cell string is a memory cell of the first type, and the corresponding memory cell 200 in the next memory cell string is a memory cell of the second type.
  • the memory cell 200 in the previous memory cell string is a memory cell of the second type
  • the corresponding memory cell 200 in the next memory cell string is a memory cell of the first type
  • the first gate 211 of each memory cell 200 is used to be connected to a first word line.
  • the first word line extends along the second direction.
  • the first gate 211 of each memory cell 200 in each memory cell string is used to be connected to the same first word line.
  • the same first word line is used to simultaneously apply voltage to the first gate 211 of each memory cell 200 in each memory cell string, which is conducive to reducing the number of first word lines to a certain extent.
  • the first gates 211 of the memory cells 200 in different memory cell strings are used to connect to different first word lines, so that voltages can be applied to the first gates 211 of the memory cells 200 in different memory cell strings using different first word lines, thereby improving flexibility in voltage application.
  • the first gates 211 of the memory cells 200 in the first memory cell string and the second memory cell string can be set to be connected to the same first word line, so that voltage can be applied to the first gates 211 of the memory cells 200 in the first memory cell string and the second memory cell string at the same time using one first word line, that is, the first gates 211 of the memory cells 200 in the first memory cell string and the second memory cell string share the same first word line.
  • This method is beneficial to further reduce the number of first word lines and improve the storage density of the memory.
  • the first word line extends along the second direction (that is, perpendicular to the substrate), the first gate 211 also extends along the second direction (that is, perpendicular to the substrate), and the first gate 211 of each memory cell 200 in each memory cell string is a part of the connected first word line.
  • the projection of the first gate 211 of each memory cell 200 in each memory cell string on the substrate falls within the projection of the connected first word line on the substrate.
  • Using the first gate 211 itself to form the first word line can reduce the material required for the layout of the first word line and improve the storage density of the memory.
  • the projection profile of the first gate 211 on the substrate is the cross-sectional profile of the first gate 211
  • the projection profile of the first word line on the substrate is the cross-sectional profile of the first word line.
  • the first gates 211 of the memory cells 200 in two memory cell strings (not shown) adjacent to each other in the first direction and corresponding to each other through their respective first transistors 210 share the same first word line, and the same first word line covers the first gates 211 of the memory cells 200 in the two memory cell strings.
  • the same first word line can be regarded as a longitudinal straight line perpendicular to the substrate, and the cross-sectional areas of the longitudinal straight line at different positions may be the same or different.
  • the third gate 221 of each memory cell 200 is used to be connected to a second word line.
  • a smaller number of second word lines can be used to control the third gates 221 of all memory cells 200 in the memory, thereby improving the storage density of the memory.
  • the second word line extends along the second direction.
  • the third gate 221 of each memory cell 200 in each memory cell string is used to be connected to the same second word line.
  • the same second word line is used to apply a voltage to the third gate 221 of each memory cell 200 in each memory cell string, which is conducive to reducing the number of second word lines to a certain extent.
  • the third gates 221 of the memory cells 200 in different memory cell strings are used to connect to different second word lines, so that voltages can be applied to the third gates 221 of the memory cells 200 in different memory cell strings using different second word lines, thereby ensuring flexibility in voltage application.
  • the second word line extends along the second direction (that is, perpendicular to the substrate)
  • the third gate 221 of the memory cell 200 also extends along the second direction (that is, perpendicular to the substrate)
  • the third gate 221 of each memory cell 200 in each memory cell string is a part of the connected second word line.
  • the projection of the third gate 221 of each memory cell 200 in each memory cell string on the substrate falls within the projection of the connected second word line on the substrate.
  • the third gates 221 of the memory cells 200 in a memory cell string can be directly connected in series to form a second word line, or connected in series through a connecting line to form a second word line.
  • the second word line covers the third gates 221 of the memory cells 200 in the memory cell string, and the second word line can be regarded as a vertical straight line perpendicular to the substrate, and the cross-sectional areas of the vertical straight line at different positions can be the same or different.
  • the memory may be prepared by integral molding.
  • the memory provided by the present application can be applied to the logic circuit shown in FIG10.
  • the memory includes N memory cell columns, each memory cell column includes M memory cells.
  • the N memory cell columns refer to N memory cell columns whose projections on the substrate overlap or approximately overlap in the memory, and each memory cell in any of the N memory cell columns constitutes a memory cell string with the memory cells at the corresponding positions in other memory cell columns, thereby constituting M memory cell strings, that is, in the logic circuit shown in FIG10, the memory includes M memory cell strings.
  • the first electrodes of the memory cells in each memory cell column are connected to a first bit line (W-BL) in common, one end of the first semiconductor layer of the series connection of the memory cells in each memory cell column is connected to a second bit line (R-BL), the first gates of the memory cells in each memory cell string are connected to a first word line (R-WL) in common, and the second gates of the memory cells in each memory cell string are connected to a second word line (W-WL) in common.
  • W-BL bit line
  • R-BL first bit line
  • R-WL first word line
  • W-WL second word line
  • W-BL_0 to W-BL_N are first bit lines to which the first electrodes of the memory cells in each of the N memory cell columns are respectively connected
  • R-BL_0 to R-BL_0 are second bit lines to which one end of the first semiconductor layer of the series connection of the memory cells in each of the N memory cell columns is respectively connected
  • SSL is a source line selection line
  • DSL is a drain selection line
  • R-WL_0 to R-WL_M are first word lines to which the first gates of the memory cells in each of the M memory cell strings are respectively connected
  • W-WL_0 to W-WL_M are second word lines to which the third gates of the memory cells in each of the M memory cell strings are respectively connected.
  • the other end of the first semiconductor layer of the series connection of the memory cells in each of the N memory cell columns is connected to the same source line.
  • a low voltage is applied to all second word lines to turn off all second transistors; the first word line connected to the target memory cell being read or the first gate of the first transistor of the target memory cell being read is at a preset voltage; a high voltage is applied to other first word lines, drain selection lines and source selection lines except the first word line connected to the target memory cell being read.
  • all W-WLs are provided with a low voltage to turn off all second transistors.
  • its word line or the first gate of the first transistor is provided with a preset voltage (the preset voltage is a voltage that only enables the stored data to be read, and an example of the preset voltage is shown in FIG11). If a high voltage or data "1" is stored in the second gate of the first transistor, the preset voltage can turn on the first transistor, but if a low voltage or data "0" is stored, the preset voltage keeps the first transistor off. All other R-WLs (i.e., the first gates of other first transistors) as well as SSL and DSL are given a high voltage to ensure that current (for data "1") can flow from the source line to the corresponding second bit line.
  • all storage cells in the same row may constitute a page, so that one page may be read each time, thereby increasing the reading speed.
  • a write operation is performed by selecting the corresponding second word line and first bit line of the target memory cell. For example, a high voltage is applied to the second word line connected to the target memory cell to turn on the second transistor of the target memory cell, and a high voltage or a low voltage is applied to the first bit line connected to the target memory cell to transfer the applied voltage to the second gate of the first transistor, thereby changing the threshold voltage of the first transistor and writing data.
  • a low voltage is applied to all second word lines except the second word line connected to the target memory cell to turn off the second transistors except the second transistor in the target memory cell; and a low voltage is applied to all first word lines to turn off all first transistors.
  • the write and read operations are separated, and the write operation can be faster because the signal is written to the second gate through only one transistor.
  • the write operation can be easily implemented by selecting the corresponding W-WL (second word line) and W-BL (first bit line) connected to the target cell. It should be noted that the refresh operation on the data is similar to the write operation.
  • a memory cell includes a read transistor ( T1 ) and a write transistor ( T2 ).
  • the read transistor includes a first gate (main gate) 211 and a second gate (back gate) 213, and the back gate is connected to the semiconductor layer (second semiconductor layer 222) of the write transistor; of course, if an additional electrode is made on the semiconductor layer, it can also be connected to the electrode, and the electrode is a source or a drain; alternatively, the non-channel area of the second semiconductor layer 222 can also be used as a source or a drain.
  • the read transistor and the write transistor are vertical transistors respectively, and the vertical transistor can be a planar transistor or a transistor with a three-dimensional ring structure.
  • the planar type can also be called planar
  • the three-dimensional ring structure can also be called a ring-shaped three-dimensional structure.
  • one of the read transistor and the write transistor is a planar transistor, and the other is a transistor with a ring-shaped three-dimensional structure.
  • the planar transistor is a transistor in which the key film layer is distributed in a planar manner, but the main surface is perpendicular to the substrate to form a vertical transistor
  • the transistor with a ring-shaped three-dimensional structure is a transistor in which the key film layer (such as a gate or semiconductor layer) is ring-shaped and the side surface is perpendicular to the substrate to form a vertical transistor.
  • the first gate (main gate) 211 and the second gate (back gate) 213 are respectively planar, and the semiconductor layer of the read transistor (the first semiconductor layer 212) is planar; the gate of the write transistor (the third gate 221 in the figure) is columnar, and the semiconductor layer of the write transistor (the second semiconductor layer 222 in the figure) is annular, and the annular semiconductor layer surrounds the side surface of the columnar gate.
  • the read transistor and the write transistor are located on the substrate and are adjacently distributed in a plane parallel to the substrate; the main gate and the main surface of the planar semiconductor layer are respectively perpendicular to the substrate; and the side surface of the columnar gate is perpendicular to the substrate.
  • the planar semiconductor layer has a first main surface and a second main surface facing each other, and a main gate and a back gate are respectively arranged on the first main surface and the second main surface;
  • the back gate has two main surfaces facing each other, one of which is parallel to and adjacent to the second main surface of the planar semiconductor layer, and the other main surface is in contact with the side surface of the annular semiconductor layer.
  • the semiconductor main surface of the planar semiconductor layer close to the first gate (main gate) 211 is the first main surface, and the main surface opposite thereto is the second main surface.
  • the main surface of the present application is the surface with a larger area in a multi-faceted structure.
  • a memory comprising:
  • a plurality of first conductive lines (such as 212 as shown in FIG. 5 ) and a plurality of second conductive lines (such as 300 as shown in FIG. 5 ) on a substrate extend in a first direction (corresponding to a third direction in FIG. 5 ) parallel to a top surface of the substrate, and are spaced apart in a second direction (corresponding to the first direction in FIG. 5 ) perpendicular to the first direction, and a first conductive line and a second conductive line constitute a conductive line group and are adjacently arranged, and the conductive lines within the dotted line box as shown in FIG. 5 constitute a conductive line group.
  • n storage cells are arranged on adjacent first and second wires and are spaced apart along a first direction; each storage cell array in each wire group is distributed on a substrate; and one storage cell includes a read transistor and a write transistor;
  • n read transistors (the first transistors in the above embodiment) are spaced apart on the first wire along the first direction
  • n write transistors (the second transistors in the above embodiment) connected to the n read transistors in a one-to-one correspondence are spaced apart on the second wire along the first direction;
  • the region of the first wire corresponding to each read transistor is the semiconductor region of each read transistor; the second wire is connected to the semiconductor region or the source region or the drain region of each write transistor.
  • a semiconductor region of a read transistor is formed on the first wire.
  • a metal wire is used as the first wire
  • a metal oxide semiconductor or a polysilicon semiconductor that wraps the first wire can be formed in the corresponding semiconductor region as the semiconductor region of the read transistor.
  • conductive silicon (such as Si n+) is formed as the first wire, and the semiconductor region to be formed of the first wire is doped and modified to obtain a region with semiconductor characteristics as the semiconductor region of the read transistor.
  • the memory further includes a plurality of first word lines (corresponding to 211 in FIG. 1 and FIG. 5 ), extending in a direction perpendicular to the substrate and arranged at intervals in a first direction;
  • Each first word line corresponds to a semiconductor region of each read transistor arranged in the first conductive line and is insulated from the semiconductor region by a dielectric layer.
  • the region corresponding to the semiconductor region of each read transistor in the first word line is a gate region of each read transistor, and the gate region is provided with a main gate of the read transistor.
  • the memory further comprises:
  • a plurality of back gates (such as the second gate 213 shown in FIG. 1 and FIG. 5 ) extend in a direction perpendicular to the substrate and are sequentially spaced apart in the first direction; the plurality of back gates are respectively disposed in the semiconductor region of each read transistor and are disposed opposite to the gate region of each read transistor.
  • the memory further comprises:
  • a plurality of wraparound semiconductor layers (such as 222 shown in FIG. 1 and FIG. 5 ) of a plurality of write transistors are respectively extended in a direction perpendicular to the substrate and are arranged at intervals in a first direction;
  • a plurality of columnar gates of a plurality of write transistors (such as the third gate 221 shown in FIG. 1 and FIG. 5 ), respectively extending in a direction perpendicular to the substrate and arranged at intervals in the first direction;
  • Each surrounding semiconductor layer is disposed around a columnar gate of a corresponding write transistor
  • the side surfaces of the columnar gate and the surrounding semiconductor layer are perpendicular to the substrate;
  • One area of the side surface of each surrounding semiconductor layer is connected to the second wire, and another area of the side surface of each surrounding semiconductor layer is connected to the back gate of each read transistor in a one-to-one correspondence.
  • a main gate (a first gate 211 as shown in FIG. 5 ), a first conductive line (212 as shown in FIG. 5 ), a back gate (213 as shown in FIG. 5 ), a surrounding semiconductor layer (222 as shown in FIG. 5 ), and a second conductive line (300 as shown in FIG. 5 ) belonging to a storage unit are arranged in sequence.
  • the first wire and the second wire are planar structures extending perpendicularly to the substrate and having a set width, respectively.
  • the planar structures have a first main surface and a second main surface, the first main surface and the second main surface are side surfaces, and the second main surface of the first wire and the first main surface of the second wire are adjacently arranged.
  • Each main grid is arranged on the first main surface of the first wire and is insulated from the first wire;
  • Each back gate is arranged on the second main surface of the first conductive line and is insulated from the first conductive line.
  • each surrounding semiconductor layer is disposed between the second conductive line and each back gate, and each surrounding semiconductor layer is disposed on the first main surface of the second conductive line and connected to the first main surface.
  • the arrangement of the storage units in one conductive line group is mirror-symmetric to the arrangement of the storage units corresponding to the adjacent conductive line group and they share the second conductive line;
  • the second main surface of the second conductive line is connected to each surrounding semiconductor layer in each memory cell corresponding to the adjacent conductive line group.
  • a second conductive wire (300 as shown in FIG. 5 ) is provided every two first conductive wires, the second conductive wire and two first conductive wires adjacent to the second conductive wire (212 as shown in FIG. 5 ) form a conductive wire group, and the second conductive wire is shared by storage units corresponding to the two first conductive wires.
  • the embodiment of the present application also provides an electronic device, as shown in FIG12, the electronic device includes the above-mentioned storage unit or memory.
  • the electronic device provided in the present application may be an electronic device including the storage unit or memory described in any of the above-mentioned embodiments.
  • the electronic device may be a terminal device, such as a chip, or a product encapsulated with a chip, etc.

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Abstract

存储单元、存储器和电子设备，属于半导体技术领域。该存储单元(200)包括沿第一方向排列的第一晶体管(210)和第二晶体管(220)；第一晶体管(210)包括沿第一方向排列的第一栅极(211)、第一半导体层(212)和第二栅极(213)；第二晶体管(220)包括第三栅极(221)以及环绕第三栅极(221)的第二半导体层(222)，第二半导体层(222)包括沟道(223)以及通过沟道(223)连接的第一电极(224)和第二电极(225)，第二电极(225)与第二栅极(213)连接。

Description

存储单元、存储器和电子设备
本申请要求于2022年10月18日提交的申请号为202211275961.4、发明名称为“存储单元、存储器和电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及半导体技术领域，特别涉及一种存储单元、存储器和电子设备。
背景技术
随着半导体技术的发展，存储器的类型越来越多，三维与非门(Three Dimensional Not AND，3D NAND)存储器便是其中的一种。3D NAND存储器包括多个存储单元，双晶体管无电容(2 Transistor 0 Capacitor，2T0C)存储单元的应用越来越广泛。
发明内容
本申请实施例提供了一种存储单元、存储器和电子设备，可用于减小存储单元尺寸。所述技术方案如下：
一方面，本申请实施例提供了一种存储单元，所述存储单元包括沿第一方向排列的第一晶体管和第二晶体管；所述第一晶体管包括沿所述第一方向排列的第一栅极、第一半导体层和第二栅极，所述第一栅极沿第二方向延伸，所述第一半导体层沿第三方向延伸，所述第一方向和所述第三方向为平行于衬底且相互垂直的两个方向，所述第二方向为垂直于所述衬底的方向；所述第二晶体管包括第三栅极以及环绕所述第三栅极的第二半导体层，所述第三栅极沿所述第二方向延伸，所述第二半导体层包括沟道以及通过所述沟道连接的第一电极和第二电极，所述第二电极与所述第二栅极连接。
在一种可能实现方式中，所述沟道为水平沟道。
在一种可能实现方式中，所述第二半导体层具有垂直于衬底的第一表面、第二表面、第三表面和第四表面，所述第二半导体层的第一表面和第二表面垂直于所述第一方向，所述第二半导体层的第二表面比第一表面远离所述第一晶体管，所述第二半导体层的第三表面和第四表面垂直于所述第三方向；所述第二栅极包裹所述第二半导体层的第一表面整体以及包裹所述第二半导体层的第三表面和第四表面的靠近所述第一晶体管的一部分；一个第一位线包裹所述第二半导体层的第二表面整体以及包裹所述第二半导体层的第三表面和第四表面的远离所述第一晶体管的一部分。
在一种可能实现方式中，所述第一栅极和所述第一半导体层之间存在第一栅极绝缘层，所述第一半导体层和所述第二栅极之间存在第二栅极绝缘层；所述第一栅极、所述第一栅极绝缘层、所述第一半导体层、所述第二栅极绝缘层和所述第二栅极均具有垂直于所述第一方向的第一表面和第二表面，同一部件的第一表面比第二表面远离所述第二晶体管；所述第一栅极的第二表面与所述第一栅极绝缘层的第一表面贴合，所述第一栅极绝缘层的第二表面与所述第一半导体层的第一表面贴合，所述第一半导体层的第二表面与所述第二栅极绝缘层的第一表面贴合，所述第二栅极绝缘层的第二表面与所述第二栅极的第一表面贴合。
在一种可能实现方式中，所述第二半导体层的材料为金属氧化物半导体。
在一种可能实现方式中，所述第二半导体层具有与一个第一位线连接的第一连接区、与所述第二栅极连接的第二连接区以及除所述第一连接区和所述第二连接区外的栅极控制区，所述栅极控制区的导电性通过所述第三栅极控制。
另一方面，还提供了一种存储器，所述存储器包括多个存储单元层，每个存储单元层包括多个上述任一所述的存储单元，所述多个存储单元层沿所述第二方向排布；每个存储单元 层包括沿所述第一方向排布的多个存储单元列，每个存储单元列中的多个存储单元通过各自的第一半导体层串联，串联的第一半导体层用于与一个第二位线连接；每个存储单元列中的各个存储单元的第一电极用于与同一个第一位线连接；任一存储单元层中的每个存储单元与其他存储单元层中对应位置的各个存储单元构成一个存储单元串，每个存储单元串中的各个存储单元的第一栅极用于与同一个第一字线连接，每个存储单元串中的各个存储单元的第三栅极用于与同一个第二字线连接。
在一种可能实现方式中，在所述第一方向相邻的第一存储单元列和第二存储单元列中的各个存储单元的第一电极用于与同一个第一位线连接；其中，所述第一存储单元列和所述第二存储单元列镜像对称，且所述第一存储单元列中的存储单元和所述第二存储单元列中的相应存储单元通过各自的第二晶体管相邻。
在一种可能实现方式中，所述同一个第一位线位于所述第一存储单元列和所述第二存储单元列之间，所述同一个第一位线具有垂直于所述第一方向的第一表面和第二表面；所述第一存储单元列中的各个存储单元的第一电极与所述同一个第一位线的第一表面连接，所述第二存储单元列中的各个存储单元的第一电极与所述同一个第一位线的第二表面连接。
在一种可能实现方式中，在所述第一方向相邻的第一存储单元串和第二存储单元串中的各个存储单元的第一栅极用于与同一个第一字线连接；其中，所述第一存储单元串和所述第二存储单元串镜像对称，且所述第一存储单元串中的存储单元和所述第二存储单元串中的相应存储单元通过各自的第一晶体管相邻。
在一种可能实现方式中，所述第一字线沿所述第二方向延伸，每个存储单元串中的各个存储单元的第一栅极均为所连接的第一字线的一部分。
在一种可能实现方式中，所述第二字线沿所述第二方向延伸，每个存储单元串中的各个存储单元的第三栅极均为所连接的第二字线的一部分。
另一方面，还提供了一种存储单元，包括：读晶体管和写晶体管，所述读晶体管包括主栅和背栅，所述背栅与所述写晶体管的半导体层、源极或漏极相连；
所述读晶体管和所述写晶体管分别为垂直晶体管；
所述主栅和所述背栅分别为面状、所述读晶体管的半导体层为面状；所述写晶体管的栅极为柱状，所述写晶体管的半导体层为环形，所述环形的半导体层环绕所述柱状的栅极的侧表面。
在一种可能实现方式中，所述读晶体管和写晶体管位于衬底上在平行于衬底的平面内相邻分布；所述主栅和面状的半导体层的主表面分别垂直于所述衬底；所述柱状的栅极的所述侧表面垂直于所述衬底。
在一种可能实现方式中，所述面状的半导体层具有相向的第一主表面和第二主表面，所述第一主表面和第二主表面上分别设置有所述主栅和背栅；所述背栅具有相向的两个主表面，其中一个主表面与所述面状半导体层的第二主表面平行且相邻，另一个主表面与所述环形半导体层的侧表面接触。
另一方面，还提供了一种存储器，所述存储器包括：
衬底；
所述衬底上的多条第一导线和多条第二导线，所述多条第一导线和多条第二导线在平行于所述衬底的顶表面的第一方向延伸，且在垂直所述第一方向的第二方向间隔设置，且一条第一导线和一条第二导线构成一个导线组相邻设置；
每个所述导线组中，所述相邻设置的第一导线和第二导线上设置有沿第一方向间隔分布的n个存储单元；各导线组中的各存储单元阵列分布在所述衬底上；所述一个存储单元包括一个读晶体管和一个写晶体管；
其中，所述第一导线上沿着所述第一方向间隔分布有n个读晶体管，所述第二导线上沿着所述第一方向间隔分布有与所述n个读晶体管一一对应连接的n个写晶体管；
其中，所述第一导线对应于每个读晶体管的区域为所述每个读晶体管的半导体区域；所 述第二导线对应于每个写晶体管的区域与所述每个写晶体管的半导体区域或源极区或漏极区连接。
在一种可能实现方式中，所述存储器还包括：
多条第一字线，在垂直于衬底的方向延伸且在所述第一方向间隔排列；
所述各第一字线分别对应设置于所述第一导线的所述每个读晶体管的半导体区域且与所述半导体区域通过介质层绝缘，所述第一字线中对应于所述每个读晶体管的半导体区域的区域为每个所述读晶体管的栅极区域，所述栅极区域设置有所述读晶体管的主栅。
在一种可能实现方式中，所述存储器还包括：
多个背栅，沿着垂直衬底的方向延伸且在所述第一方向上依次间隔排列；所述多个背栅分别设置在所述每个读晶体管的半导体区域且与每个所述读晶体管的栅极区域相向设置。
在一种可能实现方式中，所述存储器还包括：
多个写晶体管的多个环绕型半导体层，分别沿着垂直于所述衬底的方向延伸且在所述第一方向间隔排列；
多个写晶体管的多个柱状栅极，分别沿着垂直于所述衬底的方向延伸且在所述第一方向间隔排列；
每个所述环绕型半导体层环绕对应的写晶体管的柱状栅极设置；
所述柱状栅极和所述环绕型半导体层的侧表面垂直于所述衬底；
各所述环绕型半导体层的侧表面的一个区域与所述第二导线连接，各所述环绕型半导体层的侧表面的另一个区域分别与所述各读晶体管的背栅一一对应连接。
在一种可能实现方式中，在垂直于所述第一方向的第二方向上，属于一个存储单元的所述主栅、所述第一导线、所述背栅、所述环绕型半导体层、所述第二导线依次排列设置。
在一种可能实现方式中，所述第一导线和第二导线分别为垂直衬底延伸设定宽度的面状结构，所述面状结构具有第一主表面和第二主表面，所述第一主表面和第二主表面为侧表面，所述第一导线的第二主表面和所述第二导线的第一主表面相邻设置；
各所述主栅设置于所述第一导线的第一主表面上与所述第一导线绝缘；
各所述背栅设置于所述第一导线的第二主表面上与所述第一导线绝缘。
在一种可能实现方式中，各所述环绕型半导体层设置于所述第二导线和各所述背栅之间，且各所述环绕型半导体层设置于所述第二导线的第一主表面上与所述第一主表面连接。
在一种可能实现方式中，所述一个导线组的各存储单元的排布与相邻的导线组对应的各存储单元的排布镜像对称且共用所述第二导线；
所述第二导线的第二主表面与所述相邻的导线组对应的各存储单元中的各环绕型半导体层连接。
在一种可能实现方式中，每间隔两条第一导线设置有一条第二导线，所述第二导线和与所述第二导线相邻的两条第一导线构成一个导线组，所述第二导线由所述两条第一导线对应的存储单元共用。
另一方面，还提供了一种电子设备，该电子设备包括上述任一所述的存储单元或存储器。
本申请提供的新型结构的2T0C设计方案，第二晶体管的栅极为垂直结构且与第一晶体管不堆叠，可以减小垂直衬底方向存储单元尺寸，且可以方便制作结构紧凑的2T0C存储单元的3D堆叠，简化工艺，降低成本。
此外，存储单元中的两个晶体管是沿平行于衬底的第一方向排列的，有利于节省存储单元在垂直于衬底的方向上的占用空间，从而提高存储单元在垂直于衬底方向上的集成密度，进而提高存储器的存储密度。
附图说明
图1是本申请实施例提供的一种存储单元的立体结构示意图；
图2是本申请实施例提供的一种存储单元的截面示意图；
图3是本申请实施例提供的一种存储单元的截面示意图；
图4是本申请实施例提供的一种存储单元适用的逻辑电路的示意图；
图5是本申请实施例提供的一种存储器的截面示意图；
图6是本申请实施例提供的一种存储器的截面示意图；
图7是本申请实施例提供的一种存储单元列的结构示意图；
图8是本申请实施例提供的一种存储单元列的截面示意图；
图9是本申请实施例提供的一种存储单元列适用的逻辑电路的示意图；
图10是本申请实施例提供的一种存储器适用的逻辑电路的示意图；
图11是本申请实施例提供的一种晶体管输出特性曲线的示意图；
图12是本申请实施例提供的一种电子设备的结构示意图。
图中的附图标记分别表示为：
200-存储单元；210-第一晶体管；220-第二晶体管；211-第一栅极；212-第一半导体层；213-第二栅极；221-第三栅极；222-第二半导体层；223-沟道；224-第一电极；225-第二电极；300-第一位线。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。但是应该理解，这些描述只是示例性的，而并非要限制本申请的范围。
在附图中示出了根据本申请实施例的各种结构示意图。这些附图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。附图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在申请中使用的术语仅仅是为了描述具体实施例，而并非意在限制本申请。在本申请中使用的术语“包括”、“包含”等表明了特征、步骤、操作和/或部件的存在，但是并不排除存在或添加一个或多个其他特征、步骤、操作或部件。在本申请中，除非另有明确的规定和限定，术语“相连”“连接”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接或可以互相通讯；可以是直接连接，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。本申请中使用的术语“层”指包括具有厚度的区域的材料部分。层可以水平地、垂直地和/或沿锥形表面延伸。
本申请中使用的术语“衬底”是用于支撑存储器的基板，衬底上可以制备一个或多个膜层。衬底的类型可以为绝缘体衬底、半导体衬底、导电体衬底等。其中，绝缘体衬底可以包括玻璃衬底、石英衬底、蓝宝石衬底、氧化锆衬底、树脂衬底等。半导体衬底可以包括以硅或锗等为材料的半导体衬底、或者碳化硅、硅锗、砷化镓、磷化铟、氧化锌或氧化镓等的化合物半导体衬底等。导电体衬底可以包括石墨衬底、金属衬底、合金衬底、导电树脂衬底等。
本申请中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施。应当理解的是，在本文中提及的“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。
存储器包括多个存储单元，本申请实施例针对2T0C存储单元，提供一种新型结构的2T0C，在空间上更加有利于高密度存储单元的设计，在工艺上更有利于产业化的存储单元，以及3D存储器。该存储单元为如图4所示的2T0C逻辑电路对应的存储单元。其中一个晶体管为读晶体管，另一晶体管为写晶体管。
图1示出了本申请实施例提供的存储单元的立体结构示意图，图2和图3示出了本申请实施例提供的存储单元的截面示意图，其中，图2所示的截面示意图是根据图1中的a平面截断图1所示的存储单元后观察到的截面的示意图，图3所示的截面示意图是图2中示出的A-A’对应的截面的示意图。
如图1至图3所示，本申请实施例提供的存储单元200包括位于支撑面(比如衬底或衬底上的其他膜层)上在支撑面内沿第一方向排列且相连接的第一晶体管210和第二晶体管220。第一晶体管210为读晶体管(T1)，第二晶体管220为写晶体管(T2)。
图1中的第一方向和第三方向交叉且平行于支撑面的上表面，第二方向垂直支撑面。示例性地，第一方向和第三方向相互垂直。
位于支撑面的上表面的第一晶体管210包括沿第一方向依次排列的第一栅极211、第一半导体层212和第二栅极213。其中，第一栅极211与字线连接，用于控制第一晶体管210的开启或关闭，第二栅极213为背栅，用于形成如图4所示的存储电容C BG。
第一半导体层212具有两个主平面，两个主平面垂直于支撑面。第一栅极211和第二栅极213分别位于第一半导体层212的两个主平面上且与第一半导体层212通过绝缘层绝缘。
第二晶体管220包括沿着垂直支撑面的方向延伸的第三栅极221，第三栅极221具有垂直于支撑面的侧壁(或者称为侧表面)；第二晶体管220包括环绕第三栅极221的侧壁的第二半导体层222，第三栅极221和第二半导体层222这二者之间通过绝缘层绝缘。
第二半导体层222为环绕型结构，第二半导体层222的横截面为环形，示例性的，第二半导体层222的横截面为如圆形、方形、椭圆形等。
第二半导体层222具有垂直于支撑面的侧壁。侧壁上具有间隔分布的两个区域，其中之一区域与第二栅极213连接，另一区域与第一位线300连接。
第二半导体层222包括沟道223以及通过沟道223连接的第一电极224和第二电极225。其中，第一电极224为第二半导体层222中与第一位线300连接的区域，第二电极225为第二半导体层222中与第二栅极213连接的区域。这样，也可以理解为第二电极225与第二栅极213连接，第一电极224用于与一个第一位线300连接。这样，第一电极224和第二电极225之间的间隔区域为沟道区域。
第一电极224和第二电极225其中之一可以理解为源极，另一可以理解为漏极。在判断哪一个是源极哪一个是漏极时，与该晶体管中电流的流向有关，该处不做限定。
该一个第一位线300可以用于向第一电极224施加电压；第一栅极211用于与一个第一字线连接，该一个第一字线用于向第一栅极211施加电压；第三栅极221用于与一个第二字线连接，该一个第二字线用于向第三栅极221施加电压。
第一字线和第二字线均沿垂直支撑面的方向延伸，用于在三维空间上形成3D结构的存储阵列。比如，在纵向方向，存储单元200中的2T0C的结构周期性分布，则，第一字线为多个第一晶体管210共用的字线，第二字线为多个第二晶体管220共用的字线。
进一步的，第一栅极211为第一字线的一部分，第三栅极221为第二字线的一部分，此时，第一栅极211与第一字线在支撑面上的投影重叠，第三栅极221与第二字线在支撑面上的投影重叠，此时，可提高存储单元的密度。
第一半导体层212和第一位线300在支撑面内沿第三方向延伸且间隔分布。这样，在第三方向上，可周期性分布第一晶体管210和第二晶体管220，在第三方向上，各第一晶体管210的第一半导体层212可以共用一个公共的半导体层，也可以理解为在第三方向分布一条半导体层，该半导体层具有两个主表面，该主表面为置于支撑面上的两个侧面。两个侧面上周期性地间隔分布有多对栅极，每一对栅极为相对设置的第一栅极211和第二栅极213，第一栅极211和第二栅极213分别设置在该两个侧面并与这两个侧面的半导体层相绝缘，由此构成多个串联的第一晶体管210，且该第一晶体管210为具有主栅和背栅的晶体管。
上述2T0C晶体管，在此种结构的存储单元下，与第二晶体管220的第一电极224连接的一个第一位线300能够向第二半导体层222施加电压，由于第二晶体管220的第二半导体 层222与第一晶体管210的第二栅极213连接，所以向第二半导体层222施加的电压能够写入第一晶体管210的第二栅极213。第二栅极213是第一晶体管210的两个栅极中的一个栅极(背栅)，第二栅极213中写入电压(高压或低压等)后，能够使用第二栅极213的电势来改变第一晶体管210的阈值电压，通过改变第一晶体管210的阈值电压，能够实现数据的写入，例如，可以实现多个阈值电压的多位存储。
也就是说，在本申请实施例提供的存储单元下，数据写入的实现仅需通过第一位线300施加电压即可，无需形成高电压差，更无需依赖电荷的隧穿，数据写入的要求较低，从而使得数据写入更加容易实现，有利于提高数据写入的速度，进而提高存储器的性能。本申请实施例提供的存储单元能够为实现高速高密度的存储器奠定基础，使用该存储单元制作的存储器的数据写入速度较相关技术中的存储器有较大的提高。
本申请提供的新型结构的2T0C设计方案，第二晶体管的栅极为垂直结构且与第一晶体管不堆叠，可以方便制作结构紧凑的2T0C存储单元的3D堆叠。一些实施例中，可以减小垂直衬底方向存储单元尺寸，且，简化工艺，降低成本。
此外，存储单元中的两个晶体管是沿平行于衬底的第一方向排列的，有利于节省存储单元在垂直于衬底的方向上的占用空间，从而提高存储单元在垂直于衬底方向上的集成密度，进而提高存储器的存储密度。
示例性地，本申请实施例提供的存储单元适用于图4所示的逻辑电路。在图4所示逻辑电路中，存储单元包括第一晶体管(T1)和第二晶体管(T2)。其中，T1为双栅极晶体管，T1的第一栅极(也可以称为主栅极)用于与一个第一字线(R-WL)连接，T1的第二栅极(也可以称为背栅极，简称BG)与T2的一个电极(源极或漏极)连接。T1的背栅极与T1的沟道以及二者之间的介电层能够形成用于存储电信号的电容(C BG)。T2除了有一个栅极还有两个电极，两个电极其中之一为源极，另一为漏极。T2的一个电极与上述背栅连接，另一个电极用于与一个第一位线(W-BL)连接，T2的栅极(也即第三栅极)用于与一个第二字线(W-WL)连接。
在一种可能实现方式中，第一晶体管210或第二晶体管220可以为N型MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor，金属-氧化物-半导体场效应晶体管)，可以为P型MOSFET。在示例性实施例中，第一晶体管210和/或第二晶体管220是一种耗尽型N型MOSFET。
示例性地，第一晶体管210的第一栅极211用于控制第一晶体管210的沟道的状态(导通或不导通)，还可以称为主控制栅；第一晶体管210的第二栅极213用于存储数据，还可以称作背栅或存储栅。示例性地，由于存储单元200中的数据写入是通过在第一晶体管210中的第二栅极213上写入电压(高压或低压)实现的，所以，第一晶体管210还可以称为存储晶体管，该存储晶体管还支持数据读取，从而还能够称为读取晶体管。第一晶体管210为一种双栅晶体管，此种双栅晶体管中的背栅上的电势能够用来改变阈值电压。示例性地，第一晶体管210中的第二栅极213的功能与浮栅型晶体管中的浮栅以及电荷捕获型晶体管中的电荷捕获层的功能类似。
第二晶体管220用于将高压或低压写入第一晶体管210中的第二栅极213，因此第二晶体管220还可以称为写入晶体管。
本申请实施例对第一晶体管210和第二晶体管220中的各个部件的具体形状以及尺寸不加以限定，可以根据实际的需求灵活调整。
示例性地，第一晶体管210中的主栅极，在该申请两个晶体管的方案中为第一栅极211，在垂直于衬底的方向延伸，也即沿第二方向延伸。
第一栅极211在不同位置的横截面的面积可以相同，也可以不同，这与实际的制备工艺有关。其中，第一栅极211在任一位置的横截面是指利用平行于衬底的平面从该任一位置处截断第一栅极211后得到的平面。例如，如图1至图3所示，第一栅极211在不同位置的横截面的面积相同。
示例性地，第二晶体管220中的栅极，在该申请两个晶体管的方案中为第三栅极221，在垂直于衬底的方向延伸，也即沿第二方向延伸。第三栅极221在不同位置的横截面的面积可以相同，也可以不同，这与实际的制备工艺有关。其中，第三栅极221在任一位置的横截面是指利用平行于衬底的平面从该任一位置处截断第三栅极221后得到的平面。例如，如图1至图3所示，第三栅极221在被第二半导体层222包裹的位置的横截面的面积大于在未被第二半导体层222包裹的位置的横截面的面积。
第一晶体管210和第二晶体管220沿第一方向排列，即在平行于衬底的方向上紧邻设置且相互连接，也就是说，属于一个存储单元200的第一晶体管210和第二晶体管220在垂直于衬底的方向上无堆叠，有利于节省存储单元在垂直于衬底的方向上的占用空间，从而提高存储单元在垂直于衬底方向上的集成密度，进而提高存储器的存储密度。
需要说明的是，第一晶体管210和第二晶体管220沿第一方向排列，可以是指从第一晶体管210到第二晶体管220的排列方向为第一方向，也可以是指从第二晶体管220到第一晶体管210的排列方向为第一方向。同理地，第一栅极211、第一半导体层212和第二栅极213沿第一方向排列，可以是指从第一栅极211到第二栅极213的排列方向为第一方向，也可以是指从第二栅极213到第一栅极211的排列方向为第一方向。示例性地，若从第一晶体管210到第二晶体管220的排列方向为第一方向，则从第一栅极211到第二栅极213的排列方向为第一方向；若从第二晶体管220到第一晶体管210的排列方向为第一方向，则从第二栅极213到第一栅极211的排列方向为第一方向。
第一晶体管210中的第一栅极211与第一半导体层212之间绝缘，也即第一栅极211和第一半导体层212之间存在栅极绝缘层(称为第一栅极绝缘层)。第二栅极213与第一半导体层212之间绝缘，也即第二栅极213和第一半导体层212之间存在栅极绝缘层(称为第二栅极绝缘层)。
示例性地，第一晶体管210和第二晶体管220均是一种垂直晶体管，第一晶体管210中的第一栅极211、第一栅极绝缘层、第一半导体层212均垂直于衬底。第一栅极211、第一栅极绝缘层、第一半导体层212、第二栅极绝缘层和第二栅极213在平行于衬底的方向(第一方向)上紧邻设置且相互连接，也就是说，属于一个存储单元200的第一晶体管210的各个部件在垂直于衬底的方向上无堆叠。相比于环状的第二半导体层222，第一晶体管210的各个部件可视为平面状。
示例性地，第一栅极211、第一栅极绝缘层、第一半导体层212、第二栅极绝缘层和第二栅极213均具有垂直于第一方向的第一表面和第二表面，其中，同一部件的第一表面比第二表面远离第二晶体管220。也就是说，第一栅极211的第一表面比第一栅极211的第二表面远离第二晶体管220，第一栅极绝缘层的第一表面比第一栅极绝缘层的第二表面远离第二晶体管220，第一半导体层212的第一表面比第一半导体层212的第二表面远离第二晶体管220，第二栅极绝缘层的第一表面比第二栅极绝缘层的第二表面远离第二晶体管220，第二栅极213的第一表面比第二栅极213的第二表面远离第二晶体管220。
第一栅极211、第一栅极绝缘层、第一半导体层212、第二栅极绝缘层和第二栅极213在平行于衬底的方向(第一方向)上紧邻设置且相互连接具体是指：第一栅极211的第二表面与第一栅极绝缘层的第一表面贴合，第一栅极绝缘层的第二表面与第一半导体层212的第一表面贴合，第一半导体层212的第二表面与第二栅极绝缘层的第一表面贴合，第二栅极绝缘层的第二表面与第二栅极213的第一表面贴合。
通过第一栅极211、第一栅极绝缘层、第一半导体层212、第二栅极绝缘层和第二栅极213在平行于衬底的方向(第一方向)上紧邻设置且相互连接的方式设置存储单元200中的第一晶体管210，有利于节省第一晶体管210占用的空间，提高存储单元200的集成密度，进而提高存储器的存储密度。
第二晶体管220中的第三栅极221和第二半导体层222之间绝缘，也即第三栅极221和第二半导体层222之间存在栅极绝缘层(称为第三栅极绝缘层)。需要说明的是，由于第二 半导体层222环绕第三栅极221，所以，第三栅极221和第二半导体层222之间的第三栅极绝缘层同样环绕第三栅极221，以保证第三栅极221与第二半导体层222之间绝缘。在示例性实施例中，第二晶体管220是一种环栅(CAA，Channel-All-Around)晶体管。
在示例性实施例中，第二半导体层222中的第二电极225嵌入第二栅极213中，以实现与第二栅极213的连接；第二半导体层222中的第一电极224嵌入对应的一个第一位线300中，以实现与对应的一个第一位线300的连接。也就是说，如图1至图3所示，第二半导体层222中的嵌入第二栅极213的部分为第二电极225，第二半导体层222中的嵌入对应的一个第一位线300的部分为第一电极224，第二半导体层222中除第一电极224和第二电极225外的其他部分为沟道223。
在一些实施例中，第二半导体层222中的第二电极225为第二晶体管220的漏极，第一电极224为第二晶体管220的源极；在另一些实施例中，第二半导体层222中的第一电极224为第二晶体管220的漏极，第二电极225为第二晶体管220的源极。也就是说，第二晶体管220的源极和漏极在一些情况下可以互相调换。实际应用中可以按照电流的方向识别第二晶体管220的源极和漏极。
在示例性实施例中，如图1和图2所示，第二半导体层222中的沟道223为水平沟道。一些实施例中，可以理解为沟道长度方向在平行于衬底的平面内，其中，沟道长度方向是指第一电极224和第二电极225之间的导电路径的方向。
本申请实施例所述的水平沟道可以理解为非垂直沟道的一种，大体上或大约，沟道在平行衬底的平面内延伸，可以理解为沟道的长度方向或载流子的传输方向在与衬底平行的平面内的实施例。
沟道与衬底平行可以是大约平行，误差可以在一定范围内，如，10度以内，在实际应用中视有效源极和漏极之间的相对位置而定，比如，源极和漏极的纵截面图中电极的上和/或下表面的外轮廓在一个平面上，且该平面大约与衬底主表面平行。
在一些实施方式中，该水平沟道可以为平面型沟道(planar channel)，也可以为环形沟道，具体视第二半导体层222、源极、漏极的形状以及相对位置等因素而定。
本申请实施例中的第二晶体管220为栅极沿垂直方向延伸且沟道为水平沟道的晶体管，可以减小垂直衬底方向的存储单元尺寸，且可以方便制作结构紧凑的2T0C存储单元的3D堆叠，简化工艺。
示例性地，第二半导体层222中的沟道223可以包括至少一个沟道层，例如，包括一个沟道层，或者包括沿第三方向并列排布的两个或两个以上沟道层等。不同沟道层的尺寸可以相同，也可以不同，这与实际的制备工艺有关。
例如，沟道223包括沿第三方向并列排布的两个沟道层，这两个沟道层的长度相同，这两个沟道层的宽度也相同，其中，任一沟道层的宽度为第二半导体层222在第二方向上的尺寸，任一沟道层的长度为第二半导体层222中的第一电极224和第二电极225在第一方向上的距离。例如，任一沟道层的长度可以为图2中的L标记的长度，L标记的长度可视为第二半导体层222中的第一电极224和第二电极225在第一方向上的最短距离。
一些实施方式中，沟道223与所连接的第一电极224和第二电极225的导电性不同。比如，沟道223为金属氧化物半导体，第一电极224和第二电极225的导电性高于金属氧化物半导体，实际应用中可以通过测试导电性区别。沟道223连接的第一电极224和第二电极225的主体材料可以相同，导电性较高的区域可以通过掺杂实现。
一些实施方式中，沟道223与所连接的第一电极224和第二电极225的导电性相同。比如，沟道223、第一电极224和第二电极225均为多晶硅或金属氧化物半导体，其导电性可以接近导体或半导体，可以通过控制栅极控制晶体管关断或打开。在制备时，沟道223、第一电极224和第二电极225可以在相同工艺条件下通过一次工艺形成，因此，该实施例中，沟道223、第一电极224和第二电极225在界限上区分不是特别明显，仅仅是从功能角度提出沟道和电极的概念。
换言之，第二半导体层222具有与一个第一位线300连接的第一连接区、与第二栅极213连接的第二连接区以及除第一连接区和第二连接区外的栅极控制区，其中，栅极控制区的导电性通过第三栅极221控制。例如，当第三栅极221上施加较大的电压时，栅极控制区具有较强的导电性，当第三栅极221上施加较小的电压时，栅极控制区具有较弱的导电性。通过控制栅极控制区的导电性，可以实现对第二晶体管220的关断或打开。第一连接区、第二连接区和栅极控制区可以由相同的半导体材料制备得到，也可以由不同的半导体材料制备得到。示例性地，上述第一连接区在功能上可以称为第一电极，上述第二连接区在功能上可以称为第二电极，上述栅极控制区在功能上可以称为沟道。
如图1至图3所示，第二半导体层222具有垂直于衬底的四个外表面，分别称为第一表面、第二表面、第三表面和第四表面，其中，第二半导体层222的第一表面和第二表面垂直于第一方向，第二半导体层222的第三表面和第四表面垂直于第三方向。第二半导体层222的第二表面比第二半导体层222的第一表面远离第一晶体管210。
需要说明的是，虽然图1至图3中示出的第二半导体层222是具有圆角的矩形环柱状，但本申请实施例并不局限于此，也可以将第二半导体层222制备成直角的矩形环柱状，这与实际制备工艺有关。示例性地，对于第二半导体层222是具有圆角的矩形环柱状的情况，第二半导体层222具有的四个垂直于衬底的外表面均包括圆角部分对应的表面，此时，第二半导体层222的第一表面和第二表面垂直于第一方向可以是指除圆角部分对应的表面外的其他地方垂直于第一方向，第二半导体层222的第三表面和第四表面垂直于第三方向可以是指除圆角部分对应的表面外的其他地方垂直于第三方向。
根据图1至图3可知，第二栅极213包裹第二半导体层222的第一表面整体以及包裹第二半导体层222的第三表面和第四表面的靠近第一晶体管210的一部分；一个第一位线300包裹第二半导体层222的第二表面整体以及包裹第二半导体层222的第三表面和第四表面的远离第一晶体管210的一部分。
示例性地，第二半导体层222的第三表面中被第二栅极213和一个第一位线300包裹的两部分占据第三表面的整体，或者占据第三表面的部分，本申请实施例对此不加以限定。第二半导体层222的第四表面中被第二栅极213和一个第一位线300包裹的两部分占据第四表面的整体，或者占据第四表面的部分，本申请实施例对此不加以限定。
例如，如图1至3所示，第二半导体层222的第三表面中被第二栅极213和一个第一位线300包裹的两部分占据第三表面的部分，第二半导体层222的第四表面中被第二栅极213和一个第一位线300包裹的两部分占据第四表面的部分，也就是说，第二半导体层222的第三表面和第四表面均具有未被第二栅极213和一个第一位线300包裹的部分区域。
在示例性实施例中，第一半导体层212包括第二沟道以及通过第二沟道连接的第三电极和第四电极，其中，第三电极和第四电极分布在第二沟道的两侧。
一些实施方式中，第二沟道与所连接的第三电极和第四电极的导电性不同。比如，第二沟道为金属氧化物半导体，第三电极和第四电极的导电性高于金属氧化物半导体，实际应用中可以通过测试导电性区别。第二沟道连接的第三电极和第四电极的主体材料可以相同，导电性较高的区域可以通过掺杂实现。
一些实施例中，第二沟道为水平沟道，也即第二沟道的长度方向或载流子的传输方向在与衬底平行的平面内。本申请实施例中的第一晶体管210为栅极沿垂直方向延伸且沟道为水平沟道的晶体管，可以减小垂直衬底方向存储单元尺寸，且可以方便制作结构紧凑的2T0C存储单元的3D堆叠，简化工艺。
一些实施方式中，第二沟道与所连接的第三电极和第四电极的导电性相同。比如，第二沟道、第三电极和第四电极均为多晶硅或金属氧化物半导体，其导电性可以接近导体或半导体，可以通过控制栅极控制晶体管关断或打开。在制备时，第二沟道、第三电极和第四电极可以在相同工艺条件下通过一次工艺形成，因此，该实施例中，第二沟道、第三电极和第四电极在界限上区分不是特别明显。仅仅是从功能角度提出沟道和电极的概念。
示例性地，从功能的角度描述，第三电极、第二沟道和第四电极在第一半导体层212中所处的位置分别如图2中的①、②和③所示。第二沟道的导电性由第一栅极211控制。理论上，第二沟道的沟道长度(也即第三电极和第四电极之间的导电路径的长度)为第一栅极211在第三方向上的尺寸。在一些实施例中，第三电极为第一晶体管210的漏极，第四电极为第一晶体管210的源极；在另一些实施例中，第四电极为第一晶体管210的漏极，第三电极为第一晶体管210的源极。也就是说，第一晶体管210的源极和漏极在一些情况下可以互相调换。实际应用中在识别源极和漏极时可以按照电流的方向识别，不同的电流方向下同一个电极可能是源极或漏极。
换言之，第一半导体层212具有第三连接区、第四连接区以及除第三连接区和第四连接区外的第二栅极控制区，其中，第三连接区、第二栅极控制区和第四连接区沿第三方向排列。第二栅极控制区的导电性通过第一栅极211控制。例如，当第一栅极211上施加较大的电压时，第二栅极控制区具有较强的导电性，当第一栅极211上施加较小的电压时，第二栅极控制区具有较弱的导电性。通过控制第二栅极控制区的导电性，可以实现对第一晶体管210的关断或打开。第三连接区、第四连接区和第二栅极控制区可以由相同的半导体材料制备得到，也可以由不同的半导体材料制备得到。示例性地，上述第三连接区在功能上可以称为第三电极，上述第四连接区在功能上可以称为第四电极，上述第二栅极控制区在功能上可以称为第二沟道。
在示例性实施例中，第一栅极211、第二栅极213、第三栅极221和第一位线300的材料均为导电材料。示例性地，导电材料可以是指以金属元素为成分的合金或者组合金属元素的合金等。例如，氮化钽、氮化钛、钨、包含钛和铝的氮化物、包含钽和铝的氮化物、氧化钌、氮化钌、包含锶和钌的氧化物、包含镧和镍的氧化物、以包含磷等杂质元素的多晶硅为代表的导电率高的半导体以及镍硅化物等硅化物。示例性地，第一栅极211、第二栅极213、第三栅极221和第一位线300的材料可以相同，也可以不同。
在示例性实施例中，第一半导体层212和第二半导体层222的材料是半导体材料。半导体材料可以是指单晶半导体材料、多晶半导体材料、微晶半导体材料或非晶半导体材料等。示例性地，半导体材料可以包括但不限于单晶硅、多晶硅、锗、碳化硅、砷化镓、金属氧化物半导体、氮化物半导体等。示例性地，第一半导体层212和第二半导体层222的材料可以相同，也可以不同。
金属氧化物半导体的带隙为2eV以上，当半导体层的材料使用金属氧化物半导体时，可以实现关态电流极小的晶体管。此外，在半导体层的材料使用金属氧化物半导体的晶体管中，源极与漏极间的绝缘耐压高，从而可以提供可靠性良好的晶体管，进而提供可靠性良好的存储器，还可以提供输出电压大且高耐压的晶体管，进而提供输出电压大且高耐压的存储器。示例性地，第二半导体层222的材料为金属氧化物半导体，以使第二晶体管220实现为关态电流极小的晶体管。当然，在一些实施例中，第一半导体层212的材料也可以为金属氧化物半导体，以使第一晶体管210实现为关态电流极小的晶体管。
示例性地，金属氧化物半导体可以包含铟或锌中的至少一种。示例性地，金属氧化物半导体也可以包含铝、镓、钇或锡等。示例性地，金属氧化物半导体也可以包含硼、硅、钛、铁、镍、锗、锆、钼、镧、铈、钕、铪、钽、钨、镁等中的一种或多种。
示例性地，以金属氧化物半导体包含铟、元素M及锌为例，元素M可以为铝、镓、钇或锡等，也可以为硼、硅、钛、铁、镍、锗、锆、钼、镧、铈、钕、铪、钽、钨、镁等，还可以组合多个上述元素。示例性地，包含铟、镓及锌的金属氧化物半导体可以称为铟镓锌氧化物(IGZO)。示例性地，若一个晶体管的半导体层的材料为IGZO，则该晶体管可以称为IGZO MOSFET。
在示例性实施例中，第一栅极211和第一半导体层212之间的第一栅极绝缘层、第二栅极213和第一半导体层212之间的第二栅极绝缘层、第三栅极221和第二半导体层222之间的第三栅极绝缘层的材料均为绝缘材料。需要说明的是，不同的栅极绝缘层的材料可以相同， 也可以不同。
示例性地，绝缘材料可以是指具有绝缘性的氧化物、氮化物、氧氮化物、氮氧化物、金属氧化物、金属氧氮化物以及金属氮氧化物等。示例性地，当进行晶体管的微型化及高集成化时，由于栅极绝缘层的薄膜化，有时会发生泄漏电流等的问题，因此，用作栅极绝缘层的绝缘材料可以使用high-k(高介电常数)材料，high-k材料可以在保持物理厚度的同时实现晶体管工作时的低电压化。示例性地，介电常数高的绝缘材料可以是指氧化镓、氧化铪、氧化锆、含有铝及铪的氧化物、含有铝及铪的氧氮化物、含有硅及铪的氧化物、含有硅及铪的氧氮化物或者含有硅及铪的氮化物等。
本申请实施例还提供了一种包括如图1至图3所示的存储单元的存储器，由于图1至图3所示的存储单元能够提高数据写入的速度，所以，包括如图1至图3所示的存储单元的存储器同样能够提高数据写入的速度。图5和图6示出了本申请实施例提供的存储器的两个截面示意图。其中，图5是利用一个与第一方向和第三方向均平行的平面(未示出)截断存储器后观察到的截面的示意图，图6是与图5中的A-A’对应的截面的示意图。需要说明的是，图5和图6仅为示例性举例，本申请实施例并不局限于此。需要进一步说明的是，为便于区分，在图5和图6中，对由相同类型的材料制备的部件利用相同的填充方式进行了填充，对由不同类型的材料制备的部件利用不同的填充方式进行了填充。
参见图5和图6，该存储器包括多个存储单元层，每个存储单元层包括多个如图1至图3所示的存储单元200，多个存储单元层沿第二方向排布。每个存储单元层包括沿第一方向排布的多个存储单元列，每个存储单元列中的多个存储单元200通过各自的第一半导体层212串联，串联的第一半导体层212用于与一个第二位线连接；每个存储单元列中的各个存储单元200的第一电极224用于与同一个第一位线300连接。
任一存储单元层中的每个存储单元200与其他存储单元层中对应位置的各个存储单元200构成一个存储单元串，每个存储单元串中的各个存储单元200的第一栅极211用于与同一个第一字线连接，每个存储单元串中的各个存储单元200的第三栅极221用于与同一个第二字线连接。
多个存储单元列沿第一方向排布，构成一个存储单元层，多个存储单元层沿第二方向排布，构成存储器，此种存储器为三维存储器，具有较高的存储密度。
示例性地，第一字线和第二位线可以在数据读取过程中使用，因此第一字线还可以称为读取字线(简称为WL-r或R-WL)，第二位线还可以称为读取位线(简称BL-r或R-BL)。第二字线和第一位线300可以在数据写入过程中使用，因此第二字线还可以称为写入字线(简称为WL-w或W-WL)，第一位线300还可以称为写入位线(简称为BL-w或W-BL)。
图7示出了一种包括两个存储单元200的存储单元列的结构示意图，图8示出了图7所示的存储单元列的一个截面示意图，该截面示意图是根据图7中的b平面截断图7所示的存储单元列后观察到的截面的示意图。需要说明的是，图7和图8仅以一个存储单元列包括两个存储单元200为例，但本申请实施例并不局限于此，也即一个存储单元列还可以包括两个以上(如，4个、8个、16个)的存储单元200。
如图7和图8所示，每个存储单元列包括多个存储单元200，每个存储单元200包括沿第一方向排列的第一晶体管210和第二晶体管220；第一晶体管210包括沿第一方向排列的第一栅极211、第一半导体层212和第二栅极213，第一栅极211沿第二方向延伸，第一半导体层212沿第三方向延伸，第一方向和第三方向为平行于衬底且相互垂直的两个方向，第二方向为垂直于衬底的方向。
第二晶体管220包括第三栅极221以及环绕第三栅极221的第二半导体层222，第三栅极221沿第二方向延伸，第二半导体层222包括沟道223以及通过沟道223连接的第一电极224和第二电极225，第二电极225与第二栅极213连接。第一电极224用于与一个第一位线300连接，该一个第一位线300用于向第一电极224施加电压，第一栅极211用于与一个第一字线连接，该一个第一字线用于向第一栅极211施加电压；第三栅极221用于与一个第二 字线连接，该一个第二字线用于向第三栅极221施加电压。存储单元200的介绍详见图1至图3涉及的实施例，此处不再加以赘述。
根据图7和图8可知，存储单元列沿第三方向延伸且存储单元列中的多个存储单元200通过各自的第一半导体层212串联。串联的第一半导体层212的一端用于与一个第二位线连接，该一个第二位线用于向串联的第一半导体层212施加电压；串联的第一半导体层212的另一端用于与一个源线连接，该一个源线同样用于向串联的第一半导体层212施加电压。
示例性地，每个存储单元200的第一半导体层212依次包括第三电极、第二沟道和第四电极，通过第一半导体层212串联的存储单元之间共享第三电极或第四电极。
示例性地，存储单元列还包括第三晶体管和第四晶体管，第三晶体管和第四晶体管分别位于串联的多个存储单元200的两端；第三晶体管和第四晶体管均包括栅极和半导体层，其中，第三晶体管和第四晶体管的半导体层均包括源极、沟道和漏极。第三晶体管、第四晶体管通过各自的半导体层与串联的多个存储单元200串联。示例性地，存储单元列中的第三晶体管的漏极与存储单元200串联，第三晶体管的源极用于与第二位线连接，第三晶体管的栅极用于与漏极选择线连接，漏极选择线用于控制第三晶体管的沟道的状态，通过控制第三晶体管的沟道的状态，能够控制第三晶体管的关断或打开。存储单元列中的第四晶体管的漏极与存储单元200串联，第四晶体管的栅极用于与源极选择线连接，第四晶体管的源极用于与源线连接，其中，源极选择线用于控制第四晶体管的沟道的状态，通过控制第四晶体管的沟道的状态，能够控制第四晶体管的关断或打开。需要说明的是，第三晶体管的源极和漏极在一些情况下可以互相调换，第四晶体管的源极和漏极在一些情况下也可以互相调换。实际应用中在识别源极和漏极时可以按照电流的方向进行识别。
一些实施方式中，第三晶体管(或第四晶体管)的半导体层中的沟道与源极和漏极的导电性不同。比如，沟道为金属氧化物半导体，源极和漏极的导电性高于金属氧化物半导体，实际应用中可以通过测试导电性区别。源极和漏极的主体材料可以相同，导电性较高的区域可以通过掺杂实现。
一些实施方式中，第三晶体管(或第四晶体管)的半导体层中的沟道与源极和漏极的导电性相同。比如，沟道、源极和漏极均为多晶硅或金属氧化物半导体，其导电性可以接近导体或半导体，可以通过控制栅极控制晶体管关断或打开。在制备时，沟道、源极和漏极可以在相同工艺条件下通过一次工艺形成，因此，该实施例中，沟道、源极和漏极在界限上区分不是特别明显。仅仅是从功能角度提出沟道、源极和漏极的概念。
换言之，第三晶体管(或第四晶体管)的半导体层具有两个连接区和除两个连接区外的栅极控制区，其中，两个连接区位于栅极控制区在第三方向上的两侧。栅极控制区的导电性通过第三晶体管(或第四晶体管)的栅极控制。两个连接区和栅极控制区可以由相同的半导体材料制备得到，也可以由不同的半导体材料制备得到。示例性地，上述两个连接区在功能上分别可以称为源极和漏极，上述栅极控制区在功能上可以称为沟道。
需要说明的是，存储单元列中的多个存储单元200的第一栅极211在第三方向上彼此隔离，如，通过介质层隔离；多个存储单元200的第二栅极213在第三方向上彼此隔离，如，通过介质层隔离；多个存储单元200的第二半导体层222在第三方向上彼此隔离，如，通过介质层隔离。
如图7和图8所示，存储单元列中的不同存储单元200的第一电极224可以用于与同一个第一位线300连接，也即存储单元列中的多个存储单元200的第一电极224用于与同一个第一位线300连接，此种情况下，可以通过同一个第一位线300对存储单元列中的多个存储单元200的第一电极224同时施加电压，提高电压施加效率，并且减少第一位线300的数量，有利于提高存储器的存储密度。示例性地，如图7和图8所示，第一位线300沿第三方向延伸。
示例性地，多个存储单元列中，在第一方向相邻的两个存储单元列可以完全相同，也可以镜面对称，本申请实施例对此不加以限定。两个存储单元列镜面对称具有两种情况：两个 存储单元列中的相应的存储单元200通过各自的第二晶体管220相邻；或者，两个存储单元列中的相应的存储单元200通过各自的第一晶体管210相邻。
两个存储单元列中相应的存储单元是指两个存储单元列中位于同一行的存储单元。对于两个存储单元列中的相应的存储单元200通过各自的第二晶体管220相邻的情况，在第一方向的排列方向下，前一个存储单元列中的存储单元200为第一类型的存储单元，后一个存储单元列中的相应存储单元200为第二类型的存储单元，其中，第一类型的存储单元是指从第一晶体管210到第二晶体管220的排列方向为第一方向的存储单元200，第二类型的存储单元是指从第二晶体管220到第一晶体管210的排列方向为第一方向的存储单元200。
对于两个存储单元列中的相应的存储单元200通过各自的第一晶体管210相邻的情况，在第一方向的排列方向下，前一个存储单元列中的存储单元200为第二类型的存储单元，后一个存储单元列中的相应存储单元200为第一类型的存储单元。
示例性地，不同存储单元列中的多个存储单元200的第一电极224所连接的第一位线300不同，以利用不同的第一位线300对不同的存储单元列中的多个存储单元200的第一电极224施加电压，提高电压施加的灵活性。
示例性地，若多个存储单元列中在第一方向相邻的两个存储单元列镜面对称，则对于在第一方向相邻且呈相应的存储单元200通过各自的第二晶体管220相邻的每两个存储单元列(称为第一存储单元列和第二存储单元列)，由于该第一存储单元列和第二存储单元列中的存储单元200的第一电极224距离较近，所以该第一存储单元列和第二存储单元列中的各个存储单元200的第一电极224可以共享同一第一位线300，也即该在第一方向相邻的第一存储单元列和第二存储单元列中的各个存储单元200的第一电极224用于与同一个第一位线300连接。其中，第一存储单元列和第二存储单元列镜像对称，且第一存储单元列中的存储单元200和第二存储单元列中的相应存储单元200通过各自的第二晶体管220相邻。此种情况下，能够利用一个第一位线300同时对两个存储单元列中的存储单元200的第一电极224施加电压，提高电压施加的效率，减少第一位线300的数量，提高存储密度。
如图5所示，在第一方向相邻且相应的存储单元200通过各自的第二晶体管220相邻的两个存储单元列中的各个存储单元200的第一电极224用于与同一第一位线300连接。其中，两个存储单元列中的各个存储单元200的第一电极224均嵌入同一个第一位线300，以实现与该同一个第一位线300的连接。
示例性地，如图5所示，对于在第一方向相邻的第一存储单元列和第二存储单元列中的各个存储单元200的第一电极224用于与同一个第一位线300连接的情况，同一个第一位线300位于第一存储单元列和第二存储单元列之间，同一个第一位线300具有垂直于第一方向的第一表面和第二表面。第一存储单元列中的各个存储单元200的第一电极224与同一个第一位线300的第一表面连接，第二存储单元列中的各个存储单元200的第一电极224与同一个第一位线300的第二表面连接。此种布局方式不仅可以节省第一位线300的数量，还可以节省占用空间，有利于进一步提高存储密度。
示例性地，本申请所提供的存储器中的每个存储单元列可以适用于如图9所示的逻辑电路。在图9中，W-BL为一个存储单元列中的存储单元的第一电极所共同连接的一个第一位线，R-BL为一个存储单元列中的存储单元的串联的第一半导体层的一端所连接的第二位线，SSL为源极选择线，DSL为漏极选择线，R-WL_0～R-WL_M为一个存储单元列中的每个存储单元的第一栅极分别连接的第一字线，W-WL_0～W-WL_M为一个存储单元列中的每个存储单元的第三栅极分别连接的第二字线。其中，M为一个存储单元列中的存储单元的数量。
任一存储单元层中的每个存储单元200与其他存储单元层中对应位置的各个存储单元200构成一个存储单元串，不同层对应位置的存储单元200可以是指不同层中在衬底上的投影重合或近似重合的存储单元。存储器包括沿第一方向和第三方向阵列排布的多个存储单元串，每个存储单元串中的存储单元200中的第二栅极213在第二方向上隔离。
在第一方向相邻的两个存储单元串可以完全相同，也可以镜面对称，本申请实施例对此 不加以限定。两个存储单元串镜面对称具有两种情况：两个存储单元串中的相应的存储单元200通过各自的第一晶体管210相邻；或者，两个存储单元串中的相应的存储单元200通过各自的第二晶体管220相邻。
两个存储单元串中相应的存储单元是指两个存储单元串中与衬底的距离相同或近似相同的存储单元。对于两个存储单元串中的相应的存储单元200通过各自的第二晶体管220相邻的情况，在第一方向的排列方向下，前一个存储单元串中的存储单元200为第一类型的存储单元，后一个存储单元串中的相应存储单元200为第二类型的存储单元。对于两个存储单元串中的相应的存储单元200通过各自的第一晶体管210相邻的情况，在第一方向的排列方向下，前一个存储单元串中的存储单元200为第二类型的存储单元，后一个存储单元串中的相应存储单元200为第一类型的存储单元。
每个存储单元200的第一栅极211均用于与一个第一字线连接，通过对不同存储单元200的第一栅极211所连接的第一字线进行合理设置，能够利用较少数量的第一字线实现对存储器中的全部存储单元200的第一栅极211的控制，提高存储器的存储密度。示例性地，第一字线沿第二方向延伸。
在本申请提供的存储器中，每个存储单元串中的各个存储单元200的第一栅极211用于与同一个第一字线连接。该同一个第一字线用于对每个存储单元串中的各个存储单元200的第一栅极211同时施加电压，有利于一定程度上减少第一字线的数量。
示例性地，不同存储单元串中的存储单元200的第一栅极211用于与不同的第一字线连接，以利用不同的第一字线对不同存储单元串中的存储单元200的第一栅极211施加电压，提高电压施加的灵活性。
在一种可能实现方式中，若多个存储单元串中在第一方向相邻的两个存储单元串镜面对称，则对于在第一方向相邻且相应的存储单元200通过各自的第一晶体管210相邻的每两个存储单元串(称为第一存储单元串和第二存储单元串)，由于第一存储单元串和第二存储单元串中的存储单元200的第一栅极211距离较近，所以，可以设置第一存储单元串和第二存储单元串中的存储单元200的第一栅极211用于与同一个第一字线连接，从而能够利用一个第一字线同时对第一存储单元串和第二存储单元串中存储单元200的第一栅极211施加电压，也即第一存储单元串和第二存储单元串中的存储单元200的第一栅极211共享同一个第一字线，此种方式有利于进一步减少第一字线的数量，提高存储器的存储密度。
示例性地，第一字线沿第二方向延伸(也即垂直于衬底)，第一栅极211也沿第二方向延伸(也即垂直于衬底)，每个存储单元串中的各个存储单元200的第一栅极211均为所连接的第一字线的一部分。也就是说，每个存储单元串中的每个存储单元200的第一栅极211在衬底上的投影均落在所连接的第一字线在衬底上的投影中。利用第一栅极211本身来形成第一字线，能够减少布局第一字线所需的材料，提高存储器的存储密度。示例性地，第一栅极211在衬底上的投影轮廓为第一栅极211的横截面轮廓，第一字线在衬底上的投影轮廓为第一字线的横截面轮廓。
示例性地，如图6所示，第一方向相邻且相应的存储单元200通过各自的第一晶体管210相邻的两个存储单元串(未示出)中的存储单元200的第一栅极211共享同一个第一字线，该同一个第一字线涵盖两个存储单元串中的存储单元200的第一栅极211，该同一个第一字线可视为一条垂直于衬底的纵向直线，该纵向直线在不同位置的横截面的面积可以相同，也可以不同。
每个存储单元200的第三栅极221均用于与一个第二字线连接，通过对不同存储单元200的第三栅极221所连接的第二字线进行合理设置，能够利用较少数量的第二字线实现对存储器中的全部存储单元200的第三栅极221的控制，提高存储器的存储密度。示例性地，第二字线沿第二方向延伸。
在本申请提供的存储器中，每个存储单元串中的各个存储单元200的第三栅极221用于与同一个第二字线连接。该同一个第二字线用于对每个存储单元串中的各个存储单元200的 第三栅极221施加电压，有利于一定程度上减少第二字线的数量。
示例性地，不同存储单元串中的存储单元200的第三栅极221用于与不同的第二字线连接，以利用不同的第二字线对不同存储单元串中的存储单元200的第三栅极221施加电压，保证电压施加的灵活性。
示例性地，第二字线沿第二方向延伸(也即垂直于衬底)，存储单元200的第三栅极221也沿第二方向延伸(也即垂直于衬底)，每个存储单元串中的各个存储单元200的第三栅极221均为所连接的第二字线的一部分。也就是说，每个存储单元串中的每个存储单元200的第三栅极221在衬底上的投影均落在所连接的第二字线在衬底上的投影中。利用第三栅极221本身形成第二字线，能够减少布局第二字线所需的材料，从而进一步提高存储密度。
示例性地，如图6所示，一个存储单元串(未示出)中的存储单元200的第三栅极221可以直接串联形成一个第二字线，或者通过连接线串联形成一个第二字线。无论哪种情况，该一个第二字线均涵盖存储单元串中的存储单元200的第三栅极221，该一个第二字线可视为一条垂直于衬底的纵向直线，该纵向直线在不同位置的横截面的面积可以相同，也可以不同。
示例性地，存储器可以通过一体成型的方式制备得到。
示例性地，本申请提供的存储器可以适用于如图10所示的逻辑电路。在图10所示的逻辑电路中，存储器包括N个存储单元列，每个存储单元列中包括M个存储单元。该N个存储单元列是指存储器中的在衬底上的投影重合或近似重合的N个存储单元列，该N个存储单元列中的任一存储单元列中的每个存储单元均与其他存储单元列中对应位置的存储单元构成一个存储单元串，从而构成M个存储单元串，也即在图10所示的逻辑电路中，存储器包括M个存储单元串。每个存储单元列中的存储单元的第一电极共同与一个第一位线(W-BL)连接，每个存储单元列中的存储单元的串联的第一半导体层的一端与一个第二位线(R-BL)连接，每个存储单元串中的存储单元的第一栅极共同与一个第一字线(R-WL)连接，每个存储单元串中的存储单元的第二栅极共同与一个第二字线(W-WL)连接。需要说明的是，N个存储单元列中的不同存储单元列中对应位置的存储单元是指不同存储单元列中在衬底上的投影重合或近似重合的存储单元。
在图10中，W-BL_0～W-BL_N为N个存储单元列中的每个存储单元列中的存储单元的第一电极所分别连接的第一位线，R-BL_0～R-BL_0为N个存储单元列中的每个存储单元列中的存储单元的串联的第一半导体层的一端所分别连接的第二位线，SSL为源线选择线，DSL为漏极选择线，R-WL_0～R-WL_M为M个存储单元串中的每个存储单元串中的存储单元的第一栅极所分别连接的第一字线，W-WL_0～W-WL_M为M个存储单元串中的每个存储单元串中的存储单元的第三栅极所分别连接的第二字线。N个存储单元列中的每个存储单元列中的存储单元的串联的第一半导体层的另一端均与同一个源线连接。
接下来，以图10所示的逻辑电路为例，介绍存储器的数据读取和数据写入过程。
当读取目标存储单元中的数据时，向所有的第二字线施加低电压以关断所有的第二晶体管；所读取的目标存储单元所连接的第一字线或所读取的目标存储单元的第一晶体管的第一栅极处于预设电压；向除所读取的目标存储单元所连接的第一字线外的其他第一字线、漏极选择线和源极选择线施加高电压。
在读取操作期间，所有W-WL(第二字线)被提供低电压以关断所有第二晶体管。为了读取一个单元，它的字线或第一晶体管的第一栅极被提供预设电压(预设电压为仅能使存储数据能够被读取的电压，图11中示出了预设电压示例)，如果高电压或数据“1”被存储在第一晶体管的第二栅极中，预设电压可以接通第一晶体管，但是如果低电压或数据“0”被存储，预设电压保持第一晶体管关断。所有其他R-WL(即其他第一晶体管的第一栅极)以及SSL和DSL被给予高电压，以确保电流(对于数据“1”)可以从源线流到相应的第二位线。
需要说明，同一行中的所有存储单元可以构成页，从而可以每次读取一页，从而提高读取速度。
当对目标存储单元写入数据时，通过选择目标存储单元的相应的第二字线和第一位线进行写操作。例如，对目标存储单元连接的第二字线施加高电压，以使目标存储单元的第二晶体管打开，对目标存储单元连接的第一位线施加高电压或低电压，以将施加的电压传递至第一晶体管的第二栅极，实现对第一晶体管的阈值电压的改变，从而实现数据写入。示例性地，对除目标存储单元连接的第二字线外的其他第二字线均施加低电压，以使除目标存储单元中的第二晶体管外的其他第二晶体管关断；对全部的第一字线均施加低电压，以使全部的第一晶体管均关断。
写和读操作是分开的，并且写操作可以更快，因为信号仅通过一个晶体管被写入第二栅极。通过选择连接到目标单元的相应的W-WL(第二字线)和W-BL(第一位线)，可以容易地实现写操作。需要说明的是，对数据的刷新操作类似于写入操作。
以下将继续介绍本申请发明构思的不同实施例。
如图4，一种存储单元，包括：读晶体管(T1)和写晶体管(T2)。
如图1和图2，读晶体管包括第一栅极(主栅)211和第二栅极(背栅)213，背栅与写晶体管的半导体层(第二半导体层222)相连；当然，若半导体层上额外制作电极时，也可以与该电极连接，电极为源极或漏极；或者，也可以将第二半导体层222的非沟道区域作为源极或漏极。
读晶体管和写晶体管分别为垂直晶体管，垂直晶体管可以是平面型晶体管，或立体环形结构的晶体管。其中，平面型也可以称为面状，立体环形结构也可以称为环形立体结构。比如，读晶体管和写晶体管的其中一个为面状晶体管，另一个为环形立体结构的晶体管。其中，面状晶体管为关键膜层为面状分布，但是主表面垂直衬底构成垂直晶体管，环形立体结构的晶体管为关键膜层(如栅或半导体层)为环形且侧表面垂直衬底构成垂直晶体管。
一种实施例中，如图1和2所示，第一栅极(主栅)211和第二栅极(背栅)213分别为面状、读晶体管的半导体层(第一半导体层212)为面状；写晶体管的栅极(附图中的第三栅极221)为柱状，写晶体管的半导体层(附图中的第二半导体层222)为环形，环形的半导体层环绕柱状的栅极的侧表面。
如图1和2，读晶体管和写晶体管位于衬底上在平行于衬底的平面内相邻分布；主栅和面状的半导体层的主表面分别垂直于衬底；柱状的栅极的侧表面垂直于衬底。
如图1和2，面状的半导体层具有相向的第一主表面和第二主表面，第一主表面和第二主表面上分别设置有主栅和背栅；背栅具有相向的两个主表面，其中一个主表面与面状半导体层的第二主表面平行且相邻，另一个主表面与环形半导体层的侧表面接触。
如图2中，面状的半导体层的靠近第一栅极(主栅)211的半导体主表面为第一主表面，相对设置的主表面为第二主表面。
本申请的主表面为在一个多面结构中，面积较大的面为主表面。
一些实施例中，提供一种存储器，其中，存储器包括：
如图5-7，包含衬底；
衬底上的多条第一导线(如图5所示的212)和多条第二导线(如图5所示的300)，多条第一导线和多条第二导线在平行于衬底的顶表面的第一方向(对应于图5的第三方向)延伸，且在垂直第一方向的第二方向(对应于图5的第一方向)间隔设置，且一条第一导线和一条第二导线构成一个导线组相邻设置，如图5所示的虚线框内的导线构成一个导线组。
每个导线组中，相邻设置的第一导线和第二导线上设置有沿第一方向间隔分布的n个存储单元；各导线组中的各存储单元阵列分布在衬底上；一个存储单元包括一个读晶体管和一个写晶体管；
其中，第一导线上沿着第一方向间隔分布有n个读晶体管(上述实施例中的第一晶体管)，第二导线上沿着第一方向间隔分布有与n个读晶体管一一对应连接的n个写晶体管(上述实施例中的第二晶体管)；
其中，如图5，第一导线对应于每个读晶体管的区域为每个读晶体管的半导体区域；第二 导线与每个写晶体管的半导体区域或源极区或漏极区连接。可以理解为，第一导线上形成有读晶体管的半导体区域。比如，一个金属导线作为第一导线时，可以在对应的半导体区域形成包裹第一导线的金属氧化物半导体或多晶硅半导体，作为读晶体管的半导体区域。或者，形成导电的硅(如Si n+)作为第一导线，对第一导线的待形成的半导体区域进行掺杂改性，得到半导体特性的区域作为读晶体管的半导体区域。
如图1和图5，存储器还包括多条第一字线(对应于图1和图5的211)，在垂直于衬底的方向延伸且在第一方向间隔排列；
各第一字线分别对应设置于第一导线的每个读晶体管的半导体区域且与半导体区域通过介质层绝缘，第一字线中对应于每个读晶体管的半导体区域的区域为每个读晶体管的栅极区域，栅极区域设置有读晶体管的主栅。
一些实施例中，存储器还包括：
多个背栅(如图1和图5所示的第二栅极213)，沿着垂直衬底的方向延伸且在第一方向上依次间隔排列；多个背栅分别设置在每个读晶体管的半导体区域且与每个读晶体管的栅极区域相向设置。
一些实施例中，存储器还包括：
多个写晶体管的多个环绕型半导体层(如图1和如图5所示的222)，分别沿着垂直于衬底的方向延伸且在第一方向间隔排列；
多个写晶体管的多个柱状栅极(如图1和图5所示的第三栅极221)，分别沿着垂直于衬底的方向延伸且在第一方向间隔排列；
每个环绕型半导体层环绕对应的写晶体管的柱状栅极设置；
柱状栅极和环绕型半导体层的侧表面垂直于衬底；
各环绕型半导体层的侧表面的一个区域与第二导线连接，各环绕型半导体层的侧表面的另一个区域分别与各读晶体管的背栅一一对应连接。
其中，在垂直于第一方向(对应图5所示的第三方向)的第二方向(对应图5所示的第一方向)上，属于一个存储单元的主栅(如图5所示的第一栅极211)、第一导线(如图5所示的212)、背栅(如图5所示的213)、环绕型半导体层(如图5所示的222)、第二导线(如图5所示的300)依次排列设置。
其中，如图1，第一导线和第二导线分别为垂直衬底延伸设定宽度的面状结构，面状结构具有第一主表面和第二主表面，第一主表面和第二主表面为侧表面，第一导线的第二主表面和第二导线的第一主表面相邻设置。
各主栅设置于第一导线的第一主表面上与第一导线绝缘；
各背栅设置于第一导线的第二主表面上与第一导线绝缘。
更具体的，各环绕型半导体层设置于第二导线和各背栅之间，且各环绕型半导体层设置于第二导线的第一主表面上与第一主表面连接。
一些实施例中，一个导线组的各存储单元的排布与相邻的导线组对应的各存储单元的排布镜像对称且共用第二导线；
第二导线的第二主表面与相邻的导线组对应的各存储单元中的各环绕型半导体层连接。
一些实施例中，如图5所示，每间隔两条第一导线设置有一条第二导线(如图5所示的300)，第二导线和与该第二导线相邻的两条第一导线(如图5所示的212)构成一个导线组，第二导线由两个第一导线对应的存储单元共用。
本申请实施例还提供了一种电子设备，如图12所示，该电子设备包括上述存储单元或存储器。本申请提供的电子设备，可以是包含上述任何一种实施例所述的存储单元或存储器的电子设备。所述电子设备可以是终端设备，如芯片，或封装有芯片的产品等。
以上所述仅为本申请的示例性实施例，并不用以限制本申请，凡在本申请的原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (25)

  1. 一种存储单元，其中，所述存储单元(200)包括沿第一方向排列的第一晶体管(210)和第二晶体管(220)；
    所述第一晶体管(210)包括沿所述第一方向排列的第一栅极(211)、第一半导体层(212)和第二栅极(213)，所述第一栅极(211)沿第二方向延伸，所述第一半导体层(212)沿第三方向延伸，所述第一方向和所述第三方向为平行于衬底且相互垂直的两个方向，所述第二方向为垂直于所述衬底的方向；
    所述第二晶体管(220)包括第三栅极(221)以及环绕所述第三栅极(221)的第二半导体层(222)，所述第三栅极(221)沿所述第二方向延伸，所述第二半导体层(222)包括沟道(223)以及通过所述沟道(223)连接的第一电极(224)和第二电极(225)，所述第二电极(225)与所述第二栅极(213)连接。
  2. 根据权利要求1所述的存储单元，其中，所述沟道(223)为水平沟道。
  3. 根据权利要求1所述的存储单元，其中，所述第二半导体层(222)具有垂直于衬底的第一表面、第二表面、第三表面和第四表面，所述第二半导体层(222)的第一表面和第二表面垂直于所述第一方向，所述第二半导体层(222)的第二表面比第一表面远离所述第一晶体管(210)，所述第二半导体层(222)的第三表面和第四表面垂直于所述第三方向；
    所述第二栅极(213)包裹所述第二半导体层(222)的第一表面整体以及包裹所述第二半导体层(222)的第三表面和第四表面的靠近所述第一晶体管(210)的一部分；一个第一位线(300)包裹所述第二半导体层(222)的第二表面整体以及包裹所述第二半导体层(222)的第三表面和第四表面的远离所述第一晶体管(210)的一部分。
  4. 根据权利要求1所述的存储单元，其中，所述第一栅极(211)和所述第一半导体层(212)之间存在第一栅极绝缘层，所述第一半导体层(212)和所述第二栅极(213)之间存在第二栅极绝缘层；
    所述第一栅极(211)、所述第一栅极绝缘层、所述第一半导体层(212)、所述第二栅极绝缘层和所述第二栅极(213)均具有垂直于所述第一方向的第一表面和第二表面，同一部件的第一表面比第二表面远离所述第二晶体管(220)；
    所述第一栅极(211)的第二表面与所述第一栅极绝缘层的第一表面贴合，所述第一栅极绝缘层的第二表面与所述第一半导体层(212)的第一表面贴合，所述第一半导体层(212)的第二表面与所述第二栅极绝缘层的第一表面贴合，所述第二栅极绝缘层的第二表面与所述第二栅极(213)的第一表面贴合。
  5. 根据权利要求1-4任一所述的存储单元，其中，所述第二半导体层(222)的材料为金属氧化物半导体。
  6. 根据权利要求1-4任一所述的存储单元，其中，所述第二半导体层(222)具有与一个第一位线(300)连接的第一连接区、与所述第二栅极(213)连接的第二连接区以及除所述第一连接区和所述第二连接区外的栅极控制区，所述栅极控制区的导电性通过所述第三栅极(221)控制。
  7. 一种存储器，其中，所述存储器包括多个存储单元层，每个存储单元层包括多个如权利要求1-6任一所述的存储单元(200)，所述多个存储单元层沿所述第二方向排布；
    每个存储单元层包括沿所述第一方向排布的多个存储单元列，每个存储单元列中的多个存储单元(200)通过各自的第一半导体层(212)串联，串联的第一半导体层(212)用于与一个第二位线连接；每个存储单元列中的各个存储单元(200)的第一电极(224)用于与同一个第一位线(300)连接；
    任一存储单元层中的每个存储单元(200)与其他存储单元层中对应位置的各个存储单元(200)构成一个存储单元串，每个存储单元串中的各个存储单元(200)的第一栅极(211)用于与同一个第一字线连接，每个存储单元串中的各个存储单元(200)的第三栅极(221) 用于与同一个第二字线连接。
  8. 根据权利要求7所述的存储器，其中，在所述第一方向相邻的第一存储单元列和第二存储单元列中的各个存储单元(200)的第一电极(224)用于与同一个第一位线(300)连接；
    其中，所述第一存储单元列和所述第二存储单元列镜像对称，且所述第一存储单元列中的存储单元(200)和所述第二存储单元列中的相应存储单元(200)通过各自的第二晶体管(220)相邻。
  9. 根据权利要求8所述的存储器，其中，所述同一个第一位线(300)位于所述第一存储单元列和所述第二存储单元列之间，所述同一个第一位线(300)具有垂直于所述第一方向的第一表面和第二表面；
    所述第一存储单元列中的各个存储单元(200)的第一电极(224)与所述同一个第一位线(300)的第一表面连接，所述第二存储单元列中的各个存储单元(200)的第一电极(224)与所述同一个第一位线(300)的第二表面连接。
  10. 根据权利要求7所述的存储器，其中，在所述第一方向相邻的第一存储单元串和第二存储单元串中的各个存储单元(200)的第一栅极(211)用于与同一个第一字线连接；
    其中，所述第一存储单元串和所述第二存储单元串镜像对称，且所述第一存储单元串中的存储单元(200)和所述第二存储单元串中的相应存储单元(200)通过各自的第一晶体管(210)相邻。
  11. 根据权利要求7-10任一所述的存储器，其中，所述第一字线沿所述第二方向延伸，每个存储单元串中的各个存储单元(200)的第一栅极(211)均为所连接的第一字线的一部分。
  12. 根据权利要求7-10任一所述的存储器，其中，所述第二字线沿所述第二方向延伸，每个存储单元串中的各个存储单元(200)的第三栅极(221)均为所连接的第二字线的一部分。
  13. 一种存储单元，包括：读晶体管和写晶体管，所述读晶体管包括主栅和背栅，所述背栅与所述写晶体管的半导体层、源极或漏极相连；
    其中，
    所述读晶体管和所述写晶体管分别为垂直晶体管；
    所述主栅和所述背栅分别为面状、所述读晶体管的半导体层为面状；所述写晶体管的栅极为柱状，所述写晶体管的半导体层为环形，所述环形的半导体层环绕所述柱状的栅极的侧表面。
  14. 根据权利要求13所述的存储单元，其中，所述读晶体管和写晶体管位于衬底上在平行于衬底的平面内相邻分布；所述主栅和面状的半导体层的主表面分别垂直于所述衬底；所述柱状的栅极的所述侧表面垂直于所述衬底。
  15. 根据权利要求14所述的存储单元，其中，所述面状的半导体层具有相向的第一主表面和第二主表面，所述第一主表面和第二主表面上分别设置有所述主栅和背栅；所述背栅具有相向的两个主表面，其中一个主表面与所述面状半导体层的第二主表面平行且相邻，另一个主表面与所述环形半导体层的侧表面接触。
  16. 一种存储器，其中，所述存储器包括：
    衬底；
    所述衬底上的多条第一导线和多条第二导线，所述多条第一导线和多条第二导线在平行于所述衬底的顶表面的第一方向延伸，且在垂直所述第一方向的第二方向间隔设置，且一条第一导线和一条第二导线构成一个导线组相邻设置；
    每个所述导线组中，所述相邻设置的第一导线和第二导线上设置有沿第一方向间隔分布的n个存储单元；各导线组中的各存储单元阵列分布在所述衬底上；所述一个存储单元包括一个读晶体管和一个写晶体管；
    其中，所述第一导线上沿着所述第一方向间隔分布有n个读晶体管，所述第二导线上沿着所述第一方向间隔分布有与所述n个读晶体管一一对应连接的n个写晶体管；
    其中，所述第一导线对应于每个读晶体管的区域为所述每个读晶体管的半导体区域；所 述第二导线与所述每个写晶体管的半导体区域或源极区或漏极区连接。
  17. 根据权利要求16所述的存储器，其中，所述存储器还包括：
    多条第一字线，在垂直于衬底的方向延伸且在所述第一方向间隔排列；
    所述各第一字线分别对应设置于所述第一导线的所述每个读晶体管的半导体区域且与所述半导体区域通过介质层绝缘，所述第一字线中对应于所述每个读晶体管的半导体区域的区域为每个所述读晶体管的栅极区域，所述栅极区域设置有所述读晶体管的主栅。
  18. 根据权利要求17所述的存储器，其中，所述存储器还包括：
    多个背栅，沿着垂直衬底的方向延伸且在所述第一方向上依次间隔排列；所述多个背栅分别设置在所述每个读晶体管的半导体区域且与每个所述读晶体管的栅极区域相向设置。
  19. 根据权利要求18所述的存储器，其中，所述存储器还包括：
    多个写晶体管的多个环绕型半导体层，分别沿着垂直于所述衬底的方向延伸且在所述第一方向间隔排列；
    多个写晶体管的多个柱状栅极，分别沿着垂直于所述衬底的方向延伸且在所述第一方向间隔排列；
    每个所述环绕型半导体层环绕对应的写晶体管的柱状栅极设置；
    所述柱状栅极和所述环绕型半导体层的侧表面垂直于所述衬底；
    各所述环绕型半导体层的侧表面的一个区域与所述第二导线连接，各所述环绕型半导体层的侧表面的另一个区域分别与所述各读晶体管的背栅一一对应连接。
  20. 根据权利要求19所述的存储器，其中，在垂直于所述第一方向的第二方向上，属于一个存储单元的所述主栅、所述第一导线、所述背栅、所述环绕型半导体层、所述第二导线依次排列设置。
  21. 根据权利要求19所述的存储器，其中，所述第一导线和第二导线分别为垂直衬底延伸设定宽度的面状结构，所述面状结构具有第一主表面和第二主表面，所述第一主表面和第二主表面为侧表面，所述第一导线的第二主表面和所述第二导线的第一主表面相邻设置；
    各所述主栅设置于所述第一导线的第一主表面上与所述第一导线绝缘；
    各所述背栅设置于所述第一导线的第二主表面上与所述第一导线绝缘。
  22. 根据权利要求21所述的存储器，其中，各所述环绕型半导体层设置于所述第二导线和各所述背栅之间，且各所述环绕型半导体层设置于所述第二导线的第一主表面上与所述第一主表面连接。
  23. 根据权利要求22所述的存储器，其中，
    所述一个导线组的各存储单元的排布与相邻的导线组对应的各存储单元的排布镜像对称且共用所述第二导线；
    所述第二导线的第二主表面与所述相邻的导线组对应的各存储单元中的各环绕型半导体层连接。
  24. 根据权利要求16所述的存储器，其中，
    每间隔两条第一导线设置有一条第二导线，所述第二导线和与所述第二导线相邻的两条第一导线构成一个导线组，所述第二导线由所述两条第一导线对应的存储单元共用。
  25. 一种电子设备，其中，所述电子设备包含权利要求1-24任一所述的存储单元或存储器。
PCT/CN2022/134673 2022-10-18 2022-11-28 存储单元、存储器和电子设备 WO2024082381A1 (zh)

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