WO2024055401A1 - 显示面板及其驱动方法和显示装置 - Google Patents

显示面板及其驱动方法和显示装置 Download PDF

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Publication number
WO2024055401A1
WO2024055401A1 PCT/CN2022/130498 CN2022130498W WO2024055401A1 WO 2024055401 A1 WO2024055401 A1 WO 2024055401A1 CN 2022130498 W CN2022130498 W CN 2022130498W WO 2024055401 A1 WO2024055401 A1 WO 2024055401A1
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Prior art keywords
transistor
module
node
signal
reset
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PCT/CN2022/130498
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English (en)
French (fr)
Inventor
刘胜
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武汉天马微电子有限公司
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Publication of WO2024055401A1 publication Critical patent/WO2024055401A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels

Definitions

  • the present application relates to the field of display technology, for example, to a display panel, a driving method thereof, and a display device.
  • the design purpose is to increase the screen-to-body ratio of the display panel.
  • an under-screen display panel that is, optical devices (such as cameras) are arranged below the display screen.
  • optical devices such as cameras
  • the display screen When it is necessary to take pictures, the display screen will become transparent glass, allowing external light to pass through the display screen and reach the camera. When there is no need to take pictures, the display screen can display normally.
  • LCD liquid crystal display
  • OLED organic light-emitting diode
  • This application provides a display panel, its driving method and a display device, aiming to effectively improve the transmittance of the optical device area.
  • the present application provides a display panel, including a first display area and a second display area. Both the first display area and the second display area include a plurality of sub-pixels arranged in an array, and each sub-pixel includes a pixel driving circuit, wherein the first display area and the second display area include a plurality of sub-pixels arranged in an array.
  • the second display area corresponds to the photosensitive element;
  • Each pixel driving circuit located in the second display area includes at least one transistor, and at least one of the transistors is a low-temperature polycrystalline oxide thin film transistor.
  • This application also provides a driving method for a display panel, used to drive the display panel provided above,
  • Driving methods include:
  • the compensation module and the first reset module are turned on, and the first reset module and the compensation module transmit the reset signal at the reset signal terminal to the first node to reset the first node;
  • the data writing module, the driving transistor and the compensation module included in the pixel driving circuit are turned on, and the data signal of the data signal end connected to the first end of the data writing module is transmitted through the second end of the data writing module.
  • the signal of the second node is transmitted to the third node through the driving transistor, and the signal of the third node is transmitted to the first node through the compensation module;
  • the power supply voltage writing module, the driving transistor and the light-emitting control module included in the pixel driving circuit are turned on.
  • the power supply voltage writing module transmits the first voltage signal of the first power signal terminal to the second node, and the driving transistor forms a current transmission to the light-emitting component.
  • the present application also provides a display device, including the display panel provided by the present application.
  • Figure 1 is a top view of a display panel provided by an embodiment of the present application.
  • Figure 2 is a schematic diagram of the frame structure of a pixel driving circuit provided by an embodiment of the present application
  • Figure 3 is a circuit schematic diagram of a pixel driving circuit provided by an embodiment of the present application.
  • Figure 4 is a schematic diagram of the frame structure of another pixel driving circuit provided by an embodiment of the present application.
  • Figure 5 is a circuit schematic diagram of another pixel driving circuit provided by an embodiment of the present application.
  • Figure 6 is a schematic diagram of the frame structure of another pixel driving circuit provided by an embodiment of the present application.
  • Figure 7 is a schematic diagram of the framework structure of another pixel driving circuit provided by an embodiment of the present application.
  • Figure 8 is a circuit schematic diagram of another pixel driving circuit provided by an embodiment of the present application.
  • Figure 9 is a circuit schematic diagram of another pixel driving circuit provided by an embodiment of the present application.
  • Figure 10 is a timing diagram of a pixel driving circuit provided by an embodiment of the present application.
  • FIG11 is a flow chart of a method for driving a display panel provided in an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • FIG. 13 is a cross-sectional view along the C1-C2 direction of the display device shown in FIG. 12 .
  • any specific values are to be construed as illustrative only and not as limiting. Accordingly, other examples of the exemplary embodiments may have different values.
  • FIG. 1 is a top view of a display panel 100 provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a pixel driving circuit 200 provided by an embodiment of the present application.
  • the display panel 100 It includes a first display area AA1 and a second display area AA2. Both the first display area AA1 and the second display area AA2 include a plurality of sub-pixels P arranged in an array.
  • the sub-pixels P include a pixel driving circuit 200, wherein the second display area Area AA2 corresponds to the photosensitive element G;
  • the pixel driving circuit 200 located in the second display area AA2 includes at least one transistor, at least part of which is a low-temperature polycrystalline oxide thin film transistor.
  • Figure 1 only illustrates the display panel 100 of the present application by taking the top view structure of the display panel 100 as a rectangle as an example, and does not limit the actual shape of the display panel 100.
  • the top view structure of the display panel 100 The shape can also be embodied as a rounded rectangle, a circle, an oval or a special shape including an arc structure, which is not limited in this application.
  • a display panel 100 provided by an embodiment of the present application includes a first display area AA1 and a second display area AA2, where the second display area AA2 corresponds to the photosensitive element G.
  • the photosensitive element G includes electronic photosensitive devices such as cameras, infrared sensing devices, and fingerprint recognition devices.
  • the second display area AA2 is disposed in the display area AA, the second display area AA2 does not need to occupy the space of the non-display area, which is beneficial to increasing the screen-to-body ratio of the display panel.
  • the second display area AA2 can play a display role; when it is necessary to take photos or videos, the camera takes photos or videos through the second display area AA2. In this way, the second display area AA2 can simultaneously realize the display and shooting functions.
  • the widely used panel technology includes Low Temperature Poly-silicon (LTPS) technology.
  • Low Temperature Poly-silicon Thin Film Transistor (LTPS-TFT) is a low-temperature polysilicon transistor. It has the characteristics of fast response speed and high electron mobility. However, the transmittance of LTPS-TFT is low. When corresponding to the photosensitive element G When more low-temperature polysilicon transistors are arranged in the second display area AA2, it is difficult to increase the transmittance of the second display area AA2.
  • At least some low temperature polycrystalline oxide (LTPO) thin film transistors are arranged in the second display area AA2 corresponding to the photosensitive element G, that is, the At least some of the transistors in the pixel driving circuit 200 in the second display area AA2 use low-temperature polycrystalline oxide thin film transistors.
  • LTPO low temperature polycrystalline oxide
  • the low-temperature polycrystalline oxide thin film transistor when applied to the second display area AA2, it is beneficial to improve the transmittance of the second display area AA2, improve the photosensitive performance of the display panel 100 in the photosensitive stage, and thus help improve the user's Use experience effect.
  • FIG. 1 only shows the situation where the display panel 100 includes one second display area AA2.
  • two or more second display areas can be provided on the display panel 100 as needed. AA2, this application does not limit this.
  • This embodiment will only take the display panel 100 including one second display area AA2 as an example for explanation.
  • the display panel 100 includes two or more second display areas AA2 When doing so, you can refer to the embodiments of this application for execution.
  • FIG. 1 only shows the situation where the first display area AA1 half surrounds the second display area AA2. In some other embodiments of the present application, the first display area AA1 may also completely surround the second display area AA2.
  • FIG. 1 only shows the situation where the first display area AA1 half surrounds the second display area AA2.
  • the first display area AA1 may also completely surround the second display area AA2.
  • the second display area AA2 is located in the display panel 100.
  • This application does not limit other positions; in addition, the shape of the second display area AA2 in Figure 1 is a rectangle, which is only for illustration.
  • the second display area AA2 can also be embodied as a circle. shape, or ellipse or other shapes, the size of the second display area AA2 can also be set according to actual needs, and this application is not limited.
  • the pixel driving circuit 200 includes:
  • the first power signal terminal PVDD is configured to receive the first voltage signal
  • the second power signal terminal PVEE is configured to receive the second voltage signal
  • the gate of the driving transistor M0 is connected to the first node N1, the first pole of the driving transistor M0 is connected to the second node N2, and the second pole of the driving transistor M0 is connected to the third node N3; the driving transistor M0 is set to emit light. stage provides drive current;
  • Light-emitting element D1 the first end of the light-emitting element D1 is connected to the fourth node N4, and the second end of the light-emitting element D1 is connected to the second power signal terminal PVEE; the light-emitting element D1 is configured to respond to the driving current and emit light;
  • the lighting control module 10 has a control terminal connected to the switch signal control terminal Emit, a first terminal connected to the third node N3, and a second terminal connected to the third node N3 of the lighting element D1. One end; the light-emitting control module 10 is set to cut off or turn on the light-emitting element D1;
  • the control terminal of the compensation module 20 is connected to the switch signal control terminal Emit, the first terminal of the compensation module 20 is connected to the first node N1, and the second terminal of the compensation module 20 is connected to the third node N3; during the compensation phase, The compensation module 20 is configured to detect and self-compensate for deviations in the threshold voltage of the drive transistor M0;
  • the first reset module 30 has a control terminal connected to the switch signal control terminal Emit, a first terminal connected to the third node N3, and a second terminal connected to the reset node. Signal terminal Vref; In the initialization phase, the first reset module 30 and the compensation module 20 are jointly configured to reset the first node N1.
  • FIG. 2 only shows one frame structure of the pixel driving circuit 200 in this embodiment.
  • the frame structure of the pixel driving circuit 200 can also be embodied in other forms, and this application is not limited thereto. .
  • the pixel driving circuit 200 provided by the embodiment of the present application includes a driving transistor M0, a light-emitting element D1, and a light-emitting control module 10.
  • the driving transistor M0 is configured to provide a driving current to the light-emitting element D1 during the light-emitting phase;
  • the light-emitting element D1 is configured to provide a driving current to the light-emitting element D1 during the light-emitting phase.
  • Under the control of the control module 10 it emits light in response to the driving current.
  • the control terminal of the compensation module 20 and the control terminal of the lighting control module 10 are both connected to the switch signal control terminal Emit.
  • the way in which the control terminal of the compensation module 20 is connected to the switching signal control terminal Emit can also reduce the leakage phenomenon of the first node N1 during the on or off switching process of the compensation module 20, which is beneficial to the potential of the first node N1 The maintenance is helpful to ensure the accuracy of the light emitting of the light emitting element D1.
  • the control signal of the switch signal control terminal Emit only one of the compensation module 20 and the lighting control module 10 is turned on. For example, during the compensation phase, the compensation module 20 is turned on and the light-emitting control module 10 is turned off; During the light-emitting phase, the compensation module 20 is turned off and the light-emitting control module 10 is turned on.
  • the control terminal of the first reset module 30 is connected to the switch signal control terminal Emit.
  • the first reset module 30 is turned on in response to the conduction level of the switch signal control terminal Emit.
  • the first reset module 30 and the compensation module 20 are turned on at the same time, and the signal of the reset signal terminal Vref is transmitted to the first node N1 through the first reset module 30 and the compensation module 20, and the first node N1 is Reset, this connection method of the first reset module 30 and the compensation module 20 can also reduce the leakage phenomenon of the first node N1 during the on or off switching process of the first reset module 30 and the compensation module 20. For example, it can reduce The leakage current of the first reset module 30 and the compensation module 20 to the first node N1 is reduced, so that the potential of the first node N1 is effectively maintained.
  • the first electrode of the driving transistor M0 is the source electrode
  • the second electrode of the driving transistor M0 is the drain electrode.
  • the source of the driving transistor M0 is connected to the second node N2, and the drain of the driving transistor M0 is connected to the third node N3.
  • the second node N2 is connected to the first power signal terminal PVDD
  • the third node N3 is connected to the lighting control module 10 .
  • the light-emitting control module 10 is connected in series between the third node N3 and the light-emitting element D1, and the control terminal of the light-emitting control module 10 is connected to the switch signal control terminal Emit.
  • the light-emitting control module 10 is turned on or off according to the signal of the switch signal control terminal Emit, thereby controlling the current transmission to the light-emitting element D1.
  • the lighting control module 10 is turned off when the control terminal receives a first level signal, and is turned on when the control terminal receives a second level signal.
  • the control terminal of the lighting control module 10 is connected to the switch signal control terminal Emit.
  • the switch signal control terminal Emit outputs a first level signal
  • the control terminal of the lighting control module 10 receives the first level signal, causing the lighting control module 10 to cut off, and the current cannot pass through the lighting control module 10 It is transmitted to the light-emitting element D1 to drive the light-emitting element D1 to emit light.
  • the switch signal control terminal Emit outputs a second level signal
  • the control terminal of the light-emitting control module 10 receives the second-level signal, causing the light-emitting control module 10 to be turned on, and the current is transmitted to the light-emitting element D1 through the light-emitting control module 10 , driving the light-emitting element D1 to emit light.
  • Figure 3 is a schematic circuit diagram of a pixel driving circuit 200 provided by an embodiment of the present application.
  • the compensation module 20 includes a first transistor M1.
  • the gate of is connected to the switch signal control terminal Emit, the first electrode of the first transistor M1 is connected to the first node N1, and the second electrode of the first transistor M1 is connected to the third node N3; the first transistor M1 is a low-temperature polycrystalline oxidation Thin film transistor.
  • the first transistor M1 in the compensation module 20 in the pixel driving circuit 200 is set as a low-temperature polycrystalline oxide thin film transistor.
  • the low-temperature polycrystalline oxide thin film transistor conducts when the gate receives a high-level signal. On, it turns off when the gate receives a low level signal.
  • the gate of the first transistor M1 is the control terminal of the compensation module 20 , and the gate of the first transistor M1 is connected to the switch signal control terminal Emit.
  • the first transistor M1 is a low-temperature polycrystalline oxide thin film transistor. Since the low-temperature polycrystalline oxide thin film transistor has a high transmittance, it is easy to realize While detecting and self-compensating the threshold voltage of the driving transistor M0, the transmittance of the second display area AA2 can also be effectively improved. In the photosensitive stage, more light is allowed to pass through the second display area AA2 and reach the photosensitive element G, which is beneficial to improving the photosensitive performance of the display panel 100 .
  • the first reset module 30 includes a second transistor M2.
  • the gate of the second transistor M2 is connected to the switch signal control terminal Emit.
  • the first electrode is connected to the third node N3, and the second electrode of the second transistor M2 is connected to the reset signal terminal Vref; the second transistor M2 is a low-temperature polycrystalline oxide thin film transistor.
  • the second transistor M2 is a low-temperature polycrystalline oxide thin film transistor
  • the low-temperature polycrystalline oxide thin film transistor is turned on when the gate receives a high-level signal, and is turned off when the gate receives a low-level signal.
  • the gate of the second transistor M2 is the control terminal of the first reset module 30 , and the gate of the second transistor M2 is connected to the switch signal control terminal Emit.
  • the switch signal control terminal Emit outputs a high-level signal
  • the gate of the second transistor M2 receives the high-level signal
  • the second transistor M2 is turned on
  • the first transistor M1 is turned on at the same time.
  • the reset signal sent by the reset signal terminal Vref is written into the first node N1 via the second transistor M2 and the first transistor M1, thereby realizing the reset of the first node N1.
  • the embodiment of the present application uses the second transistor M2 to form the first reset module 30 in the present application, which can reset the first node N1, clear the residual voltage of the first node N1 in the last light emission, and then make the light-emitting element D1 according to the
  • the preset brightness emits light, which is helpful to improve the accuracy of the lighting brightness of the light-emitting element D1, and when the second transistor M2 is turned on, it writes the reset signal to the first node N1 through the first transistor M1, avoiding the second
  • the problem of excessive leakage of the first node N1 caused by the transistor M2 being directly connected to the first node N1 is beneficial to stabilizing the voltage of the first node N1.
  • the second transistor M2 is a low-temperature polycrystalline oxide thin film transistor, which has the characteristics of high transmittance and low power consumption, and can improve the transmittance of the second display area AA2.
  • the photosensitive stage more light is allowed to pass through the second display area AA2 and reach the photosensitive element G, which is beneficial to improving the photosensitive performance of the display panel 100 .
  • both the first transistor M1 and the second transistor M2 adopt low-temperature polycrystalline oxide thin film transistors, it is more beneficial to improve the transmittance of the second display area AA2.
  • FIG. 4 is a schematic diagram of the frame structure of another pixel driving circuit 200 provided by an embodiment of the present application
  • FIG. 5 is a schematic circuit diagram of another pixel driving circuit 200 provided by an embodiment of the present application.
  • This embodiment shows the first Another implementation of reset module 30. Please refer to Figures 4 and 5.
  • the first reset module 30 also includes a third transistor M3.
  • the gate of the third transistor M3 is connected to the first signal control terminal S1.
  • the first electrode of the transistor M3 is connected to the third node N3, and the second electrode of the third transistor M3 is connected to the first electrode of the second transistor M2; the third transistor M3 is a low-temperature polycrystalline oxide thin film transistor.
  • the third transistor M3 is a low-temperature polycrystalline oxide thin film transistor
  • the low-temperature polycrystalline oxide thin film transistor is turned on when the gate receives a high-level signal, and is turned off when the gate receives a low-level signal.
  • the gate of the third transistor M3 is connected to the first signal control terminal S1.
  • the first signal control terminal S1 outputs a high-level signal
  • the gate of the third transistor M3 receives the high-level signal
  • the third transistor M3 is turned on.
  • the first transistor M1 and the third transistor M3 are turned on.
  • the second transistor M2 is turned on.
  • the reset signal sent by the reset signal terminal Vref is written into the first node N1 through the second transistor M2, the third transistor M3 and the first transistor M1, thereby realizing the reset of the first node N1.
  • the first signal control terminal S1 outputs a low-level signal
  • the gate of the third transistor M3 receives the low-level signal
  • the third transistor M3 is turned off to prevent the reset signal terminal Vref from The reset signal continues to be transmitted to the first node N1.
  • the third transistor M3 is a low-temperature polycrystalline oxide thin film transistor, which has the characteristics of high transmittance and low power consumption, and can improve the transmittance of the second display area AA2. In the photosensitive stage, more light is allowed to pass through the second display area AA2 and reach the photosensitive element G, which is beneficial to improving the photosensitive performance of the display panel 100 .
  • the pixel driving circuit 200 further includes a data writing module 40 .
  • the control end of the data writing module 40 is connected to the first signal control end S1 .
  • the first end of the data writing module 40 is connected to The data signal terminal Vdata, the second terminal of the data writing module 40 is connected to the second node N2; the data writing module 40 is configured to provide a data signal to the driving transistor M0.
  • the data writing module 40 is connected in series between the data signal terminal Vdata and the second node N2, and the control terminal of the data writing module 40 is connected to the first signal control terminal S1.
  • the data writing module 40 is turned on or off according to the signal of the first signal control terminal S1.
  • the first reset module 30 also includes a third transistor M3.
  • the control end of the third transistor M3 and the control end of the data writing module 40 are both connected to the first signal control end S1, and there is no need to be the first reset module.
  • the third transistor M3 of 30 and the data writing module 40 respectively introduce different signal control terminals, which is beneficial to simplifying the overall design of the display panel 100 .
  • the data writing module 40 is turned off when the control terminal receives a high-level signal, and is turned on when the control terminal receives a low-level signal.
  • the control terminal of the data writing module 40 is connected to the first signal control terminal S1.
  • the first signal control terminal S1 outputs a low-level signal
  • the control terminal of the data writing module 40 receives the low-level signal
  • the data writing module 40 is turned on, and the data signal passes through the data writing phase.
  • the input module 40 is transmitted to the second node N2 to provide a data signal to the driving transistor M0.
  • the driving transistor M0 In the light-emitting stage, the driving transistor M0 generates a driving current for driving the light-emitting element D1 to emit light according to the data signal and the signal of the first power signal terminal PVDD.
  • the lighting control module 10 includes a fourth transistor M4 .
  • the gate of the fourth transistor M4 is connected to the switch signal control terminal Emit.
  • the fourth transistor M4 The first electrode of the fourth transistor M4 is connected to the third node N3, and the second electrode of the fourth transistor M4 is connected to the first terminal of the light-emitting element D1.
  • the fourth transistor M4 is a low-temperature polysilicon thin film transistor.
  • the fourth transistor M4 is a P-type transistor or an N-type transistor.
  • the fourth transistor M4 When the fourth transistor M4 is a P-type transistor, its gate is turned on when it receives a low-level signal, and when it receives a high-level signal Turn off; when the fourth transistor M4 is an N-type transistor, its gate is turned on when receiving a high-level signal and turned off when receiving a low-level signal.
  • the embodiments shown in Figures 3 and 5 are only described by taking the fourth transistor M4 as a P-type transistor as an example. In some other embodiments of the present application, the fourth transistor M4 can also be embodied as an N-type transistor. This application Not limited.
  • the embodiment of the present application uses the fourth transistor M4 to constitute the light-emitting control module 10 in the present application.
  • the structure is simple, and while realizing the control of the on or off of the light-emitting element D1, it is also conducive to simplifying the circuit of the pixel driving circuit 200. structure.
  • the fourth transistor M4 is a low-temperature polysilicon thin film transistor, which has high electron mobility and can improve the current carrying capacity and response speed of the second display area AA2.
  • the data writing module 40 includes a sixth transistor M6 .
  • the gate of the sixth transistor M6 is connected to the first signal control terminal S1 .
  • the first electrode of the sixth transistor M6 is connected to the data signal terminal.
  • Vdata, the second pole of the sixth transistor M6 is connected to the second node N2.
  • the sixth transistor M6 is a low-temperature polysilicon thin film transistor.
  • the sixth transistor M6 is a P-type transistor or an N-type transistor.
  • the sixth transistor M6 When the sixth transistor M6 is a P-type transistor, its gate is turned on when it receives a low-level signal, and when it receives a high-level signal Cut off; when the sixth transistor M6 is an N-type transistor, its gate is turned on when it receives a high-level signal, and is turned off when it receives a low-level signal.
  • the embodiments shown in Figures 3 and 5 are only explained by taking the sixth transistor M6 as a P-type transistor as an example. In some other embodiments of the present application, the sixth transistor M6 can also be embodied as an N-type transistor. This application Not limited.
  • the pixel driving circuit 200 also includes a power supply voltage writing module 50.
  • the control terminal of the power supply voltage writing module 50 is connected to the switch signal control terminal Emit.
  • the first terminal of the power supply voltage writing module 50 Connected to the first power signal terminal PVDD, the second end of the power voltage writing module 50 is connected to the second node N2; the power voltage writing module 50 is configured to write the first power signal terminal PVDD output to the driving transistor M0 during the light-emitting phase. the first voltage signal.
  • the power supply voltage writing module 50 is connected in series between the first power signal terminal PVDD and the second node N2, and the control terminal of the power supply voltage writing module 50 is connected to the switch signal control terminal Emit.
  • the power supply voltage writing module 50 is turned on or off according to the signal of the switch signal control terminal Emit.
  • the control terminal of the power supply voltage writing module 50 is connected to the switch signal control terminal Emit, and there is no need to set up an additional signal control terminal for the power supply voltage writing module 50. Therefore, it is conducive to simplifying the structure of the pixel driving circuit 200 and simplifying the display. Overall structure of panel 100.
  • the power supply voltage writing module 50 includes a seventh transistor M7 , the gate of the seventh transistor M7 is connected to the switch signal control terminal Emit, and the first electrode of the seventh transistor M7 is connected to the first power supply.
  • the signal terminal PVDD and the second pole of the seventh transistor M7 are connected to the second node N2.
  • the seventh transistor M7 is a low-temperature polysilicon thin film transistor.
  • the seventh transistor M7 is a P-type transistor or an N-type transistor.
  • the seventh transistor M7 When the seventh transistor M7 is a P-type transistor, its gate receives a low voltage.
  • the seventh transistor M7 is an N-type transistor, its gate is turned on when receiving a high-level signal and turned off when receiving a low-level signal. .
  • the embodiments shown in Figures 3 and 5 are only explained by taking the seventh transistor M7 as a P-type transistor as an example. In some other embodiments of the present application, the seventh transistor M7 can also be embodied as an N-type transistor. This application will Not limited.
  • the switch signal control terminal Emit outputs a low-level signal
  • the gate of the seventh transistor M7 receives the low-level signal
  • the seventh transistor M7 conducts Pass
  • the first voltage signal is transmitted to the second node N2 through the seventh transistor M7
  • the first voltage signal is provided to the driving transistor M0 to generate a driving current for driving the light-emitting element D1 to emit light.
  • the pixel driving circuit 200 further includes a storage capacitor Cst.
  • the first pole of the storage capacitor Cst is connected to the first power signal terminal PVDD, and the second pole of the storage capacitor Cst is connected to the first power signal terminal PVDD.
  • Node N1; the storage capacitor Cst is set to maintain the potential of the first node N1.
  • the storage capacitor Cst is connected in series between the first power signal terminal PVDD and the first node N1.
  • the storage function of the storage capacitor Cst compensates for the voltage change of the first node N1 caused by the leakage current, thereby ensuring the voltage of the first node N1 and improving the display quality of the display panel 100.
  • FIG. 6 is a schematic structural diagram of another pixel driving circuit 200 provided by an embodiment of the application.
  • FIG. 7 is a schematic structural diagram of another pixel driving circuit 200 provided by an embodiment of the application. This embodiment shows the pixel driving process.
  • the second reset module 60 is introduced into the circuit 200.
  • the difference between FIG. 6 and FIG. 7 is that the structure of the first reset module 30 is different.
  • the pixel driving circuit 200 further includes a second reset module 60.
  • the control terminal of the second reset module 60 is connected to the second signal control terminal S2.
  • the first end of the second reset module 60 is connected to the reset signal terminal Vref, and the second end of the second reset module 60 is connected to the first end of the light-emitting element D1; in the initialization phase, the second reset module 60 is configured to connect to the fourth node N4 Perform a reset.
  • the second reset module 60 is connected in series between the reset signal terminal Vref and the fourth node N4, and the control terminal of the second reset module 60 is connected to the second signal control terminal S2.
  • the second reset module 60 is turned on or off according to the signal of the second signal control terminal S2.
  • the fourth node N4 is reset, thereby realizing the reset of the anode of the light-emitting element D1.
  • FIG. 8 is a circuit schematic diagram of another pixel driving circuit 200 provided by an embodiment of the present application
  • FIG. 9 is a circuit schematic diagram of another pixel driving circuit 200 provided by an embodiment of the present application.
  • FIG. 8 is a modification of the structure of FIG. 6 Refinement.
  • Figure 9 is a refinement of the structure of Figure 7. The embodiments shown in Figures 8 and 9 both refine the structure of the pixel driving circuit 200. The difference lies in the composition of the first reset module 30.
  • the second reset module 60 includes a fifth transistor M5.
  • the gate of the fifth transistor M5 is connected to the second signal control terminal S2.
  • the first terminal of M5 is connected to the reset signal terminal Vref, and the second terminal of the fifth transistor M5 is connected to the first terminal of the light-emitting element D1;
  • the fifth transistor M5 is a low-temperature polycrystalline oxide thin film transistor.
  • the fifth transistor M5 is a low-temperature polycrystalline oxide thin film transistor.
  • the low-temperature polycrystalline oxide thin film transistor is turned on when the gate receives a high-level signal, and is turned off when the gate receives a low-level signal.
  • the gate of the fifth transistor M5 is the control terminal of the second reset module 60 , and the gate of the fifth transistor M5 is connected to the second signal control terminal S2 .
  • the second signal control terminal S2 outputs a high-level signal
  • the gate of the fifth transistor M5 receives the high-level signal
  • the fifth transistor M5 is turned on
  • the reset signal terminal Vref sends a reset signal. It is transmitted to the fourth node N4 via the fifth transistor M5 to realize the reset of the fourth node N4.
  • the embodiment of the present application uses the fifth transistor M5 to form the second reset module 60 in the present application.
  • the structure is simple and can reset the fourth node N4, clear the residual voltage of the fourth node N4 in the last light-emitting process, and then enable The light-emitting element D1 emits light according to a preset brightness. While improving the accuracy of the light-emitting brightness of the light-emitting element D1, it is also helpful to simplify the circuit structure of the pixel driving circuit 200.
  • the fifth transistor M5 is a low-temperature polycrystalline oxide thin film transistor, which has the characteristics of high transmittance and low power consumption, and can improve the transmittance of the second display area AA2. In the photosensitive stage, more light is allowed to pass through the second display area AA2 and reach the photosensitive element G, which is beneficial to improving the photosensitive performance of the display panel 100 .
  • FIG. 10 is a timing diagram of a pixel driving circuit provided by an embodiment of the present application
  • FIG. 11 is a flow chart of a driving method of a display panel provided by an embodiment of the present application. .
  • the display panel 100 includes: a compensation module 20, a first reset module 30, a data writing module 40, a driving transistor M0, a power supply voltage writing module 50, a light emitting control module 10 and a light emitting element D1;
  • Driving methods include:
  • the compensation module 20 and the first reset module 30 are turned on, and the first reset module 30 and the compensation module 20 transmit the reset signal of the reset signal terminal Vref to the first node N1 to reset the first node N1;
  • the data writing module 40 and the compensation module 20 are turned on, the data signal of the data signal terminal Vdata is transmitted to the second node N2 through the data writing module 40, and the signal of the second node N2 is transmitted through the driving transistor M0.
  • the signal of the third node N3 is transmitted to the first node N1 through the compensation module 20;
  • the power supply voltage writing module 50 and the lighting control module 10 are turned on.
  • the power supply voltage writing module 50 transmits the first voltage signal of the first power signal terminal PVDD to the second node N2, and the driving transistor M0 forms a current transmission. to the light-emitting element D1.
  • the first signal control terminal S1 outputs a high-level signal
  • the second signal control terminal S2 outputs a high-level signal
  • the switch signal control terminal Emit outputs a high-level signal.
  • the compensation module 20 and the first reset module 30 are turned on, and the first reset module 30 and the compensation module 20 transmit the reset signal of the reset signal terminal Vref to the first node N1 to reset the first node N1.
  • the initialization phase T1 can reset the first node N1 and clear the remaining voltage of the first node N1 in the last light emission, thereby causing the light-emitting element D1 to emit light according to the preset brightness, thereby improving the accuracy of the light-emitting brightness of the light-emitting element D1.
  • the first signal control terminal S1 outputs a low-level signal
  • the second signal control terminal S2 outputs a high-level signal
  • the data writing module 40, the driving transistor M0 and the compensation module 20 are turned on, the data signal of the data signal terminal Vdata is transmitted to the second node N2 through the data writing module 40, and the signal of the second node N2 is transmitted to the third node N2 through the driving transistor M0.
  • Node N3, the signal of the third node N3 is transmitted to the first node N1 through the compensation module 20.
  • the first signal control terminal S1 outputs a high-level signal
  • the second signal control terminal S2 outputs a low-level signal
  • the switch signal control terminal Emit outputs a low-level signal.
  • the power supply voltage writing module 50 and the light emitting control module 10 are connected.
  • the power supply voltage writing module 50 transmits the first voltage signal of the first power signal terminal PVDD to the second node N2, and the driving transistor M0 forms a current and transmits it to the light emitting element D1.
  • the driving transistor M0 generates a driving current for driving the light-emitting element D1 to emit light according to the data signal written in the data writing phase T2 and the signal of the first power signal terminal PVDD.
  • both the first reset module 30 and the compensation module 20 in the pixel driving circuit 200 use low-temperature polycrystalline oxide thin film transistors to effectively improve the transmittance of the second display area AA2.
  • the display panel 100 further includes: a second reset module 60;
  • Driver methods also include:
  • the second reset module 60 is turned on, and the second reset module 60 transmits the reset signal to the fourth node N4 to reset the fourth node N4.
  • this embodiment is explained by taking the transistor in the second reset module 60 as a low-temperature polycrystalline oxide thin film transistor.
  • the low-temperature polycrystalline oxide thin film transistor is turned on when its gate receives a high-level signal. , cut off when receiving a low level signal.
  • the first signal control terminal S1 outputs a high-level signal
  • the second signal control terminal S2 outputs a high-level signal
  • the switch signal control terminal Emit outputs a high-level signal.
  • the second reset module 60 is turned on, and the second reset module 60 transmits the reset signal to the fourth node N4 to reset the fourth node N4.
  • the residual voltage of the fourth node N4 in the last light emission can be cleared, thereby causing the light-emitting element D1 to emit light according to the preset brightness.
  • the present application also provides a display device. Please refer to Figure 12.
  • Figure 12 shows a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the display device 500 provided by this embodiment includes any of the above implementations of the present application.
  • the provided display panel 100 is shown in the example.
  • the display device 500 provided in the embodiment of the present application can be a computer, a mobile phone, a tablet, or other display device with a display function, which is not limited by the present application.
  • the display device provided by the embodiment of the present application has the effect of the display panel provided by the embodiment of the present application. Reference can be made to the description of the display panel in the above embodiments, and the details of this embodiment will not be repeated here.
  • the display device 500 provided in the embodiment of the present application further includes a photosensitive element G.
  • the photosensitive element G is located in the second display area AA2 of the display panel 100.
  • the photosensitive element G included in the display device 500 is an electronic photosensitive device such as a camera, an infrared sensing device, a fingerprint recognition device, etc.
  • the second display area AA2 is used to perform the display function; in the photosensitive stage, the photosensitive element G in the second display area AA2 is configured to sense light.
  • the display panel 100 provided in the embodiment of the present application can be applied to a display device, and can be embodied as any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator.
  • the display panel, its driving method and the display device provided by this application at least achieve the following effects:
  • a plurality of sub-pixels arranged in an array are provided in both the first display area AA1 and the second display area AA2, and each sub-pixel includes a pixel driving circuit 200.
  • the second display area AA2 is configured to provide electronic photosensitive devices such as cameras, infrared sensing devices, and fingerprint recognition devices.
  • At least part of the plurality of transistors included in the pixel driving circuit 200 of the second display area AA2 are low-temperature polycrystalline oxide thin film transistors. Since the low-temperature polycrystalline oxide thin film transistor has a high transmittance, when the second display area AA2 is used for light recognition, such as when taking a photo, the second display area AA2 can become transparent glass.
  • the light is allowed to pass through the second display area AA2 and reach the photosensitive element G provided below the second display area AA2, thereby completing the imaging function.
  • the second display area AA2 can be displayed together with the first display area AA1, which is beneficial to increasing the screen-to-body ratio.
  • Replacing at least part of the transistors in the second display area AA2 with low-temperature polycrystalline oxide thin film transistors effectively improves the transmittance of the second display area AA2, thereby conducive to improving the photosensitive performance of the second display area AA2.

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Abstract

一种显示面板及其驱动方法和显示装置，该显示面板包括:第一显示区（AA1）和第二显示区（AA2），第一显示区（AA1）和第二显示区（AA2）均包括多个呈阵列排列的子像素（P），每个子像素（P）包括像素驱动电路（200），其中，第二显示区（AA2）与感光元件（G）对应；位于第二显示区（AA2）的每个像素驱动电路（200）包括至少一个晶体管，晶体管中的至少一个为低温多晶氧化物薄膜晶体管。

Description

显示面板及其驱动方法和显示装置
本申请要求在2022年09月13日提交中国专利局、申请号为202211110896.X的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，例如，涉及一种显示面板及其驱动方法和显示装置。
背景技术
随着技术进步，消费者对大屏需求日益增加，无论是刘海显示屏、水滴显示屏还是升降摄像头，其设计目的均是提高显示面板的屏占比。
相关技术中，提供了一种屏下显示面板，即将光学器件(例如摄像头)设置于显示屏下方。当需要拍照时，显示屏会变成透明的玻璃状，使外界的光线穿过显示屏到达摄像头，当不需要拍照时，显示屏能够正常显示。然而，无论是液晶显示器(Liquid Crystal Display，LCD)装置还是有机发光二极管(Organic Light-Emitting Diode，OLED)显示装置，光学器件区的透过率均难以提升。
发明内容
本申请提供了一种显示面板及其驱动方法和显示装置，旨在有效提升光学器件区的透过率。
本申请提供一种显示面板，包括第一显示区和第二显示区，第一显示区和第二显示区均包括多个呈阵列排列的子像素，每个子像素包括像素驱动电路，其中，第二显示区与感光元件对应；
位于第二显示区的每个像素驱动电路包括至少一个晶体管，晶体管中的至少一个为低温多晶氧化物薄膜晶体管。
本申请还提供一种显示面板的驱动方法，用于驱动上述提供的显示面板，
驱动方法包括：
在初始化阶段，补偿模块和第一复位模块导通，第一复位模块和补偿模块将复位信号端的复位信号传输至第一节点，对第一节点进行复位；
在数据写入阶段，像素驱动电路包括的数据写入模块，驱动晶体管和补偿模块导通，数据写入模块的第一端所连接的数据信号端的数据信号通过数 据写入模块的第二端传输至第二节点，第二节点的信号通过驱动晶体管传输至第三节点，第三节点的信号通过补偿模块传输至第一节点；
在发光阶段，像素驱动电路包括的电源电压写入模块、驱动晶体管和发光控制模块导通，电源电压写入模块将第一电源信号端的第一电压信号传输至第二节点，驱动晶体管形成电流传输至发光元件。
本申请还提供一种显示装置，包括本申请上述提供的显示面板。
附图说明
图1为本申请实施例所提供的一种显示面板的俯视图；
图2为本申请实施例所提供的一种像素驱动电路的框架结构示意图；
图3为本申请实施例所提供的一种像素驱动电路的电路示意图；
图4为本申请实施例所提供的另一种像素驱动电路的框架结构示意图；
图5为本申请实施例所提供的另一种像素驱动电路的电路示意图；
图6为本申请实施例所提供的另一种像素驱动电路的框架结构示意图；
图7为本申请实施例所提供的另一种像素驱动电路的框架结构示意图；
图8为本申请实施例所提供的另一种像素驱动电路的电路示意图；
图9为本申请实施例所提供的另一种像素驱动电路的电路示意图；
图10为本申请实施例所提供的一种像素驱动电路的时序图；
图11为本为申请实施例所提供的一种显示面板的驱动方法的流程图；
图12为本申请实施例所提供的一种显示装置的结构示意图。
图13为沿着图12所示显示装置的C1-C2方向的剖视图。
具体实施方式
现在将参照附图来描述本申请的至少一种示例性实施例。除非另外说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本申请的范围。
以下对至少一个示例性实施例的描述实际上仅仅是说明性的，不作为对本申请及其应用或使用的任何限制。
对于已知的技术、方法和设备可能不作讨论，但在适当情况下，所述已知的技术、方法和设备应当被视为说明书的一部分。
在这里示出和讨论的所有例子中，任何具体值应被解释为仅仅是示例性的，而不是作为限制。因此，示例性实施例的其它例子可以具有不同的值。
相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行讨论。
图1为本申请实施例所提供的一种显示面板100的俯视图，图2为本申请实施例所提供的一种像素驱动电路200的结构示意图，参照图1和图2所示，显示面板100包括第一显示区AA1和第二显示区AA2，第一显示区AA1和第二显示AA2区均包括多个呈阵列排列的子像素P，子像素P包括像素驱动电路200，其中，第二显示区AA2与感光元件G对应；
位于第二显示区AA2的像素驱动电路200包括至少一个晶体管，晶体管中至少部分为低温多晶氧化物薄膜晶体管。
图1仅以显示面板100的俯视结构为矩形为例对本申请的显示面板100进行示意，并不对显示面板100的实际形状进行限定，在本申请的一些其他实施例中，显示面板100的俯视结构的形状还可体现为圆角矩形、圆形、椭圆形或者包括弧形结构的异形，本申请对此不进行限定。
本申请实施例提供的一种显示面板100包括第一显示区AA1和第二显示区AA2，其中，第二显示区AA2与感光元件G对应。可选地，感光元件G包括摄像头、红外感测器件和指纹识别器件等电子感光器件。当将第二显示区AA2设置于显示区AA时，第二显示区AA2无需占用非显示区的空间，因而有利于提升显示面板的屏占比。以第二显示区AA2设置有摄像头为例，在正常显示时，第二显示区AA2可以发挥显示作用；在需要拍照或拍视频时，摄像头通过该第二显示区AA2进行照片或视频的拍摄，如此第二显示区AA2可同步实现显示和拍摄的功能。
相关技术中，广泛应用的面板技术包括低温多晶硅(Low Temperature Poly-silicon，LTPS)技术。低温多晶硅晶体管(Low Temperature Poly-silicon Thin Film Transistor，LTPS-TFT)即低温多晶硅晶体管，具有反应速度快和电子迁移率高等特点，但LTPS-TFT的透过率较低，当与感光元件G对应的第二显示区AA2内布设较多的低温多晶硅晶体管时，难以提升第二显示区AA2的透过率。
鉴于此，本申请实施例所提供的显示面板100中，在对应感光元件G的第二显示区AA2内布置至少部分低温多晶氧化物(Low Temperature Polycrystalline Oxide，LTPO)薄膜晶体管，即，将设置于第二显示区AA2中的像素驱动电路200中的至少部分晶体管采用低温多晶氧化物薄膜晶体 管，相比于低温多晶硅晶体管而言，低温多晶氧化物薄膜晶体管具有更高的透过率，因此，当将低温多晶氧化物薄膜晶体管应用在第二显示区AA2时，有利于提升第二显示区AA2的透过率，提升显示面板100在感光阶段的感光性能，进而有利于提升用户的使用体验效果。
图1仅示出了显示面板100中包括一个第二显示区AA2的情形，在本申请的一些其他实施例中，显示面板100上还可根据需要设置两个或更多数量的第二显示区AA2，本申请对此不进行限定，本实施例将仅以显示面板100中包括一个第二显示区AA2为例进行说明，当显示面板100中包括两个及两个以上的第二显示区AA2时，均可参考本申请的实施例执行。图1仅示出了第一显示区AA1半包围第二显示区AA2的情形，在本申请的一些其他实施例中，第一显示区AA1还可全包围第二显示区AA2。图1也仅示出了显示面板100中第一显示区AA1和第二显示区AA2的一种相对位置关系，在本申请的一些其他实施例中，第二显示区AA2位于显示面板100中的其他位置，本申请对此不进行限定；另外，图1中第二显示区AA2的形状为矩形也仅为示意，在本申请的一些其他实施例中，第二显示区AA2还可体现为圆形、或椭圆形等其他形状，第二显示区AA2的尺寸也可根据实际需求进行设定，本申请对此也不进行限定。
在本申请的一些可选实施例中，像素驱动电路200包括：
第一电源信号端PVDD和第二电源信号端PVEE，第一电源信号端PVDD设置为接收第一电压信号，第二电源信号端PVEE设置为接收第二电压信号；
驱动晶体管M0，驱动晶体管M0的栅极连接到第一节点N1，驱动晶体管M0的第一极连接第二节点N2，驱动晶体管M0的第二极连接第三节点N3；驱动晶体管M0设置为在发光阶段提供驱动电流；
发光元件D1，发光元件D1的第一端连接于第四节点N4，发光元件D1的第二端连接于第二电源信号端PVEE；发光元件D1设置为响应驱动电流并发光；
发光控制模块10，发光控制模块10的控制端连接于开关信号控制端Emit，发光控制模块10的第一端连接于第三节点N3，发光控制模块10的第二端连接于发光元件D1的第一端；发光控制模块10设置为截止或导通发光元件D1；
补偿模块20，补偿模块20的控制端连接于开关信号控制端Emit，补偿模块20的第一端连接于第一节点N1，补偿模块20的第二端连接于第三节点N3；在补偿阶段，补偿模块20设置为检测和自补偿驱动晶体管M0的阈值 电压的偏差；
第一复位模块30，第一复位模块30的控制端连接于开关信号控制端Emit，第一复位模块30的第一端连接于第三节点N3，第一复位模块30的第二端连接于复位信号端Vref；在初始化阶段，第一复位模块30和补偿模块20共同设置为对第一节点N1进行复位。
图2仅示出了本实施例中像素驱动电路200的一种框架结构，在本申请的一些其他实施例中，像素驱动电路200的框架结构还可体现为其它，本申请对此不进行限定。
本申请实施例提供的像素驱动电路200，包括驱动晶体管M0、发光元件D1和发光控制模块10，其中，驱动晶体管M0设置为在发光阶段向发光元件D1提供驱动电流；发光元件D1设置为在发光控制模块10的控制下响应驱动电流而发光。本实施例中，补偿模块20的控制端与发光控制模块10的控制端均连接至开关信号控制端Emit，如此，无需将补偿模块20和发光控制模块10分别连接不同的控制端，由此简化像素驱动电路200的设计。此外，将补偿模块20的控制端与开关信号控制端Emit连接的方式，还可减小第一节点N1在补偿模块20导通或截止切换过程中的漏流现象，有利于第一节点N1电位的保持，有利于保证发光元件D1的发光准确性。可选地，在开关信号控制端Emit的控制信号的控制下，补偿模块20与发光控制模块10中仅有一者导通，例如，在补偿阶段，补偿模块20导通，发光控制模块10截止；在发光阶段，补偿模块20截止，发光控制模块10导通。
本申请实施例中，第一复位模块30的控制端连接于开关信号控制端Emit，在初始化阶段，第一复位模块30响应开关信号控制端Emit的导通电平而导通。可选地，在初始化阶段，第一复位模块30与补偿模块20同时导通，复位信号端Vref的信号通过第一复位模块30与补偿模块20传输至第一节点N1，对第一节点N1进行复位，第一复位模块30和补偿模块20的此种连接方式，同样可减小第一节点N1在第一复位模块30和补偿模块20导通或截止切换过程中的漏流现象，例如可减小第一复位模块30和补偿模块20向第一节点N1的漏流，使得第一节点N1的电位得以有效保持。
可选地，驱动晶体管M0的第一极为源极，驱动晶体管M0的第二极为漏极。驱动晶体管M0的源极连接第二节点N2，驱动晶体管M0的漏极连接第三节点N3。其中，第二节点N2连接第一电源信号端PVDD，第三节点N3连接发光控制模块10。可选地，发光控制模块10串联于第三节点N3和发光元件D1之间，发光控制模块10的控制端连接开关信号控制端Emit。发光控制模块10根据开关信号控制端Emit的信号导通或截止，进而控制电流 传输至发光元件D1。可选地，发光控制模块10在控制端接收到第一电平信号时截止，在控制端接收到第二电平信号时导通。发光控制模块10的控制端连接开关信号控制端Emit。在初始化阶段和数据写入阶段，开关信号控制端Emit输出第一电平信号，发光控制模块10的控制端接收到第一电平信号，使发光控制模块10截止，电流无法通过发光控制模块10传输至发光元件D1，驱动发光元件D1发光。在发光阶段，开关信号控制端Emit输出第二电平信号，发光控制模块10的控制端接收到第二电平信号，使发光控制模块10导通，电流通过发光控制模块10传输至发光元件D1，驱动发光元件D1发光。
图3为本申请实施例所提供的一种像素驱动电路200的电路示意图，请参考图3，在本申请的一种可选实施例中，补偿模块20包括第一晶体管M1，第一晶体管M1的栅极连接于开关信号控制端Emit，第一晶体管M1的第一极连接于第一节点N1，第一晶体管M1的第二极连接于第三节点N3；第一晶体管M1为低温多晶氧化物薄膜晶体管。
本实施例将像素驱动电路200中补偿模块20内的第一晶体管M1设置为低温多晶氧化物薄膜晶体管，可选地，低温多晶氧化物薄膜晶体管在栅极接收到高电平信号时导通，在栅极接收到低电平信号时截止。第一晶体管M1的栅极为补偿模块20的控制端，第一晶体管M1的栅极连接于开关信号控制端Emit。
本申请实施例采用第一晶体管M1构成本申请中的补偿模块20时，第一晶体管M1采用低温多晶氧化物薄膜晶体管，由于低温多晶氧化物薄膜晶体管具有较高的透过率，在实现对驱动晶体管M0的阈值电压进行检测和自补偿的同时，还能够有效提高第二显示区AA2的透过率。在感光阶段，使更多的光线穿过第二显示区AA2到达感光元件G，从而有利于提升显示面板100的感光性能。
在本申请的一种可选实施例中，继续参照图3所示，第一复位模块30包括第二晶体管M2，第二晶体管M2的栅极连接于开关信号控制端Emit，第二晶体管M2的第一极连接于第三节点N3，第二晶体管M2的第二极连接于复位信号端Vref；第二晶体管M2为低温多晶氧化物薄膜晶体管。
可选地，第二晶体管M2为低温多晶氧化物薄膜晶体管时，低温多晶氧化物薄膜晶体管在栅极接收到高电平信号时导通，在栅极接收到低电平信号时截止。第二晶体管M2的栅极为第一复位模块30的控制端，第二晶体管M2的栅极连接于开关信号控制端Emit。在像素驱动电路200的初始化阶段，开关信号控制端Emit输出高电平信号，第二晶体管M2的栅极接收到高电平信号，第二晶体管M2导通，同时第一晶体管M1导通。复位信号端Vref发 出的复位信号经由第二晶体管M2和第一晶体管M1写入第一节点N1，实现对第一节点N1的复位。
本申请实施例采用第二晶体管M2构成本申请中的第一复位模块30的方式，能够对第一节点N1进行复位，清除上一次发光中第一节点N1残留的电压，进而使发光元件D1按照预设的亮度发光，因此有利于提升发光元件D1的发光亮度的准确性，并且第二晶体管M2在导通时，是通过第一晶体管M1向第一节点N1写入复位信号，避免了第二晶体管M2直接连接于第一节点N1而导致的第一节点N1漏流过大的问题，有利于稳定第一节点N1的电压。同时，第二晶体管M2为低温多晶氧化物薄膜晶体管，其具有透过率高和功耗低等特性，能够提高第二显示区AA2的透过率。在感光阶段，使更多的光线穿过第二显示区AA2到达感光元件G，从而有利于提升显示面板100的感光性能。
可选地，当第一晶体管M1和第二晶体管M2均采用低温多晶氧化物薄膜晶体管时，更加有利于提升第二显示区AA2的透过率。
图4为本申请实施例所提供的另一种像素驱动电路200的框架结构示意图；图5为本申请实施例所提供的另一种像素驱动电路200的电路示意图，本实施例示出了第一复位模块30的另一种实现方式。请参考图4和图5，在本申请的一种可选实施例中，第一复位模块30还包括第三晶体管M3，第三晶体管M3的栅极连接于第一信号控制端S1，第三晶体管M3的第一极连接于第三节点N3，第三晶体管M3的第二极连接于第二晶体管M2的第一极；第三晶体管M3为低温多晶氧化物薄膜晶体管。
可选地，第三晶体管M3为低温多晶氧化物薄膜晶体管时，低温多晶氧化物薄膜晶体管在栅极接收到高电平信号时导通，在栅极接收到低电平信号时截止。第三晶体管M3的栅极连接第一信号控制端S1。在像素驱动电路200的初始化阶段，第一信号控制端S1输出高电平信号，第三晶体管M3的栅极接收到高电平信号，第三晶体管M3导通，同时，第一晶体管M1和第二晶体管M2导通。复位信号端Vref发出的复位信号经由第二晶体管M2、第三晶体管M3和第一晶体管M1写入第一节点N1，实现对第一节点N1的复位。在像素驱动电路200的数据写入阶段，第一信号控制端S1输出低电平信号，第三晶体管M3的栅极接收到低电平信号，第三晶体管M3截止，防止复位信号端Vref发出的复位信号继续传输至第一节点N1。本实施例中，第三晶体管M3为低温多晶氧化物薄膜晶体管，其具有透过率高和功耗低等特性，能够提高第二显示区AA2的透过率。在感光阶段，使更多的光线穿过第二显示区AA2到达感光元件G，从而有利于提升显示面板100的感光性能。
继续参照图2或图4所示，像素驱动电路200还包括数据写入模块40，数据写入模块40的控制端连接于第一信号控制端S1，数据写入模块40的第一端连接于数据信号端Vdata，数据写入模块40的第二端连接于第二节点N2；数据写入模块40设置为向驱动晶体管M0提供数据信号。
本申请实施例中，数据写入模块40串联于数据信号端Vdata和第二节点N2之间，数据写入模块40的控制端连接第一信号控制端S1。数据写入模块40根据第一信号控制端S1的信号导通或截止。在数据写入模块40导通时，数据信号端Vdata的数据信号通过数据写入模块40传输至驱动晶体管M0的第二节点N2。本申请实施例中，第一复位模块30还包括第三晶体管M3，第三晶体管M3的控制端与数据写入模块40的控制端均连接至第一信号控制端S1，无需为第一复位模块30的第三晶体管M3和数据写入模块40分别引入不同的信号控制端，因而有利于简化显示面板100的整体设计。
可选地，数据写入模块40在控制端接收到高电平信号时截止，在控制端接收到低电平信号时导通。数据写入模块40的控制端连接第一信号控制端S1。在像素驱动电路200的数据写入阶段，第一信号控制端S1输出低电平信号，数据写入模块40的控制端接收低电平信号，数据写入模块40导通，数据信号通过数据写入模块40传输至第二节点N2，向驱动晶体管M0提供数据信号。在发光阶段，驱动晶体管M0根据该数据信号以及第一电源信号端PVDD的信号生成用以驱动发光元件D1发光的驱动电流。
在本申请的一种可选实施例中，参照图3或图5所示，发光控制模块10包括第四晶体管M4，第四晶体管M4的栅极连接于开关信号控制端Emit，第四晶体管M4的第一极连接于第三节点N3，第四晶体管M4的第二极连接于发光元件D1的第一端。
可选地，第四晶体管M4为低温多晶硅薄膜晶体管。可选地，第四晶体管M4为P型晶体管或者N型晶体管，当第四晶体管M4为P型晶体管时，其栅极在接收到低电平信号时导通，在接收到高电平信号时截止；当第四晶体管M4为N型晶体管时，其栅极在接收到高电平信号时导通，在接收到低电平信号时截止。图3和图5所示实施例仅以第四晶体管M4为P型晶体管为例进行说明，在本申请的一些其他实施例中，第四晶体管M4还可体现为N型晶体管，本申请对此不进行限定。
本申请实施例采用第四晶体管M4构成本申请中的发光控制模块10的方式，结构简单，在实现对发光元件D1的导通或截止的控制的同时，还有利于简化像素驱动电路200的电路结构。同时，第四晶体管M4为低温多晶硅薄膜晶体管，其具有高电子迁移率，能够提高第二显示区AA2的电流承载能 力和响应速度。
继续参照图3或图5所示，数据写入模块40包括第六晶体管M6，第六晶体管M6的栅极连接于第一信号控制端S1，第六晶体管M6的第一极连接于数据信号端Vdata，第六晶体管M6的第二极连接于第二节点N2。
可选地，第六晶体管M6为低温多晶硅薄膜晶体管。可选地，第六晶体管M6为P型晶体管或者N型晶体管，当第六晶体管M6为P型晶体管时，其栅极在接收到低电平信号时导通，在接收到高电平信号时截止；当第六晶体管M6为N型晶体管时，其栅极在接收到高电平信号时导通，在接收到低电平信号时截止。图3和图5所示实施例仅以第六晶体管M6为P型晶体管为例进行说明，在本申请的一些其他实施例中，第六晶体管M6还可体现为N型晶体管，本申请对此不进行限定。
继续参照图2或图4所示，像素驱动电路200还包括电源电压写入模块50，电源电压写入模块50的控制端连接于开关信号控制端Emit，电源电压写入模块50的第一端连接于第一电源信号端PVDD，电源电压写入模块50的第二端连接于第二节点N2；电源电压写入模块50设置为在发光阶段向驱动晶体管M0写入第一电源信号端PVDD输出的第一电压信号。
本申请实施例中，电源电压写入模块50串联于第一电源信号端PVDD和第二节点N2之间，电源电压写入模块50的控制端连接开关信号控制端Emit。电源电压写入模块50根据开关信号控制端Emit的信号导通或截止。在电源电压写入模块50导通时，第一电源信号端PVDD的第一电压信号通过电源电压写入模块50传输至驱动晶体管M0的第二节点N2。本申请实施例中，将电源电压写入模块50的控制端连接开关信号控制端Emit，无需为电源电压写入模块50另外设置信号控制端，因而有利于简化像素驱动电路200的结构，简化显示面板100的整体结构。
继续参照图3或图5所示，电源电压写入模块50包括第七晶体管M7，第七晶体管M7的栅极连接于开关信号控制端Emit，第七晶体管M7的第一极连接于第一电源信号端PVDD，第七晶体管M7的第二极连接于第二节点N2。
可选地，第七晶体管M7为低温多晶硅薄膜晶体管，可选地，第七晶体管M7为P型晶体管或者N型晶体管，当第七晶体管M7为P型晶体管时，其栅极在接收到低电平信号时导通，在接收到高电平信号时截止；当第七晶体管M7为N型晶体管时，其栅极在接收到高电平信号时导通，在接收到低电平信号时截止。图3和图5所示实施例仅以第七晶体管M7为P型晶体管为例进行说明，在本申请的一些其他实施例中，第七晶体管M7还可体现为 N型晶体管，本申请对此不进行限定。以第七晶体管M7为P型晶体管为例，在像素驱动电路200的发光阶段，开关信号控制端Emit输出低电平信号，第七晶体管M7的栅极接收低电平信号，第七晶体管M7导通，第一电压信号通过第七晶体管M7传输至第二节点N2，向驱动晶体管M0提供第一电压信号，生成用以驱动发光元件D1发光的驱动电流。
参照图2至图5任一附图所示，像素驱动电路200还包括存储电容Cst，存储电容Cst的第一极连接于第一电源信号端PVDD，存储电容Cst的第二极连接于第一节点N1；存储电容Cst设置为保持第一节点N1的电位。
存储电容Cst串联于第一电源信号端PVDD和第一节点N1之间，通过存储电容Cst的存储功能对由于漏电流引起的第一节点N1电压变化进行补偿，保障第一节点N1的电压，提高显示面板100的显示品质。
图6为申请实施例所提供的另一种像素驱动电路200的结构示意图，图7为本申请实施例所提供的另一种像素驱动电路200的框架结构示意图，本实施例示出了在像素驱动电路200中引入第二复位模块60的方案，图6和图7的区别在于第一复位模块30的构成不同。
请参考图6和图7，在本申请的一种可选实施例中，像素驱动电路200还包括第二复位模块60，第二复位模块60的控制端连接于第二信号控制端S2，第二复位模块60的第一端连接于复位信号端Vref，第二复位模块60的第二端连接于发光元件D1的第一端；在初始化阶段，第二复位模块60设置为对第四节点N4进行复位。
第二复位模块60串联于复位信号端Vref和第四节点N4之间，第二复位模块60的控制端连接第二信号控制端S2。第二复位模块60根据第二信号控制端S2的信号导通或截止。当第二复位模块60导通时，对第四节点N4进行复位，从而实现对发光元件D1的阳极的复位。
图8为本申请实施例所提供的另一种像素驱动电路200的电路示意图；图9为本申请实施例所提供的另一种像素驱动电路200的电路示意图，图8为对图6结构的细化，图9为对图7结构的细化，图8和图9所示实施例均对像素驱动电路200的结构进行了细化，区别在于第一复位模块30的构成不同。
请参考图8和图9，在本申请的一种可选实施例中，第二复位模块60包括第五晶体管M5，第五晶体管M5的栅极连接于第二信号控制端S2，第五晶体管M5的第一极连接于复位信号端Vref，第五晶体管M5的第二极连接于发光元件D1的第一端；第五晶体管M5为低温多晶氧化物薄膜晶体管。
第五晶体管M5为低温多晶氧化物薄膜晶体管，低温多晶氧化物薄膜晶体管在栅极接收到高电平信号时导通，在栅极接收到低电平信号时截止。第五晶体管M5的栅极为第二复位模块60的控制端，第五晶体管M5的栅极连接第二信号控制端S2。在像素驱动电路200的初始化阶段，第二信号控制端S2输出高电平信号，第五晶体管M5的栅极接收到高电平信号，第五晶体管M5导通，复位信号端Vref发出的复位信号经由第五晶体管M5传输至第四节点N4，实现对第四节点N4的复位。
本申请实施例采用第五晶体管M5构成本申请中的第二复位模块60的方式，结构简单，能够对第四节点N4进行复位，清除上一次发光过程中第四节点N4残留的电压，进而使发光元件D1按照预设的亮度发光。在提升发光元件D1发光亮度的准确性的同时，还有利于简化像素驱动电路200的电路结构。同时，第五晶体管M5为低温多晶氧化物薄膜晶体管，其具有透过率高和功耗低等特性，能够提高第二显示区AA2的透过率。在感光阶段，使更多的光线穿过第二显示区AA2到达感光元件G，从而有利于提升显示面板100的感光性能。
本申请实施例还提供一种显示面板的驱动方法，用于驱动上述任一种实施例所提供的显示面板100。参照图10和图11所示，其中，图10为本申请实施例所提供的一种像素驱动电路的时序图，图11本为申请实施例所提供的一种显示面板的驱动方法的流程图。
请结合图1至图9，显示面板100包括：补偿模块20、第一复位模块30、数据写入模块40、驱动晶体管M0、电源电压写入模块50、发光控制模块10和发光元件D1；
驱动方法包括：
初始化阶段T1、数据写入阶段T2和发光阶段T3；
在初始化阶段T1，补偿模块20和第一复位模块30导通，第一复位模块30和补偿模块20将复位信号端Vref的复位信号传输至第一节点N1，对第一节点N1进行复位；
在数据写入阶段T2，数据写入模块40和补偿模块20导通，数据信号端Vdata的数据信号通过数据写入模块40传输至第二节点N2，第二节点N2的信号通过驱动晶体管M0传输至第三节点N3，第三节点N3的信号通过补偿模块20传输至第一节点N1；
在发光阶段T3，电源电压写入模块50和发光控制模块10导通，电源电压写入模块50将第一电源信号端PVDD的第一电压信号传输至第二节点 N2，驱动晶体管M0形成电流传输至发光元件D1。
请结合图9和图10，以第一晶体管M1、第二晶体管M2、第三晶体管M3和第五晶体管M5为低温多晶氧化物薄膜晶体管，其余晶体管为P型晶体管为例进行对像素驱动电路200的工作时序进行说明。
在初始化阶段T1，第一信号控制端S1输出高电平信号，第二信号控制端S2输出高电平信号，开关信号控制端Emit输出高电平信号。补偿模块20和第一复位模块30导通，第一复位模块30和补偿模块20将复位信号端Vref的复位信号传输至第一节点N1，对第一节点N1进行复位。初始化阶段T1能够对第一节点N1进行复位，清除上一次发光中第一节点N1残留的电压，进而使发光元件D1按照预设的亮度发光，提升发光元件D1发光亮度的准确性。
在数据写入阶段T2，第一信号控制端S1输出低电平信号，第二信号控制端S2输出高电平信号，开关信号控制端Emit输出高电平信号。数据写入模块40，驱动晶体管M0和补偿模块20导通，数据信号端Vdata的数据信号通过数据写入模块40传输至第二节点N2，第二节点N2的信号通过驱动晶体管M0传输至第三节点N3，第三节点N3的信号通过补偿模块20传输至第一节点N1。
在发光阶段T3，第一信号控制端S1输出高电平信号，第二信号控制端S2输出低电平信号，开关信号控制端Emit输出低电平信号。电源电压写入模块50和发光控制模块10导通，电源电压写入模块50将第一电源信号端PVDD的第一电压信号传输至第二节点N2，驱动晶体管M0形成电流传输至发光元件D1。在发光阶段T3，驱动晶体管M0根据数据写入阶段T2写入的数据信号以及第一电源信号端PVDD的信号生成用以驱动发光元件D1发光的驱动电流。
可选地，像素驱动电路200中的第一复位模块30和补偿模块20均采用低温多晶氧化物薄膜晶体管，以有效提升第二显示区AA2的透过率。
在本申请的一种可选实施例中，显示面板100还包括：第二复位模块60；
驱动方法还包括：
在初始化阶段T1，第二复位模块60导通，第二复位模块60将复位信号传输至第四节点N4，对第四节点N4进行复位。
继续参考图9，本实施例以第二复位模块60中的晶体管为低温多晶氧化物薄膜晶体管为例进行说明，低温多晶氧化物薄膜晶体管在其栅极接收到高电平信号时导通，接收到低电平信号时截止。
在初始化阶段T1，第一信号控制端S1输出高电平信号，第二信号控制端S2输出高电平信号，开关信号控制端Emit输出高电平信号。第二复位模块60导通，第二复位模块60将复位信号传输至第四节点N4，对第四节点N4进行复位。在初始化阶段T1能够清除上一次发光中第四节点N4残留的电压，进而使发光元件D1按照预设的亮度发光。
本申请还提供一种显示装置，请参考图12，图12所示为本申请实施例所提供的一种显示装置的结构示意图，本实施例所提供的显示装置500包括本申请上述任一实施例所提供的显示面板100。
本申请实施例提供的显示装置500，可以是电脑、手机、或平板等其他具有显示功能的显示装置，本申请对此不作限制。本申请实施例提供的显示装置，具有本申请实施例提供的显示面板的效果，可以参考上述多个实施例对于显示面板的说明，本实施例在此不再赘述。
在本申请的一种可选实施方式中，请继续参考图12及图13，本申请实施例所提供的显示装置500还包括感光元件G，感光元件G位于显示面板100的第二显示区AA2。可选地，显示装置500中所包含的感光元件G为摄像头、红外感测器件和指纹识别器件等电子感光器件。在显示阶段，第二显示区AA2用以发挥显示功能；在感光阶段，第二显示区AA2中的感光元件G设置为感应光线。
本申请实施例所提供的显示面板100可以应用于显示装置，可体现为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、或导航仪等任何具有显示功能的产品或部件。
综上，本申请提供的显示面板及其驱动方法和显示装置，至少实现了如下效果：
本申请实施例在第一显示区AA1和第二显示区AA2均设置有多个呈阵列排布的子像素，每个子像素包括一个像素驱动电路200。可选地，第二显示区AA2设置为设置摄像头、红外感测器件、指纹识别器件等电子感光器件。第二显示区AA2的像素驱动电路200中包括的多个晶体管至少部分为低温多晶氧化物薄膜晶体管。由于低温多晶氧化物薄膜晶体管具有较高的透过率，因此，当利用第二显示区AA2进行光线识别时，例如在进行拍照时，第二显示区AA2能够变成透明状的玻璃状，使光线透过第二显示区AA2到达第二显示区AA2下方设置的感光元件G，从而完成成像功能。当第二显示区AA2用于显示时，第二显示区AA2能够同第一显示区AA1共同进行显示，有利于提高屏占比。将第二显示区AA2中的至少部分晶体管换为低温多晶氧化物薄膜晶体管的方式，有效提升了第二显示区AA2的透过率，因而有利于提升 第二显示区AA2的感光性能。

Claims (16)

  1. 一种显示面板，包括第一显示区和第二显示区，所述第一显示区和所述第二显示区均包括多个呈阵列排列的子像素，每个子像素包括像素驱动电路，其中，所述第二显示区与感光元件对应；
    位于所述第二显示区的每个像素驱动电路包括至少一个晶体管，所述晶体管中的至少一个为低温多晶氧化物薄膜晶体管。
  2. 根据权利要求1所述的显示面板，其中，所述像素驱动电路包括：
    第一电源信号端和第二电源信号端，所述第一电源信号端设置为接收第一电压信号，所述第二电源信号端设置为接收第二电压信号；
    驱动晶体管，所述驱动晶体管的栅极连接到第一节点，所述驱动晶体管的第一极连接第二节点，所述驱动晶体管的第二极连接第三节点；所述驱动晶体管设置为在发光阶段提供驱动电流；
    发光控制模块，所述发光控制模块的控制端连接于开关信号控制端，所述发光控制模块的第一端连接于所述第三节点，所述发光控制模块的第二端连接于第四节点；
    发光元件，所述发光元件的第一端通过所述第四节点连接于所述发光控制模块的第二端，所述发光元件的第二端连接于所述第二电源信号端；所述发光元件设置为在所述发光控制模块的控制下响应驱动电流并发光；
    补偿模块，所述补偿模块的控制端连接于所述开关信号控制端，所述补偿模块的第一端连接于所述第一节点，所述补偿模块的第二端连接于所述第三节点；所述补偿模块设置为在补偿阶段检测和自补偿所述驱动晶体管的阈值电压的偏差；
    第一复位模块，所述第一复位模块的控制端连接于所述开关信号控制端，所述第一复位模块的第一端连接于所述第三节点，所述第一复位模块的第二端连接于复位信号端；所述第一复位模块和所述补偿模块共同设置为在初始化阶段对所述第一节点进行复位。
  3. 根据权利要求2所述的显示面板，其中，所述补偿模块包括第一晶体管，所述第一晶体管的栅极连接于所述开关信号控制端，所述第一晶体管的第一极连接于所述第一节点，所述第一晶体管的第二极连接于所述第三节点；其中，所述第一晶体管为低温多晶氧化物薄膜晶体管。
  4. 根据权利要求2所述的显示面板，其中，所述第一复位模块包括第二晶体管，所述第二晶体管的栅极连接于所述开关信号控制端，所述第二晶体管的第一极连接于所述第三节点，所述第二晶体管的第二极连接于所述复位 信号端；其中，所述第二晶体管为低温多晶氧化物薄膜晶体管。
  5. 根据权利要求4所述的显示面板，其中，所述第一复位模块还包括第三晶体管，所述第三晶体管的栅极连接于第一信号控制端，所述第三晶体管的第一极连接于所述第三节点，所述第三晶体管的第二极连接于所述第二晶体管的第一极；其中，所述第三晶体管为低温多晶氧化物薄膜晶体管。
  6. 根据权利要求2所述的显示面板，其中，所述发光控制模块包括第四晶体管，所述第四晶体管的栅极连接于所述开关信号控制端，所述第四晶体管的第一极连接于所述第三节点，所述第四晶体管的第二极连接于所述第四节点。
  7. 根据权利要求2所述的显示面板，其中，所述像素驱动电路还包括第二复位模块，所述第二复位模块的控制端连接于第二信号控制端，所述第二复位模块的第一端连接于所述复位信号端，所述第二复位模块的第二端连接于所述发光元件的第一端；所述第二复位模块设置为在所述初始化阶段对所述第四节点进行复位。
  8. 根据权利要求7所述的显示面板，其中，所述第二复位模块包括第五晶体管，所述第五晶体管的栅极连接于所述第二信号控制端，所述第五晶体管的第一极连接于所述复位信号端，所述第五晶体管的第二极连接于所述发光元件的第一端；其中，所述第五晶体管为低温多晶氧化物薄膜晶体管。
  9. 根据权利要求5所述的显示面板，其中，所述像素驱动电路还包括数据写入模块，所述数据写入模块的控制端连接于所述第一信号控制端，所述数据写入模块的第一端连接于数据信号端，所述数据写入模块的第二端连接于所述第二节点；其中，所述数据写入模块设置为向所述驱动晶体管提供数据信号。
  10. 根据权利要求9所述的显示面板，其中，所述数据写入模块包括第六晶体管，所述第六晶体管的栅极连接于所述第一信号控制端，所述第六晶体管的第一极连接于所述数据信号端，所述第六晶体管的第二极连接于所述第二节点。
  11. 根据权利要求2所述的显示面板，其中，所述像素驱动电路还包括电源电压写入模块，所述电源电压写入模块的控制端连接于所述开关信号控制端，所述电源电压写入模块的第一端连接于所述第一电源信号端，所述电源电压写入模块的第二端连接于所述第二节点；其中，所述电源电压写入模块设置为在所述发光阶段向所述驱动晶体管写入所述第一电源信号端输出的第一电压信号。
  12. 根据权利要求11所述的显示面板，其中，所述电源电压写入模块包括第七晶体管，所述第七晶体管的栅极连接于所述开关信号控制端，所述第七晶体管的第一极连接于所述第一电源信号端，所述第七晶体管的第二极连接于所述第二节点。
  13. 根据权利要求2所述的显示面板，所述像素驱动电路还包括存储电容，所述存储电容的第一极连接于所述第一电源信号端，所述存储电容的第二极连接于所述第一节点；其中，所述存储电容设置为保持所述第一节点的电位。
  14. 一种显示面板的驱动方法，用于驱动权利要求2-13中任一项所述的显示面板，
    所述方法包括：
    在所述初始化阶段，所述补偿模块和所述第一复位模块导通，所述第一复位模块和所述补偿模块将复位信号端的复位信号传输至第一节点，对所述第一节点进行复位；
    在数据写入阶段，所述像素驱动电路包括的数据写入模块和所述补偿模块导通，所述数据写入模块的第一端所连接的数据信号端的数据信号通过所述数据写入模块的第二端传输至第二节点，所述第二节点的信号通过所述驱动晶体管传输至第三节点，所述第三节点的信号通过所述补偿模块传输至所述第一节点；
    在所述发光阶段，所述像素驱动电路包括的电源电压写入模块和所述发光控制模块导通，所述电源电压写入模块将所述第一电源信号端的第一电压信号传输至所述第二节点，驱动所述驱动晶体管形成电流传输至所述发光元件。
  15. 根据权利要求14所述的方法，其中，所述像素驱动电路还包括：第二复位模块；
    所述方法还包括：
    在所述初始化阶段，所述第二复位模块导通，所述第二复位模块将所述复位信号传输至所述第四节点，对所述第四节点进行复位。
  16. 一种显示装置，包括权利要求1-13中任一项所述的显示面板。
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