WO2024051225A1 - 一种扇出型系统级封装结构及制作方法 - Google Patents

一种扇出型系统级封装结构及制作方法 Download PDF

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Publication number
WO2024051225A1
WO2024051225A1 PCT/CN2023/097799 CN2023097799W WO2024051225A1 WO 2024051225 A1 WO2024051225 A1 WO 2024051225A1 CN 2023097799 W CN2023097799 W CN 2023097799W WO 2024051225 A1 WO2024051225 A1 WO 2024051225A1
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layer
rewiring layer
rewiring
packaging
functional chip
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PCT/CN2023/097799
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English (en)
French (fr)
Inventor
陈彦亨
林正忠
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盛合晶微半导体(江阴)有限公司
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Publication of WO2024051225A1 publication Critical patent/WO2024051225A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector

Definitions

  • the invention belongs to the field of semiconductor packaging and relates to a fan-out system-level packaging structure and a manufacturing method.
  • system-level packaging technology has become the packaging form of more and more chips.
  • System-level packaging integrates multiple functional chips and components into one package to achieve a basically complete function and has a development cycle. Short, more functions, lower power consumption, better performance, smaller size, light weight and other advantages.
  • existing system-level packaging still has defects such as poor integration, poor compatibility, and low integration, and cannot meet the needs of ultra-high-density packaging.
  • the purpose of the present invention is to provide a fan-out system-level packaging structure and a manufacturing method, which integrates multiple functional chips and components into one packaging wafer to solve current problems.
  • System-level packaging in certain technologies has problems such as poor integration, poor compatibility, and low integration.
  • the present invention provides a method for manufacturing a fan-out system-level packaging structure, which includes the following steps:
  • first rewiring layer Forming a first rewiring layer on the separation layer, the first rewiring layer including a stacked first dielectric layer and a first metal wiring layer;
  • the second rewiring layer including a stacked second dielectric layer and a second metal wiring layer, the second metal wiring layer is electrically connected to the metal connection pillar;
  • At least one first functional chip and at least one component Provide at least one first functional chip and at least one component, and electrically connect the first functional chip and the component to a side of the second rewiring layer away from the packaging layer;
  • a cooling layer is formed on the second rewiring layer, a cavity is formed between the cooling layer and the second rewiring layer, and the first functional chip and the component are located in the cavity;
  • a packaging wafer is provided, and the conductive bumps are connected to the packaging wafer.
  • the step further includes the step of forming a first opening on a side of the first rewiring layer away from the separation layer, the first opening exposing the first metal wiring layer,
  • the metal connection pillar extends into the first opening and is connected to the first metal wiring layer.
  • the method before forming the conductive bumps, further includes the step of forming a second opening on a side of the first rewiring layer away from the packaging layer, the second opening exposing the first metal wiring layer, The conductive bump extends into the second opening and is connected to the first metal wiring layer.
  • the number of the first functional chips is multiple, and the plurality of first functional chips are arranged in an array in the horizontal direction; the number of the components is multiple, and the multiple components are arranged in an array.
  • the devices are arranged in an array in the horizontal direction.
  • the first rewiring layer includes at least one first dielectric layer and at least one first metal wiring layer stacked in a vertical direction;
  • the second rewiring layer includes a stacked layer in a vertical direction. at least one second dielectric layer and at least one second metal wiring layer.
  • a connector is provided to connect the connector to the conductive bump, and the second functional chip is separated from the connector by a preset distance, wherein the conductive bump is connected to the package through the connector Wafer connection.
  • the invention also provides a fan-out system-level packaging structure, which includes:
  • the first rewiring layer including a stacked first dielectric layer and a first metal wiring layer;
  • a second rewiring layer is located above the first rewiring layer and is separated from the first rewiring layer by a preset distance.
  • the second rewiring layer includes a stacked second dielectric layer and a second metal wiring layer;
  • An encapsulation layer located between the first rewiring layer and the second rewiring layer;
  • Metal connection pillars penetrate the packaging layer in the vertical direction.
  • the bottom end of the metal connection pillars is electrically connected to the first metal wiring layer, and the top end of the metal connection pillars is electrically connected to the second metal wiring layer. ;
  • a conductive bump located under the first rewiring layer, the conductive bump being electrically connected to the first rewiring layer;
  • At least one first functional chip the first functional chip is electrically connected to the second rewiring layer;
  • the component is electrically connected to the second rewiring layer, and the component is separated from the first functional chip by a preset distance;
  • a cooling layer located on the second rewiring layer, a cavity is formed between the cooling layer and the second rewiring layer, and the first functional chip and the components are located in the cavity;
  • a packaging wafer is located on a side of the first rewiring layer having the conductive bumps, and the packaging wafer is connected to the conductive bumps.
  • the number of the first functional chips is multiple, and the plurality of first functional chips are arranged in an array in the horizontal direction; the number of the components is multiple, and the multiple components are arranged in an array.
  • the devices are arranged in an array in the horizontal direction.
  • the first rewiring layer includes at least one of the first dielectric layers stacked in a vertical direction and At least one first metal wiring layer; the second rewiring layer includes at least one second dielectric layer and at least one second metal wiring layer stacked in a vertical direction.
  • a connector and at least a second functional chip are further included between the packaging wafer and the conductive bump, the connector is connected to the conductive bump, and the second functional chip is connected to the conductive bump.
  • the conductive bumps are connected, and the second functional chip is separated from the connector by a preset distance, wherein the package wafer is connected to the conductive bumps through the connector.
  • the upper and lower layers are interconnected through metal connecting pillars, allowing for ultra-high-level system-level packaging, and connecting the first function on the second rewiring layer.
  • Chips and components are packaged with high-density connections.
  • Functional chips such as processors and memories, as well as optoelectronic components, optical components and MEMS components, can be integrated into one package in a package wafer (such as 8-inch or 12-inch). Achieving a basically complete function not only improves the integration of the process structure, but also helps reduce the package size.
  • the second functional chip can be connected to the conductive bumps to achieve high-density sealed connections while improving flexibility and compatibility and increasing package performance.
  • FIG. 1 shows a process flow chart of the manufacturing method of the fan-out system-in-package structure of the present invention.
  • FIG. 2 shows a schematic diagram of providing a support carrier and forming a separation layer on the support carrier in the manufacturing method of the fan-out system-in-package structure of the present invention.
  • FIG. 3 shows a schematic diagram of forming a first rewiring layer on the separation layer and forming a first opening in the manufacturing method of the fan-out system-in-package structure of the present invention.
  • FIG. 4 shows a schematic diagram of forming metal connection pillars on the first rewiring layer in the manufacturing method of the fan-out system-in-package structure of the present invention.
  • FIG. 5 is a schematic diagram of forming a packaging layer on the first rewiring layer in the manufacturing method of the fan-out system-in-package structure of the present invention.
  • FIG. 6 shows a schematic diagram of thinning the packaging layer in the manufacturing method of the fan-out system-in-package structure of the present invention.
  • FIG. 7 shows a schematic diagram of forming a second rewiring layer on the packaging layer in the manufacturing method of the fan-out system-in-package structure of the present invention.
  • FIG. 8 shows a schematic diagram of removing the support carrier based on the separation layer to reveal the first rewiring layer in the manufacturing method of the fan-out system-in-package structure of the present invention.
  • FIG. 9 is a schematic diagram of forming a second opening on the side of the first rewiring layer away from the packaging layer in the manufacturing method of the fan-out system-in-package structure of the present invention.
  • FIG. 10 shows a schematic diagram of forming conductive bumps on the side of the first rewiring layer away from the packaging layer in the manufacturing method of the fan-out system-in-package structure of the present invention.
  • FIG. 11 shows a method for manufacturing a fan-out system-in-package structure of the present invention that provides a first functional chip and components, and connects the first functional chip and the components to the second rewiring layer respectively.
  • FIG. 12 is a schematic diagram of forming a first filling layer at the connection gap between the first functional chip and the second rewiring layer in the manufacturing method of the fan-out system-in-package structure of the present invention.
  • FIG. 13 is a schematic diagram of forming a cooling layer on the second rewiring layer in the manufacturing method of the fan-out system-in-package structure of the present invention.
  • FIG. 14 shows a plan layout diagram of the first functional chip and the components in the fan-out system-in-package structure of the present invention.
  • FIG. 15 shows a schematic diagram of providing a second functional chip and a connector in the manufacturing method of the fan-out system-in-package structure of the present invention, and connecting the second functional chip and the connector to the conductive bumps respectively.
  • This embodiment provides a method for manufacturing a fan-out system-level packaging structure. Please refer to Figure 1, which shows a process flow chart of the method, which includes the following steps:
  • S2 Form a first rewiring layer on the separation layer, where the first rewiring layer includes a stacked first dielectric layer and a first metal wiring layer;
  • S3 Form a metal connection pillar on the first rewiring layer, and the metal connection pillar is electrically connected to the first metal wiring layer;
  • S4 Form an encapsulation layer on the first rewiring layer, the encapsulation layer covers the first rewiring layer and the metal connection pillar, and thin the encapsulation layer to expose the metal connection pillar;
  • S5 Form a second rewiring layer on the packaging layer.
  • the second rewiring layer includes a stacked second dielectric layer and a second metal wiring layer.
  • the second metal wiring layer is electrically connected to the metal connection pillar. connect;
  • S7 Form a conductive bump on the side of the first rewiring layer away from the packaging layer, and the conductive bump is electrically connected to the first rewiring layer;
  • S8 Provide at least one first functional chip and at least one component, and electrically connect the first functional chip and the component to a side of the second rewiring layer away from the packaging layer;
  • S9 Form a cooling layer on the second rewiring layer.
  • a cavity is formed between the cooling layer and the second rewiring layer.
  • the first functional chip and the component are located in the cavity. middle;
  • S10 Provide a packaging wafer, and connect the conductive bumps to the packaging wafer.
  • step S1 provide a support carrier 10 and form a separation layer 20 on the support carrier 10.
  • the support carrier 10 includes but is not limited to any one of a glass carrier, a metal carrier, a semiconductor carrier, a polymer carrier, and a ceramic carrier, and is used to prevent the layer structure from cracking, warping, breaking, etc. during the packaging process.
  • the shape of the support carrier 10 may be wafer-shaped, panel-shaped, or any other desired shape.
  • the support carrier 10 is made of a glass carrier, which has low cost, is easy to form the separation layer 20 on its surface, and can reduce the difficulty of the subsequent peeling process.
  • the material of the separation layer 20 includes tape or polymer, which is coated on the surface of the support carrier 10 through a spin coating process, and then formed using ultraviolet light curing or thermal curing.
  • step S2 is then performed: forming a first rewiring layer 30 on the separation layer 20 .
  • the first rewiring layer 30 includes a stacked first dielectric layer 31 and a first metal wiring layer 32 .
  • the step of forming the first rewiring layer 30 includes:
  • the material of the first dielectric layer 31 includes but is not limited to epoxy resin and silica gel. , PI, PBO, BCB, silicon oxide, phosphosilicate glass, fluorine-containing glass, one or more combinations;
  • the material of the first metal wiring layer 32 includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.
  • the above steps can be repeated as needed to form the first rewiring layer 30 with a multi-layer stacked structure to achieve different wiring requirements.
  • the multi-layer first metal wiring layers 32 are electrically connected through conductive plugs. connect.
  • a first opening 301 is formed on a side of the first rewiring layer 30 away from the separation layer 20 to expose the first rewiring layer 32 .
  • the method of forming the first opening 301 includes photolithography. Method, laser drilling method or other suitable methods, the first opening 301 gradually increases from bottom to top and is funnel-shaped.
  • step S3 is then performed: forming metal connection pillars 40 on the first rewiring layer 30 , and the metal connection pillars 40 are electrically connected to the first metal wiring layer 32 .
  • the metal connection post 40 extends into the first opening 301 and is connected to the first metal wiring layer 32 .
  • the method of forming the metal connection post 40 includes electroplating, chemical plating, wire bonding or other suitable methods.
  • the material of the metal connection post 40 includes one of copper, aluminum, nickel, gold, silver, and titanium. Or a combination of two or more. In this embodiment, electroplated copper pillars are preferred.
  • the metal connection pillars 40 are directly formed on the surface of the first rewiring layer 30 without any obstruction, so there is no need to worry about adverse effects on other structures during the manufacturing process, and the connection with the first rewiring layer 30 can be realized.
  • the process of aligning the metal wiring layer 32 is greatly simplified and can achieve fine line width and line spacing layout, which is conducive to high-level density connection.
  • step S4 is performed: forming an encapsulation layer 50 on the first rewiring layer 30 , covering the first rewiring layer 30 and the metal connection pillar 40 , and thinning the encapsulation layer 50 to expose the metal connecting posts 40 .
  • the encapsulation layer 50 is formed on the first rewiring layer 30 .
  • the method of forming the encapsulation layer 50 includes but is not limited to compression molding, transfer molding, liquid sealing molding, Either vacuum lamination or spin coating, the material of the encapsulation layer 50 includes curable materials, such as polymer-based materials, resin-based materials, polyamide and any combination thereof.
  • the encapsulation layer 50 is thinned to expose the metal connecting pillar 40 .
  • the method of thinning the encapsulation layer 50 includes grinding, polishing or other suitable methods. After the thinning, the The upper surface of the encapsulation layer 50 is flush with the upper surface of the metal connection post 40 .
  • step S5 is then performed: forming a second rewiring layer 60 on the packaging layer 50 .
  • the second rewiring layer 60 includes a stacked second dielectric layer 61 and a second metal wiring layer 62 .
  • the second metal wiring layer 62 is electrically connected to the metal connection pillar 40 .
  • the method of forming the second rewiring layer 60 is the same as the method of forming the first rewiring layer 30 and will not be described in detail here.
  • step S6 is then performed: peeling off the support carrier 10 based on the separation layer 20 to expose the side of the first rewiring layer 30 away from the encapsulation layer 50 .
  • a corresponding method is used according to the type of the separation layer 20 to reduce the viscosity of the separation layer 20, and then the support carrier 10 and the separation layer 20 are peeled off.
  • a laser can be used to irradiate the photothermal conversion layer to separate the photothermal conversion layer from the first rewiring layer 30 and the support carrier 10 .
  • a second opening 302 is formed on a side of the first rewiring layer 30 away from the encapsulation layer 50 to expose the first rewiring layer 32 ;
  • the method includes photolithography, laser drilling or other suitable methods.
  • the second opening 302 gradually decreases from bottom to top, taking on the shape of an inverted funnel.
  • step S7 is then performed: forming a conductive bump 70 on a side of the first rewiring layer 30 away from the packaging layer 50 , and the conductive bump 70 is electrically connected to the first rewiring layer 32 .
  • the conductive bumps 70 extend into the second opening 302 and are connected to the first metal wiring layer 32 .
  • the conductive bumps 70 may be composed of metal pillars, solder joints, or just solder balls.
  • step S8 is then performed: providing at least one first functional chip 80 and at least one component 90 , and placing the first functional chip 80 and the component 90 away from the second rewiring layer 60 respectively.
  • One side of the packaging layer 50 is electrically connected.
  • first functional chips 80 there are multiple first functional chips 80 , and their types include processors, memories, etc.; there are multiple components 90 , and their types include optoelectronic components, optical components, and MEMS. components etc. It should be noted that this embodiment only exemplifies several types of the first functional chip 80 and the component 90 and is not limited to this embodiment. In actual production and manufacturing, the above-mentioned first functional chips 80 and the components 90 are selected according to the functional requirements of the package. The type and quantity of the first functional chip 80 and the components 90 .
  • the first functional chip 80 is electrically connected to the second rewiring layer 60 through chip pads (chip pins) 81, and the components 90 are connected through surface mount technology (SMT). on the second rewiring layer 60 .
  • SMT surface mount technology
  • a dispensing process or other suitable processes may be further used to form a first filling layer 100 at the connection gap between the first functional chip 80 and the second rewiring layer 60 .
  • the first filling layer 100 can provide protection for the connection between the first functional chip 80 and the second rewiring layer 60 to prevent This prevents corrosion or connection damage.
  • it can improve the bonding performance between the first functional chip 80 and the second rewiring layer 60 and improve the mechanical strength.
  • step S9 is then performed: forming a cooling layer 110 on the second rewiring layer 60, forming a cavity between the cooling layer 110 and the second rewiring layer 60, and the first function
  • the chip 80 and the component 90 are both located in the cavity.
  • the material of the cooling layer 110 includes one of silver, copper, gold, and aluminum, and may also be other suitable materials with high thermal conductivity.
  • a heat transfer medium layer 120 is formed between the surface of the first functional chip 80 and the cooling layer 110 .
  • the heat transfer medium layer 120 may be heat dissipation paste or other high thermal conductivity materials.
  • the heat transfer medium layer 120 can serve as a bonding agent between the first functional chip 80 and the cooling layer 110 .
  • the heat from the first functional chip 80 can pass through the heat transfer medium layer 120 More efficient heat conduction to the cooling layer 110 .
  • step S10 is performed: providing a packaging wafer, and connecting the conductive bumps 70 to the packaging wafer.
  • the packaging wafer includes an 8-inch or 12-inch packaging wafer.
  • the packaging wafer uses a 12-inch packaging wafer.
  • the conductive bumps 70 are in contact with the packaging wafer. Wafer connection is used for subsequent electrical extraction of the package, such as connection to an external power supply, etc.
  • FIG. 14 a plan layout diagram of the first functional chip 80 and the components 90 is shown, and a plurality of the first functional chips 80 and a plurality of the components 90 are arranged in an array.
  • multiple functional chips including processors, memories, etc., and multiple components including optoelectronic components, optical components, MEMS components, etc. can be integrated into one package in one package wafer, thereby achieving a basically complete function.
  • a second functional chip 130 and a connector 140 are provided, and the second functional chip 130 and the connector 140 are respectively connected to the conductive bumps 70 .
  • the second functional chip 120 includes but is not limited to a processor, a memory, a power management chip, a transmitter chip, a receiver chip, etc.
  • a second filling layer 150 is formed at the connection gap between the second functional chip 130 and the conductive bump 70 .
  • the second filling layer 150 can connect the second functional chip 130 and the conductive bump 70 .
  • the connection of the conductive bump 70 provides protection to prevent corrosion or connection damage.
  • it can improve the bonding performance between the second functional chip 150 and the conductive bump 70 and improve the mechanical strength.
  • the connector 140 includes a header connector, and the connector 140 is used to subsequently connect to the package wafer and thereby connect to an external power supply.
  • the upper and lower layers are interconnected through metal connecting pillars, which allows for ultra-high-level system-level packaging.
  • the first functional chip and the first functional chip are connected on the second rewiring layer.
  • Components are packaged with high-density connections.
  • Functional chips such as processors and memories, as well as optoelectronic components, optical components and MEMS components, can be integrated into one package to achieve a basic and complete function in a package wafer, which can improve the manufacturing process.
  • the structural integration reduces the package size; in addition, the conductive bumps can also be used to connect the second functional chip and the connector. While achieving high-density sealed connections, it has higher flexibility and wider compatibility, increasing Package performance.
  • This embodiment provides a fan-out system-level packaging structure.
  • the fan-out system-level packaging structure can be manufactured by the manufacturing method described in the first embodiment, but is not limited to the method described in the first embodiment. The production method described above.
  • the fan-out system-in-package structure includes a first rewiring layer 30, a second rewiring layer 60, a packaging layer 50, metal connecting pillars 40, conductive bumps 70, at least one first functional chip 80, and at least one component 90 , cooling layer 110 and packaging wafer, wherein the first rewiring layer 30 includes a stacked first dielectric layer 31 and a first metal wiring layer 32, and the second rewiring layer 60 is located on the first rewiring layer.
  • the second rewiring layer 60 includes a stacked second dielectric layer 61 and a second metal wiring layer 62, and the packaging layer 50 is located on the Between the first rewiring layer 30 and the second rewiring layer 60, the metal connection post 40 penetrates the packaging layer 50 in the vertical direction, and the bottom end of the metal connection post 40 is in contact with the first metal
  • the wiring layer 32 is electrically connected, the top of the metal connection post 40 is electrically connected to the second metal wiring layer 62 , and the conductive bump 70 is located below the first rewiring layer 30 and connected to the first rewiring layer 30 .
  • the layer 30 is electrically connected, the first functional chip 80 is electrically connected to the second rewiring layer 60, the component 90 is electrically connected to the second rewiring layer 60, and the component 90 is electrically connected to the second rewiring layer 60.
  • a functional chip 80 is spaced at a preset distance.
  • the cooling layer 110 is located on the second rewiring layer 60.
  • a cavity is formed between the cooling layer 110 and the second rewiring layer 60.
  • the first function chip 80 is spaced at a preset distance.
  • the chip 80 and the component 90 are both located in the cavity.
  • the packaging wafer is located on the side of the first rewiring layer 60 with the conductive bump 70 .
  • the packaging wafer is connected to the conductive bump 70 . Bump 70 connects.
  • the first rewiring layer 30 includes at least one first dielectric layer 31 and at least one first metal wiring layer 32 stacked in a vertical direction
  • the second rewiring layer 60 includes at least one first rewiring layer 31 stacked in a vertical direction.
  • At least one second dielectric layer 61 and at least one second metal wiring layer 62 are stacked in the direction.
  • the encapsulation layer 50 includes, but is not limited to, a polymer-based material layer, a resin-based material layer, a polyamide layer, an epoxy resin layer, and any combination thereof.
  • the metal connection pillars 40 include but are not limited to copper pillars.
  • the conductive bumps 70 may be composed of metal pillars, solder joints, or just solder balls.
  • first functional chips 80 there are multiple first functional chips 80 , and their types include processors, memories, etc.; there are multiple components 90 , and their types include optoelectronic components, optical components, and MEMS. components etc.
  • this embodiment only exemplifies several types of the first functional chip 80 and the component 90 and is not limited to this embodiment. In practical applications, the first functional chip 80 and the component 90 are selected according to the functional requirements of the package. The type and quantity of a functional chip 80 and the components 90 .
  • the first functional chip 80 includes a chip pad 81 through which the first functional chip 80 is electrically connected to the second metal wiring layer 62 .
  • a first filling layer 100 is provided at the connection gap between the first functional chip 80 and the second rewiring layer 60.
  • the first filling layer 100 can The connection between 80 and the second rewiring layer 60 provides protection to prevent corrosion or connection damage. On the other hand, it can improve the bonding performance of the first functional chip 80 and the second rewiring layer 60 and improve mechanical performance. strength.
  • a heat transfer medium layer 120 is provided between the first functional chip 80 and the cooling layer 110 .
  • the heat transfer medium layer 120 may be thermal paste or other high thermal conductivity materials.
  • the heat transfer medium The layer 120 can serve as a bonding agent between the first functional chip 80 and the cooling layer 110 .
  • the heat from the first functional chip 80 can be more efficiently passed through the heat transfer medium layer 120 Heat is conducted to the cooling layer 110 .
  • the packaging wafer includes an 8-inch or 12-inch packaging wafer.
  • the packaging wafer uses a 12-inch packaging wafer.
  • the conductive bumps 70 are in contact with the packaging wafer. Wafer connection is used for subsequent electrical extraction of the package, such as connection to an external power supply, etc.
  • FIG. 14 a plan layout diagram of the first functional chip 80 and the components 90 is shown, and a plurality of the first functional chips 80 and a plurality of the components 90 are arranged in an array.
  • multiple functional chips including processors, memories, etc., and multiple components including optoelectronic components, optical components, MEMS components, etc. can be integrated into one package in one package wafer, thereby achieving a basically complete function.
  • a second functional chip 130 and a connector 140 are also included, and the second functional chip 130 and the connector 140 are respectively connected to the conductive bumps 70 .
  • the second functional chip 130 includes but is not limited to a processor, a memory, a power management chip, a transmitter chip, a receiver chip, etc.
  • a second filling layer 150 is provided between the second functional chip 130 and the conductive bumps 70 .
  • the second filling layer 150 can be used to seal the second functional chip 130 and the conductive bumps 70 .
  • the connection of the block 70 provides protection to prevent corrosion or connection damage. On the other hand, it can improve the bonding performance between the second functional chip 150 and the conductive bump 70 and improve the mechanical strength.
  • the connector 140 includes a header connector, and the connector 140 is used to subsequently connect to the package wafer and thereby connect to an external power supply.
  • the upper and lower layers are interconnected through metal connecting pillars, so that ultra-high-level system-level packaging can be performed, and the second rewiring layer is connected to the second layer.
  • High-density connection packaging of functional chips and components can integrate functional chips such as processors and memories with optoelectronic components, optical components and MEMS components in one packaging wafer (such as 8-inch or 12-inch)
  • Implementing a basically complete function within the package can improve the integration of the process structure and reduce the package size; in addition, it can also connect the second functional chip and the connector on the conductive bumps, achieving high-density sealed connections while having higher Flexibility and broader compatibility, increasing package performance. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

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Abstract

本公开提供一种扇出型系统级封装结构及制作方法，该方法包括：提供支撑载体、形成第一重新布线层、金属连接柱、第二重新布线层，形成导电凸块与第一重新布线层电连接，提供第一功能芯片和元器件分别与第二重新布线层电连接，提供一封装晶圆，将导电凸块与封装晶圆连接。本发明通过金属连接柱实现上下层互连，在第二重新布线层上连接第一功能芯片及元器件做高密度连接，在一片封装晶圆中将处理器、记忆体等功能芯片和光电元器件、光学元件及MEMS元件等集成在一个封装体内实现一个基本完整的功能，能够提高制程结构整合性；另外，还可在导电凸块上连接第二功能芯片与连接器，在实现高密度密封连接的同时，提高灵活性与相容性，增加封装体性能。

Description

一种扇出型系统级封装结构及制作方法 技术领域
本发明属于半导体封装领域，涉及一种扇出型系统级封装结构及制作方法。
背景技术
随着科技的进步，电子终端产品的小型化和多功能化成为产业发展的大趋势，如何将多个不同种类的高密度芯片集成封装在一起构成一个功能强大且体积功耗又比较小的系统或者子系统，成为半导体芯片先进封装领域的一大挑战。
人们对更高功能、更好性能、更高能源效率、更低制造成本和更小尺寸的不断需求，一些先进的封装技术如芯片级封装(CSP)、晶圆级封装(WLP)、系统级封装(SIP)等应运而生。系统级封装技术作为新兴异质集成技术，成为越来越多芯片的封装形式，系统级封装是将多种功能芯片和元器件集成在一个封装内，从而实现一个基本完整的功能，有开发周期短，功能更多，功耗更低，性能更优良，体积更小，质量轻等优点。然而，随着对封装组件及功能越来越高的要求，现有的系统级封装还存在整合性差、相容性差、集成度小等缺陷，无法满足超高密度封装需求。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种扇出型系统级封装结构及制作方法，于一片封装晶圆中将多种功能芯片和元器件集成封装，用于解决现有技术中的系统级封装存在整合性差、相容性差、集成度小的问题。
为实现上述目的，本发明提供一种扇出型系统级封装结构的制作方法，包括以下步骤：
提供一支撑载体，于所述支撑载体上形成分离层；
于所述分离层上形成第一重新布线层，所述第一重新布线层包括层叠的第一介质层和第一金属布线层；
于所述第一重新布线层上形成金属连接柱，所述金属连接柱与所述第一金属布线层电连接；
于所述第一重新布线层上形成封装层，所述封装层覆盖所述第一重新布线层及所述金属连接柱，并减薄所述封装层以显露所述金属连接柱；
于所述封装层上形成第二重新布线层，所述第二重新布线层包括层叠的第二介质层及第二金属布线层，所述第二金属布线层与所述金属连接柱电连接；
基于所述分离层剥离所述支撑载体，以暴露所述第一重新布线层远离所述封装层的一面；
于所述第一重新布线层远离所述封装层的一面形成导电凸块，所述导电凸块与所述第一重新布线层电连接；
提供至少一第一功能芯片与至少一元器件，将所述第一功能芯片和所述元器件分别与所述第二重新布线层远离所述封装层的一面电连接；
于所述第二重新布线层上形成冷却层，所述冷却层与所述第二重新布线层之间形成空腔，所述第一功能芯片与所述元器件均位于所述空腔中；
提供一封装晶圆，将所述导电凸块与所述封装晶圆连接。
可选地，形成所述金属连接柱之前，还包括于所述第一重新布线层远离所述分离层的一面形成第一开口的步骤，所述第一开口显露所述第一金属布线层，所述金属连接柱伸入所述第一开口与所述第一金属布线层连接。
可选地，形成所述导电凸块之前，还包括于所述第一重新布线层远离所述封装层的一面形成第二开口的步骤，所述第二开口显露所述第一金属布线层，所述导电凸块伸入所述第二开口与所述第一金属布线层连接。
可选地，所述第一功能芯片的个数为多个，多个所述第一功能芯片在水平方向上呈阵列排布；所述元器件的个数为多个，多个所述元器件在水平方向上呈阵列排布。
可选地，所述第一重新布线层包括在垂直方向上堆叠的至少一所述第一介质层及至少一所述第一金属布线层；所述第二重新布线层包括在垂直方向上堆叠的至少一所述第二介质层及至少一所述第二金属布线层。
可选地，所述提供一封装晶圆，将所述导电凸块与所述封装晶圆连接之前，还包括以下步骤：
提供至少一第二功能芯片，将所述第二功能芯片与所述导电凸块连接；
提供一连接器，将所述连接器与所述导电凸块连接，所述第二功能芯片与所述连接器间隔预设距离，其中，所述导电凸块通过所述连接器与所述封装晶圆连接。
本发明还提供一种扇出型系统级封装结构，包括：
第一重新布线层，所述第一重新布线层包括层叠的第一介质层和第一金属布线层；
第二重新布线层，位于所述第一重新布线层上方并与所述第一重新布线层间隔预设距离，所述第二重新布线层包括层叠的第二介质层及第二金属布线层；
封装层，位于所述第一重新布线层与所述第二重新布线层之间；
金属连接柱，在垂直方向上贯穿所述封装层，所述金属连接柱的底端与所述第一金属布线层电连接，所述金属连接柱的顶端与所述第二金属布线层电连接；
导电凸块，位于所述第一重新布线层下方，所述导电凸块与所述第一重新布线层电连接；
至少一第一功能芯片，所述第一功能芯片与所述第二重新布线层电连接；
至少一元器件，所述元器件与所述第二重新布线层电连接，所述元器件与所述第一功能芯片间隔预设距离；
冷却层，位于所述第二重新布线层上，所述冷却层与所述第二重新布线层之间形成空腔，所述第一功能芯片和所述元器件均位于所述空腔中；
封装晶圆，位于所述第一重新布线层具有所述导电凸块的一侧，所述封装晶圆与所述导电凸块连接。
可选地，所述第一功能芯片的个数为多个，多个所述第一功能芯片在水平方向上呈阵列排布；所述元器件的个数为多个，多个所述元器件在水平方向上呈阵列排布。
可选地，所述第一重新布线层包括在垂直方向上堆叠的至少一所述第一介质层及 至少一所述第一金属布线层；所述第二重新布线层包括在垂直方向上堆叠的至少一所述第二介质层及至少一所述第二金属布线层。
可选地，所述封装晶圆与所述导电凸块之间还包括连接器与至少一第二功能芯片，所述连接器与所述导电凸块连接，所述第二功能芯片与所述导电凸块连接，所述第二功能芯片与所述连接器间隔预设距离，其中，所述封装晶圆通过所述连接器与所述导电凸块连接。
如上所述，本发明的扇出型系统级封装结构及制作方法中，通过金属连接柱实现上下层的互连，可以进行超高级程系统级封装，在第二重新布线层上连接第一功能芯片及元器件做高密度连接封装，可以在一片封装晶圆(例如8寸或12寸)中将处理器、记忆体等功能芯片和光电元器件、光学元件及MEMS元件等集成在一个封装体内实现一个基本完整的功能，不仅提高制程结构的整合性，有利于缩小封装尺寸。并且可以在导电凸块上连接第二功能芯片，在实现高密度密封连接的同时，提高灵活性与相容性，增加封装体性能。
附图说明
图1显示为本发明的扇出型系统级封装结构的制作方法的工艺流程图。
图2显示为本发明的扇出型系统级封装结构的制作方法中提供支撑载体，并于所述支撑载体上形成分离层的示意图。
图3显示为本发明的扇出型系统级封装结构的制作方法中于所述分离层上形成第一重新布线层，并形成第一开口的示意图。
图4显示为本发明的扇出型系统级封装结构的制作方法中于所述第一重新布线层上形成金属连接柱的示意图。
图5显示为本发明的扇出型系统级封装结构的制作方法中于所述第一重新布线层上形成封装层的示意图。
图6显示为本发明的扇出型系统级封装结构的制作方法中减薄所述封装层的示意图。
图7显示为本发明的扇出型系统级封装结构的制作方法中于所述封装层上形成第二重新布线层的示意图。
图8显示为本发明的扇出型系统级封装结构的制作方法中基于所述分离层去除所述支撑载体，以显露所述第一重新布线层的示意图。
图9显示为本发明的扇出型系统级封装结构的制作方法中于所述第一重新布线层远离所述封装层的一面形成第二开口的示意图。
图10显示为本发明的扇出型系统级封装结构的制作方法中于所述第一重新布线层远离所述封装层的一面形成导电凸块的示意图。
图11显示为本发明的扇出型系统级封装结构的制作方法中提供第一功能芯片和元器件，将所述第一功能芯片和所述元器件分别与所述第二重新布线层连接的示意图。
图12显示为本发明的扇出型系统级封装结构的制作方法中于所述第一功能芯片与所述第二重新布线层的连接间隙处形成第一填充层的示意图。
图13显示为本发明的扇出型系统级封装结构的制作方法中于所述第二重新布线层上形成冷却层的示意图。
图14显示为本发明的扇出型系统级封装结构中所述第一功能芯片和所述元器件的平面布局图。
图15显示为本发明的扇出型系统级封装结构的制作方法中提供第二功能芯片与连接器，将所述第二功能芯片和所述连接器分别与所述导电凸块连接的示意图。
元件标号说明：10-支撑载体，20-分离层，30-第一重新布线层，31-第一介质层，32-第一金属布线层，301-第一开口，302-第二开口，40-金属连接柱，50-封装层，60-第二重新布线层，61-第二介质层，62-第二金属布线层，70-导电凸块，80-第一功能芯片，81-芯片焊盘，90-元器件，100-第一填充层，110-冷却层，120-热传递介质层，130-第二功能芯片，140-连接器，150-第二填充层，S1～S10-步骤。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1至图15。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
实施例一
本实施例提供一种扇出型系统级封装结构的制作方法，请参阅图1，显示为该方法的工艺流程图，包括以下步骤：
S1：提供一支撑载体，于所述支撑载体上形成分离层；
S2：于所述分离层上形成第一重新布线层，所述第一重新布线层包括层叠的第一介质层和第一金属布线层；
S3：于所述第一重新布线层上形成金属连接柱，所述金属连接柱与所述第一金属布线层电连接；
S4：于所述第一重新布线层上形成封装层，所述封装层覆盖所述第一重新布线层及所述金属连接柱，并减薄所述封装层以显露所述金属连接柱；
S5：于所述封装层上形成第二重新布线层，所述第二重新布线层包括层叠的第二介质层及第二金属布线层，所述第二金属布线层与所述金属连接柱电连接；
S6：基于所述分离层剥离所述支撑载体，以暴露所述第一重新布线层远离所述封装层的一面；
S7：于所述第一重新布线层远离所述封装层的一面形成导电凸块，所述导电凸块与所述第一重新布线层电连接；
S8：提供至少一第一功能芯片与至少一元器件，将所述第一功能芯片和所述元器件分别与所述第二重新布线层远离所述封装层的一面电连接；
S9：于所述第二重新布线层上形成冷却层，所述冷却层与所述第二重新布线层之间形成空腔，所述第一功能芯片与所述元器件均位于所述空腔中；
S10：提供一封装晶圆，将所述导电凸块与所述封装晶圆连接。
首先，请参阅图2，执行步骤S1：提供一支撑载体10，于所述支撑载体10上形成分离层20。
作为示例，所述支撑载体10包括但不限于玻璃载体、金属载体、半导体载体、聚合物载体及陶瓷载体中的任意一种，用于防止封装过程中层结构开裂、翘曲、断裂等，所述支撑载体10的形状可以是晶圆状、面板状和其他任何需要的形状。本实施例中，所述支撑载体10采用玻璃载体，其成本较低，容易在其表面形成所述分离层20，且能降低后续的剥离工艺的难度。
作为示例，所述分离层20的材质包括胶带或聚合物，通过旋涂工艺涂覆于所述支撑载体10表面，然后采用紫外光固化或热固化方式成型。
请参阅图3，接着执行步骤S2：于所述分离层20上形成第一重新布线层30，所述第一重新布线层30包括层叠的第一介质层31和第一金属布线层32。
作为示例，形成所述第一重新布线层30的步骤包括：
(1)采用化学气相沉积法、物理气相沉积法或其它合适的方法于所述分离层20表面形成第一介质层31，所述第一介质层31的材质包括但不限于环氧树脂、硅胶、PI、PBO、BCB、氧化硅、磷硅玻璃、含氟玻璃中的一种或两种以上组合；
(2)采用溅射、电镀、化学镀或其它合适的方法于所述第一介质层31表面形成第一金属层，并对所述第一金属层进行刻蚀形成图形化的第一金属布线层32。所述第一金属布线层32的材料包括铜、铝、镍、金、银、钛中的一种或两种以上组合。
需要说明的是，可以根据需要重复上述步骤，以形成具有多层堆叠结构的所述第一重新布线层30，以实现不同的布线需求，多层第一金属布线层32之间通过导电栓塞电连接。
作为示例，于所述第一重新布线层30远离所述分离层20的一面形成第一开口301以显露所述第一重新布线层32，形成所述第一开口301的方法包括光刻刻蚀法、激光打孔法或其它合适的方法，所述第一开口301自下而上逐渐增大，呈漏斗状。
请参阅图4，接着执行步骤S3：于所述第一重新布线层上30形成金属连接柱40，所述金属连接柱40与所述第一金属布线层32电连接。
作为示例，所述金属连接柱40伸入所述第一开口301中与所述第一金属布线层32连接。
作为示例，形成所述金属连接柱40的方法包括电镀、化学镀、焊线或其它合适的方法，所述金属连接柱40的材质包括铜、铝、镍、金、银、钛中的一种或两种以上组合，本实施例优选电镀铜柱。
需要说明的是，于所述第一重新布线层30的表面直接形成所述金属连接柱40，由于没有任何阻碍，不用担心制作过程中对其他结构造成不良影响，且可以实现与所述第一金属布线层32的对准，相较于传统的先形成介质层再在介质层中形成通孔后沉积金属的方法，工艺过程极大简化，且能够实现细线宽线距布局，利于进行高密度连接。
接着执行步骤S4：于所述第一重新布线层30上形成封装层50，所述封装层50覆盖所述第一重新布线层30及所述金属连接柱40，并减薄所述封装层50以显露所述金属连接柱40。
作为示例，如图5所示，于所述第一重新布线层30上形成所述封装层50，形成所述封装层50的方法包括但不限于压缩成型、传递模塑成型、液封成型、真空层压及旋涂中的任意一种，所述封装层50的材质包括可固化材料，如聚合物基材料、树脂基材料、聚酰胺及其任何组合。
作为示例，如图6所示，减薄所述封装层50以显露所述金属连接柱40，减薄所述封装层50的方法包括研磨、抛光或其它合适的方法，减薄后的所述封装层50的上表面与所述金属连接柱40的上表面齐平。
请参阅图7，接着执行步骤S5：于所述封装层50上形成第二重新布线层60，所述第二重新布线层60包括层叠的第二介质层61及第二金属布线层62，所述第二金属布线层62与所述金属连接柱40电连接。
作为示例，形成所述第二重新布线层60的方法与形成所述第一重新布线层30的方法相同，这里不做详细赘述。
请参阅图8，接着执行步骤S6：基于所述分离层20剥离所述支撑载体10，以暴露所述第一重新布线层30远离所述封装层50的一面。
具体的，根据所述分离层20的类型采用相应的方法使得所述分离层20粘性下降，进而剥离所述支撑载体10及所述分离层20。例如，当所述分离层20采用光热转换材料时，可采用激光照射所述光热转换层，以使所述光热转换层与所述第一重新布线层30及所述支撑载体10分离。
作为示例，如图9所示，于所述第一重新布线层30远离所述封装层50的一面形成第二开口302以显露所述第一重新布线层32；形成所述第二开口302的方法包括光刻刻蚀法、激光打孔法或其它合适的方法，所述第二开口302自下而上逐渐减小，呈倒漏斗状。
请参阅图10，接着执行步骤S7：于所述第一重新布线层30远离所述封装层50的一面形成导电凸块70，所述导电凸块70与所述第一重新布线层32电连接。
作为示例，所述导电凸块70伸入所述第二开口302中与所述第一金属布线层32连接，所述导电凸块70可由金属柱、焊点组成，也可以只是锡球。
请参阅图11，接着执行步骤S8：提供至少一第一功能芯片80与至少一元器件90，将所述第一功能芯片80和所述元器件90分别与所述第二重新布线层60远离所述封装层50的一面电连接。
作为示例，所述第一功能芯片80的个数为多个，其种类包括处理器、记忆体等；所述元器件90的个数为多个，其种类包括光电元器件，光学元件和MEMS元件等。须知，本实施例仅示例性列举几种所述第一功能芯片80和所述元器件90的类型，不以本实施例为限制，在实际生产制造中，根据封装体的功能需求选择所述第一功能芯片80和所述元器件90的种类与数量。
具体的，所述第一功能芯片80通过芯片焊盘(芯片引脚)81与所述第二重新布线层60电连接，所述元器件90通过表面贴装技术(Surface Mounted Technology，SMT)连接于所述第二重新布线层60。
作为示例，如图12所示，可进一步采用点胶工艺或其它合适的工艺于所述第一功能芯片80与所述第二重新布线层60之间的连接间隙处形成第一填充层100，所述第一填充层100一方面可以对所述第一功能芯片80与所述第二重新布线层60的连接处提供保护，防 止腐蚀或连接损坏，另一方面可以提高所述第一功能芯片80与所述第二重新布线层60的粘结性能，提高机械强度。
请参阅图13，接着执行步骤S9：于所述第二重新布线层60上形成冷却层110，所述冷却层110与所述第二重新布线层60之间形成空腔，所述第一功能芯片80与所述元器件90均位于所述空腔中。
作为示例，所述冷却层110的材质包括银、铜、金及铝中的一种，也可以是其它合适的高导热系数材料。
作为示例，于所述第一功能芯片80的表面和所述冷却层110之间形成有热传递介质层120，所述热传递介质层120可以是散热膏或其他高导热材料，一方面所述热传递介质层120可以作为所述第一功能芯片80和所述冷却层110之间的粘结剂，另一方面，来自所述第一功能芯片80的热量可以通过所述热传递介质层120更有效的热传导至所述冷却层110。
接着，执行步骤S10：提供一封装晶圆，将所述导电凸块70与所述封装晶圆连接。
作为示例，所述封装晶圆包括8寸或12寸的封装晶圆，具体的，本实施例中，所述封装晶圆采用12寸的封装晶圆，所述导电凸块70与所述封装晶圆连接，用以后续对封装体的电性引出，例如与外部电源连接等。
作为示例，如图14所示，显示为所述第一功能芯片80与所述元器件90的平面布局图，多个所述第一功能芯片80与多个所述元器件90呈阵列排布，可以在一片封装晶圆中将多种功能芯片包括处理器、记忆体等和多种元器件包括光电元器件、光学元件、MEMS元件等集成在一个封装体内，从而实现一个基本完整的功能。
可选地，如图15所示，提供第二功能芯片130和连接器140，将所述第二功能芯片130和所述连接器140分别与所述导电凸点70连接。
作为示例，所述第二功能芯片120包括但不限于处理器、记忆体、电源管理芯片、发射器芯片、接收器芯片等。
作为示例，于所述第二功能芯片130和所述导电凸块70的连接间隙处形成第二填充层150，所述第二填充层150一方面可以对所述第二功能芯片130与所述导电凸块70的连接处提供保护，防止腐蚀或连接损坏，另一方面可以提高所述第二功能芯片150与所述导电凸块70的粘结性能，提高机械强度。
作为示例，所述连接器140包括针座连接器，所述连接器140用以后续与所述封装晶圆连接，进而连接外部电源。
需要说明的是，通过设置两层芯片层(即第一功能芯片80层区和第二功能芯片130层区)，在实现高密度密封连接的同时，具有更高的灵活性与更广泛的相容性。例如，实现封装体完整功能的同时，设置两层芯片层，可以提高芯片之间的间距，降低芯片之间的串扰，提高灵活性与相容性。
本实施例提供的扇出型系统级封装结构的制作方法中，通过金属连接柱实现上下层的互连，可以进行超高级程系统级封装，在第二重新布线层上连接第一功能芯片及元器件做高密度连接封装，可以在一片封装晶圆中将处理器、记忆体等功能芯片和光电元器件、光学元件及MEMS元件等集成在一个封装体内实现一个基本完整的功能，能够提高制程结构的整合性，缩小封装尺寸；另外，还可以在导电凸块连接第二功能芯片与连接器，在实现高密度密封连接的同时，具有更高的灵活性与更广泛的相容性，增加封装体性能。
实施例二
请参阅图13，本实施例提供一种扇出型系统级封装结构，所述扇出型系统级封装结构可由实施例一所述的制作方法制作而成，但不局限于实施例一中所述的制作方法。
所述扇出型系统级封装结构包括第一重新布线层30、第二重新布线层60、封装层50、金属连接柱40、导电凸块70、至少一第一功能芯片80、至少一元器件90、冷却层110及封装晶圆，其中，所述第一重新布线层30包括层叠的第一介质层31和第一金属布线层32，所述第二重新布线层60位于所述第一重新布线层30上方并与所述第一重新布线层30间隔预设距离，所述第二重新布线层60包括层叠的第二介质层61及第二金属布线层62，所述封装层50位于所述第一重新布线层30与所述第二重新布线层60之间，所述金属连接柱40在垂直方向上贯穿所述封装层50，所述金属连接柱40的底端与所述第一金属布线层32电连接，所述金属连接柱40的顶端与所述第二金属布线层62电连接，所述导电凸块70位于所述第一重新布线层30下方并与所述第一重新布线层30电连接，所述第一功能芯片80与所述第二重新布线层60电连接，所述元器件90与所述第二重新布线层60电连接，所述元器件90与所述第一功能芯片80间隔预设距离，所述冷却层110位于所述第二重新布线层60上，所述冷却层110与所述第二重新布线层60之间形成空腔，所述第一功能芯片80及所述元器件90均位于所述空腔中，所述封装晶圆位于所述第一重新布线层60具有所述导电凸块70的一侧，所述封装晶圆与所述导电凸块70连接。
作为示例，所述第一重新布线层30包括在垂直方向上堆叠的至少一所述第一介质层31及至少一所述第一金属布线层32，所述第二重新布线层60包括在垂直方向上堆叠的至少一第二介质层61及至少一第二金属布线层62。
作为示例，所述封装层50包括但不限于聚合物基材料层、树脂基材料层、聚酰胺层、环氧树脂层及其任何组合。
作为示例，所述金属连接柱40包括但不限于铜柱。
作为示例，所述导电凸块70可由金属柱、焊点组成，也可以只是锡球。
作为示例，所述第一功能芯片80的个数为多个，其种类包括处理器、记忆体等；所述元器件90的个数为多个，其种类包括光电元器件，光学元件和MEMS元件等。须知，本实施例仅示例性列举几种所述第一功能芯片80和所述元器件90的类型，不以本实施例为限制，在实际应用中，根据封装体的功能需求选择所述第一功能芯片80和所述元器件90的种类与数量。
作为示例，所述第一功能芯片80包括芯片焊盘81，所述第一功能芯片80通过所述芯片焊盘81与所述第二金属布线层62电连接。
作为示例，所述第一功能芯片80及所述第二重新布线层60之间的连接间隙处设有第一填充层100，所述第一填充层100一方面可以对所述第一功能芯片80与所述第二重新布线层60的连接处提供保护，防止腐蚀或连接损坏，另一方面可以提高所述第一功能芯片80与所述第二重新布线层60的粘结性能，提高机械强度。
作为示例，所述第一功能芯片80和所述冷却层110之间设有热传递介质层120，所述热传递介质层120可以是散热膏或其他高导热材料，一方面所述热传递介质层120可以作为所述第一功能芯片80和所述冷却层110之间的粘结剂，另一方面，来自所述第一功能芯片80的热量可以通过所述热传递介质层120更有效的热传导至所述冷却层110。
作为示例，所述封装晶圆包括8寸或12寸的封装晶圆，具体的，本实施例中，所述封装晶圆采用12寸的封装晶圆，所述导电凸块70与所述封装晶圆连接，用以后续对封装体的电性引出，例如与外部电源连接等。
作为示例，如图14所示，显示为所述第一功能芯片80与所述元器件90的平面布局图，多个所述第一功能芯片80与多个所述元器件90呈阵列排布，可以在一片封装晶圆中将多种功能芯片包括处理器、记忆体等和多种元器件包括光电元器件、光学元件、MEMS元件等集成在一个封装体内，从而实现一个基本完整的功能。
可选地，如图15所示，还包括第二功能芯片130和连接器140，所述第二功能芯片130和所述连接器140分别与所述导电凸点70连接。
作为示例，所述第二功能芯片130包括但不限于处理器、记忆体、电源管理芯片、发射器芯片、接收器芯片等。
作为示例，所述第二功能芯片130与所述导电凸块70之间设有第二填充层150，所述第二填充层150一方面可以对所述第二功能芯片130与所述导电凸块70的连接处提供保护，防止腐蚀或连接损坏，另一方面可以提高所述第二功能芯片150与所述导电凸块70的粘结性能，提高机械强度。
作为示例，所述连接器140包括针座连接器，所述连接器140用以后续与所述封装晶圆连接，进而连接外部电源。
需要说明的是，通过设置两层芯片层(即第一功能芯片80层区和第二功能芯片130层区)，在实现高密度密封连接的同时，具有更高的灵活性与更广泛的相容性。例如，实现封装体完整功能的同时，设置两层芯片层，可以提高芯片之间的间距，降低芯片之间的串扰，提高灵活性与相容性。
综上所述，本发明提供的扇出型系统级封装结构及制作方法中，通过金属连接柱实现上下层的互连，可以进行超高级程系统级封装，在第二重新布线层上连接第一功能芯片及元器件做高密度连接封装，可以在一片封装晶圆(例如8寸或12寸)中将处理器、记忆体等功能芯片和光电元器件、光学元件及MEMS元件等集成在一个封装体内实现一个基本完整的功能，能够提高制程结构的整合性，缩小封装尺寸；另外，还可以在导电凸块连接第二功能芯片与连接器，在实现高密度密封连接的同时，具有更高的灵活性与更广泛的相容性，增加封装体性能。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (10)

  1. 一种扇出型系统级封装结构的制作方法，其特征在于，包括以下步骤：
    提供一支撑载体，于所述支撑载体上形成分离层；
    于所述分离层上形成第一重新布线层，所述第一重新布线层包括层叠的第一介质层和第一金属布线层；
    于所述第一重新布线层上形成金属连接柱，所述金属连接柱与所述第一金属布线层电连接；
    于所述第一重新布线层上形成封装层，所述封装层覆盖所述第一重新布线层及所述金属连接柱，并减薄所述封装层以显露所述金属连接柱；
    于所述封装层上形成第二重新布线层，所述第二重新布线层包括层叠的第二介质层及第二金属布线层，所述第二金属布线层与所述金属连接柱电连接；
    基于所述分离层剥离所述支撑载体，以暴露所述第一重新布线层远离所述封装层的一面；
    于所述第一重新布线层远离所述封装层的一面形成导电凸块，所述导电凸块与所述第一重新布线层电连接；
    提供至少一第一功能芯片与至少一元器件，将所述第一功能芯片和所述元器件分别与所述第二重新布线层远离所述封装层的一面电连接；
    于所述第二重新布线层上形成冷却层，所述冷却层与所述第二重新布线层之间形成空腔，所述第一功能芯片与所述元器件均位于所述空腔中；
    提供一封装晶圆，将所述导电凸块与所述封装晶圆连接。
  2. 根据权利要求1所述的扇出型系统级封装结构的制作方法，其特征在于：形成所述金属连接柱之前，还包括于所述第一重新布线层远离所述分离层的一面形成第一开口的步骤，所述第一开口显露所述第一金属布线层，所述金属连接柱伸入所述第一开口与所述第一金属布线层连接。
  3. 根据权利要求1所述的扇出型系统级封装结构的制作方法，其特征在于：形成所述导电凸块之前，还包括于所述第一重新布线层远离所述封装层的一面形成第二开口的步骤，所述第二开口显露所述第一金属布线层，所述导电凸块伸入所述第二开口与所述第一金属布线层连接。
  4. 根据权利要求1所述的扇出型系统级封装结构的制作方法，其特征在于：所述第一功能芯片的个数为多个，多个所述第一功能芯片在水平方向上呈阵列排布；所述元器件的个数为多个，多个所述元器件在水平方向上呈阵列排布。
  5. 根据权利要求1所述的扇出型系统级封装结构的制作方法，其特征在于：所述第一重新布线层包括在垂直方向上堆叠的至少一所述第一介质层及至少一所述第一金属布线层；所述第二重新布线层包括在垂直方向上堆叠的至少一所述第二介质层及至少一所述第二金属布线层。
  6. 根据权利要求1-5中任意一项所述的扇出型系统级封装结构的制作方法，其特征在于，所述提供一封装晶圆，将所述导电凸块与所述封装晶圆连接之前，还包括以下步骤：
    提供至少一第二功能芯片，将所述第二功能芯片与所述导电凸块连接；
    提供一连接器，将所述连接器与所述导电凸块连接，所述第二功能芯片与所述连接器间隔预设距离，其中，所述导电凸块通过所述连接器与所述封装晶圆连接。
  7. 一种扇出型系统级封装结构，其特征在于，包括：
    第一重新布线层，所述第一重新布线层包括层叠的第一介质层和第一金属布线层；
    第二重新布线层，位于所述第一重新布线层上方并与所述第一重新布线层间隔预设距离，所述第二重新布线层包括层叠的第二介质层及第二金属布线层；
    封装层，位于所述第一重新布线层与所述第二重新布线层之间；
    金属连接柱，在垂直方向上贯穿所述封装层，所述金属连接柱的底端与所述第一金属布线层电连接，所述金属连接柱的顶端与所述第二金属布线层电连接；
    导电凸块，位于所述第一重新布线层下方，所述导电凸块与所述第一重新布线层电连接；
    至少一第一功能芯片，所述第一功能芯片与所述第二重新布线层电连接；
    至少一元器件，所述元器件与所述第二重新布线层电连接，所述元器件与所述第一功能芯片间隔预设距离；
    冷却层，位于所述第二重新布线层上，所述冷却层与所述第二重新布线层之间形成空腔，所述第一功能芯片和所述元器件均位于所述空腔中；
    封装晶圆，位于所述第一重新布线层具有所述导电凸块的一侧，所述封装晶圆与所述导电凸块连接。
  8. 根据权利要求7所述的扇出型系统级封装结构，其特征在于：所述第一功能芯片的个数为多个，多个所述第一功能芯片在水平方向上呈阵列排布；所述元器件的个数为多个，多个所述元器件在水平方向上呈阵列排布。
  9. 根据权利要求7所述的扇出型系统级封装结构，其特征在于：所述第一重新布线层包括在垂直方向上堆叠的至少一所述第一介质层及至少一所述第一金属布线层；所述第二重新布线层包括在垂直方向上堆叠的至少一所述第二介质层及至少一所述第二金属布线层。
  10. 根据权利要求7-9中任意一项所述的扇出型系统级封装结构，其特征在于：所述封装晶圆与所述导电凸块之间还包括连接器与至少一第二功能芯片，所述连接器与所述导电凸块连接，所述第二功能芯片与所述导电凸块连接，所述第二功能芯片与所述连接器间隔预设距离，其中，所述封装晶圆通过所述连接器与所述导电凸块连接。
PCT/CN2023/097799 2022-09-05 2023-06-01 一种扇出型系统级封装结构及制作方法 WO2024051225A1 (zh)

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