WO2024050951A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2024050951A1
WO2024050951A1 PCT/CN2022/129729 CN2022129729W WO2024050951A1 WO 2024050951 A1 WO2024050951 A1 WO 2024050951A1 CN 2022129729 W CN2022129729 W CN 2022129729W WO 2024050951 A1 WO2024050951 A1 WO 2024050951A1
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semiconductor
forming
substrate
along
layer
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PCT/CN2022/129729
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English (en)
French (fr)
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李晓杰
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长鑫存储技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure and a method of forming the same.
  • DRAM Dynamic Random Access Memory
  • each storage unit usually includes a transistor and a capacitor.
  • the gate of the transistor is electrically connected to the word line
  • the source is electrically connected to the bit line
  • the drain is electrically connected to the capacitor.
  • the word line voltage on the word line can control the turning on and off of the transistor, so that the memory can be read through the bit line. Data information in the capacitor, or writing data information into the capacitor.
  • memories such as DRAM are gradually developing from two-dimensional structures to three-dimensional structures.
  • a superlattice structure in which semiconductor layers and sacrificial layers are stacked needs to be formed through a deposition process. This inevitably leads to stress and large differences in crystal orientation in the final semiconductor structure. And defects such as the incorporation of impurities are easily caused, which leads to a decrease in the yield of semiconductor structures and limits the further improvement of the performance of semiconductor structure products.
  • the semiconductor structure and its formation method provided by some embodiments of the present disclosure are used to reduce defects in the semiconductor structure to improve the manufacturing yield of the semiconductor structure and improve the performance of the semiconductor structure.
  • the present disclosure provides a method for forming a semiconductor structure, including the following steps:
  • a plurality of first trenches are formed in the semiconductor block, and the plurality of first trenches separate the semiconductor block into a plurality of semiconductor layers spaced apart along a first direction, the first direction being perpendicular to the the top surface of the substrate.
  • the following steps are also included:
  • Doping ions are implanted into the active area.
  • forming a substrate and a semiconductor block protruding from a top surface of the substrate includes:
  • the initial substrate remaining on the side of the opening serves as the semiconductor block, the opening, and the The initial substrate remaining under the semiconductor block serves as the substrate, and the semiconductor block is located in the active area.
  • forming a plurality of first trenches in the semiconductor block includes:
  • a dielectric layer located on the side of the semiconductor block is formed on the substrate.
  • the dielectric layer includes a plurality of first etching windows.
  • the plurality of first etching windows are spaced apart along the first direction. ;
  • the adjacent first trenches are The semiconductor blocks remaining between the grooves serve as the semiconductor layer.
  • the number of the openings is multiple, and the semiconductor block is located between two adjacent openings along the third direction;
  • the steps for the dielectric layer include:
  • the dielectric layers are respectively formed on opposite sides of the semiconductor block in the third direction, and the dielectric layers located on opposite sides of the semiconductor block in the third direction face each other along the center of the semiconductor block.
  • the central plane is perpendicular to the third direction, and the third direction is parallel to the top surface of the substrate.
  • the step of forming a dielectric layer located on the side of the semiconductor block on the substrate includes:
  • first dielectric layer and a second dielectric layer Forming a first dielectric layer and a second dielectric layer on the side of the semiconductor block, the first dielectric layer and the second dielectric layer being alternately stacked along the first direction;
  • the following steps are further included:
  • a first support pillar is formed that penetrates the semiconductor block at least along the first direction.
  • forming a support pillar extending through the semiconductor block at least along the first direction includes:
  • the first support pillar is formed in the first support hole, and a second support pillar is formed in the second support hole at the same time.
  • the first support pillar is located in the middle or end of the semiconductor block
  • the second support pillar is located in the middle or end of the first dielectric layer and the second dielectric layer.
  • a protective layer covering the top surface of the semiconductor block is formed.
  • the following first cyclic steps are performed at least once until the first trench penetrating the semiconductor block in a direction parallel to the top surface of the substrate is formed, the first cyclic steps include:
  • the etching rate of the first etchant for the ⁇ 100> crystal orientation is smaller than the etching rate for other crystal orientations
  • Silicon material is epitaxially grown along the surface of the semiconductor block exposed through the first etching window.
  • the step of etching the semiconductor block along the first etch window using a first etchant includes:
  • An atomic layer etching process is used to etch the semiconductor block along the first etching window.
  • the first etchant includes tetramethylammonium hydroxide.
  • the first etchant further includes an additive, and the additive is any one of isopropyl alcohol, butanol, and tritium or a combination of two or more.
  • the following second cycle steps are performed at least once until the first trench penetrating the semiconductor block in a direction parallel to the top surface of the substrate is formed, the second cycle steps include:
  • Conversion processing is performed on the semiconductor block along the first etching window to form a conversion layer, and the conversion processing rate of the ⁇ 100> crystal orientation is smaller than the conversion processing rate of other crystal orientations;
  • a second etchant is used to etch the conversion layer along the first etching window, and the etching rate of the second etchant on the conversion layer is greater than the etching rate of silicon.
  • the conversion treatment is an oxidation treatment
  • the conversion layer is a silicon oxide layer.
  • the following steps are further included:
  • the plurality of second trenches separate the semiconductor layer into a plurality of second trenches spaced apart along the second direction.
  • Semiconductor pillar, the second direction is parallel to the top surface of the substrate, and the second direction intersects the third direction;
  • a channel region in the semiconductor pillar of the transistor region forming a channel region in the semiconductor pillar of the transistor region, source regions and drain regions distributed on opposite sides of the channel region along the third direction, and covering the surface of the channel region a word line, the source region is adjacent to the bit line region, and the drain region is adjacent to the capacitor region;
  • a bit line is formed in the bit line trench, and the bit line is electrically connected to the source region.
  • the present disclosure also provides a semiconductor structure, including:
  • a plurality of semiconductor layers are spaced apart along a first direction, the first direction is perpendicular to the top surface of the substrate; the plurality of semiconductor layers and the substrate have the same crystal orientation.
  • the semiconductor layer includes a plurality of active regions spaced apart along the second direction, the active region includes a channel region, and a plurality of active regions distributed in the channel region along the third direction.
  • the source region and the drain region on opposite sides, and the plurality of active regions in the semiconductor layer have the same crystallographic orientation.
  • the semiconductor structure and its formation method provided by some embodiments of the present disclosure first form a semiconductor block by etching an initial substrate, and then lateral etching the semiconductor block, thereby separating the semiconductor block into sections along the top surface perpendicular to the substrate.
  • Multiple semiconductor layers spaced apart in the direction thereby eliminating the need to form multiple semiconductor layers spaced apart in the direction perpendicular to the substrate through deposition or epitaxial processes, reducing or even eliminating problems caused by layer-by-layer deposition Defect problems such as stress are eliminated, and the plurality of semiconductor layers formed have the same crystal orientation as the substrate, which reduces defects such as lattice deformation and impurity introduction in the semiconductor layer, thereby improving the manufacturing yield of the semiconductor structure and improving Electrical properties of semiconductor structures.
  • some embodiments of the present disclosure form first dielectric layers and second dielectric layers that are alternately stacked in a direction perpendicular to the top surface of the substrate, and form the first etching window by removing the first dielectric layer, That is, the semiconductor block is laterally etched through a self-alignment process, thereby improving the controllability of the position and thickness of a single semiconductor layer and the position and width of the first trench between adjacent semiconductor layers. , improving the flexibility of manufacturing the semiconductor structure.
  • FIG. 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure
  • Figures 2-12 are schematic diagrams of the main process structures in the process of forming semiconductor structures according to specific embodiments of the present disclosure
  • FIG. 13 is a schematic diagram of the relationship between the thickness of the oxide layer of different crystallographic directions and the oxidation time during the oxidation process of silicon in a specific embodiment of the present disclosure.
  • FIG. 1 is a flow chart of the method for forming a semiconductor structure in the specific embodiment of the present disclosure.
  • Figures 2-12 are diagrams of the process of forming the semiconductor structure in the specific embodiment of the present disclosure. Schematic diagram of the main process structure. As shown in Figures 1-12, the method for forming the semiconductor structure includes the following steps:
  • step S11 an initial substrate 20 is provided, as shown in FIG. 2 .
  • the initial substrate 20 may be, but is not limited to, a silicon substrate.
  • the initial substrate 20 is a silicon substrate as an example for description.
  • the initial substrate 20 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI.
  • step S12 the initial substrate 20 is etched to form a substrate 40 and a semiconductor block 41 protruding from the top surface of the substrate 40 , as shown in FIG. 4 .
  • Implant doping ions into the active area Implant doping ions into the active area.
  • the active region can be defined in the initial substrate 20 through a photomask, etc., and then doping ions can be injected into the initial substrate using vapor diffusion or plasma injection. Active area in 20. The active area is subsequently used to form at least the transistors in the memory cell.
  • the implanted doping ions may be N-type ions or P-type ions, and those skilled in the art can choose according to actual needs.
  • the arrow in Figure 2 indicates the direction in which doping ions are implanted into the initial substrate 20.
  • the specific steps of forming the substrate 40 and the semiconductor block 41 protruding from the top surface of the substrate 40 include:
  • the initial substrate 20 is etched from the top surface of the initial substrate 20 using a deep etching process to form at least one opening 42 .
  • the initial substrate 20 remaining on the side of the opening 42 serves as the semiconductor block 41 , and the initial substrate 20 remains below the opening 42 and the semiconductor block 41 .
  • the substrate 20 serves as the substrate 40, and the semiconductor block 41 is located in the active area.
  • the first mask layer 30 is formed on the top surface of the initial substrate 20 , and the first mask layer 30 is patterned to form a top surface of the first mask layer 30 that exposes the initial substrate 20 .
  • the second etching window on the surface.
  • a deep etching process is used to etch the original substrate 20 downward along the second etching window to form an opening 42 .
  • the initial substrate 20 remaining on the side of the opening 42 serves as the semiconductor block 41
  • the initial substrate 20 remaining below the opening 42 and the semiconductor block 41 serves as the substrate 40 .
  • the semiconductor block 41 is protrudingly disposed on the top surface of the substrate 40 , so that the semiconductor block 41 and the substrate 40 jointly form a step-like structure.
  • the number of openings 42 may be multiple.
  • the number of openings 42 shown in FIG. 4 is two. and are symmetrically distributed on opposite sides of the semiconductor block 41 along the third direction D3, where the third direction D3 is parallel to the top surface of the substrate 40.
  • the top surface of the substrate 40 in this specific embodiment refers to the surface of the substrate 40 facing the semiconductor block 41 .
  • Step S13 forming a plurality of first trenches 81 in the semiconductor block 41.
  • the plurality of first trenches 81 separate the semiconductor block 41 into a plurality of semiconductor layers 82 spaced apart along the first direction D1.
  • the first direction D1 is vertical.
  • FIGS. 8, 9 and 10 where FIG. 9 is a schematic cross-sectional view of FIG. 8 at position AA, and FIG. 10 is a schematic cross-sectional view of FIG. 8 at position BB.
  • specific steps of forming a plurality of first trenches 81 in the semiconductor block 41 include:
  • a dielectric layer located on the side of the semiconductor block 41 is formed on the substrate 40.
  • the dielectric layer includes a plurality of first etching windows 80, and the plurality of first etching windows 80 are arranged at intervals along the first direction D1;
  • the semiconductor block 41 is laterally etched along the first etching window 80 to form a plurality of first trenches 81 spaced apart along the first direction D1 in the semiconductor block 41 , and the semiconductor remains between adjacent first trenches 81 Block 41 serves as semiconductor layer 82 .
  • the number of openings 42 is multiple, and the semiconductor block 41 is located between two adjacent openings 42 along the third direction;
  • the specific steps of forming the dielectric layer located on the side of the semiconductor block 41 on the bottom 40 include:
  • Dielectric layers are formed on opposite sides of the semiconductor block 41 in the third direction D3.
  • the dielectric layers located on the opposite sides of the semiconductor block 41 in the third direction D3 are symmetrically distributed along the central plane of the semiconductor block 41, and the central plane is perpendicular to The third direction D3 is parallel to the top surface of the substrate 40 .
  • the specific steps of forming a dielectric layer located on the side of the semiconductor block 41 on the substrate 40 include:
  • a first dielectric layer 51 and a second dielectric layer 52 are formed on the side of the semiconductor block 41, and the first dielectric layer 51 and the second dielectric layer 52 are alternately stacked along the first direction D1, as shown in Figure 5;
  • the first dielectric layer 51 is removed to form a first etching window 80 between the adjacent second dielectric layers 52 along the first direction D1.
  • the second dielectric layer 52 and the first etching window 80 constitute a dielectric layer.
  • a selective atomic layer deposition process may be used to alternately deposit the first dielectric material and the second dielectric material in the opening 42 to form the first dielectric layer 51 and the second dielectric layer 51 alternately stacked along the first direction D1 in the opening 42 .
  • Dielectric layer 52 Using a selective atomic layer deposition process to form the first dielectric layer 51 and the second dielectric layer 52 can control the first dielectric layer 51 and the second dielectric layer 52 to only be stacked alternately along the first direction D1 and not along other directions ( For example, the third direction D3) is stacked to ensure that the first trench 81 can be accurately formed later through a self-alignment process.
  • the material of the first dielectric layer 51 may be an oxide material (such as silicon dioxide), and the material of the second dielectric layer 52 may be a nitride material (such as silicon nitride).
  • the semiconductor block 41 Since the first dielectric layer 51 is subsequently removed to form the first etching window 80 between the adjacent second dielectric layers 52, and then the semiconductor block 41 is self-aligned and etched along the first etching window 80. Therefore, by adjusting the thickness of the first dielectric layer 51 and the second dielectric layer 52 , and the number of alternately stacked layers of the first dielectric layer 51 and the second dielectric layer 52 , it is possible to realize the adjustment of the first trench 81 along the first direction. The width of D1, the thickness of the semiconductor layer 82 along the first direction D1, and the number of semiconductor layers 82 formed after etching are adjusted, thereby further improving the flexibility of the semiconductor structure manufacturing process.
  • a deep etching process and a lateral etching process are combined to form a plurality of semiconductor layers 82 spaced and stacked along the first direction D1, thereby reducing or even avoiding the use of deposition or epitaxial processes to form a plurality of semiconductor layers 82 along the first direction D1.
  • the internal stress problem caused by the stacked semiconductor layers improves the crystal orientation consistency between multiple semiconductor layers, thereby reducing defects (such as crystal orientation defects or impurity defects) within the final formed semiconductor structure and improving Yield of semiconductor structures.
  • this specific embodiment uses a self-aligned etching process to etch the semiconductor block 41 to form a plurality of semiconductor layers 82, and can flexibly adjust the number and thickness of the semiconductor layers 82, which not only helps to improve the semiconductor structure manufacturing process Controllability and flexibility, and lays the foundation for improving the integration of semiconductor structures and storage density.
  • the following steps are also included:
  • a first support pillar 71 is formed that penetrates the semiconductor block 41 at least along the first direction D1, as shown in FIG. 7 .
  • the specific steps of forming the support pillar 71 penetrating the semiconductor block 41 at least along the first direction D1 include:
  • first support hole 61 penetrating the semiconductor block 41 along the first direction D1, and simultaneously form a second support hole 62 penetrating the first dielectric layer 51 and the second dielectric layer 52 along the first direction D1, as shown in Figure 6;
  • a first support post 71 is formed in the first support hole 61 and a second support post 72 is formed in the second support hole 62 at the same time, as shown in FIG. 7 .
  • the second mask layer 60 may be formed on the top surface of the semiconductor block 41, and in the second mask layer 60 There is a third etching window exposing the semiconductor block 41 and a fourth etching window exposing the dielectric layer.
  • the semiconductor block 41 is etched downward along the third etching window, and the first dielectric layer 51 and the second dielectric layer 52 are etched downward along the fourth etching window to form a third portion of the semiconductor block 41 exposing the substrate 40 .
  • a support hole 61 and a second support hole 62 exposing the substrate 40 are simultaneously formed in the first dielectric layer 51 and the second dielectric layer 52, as shown in FIG. 6 .
  • the second support post 72 supports the hole 62 as shown in FIG. 7 .
  • the first support pillar 71 is used to support the semiconductor block 41 to prevent the semiconductor block 41 from tipping or collapsing during the lateral etching process.
  • the second support pillar 72 is used to support the second dielectric layer 52 to prevent the second dielectric layer 52 from collapsing during the removal of the first dielectric layer 51 to ensure smooth progress of the lateral etching process.
  • the first support pillar 71 Located in the middle or end of the semiconductor block 41;
  • the second support pillar 72 is located in the middle or end of the first dielectric layer 51 and the second dielectric layer 52 .
  • the first support pillar 71 is located in the middle of the semiconductor block 41
  • the second support pillar 72 is located in the middle of the first dielectric layer 51 and the second dielectric layer 52
  • the two second support pillars 72 They are symmetrically distributed on opposite sides of the first support column 71 along the third direction D3.
  • multiple layers are formed in the semiconductor block 41 Before the first trench 81, the following steps are also included:
  • a protective layer covering the top surface of the semiconductor block 41 is formed.
  • the material of the protective layer may be the same as the material of the second dielectric layer 52 , for example, both are nitride materials (eg, silicon nitride).
  • the material of the initial substrate 20 is silicon; the specific steps of forming a plurality of first trenches 81 in the semiconductor block 41 include:
  • the following first cycle steps are performed at least once until the first trench 81 penetrating the semiconductor block 41 in a direction parallel to the top surface of the substrate 40 is formed.
  • the first cycle steps include:
  • the first etchant is used to etch the semiconductor block 41 along the first etching window 80, and the etching rate of the first etchant in the ⁇ 100> crystal direction is smaller than the etching rate in other crystal directions;
  • Silicon material is epitaxially grown along the surface of the semiconductor block 41 exposed by the first etching window 80 .
  • specific steps of using the first etchant to etch the semiconductor block 41 along the first etching window 80 include:
  • the semiconductor block 41 is etched along the first etching window 80 using an atomic layer etching process.
  • Crystal orientation includes six crystal orientations, namely crystal orientation [100], crystal orientation [010], crystal orientation [001] and the opposite crystal orientation of the above three. It can be understood that the [100] crystal orientation is the same as the crystal orientation [100].
  • the crystal plane is vertical. Specifically, the vertical direction of the top surface of the substrate 40 is the ⁇ 100> crystal direction, and the vertical direction of the side surface of the semiconductor block 41 exposed by the first etching window 80 is the ⁇ 100> crystal direction.
  • the semiconductor block 41 of silicon material by selecting an appropriate first etchant, different etching selectivity ratios between different crystallographic directions of silicon can be achieved, that is, the semiconductor block 41 can be etched in all directions.
  • Opposite etching For example, during the lateral etching process of the semiconductor block 41 along the first etching window 80 , atoms with ⁇ 100> crystal orientation in the semiconductor block 41 need to be retained, and atoms with non- ⁇ 100> crystal orientation need to be etched. Etching away means that the ⁇ 100 ⁇ crystal plane group atoms in the semiconductor block 41 are retained, but the non- ⁇ 100 ⁇ crystal plane group atoms need to be etched away. Among them, the non- ⁇ 100> crystal orientation includes the ⁇ 110> crystal orientation and the ⁇ 111> crystal orientation. Therefore, the etching rate of the ⁇ 100> crystal orientation by the first etchant is smaller than the etching rate of other crystal orientations.
  • the etching rate of the ⁇ 100> crystal direction by the first etchant is lower than that of other crystal directions, during the lateral etching process, the ⁇ 100> crystal direction will also be partially etched, thus affecting the need to form The thickness and surface roughness of the semiconductor layer 82.
  • the lateral etching process is suspended, and silicon is epitaxially grown along the surface of the semiconductor block 41 exposed by the first etching window 80
  • the material is preset for a second time, thereby improving the flatness of the surface of the finally formed semiconductor layer 82 while preventing the thickness of the end of the semiconductor layer 82 close to the first etching window 80 from being too thin, thereby increasing the overall thickness of the semiconductor layer 82 uniformity.
  • the next first cycle step is performed, that is, the semiconductor block 41 is etched along the first etching window 80 again, and after the etching process continues for a first preset time, the semiconductor block 41 exposed along the first etching window 80 is Silicon material is epitaxially grown on the surface of substrate 41 for a second preset time, that is, etching and epitaxial growth processes are alternately performed until a first trench 81 is formed that penetrates the semiconductor block 41 in a direction parallel to the top surface of the substrate 40.
  • suspended semiconductor layers 82 are formed (that is, adjacent semiconductor layers 82 along the first direction D1 are completely physically isolated by the first trench 81).
  • the relative sizes of the first preset time and the second preset time, as well as the number of times the first cycle step is performed, can be selected according to actual needs, for example, according to the specific type of the first etchant and the semiconductor layer to be formed.
  • the thickness of 82 and other factors are selected, and this specific embodiment does not limit this.
  • the first etchant includes tetramethylammonium hydroxide (TMAH).
  • TMAH tetramethylammonium hydroxide
  • the first etchant includes tetramethylammonium hydroxide with a volume percentage of 15% to 30% (eg, 25%).
  • the first etchant further includes an additive, and the additive is any one of isopropyl alcohol, butanol, and tritium, or a combination of two or more.
  • additives may also be added to the first etchant. Any one or a combination of two or more of propanol, butanol, and tritium.
  • the ratio between tetramethylammonium hydroxide and additives in the first etchant and the etching temperature when laterally etching the semiconductor block 41 the etching rate between different crystal planes and the etching rate can be more accurately controlled.
  • the surface roughness of the formed semiconductor layer 82 is adjusting the ratio between tetramethylammonium hydroxide and additives in the first etchant and the etching temperature when laterally etching the semiconductor block 41.
  • the first etchant may include tetramethylammonium hydroxide with a volume fraction of 19% to 23% and isopropyl alcohol with a volume fraction of 10% to 25%; alternatively, the first etchant may include a volume fraction of It is 19% to 23% tetramethylammonium hydroxide and the volume fraction is 4% to 15% butanol; alternatively, the first etching agent may include 19% to 23% volume fraction of tetramethylammonium hydroxide.
  • the first etchant may include tetramethylammonium hydroxide with a volume fraction of 19% to 23% , butanol with a volume fraction of 4% to 15%, and tritium with a volume fraction of 0.1% to 0.2%.
  • the material of the initial substrate 20 is silicon; the specific steps of forming the plurality of first trenches 81 in the semiconductor block 41 include:
  • the following second cycle steps are performed at least once until the first trench 81 penetrating the semiconductor block 41 in a direction parallel to the top surface of the substrate 40 is formed.
  • the second cycle steps include:
  • the semiconductor block 41 is converted along the first etching window 80 to form a conversion layer, and the conversion processing rate of the ⁇ 100> crystal orientation is smaller than the conversion processing rate of other crystal orientations;
  • the conversion layer is etched along the first etching window 80 using a second etchant, and the etching rate of the conversion layer by the second etchant is greater than the etching rate of silicon.
  • the conversion treatment is an oxidation treatment
  • the conversion layer is a silicon oxide layer.
  • Figure 13 is a schematic diagram of the relationship between the oxide layer thickness of different crystal orientations and the oxidation time during the oxidation process of silicon in a specific embodiment of the present disclosure.
  • the first curve 1301 in Figure 13 represents ⁇ 100> during the oxidation process of silicon at 900°C.
  • the thickness of the oxide layer formed by the silicon in the crystal orientation changes with the oxidation time.
  • the second curve 1311 represents the thickness of the oxide layer generated by the silicon with the ⁇ 110> crystal orientation during the oxidation process of silicon at 900°C.
  • the change curve with the oxidation time is The third curve 1321 represents the thickness of the oxide layer generated by silicon with the ⁇ 111> crystal orientation during the oxidation process of silicon at 900°C, as a function of oxidation time.
  • the fourth curve 1302 represents the silicon with the ⁇ 100> crystal orientation during the oxidation process of silicon at 1000°C.
  • the thickness of the generated oxide layer changes with the oxidation time.
  • the fifth curve 1312 represents the variation of the thickness of the oxide layer with the ⁇ 110> crystal orientation during the oxidation process of silicon at 1000°C.
  • the sixth curve 1322 represents the change of the thickness of the oxide layer with the oxidation time. During the oxidation of silicon at 1000°C, the thickness of the oxide layer generated by the ⁇ 111> crystalline silicon changes with the oxidation time.
  • the thickness of the oxide layer formed by silicon with ⁇ 111> crystal orientation is greater than the thickness of the oxide layer formed by silicon with ⁇ 110> crystal orientation
  • the thickness of the oxide layer formed by silicon with ⁇ 110> crystal orientation is The thickness of the oxide layer is greater than the thickness of the oxide layer generated by silicon with the ⁇ 100> crystal orientation, that is, the oxidation rate of silicon with the ⁇ 111> crystal orientation is greater than the oxidation rate of silicon with the ⁇ 110> crystal orientation, and the silicon with the ⁇ 110> crystal orientation
  • the oxidation rate is greater than the oxidation rate of silicon in the ⁇ 100> crystal orientation.
  • the silicon oxide layer is removed through a selective etching process, and the etching process continues for a fourth preset time, and then the silicon oxide layer is removed along the first etching window 80 again.
  • the window 80 oxidizes the semiconductor block 41 for a third preset time. Since the oxidation rate of silicon with non- ⁇ 100> crystal orientation is greater than that of silicon with ⁇ 100> crystal orientation, under the same oxidation time and etching time, the amount of silicon with non- ⁇ 100> crystal orientation removed is greater than ⁇ 100 >The amount of silicon in the crystal orientation.
  • a first trench 81 penetrating the semiconductor block 41 in a direction parallel to the top surface of the substrate 40 is formed, thereby forming a suspended semiconductor layer 82 (ie, adjacent along the first direction D1
  • the semiconductor layer 82 is completely physically isolated by the first trench 81).
  • those skilled in the art can select the relative sizes of the third preset time and the fourth preset time and the number of executions of the second cycle step according to actual needs, for example, according to the type of the second etchant selected, The thickness of the semiconductor layer 82 to be formed is selected based on factors such as the thickness.
  • the following steps are also included:
  • FIG. 11 is a semiconductor Figure 12 is a schematic cross-sectional view of the structure at CC position in Figure 11.
  • the following steps are also included:
  • the sacrificial material is filled in the first trench 81 to form a sacrificial layer located between adjacent semiconductor layers 82.
  • the sacrificial layers and the semiconductor layers 82 are alternately stacked along the first direction D1 to form a stacked layer.
  • the material of the sacrificial layer may be, but is not limited to, SiGe or other insulating dielectric materials (such as silicon dioxide or silicon nitride).
  • the following steps are also included:
  • the stacked layer is etched to form a plurality of second trenches spaced apart along the second direction D2.
  • the plurality of second trenches separate the semiconductor layer 82 into a plurality of semiconductor pillars 121 spaced apart along the second direction D2.
  • the two directions D2 are parallel to the top surface of the substrate 40, and the second direction D2 intersects the third direction D3;
  • a channel region is formed in the semiconductor pillar 121 of the transistor region, a source region and a drain region distributed on opposite sides of the channel region along the third direction D3, and a word line 111 covering the surface of the channel region.
  • the source region It is adjacent to the bit line area, and the drain area is adjacent to the capacitor area;
  • a conductive layer 123 covering the surface of the semiconductor pillar 121 in the capacitor region, a dielectric layer 122 covering the surface of the conductive layer 123, and an upper electrode layer 112 covering the surface of the dielectric layer 122;
  • a bit line 110 is formed in the bit line trench, and the bit line 110 is electrically connected to the source region, see FIG. 11 and FIG. 12 .
  • the semiconductor structure formed in this specific embodiment may be, but is not limited to, DRAM.
  • the following description takes the semiconductor structure as DRAM as an example.
  • the semiconductor structure includes a word line and a bit line, the word line extends along a first direction and the bit line extends along a second direction, or the word line extends along the second direction and the bit line extends along the first direction.
  • a transistor region, and a capacitor region and a bit line region distributed on opposite sides of the transistor region along the third direction D3 may be defined in the stacked layer.
  • each semiconductor layer 82 is separated into a plurality of semiconductor pillars 121 arranged at intervals along the second direction D2, thereby forming a plurality of semiconductor pillars stacked in a three-dimensional array along the first direction D1 and the second direction D2. 121.
  • a channel region is formed in the semiconductor pillar 121 of the transistor region, and source regions and drain regions distributed on opposite sides of the channel region along the third direction D3.
  • a word line 111 extending along the second direction D2 and covering a plurality of channel regions spaced apart along the second direction D2 is formed in the transistor region.
  • the gate dielectric layer 120 may also be formed through an in-situ oxidation process (eg, an in-situ water vapor oxidation process).
  • a capacitor is formed in the capacitive region.
  • the capacitor includes a semiconductor pillar 121 located in the capacitance area, a conductive layer 123 covering the surface of the semiconductor pillar 121, a dielectric layer 122 covering the surface of the conductive layer 123, and an upper electrode layer 112 covering the surface of the dielectric layer 122, wherein the capacitance area
  • the semiconductor pillar 121 and the conductive layer 123 jointly serve as the lower electrode layer of the capacitor.
  • the capacitive region may also include a common electrode layer 113 covering the plurality of capacitors.
  • the bit line 110 is formed in the bit line region of the stacked layer.
  • the word line 111 and the bit line 110 may be made of the same material, for example, both are metal tungsten.
  • the above description takes the horizontal word line structure and the vertical bit line structure as an example. In other embodiments, a vertical word line structure and a horizontal bit line structure may also be formed.
  • This specific implementation method is explained by taking two transistors spaced apart along the third direction D3 sharing a bit line 110 as an example.
  • a bit line electrically connected to each transistor may also be provided.
  • This specific embodiment also provides a semiconductor structure formed by the method of forming a semiconductor structure as shown in FIGS. 1 to 12 .
  • the structure of the semiconductor structure formed in this specific embodiment can be seen in Figures 2-12.
  • the semiconductor structure in this specific embodiment may be, but is not limited to, DRAM.
  • the semiconductor structure includes:
  • the plurality of semiconductor layers 82 are spaced apart along the first direction D1, and the first direction D1 is perpendicular to the top surface of the substrate 40; the plurality of semiconductor layers 82 and the substrate 40 have the same crystal orientation.
  • the semiconductor layer 82 includes a plurality of active regions spaced apart along the second direction D2, the active regions include a channel region, and sources distributed on opposite sides of the channel region along the third direction D3.
  • the electrode region and the drain region, and the crystallographic directions of the multiple active regions in the semiconductor layer 82 are all the same.
  • the substrate 40 includes a plurality of semiconductor layers 82 stacked sequentially along the first direction D1, and each semiconductor layer 82 has the same crystal orientation as the substrate 40, and the crystal orientations between the semiconductor layers 82 are also the same. same.
  • this embodiment can reduce the difference in crystal orientation between semiconductor layers and ensure the consistency of crystal orientation between semiconductor layers.
  • the active area of the semiconductor layer 82 is used to form memory cells, and the intra-layer crystal orientation consistency of the semiconductor layer 82 ensures the performance consistency of multiple subsequently formed memory cells spaced apart along the second direction D2, improving the performance of the memory cells. Improve the performance consistency and performance stability of semiconductor structures.
  • the semiconductor structure further includes:
  • the first support column 71 penetrates the stacked structure along the first direction D1, and the first support column 71 is located between two adjacent storage units along the second direction D2.
  • the first support pillar 71 is used to support the semiconductor block 41 during the process of etching the semiconductor block 41 using a lateral etching process.
  • the semiconductor structure and its formation method provided by some embodiments in this specific implementation mode first form a semiconductor block by etching the initial substrate, and then etching the semiconductor block laterally, thereby dividing the semiconductor block into two parts along the top surface perpendicular to the substrate.
  • Multiple semiconductor layers are spaced apart in the direction of the substrate, so there is no need to use deposition or epitaxial processes to form multiple semiconductor layers spaced apart in the direction perpendicular to the substrate, reducing or even eliminating the risk of layer-by-layer deposition.
  • Defect problems such as stress, and the multiple semiconductor layers formed have the same crystal orientation as the substrate, which reduces defects such as lattice deformation and impurity introduction in the semiconductor layer, thereby increasing the manufacturing yield of the semiconductor structure and improving the quality of the semiconductor electrical properties of the structure.
  • some embodiments of this specific embodiment form a first dielectric layer and a second dielectric layer that are alternately stacked in a direction perpendicular to the top surface of the substrate, and the first etching window is formed by removing the first dielectric layer, that is, by The self-aligned process laterally etches the semiconductor block, which improves the controllability of the position and thickness of a single semiconductor layer, as well as the position and width of the first trench between adjacent semiconductor layers, and improves the flexibility of semiconductor structure manufacturing. sex.

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Abstract

本公开涉及一种半导体结构及其形成方法。所述半导体结构的形成方法包括如下步骤：提供初始衬底；刻蚀所述初始衬底，形成衬底以及凸设于所述衬底的顶面的半导体块；于所述半导体块中形成多个第一沟槽，多个所述第一沟槽将所述半导体块分隔为沿第一方向间隔排布的多个半导体层，所述第一方向垂直于所述衬底的顶面。本公开减少了半导体结构内部的应力等缺陷问题，从而提高了半导体结构的制造良率，改善了半导体结构的电性能。

Description

半导体结构及其形成方法
相关申请引用说明
本申请要求于2022年09月06日递交的中国专利申请号202211084006.2、申请名为“半导体结构及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本公开涉及半导体制造技术领域，尤其涉及一种半导体结构及其形成方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机等电子设备中常用的半导体装置，其由多个存储单元构成，每个存储单元通常包括晶体管和电容器。所述晶体管的栅极与字线电连接、源极与位线电连接、漏极与电容器电连接，字线上的字线电压能够控制晶体管的开启和关闭，从而通过位线能够读取存储在电容器中的数据信息，或者将数据信息写入到电容器中。
为了满足高的存储密度和高的集成度的要求，DRAM等存储器逐渐由二维结构向三维结构发展。具有三维结构的DRAM等半导体结构在制造过程中需要先通过沉积工艺形成半导体层和牺牲层堆叠的超晶格结构，这就不可避免的在导致最终形成的半导体结构中存在应力、晶向差异大以及容易导致杂质的掺入等缺陷，从而引起半导体结构良率的下降，并限制了半导体结构产品性能的进一步提高。
因此，如何避免超晶格结构对半导体结构产品良率的影响，从而改善半导体结构的性能，是当前亟待解决的技术问题。
发明内容
本公开一些实施例提供的半导体结构及其形成方法，用于减少半导体结构中的缺陷，以提高半导体结构的制造良率，并改善半导体结构的性能。
根据一些实施例，本公开提供了一种半导体结构的形成方法，包括如下步骤：
提供初始衬底；
刻蚀所述初始衬底，形成衬底以及凸设于所述衬底的顶面的半导体块；
于所述半导体块中形成多个第一沟槽，多个所述第一沟槽将所述半导体块分隔为沿第一方向间隔排布的多个半导体层，所述第一方向垂直于所述衬底的顶面。
在一些实施例中，刻蚀所述初始衬底之前，还包括如下步骤：
于所述初始衬底中定义有源区域；
注入掺杂离子至所述有源区域。
在一些实施例中，形成衬底以及凸设于所述衬底的顶面的半导体块的步骤包括：
采用深刻蚀工艺自所述初始衬底的顶面刻蚀所述初始衬底，形成至少一个开口，所述开口侧面保留的所述初始衬底作为所述半导体块，所述开口、以及所述半导体块下方保留的所述初始衬底作为所述衬底，所述半导体块位于所述有源区域。
在一些实施例中，于所述半导体块中形成多个第一沟槽的步骤包括：
于所述衬底上形成位于所述半导体块的侧面的介质层，所述介质层中包括多个第一刻蚀窗口，多个所述第一刻蚀窗口沿所述第一方向间隔排布；
沿所述第一刻蚀窗口横向刻蚀所述半导体块，于所述半导体块中形成多个沿所述第一方向间隔排布的所述第一沟槽，相邻的所述第一沟槽之间保留的所述半导体块作为所述半导体层。
在一些实施例中，所述开口的数量为多个，所述半导体块位于沿第三方向相邻的两个所述开口之间；于所述衬底上形成位于所述半导体块的侧面的介质层的步骤包括：
于所述半导体块在所述第三方向上的相对两侧分别形成所述介质层，位于所述半导体块在所述第三方向上相对两侧的所述介质层沿所述半导体块的中心面对称分布，所述中心面垂直于所述第三方向，所述第三方向与所述衬底的顶面平行。
在一些实施例中，于所述衬底上形成位于所述半导体块的侧面的介质层的步骤包括：
于所述半导体块的侧面形成第一介质层和第二介质层，所述第一介质层和所述第二介质层沿所述第一方向交替堆叠；
去除所述第一介质层，形成位于沿所述第一方向相邻的所述第二介质层之间的所述第一刻蚀窗口，所述第二介质层和所述第一刻蚀窗口构成所述介质层。
在一些实施例中，去除所述第一介质层之前，还包括如下步骤：
形成至少沿所述第一方向贯穿所述半导体块的第一支撑柱。
在一些实施例中，形成至少沿所述第一方向贯穿所述半导体块的支撑柱的步骤包括：
形成沿所述第一方向贯穿所述半导体块的第一支撑孔、并同时形成沿所述第一方向贯穿所述第一介质层和所述第二介质层的第二支撑孔；
于所述第一支撑孔内形成所述第一支撑柱、并同时于所述第二支撑孔内形成第二支撑柱。
在一些实施例中，所述第一支撑柱位于所述半导体块的中部或者端部；
所述第二支撑柱位于所述第一介质层和所述第二介质层的中部或者端部。
在一些实施例中，于所述半导体块中形成多个第一沟槽之前，还包括如下步骤：
形成覆盖所述半导体块的顶面的保护层。
在一些实施例中，所述初始衬底的材料为硅；于所述半导体块中形成多个第一沟槽的步骤包括：
进行至少一次如下第一循环步骤，直至形成沿平行于所述衬底的顶面的方向贯穿所述半导体块的所述第一沟槽，所述第一循环步骤包括：
采用第一刻蚀剂沿所述第一刻蚀窗口刻蚀所述半导体块，所述第一刻蚀剂对<100>晶向的刻蚀速率小于其他晶向的刻蚀速率；
沿所述第一刻蚀窗口露出的所述半导体块的表面外延生长硅材料。
在一些实施例中，采用第一刻蚀剂沿所述第一刻蚀窗口刻蚀所述半导体块的步骤包括：
采用原子层刻蚀工艺沿所述第一刻蚀窗口刻蚀所述半导体块。
在一些实施例中，所述第一刻蚀剂包括四甲基氢氧化铵。
在一些实施例中，所述第一刻蚀剂还包括添加剂，所述添加剂为异丙醇、丁醇、氚中的任一种或者两种以上的组合。
在一些实施例中，所述初始衬底的材料为硅；于所述半导体块中形成多个第一沟槽的步骤包括：
进行至少一次如下第二循环步骤，直至形成沿平行于所述衬底的顶面的方向贯穿所述半导体块的所述第一沟槽，所述第二循环步骤包括：
沿所述第一刻蚀窗口对所述半导体块进行转化处理，形成转化层，<100>晶向的转化处理速率小于其他晶向的转化处理速率；
采用第二刻蚀剂沿所述第一刻蚀窗口刻蚀所述转化层，所述第二刻蚀剂对所述转化层的刻蚀速率大于对硅的刻蚀速率。
在一些实施例中，所述转化处理为氧化处理，所述转化层为氧化硅层。
在一些实施例中，于所述半导体块中形成多个第一沟槽之后，还包括如下步骤：
填充牺牲材料于所述第一沟槽内，形成位于相邻的所述半导体层之间的牺牲层，沿所述第一方向交替堆叠的所述牺牲层和所述半导体层组成堆叠层。
在一些实施例中，形成位于相邻的所述半导体层之间的牺牲层之后，还包括如下步骤：
于所述堆叠层中定义晶体管区域、以及沿第三方向分布于所述晶体管区域相对两侧的电容区域和位线区域，所述第三方向平行于所述衬底的顶面；
刻蚀所述堆叠层，形成多个沿第二方向间隔排布的第二沟槽，多个所述第二沟槽将所述半导体层分隔为沿所述第二方向间隔排布的多个半导体柱，所述第二方向平行于所述衬底的顶面，且所述第二方向与所述第三方向相交；
于所述晶体管区域的所述半导体柱中形成沟道区、沿所述第三方向分布于所述沟道区 相对两侧的源极区和漏极区、以及覆盖于所述沟道区表面的字线，所述源极区与所述位线区域相邻，所述漏极区与所述电容区域相邻；
形成覆盖所述电容区域的所述半导体柱表面的导电层、覆盖所述导电层表面的电介质层、以及覆盖所述电介质层表面的上电极层；
去除所述位线区域的所述半导体柱和所述牺牲层，形成位线槽；
形成位线于所述位线槽内，所述位线电连接所述源极区。
根据另一些实施例，本公开还提供了一种半导体结构，包括：
衬底；
沿第一方向间隔排布的多个半导体层，所述第一方向垂直于所述衬底的顶面；多个所述半导体层与所述衬底具有相同的晶向。
在一些实施例中，所述半导体层包括沿第二方向间隔排布的多个有源区域，所述有源区域包括沟道区、以及沿所述第三方向分布于所述沟道区的相对两侧的源极区和漏极区，且所述半导体层中的多个所述有源区域的晶向均相同。
本公开一些实施例提供的半导体结构及其形成方法，先通过刻蚀初始衬底形成半导体块，再对半导体块进行横向刻蚀，从而将所述半导体块分隔为沿垂直于衬底的顶面的方向间隔排布的多个半导体层，从而无需通过沉积或者外延工艺来形成沿垂直于衬底的方向间隔排布的多个半导体层，减少甚至是消除了由于一层一层的沉积导致的应力等缺陷问题，而且形成的多个所述半导体层与衬底具有相同的晶向，减少了半导体层内的晶格变形以及杂质引入等缺陷，从而提高了半导体结构的制造良率，改善了半导体结构的电性能。而且，本公开一些实施例通过形成沿垂直于所述衬底的顶面的方向交替堆叠的第一介质层和第二介质层，通过去除所述第一介质层来形成第一刻蚀窗口，即通过自对准工艺来横向刻蚀所述半导体块，提高了对单个所述半导体层的位置以及厚度、以及相邻所述半导体层之间的第一沟槽的位置以及宽度的可控性，提高了所述半导体结构制造的灵活性。
附图说明
附图1是本公开具体实施方式中半导体结构的形成方法流程图；
附图2-12是本公开具体实施方式在形成半导体结构的过程中主要的工艺结构示意图；
附图13是本公开具体实施方式中硅在氧化过程中不同晶向的氧化层厚度与氧化时间之间的关系示意图。
具体实施方式
下面结合附图对本公开提供的半导体结构及其形成方法的具体实施方式做详细说明。
本具体实施方式提供了一种半导体结构的形成方法，附图1是本公开具体实施方式中半导体结构的形成方法流程图，附图2-12是本公开具体实施方式在形成半导体结构的过程中主要的工艺结构示意图。如图1-图12所示，所述半导体结构的形成方法，包括如下步骤：
步骤S11，提供初始衬底20，如图2所示。
具体来说，初始衬底20可以是但不限于硅衬底，本具体实施方式以初始衬底20为硅衬底为例进行说明。在其他实施例中，初始衬底20还可以为氮化镓、砷化镓、碳化镓、碳化硅或SOI等半导体衬底。
步骤S12，刻蚀初始衬底20，形成衬底40以及凸设于衬底40的顶面的半导体块41，如图4所示。
在一些实施例中，刻蚀初始衬底20之前，还包括如下步骤：
于初始衬底20中定义有源区域；
注入掺杂离子至有源区域。
具体来说，可以在对初始衬底20进行刻蚀之前，通过光掩膜等方式在初始衬底20中定义有源区域，然后采用气相扩散或者等离子体注入方式注入掺杂离子至初始衬底20中的有源区域。有源区域后续至少用于形成存储单元中的晶体管。其中，注入的掺杂离子可以是N型离子，也可以是P型离子，本领域技术人员可以根据实际需要进行选择。图2中的 箭头表示掺杂离子注入初始衬底20的方向。
在一些实施例中，形成衬底40以及凸设于衬底40的顶面的半导体块41的具体步骤包括：
采用深刻蚀工艺自初始衬底20的顶面刻蚀初始衬底20，形成至少一个开口42，开口42侧面保留的初始衬底20作为半导体块41，开口42、以及半导体块41下方保留的初始衬底20作为衬底40，半导体块41位于有源区域。
具体来说，形成第一掩膜层30于初始衬底20的顶面，并对第一掩膜层30进行图案化处理，以在第一掩膜层30中形成暴露初始衬底20的顶面的第二刻蚀窗口。之后，采用深刻蚀工艺、沿第二刻蚀窗口向下刻蚀初始衬底20，形成开口42。开口42侧面保留的初始衬底20作为半导体块41，开口42、以及半导体块41下方保留的初始衬底20作为衬底40。半导体块41凸出设置于衬底40的顶面，从而由半导体块41和衬底40共同形成台阶状结构。在一示例中，为了提高初始衬底20的利用率，可以仅形成一个开口42，半导体块41位于开口42的侧面。在另一示例中，为了提高后续刻蚀半导体块41的刻蚀效率，并进一步简化半导体结构的制造工艺，开口42的数量可以为多个，例如图4中所示的开口42的数量为两个、且沿第三方向D3对称分布于半导体块41的相对两侧，其中，第三方向D3平行于衬底40的顶面。本具体实施方式中的衬底40的顶面是指衬底40朝向半导体块41的表面。
步骤S13，于半导体块41中形成多个第一沟槽81，多个第一沟槽81将半导体块41分隔为沿第一方向D1间隔排布的多个半导体层82，第一方向D1垂直于衬底40的顶面，如图8、图9和图10所示，其中，图9是图8在AA位置的截面示意图，图10是图8在BB位置的截面示意图。
在一些实施例中，于半导体块41中形成多个第一沟槽81的具体步骤包括：
于衬底40上形成位于半导体块41的侧面的介质层，介质层中包括多个第一刻蚀窗口80，多个第一刻蚀窗口80沿第一方向D1间隔排布；
沿第一刻蚀窗口80横向刻蚀半导体块41，于半导体块41中形成多个沿第一方向D1间隔排布的第一沟槽81，相邻的第一沟槽81之间保留的半导体块41作为半导体层82。
为了提高刻蚀效率、且更好的实现刻蚀对准，在一些实施例中，开口42的数量为多个，半导体块41位于沿第三方向相邻的两个开口42之间；于衬底40上形成位于半导体块41的侧面的介质层的具体步骤包括：
于半导体块41在第三方向D3上的相对两侧分别形成介质层，位于半导体块41在第三方向D3上相对两侧的介质层沿半导体块41的中心面对称分布，中心面垂直于第三方向D3，第三方向D3与衬底40的顶面平行。
在一些实施例中，于衬底40上形成位于半导体块41的侧面的介质层的具体步骤包括：
于半导体块41的侧面形成第一介质层51和第二介质层52，第一介质层51和第二介质层52沿第一方向D1交替堆叠，如图5所示；
去除第一介质层51，形成位于沿第一方向D1相邻的第二介质层52之间的第一刻蚀窗口80，第二介质层52和第一刻蚀窗口80构成介质层。
具体来说，可以采用选择性原子层沉积工艺于开口42中交替沉积第一介质材料和第二介质材料，以于开口42内形成沿第一方向D1交替堆叠的第一介质层51和第二介质层52。采用选择性原子层沉积工艺来形成第一介质层51和第二介质层52，可以控制第一介质层51和第二介质层52仅沿第一方向D1交替堆叠、而不会沿其他方向(例如第三方向D3)堆叠，从而确保后续能够通过自对准工艺准确的形成第一沟槽81。其中，为了便于后续选择性的去除第一介质层51、从而形成第一刻蚀窗口80，第一介质层51和第二介质层52之间应具有较高的刻蚀选择比，例如第一介质层51与第二介质层52之间的刻蚀选择比大于3。在一示例中，第一介质层51的材料可以为氧化物材料(例如二氧化硅)，第二介质层52的材料为氮化物材料(例如氮化硅)。
由于后续是通过去除第一介质层51、形成位于相邻的第二介质层52之间的第一刻蚀窗口80，再沿第一刻蚀窗口80对半导体块41进行自对准刻蚀，因此，通过调整第一介质层51的厚度和第二介质层52的厚度、以及第一介质层51与第二介质层52交替堆叠的层数，可以实现对第一沟槽81沿第一方向D1的宽度、半导体层82沿第一方向D1的厚度、以及刻蚀后形成的半导体层82的数量的调整，从而进一步提高了半导体结构制造工艺的灵活性。
本具体实施方式通过深刻蚀工艺与横向刻蚀工艺结合来形成沿第一方向D1间隔堆叠的多个半导体层82，从而能够减少甚至是避免采用沉积或者外延工艺来形成多个沿第一方向D1间隔堆叠的半导体层所带来的内部应力问题，提高了多个半导体层之间的晶向一致性，从而减少了最终形成的半导体结构内部的缺陷(例如晶向缺陷或者杂质缺陷)，改善了半导体结构的良率。另外，本具体实施方式通过自对准刻蚀工艺来刻蚀半导体块41、从而形成多个半导体层82，且能够灵活调整半导体层82的数量和厚度，不仅有助于提高半导体结构制造工艺的可控性和灵活性，而且为提高半导体结构的集成度、以及存储密度奠定了基础。
为了提高半导体块41在横向刻蚀过程中的结构稳定性，避免刻蚀过程中半导体块41出现倾倒或者坍塌，在一些实施例中，去除第一介质层51之前，还包括如下步骤：
形成至少沿第一方向D1贯穿半导体块41的第一支撑柱71，如图7所示。
在一些实施例中，形成至少沿第一方向D1贯穿半导体块41的支撑柱71的具体步骤包括：
形成沿第一方向D1贯穿半导体块41的第一支撑孔61、并同时形成沿第一方向D1贯穿第一介质层51和第二介质层52的第二支撑孔62，如图6所示；
于第一支撑孔61内形成第一支撑柱71、并同时于第二支撑孔62内形成第二支撑柱72，如图7所示。
具体来说，在形成沿第一方向D1交替堆叠的第一介质层51和第二介质层52之后，可以形成第二掩膜层60于半导体块41的顶面，第二掩膜层60中具有暴露半导体块41的第三刻蚀窗口、以及暴露介质层的第四刻蚀窗口。沿第三刻蚀窗口向下刻蚀半导体块41、同时沿第四刻蚀窗口向下刻蚀第一介质层51和第二介质层52，以于半导体块41中形成暴露衬底40的第一支撑孔61、并同时于第一介质层51和第二介质层52中形成暴露衬底40的第二支撑孔62，如图6所示。沉积氮化物(例如氮化硅)等绝缘介质材料于第一支撑孔61内和第二支撑孔62内，形成填充满第一支撑孔61的第一支撑柱71、并同时形成填充满第二支撑孔62的第二支撑柱72，如图7所示。第一支撑柱71用于支撑半导体块41，避免半导体块41在横向刻蚀过程中出现倾倒或者坍塌。第二支撑柱72用于支撑第二介质层52，避免在去除第一介质层51的过程中第二介质层52出现坍塌，以确保横向刻蚀工艺的顺利进行。
为了在对半导体块41和第二介质层52进行稳定支撑的同时，减少对半导体块41的面积的占用、以及对第一刻蚀窗口空间的占用，在一些实施例中，第一支撑柱71位于半导体块41的中部或者端部；
第二支撑柱72位于第一介质层51和第二介质层52的中部或者端部。
举例来说，如图7所示，第一支撑柱71位于半导体块41的中部，第二支撑柱72位于第一介质层51和第二介质层52的中部，且两个第二支撑柱72沿第三方向D3对称分布于第一支撑柱71的相对两侧。
为了避免在横向刻蚀半导体块41的过程中对半导体块41的顶面造成损伤，确保形成的最顶层的半导体层82顶面的平坦，在一些实施例中，于半导体块41中形成多个第一沟槽81之前，还包括如下步骤：
形成覆盖半导体块41的顶面的保护层。在一示例中，保护层的材料可以与第二介质层52的材料相同，例如均为氮化物材料(例如氮化硅)。
在一些实施例中，初始衬底20的材料为硅；于半导体块41中形成多个第一沟槽81的 具体步骤包括：
进行至少一次如下第一循环步骤，直至形成沿平行于衬底40的顶面的方向贯穿半导体块41的第一沟槽81，第一循环步骤包括：
采用第一刻蚀剂沿第一刻蚀窗口80刻蚀半导体块41，第一刻蚀剂对<100>晶向的刻蚀速率小于其他晶向的刻蚀速率；
沿第一刻蚀窗口80露出的半导体块41的表面外延生长硅材料。
在一些实施例中，采用第一刻蚀剂沿第一刻蚀窗口80刻蚀半导体块41的具体步骤包括：
采用原子层刻蚀工艺沿第一刻蚀窗口80刻蚀半导体块41。
<100>晶向包括六个晶向，分别为晶向[100]、晶向[010]、晶向[001]及上述三者的相反晶向，可以理解的是，[100]晶向与(100)晶面垂直。具体来说，衬底40的顶面的垂直方向为<100>晶向，第一刻蚀窗口80露出的半导体块41的侧面的垂直方向为<100>晶向。在对硅材料的半导体块41进行横向刻蚀的过程中，通过选择合适的第一刻蚀剂，可以使得硅不同晶向之间具有不同的刻蚀选择比，即对半导体块41进行各向异性刻蚀。举例来说，在沿第一刻蚀窗口80对半导体块41进行横向刻蚀的过程中，需要保留半导体块41中<100>晶向的原子、而需要将非<100>晶向的原子刻蚀掉，即，保留半导体块41中{100}晶面族原子、而需要将非{100}晶面族原子刻蚀掉。其中，非<100>晶向包括<110>晶向和<111>晶向，因此，第一刻蚀剂对<100>晶向的刻蚀速率小于其他晶向的刻蚀速率。虽然第一刻蚀剂对<100>晶向的刻蚀速率小于其他晶向的刻蚀速率，在横向刻蚀过程中，也会对<100>晶向进行部分刻蚀，从而影响需要形成的半导体层82的厚度和表面粗糙度。为了解决这一问题，在沿第一刻蚀窗口80刻蚀半导体块41第一预设时间之后，暂停横向刻蚀工艺，并沿第一刻蚀窗口80露出的半导体块41的表面外延生长硅材料第二预设时间，从而在提高最终形成的半导体层82的表面的平坦度的同时，防止半导体层82靠近第一刻蚀窗口80的端部的厚度过薄，从而提高半导体层82整体厚度的均匀性。之后，再执行下一次第一循环步骤，即再次沿第一刻蚀窗口80刻蚀半导体块41，并在刻蚀工艺持续第一预设时间之后，沿第一刻蚀窗口80露出的半导体块41的表面外延生长硅材料，并持续第二预设时间，即交替实施刻蚀与外延生长工艺，直至形成沿平行于衬底40的顶面的方向贯穿半导体块41的第一沟槽81，从而形成悬空的半导体层82(即沿第一方向D1相邻的半导体层82通过第一沟槽81完全物理隔离)。其中，第一预设时间和第二预设时间的相对大小、以及第一循环步骤执行的次数，可以根据实际需要进行选择，例如根据第一刻蚀剂的具体类型、所需形成的半导体层82的厚度等因素进行选择，本具体实施方式对此不做限定。
为了进一步提高硅中<100>晶向与硅中非<100>晶向之间的刻蚀选择比，从而减小对<100>晶向的损伤，在一些实施例中，第一刻蚀剂包括四甲基氢氧化铵(TMAH)。在一示例中，第一刻蚀剂包括体积百分比为15％～30％(例如25％)的四甲基氢氧化铵。
在一些实施例中，第一刻蚀剂还包括添加剂，添加剂为异丙醇、丁醇、氚中的任一种或者两种以上的组合。
具体来说，为了改善横向刻蚀过程中第一沟槽81内壁(即半导体层82下表面和/或半导体层82上表面)的形貌，还可以在第一刻蚀剂中添加添加剂为异丙醇、丁醇、氚中的任一种或者两种以上的组合。通过调整第一刻蚀剂中四甲基氢氧化铵与添加剂之间的比例、横向刻蚀半导体块41时的刻蚀温度，从而可以更加精确的控制不同晶面之间的刻蚀速率和所形成的半导体层82的表面粗糙度。举例来说，第一刻蚀剂可以包括体积分数为19％～23％的四甲基氢氧化铵和体积分数为10％～25％的异丙醇；或者，第一刻蚀剂包括体积分数为19％～23％的四甲基氢氧化铵和体积分数为4％～15％的丁醇；或者，第一刻蚀剂可以包括体积分数为19％～23％的四甲基氢氧化铵、体积分数为10％～25％的异丙醇、以及体积分数为0.1％～0.2％的氚；或者，第一刻蚀剂可以包括体积分数为19％～23％的四甲基氢氧化铵、体积分数为4％～15％的丁醇、以及体积分数为0.1％～0.2％的氚。
在另一些实施例中，初始衬底20的材料为硅；于半导体块41中形成多个第一沟槽81的具体步骤包括：
进行至少一次如下第二循环步骤，直至形成沿平行于衬底40的顶面的方向贯穿半导体块41的第一沟槽81，第二循环步骤包括：
沿第一刻蚀窗口80对半导体块41进行转化处理，形成转化层，<100>晶向的转化处理速率小于其他晶向的转化处理速率；
采用第二刻蚀剂沿第一刻蚀窗口80刻蚀转化层，第二刻蚀剂对转化层的刻蚀速率大于对硅的刻蚀速率。
在一些实施例中，转化处理为氧化处理，转化层为氧化硅层。
以下以转换处理为氧化处理为例进行说明。附图13是本公开具体实施方式中硅在氧化过程中不同晶向的氧化层厚度与氧化时间之间的关系示意图，图13中的第一曲线1301表示硅在900℃氧化过程中<100>晶向的硅生成的氧化层的厚度随氧化时间的变化曲线，第二曲线1311表示硅900℃在氧化过程中<110>晶向的硅生成的氧化层的厚度随氧化时间的变化曲线，第三曲线1321表示硅在900℃氧化过程中<111>晶向的硅生成的氧化层的厚度随氧化时间的变化曲线，第四曲线1302表示硅在1000℃氧化过程中<100>晶向的硅生成的氧化层的厚度随氧化时间的变化曲线，第五曲线1312表示硅1000℃在氧化过程中<110>晶向的硅生成的氧化层的厚度随氧化时间的变化曲线，第六曲线1322表示硅在1000℃氧化过程中<111>晶向的硅生成的氧化层的厚度随氧化时间的变化曲线。
由图13可知，在相同的氧化时间下，<111>晶向的硅生成的氧化层的厚度大于<110>晶向的硅生成的氧化层的厚度、且<110>晶向的硅生成的氧化层的厚度大于<100>晶向的硅生成的氧化层的厚度，即<111>晶向的硅的氧化速率大于<110>晶向的硅的氧化速率、且<110>晶向的硅的氧化速率大于<100>晶向的硅的氧化速率。因此，在沿第一刻蚀窗口80氧化半导体块41第三预设时间之后，通过选择性刻蚀工艺去除氧化硅层，且刻蚀工艺持续第四预设时间之后，再次沿第一刻蚀窗口80氧化半导体块41第三预设时间。由于非<100>晶向的硅的氧化速率大于<100>晶向的硅，因此，在相同的氧化时间及刻蚀时间下，去除掉的非<100>晶向的硅的量大于<100>晶向的硅的量。通过交替进行氧化处理与刻蚀处理，来形成沿平行于衬底40的顶面的方向贯穿半导体块41的第一沟槽81，从而形成悬空的半导体层82(即沿第一方向D1相邻的半导体层82通过第一沟槽81完全物理隔离)。其中，第三预设时间与第四预设时间的相对大小、以及第二循环步骤执行的次数，本领域技术人员可以根据实际需要进行选择，例如根据所选择的第二刻蚀剂的种类、所需要形成的半导体层82的厚度等因素选择。
本具体实施方式是以转化处理为氧化处理为例进行说明，在其他实施例中，本领域技术人员也可以根据实际需要选择其他的转化处理方式，只要能使得在转化处理过程中，<100>晶向的转化处理速率小于其他晶向的转化处理速率即可。
在一些实施例中，于半导体块41中形成多个第一沟槽81之后，还包括如下步骤：
于每个半导体层82中形成沿第二方向D1间隔排布的多个存储单元，第二方向D2平行于衬底41的顶面，如图11和图12所示，其中，图11是半导体结构的俯视结构示意图，图12是图11在CC位置的截面示意图。
在一些实施例中，于半导体块41中形成多个第一沟槽81之后，还包括如下步骤：
填充牺牲材料于第一沟槽81内，形成位于相邻的半导体层82之间的牺牲层，沿第一方向D1交替堆叠的牺牲层和半导体层82组成堆叠层。
其中，牺牲层的材料可以是但不限于SiGe或者其他绝缘介质材料(例如二氧化硅或者氮化硅)。
在一些实施例中，形成位于相邻的半导体层82之间的牺牲层之后，还包括如下步骤：
于堆叠层中定义晶体管区域、以及沿第三方向D3分布于晶体管区域相对两侧的电容区域和位线区域，第三方向D3平行于衬底40的顶面；
刻蚀堆叠层，形成多个沿第二方向D2间隔排布的第二沟槽，多个第二沟槽将半导体层82分隔为沿第二方向D2间隔排布的多个半导体柱121，第二方向D2平行于衬底40的顶面，且第二方向D2与第三方向D3相交；
于晶体管区域的半导体柱121中形成沟道区、沿第三方向D3分布于沟道区相对两侧的源极区和漏极区、以及覆盖于沟道区表面的字线111，源极区与位线区域相邻，漏极区与电容区域相邻；
形成覆盖电容区域的半导体柱121表面的导电层123、覆盖导电层123表面的电介质层122、以及覆盖电介质层122表面的上电极层112；
去除位线区域的半导体柱121和牺牲层，形成位线槽；
形成位线110于位线槽内，位线110电连接源极区，参见图11和图12。
本具体实施方式中形成的半导体结构可以是但不限于DRAM。以下以半导体结构为DRAM为例进行说明。半导体结构包括字线和位线，字线沿第一方向延伸且位线沿第二方向延伸，或者，字线沿第二方向延伸且位线沿第一方向延伸。
在一些实施例中，在形成堆叠层之后，可以于堆叠层中定义晶体管区域、以及沿第三方向D3分布于晶体管区域相对两侧的电容区域和位线区域。通过刻蚀堆叠层，将每个半导体层82分隔为沿第二方向D2间隔排布的多个半导体柱121，从而形成沿第一方向D1和第二方向D2呈三维阵列堆叠的多个半导体柱121。于晶体管区域的半导体柱121中形成沟道区、以及沿第三方向D3分布于沟道区相对两侧的源极区和漏极区。于晶体管区域中形成沿第二方向D2延伸、且覆盖沿第二方向D2间隔排布的多个沟道区的字线111。在形成字线111之前，还可以通过原位氧化工艺(例如原位水汽氧化工艺)形成栅极介质层120。于电容区域形成电容器。电容器包括位于电容区域的半导体柱121、覆盖于半导体柱121表面的导电层123、覆盖于导电层123表面的电介质层122、以及覆盖于电介质层122表面的上电极层112，其中，电容区域的半导体柱121和导电层123共同作为电容器的下电极层。电容区域还可以包括覆盖多个电容器的公共电极层113。于堆叠层的位线区域形成位线110。其中，字线111与位线110的材料可以相同，例如均为金属钨。以上是以水平字线结构与垂直位线结构为例进行说明，在其他实施例中，也可以形成垂直字线结构与水平位线结构。
本具体实施方式是以沿第三方向D3间隔排布的两个晶体管共用一条位线110为例进行说明，在其他实施例中，也可以针对每个晶体管设置一条与其电连接的位线。
本具体实施方式还提供了一种如图1-图12的半导体结构的形成方法形成的半导体结构。本具体实施方式形成的半导体结构的结构可以参见图2-图12。本具体实施方式中的半导体结构可以是但不限于DRAM。如图1-图12所示，半导体结构，包括：
衬底40；
沿第一方向D1间隔排布的多个半导体层82，第一方向D1垂直于衬底40的顶面；多个半导体层82与衬底40具有相同的晶向。
在一些实施例中，半导体层82包括沿第二方向D2间隔排布的多个有源区域，有源区域包括沟道区、以及沿第三方向D3分布于沟道区的相对两侧的源极区和漏极区，且半导体层82中的多个有源区域的晶向均相同。
具体来说，衬底40上包括沿第一方向D1依次堆叠的多个半导体层82，且每个半导体层82都与衬底40具有相同的晶向、各半导体层82之间的晶向也相同。相较于外延生长或者沉积方式形成的半导体层，本具体实施方式能够减小各半导体层之间的晶向差异，确保了各半导体层之间的晶向一致性。另外，半导体层82的有源区域用于形成存储单元，而半导体层82的层内晶向一致性确保了后续形成的多个沿第二方向D2间隔排布的存储单元的性能一致性，提高了半导体结构的性能一致性和性能稳定性。
在一些实施例中，半导体结构还包括：
第一支撑柱71，沿第一方向D1贯穿堆叠结构，且第一支撑柱71位于沿第二方向D2相邻的两个存储单元之间。
具体来说，第一支撑柱71用于在采用横向刻蚀工艺刻蚀半导体块41的过程中支撑半导体块41。
本具体实施方式中一些实施例提供的半导体结构及其形成方法，先通过刻蚀初始衬底形成半导体块，再对半导体块进行横向刻蚀，从而将半导体块分隔为沿垂直于衬底的顶面的方向间隔排布的多个半导体层，从而无需通过沉积或者外延工艺来形成沿垂直于衬底的方向间隔排布的多个半导体层，减少甚至是消除了由于一层一层的沉积导致的应力等缺陷问题，而且形成的多个半导体层与衬底具有相同的晶向，减少了半导体层内的晶格变形以及杂质引入等缺陷，从而提高了半导体结构的制造良率，改善了半导体结构的电性能。而且，本具体实施方式一些实施例通过形成沿垂直于衬底的顶面的方向交替堆叠的第一介质层和第二介质层，通过去除第一介质层来形成第一刻蚀窗口，即通过自对准工艺来横向刻蚀半导体块，提高了对单个半导体层的位置以及厚度、以及相邻半导体层之间的第一沟槽的位置以及宽度的可控性，提高了半导体结构制造的灵活性。
以上所述仅是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本公开原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (20)

  1. 一种半导体结构的形成方法，包括如下步骤：
    提供初始衬底；
    刻蚀所述初始衬底，形成衬底以及凸设于所述衬底的顶面的半导体块；
    于所述半导体块中形成多个第一沟槽，多个所述第一沟槽将所述半导体块分隔为沿第一方向间隔排布的多个半导体层，所述第一方向垂直于所述衬底的顶面。
  2. 根据权利要求1所述的半导体结构的形成方法，其中，刻蚀所述初始衬底之前，还包括如下步骤：
    于所述初始衬底中定义有源区域；
    注入掺杂离子至所述有源区域。
  3. 根据权利要求2所述的半导体结构的形成方法，其中，形成衬底以及凸设于所述衬底的顶面的半导体块的步骤包括：
    采用深刻蚀工艺自所述初始衬底的顶面刻蚀所述初始衬底，形成至少一个开口，所述开口侧面保留的所述初始衬底作为所述半导体块，所述开口、以及所述半导体块下方保留的所述初始衬底作为所述衬底，所述半导体块位于所述有源区域。
  4. 根据权利要求3所述的半导体结构的形成方法，其中，于所述半导体块中形成多个第一沟槽的步骤包括：
    于所述衬底上形成位于所述半导体块的侧面的介质层，所述介质层中包括多个第一刻蚀窗口，多个所述第一刻蚀窗口沿所述第一方向间隔排布；
    沿所述第一刻蚀窗口横向刻蚀所述半导体块，于所述半导体块中形成多个沿所述第一方向间隔排布的所述第一沟槽，相邻的所述第一沟槽之间保留的所述半导体块作为所述半导体层。
  5. 根据权利要求4所述的半导体结构的形成方法，其中，所述开口的数量为多个，所述半导体块位于沿第三方向相邻的两个所述开口之间；于所述衬底上形成位于所述半导体块的侧面的介质层的步骤包括：
    于所述半导体块在所述第三方向上的相对两侧分别形成所述介质层，位于所述半导体块在所述第三方向上相对两侧的所述介质层沿所述半导体块的中心面对称分布，所述中心面垂直于所述第三方向，所述第三方向与所述衬底的顶面平行。
  6. 根据权利要求4所述的半导体结构的形成方法，其中，于所述衬底上形成位于所述半导体块的侧面的介质层的步骤包括：
    于所述半导体块的侧面形成第一介质层和第二介质层，所述第一介质层和所述第二介质层沿所述第一方向交替堆叠；
    去除所述第一介质层，形成位于沿所述第一方向相邻的所述第二介质层之间的所述第一刻蚀窗口，所述第二介质层和所述第一刻蚀窗口构成所述介质层。
  7. 根据权利要求6所述的半导体结构的形成方法，其中，去除所述第一介质层之前，还包括如下步骤：
    形成至少沿所述第一方向贯穿所述半导体块的第一支撑柱。
  8. 根据权利要求7所述的半导体结构的形成方法，其中，形成至少沿所述第一方向贯穿所述半导体块的支撑柱的步骤包括：
    形成沿所述第一方向贯穿所述半导体块的第一支撑孔、并同时形成沿所述第一方向贯穿所述第一介质层和所述第二介质层的第二支撑孔；
    于所述第一支撑孔内形成所述第一支撑柱、并同时于所述第二支撑孔内形成第二支撑柱。
  9. 根据权利要求8所述的半导体结构的形成方法，其中，所述第一支撑柱位于所述半导体块的中部或者端部；
    所述第二支撑柱位于所述第一介质层和所述第二介质层的中部或者端部。
  10. 根据权利要求1所述的半导体结构的形成方法，其中，于所述半导体块中形成多个第一 沟槽之前，还包括如下步骤：
    形成覆盖所述半导体块的顶面的保护层。
  11. 根据权利要求4所述的半导体结构的形成方法，其中，所述初始衬底的材料为硅；于所述半导体块中形成多个第一沟槽的步骤包括：
    进行至少一次如下第一循环步骤，直至形成沿平行于所述衬底的顶面的方向贯穿所述半导体块的所述第一沟槽，所述第一循环步骤包括：
    采用第一刻蚀剂沿所述第一刻蚀窗口刻蚀所述半导体块，所述第一刻蚀剂对<100>晶向的刻蚀速率小于其他晶向的刻蚀速率；
    沿所述第一刻蚀窗口露出的所述半导体块的表面外延生长硅材料。
  12. 根据权利要求11所述的半导体结构的形成方法，其中，采用第一刻蚀剂沿所述第一刻蚀窗口刻蚀所述半导体块的步骤包括：
    采用原子层刻蚀工艺沿所述第一刻蚀窗口刻蚀所述半导体块。
  13. 根据权利要求11所述的半导体结构的形成方法，其中，所述第一刻蚀剂包括四甲基氢氧化铵。
  14. 根据权利要求11所述的半导体结构的形成方法，其中，所述第一刻蚀剂还包括添加剂，所述添加剂为异丙醇、丁醇、氚中的任一种或者两种以上的组合。
  15. 根据权利要求4所述的半导体结构的形成方法，其中，所述初始衬底的材料为硅；于所述半导体块中形成多个第一沟槽的步骤包括：
    进行至少一次如下第二循环步骤，直至形成沿平行于所述衬底的顶面的方向贯穿所述半导体块的所述第一沟槽，所述第二循环步骤包括：
    沿所述第一刻蚀窗口对所述半导体块进行转化处理，形成转化层，<100>晶向的转化处理速率小于其他晶向的转化处理速率；
    采用第二刻蚀剂沿所述第一刻蚀窗口刻蚀所述转化层，所述第二刻蚀剂对所述转化层的刻蚀速率大于对硅的刻蚀速率。
  16. 根据权利要求15所述的半导体结构的形成方法，其中，所述转化处理为氧化处理，所述转化层为氧化硅层。
  17. 根据权利要求1所述的半导体结构的形成方法，其中，于所述半导体块中形成多个第一沟槽之后，还包括如下步骤：
    填充牺牲材料于所述第一沟槽内，形成位于相邻的所述半导体层之间的牺牲层，沿所述第一方向交替堆叠的所述牺牲层和所述半导体层组成堆叠层。
  18. 根据权利要求17所述的半导体结构的形成方法，其中，形成位于相邻的所述半导体层之间的牺牲层之后，还包括如下步骤：
    于所述堆叠层中定义晶体管区域、以及沿第三方向分布于所述晶体管区域相对两侧的电容区域和位线区域，所述第三方向平行于所述衬底的顶面；
    刻蚀所述堆叠层，形成多个沿第二方向间隔排布的第二沟槽，多个所述第二沟槽将所述半导体层分隔为沿所述第二方向间隔排布的多个半导体柱，所述第二方向平行于所述衬底的顶面，且所述第二方向与所述第三方向相交；
    于所述晶体管区域的所述半导体柱中形成沟道区、沿所述第三方向分布于所述沟道区相对两侧的源极区和漏极区、以及覆盖于所述沟道区表面的字线，所述源极区与所述位线区域相邻，所述漏极区与所述电容区域相邻；
    形成覆盖所述电容区域的所述半导体柱表面的导电层、覆盖所述导电层表面的电介质层、以及覆盖所述电介质层表面的上电极层；
    去除所述位线区域的所述半导体柱和所述牺牲层，形成位线槽；
    形成位线于所述位线槽内，所述位线电连接所述源极区。
  19. 一种半导体结构，包括：
    衬底；
    沿第一方向间隔排布的多个半导体层，所述第一方向垂直于所述衬底的顶面；多个所述半导体层与所述衬底具有相同的晶向。
  20. 根据权利要求19所述的半导体结构，其中，所述半导体层包括沿第二方向间隔排布的多个有源区域，所述有源区域包括沟道区、以及沿第三方向分布于所述沟道区的相对两侧的源极区和漏极区，且所述半导体层中的多个所述有源区域的晶向均相同。
PCT/CN2022/129729 2022-09-06 2022-11-04 半导体结构及其形成方法 WO2024050951A1 (zh)

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US20070231997A1 (en) * 2006-03-31 2007-10-04 Doyle Brian S Stacked multi-gate transistor design and method of fabrication
CN104078324A (zh) * 2013-03-29 2014-10-01 中国科学院微电子研究所 堆叠纳米线制造方法
CN105870183A (zh) * 2015-01-19 2016-08-17 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
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US20070231997A1 (en) * 2006-03-31 2007-10-04 Doyle Brian S Stacked multi-gate transistor design and method of fabrication
CN104078324A (zh) * 2013-03-29 2014-10-01 中国科学院微电子研究所 堆叠纳米线制造方法
CN105870183A (zh) * 2015-01-19 2016-08-17 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
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