WO2024050814A1 - 布线基板及其制造方法、电子装置 - Google Patents

布线基板及其制造方法、电子装置 Download PDF

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Publication number
WO2024050814A1
WO2024050814A1 PCT/CN2022/118096 CN2022118096W WO2024050814A1 WO 2024050814 A1 WO2024050814 A1 WO 2024050814A1 CN 2022118096 W CN2022118096 W CN 2022118096W WO 2024050814 A1 WO2024050814 A1 WO 2024050814A1
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Prior art keywords
pad
substrate
type
selected side
pads
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PCT/CN2022/118096
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English (en)
French (fr)
Inventor
张冰
高亮
张小祥
王肖
汤海
秦建伟
Original Assignee
京东方科技集团股份有限公司
合肥京东方瑞晟科技有限公司
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Priority to PCT/CN2022/118096 priority Critical patent/WO2024050814A1/zh
Publication of WO2024050814A1 publication Critical patent/WO2024050814A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a wiring substrate, an electronic device including the wiring substrate, and a method of manufacturing the wiring substrate.
  • Display devices are generally divided into two categories: liquid crystal display devices and organic light-emitting diode display devices.
  • Liquid crystal display devices are widely used due to their advantages such as thinness, lightness, good shock resistance, wide viewing angle, and high contrast.
  • a liquid crystal display device generally includes a display panel and a backlight source, and the backlight source is usually arranged on the non-display side of the display panel to provide a light source for the display operation of the display panel.
  • Characteristics such as contrast, brightness uniformity, and stability of a liquid crystal display device are related to the structure and performance of the backlight.
  • sub-millimeter light-emitting diodes Mini-LEDs
  • Mini-LEDs sub-millimeter light-emitting diodes
  • a wiring substrate including: a substrate; and a plurality of pad groups located on the substrate, each of the plurality of pad groups including at least two pads. Two of the at least two bonding pads that are adjacent in a first direction or a second direction are spaced apart, and the first direction intersects the second direction.
  • Each of the at least two pads includes a plurality of sides, the plurality of sides includes at least one selected side and at least one non-selected side, and any of the pads is along the first direction or the The second direction is adjacent to another bonding pad, the selected side of any bonding pad is the side of the plurality of sides facing another adjacent bonding pad, and the side of any bonding pad facing the phase
  • the distance between the selected side of the adjacent other pad and the selected side of the adjacent other pad facing any of the pads is greater than or equal to 30um and less than 100um.
  • the wiring substrate further includes an insulating layer located on a side of the plurality of pad groups away from the substrate.
  • the insulating layer includes a plurality of first openings, and any one of the plurality of first openings corresponds to one of the plurality of pad groups.
  • any one of the plurality of pad groups includes two pads spaced apart along the first direction or the second direction, and each of the two pads An orthographic projection of an unselected edge on the substrate coincides with a partial outline of the orthographic projection of a corresponding first opening on the substrate.
  • any one of the plurality of pad groups includes four pads arranged in an array along the first direction and the second direction and spaced apart, and the four pad groups are arranged in an array along the first direction and the second direction.
  • the non-selected sides of each of the disks include at least one first non-selected side, and the orthographic projection of the first non-selected side on the substrate is the same as the orthographic projection of the corresponding first opening on the substrate. Partial contours of the orthographic projection coincide.
  • the non-selected side of each bonding pad further includes a second non-selected side, and the orthographic projection of the second non-selected side on the substrate is consistent with the corresponding first opening.
  • the minimum distance between orthographic projection contours on the substrate is 30 to 50um.
  • any one of the plurality of pad groups includes a plurality of pads spaced apart along the first direction or the second direction, and the geometric center of the plurality of pads Lines are connected sequentially in a clockwise direction to form a convex polygon, and the non-selected side of each of the plurality of pads includes at least one first non-selected side, and the first non-selected side is on the substrate.
  • the orthographic projection coincides with the partial contour of the orthographic projection of a corresponding first opening on the substrate.
  • the plurality of pads include a first type of pads and a second type of pads
  • the selected sides of the first type of pads include a first selected side and a second selected side, so The extension direction of the first selected side and the extension direction of the second selected side have an included angle
  • the selected sides of the second type of pad include a third selected side and a fourth selected side, and the The extending direction of the third selected side is parallel to the extending direction of the fourth selected side.
  • the first type of pads and two second types of pads are spaced apart in the first direction and the second direction respectively, and adjacent to the second type of pads Any bonding pad is spaced apart from the second type of bonding pad along the first direction or the second direction.
  • the non-selected side of each first-type pad also includes a second non-selected side, and the orthographic projection of the second non-selected side on the substrate is the same as the corresponding one.
  • the minimum distance between the contours of the orthographic projection of the first opening on the substrate is 30 to 50um.
  • the non-selected side of each second-type bonding pad also includes a third non-selected side
  • the second-type bonding pad is spaced from a first-type bonding pad along the first direction.
  • the distance between the third non-selected side of the second type of pad and the second selected side of the first type of pad in the second direction is greater than 0 and less than or equal to 30um
  • the first The second selected side of the type pad is a selected side of the first type of pad and the second type of pad spaced apart along the second direction facing the first type of pad.
  • the non-selected side of each second-type bonding pad also includes a third non-selected side
  • the second-type bonding pad is spaced from a first-type bonding pad along the second direction.
  • the distance between the third non-selected side of the second type of pad and the first selected side of the first type of pad in the first direction is greater than 0 and less than or equal to 30um
  • the first The first selected side of the type pad is a selected side of the first type of pad facing the first type of pad and the second type of pad spaced apart along the first direction.
  • no other film layer is provided between the layer where the insulation layer is located and the layer where the plurality of pad groups are located.
  • an electronic device which includes the wiring substrate described in any of the previous embodiments and a plurality of electronic devices.
  • the plurality of electronic devices are located on a side of the plurality of pad groups away from the substrate, and any one of the plurality of electronic devices corresponds to one of the plurality of pad groups.
  • each of the plurality of electronic devices includes at least two pins, any one of the at least two pins corresponds to one of the at least two pads, and the electronic device Each pin is connected to a corresponding pad.
  • the ratio of the area of the surface of the pin of each electronic device facing the corresponding one of the pads to the area of the surface of the corresponding one of the pads facing the pin is 0.4 to 1.0.
  • a first orthographic projection of a pin of each electronic device on the substrate at least partially overlaps a second orthographic projection of the corresponding one pad on the substrate, and the third The area where an orthographic projection overlaps with the second orthographic projection constitutes an overlapping area, and the ratio of the area of the overlapping area to the area of the second orthographic projection is greater than or equal to 39%.
  • an insulating layer is located between the plurality of pad groups and the plurality of electronic devices, and any one of the plurality of electronic devices is in contact with a plurality of first openings in the insulating layer.
  • the third orthographic projection of each electronic device on the substrate falls within the fourth orthographic projection of the corresponding first opening on the substrate, and the third orthographic projection of The distance between the contour and the fourth orthographic projection is 20 to 40 ⁇ m.
  • a method of manufacturing an electronic device including: providing a substrate; forming a plurality of pad groups on the substrate, each of the plurality of pad groups including at least two bonding pads; and fixing a plurality of electronic devices on a side of the plurality of bonding pad groups away from the substrate. Any one of the plurality of electronic devices corresponds to one of the plurality of pad groups, each of the plurality of electronic devices includes at least two pins, and the at least two Any one of the pins corresponds to one of the at least two pads, and each pin of the electronic device is connected to a corresponding one of the pads.
  • forming a plurality of pad groups on the substrate includes: applying a conductive layer on the substrate, patterning the conductive layer to form a plurality of signal lines; An insulating layer including a plurality of first openings is formed on a side of the signal lines away from the substrate, and a portion of each of the plurality of signal lines is exposed using the first openings to form the bonding pad.
  • the step of fixing a plurality of electronic devices on a side of the plurality of pad groups away from the substrate includes: aligning each pin of the electronic device with the corresponding one of the pads, Make the first orthographic projection of each pin of the electronic device on the substrate not exceed the second orthographic projection of the corresponding one pad on the substrate; use solder to solder each pin of the electronic device to the corresponding one pad.
  • each pad group includes a plurality of pads spaced apart along the first direction or the second direction, the plurality of pads including a first type of pads, the first type
  • the bonding pad includes a first selected side and a second selected side and a first non-selected side and a second non-selected side, and the extending direction of the first selected side and the extending direction of the second selected side There is an included angle, and the extending direction of the first non-selected side and the extending direction of the second unselected side have an included angle.
  • the step of aligning each pin of the electronic device with the corresponding one pad includes: aligning the first selected side and the second selected side of each first type pad with a corresponding pin.
  • the first side and the second side are respectively aligned in the direction perpendicular to the substrate, and the first non-selected side and the second non-selected side of each first type pad are
  • the orthographic projection of the side on the substrate and the orthographic projection of the third side and the fourth side of a corresponding pin on the substrate are respectively 20 to 50 ⁇ m apart.
  • the plurality of pads further include a second type of pads, the second type of pads including third and fourth selected sides and first and third non-selected sides. Selected side, the extension direction of the third selected side is parallel to the extension direction of the fourth selected side, the extension direction of the first non-selected side is parallel to the extension direction of the third non-selected side parallel.
  • the step of aligning each pin of the electronic device with the corresponding one pad also includes: aligning the third selected side and the fourth selected side of each second type pad with the corresponding one pin.
  • the fifth side and the sixth side of the foot are respectively aligned in a direction perpendicular to the substrate, so that the third non-selected side of each second type pad is in the right direction on the substrate.
  • the projection is 0 to 30 ⁇ m away from the orthographic projection of the seventh side of a corresponding pin on the substrate, and the first non-selected side of each second type pad is on the substrate.
  • the orthographic projection is 20 to 50 ⁇ m away from the orthographic projection of the eighth side of a corresponding pin on the substrate, and the third non-selected side is closer to the pad than the first non-selected side. The center of the group.
  • each pad group includes a central area and a plurality of corner areas surrounding the central area, each of the plurality of corner areas being disposed with at least one first type pad and at least one second type Class pad.
  • it Before aligning each pin of the electronic device with the corresponding one pad, it also includes: placing a net on a side of the plurality of pad groups away from the substrate, the net including a plurality of third Two openings, any second opening among the plurality of second openings corresponds to one of the plurality of corner regions of the plurality of pad groups, and each of the plurality of second openings is located at the corresponding corner region.
  • the orthographic projection on the substrate partially overlaps the orthographic projection on the substrate of at least one first-type pad and at least one second-type pad in a corresponding corner area;
  • the two openings print flux onto the surfaces of the first type of soldering pad and the second type of soldering pad away from the substrate; the stencil is removed.
  • Figure 1 shows a schematic plan view of a light-emitting substrate in the related art
  • FIG. 2 is a schematic plan view of a partial structure of a wiring substrate according to an embodiment of the present disclosure
  • FIG. 3 shows another plan view of a partial structure of a wiring substrate according to an embodiment of the present disclosure
  • FIG. 4 shows yet another schematic plan view of a partial structure of a wiring substrate according to an embodiment of the present disclosure
  • FIG. 5 shows yet another plan view of a partial structure of a wiring substrate according to an embodiment of the present disclosure
  • Figure 6 shows the relative positional relationship between the pads and the pins of the electronic device in the related art after welding
  • FIG. 7 shows a block diagram of an electronic device according to an embodiment of the present disclosure.
  • FIG. 8 shows a schematic cross-sectional view of a partial structure of an electronic device according to an embodiment of the present disclosure
  • FIG. 9 shows a schematic plan view of a partial structure of an electronic device according to an embodiment of the present disclosure.
  • FIG. 10 shows another plan view of a partial structure of an electronic device according to an embodiment of the present disclosure
  • Figure 11 shows the relative positional relationship between the pad and the pin of the electronic device after welding according to an embodiment of the present disclosure
  • FIG. 12 shows yet another schematic plan view of a partial structure of an electronic device according to an embodiment of the present disclosure
  • FIG. 13 shows a schematic cross-sectional view of a partial structure of an electronic device according to an embodiment of the present disclosure
  • FIG. 14 shows a flow chart of a manufacturing method of an electronic device according to an embodiment of the present disclosure
  • Figure 15 shows a schematic structural diagram of a stencil used in the manufacturing process of the related art
  • Figure 16 shows another structural schematic diagram of a stencil used in the manufacturing process of the related art
  • Figure 17 shows a schematic structural diagram of a stencil used in a manufacturing process according to an embodiment of the present disclosure.
  • Figure 18 shows another structural schematic diagram of a stencil used in a manufacturing process according to an embodiment of the present disclosure.
  • Figure 1 shows a light-emitting substrate 10 in the related art.
  • the light-emitting substrate 10 includes signal lines 16 and 17, a first insulating layer 14 located on the signal lines 16 and 17, and a first insulating layer 14 located away from the signal line 16. and 17 on one side of the second insulating layer 15 and the light-emitting device 13 on the side of the second insulating layer 15 away from the first insulating layer 14 and other structures.
  • Each light emitting device 13 includes two pins 12 on one side facing the second insulating layer 15 .
  • the first insulating layer 14 includes an opening 141 at a position corresponding to each pin 12 , the portion of the signal line 16 exposed by the opening 141 constitutes the bonding pad 11 -P, and the portion of the signal line 17 exposed by the opening 141 constitutes the bonding pad 11 - N. Except for the pads 11-P and 11-N, other parts of the signal lines 16 and 17 are covered by the first insulating layer 14. In addition, the area between the two pads is covered by the first insulating layer 14. The pad 11 -P and the corresponding pin 12 are connected to each other through solder, and the pad 11 -N and the corresponding pin 12 are connected to each other through solder.
  • the second insulating layer 15 includes an opening 151 at a position corresponding to each light-emitting device 13.
  • the two pads 11-P and 11-N and the orthographic projection of the light-emitting device 13 on the substrate all fall on the opening 151 on the substrate. In orthographic projection.
  • the first insulating layer 14 may have a single-layer structure or a multi-layer stacked structure.
  • the first insulating layer 14 may be a stack structure of a passivation layer and an OC layer (Over Coating).
  • the material of the passivation layer is an inorganic material, such as SiN, SiO, or SiON, which can effectively block the intrusion of water and oxygen into the light-emitting substrate 10;
  • the material of the OC layer is usually an organic resin, which has good leveling properties and can as a flat layer.
  • the precision of the patterning process of the first insulating layer 14 is relatively high, and its precision is usually on the order of several microns.
  • the material of the second insulating layer 15 may be white ink.
  • White ink has a high reflectivity (for example, a reflectivity greater than 92%), and therefore is usually used as a reflective layer.
  • the patterning process accuracy of the second insulating layer 15 is slightly lower, and its accuracy is usually above the order of hundreds of microns.
  • the inventor of the present application found that the light-emitting substrate 10 includes at least two insulating layers, which makes the light-emitting substrate 10 thicker, which is not conducive to the thinning of the backplane, complicates the process, and increases the production cost.
  • the second insulating layer 15 can be directly used as an insulating layer and a reflective layer; however, the inventor of the present application found that it is limited by the material of the second insulating layer 15 and the precision of the patterning process. , the area between two adjacent pads is no longer separated by an insulating layer, but is directly exposed by the opening 151 of the second insulating layer 15 .
  • the wiring substrate 100 includes: a substrate (not shown in the figure); and a plurality of pad groups 102 located on the substrate, each pad group 102 including at least two pads. At least two pads that are adjacent in the first direction D1 or the second direction D2 are spaced apart from each other.
  • the first direction D1 intersects the second direction D2. For example, the first direction D1 and the second direction D2 intersect. D2 can be perpendicular to each other.
  • Each pad includes a plurality of sides, including at least one selected side 1021A and at least one non-selected side 1021B, and any pad is adjacent to another pad along the first direction D1 or the second direction D2.
  • the selected side 1021A of any pad is the side facing another adjacent pad among the multiple sides, and the selected side 1021A of any pad facing another adjacent pad is different from the other adjacent pad.
  • the distance T between the selected sides 1021A of the pad facing any pad is greater than or equal to 30um and less than 100um.
  • T can be 30um, 50um, 65um, 90um, 99um, etc.
  • the distance T is smaller than the value in the related art. In the related art, the distance between two opposite sides of two adjacent pads is greater than 100um.
  • the lower limit of the pitch T is associated with the accuracy of the solder application. For example, if the accuracy of soldering is ⁇ 30 microns, the lower limit of T is 30 microns; if the accuracy of soldering is ⁇ 50 microns, the lower limit of T is 50 microns.
  • the accuracy of solder coating is related to the size of the wiring substrate. For example, the accuracy of soldering coating on a 32-inch wiring substrate can reach ⁇ 50 microns, and the accuracy of soldering coating on a 16-inch wiring substrate can reach ⁇ 30 microns.
  • Pad groups including different numbers of pads are described below using several different examples.
  • FIG. 2 shows an example of the pad groups 102 of the wiring substrate 100.
  • each pad group 102 includes two pads 1021-P and 1021-N, the two pads 1021-P and 1021-N.
  • 1021-N is connected to the two pins of the light-emitting element respectively.
  • the two pads are spaced apart from each other along the first direction D1.
  • Each of the two pads 1021-P and 1021-N includes four sides, the four sides are the selected side 1021A and the non-selected sides 1021B, 1021C and 1021D, that is, each pad includes one selected side and three unselected edges.
  • the "selected edge” needs to meet the following two conditions: first, the selected edge faces another adjacent pad, and second, the selected edge is between the selected edge and the selected edge of another adjacent pad.
  • the distance T between them needs to be greater than or equal to 30um and less than 100um.
  • the side is an unselected side of the pad. In the example of FIG.
  • the side 1021A of the pad 1021 -P is the selected side because the side 1021A faces the adjacent another pad 1021 -N, and the side 1021A and the adjacent another pad 1021 -N
  • the distance T between the sides 1021A is greater than or equal to 30um and less than 100um.
  • the sides 1021B, 1021C and 1021D of the pad 1021-P are unselected sides because there is no other pad within 100um of the side 1021C in the first direction D1 (the side 1021A of the pad 1021-N is away from the side 1021C.
  • the distance between the non-selected side 1021C of the pad 1021-P is greater than 100um), and there is no other pad within 100um of the sides 1021B and 1021D in the second direction D2.
  • side 1021A of pad 1021-N is a selected side, and sides 1021B, 1021C, and 1021D of pad 1021-N are unselected sides.
  • the distance T between the selected side 1021A of the pad 1021-P and the selected side 1021A of the pad 1021-N is greater than or equal to 30um and less than 100um.
  • the distance T can be 30um, 50um, 65um, 90um, 99um, etc. .
  • each pad is shown as straight segments in FIG. 2 , this is only a schematic example.
  • the four sides of each pad may also be composed of multiple polyline segments or curve segments connected end to end.
  • some of the four sides of each pad may be straight line segments, and the remaining sides may be composed of multiple polyline segments or curved segments connected end to end.
  • the wiring substrate 100 further includes an insulating layer 105 located on the side of the pad group 102 away from the substrate.
  • the insulating layer 105 includes a plurality of first openings 1051 , and any one of the plurality of first openings 1051 is a first opening. 1051 corresponds to one pad group 102 among the plurality of pad groups 102 .
  • the material of the insulating layer 105 may be, for example, white ink.
  • White ink has a high reflectivity, for example, a reflectivity greater than 92%, and therefore has a reflective effect on the light emitted by the light-emitting element.
  • the wiring substrate 100 also includes a plurality of signal lines located on the same layer as the plurality of pad groups 102.
  • the portion of each signal line exposed by the first opening 1051 constitutes the pad 1021-P or 1021-N as described above, that is, Each pad is part of a corresponding signal line.
  • Figure 2 shows two signal lines 106 and 107. The portion of the signal line 106 exposed by the first opening 1051 is used as a bonding pad 1021-P, and the portion of the signal line 107 exposed by the first opening 1051 is used as a bonding pad 1021-N. .
  • the portion of the signal line 106 that overlaps the first opening 1051 defines the size and the position of the four sides of the pad 1021-P
  • the portion of the signal line 107 that overlaps the first opening 1051 defines the pad 1021-N. size and position of the four sides.
  • the orthographic projection of the non-selected sides 1021B, 1021C, and 1021D of each pad on the substrate coincides with the partial outline of the orthographic projection of the first opening 1051 on the substrate.
  • the signal line 106 also includes other parts covered by the insulating layer 105 and is mainly used for transmitting electrical signals; the signal line 107 also includes other parts covered by the insulating layer 105 and is mainly used for transmitting electrical signals.
  • the orthographic projection of other parts of the signal line 106 except the bonding pad 1021-P and the other parts of the signal line 107 except the bonding pad 1021-N on the substrate falls on the orthogonal projection of the main body part 1052 of the insulating layer 105 on the substrate. within the projection.
  • the orthographic projection of the side 161 of the signal line 16 on the substrate and the partial outline of the orthographic projection of the opening 151 of the second insulating layer 15 on the substrate have a distance D, and the side of the signal line 16
  • the orthographic projection of the side 161 on the substrate falls within the orthographic projection of the first insulating layer 14 on the substrate; the orthographic projection of the side edges 171 and 172 of the signal line 17 on the substrate is within the orthographic projection of the opening 151 of the second insulating layer 15 on the substrate.
  • the partial contours of the orthographic projections all have a distance D, and the orthographic projection of the side edges 171 and 172 of the signal line 17 on the substrate falls within the orthographic projection of the first insulating layer 14 on the substrate. That is to say, although the orthographic projection of the side 161 of the signal line 16 on the substrate falls within the orthographic projection of the opening 151 on the substrate, the side 161 may be located between the signal line 16 and the second insulating layer 15 Covered by the first insulating layer 14; similarly, although the orthographic projection of the side edges 171 and 172 of the signal line 17 on the substrate falls within the orthographic projection of the opening 151 on the substrate, the side edges 171 and 172 can be located on the signal line 17.
  • the first insulating layer 14 between the line 17 and the second insulating layer 15 is covered, so the first insulating layer 14 can prevent water, oxygen, etc. in the environment from intruding into the light-emitting substrate 10 along the sides of the signal lines 16 and 17 .
  • the first insulating layer 14 is not provided. If the design scheme regarding the relative positional relationship between the signal lines 16 and 17 and the second insulating layer 15 in the related art is continued, the sides 161 of the signal line 16 and the sides 171 and 172 of the signal line 17 will be covered by the second insulating layer. The opening 151 of 15 is directly exposed, allowing water and oxygen in the environment to invade into the interior of the wiring substrate along the sides of the signal line, corroding the signal line, thereby affecting the electrical performance of the signal line.
  • the inventor of the present application has improved the relative positional relationship between the first opening 1051 of the insulating layer 105 and the signal lines 106 and 107.
  • the signal line 106 is, for example, a strip structure, which includes four sides. The four sides are respectively sides 1061, 1062, 1063, and 1064. At least the sides 1061, 1062, and 1063 are on the substrate.
  • the orthographic projection falls within the orthographic projection of the main body portion 1052 of the insulating layer 105 on the substrate, that is, the sides 1061, 1062, and 1063 are covered by the main body portion 1052 of the insulating layer 105.
  • the signal line 107 is, for example, a strip structure, which includes four sides.
  • the four sides are sides 1071, 1072, 1073 and 1074 respectively.
  • At least the orthographic projection of the sides 1071, 1072 and 1073 on the substrate falls on the insulating layer 105.
  • the main body portion 1052 is within the orthographic projection on the substrate, that is, the sides 1071, 1072, and 1073 are covered by the main body portion 1052 of the insulating layer 105.
  • the arrangement of pads 1021-P and 1021-N is optimized such that the distance T between two selected sides 1021A of two adjacent pads that are oppositely arranged is greater than or equal to 30um and less than 100um, the value of this spacing T provides a reasonable space for subsequent pin welding with electronic devices.
  • the spacing T can ensure that the pins will not come into contact with other pads that should not have an electrical connection relationship, resulting in short circuits, such as with pads.
  • the spacing T can also be On the basis of avoiding short circuit, maximize the surface area of the pads 1021-P and 1021-N facing the pins of the electronic device, thereby increasing the soldering area of the pads 1021-P and 1021-N and the pins, Reduce or even avoid poor welding such as virtual soldering due to insufficient contact area.
  • FIG. 3 shows another example of the pad group 202 of the wiring substrate 100.
  • each pad group 202 includes four pads arranged in an array and spaced apart along the first direction D1 and the second direction D2.
  • the four pads are configured to be connected to the four pins of the driver chip respectively, that is, the pad group 202 is used to connect to the driver chip having four pins.
  • the wiring substrate 100 also includes signal lines such as PWR lines, cascade output lines, cascade input lines, GND lines, and signal channel lines.
  • the part of the PWR line exposed by the first opening 1051 of the insulating layer 105 is used as the pad Pwr.
  • the pad Pwr is connected to the power pin pwr of the driver chip.
  • the power supply voltage signal on the PWR line can be transmitted to the PWR via the pad Pwr.
  • Power pin pwr The part of the GND line exposed by the first opening 1051 of the insulating layer 105 is used as the pad Gnd.
  • the pad Gnd is connected to the ground pin gnd of the driver chip. Therefore, the ground signal on the GND line can be transmitted to the ground via the pad Gnd. pin gnd.
  • One end of the signal channel line exposed by the first opening 1051 of the insulating layer 105 is used as a pad Out.
  • the pad Out is connected to the output pin out of the driver chip, and the other end of the signal channel line is connected to the light-emitting element.
  • the side of the signal channel line is also connected to the cascade output line.
  • the cascade output line is connected to the pad Di of the next-level pad group.
  • the pad Di of the next-level pad group is connected to the address of the next-level driver chip.
  • Pin di is connected. Therefore, the output pin out is a multiplexed pin. It outputs a driving signal in one period and transmits the driving signal to the light-emitting element via the signal channel line to make the light-emitting element emit light; it outputs a relay signal in another period. , transmit the relay signal to the address pin di of the next-level driver chip cascaded with the driver chip via the signal channel line and the cascade output line, as the address signal of the next-level driver chip.
  • the part of the cascade input line exposed by the first opening 1051 of the insulating layer 105 is used as the pad Di.
  • the pad Di is connected to the address pin di of the driver chip.
  • the cascade input line is usually connected to the pad Out of the upper level. , to receive the relay signal transmitted by the output pin out of the upper level, and transmit the relay signal to the address pin di of the driver chip as the address signal of the driver chip.
  • each pad group 202 includes four pads Pwr, Out, Di, and Gnd.
  • Each of the four pads includes four sides, namely selected sides 2021A and 2021B and non-selected sides.
  • the selected side 2021A of the pad Pwr faces the adjacent pad Out in the first direction D1, and the selected side 2021A of the pad Pwr and the selected side 2021A of the pad Out are The distance T between them is greater than or equal to 30um and less than 100um; the selected side 2021B of the pad Pwr faces the adjacent pad Di in the second direction D2, and the selected side 2021B of the pad Pwr and the pad Di
  • the distance T between the selected edges 2021B is greater than or equal to 30um and less than 100um.
  • At least one of the non-selected sides 2021C and 2021D is a first non-selected side, and the orthographic projection of the first non-selected side on the substrate coincides with a partial outline of the orthographic projection of the first opening 1051 on the substrate.
  • the non-selected side 2021C is the first non-selected side, and its orthographic projection on the substrate coincides with the partial outline of the orthographic projection of the first opening 1051 on the substrate.
  • the non-selected side 2021D is a second non-selected side, and the minimum distance between the orthographic projection of the second non-selected side on the substrate and the orthographic projection of the first opening 1051 on the substrate is T2, T2 It is 30 ⁇ 50um.
  • T2 can be 30um, 40um, 50um, etc.
  • the non-selected sides 2021C and 2021D can also be both first non-selected sides, and their orthographic projections on the substrate respectively coincide with the partial contours of the orthographic projection of the first opening 1051 on the substrate. . In this case, there is no second unselected edge among the unselected edges of the pad.
  • the layout of the pads is optimized so that the distance T between the two selected sides 2021A or 2021B of two adjacent pads that are oppositely arranged is greater than or equal to 30um and less than 100um.
  • the distance T The setting of the value provides a reasonable space for subsequent pin soldering with electronic devices.
  • the spacing T can ensure that the pins will not come into contact with other pads that should not have an electrical connection relationship and cause a short circuit; on the other hand, This spacing T can also maximize the area of the surface of the pad facing the pins of the electronic device on the basis of avoiding short circuits, thereby increasing the welding area between the pad and the pins, reducing or even avoiding problems caused by insufficient contact area. Welding defects such as weak welding.
  • FIG. 4 shows yet another example of the pad group 302 of the wiring substrate 100.
  • each pad group 302 includes twelve pads spaced apart along the first direction D1 or the second direction D2.
  • the twelve pads are configured to be respectively connected to the twelve pins of the driver chip, that is, the pad group 302 is used for a driver chip with twelve pins.
  • the wiring substrate 100 also includes a power output line, a data output line, a power input line, a data input line, a cascade input line, a cascade output line, and a GND line (including the first tooth portion). , second tooth portion), first signal channel line, second signal channel line, third signal channel line and fourth signal channel line and other signal lines.
  • the part of the power input line exposed by the first opening 1051 of the insulating layer 105 is used as the pad Vcc1.
  • the pad Vcc1 is connected to the power pin vcc1 of the driver chip. Therefore, the power voltage signal on the power input line can pass through the pad Vcc1. Transmitted to power pin vcc1.
  • the part of the power output line exposed by the first opening 1051 of the insulating layer 105 is used as the pad Vcc2.
  • the pad Vcc2 is connected to the power pin vcc2 of the driver chip.
  • the power output line is usually connected to the pad of the next-level pad group 302 Vcc1 is connected.
  • the pads Vcc1 and Vcc2 are connected to each other via the connection line K1, so the power pins vcc1 and vcc2 of the driver chip receive the same voltage signal, and the power pin vcc2 can drive the power pin of the chip to the next level through the power output line.
  • vcc1 outputs the power signal. It can be understood that the power output line and the power input line are two opposite concepts, and are named according to the signal flow direction of the power line connected to the two power pins vcc1 and vcc2 in the same driver chip.
  • the power input line connected to the power pin vcc1 of the current-level driver chip is also the power output line connected to the power pin vcc2 of the previous-level driver chip; that is, the power output line connected to the power pin vcc2 of the current-level driver chip.
  • line which is also the power input line connected to the power pin vcc1 of the next-level driver chip.
  • the part of the data input line exposed by the first opening 1051 of the insulating layer 105 is used as the pad Data1.
  • the pad Data1 is connected to the data pin data1 of the driver chip. Therefore, the driving signal on the data input line can be transmitted via the pad Data1. Give data pin data1.
  • the part of the data output line exposed by the first opening 1051 of the insulating layer 105 is used as the pad Data2.
  • the pad Data2 is connected to the data pin data2 of the driver chip.
  • the data output line is usually connected to the pad of the next-level pad group 302.
  • Data1 is connected.
  • Pad Data1 and pad Data2 are connected to each other via the connection line K2, so the data pins data1 and data2 of the driver chip receive the same drive signal, and the data pin data2 can drive the data pin of the chip to the next level through the data output line.
  • data1 transmits the driving signal. It can be understood that the data output line and the data input line are two opposite concepts, and are named according to the signal flow direction of the signal lines connected to the two data pins data1 and data2 in the same driver chip.
  • the data input line connected to the data pin data1 of the current-level driver chip is also the data output line connected to the data pin data2 of the previous-level driver chip; that is, the data output line connected to the data pin data2 of the current-level driver chip.
  • line is also the data input line connected to the data pin data1 of the next-level driver chip.
  • the part of the first tooth portion of the GND line exposed by the first opening 1051 of the insulating layer 105 is used as the pad Gnd1, and the pad Gnd1 is connected to the ground pin gnd1 of the driver chip; the second tooth portion of the GND line is exposed by the first opening 1051 of the insulating layer 105.
  • the exposed part of the first opening 1051 is used as a bonding pad Gnd2, and the bonding pad Gnd2 is connected to the ground pin gnd2 of the driver chip.
  • the first tooth portion of the GND wire and the second tooth portion of the GND wire are jointly connected to the main body portion of the GND wire, and the main body portion has an included angle with the extending direction of the first tooth portion and/or the second tooth portion. Therefore, the signal transmitted by the GND line can be transmitted to the ground pins gnd1 and gnd2 via the first tooth part and the second tooth part respectively.
  • the part of the cascade input line exposed by the first opening 1051 of the insulation layer 105 is used as the pad Di_in.
  • the pad Di_in is connected to the address pin di_in of the driver chip.
  • the cascade input line is usually connected to the pad Di_out of the upper level. , to receive the relay signal transmitted by the upper-level relay pin di_out, and transmit the relay signal to the address pin di_in of the driver chip as the address signal of the driver chip.
  • the part of the cascade output line exposed by the first opening 1051 of the insulating layer 105 is used as the pad Di_out.
  • the pad Di_out is connected to the relay pin di_out of the driver chip.
  • the cascade output line is connected to the welding pad of the next stage pad group.
  • the disk Di_in is connected, and the relay pin di_out transmits the relay signal to the address pin di_in of the next-level driver chip cascaded with the driver chip through the cascade output line as the address signal of the next-level driver chip.
  • One end of the first signal channel line, the second signal channel line, the third signal channel line and the fourth signal channel line exposed by the first opening 1051 of the insulating layer 105 is used as the pads Out1, Out2, Out3 and Out4 respectively.
  • the first The other ends of the signal channel line, the second signal channel line, the third signal channel line and the fourth signal channel line are respectively connected to four light-emitting elements, and the pads Out1 to Out4 are connected to the output pins out1 to out4 of the driver chip respectively.
  • one driver chip can control at least four light-emitting elements to emit light at the same time.
  • FIG. 4 shows the arrangement positions of twelve pads, this is only an example, and the position of each pad of the pad group 302 needs to adapt to the position of each pin of the driver chip. When the pin position of the driver chip changes, the position of each pad of the pad group 302 also needs to be changed accordingly.
  • the geometric centers of the twelve pads are connected in a clockwise direction to form a convex polygon.
  • convex polygon in the textbook is: any one of the sides of a polygon is infinitely extended to two directions to form a straight line. If all other sides are on the same side of this straight line, the polygon is called a convex polygon.
  • the twelve pads include the first type of pads and the second type of pads. The number of the first type of pads is 4, which are pads Out1, Out4, Di_out, and Di_in. This application uses the reference numeral 3021. Indicates the first type of pad.
  • the number of the second type of soldering pads is 8, which are Out2, Out3, Gnd1, Gnd2, Vcc1, Vcc2, Data1, and Data2.
  • This application uses reference numeral 3022 to represent the second type of soldering pads. Two adjacent soldering pads of the second type are Two second-type pads 3022 are arranged between the first-type pads 3021.
  • Each first type of bonding pad 3021 includes four sides, which are selected sides 3021A and 3021B and non-selected sides 3021C and 3021D respectively. That is, each first type of bonding pad 3021 includes two selected sides and two Unselected edges.
  • the selected edge 3021A of the first type of pad Out1 faces the adjacent second type of pad Vcc2 in the first direction D1, and the first type of pad
  • the distance T between the selected side 3021A of Out1 and the selected side 3022A of the second type of pad Vcc2 is greater than or equal to 30um and less than 100um
  • the selected side 3021B of the first type of pad Out1 faces in the second direction D2
  • the adjacent second type of pad Out2 and the distance T between the selected side 3021B of the first type of pad Out1 and the selected side 3022B of the second type of pad Out2 is greater than or equal to 30um and less than 100um.
  • the selected side 3021A of the first type of pad Out1 may be called the first selected side, and the selected side 3021B of the first type of pad Out1 may be called the second selected side.
  • the first selected side and the second selected side The extending direction of the side has a certain included angle.
  • the included angle can be any angle greater than 0 degrees and less than 180 degrees.
  • the distance between the selected side 3022B of the second type of pad Out2 and the unselected side 3021C of the first type of pad Out1 is greater than 100um; and the distance from the unselected side of the first type of pad Out1 in the first direction D1 There is no other pad within 100um of edge 3021D, for example, the selected edge 3022A of the second type of pad Vcc2 adjacent to the first type of pad Out1 in the first direction D1 and the first type of pad Out1
  • the spacing between the non-selected edges 3021D is greater than 100um.
  • At least one of the non-selected sides 3021C and 3021D is a first non-selected side, and the orthographic projection of the first non-selected side on the substrate coincides with a partial outline of the orthographic projection of the first opening 1051 on the substrate.
  • the non-selected side 3021C is the first non-selected side, and its orthographic projection on the substrate coincides with a partial outline of the orthographic projection of the first opening 1051 on the substrate.
  • the non-selected side 3021D is the second non-selected side, and the minimum distance between the orthographic projection of the second non-selected side on the substrate and the orthographic projection of the first opening 1051 on the substrate is T2, T2 It is 30 ⁇ 50um, for example, it can be 30um, 40um, 50um, etc.
  • the non-selected sides 3021C and 3021D can also be both first non-selected sides, and their orthographic projections on the substrate respectively coincide with the partial contours of the orthographic projection of the first opening 1051 on the substrate. . In this case, there is no second non-selected side among the non-selected sides of the first type of pad 3021.
  • the eight second-type pads 3022 can be subdivided into two categories. One type is the second-type pads 3022 spaced apart from the first-type pads 3021 along the first direction D1, such as pads Vcc1, Vcc2, Data1, and Data2. . The other type is the second type of pads 3022 spaced apart from the first type of pads 3021 along the second direction D2, such as pads Out2, Out3, Gnd1, and Gnd2.
  • Each of the eight second-type bonding pads 3022 includes four sides, which are selected sides 3022A and 3022B and non-selected sides 3022C and 3022D. That is, each second-type bonding pad 3022 includes two selected sides. edge and two unselected edges. Taking the second type of pad Out2 in FIG.
  • the selected edge 3022A of the second type of pad Out2 faces the adjacent second type of pad Out3 in the second direction D2, and the second type of pad Out2
  • the distance T between the selected side 3022A of Out2 and the selected side 3022B of the second type of pad Out3 is greater than or equal to 30um and less than 100um; the selected side 3022B of the second type of pad Out2 faces in the second direction D2
  • the distance T between the adjacent first-type pad Out1 and the selected side 3022B of the second-type pad Out2 and the selected side 3021B of the first-type pad Out1 is greater than or equal to 30um and less than 100um.
  • the selected side 3022A of the second type of pad Out2 may be called the third selected side, and the selected side 3022B of the second type of pad Out2 may be called the fourth selected side.
  • the third selected side and the fourth selected side The sides extend parallel to each other.
  • the second type of bonding pad Out2 has an adjacent second type of bonding pad Gnd1 in the first direction D1
  • the distance S1 in the first direction D1 is greater than 100 um. Therefore, the side 3022C of the second type pad Out2 is an unselected side.
  • the side 3022D of the second type of pad Out2 is also an unselected side.
  • the second type of pads 3022 spaced apart from the first type of pads 3021 along the first direction D1 their selected sides are 3022A and 3022B, and their non-selected sides are 3022C and 3022D.
  • the second type of bonding pad Vcc2 has an adjacent second type of bonding pad Vcc1 in the second direction D2, since the side 3022C of the second type of bonding pad Vcc2 is in contact with the phase.
  • the distance S2 in the second direction D2 between the sides adjacent to the second type bonding pad Vcc1 is greater than 100 um. Therefore, the side 3022C of the second type bonding pad Vcc2 is an unselected side. Similarly, the side 3022D of the second type of pad Vcc2 is also an unselected side.
  • the non-selected side 3022D is the first non-selected side, and the orthographic projection of the first non-selected side on the substrate coincides with the partial outline of the orthographic projection of the first opening 1051 on the substrate.
  • Unselected edge 3022C is the third unselected edge.
  • the second type of bonding pad 3022 that is spaced apart from the first type of bonding pad 3021 along the first direction D1
  • the second type of bonding pad Vcc2 taking the second type of bonding pad Vcc2 as an example
  • the third non-selected side 3022C of the second type of bonding pad Vcc2 is connected to the first type of bonding pad 3022.
  • the spacing T1 of the second selected side 3021B of the first-type pad Out1 in the second direction D2 is greater than 0 and less than or equal to 30um.
  • the spacing T1 can be, for example, 5um, 10um, 15um, 20um, 25um, 30um, etc., the second selection
  • the fixed edge 3021B is the selected edge of the first type of pad Out1 facing the second type of pad Out2.
  • the second type of pad 3022 that is spaced apart from the first type of pad 3021 along the second direction D2
  • the third non-selected side 3022C of the second type of pad Out2 is connected to the first type of pad 3021.
  • the spacing T1 of the first selected side 3021A of the first type of pad Out1 in the first direction D1 is greater than 0 and less than or equal to 30um.
  • the spacing T1 can be, for example, 5um, 10um, 15um, 20um, 25um, 30um, etc., the first selection
  • the fixed edge 3021A is the selected edge of the first type of pad Out1 facing the second type of pad Vcc2.
  • first-type soldering pads 3022 there are two second-type soldering pads 3022 near each first-type soldering pad 3021, and the selected side of each first-type soldering pad 3021 and its adjacent second-type soldering pad 3022
  • the spacing T between the selected sides is greater than 30um and less than 100um.
  • the first type of bonding pad 3021 and the two second type of bonding pads 3022 are spaced apart in the first direction D1 and the second direction D2 respectively, and any pad adjacent to the second type of bonding pad 3022 is arranged along the first direction D1 Or the second direction D2 is spaced apart from the second type of pad 3022 .
  • the wiring substrate 100 may include at least two of them at the same time.
  • the wiring substrate 100 includes a plurality of pad groups, some of which are pad groups 102, and two pads 1021-P and 1021-N of each pad group 102 are configured with The two pins of the light-emitting element are connected respectively; others of these pad groups are pad groups 302, and the twelve pads of each pad group 302 are configured to be connected to the twelve pins of the driver chip respectively.
  • wiring substrate 100 includes a plurality of pad groups, some of which are pad groups 102 , each of which is configured with two pads 1021 -P and 1021 -N. In order to be respectively connected to two pins of the light-emitting element; others of these pad groups are pad groups 202, and the four pads of each pad group 202 are configured to be respectively connected to four pins of the driver chip.
  • the layout of the pads is optimized so that the distance T between two selected sides of two adjacent pads that are oppositely arranged is greater than or equal to 30um and less than 100um.
  • the value of this distance T is The setup provides reasonable space for subsequent soldering of pins to electronic components.
  • the spacing T can ensure that the pins will not come into contact with other pads that should not have an electrical connection relationship and cause a short circuit; on the other hand, This spacing T can also maximize the area of the surface of the pad facing the pins of the electronic device on the basis of avoiding short circuits, thereby increasing the welding area between the pad and the pins, reducing or even avoiding problems caused by insufficient contact area. Welding defects such as weak welding.
  • the distance T between adjacent pads in the same pad group may be the same as each other or may be different from each other.
  • the area of each pad in the same pad group ranges from 8000 to 14400 ⁇ m 2
  • the ratio of the areas of any two pads among multiple pads in the same pad group ranges from 0.556 to 1.800.
  • the shape, size, and area of multiple pads in the same pad group can be adapted to the structural features of the corresponding pins of the connected electronic device, such as each pad and the electronic device connected to it.
  • the pins of the devices are similar to each other.
  • the wiring substrate 100 may further include a flux 109 located on the surface of the plurality of pads of each pad group facing away from the substrate.
  • FIG. 5 takes the pad group as the pad group 302 as an example for introduction.
  • the flux 109 is mainly distributed in four areas, and each area includes one first type solder pad 3021 and two second type solder pads 3022. In each area, the flux 109 is disposed on the surfaces of the first and second type soldering pads 3021 and 3022 facing away from the substrate and between adjacent first and second type soldering pads 3021 and 3022 Area.
  • the orthographic projection of the flux 109 on the substrate does not overlap with the orthographic projection of the central area of the pad group 302 on the substrate, that is, the flux 109 is not disposed in the central area of the pad group 302, and The plurality of pads are also not provided in the central area of the pad group 302 .
  • This arrangement of the flux 109 depends on the shape of the opening of the stencil used in the manufacturing process. The structure of the stencil will be described in detail later, and will not be described in detail here.
  • Flux 109 can help and promote the soldering of pads and pins during the reflow soldering process, while also protecting and preventing oxidation. Since no pads are provided in the central area of the pad group 302, there is no need to form the flux 109 in the central area.
  • a stencil is used to set the flux, and the opening of the stencil corresponds to the area where the entire pad group 302 is located. In this way, the flux 109 is not only formed on the surfaces of all pads in the pad group facing away from the substrate, but also It is formed in the central area of the pad group where no pads are provided. When the pad group includes a large number of pads, the flux may remain in the central area of the pad group and cannot be effectively discharged.
  • the flux 109 is only disposed on the surface of the plurality of pads of the pad group 302 facing away from the substrate and the adjacent first type of pads 3021 and the second type of pads. In the area between the pads 3022 instead of being disposed in the central area of the pad group 302, it is possible to avoid the flux 109 remaining in the central area of the pad group 302, thereby preventing the flux 109 from corroding the pad group 302 and/or Corresponding pins connected to each pad of pad group 302 .
  • FIG. 6 shows the relative positional relationship between each pad 11 in a pad group of the light-emitting substrate 10 and each pin 12 of the corresponding electronic device after welding in the related art.
  • the size and shape of each pad 11 are basically the same.
  • Line B1B1' and line B2B2' in Figure 6 are perpendicular to each other, and the cross dotted line formed by them represents the reference coordinate axis.
  • the intersection of line B1B1' and line B2B2' can be understood as the geometric center of a pad group.
  • Each bonding pad 11 is arranged in an array based on the reference coordinate axis, in which line B1B1' is parallel to the second direction D2, and line B2B2' is parallel to the first direction D1; the multiple pins 12 of the electronic device are connected to the above-mentioned bonding pad group. Each pad 11 is connected in a one-to-one correspondence. Lines C1C1' and C2C2' are perpendicular to each other.
  • the intersection of line C1C1' and line C2C2' can be understood as the geometric center of the electronic device welded to the above-mentioned pad group, and multiple electronic devices
  • the pins 12 are distributed based on the coordinate axis formed by the dotted cross line formed by the line C1C1' and the line C2C2', in which the angle between the line C1C1' and the line B1B1' (i.e. the second direction D2) is an acute angle, and the angle between the line C2C2' and the line
  • the angle between B2B2' ie, the first direction D1 is an acute angle, that is, each pin 12 is deflected relative to the corresponding pad 11.
  • the welding process includes steps such as alignment of pins and pads and welding of pins and pads.
  • pin 12 will be accurately welded to the predetermined position of pad 11, that is, the intersection of line B1B1' and line B2B2' and line C1C1' and line
  • the intersection points of C2C2' basically coincide with each other, and the angle between line C1C1' and line B1B1' (i.e., the second direction D2) is almost 0, and the angle between line C2C2' and line B2B2' (i.e., the first direction D1) is almost 0; That is, pin 12 will not rotate and/or shift undesirably relative to pad 11 .
  • the pin 12 soldered to the pad 11 always inevitably rotates and shifts to a certain extent relative to the pad 11 , as shown in Figure 6. Therefore, in the actual process, the pin 12 soldered to the bonding pad 11 is allowed to have a certain degree of rotation and offset relative to the bonding pad 11 .
  • the rotation and offset angle of pin 12 is too large, the contact area between pin 12 and pad 11 will be lower than the required lower limit, resulting in insufficient soldering overlap area between pin 12 and pad 11 , resulting in welding defects such as virtual welding, thus affecting the welding yield.
  • a driver chip with twelve pins is larger in size.
  • the relative offset of the edge pins of the driver chip will increase significantly, thus As a result, the welding overlap area is even more insufficient, which in turn more easily leads to poor welding such as weak welding.
  • the related art expands the four sides of each pad 11 relative to the four sides of the pin 12 to increase the contact area between the pin 12 and the pad 11 , for example, the pad 11
  • the length of each side of pin 12 is extended by 15 ⁇ m relative to the length of the corresponding side of pin 12.
  • Each side of the pad 11 is designed to be expanded, which will cause the distance between two adjacent pads 11 to become smaller, especially for the pad 11 in the first row of Figure 6, the second row in the first row
  • a part of the orthographic projection of the side of 12 on the substrate basically overlaps, and a part of the orthographic projection of the side of the pin 12 in the 1st row and 3rd column close to the pad 11 in the 1st row and 2nd column on the substrate overlaps with
  • the sides of the pads 11 in the first row and the second column that are close to the pins 12 in the first row and the third column basically overlap with a part of the orthographic projection on the substrate.
  • the first insulating layer 14 may be disposed in the area between two adjacent pads 11 to connect the pin 12 to the adjacent one.
  • the bonding pads 11 are insulated from each other, so even if the distance between two adjacent bonding pads 11 becomes smaller due to the expansion of the bonding pad 11, it will basically not cause a short circuit problem between the pin 12 and the adjacent bonding pad 11.
  • the wiring substrate 100 provided by the embodiment of the present disclosure, as mentioned above, in order to reduce the thickness of the wiring substrate 100 and reduce the production cost, only one insulating layer 105 with both reflective and insulating functions is provided, and the first opening of the insulating layer 105 1051 exposes portions of multiple signal lines to form multiple pads, so there is no insulation layer between adjacent pads. If the related art design scheme in which each edge of the pad is equally expanded is continued to be used in this application, the smaller spacing between adjacent pads will cause the pins to come into contact with the adjacent pads, resulting in short circuit.
  • the first opening 1051 of the insulating layer 105 exposes each pad, if the area of the pad is significantly larger than the area of the pin due to expansion, it means that the pad will have a larger non-soldering surface area and the non-soldering surface area will be larger.
  • the welding surface will be exposed by the first opening 1051 , which may easily cause water and oxygen in the environment to intrude into the exposed non-soldering surface of the welding pad 11 , thereby increasing the risk of corrosion.
  • FIG. 7 shows a block diagram of the electronic device 200
  • FIG. 8 shows a schematic cross-sectional view of a partial structure of the electronic device 200 , along line AA' of FIG. 9
  • the structure of Figure 8 can be obtained by sectioning, but for the sake of simplicity, Figure 9 omits the substrate 101, multiple signal lines and other structures.
  • the electronic device 200 includes the wiring substrate 100 described in any of the previous embodiments and a plurality of electronic devices 103 .
  • the plurality of electronic devices 103 are located on a side of the plurality of pad groups away from the substrate, and any one of the plurality of electronic devices 103 corresponds to one of the plurality of pad groups.
  • Each electronic device 103 includes a pin group 104, the pin group 104 includes at least two pins 1041, any one of the at least two pins 1041 corresponds to one of the at least two pads, and each The pins 1041 of each electronic device 103 are connected to a corresponding pad.
  • the bonding pad group may be any of the bonding pad groups 102, 202, and 302 described in the previous embodiments, and the electronic device 103 may include a light-emitting element and a driver chip.
  • the light-emitting element may be a micro-light-emitting diode (Micro-LED) or a sub-millimeter light-emitting diode (Mini-LED) in the order of hundreds of microns and below.
  • the driver chip can be used to provide signals to the light-emitting element to cause the light-emitting element to emit light.
  • the electronic device 200 may be any suitable type of electronic device, for example, it may be a television, a laptop, a tablet, a wearable display device, a mobile phone, a car display, a navigation, an e-book, a digital photo frame, an advertising light box, or any other device with A product or component that displays functionality.
  • the electronic device 200 can be used as a backlight source of a liquid crystal display panel.
  • the electronic device 200 may be a liquid crystal display device, and the liquid crystal display device may have more uniform backlight brightness and better display contrast.
  • FIG. 9 shows the relative positional relationship between the pin 1041 and the corresponding pad during the alignment process of the manufacturing process (before soldering).
  • FIG. 9 omits multiple signal lines, substrate 101 and other structures, but as mentioned above, the bonding pad is obtained by exposing a part of the signal lines through the first opening 1051 of the insulating layer 105 .
  • the pad group is the pad group 302 described in the previous embodiment, and the electronic device 103 is a driver chip 1031 with twelve pins 1041 .
  • the driver chip 1031 includes four output pins out1, out2, out3, and out4, two power pins vcc1 and vcc2, two data pins data1 and data2, two ground pins gnd1 and gnd2, An address pin di_in and a relay pin di_out.
  • Each output pin can be connected to at least one light-emitting element (not shown), so one driver chip 1031 can drive at least four light-emitting elements.
  • the number of driver chips 1031 can be reduced exponentially, which greatly reduces the usage of driver chips 1031 and thereby reduces the cost of the electronic device 200 .
  • the address pin di_in is configured to receive an address signal, configure the address information of the driver chip 1031 according to the address signal, and generate a relay signal.
  • the relay pin di_out is connected to the address pin di_in of the next-level driver chip 1031 cascaded with the driver chip 1031, and is configured to output the relay signal as the address signal of the next-level driver chip 1031.
  • the data pins data1 and data2 are configured to receive drive data, which includes drive information, address verification information and other information.
  • the power pins vcc1 and vcc2 are configured to receive power signals to provide the voltage required for the operation of the driver chip 1031 to ensure the normal operation of the driver chip 1031.
  • Ground pins gnd1 and gnd2 are configured to receive ground signals.
  • FIG. 9 shows the arrangement position of the twelve pins 1041 of the driver chip 1031, this is only an example, and the arrangement position of the twelve pins 1031 of the driver chip 1031 can be flexible according to specific needs. Change.
  • the pad group 302 includes the first type of pads 3021 and the second type of pads 3022.
  • the first type of pads 3021 are pads soldered to the pins out1, out4, di_out, and di_in respectively.
  • Pads 3022 are pads soldered to pins out2, out3, gnd1, gnd2, vcc1, vcc2, data1, and data2 respectively.
  • each first type pad 3021 includes a first selected side 3021A, a second selected side 3021B, a first non-selected side 3021C and a second non-selected side 3021D.
  • the pin 1041 soldered to the first type of pad 3021 includes four sides.
  • the upper right side of Figure 9 is an enlarged schematic diagram of the output pin out1 in the left figure and the corresponding first type of pad 3021.
  • Pin out1 is For example, the pin includes the first side 1041A, the second side 1041B, the third side 1041C, and the fourth side 1041D.
  • the other three pins out4, di_out, and di_in include the same four sides.
  • the first selected side 3021A and the second selected side 3021B of the first type of pad 3021 are in contact with the pin out1
  • the first side 1041A and the second side 1041B are respectively aligned in the direction perpendicular to the substrate.
  • the orthographic projection of the first unselected side 3021C of the first type pad 3021 on the substrate is aligned with the third side of the pin out1.
  • the orthographic projections of the three sides 1041C on the substrate are at a distance of D5, and the orthographic projection of the second unselected side 3021D of the first type pad 3021 on the substrate is at a distance of D5 from the orthographic projection of the fourth side 1041D of the pin out1 on the substrate.
  • the orthographic projection distance D5 is in the range of 20 to 50 ⁇ m, for example, it can be 20 ⁇ m, 25 ⁇ m, 30 ⁇ m, 35 ⁇ m, 40 ⁇ m, 45 ⁇ m, 50 ⁇ m, etc.
  • the first selected side 3021A since there is an adjacent second type of pad 3022 within 100 ⁇ m of the first selected side 3021A in the first direction D1, the first selected side 3021A does not expand outward relative to the first side 1041A of the pin 1041; since there is an adjacent second type of pad 3022 within 100 ⁇ m of the second selected side 3021B in the second direction D2, the second selected The fixed edge 3021B does not expand outward relative to the second side 1041B of the pin out1; since there is no other adjacent pad within 100 ⁇ m of the first non-selected edge 3021C in the second direction D2, the first unselected edge 3021B does not extend outward.
  • the non-selected side 3021C can extend a distance D5 relative to the third side 1041C of the pin out1; since there is no other adjacent pad within 100 ⁇ m of the second non-selected side 3021D in the first direction D1, Therefore, the second unselected side 3021D can be extended by a distance D5 relative to the fourth side 1041D of the pin out1.
  • the relative positional relationship between the other three pins out4, di_out, di_in and their corresponding pads is the same as the relative positional relationship between the pin out1 and the first type of pad 3021, which will not be described again for the sake of simplicity.
  • the sides of the first type of pad 3021 that are less than 100 ⁇ m apart from the adjacent pads (i.e., the selected sides 3021A and 3021B) not designed to be expanded, this can avoid the problem of causing a problem due to the small spacing between two adjacent pads.
  • the pins come into contact with other pads that should not have an electrical connection, causing a short circuit; by making the sides of the first type of pads that are more than 100 ⁇ m apart from adjacent pads (i.e., non-selected sides 3021C and 3021D) relative to the pins By extending D5 on the side, the surface area of the first type of pad 3021 facing the pin can be increased as much as possible while ensuring that short circuits are avoided, thereby increasing the soldering contact area between the first type of pad 3021 and the pin, reducing or even This avoids welding defects such as virtual soldering due to insufficient contact area between the pins and the first-type pad 3021, thereby improving the welding yield.
  • each second type pad 3022 includes a third selected side 3022A, a fourth selected side 3022B, a first non-selected side 3022D, and a third non-selected side 3022C.
  • the pin 1041 corresponding to the second type of pad 3022 includes four sides.
  • the lower right side of Figure 9 is an enlargement of the output pin out2 in the left figure and the second type of pad 3022 (ie, pad Out2) welded to it. Schematic diagram, taking pin out2 as an example, this pin includes the fifth side 1041E, the sixth side 1041F, the seventh side 1041G and the eighth side 1041H.
  • the other seven pins are out3, gnd1, gnd2, vcc1, vcc2, data1, and data2 include the same four sides.
  • the third selected side 3022A and the fourth selected side 3022B of the second type bonding pad 3022 and the fifth side 1041E and the sixth side 1041F of the pin out2 are respectively in the direction perpendicular to the substrate.
  • Alignment, the orthographic projection of the first non-selected side 3022D of the second type pad 3022 on the substrate and the orthographic projection of the eighth side 1041H of the pin out2 on the substrate are separated by D3, and D3 is between 20 and 50 ⁇ m.
  • the orthographic projection of the third non-selected side 3022C of the second type pad 3022 on the substrate is consistent with the seventh side of the pin out2
  • the orthographic projection of edge 1041G on the substrate is at a distance D4, and D4 is in the range of 0 to 30 ⁇ m, for example, it can be 5 ⁇ m, 10 ⁇ m, 15 ⁇ m, 20 ⁇ m, 25 ⁇ m, 30 ⁇ m, etc.
  • the third non-selected edge of the second type of pad 3022 3022C is closer to the center O of the pad group 302 relative to the first non-selected side 3022D.
  • the third type of pad 3022 is The selected side 3022A does not expand outward relative to the fifth side 1041E of the pin out2; because there is another adjacent first type pad 3021 within a range of 100 ⁇ m from the fourth selected side 3022B along the second direction D2.
  • the fourth selected side 3022B does not expand outward relative to the sixth side 1041F of the pin out2; because there is no other adjacent side within 100 ⁇ m of the first non-selected side 3022D along the first direction D1 pad, so the first non-selected side 3022D can be extended by a distance D3 relative to the eighth side 1041H of the pin out2; since it is within a range of 100 ⁇ m from the third non-selected side 3022C along the first direction D1 There is no other adjacent pad, so the third non-selected side 3022C can be extended by a distance D4 relative to the seventh side 1041G of the pin out2.
  • the sides of the second type of pad 3022 that are less than 100 ⁇ m apart from the adjacent pads (ie, the selected sides 3022A and 3022B) not designed to be expanded, this can avoid the problem of causing a problem due to the small spacing between two adjacent pads.
  • the pins come into contact with other pads that should not have an electrical connection relationship, thereby causing a short circuit; by making the sides of the second type pad 3022 that are more than 100 ⁇ m apart from adjacent pads (ie, the non-selected sides 3022C and 3022D) relative to the pins.
  • the sides of the pins are expanded by D3 and D4 respectively, which can increase the surface area of the second type of pad 3022 facing the pin as much as possible while ensuring that short circuits are avoided, thereby increasing the soldering contact between the second type of pad 3022 and the pin. area, reducing or even avoiding welding defects such as virtual soldering caused by insufficient contact area between the pin and the second type pad 3022, thereby improving the welding yield. Further, since the third non-selected side 3022C is closer to the center O of the pad group 302 than the first non-selected side 3022D, therefore, the third non-selected side 3022C is closer to the seventh side 1041G of the pin.
  • the expansion distance D4 may be less than the expansion distance D3 of the first non-selected side 3022D relative to the eighth side 1041H of the pin, so that the two adjacent second-type pads 3022 can be positioned oppositely.
  • the spacing between non-selected edges 3022C will not be too small.
  • the area of the surface of each pin 1041 facing the corresponding pad is C1, and the range of C1 is 6400 ⁇ 12100 ⁇ m 2 .
  • the area of the surface of the corresponding pad facing the pin 1041 is C2.
  • the range of C2 is 8000 ⁇ 14400 ⁇ m 2
  • the ratio of C1 to C2 is 0.4 ⁇ 1.0.
  • the ratio of C1 to C2 can be 0.4, 0.6, 0.8, 1.0, etc.
  • the orthographic projection of the first non-selected side 3021C of the first type bonding pad 3021 on the substrate coincides with the partial outline of the orthographic projection of the first opening 1051 of the insulating layer 105 on the substrate.
  • the first The minimum distance between the orthographic projection of the second non-selected side 3021D of the class pad 3021 on the substrate and the orthographic projection of the first opening 1051 of the insulating layer 105 on the substrate is T2, and the range of T2 is 30 ⁇ 50um, for example, T2 can be 30um, 40um, 50um, etc.
  • Figure 10 is a modification of Figure 9. Except for the first type of pad 3021, other structures of Figure 10 are the same as the structure of Figure 9. In FIG.
  • Figure 11 shows each pad in a pad group 302 of the electronic device 200 provided by an embodiment of the present disclosure (referring to Figure 4, including four first type pads 3021 and eight second type pads 3022) and Corresponds to the relative positional relationship of each pin 1041 of the electronic device after welding.
  • the line E1E1' and the line E2E2' in Figure 11 are perpendicular to each other, and the cross dotted line formed by them represents the reference coordinate axis.
  • the intersection of the line E1E1' and the line E2E2' can be understood as the geometric center of a pad group 302.
  • a pad group 302 Each pad in is arranged in an array with the reference coordinate axis as a reference, in which the line E1E1' is parallel to the second direction D2 and the line E2E2' is parallel to the first direction D1.
  • a plurality of pins 1041 of the electronic device are connected to each pad in the above-mentioned pad group 302 in a one-to-one correspondence.
  • the line F1F1' and the line F2F2' are perpendicular to each other.
  • the intersection of the line F1F1' and the line F2F2' can be understood as the intersection with the above-mentioned pad.
  • the group 302 is welded to the geometric center of the connected electronic device, and the plurality of pins 1041 of the electronic device are distributed in an array based on the coordinate axis formed by the cross dotted line formed by the line F1F1' and the line F2F2'.
  • the angle between line F1F1' and line E1E1' is an acute angle
  • the angle between line F2F2' and line E2E2' is an acute angle.
  • the pin 1041 has a certain rotation and offset relative to the first type of pad 3021 or the second type of pad 3022 of the pad group 302 (for example, the rotation and offset in the related art shown in FIG. 6
  • the angle of movement is the same).
  • the rotation angle of the pin 1041 relative to the first type of soldering pad 3021 or the second type of soldering pad 3022 connected thereto is no more than 3 degrees, and the pin 1041 is relative to the first type of soldering pad 3021 or the second type connected to it.
  • the offset size of pad 3022 is no greater than 36 microns. Under this rotation angle and offset size, the contact area between the pin 1041 and the pad in the pad group can meet the requirements, so that the two can be reliably connected.
  • the orthographic projection of each pin 1041 on the substrate is the first orthographic projection B1
  • the orthographic projection of the pad 3021 or 3022 soldered to the pin 1041 on the substrate is the second orthographic projection B2.
  • the first orthographic projection B1 and the second orthographic projection B2 at least partially overlap, the area where the first orthographic projection B1 and the second orthographic projection B2 overlap constitutes the overlapping area B3, and the area of the overlapping area B3 is the same as the area of the second orthographic projection B2.
  • the ratio is greater than or equal to 39%.
  • the ratio of the area of the overlapping area B3 to the area of the second orthographic projection B2 ranges from 39% to 100%, that is, the minimum value of the ratio of the area of the overlapping area B3 to the area of the second orthographic projection B2 is 39%, and the maximum value is 100%; for a pad group, the ratio of the smallest to the largest area of each overlapping area B3 is approximately 0.5.
  • the orthographic projection of each pin 12 on the substrate is the first orthographic projection A1
  • the orthographic projection of the pad 11 soldered to the pin 12 on the substrate is the third orthographic projection.
  • Two orthographic projections A2, the first orthographic projection A1 and the second orthographic projection A2 at least partially overlap to form an overlapping area A3, and the ratio of the area of the overlapping area A3 to the area of the second orthographic projection A2 is greater than or equal to 31%; for a welding In the disk set, the minimum value of the ratio between the smallest area and the largest area of each overlapping area A3 is, for example, 0.25. .
  • the embodiment of the present disclosure can not only avoid the risk of short circuit by designing the selected sides and non-selected sides of the first type of pad 3021 and the second type of pad 3022 respectively as mentioned above. , it can also significantly increase the soldering contact area between the pin 1041 and the first type of pad 3021 or the second type of pad 3022, and reduce or even avoid the soldering contact area between the pin 1041 and the first type of pad 3021 or the second type of pad 3022. Welding defects such as virtual soldering caused by insufficient contact area can help improve the welding yield.
  • the ratio of the area of the overlapping area A3 to the area of the second orthographic projection A2 is greater than 40%, and the other eight pads
  • the ratio of the area of the overlapping area A3 to the area of the second orthographic projection A2 is significantly less than 40%, especially the pad 11 and the pin 12 located in the 1st row and 4th column.
  • the ratio of the area of projection A2 is the smallest, for example, less than 20%. In the example of FIG. 6 , the ratio of the area of the overlapping area A3 to the area of the second orthographic projection A2 ranges from approximately 20% to 100%.
  • the twelve pads at least eleven pads satisfy the requirement that the ratio of the area of the overlapping area B3 to the area of the second orthographic projection B2 is greater than 40%, and only one The ratio of the area of the overlapping area B3 of the pad to the area of the second orthographic projection B2 is slightly less than 40%. Therefore, compared with the related art, a larger number of pads satisfy that the ratio of the area of the overlapping area B3 to the area of the second orthographic projection B2 is greater than 40%, which further ensures that the pin 1041 is connected to the first type pad 3021 or the first type pad 3021.
  • the soldering contact area of the second type of pad 3022 avoids insufficient soldering contact area between the pin 1041 and the first type of pad 3021 or the second type of pad 3022, thereby helping to further improve the welding yield.
  • the insulating layer 105 is located between the plurality of pad groups and the plurality of electronic devices 103 , and any one of the plurality of electronic devices 103 is connected to one of the plurality of first openings 1051 of the insulating layer 105 .
  • One opening corresponds to 1051.
  • the insulating layer 105 is located between the plurality of pad groups 302 and the plurality of driver chips 1031, And any one of the plurality of driving chips 1031 corresponds to one of the plurality of first openings 1051 of the insulating layer 105, and the third orthographic projection of each driving chip 1031 on the substrate falls on the corresponding A first opening 1051 is within the fourth orthographic projection on the substrate, and the distance between the outline of the third orthographic projection and the outline of the fourth orthographic projection is D8, and D8 can be 20 to 40 ⁇ m, such as 20 ⁇ m, 25 ⁇ m, 30 ⁇ m.
  • the first opening 1051 of the insulating layer 105 is expanded by D8 relative to the outline of the driver chip 1031, which can provide a certain amount of redundancy to provide a tolerance range during the process, and can also be used from the first direction D1 during the die-bonding process. and limiting the driving chip 1031 in the second direction D2.
  • the insulating layer 105 is located between the plurality of pad groups 102 and the plurality of pad groups 102 .
  • the third orthographic projection falls within the fourth orthographic projection of the corresponding first opening 1051 on the substrate, and the distance between the outline of the third orthographic projection and the outline of the fourth orthographic projection is D8, and D8 can be 20 to 40 ⁇ m. , such as 20 ⁇ m, 25 ⁇ m, 30 ⁇ m, 35 ⁇ m, 40 ⁇ m, etc.
  • the first opening 1051 of the insulating layer 105 is expanded D8 relative to the outline of the light-emitting element 1032, which can provide a certain amount of redundancy to have a certain limiting effect on the light-emitting element 1032 in the first direction D1 and the second direction D2. .
  • the thickness of the insulating layer 105 in the direction perpendicular to the substrate 101 is usually 50-60 ⁇ m to meet the reflection requirements; at the same time, since the first opening 1051 of the insulating layer 105 is relatively close to the electron
  • the outline of the device 103 is expanded by 20 to 40 ⁇ m. Therefore, the insulating layer 105 can have a certain limiting effect on the electronic device 103 in the first direction D1 and the second direction D2, preventing the pins 1041 of the electronic device 103 during the solidification process.
  • the offset is limited, which can easily cause the local position of the electronic device 103 to come into contact with the surface of the insulating layer 105 facing the electronic device 103, causing the electronic device to roll over and making welding impossible; if the external expansion is too large, the insulating layer will 105 basically loses its limiting function, causing the pin 1041 of the electronic device 103 to rotate and/or shift too much relative to the pad, which can easily lead to a reduction in the contact area between the pin 1041 and the pad, causing false soldering. And it may bring the risk of short circuit between pin 1041 and the adjacent pad.
  • the light-emitting element 1032 may be a micro-light-emitting diode (Micro-LED) or a sub-millimeter light-emitting diode (Mini-LED) in the order of hundreds of microns and below.
  • the driver chip 1031 can be used to provide signals to the light-emitting element 1032 to cause the light-emitting element 1032 to emit light.
  • FIG. 13 shows a schematic cross-sectional structural view of the electronic device 200 .
  • the electronic device 200 may also include structures such as support pillars 111 , a diffusion plate 112 , a wavelength conversion layer 113 , a diffusion sheet 114 , and a composite film 115 .
  • the support pillar 111 is fixed on the insulating layer 105, which can provide a certain spatial interval between the diffusion plate 112 and the insulating layer 105, thereby obtaining a certain light mixing distance and reducing or eliminating the light shadow generated by the light-emitting element.
  • the diffusion plate 112 and the diffusion sheet 114 can be used to further eliminate potential light shadows and improve the uniformity of the picture.
  • the wavelength conversion layer 113 may, for example, convert blue light emitted by the light-emitting element into white light. In some embodiments, wavelength converting layer 113 is a quantum dot film.
  • the composite film 115 can be used to increase the brightness of the emitted light.
  • the soldered electronic devices (such as light-emitting components, driver chips, etc.) are protected by encapsulant.
  • FIG. 14 shows a flow chart of a method 400 for manufacturing an electronic device.
  • the method 400 is applicable to the electronic device described in any of the previous embodiments.
  • Method 400 includes the following steps:
  • S402 Form a plurality of pad groups on the substrate, each of the plurality of pad groups including at least two pads.
  • S403 Fix multiple electronic devices on a side of the multiple pad groups away from the substrate, wherein any one of the multiple electronic devices corresponds to one of the multiple pad groups, and the multiple electronic devices Each of the devices includes at least two pins, any one of the at least two pins corresponds to one of the at least two pads, and each pin of the electronic device is connected to a corresponding one of the pads .
  • the substrate may be a flexible or rigid material. Specifically, it may be PEN resin, silicone resin, polyimide, glass, quartz, plastic, etc. The embodiments of the present disclosure do not limit the material of the substrate.
  • S402 Form a plurality of pad groups on the substrate, each of the plurality of pad groups including at least two pads.
  • a conductive layer is formed on the substrate, and the conductive layer is patterned to form a plurality of signal lines; an insulating layer 105 including a plurality of first openings 1051 is formed on the side of the plurality of signal lines away from the substrate.
  • An opening 1051 exposes a portion of each signal line to form a bonding pad.
  • the plurality of signal lines may include a power supply voltage signal line configured to provide voltage to the light emitting element 1032, a ground signal line configured to provide a ground voltage to the ground pin gnd of the driver chip, and a data pin data configured to provide data to the driver chip.
  • the signal transmission signal line, the power supply voltage signal line configured to provide voltage to the power pin vcc of the driver chip, etc.
  • the pad group may be the pad groups 102, 202, and 302 described in the previous embodiments.
  • a step of applying flux to the pin 1041 or the pad is also included.
  • Flux can help and promote the soldering of pads and pins in the subsequent reflow soldering process, while also protecting and preventing oxidation.
  • One method is to adhere and arrange several driver chips on the UV film.
  • the pins 1041 of the driver chips are located on the side away from the UV film. Dipping the pins 1041 of all the driver chips on the UV film will help in setting.
  • the surfaces of all pins 1041 facing away from the UV film are covered with flux.
  • This method of applying flux is often referred to as the "dip flux process.”
  • solder may be applied on the surface of the pad facing the pin 1041 .
  • the driver chip is a driver chip with twelve pins as mentioned above, using this flux dipping process, not only the surfaces of all pins 1041 facing away from the UV film will be dipped in flux, but also the surfaces of the driver chip facing away from the UV film will be dipped in flux. The center area of the surface of the UV film will also be dipped in flux. The central area of the driver chip does not have any pins 1041, so in fact this central area does not require flux.
  • This flux dipping process will cause the flux to remain in the central area of the driver chip and cannot be effectively discharged, causing the flux to corrode the pins of the driver chip and the pads connected to the pins.
  • Another method of applying flux is to use a mesh with openings, such as a stencil, to print the flux onto the surface of each pad of the pad group facing the pin 1041, and for example, a dipping method may be used such that The surface of pin 1041 facing the pad is dipped in solder.
  • This method of applying flux is often called the "printed flux process.”
  • the stencil 120 includes an opening 122 at a position corresponding to each pad group, and the opening 122 exposes all twelve pads 11 of the pad group and the In the central area, flux is printed onto the twelve pads 11 of each pad group and into the central area of the pad group through the opening 122 .
  • this method is similar to the flux dipping process, which will cause the flux to remain in the central area of the pad group where the pads 11 are not provided.
  • the mesh plate 220 is provided with an opening 222 at a position corresponding to each pad 11 of the pad group, and the opening 222 exposes the surface of the pad 11 facing the pin 1041.
  • flux is printed through the opening 222 onto a portion of the surface of each pad 11 facing the pin 1041 .
  • this method can avoid printing flux into the central area of the pad group, since the screen plate 220 includes twelve openings 222 at positions corresponding to each pad group, and a large number of pads are provided on the light-emitting substrate. groups, this will result in the entire screen plate 220 having a correspondingly large number of openings 222 .
  • the adhesion between the flux and the stencil 220 and/or the substrate will increase significantly.
  • the spacing between two adjacent openings 222 of the disk set is small, which will cause the strength and tension of the screen plate 220 to be insufficient and the tension to be reduced, making it difficult to ensure the accuracy of removing the screen plate 220 from the substrate, and the reduced strength and tension will also accelerate.
  • the wear of the screen plate 220 shortens its life.
  • embodiments of the present disclosure provide an improved stencil to optimize the flux printing process.
  • the mesh plate 320 includes four second openings 322 at positions corresponding to each pad group 202 , and each opening 322 is in The orthographic projection on the substrate falls within the orthographic projection of a corresponding pad on the substrate. Flux can be printed to the surface of each pad facing the pin 1041 through the second opening 322 without printing the flux to the center area of the pad group 202, thereby avoiding flux remaining in the center of the pad group 202. area, thereby preventing the flux from corroding each pad of the pad group 202 and the corresponding pins of the electronic device connected to each pad.
  • the distance D7 between two opposite sides of two adjacent pads is relatively large, about 140 ⁇ m, and the distance D6 between two opposite profiles of two adjacent second openings 322 can be increased to 160 ⁇ m.
  • the larger distance D6 can ensure that the screen plate 320 has higher strength and tension.
  • each pad group 302 when the pad group is a pad group 302 including twelve pads, each pad group 302 includes a central area and four corner areas surrounding the central area, and each corner area is arranged There is one first type pad 3021 and two second type pads 3022.
  • the mesh plate 420 includes a plurality of second openings 422, any one of the second openings 422 of the plurality of second openings 422 corresponds to one of the plurality of corner areas of the plurality of pad groups 302, and each second opening
  • the orthographic projection of 422 on the substrate partially overlaps with the orthographic projection of one first-type pad 3021 and two second-type pads 3022 in a corresponding corner area on the substrate, that is, the screen 420 is in the corresponding corner area corresponding to each Four second openings 422 are included at the location of the pad group 302 .
  • the second opening 422 is shaped like an "L" shape, and each second opening 422 should expose at least one first type pad 3021 and at least two second type pads in the pad group 302 3022.
  • the screen 420 is used to print flux, the flux is printed through the second opening 422 of the screen 420 onto the surfaces of the first type of soldering pad 3021 and the second type of soldering pad 3022 facing away from the substrate. After printing is completed, The screen 420 is removed.
  • the stencil 420 does not have an opening corresponding to the central area of the pad group 302 , the flux will not be printed to the central area of the pad group 302 , thus causing the flux to remain in the central area of the pad group 302 . , thereby preventing the flux from corroding each pad of the pad group 302 and the corresponding pins of the electronic device connected to each pad.
  • the number of openings 222 of the mesh plate 220 is twelve; while in the embodiment of the present disclosure, at the position corresponding to each pad group 302, The number of the second openings 422 of the screen plate 420 is reduced from twelve to four, so the strength and tension of the screen plate 420 are significantly improved compared to the strength and tension of the screen plate 220 . Furthermore, reducing the number of second openings 422 can effectively ensure the accuracy of separation of the screen plate 420 from the substrate.
  • S403 Fix multiple electronic devices on the side of multiple pad groups away from the substrate.
  • this step may include: aligning each pin 1041 of the electronic device with a corresponding pad so that the first orthographic projection of each pin 1041 of the electronic device on the substrate does not exceed the position of the corresponding pad. Second orthographic projection on the substrate; each pin 1041 of the electronic device is soldered to a corresponding pad using solder. Since the surface of the pin 1041 facing the pad has been dipped in solder including tin in the previous step, and the surface of the pad facing the pin 1041 has been printed with flux, during the reflow process of the pin and the pad , the tin in the solder and the surface material of the pad can generate an intermetallic compound, and coupled with the promotion effect of the flux, pin 1041 can achieve a reliable electrical connection with the pad.
  • the step of aligning each pin 1041 of the electronic device with a corresponding pad may include the following sub-steps:
  • the first selected side 3021A and the second selected side 3021B of each first type bonding pad 3021 and the first side 1041A and the second side 1041B of a corresponding pin 1041 are respectively in the direction perpendicular to the substrate. Align so that the orthographic projection of the first non-selected side 3021C of each first type pad 3021 on the substrate is at a distance D5 from the orthographic projection of the third side 1041C of a corresponding pin 1041 on the substrate, and Make the orthographic projection of the second unselected side 3021D of each first type pad 3021 on the substrate and the orthographic projection of the fourth side 1041D of the corresponding pin 1041 on the substrate be at a distance of D5, and D5 is between 20 and 20 Within the range of 50 ⁇ m, it may be, for example, 20 ⁇ m, 25 ⁇ m, 30 ⁇ m, 35 ⁇ m, 40 ⁇ m, 45 ⁇ m, 50 ⁇ m, etc.
  • the third selected side 3022A and the fourth selected side 3022B of each second type bonding pad 3022 are aligned with the fifth side 1041E and the sixth side 1041F of a corresponding pin 1041 in a direction perpendicular to the substrate. respectively, so that the orthographic projection of the first non-selected side 3022D of each second type pad 3022 on the substrate is at a distance D3 from the orthographic projection of the eighth side 1041H of the corresponding pin 1041 on the substrate.
  • D3 is in the range of 20 to 50 ⁇ m, for example, it can be 20 ⁇ m, 25 ⁇ m, 30 ⁇ m, 35 ⁇ m, 40 ⁇ m, 45 ⁇ m, 50 ⁇ m, etc.
  • the third non-selected side 3022C of each second type pad 3022 is on the substrate
  • the distance D4 between the orthographic projection of the seventh side 1041G of the corresponding pin 1041 on the substrate is D4, and D4 is in the range of 0 to 30 ⁇ m, for example, it can be 5 ⁇ m, 10 ⁇ m, 15 ⁇ m, 20 ⁇ m, 25 ⁇ m, 30 ⁇ m, etc.
  • first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed above could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
  • the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Additionally, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
  • Embodiments of the present disclosure are described herein with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the disclosure. Because of this, variations in the shapes illustrated may be expected, for example, as a result of manufacturing techniques and/or tolerances. Thus, embodiments of the present disclosure should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Accordingly, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of the regions of the device and are not intended to limit the scope of the present disclosure.

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Abstract

本公开提供了一种布线基板及其制造方法、电子装置。该布线基板包括：衬底；位于衬底上的多个焊盘组，每个焊盘组包括至少两个焊盘。至少两个焊盘中的在第一方向或第二方向上相邻的两个焊盘间隔设置，第一方向与第二方向相交。每个焊盘包括多条边，该多条边包括至少一个选定边和至少一个非选定边，任一焊盘沿第一方向或第二方向与另一焊盘相邻，任一焊盘的选定边为多条边中面向相邻另一焊盘的边，并且任一焊盘的面向所述相邻另一焊盘的选定边和所述相邻另一焊盘的面向所述任一焊盘的选定边之间的间距大于或等于30um且小于100um。

Description

布线基板及其制造方法、电子装置 技术领域
本公开涉及显示技术领域，尤其涉及一种布线基板、包括该布线基板的电子装置、以及制造该布线基板的方法。
背景技术
显示装置通常分为液晶显示装置和有机发光二极管显示装置两大类，液晶显示装置由于具有轻薄化、抗震性好、视角广、对比度高等优点而得到广泛应用。液晶显示装置通常包括显示面板和背光源，背光源通常布置在显示面板的非显示侧以为显示面板的显示操作提供光源。液晶显示装置的对比度、亮度均匀性以及稳定性等特性与背光源的结构和性能相关联。近几年，次毫米发光二极管(Mini-LED)由于其优异的性能而得到广泛的关注，并被越来越多地应用到背光源中。
发明内容
根据本公开的一方面，提供了一种布线基板，包括：衬底；多个焊盘组，位于所述衬底上，所述多个焊盘组中的每一个包括至少两个焊盘。所述至少两个焊盘中的在第一方向或第二方向上相邻的两个焊盘间隔设置，所述第一方向与所述第二方向相交。所述至少两个焊盘中的每一个包括多条边，所述多条边包括至少一个选定边和至少一个非选定边，所述任一焊盘沿所述第一方向或所述第二方向与另一焊盘相邻，所述任一焊盘的选定边为所述多条边中面向相邻另一焊盘的边，并且所述任一焊盘的面向所述相邻另一焊盘的选定边和所述相邻另一焊盘的面向所述任一焊盘的选定边之间的间距大于或等于30um且小于100um。
在一些实施例中，所述布线基板还包括位于所述多个焊盘组远离所述衬底一侧的绝缘层。所述绝缘层包括多个第一开口，所述多个第一开口中的任一个第一开口与所述多个焊盘组中的一个焊盘组对应。
在一些实施例中，所述多个焊盘组中的任意一个焊盘组包括沿所述第一方向或所述第二方向间隔设置的两个焊盘，所述两个焊盘中的每一个的非选定边在所述衬底上的正投影与相应一个第一开口在所述 衬底上的正投影的部分轮廓重合。
在一些实施例中，所述多个焊盘组中的任意一个焊盘组包括沿所述第一方向和所述第二方向阵列排布且间隔设置的四个焊盘，所述四个焊盘中的每一个的非选定边包括至少一个第一非选定边，所述第一非选定边在所述衬底上的正投影与相应一个第一开口在所述衬底上的正投影的部分轮廓重合。
在一些实施例中，每个焊盘的非选定边还包括一个第二非选定边，所述第二非选定边在所述衬底上的正投影与所述相应一个第一开口在所述衬底上的正投影的轮廓之间的最小间距为30～50um。
在一些实施例中，所述多个焊盘组中的任意一个焊盘组包括沿所述第一方向或所述第二方向间隔设置的多个焊盘，所述多个焊盘的几何中心沿顺时针方向依次连线构成凸多边形，所述多个焊盘中的每一个的非选定边包括至少一个第一非选定边，所述第一非选定边在所述衬底上的正投影与相应一个第一开口在所述衬底上的正投影的部分轮廓重合。
在一些实施例中，所述多个焊盘包括第一类焊盘和第二类焊盘，所述第一类焊盘的选定边包括第一选定边和第二选定边，所述第一选定边的延伸方向和所述第二选定边的延伸方向具有夹角，所述第二类焊盘的选定边包括第三选定边和第四选定边，所述第三选定边的延伸方向和所述第四选定边的延伸方向平行。
在一些实施例中，所述第一类焊盘与两个第二类焊盘分别在所述第一方向和所述第二方向上间隔设置，并且与所述第二类焊盘相邻的任一焊盘沿第一方向或第二方向和该第二类焊盘间隔设置。
在一些实施例中，每个第一类焊盘的非选定边还包括一个第二非选定边，所述第二非选定边在所述衬底上的正投影与所述相应一个第一开口在所述衬底上的正投影的轮廓之间的最小间距为30～50um。
在一些实施例中，每个第二类焊盘的非选定边还包括一个第三非选定边，所述第二类焊盘沿所述第一方向与一个第一类焊盘间隔设置，所述第二类焊盘的第三非选定边与所述第一类焊盘的第二选定边在所述第二方向上的间距大于0且小于或等于30um，所述第一类焊盘的第二选定边为该第一类焊盘的面向该第一类焊盘沿所述第二方向间隔设置的第二类焊盘的选定边。
在一些实施例中，每个第二类焊盘的非选定边还包括一个第三非选定边，所述第二类焊盘沿所述第二方向与一个第一类焊盘间隔设置，所述第二类焊盘的第三非选定边与所述第一类焊盘的第一选定边在所述第一方向上的间距大于0且小于或等于30um，所述第一类焊盘的第一选定边为该第一类焊盘的面向该第一类焊盘沿所述第一方向间隔设置的第二类焊盘的选定边。
在一些实施例中，所述绝缘层所在层与所述多个焊盘组所在层之间没有设置其他膜层。
根据本公开的另一方面，提供了一种电子装置，其包括在前面任一实施例描述的布线基板以及多个电子器件。所述多个电子器件位于所述多个焊盘组远离所述衬底的一侧，所述多个电子器件中的任一个电子器件与所述多个焊盘组中的一个焊盘组对应，所述多个电子器件中的每一个包括至少两个引脚，所述至少两个引脚中的任一个引脚与所述至少两个焊盘中的一个焊盘对应，并且电子器件的每个引脚与相应一个焊盘连接。
在一些实施例中，每个电子器件的引脚面向所述相应一个焊盘的表面的面积与所述相应一个焊盘面向所述引脚的表面的面积的比值为0.4～1.0。
在一些实施例中，每个电子器件的引脚在所述衬底上的第一正投影与所述相应一个焊盘在所述衬底上的第二正投影至少部分地重叠，所述第一正投影与所述第二正投影重叠的区域构成重叠区，所述重叠区的面积与所述第二正投影的面积的比值大于或等于39％。
在一些实施例中，绝缘层位于所述多个焊盘组和所述多个电子器件之间，所述多个电子器件中的任一个电子器件与所述绝缘层的多个第一开口中的一个第一开口对应，每个电子器件在所述衬底上的第三正投影落在相应一个第一开口在所述衬底上的第四正投影内，并且所述第三正投影的轮廓与所述第四正投影的轮廓之间的间距为20～40μm。
根据本公开的又一方面，提供了一种制造电子装置的方法，包括：提供衬底；在所述衬底上形成多个焊盘组，所述多个焊盘组中的每一个包括至少两个焊盘；以及将多个电子器件固定在所述多个焊盘组远离所述衬底的一侧。所述多个电子器件中的任一个电子器件与所述多个焊盘组中的一个焊盘组对应，所述多个电子器件中的每一个包括至 少两个引脚，所述至少两个引脚中的任一个引脚与所述至少两个焊盘中的一个焊盘对应，并且电子器件的每个引脚与相应一个焊盘连接。
在一些实施例中，在所述衬底上形成多个焊盘组的步骤包括：在所述衬底上施加导电层，对所述导电层进行构图以形成多条信号线；在所述多条信号线远离所述衬底的一侧形成包括多个第一开口的绝缘层，利用所述第一开口暴露所述多条信号线中的每一条的一部分以形成所述焊盘。
在一些实施例中，将多个电子器件固定在所述多个焊盘组远离所述衬底的一侧的步骤包括：将电子器件的每个引脚与所述相应一个焊盘对位，使电子器件的每个引脚在所述衬底上的第一正投影不超出所述相应一个焊盘在所述衬底上的第二正投影；利用焊料将电子器件的每个引脚焊接到所述相应一个焊盘。
在一些实施例中，每个焊盘组包括沿所述第一方向或所述第二方向间隔设置的多个焊盘，所述多个焊盘包括第一类焊盘，所述第一类焊盘包括第一选定边和第二选定边以及第一非选定边和第二非选定边，所述第一选定边的延伸方向和所述第二选定边的延伸方向具有夹角，所述第一非选定边的延伸方向和所述第二非选定边的延伸方向具有夹角。将电子器件的每个引脚与所述相应一个焊盘对位的步骤包括：使每个第一类焊盘的所述第一选定边和所述第二选定边与相应一个引脚的第一侧边和第二侧边在垂直于所述衬底的方向上分别对准，并且使每个第一类焊盘的所述第一非选定边和所述第二非选定边在所述衬底上的正投影与相应一个引脚的第三侧边和第四侧边在所述衬底上的正投影分别相距20～50μm。
在一些实施例中，所述多个焊盘还包括第二类焊盘，所述第二类焊盘包括第三选定边和第四选定边以及第一非选定边和第三非选定边，所述第三选定边的延伸方向和所述第四选定边的延伸方向平行，所述第一非选定边的延伸方向和所述第三非选定边的延伸方向平行。将电子器件的每个引脚与所述相应一个焊盘对位的步骤还包括：使每个第二类焊盘的所述第三选定边和所述第四选定边与相应一个引脚的第五侧边和第六侧边在垂直于所述衬底的方向上分别对准，使每个第二类焊盘的所述第三非选定边在所述衬底上的正投影与相应一个引脚的第七侧边在所述衬底上的正投影相距0～30μm，并且使每个第二类焊盘的 所述第一非选定边在所述衬底上的正投影与相应一个引脚的第八侧边在所述衬底上的正投影相距20～50μm，所述第三非选定边相对于所述第一非选定边更靠近所述焊盘组的中心。
在一些实施例中，每个焊盘组包括中心区和围绕在所述中心区外围的多个角落区，多个角落区中的每一个布置有至少一个第一类焊盘和至少一个第二类焊盘。在将电子器件的每个引脚与所述相应一个焊盘对位之前，还包括：将网放置在所述多个焊盘组远离所处衬底的一侧，所述网包括多个第二开口，所述多个第二开口中的任一个第二开口与所述多个焊盘组的多个角落区中的一个角落区对应，所述多个第二开口中的每一个在所述衬底上的正投影与相应一个角落区内的至少一个第一类焊盘和至少一个第二类焊盘在所述衬底上的正投影部分地重叠；透过所述网板的第二开口将助焊剂印刷到第一类焊盘和第二类焊盘的远离所述衬底的表面上；移除所述网板。
附图说明
为了更清楚地描述本公开实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了相关技术中的发光基板的平面结构示意图；
图2示出了根据本公开实施例的布线基板的局部结构的平面示意图；
图3示出了根据本公开实施例的布线基板的局部结构的另一平面示意图；
图4示出了根据本公开实施例的布线基板的局部结构的又一平面示意图；
图5示出了根据本公开实施例的布线基板的局部结构的再一平面示意图；
图6示出了相关技术中的焊盘与电子器件的引脚焊接后的相对位置关系；
图7示出了根据本公开实施例的电子装置的框图；
图8示出了根据本公开实施例的电子装置的局部结构的剖面示意 图；
图9示出了根据本公开实施例的电子装置的局部结构的平面示意图；
图10示出了根据本公开实施例的电子装置的局部结构的另一平面示意图；
图11示出了根据本公开实施例的焊盘与电子器件的引脚焊接后的相对位置关系；
图12示出了根据本公开实施例的电子装置的局部结构的又一平面示意图；
图13示出了根据本公开实施例的电子装置的局部结构的剖面示意图；
图14示出了根据本公开实施例的电子装置的制造方法的流程图；
图15示出了相关技术的制造工艺中使用的网板的结构示意图；
图16示出了相关技术的制造工艺中使用的网板的另一结构示意图；
图17示出了根据本公开实施例的制造工艺中使用的网板的结构示意图；以及
图18示出了根据本公开实施例的制造工艺中使用的网板的另一结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
图1示出了相关技术中的一种发光基板10，该发光基板10包括信号线16和17、位于信号线16和17上的第一绝缘层14、位于第一绝缘层14远离信号线16和17一侧的第二绝缘层15以及位于第二绝缘层15远离第一绝缘层14一侧的发光器件13等结构。每个发光器件13包括面向第二绝缘层15一侧的两个引脚12。第一绝缘层14在对应每个引脚12的位置处包括一个开口141，信号线16被开口141暴露的部分构成焊盘11-P，信号线17被开口141暴露的部分构成焊盘11-N。除 了焊盘11-P和11-N，信号线16和17的其他部分均被第一绝缘层14覆盖，此外两个焊盘之间的区域被第一绝缘层14覆盖。焊盘11-P与相应一个引脚12通过焊料彼此连接，焊盘11-N与相应一个引脚12通过焊料彼此连接。为了增大焊盘与引脚12之间的焊接面积，焊盘11-P和11-N中的任一个焊盘的边界相对于引脚12的边界均进行了外扩，即每个引脚12在基板上的正投影落在相应一个焊盘在基板上的正投影内。焊盘的边缘外扩会导致相邻两个焊盘之间的间距L减小，但是由于相邻焊盘之间具有第一绝缘层14，因此，可以避免应和焊盘11-P连接的引脚12与相邻的焊盘11-N产生接触而导致短路，即与焊盘11-P焊接的引脚12不会与焊盘11-N接触，类似地，与焊盘11-N焊接的引脚12不会与焊盘11-P接触。第二绝缘层15在对应每个发光器件13的位置处包括一个开口151，两个焊盘11-P和11-N以及发光器件13在基板上的正投影均落在开口151在基板上的正投影内。
第一绝缘层14可以是单层结构，也可以是多层堆叠结构。例如，第一绝缘层14可以是钝化层和OC层(Over Coating)的堆叠结构。钝化层的材料为无机材料，例如可以是SiN、SiO、SiON，其可以有效阻隔水氧入侵到发光基板10中；OC层的材料通常为有机树脂，其具有较好的流平性，可以作为平坦层。第一绝缘层14的图案化工艺精度较高，其精度通常在几微米量级。第二绝缘层15的材料可以是白色油墨，白色油墨具有较高的反射率(例如大于92％的反射率)，因此通常作为反射层。相比于第一绝缘层14，第二绝缘层15的图案化工艺精度略低，其精度通常在百微米量级以上。
本申请的发明人发现，发光基板10包括至少两层绝缘层，这使得发光基板10具有较厚的厚度，不利于背板的轻薄化，并且使得工艺复杂，生产成本增加。为了减少背板的厚度和降低生产成本，可以直接利用第二绝缘层15兼作绝缘层和反射层；但是，本申请的发明人发现，受限于第二绝缘层15的材料以及图案化工艺精度，相邻两个焊盘之间的区域不再有绝缘层间隔，而是被第二绝缘层15的开口151直接暴露。如果继续沿用相关技术这种对焊盘的边界进行均等外扩的设计，当相邻两个焊盘的相对设置的两个边之间的间距L过小时，由于没有了第一绝缘层14的阻隔，容易导致与焊盘11-P和11-N之一焊接的引脚12与焊盘11-P和11-N中的另一个发生接触，从而导致短路。
因此，需要提出一种全新的焊盘设计，以避免出现短路问题。
本公开的实施例提供了一种布线基板100，可以参考图2来描述布线基板100的结构。该布线基板100包括：衬底(图中未示出)；位于衬底上的多个焊盘组102，每个焊盘组102包括至少两个焊盘。至少两个焊盘中的在第一方向D1或第二方向D2上相邻的两个焊盘彼此间隔设置，第一方向D1与第二方向D2相交，例如，第一方向D1与第二方向D2可以相互垂直。每个焊盘包括多条边，该多条边包括至少一个选定边1021A和至少一个非选定边1021B，任一焊盘沿第一方向D1或第二方向D2与另一焊盘相邻，任一焊盘的选定边1021A为多条边中面向相邻另一焊盘的边，并且任一焊盘的面向相邻另一焊盘的选定边1021A和该相邻另一焊盘的面向该任一焊盘的选定边1021A之间的间距T大于或等于30um且小于100um，例如T可以是30um，50um，65um，90um，99um等。该间距T小于相关技术中的数值，在相关技术中，相邻两个焊盘的相对设置的两条边之间的间距大于100um。
需要指出的是，在制造过程中，需要向焊盘的表面涂刷焊锡以与引脚进行焊接，间距T的下限值与涂刷焊锡的精度相关联。例如，如果涂刷焊锡的精度为±30微米，则T的下限值为30微米；如果涂刷焊锡的精度为±50微米，则T的下限值为50微米。涂刷焊锡的精度与布线基板的尺寸相关联，例如32英寸的布线基板的涂刷焊锡的精度可以达到±50微米，16英寸的布线基板的涂刷焊锡的精度可以达到±30微米。
下面以几个不同的示例来分别描述包括不同数量的焊盘的焊盘组。
图2示出了布线基板100的焊盘组102的一个示例，在该示例中，每个焊盘组102包括两个焊盘1021-P和1021-N，该两个焊盘1021-P和1021-N与发光元件的两个引脚分别连接。具体地，该两个焊盘沿第一方向D1彼此间隔设置。两个焊盘1021-P和1021-N中的每一个包括四条边，四条边分别是选定边1021A和非选定边1021B、1021C以及1021D，即每个焊盘包括一个选定边和三个非选定边。如前文所定义的，“选定边”需要满足如下两个条件：一是该选定边面向相邻另一焊盘，二是该选定边和相邻另一焊盘的选定边之间的间距T需要满足大于或等于30um且小于100um。相应地，如果在第一方向D1或第二方向D2上距焊盘的某条边的100um范围内不存在另一焊盘，则该边为焊盘 的非选定边。在图2的示例中，焊盘1021-P的边1021A为选定边，因为该边1021A面向相邻另一焊盘1021-N，并且该边1021A和相邻另一焊盘1021-N的边1021A之间的间距T大于或等于30um且小于100um。焊盘1021-P的边1021B、1021C以及1021D为非选定边，因为在第一方向D1上距该边1021C的100um范围内不存在另一焊盘(焊盘1021-N的边1021A距该焊盘1021-P的非选定边1021C的距离大于100um)，并且在第二方向D2上距边1021B和1021D 100um的范围内不存在另一焊盘。类似地，焊盘1021-N的边1021A为选定边，焊盘1021-N的边1021B、1021C以及1021D为非选定边。焊盘1021-P的选定边1021A和焊盘1021-N的选定边1021A之间的间距T大于或等于30um且小于100um，例如，间距T可以是30um，50um，65um，90um，99um等。
需要说明的是，虽然图2中示出每个焊盘的四条边均为直线段，但是这仅是一个示意性示例。在替代的示例中，每个焊盘的四条边也可以由多个首尾依次相连的折线段或者曲线段构成。在替代的另一示例中，每个焊盘的四条边中的某些边可以是直线段，其余的边可以由多个首尾依次相连的折线段或者曲线段构成。可以理解的是，在某条边由多个首尾依次相连的折线段或曲线段构成的情况下，相邻两个折线段的夹角不大于30°，相邻两个曲线段的切线方向的夹角不大于30°；在某条边由多个首尾依次相连的折线段或曲线段构成的情况下，该边的延伸方向，即为该边的两个端点连线所在的方向。需要指出的是，为了简洁，图2仅示出了一个焊盘组102，省略了其它未示出的多个焊盘组102。
如图2所示，布线基板100还包括位于焊盘组102远离衬底一侧的绝缘层105，绝缘层105包括多个第一开口1051，多个第一开口1051中的任一个第一开口1051与多个焊盘组102中的一个焊盘组102对应。绝缘层105的材料例如可以是白色油墨，白色油墨具有较高的反射率，例如反射率大于92％，因此对发光元件发射的光具有反射效果。绝缘层105所在层与多个焊盘组102所在层之间没有设置其他中间膜层，也即绝缘层105与各个焊盘所在信号线直接接触。
布线基板100还包括与多个焊盘组102位于同一层的多条信号线，每条信号线的被第一开口1051暴露的部分构成如上所述的焊盘1021-P或1021-N，即每个焊盘是相应一条信号线的一部分。图2示出了两条 信号线106和107，信号线106被第一开口1051暴露的部分用作焊盘1021-P，信号线107被第一开口1051暴露的部分用作焊盘1021-N。也就是说，信号线106的与第一开口1051重叠的部分限定了焊盘1021-P的尺寸和四条边的位置，信号线107的与第一开口1051重叠的部分限定了焊盘1021-N的尺寸和四条边的位置。如图2所示，每个焊盘的非选定边1021B、1021C、1021D在衬底上的正投影与第一开口1051在衬底上的正投影的部分轮廓重合。信号线106还包括被绝缘层105覆盖的其他部分，主要用于传输电信号；信号线107还包括被绝缘层105覆盖的其他部分，主要用于传输电信号。信号线106的除焊盘1021-P外的其他部分和信号线107除焊盘1021-N外的其他部分在衬底上的正投影落在绝缘层105的主体部1052在衬底上的正投影内。这里的“主体部1052”是指绝缘层105的除第一开口1051之外的部分。
参照图1，在相关技术中，信号线16的侧边161在基板上的正投影与第二绝缘层15的开口151在基板上的正投影的部分轮廓具有间距D，并且信号线16的侧边161在基板上的正投影落在第一绝缘层14在基板上的正投影内；信号线17的侧边171和172在基板上的正投影与第二绝缘层15的开口151在基板上的正投影的部分轮廓均具有间距D，并且信号线17的侧边171和172在基板上的正投影落在第一绝缘层14在基板上的正投影内。也就是说，虽然信号线16的侧边161在基板上的正投影落在开口151在基板上的正投影内，但是该侧边161可以被位于信号线16和第二绝缘层15之间的第一绝缘层14所覆盖；类似地，虽然信号线17的侧边171和172在基板上的正投影落在开口151在基板上的正投影内，但是该侧边171和172可以被位于信号线17和第二绝缘层15之间的第一绝缘层14所覆盖，因此第一绝缘层14可以防止环境中的水、氧等沿着信号线16和17的侧边入侵到发光基板10内。
然而，若需要实现布线基板100的轻薄化和降低生产成本，则不设置第一绝缘层14。若继续沿用相关技术中关于信号线16和17与第二绝缘层15的相对位置关系的设计方案，则信号线16的侧边161和信号线17的侧边171和172将被第二绝缘层15的开口151直接暴露，从而使得环境中的水、氧沿着信号线的侧边侵入到布线基板的内部，腐蚀信号线，从而影响信号线的电学性能。为了至少解决该技术问题，本申请的发明人对绝缘层105的第一开口1051与信号线106和107的 相对位置关系进行了改进。具体而言，如图2所示，信号线106例如为条形结构，其包括四条边，该四条边分别是边1061、1062、1063以及1064，至少边1061、1062、1063在衬底上的正投影落在绝缘层105的主体部1052在衬底上的正投影内，即边1061、1062、1063被绝缘层105的主体部1052覆盖。类似地，信号线107例如为条形结构，其包括四条边，该四条边分别是边1071、1072、1073以及1074，至少边1071、1072、1073在衬底上的正投影落在绝缘层105的主体部1052在衬底上的正投影内，即边1071、1072、1073被绝缘层105的主体部1052覆盖。通过利用绝缘层105的主体部1052覆盖信号线106和107的大部分侧边，可以有效防止环境中的水、氧等沿着信号线106和107的边缘入侵到布线基板100的内部，防止信号线106和107被腐蚀。
在图2的示例中，优化了焊盘1021-P和1021-N的布置方式，使得相邻两个焊盘的相对设置的两个选定边1021A之间的间距T大于或等于30um且小于100um，该间距T的数值的设置为后续与电子器件的引脚焊接提供了合理的空间。在相邻两个焊盘之间没有绝缘层覆盖的前提下，一方面，该间距T可以保证引脚不会与不应当具有电连接关系的其他焊盘发生接触而导致短路，例如与焊盘1021-P连接的引脚不会与焊盘1021-N发生接触，并且与焊盘1021-N连接的引脚不会与焊盘1021-P发生接触；另一方面，该间距T还可以在避免短路的基础上最大程度地增大焊盘1021-P和1021-N的面向电子器件的引脚的表面的面积，从而增大焊盘1021-P和1021-N与引脚的焊接面积，减少甚至避免由于接触面积不足导致的虚焊等焊接不良。
图3示出了布线基板100的焊盘组202的另一个示例，在该示例中，每个焊盘组202包括沿第一方向D1和第二方向D2阵列排布且间隔设置的四个焊盘，该四个焊盘配置为与驱动芯片的四个引脚分别连接，即该焊盘组202用于与具有4个引脚的驱动芯片连接。具体而言，如图3所示，该布线基板100还包括PWR线、级联输出线、级联输入线、GND线、以及信号通道线等信号线。PWR线被绝缘层105的第一开口1051暴露的部分用作焊盘Pwr，焊盘Pwr与驱动芯片的电源引脚pwr相连，由此，PWR线上的电源电压信号可以经由焊盘Pwr传输给电源引脚pwr。GND线被绝缘层105的第一开口1051暴露的部分用作焊盘Gnd，焊盘Gnd与驱动芯片的接地引脚gnd相连，由此，GND线 上的接地信号可以经由焊盘Gnd传输给接地引脚gnd。信号通道线被绝缘层105的第一开口1051暴露的一端用作焊盘Out，焊盘Out与驱动芯片的输出引脚out相连，信号通道线的另一端与发光元件相连。信号通道线的旁侧还与级联输出线相连，该级联输出线与下一级焊盘组的焊盘Di连接，下一级焊盘组的焊盘Di与下一级驱动芯片的地址引脚di相连。因此，输出引脚out为复用引脚，其在一个时段内输出驱动信号，经由信号通道线将该驱动信号传输给发光元件，以使发光元件发光；其在另一个时段内输出中继信号，经由信号通道线和级联输出线将该中继信号传输给与该驱动芯片级联的下一级驱动芯片的地址引脚di，以作为该下一级驱动芯片的地址信号。级联输入线被绝缘层105的第一开口1051暴露的部分用作焊盘Di，焊盘Di与驱动芯片的地址引脚di相连，该级联输入线通常与上一级的焊盘Out相连，以接收上一级输出引脚out传输的中继信号，并将该中继信号传输至该驱动芯片的地址引脚di来作为该驱动芯片的地址信号。
如图3所示，每个焊盘组202包括四个焊盘Pwr、Out、Di、Gnd，四个焊盘中的每个焊盘包括四条边，分别是选定边2021A和2021B以及非选定边2021C以及2021D，即每个焊盘包括两个选定边和两个非选定边。以焊盘Pwr为例，该焊盘Pwr的选定边2021A面向在第一方向D1上相邻的焊盘Out，并且该焊盘Pwr的选定边2021A和焊盘Out的选定边2021A之间的间距T大于或等于30um且小于100um；该焊盘Pwr的选定边2021B面向在第二方向D2上相邻的焊盘Di，并且该焊盘Pwr的选定边2021B和焊盘Di的选定边2021B之间的间距T大于或等于30um且小于100um。在第二方向D2上距该焊盘Pwr的非选定边2021C的100um范围内不存在另一焊盘，例如在第二方向D2上与该焊盘Pwr相邻的焊盘Di的选定边2021B与该焊盘Pwr的非选定边2021C之间的间距大于100um；并且在第一方向D1上距该焊盘Pwr的非选定边2021D的100um范围内不存在另一焊盘，例如在第一方向D1上与该焊盘Pwr相邻的另一焊盘Out的选定边2021A与该焊盘Pwr的非选定边2021D之间的间距大于100um。非选定边2021C和2021D中的至少一个是第一非选定边，该第一非选定边在衬底上的正投影与第一开口1051在衬底上的正投影的部分轮廓重合。在图3的示例中，非选定边2021C是第一非选定边，其在衬底上的正投影与第一开口 1051在衬底上的正投影的部分轮廓重合。非选定边2021D是第二非选定边，该第二非选定边在衬底上的正投影与第一开口1051在衬底上的正投影的轮廓之间的最小间距为T2，T2为30～50um，例如T2可以是30um，40um，50um等。在替代的实施例中，非选定边2021C和2021D也可以都是第一非选定边，它们在衬底上的正投影与第一开口1051在衬底上的正投影的部分轮廓分别重合。在这种情况下，焊盘的非选定边中不存在第二非选定边。
在图3的示例中，优化了焊盘的布置方式，使得相邻两个焊盘的相对设置的两个选定边2021A或2021B之间的间距T大于或等于30um且小于100um，该间距T的数值的设置为后续与电子器件的引脚焊接提供了合理的空间。在相邻两个焊盘之间没有绝缘层覆盖的前提下，一方面，该间距T可以保证引脚不会与不应当具有电连接关系的其他焊盘发生接触而导致短路；另一方面，该间距T还可以在避免短路的基础上最大程度地增大焊盘的面向电子器件的引脚的表面的面积，从而增大焊盘与引脚的焊接面积，减少甚至避免由于接触面积不足导致的虚焊等焊接不良。
图4示出了布线基板100的焊盘组302的又一个示例，在该示例中，每个焊盘组302包括沿第一方向D1或第二方向D2间隔设置的十二个焊盘，该十二个焊盘配置为与驱动芯片的十二个引脚分别连接，即该焊盘组302用于具有十二个引脚的驱动芯片。具体而言，如图4所示，该布线基板100还包括电源输出线、数据输出线、电源输入线、数据输入线、级联输入线、级联输出线、GND线(包括第一齿部、第二齿部)、第一信号通道线、第二信号通道线、第三信号通道线和第四信号通道线等信号线。电源输入线被绝缘层105的第一开口1051暴露的部分用作焊盘Vcc1，焊盘Vcc1与驱动芯片的电源引脚vcc1相连，由此，电源输入线上的电源电压信号可以经由焊盘Vcc1传输给电源引脚vcc1。电源输出线被绝缘层105的第一开口1051暴露的部分用作焊盘Vcc2，焊盘Vcc2与驱动芯片的电源引脚vcc2相连，电源输出线通常与下一级的焊盘组302的焊盘Vcc1相连。焊盘Vcc1和焊盘Vcc2经由连接线K1彼此连接，所以驱动芯片的电源引脚vcc1和vcc2接收相同的电压信号，并且电源引脚vcc2可以通过电源输出线向下一级驱动芯片的电源引脚vcc1输出电源信号。可以理解的是，电源输出线和 电源输入线为两个相对的概念，是根据与属于同一个驱动芯片中两个电源引脚vcc1和vcc2分别连接的电源线的信号流向而命名的。即与当前级驱动芯片的电源引脚vcc1连接的电源输入线，也是与上一级驱动芯片的电源引脚vcc2连接的电源输出线；即与当前级驱动芯片的电源引脚vcc2连接的电源输出线，也是与下一级驱动芯片的电源引脚vcc1连接的电源输入线。数据输入线被绝缘层105的第一开口1051暴露的部分用作焊盘Data1，焊盘Data1与驱动芯片的数据引脚data1相连，由此，数据输入线上的驱动信号可以经由焊盘Data1传输给数据引脚data1。数据输出线被绝缘层105的第一开口1051暴露的部分用作焊盘Data2，焊盘Data2与驱动芯片的数据引脚data2相连，数据输出线通常与下一级的焊盘组302的焊盘Data1相连。焊盘Data1和焊盘Data2经由连接线K2彼此连接，所以驱动芯片的数据引脚data1和data2接收相同的驱动信号，并且数据引脚data2可以通过数据输出线向下一级驱动芯片的数据引脚data1传输驱动信号。可以理解的是，数据输出线和数据输入线为两个相对的概念，是根据与属于同一个驱动芯片中两个数据引脚data1和data2分别连接的信号线的信号流向而命名的。即与当前级驱动芯片的数据引脚data1连接的数据输入线，也是与上一级驱动芯片的数据引脚data2连接的数据输出线；即与当前级驱动芯片的数据引脚data2连接的数据输出线，也是与下一级驱动芯片的数据引脚data1连接的数据输入线。GND线的第一齿部被绝缘层105的第一开口1051暴露的部分用作焊盘Gnd1，焊盘Gnd1与驱动芯片的接地引脚gnd1相连；GND线的第二齿部被绝缘层105的第一开口1051暴露的部分用作焊盘Gnd2，焊盘Gnd2与驱动芯片的接地引脚gnd2相连。GND线的第一齿部与GND线的第二齿部共同连接到GND线的主体部，且主体部与第一齿部和/或第二齿部的延伸方向具有夹角。由此，GND线的传输的信号可以分别经由第一齿部与第二齿部传输给接地引脚gnd1和gnd2。级联输入线被绝缘层105的第一开口1051暴露的部分用作焊盘Di_in，焊盘Di_in与驱动芯片的地址引脚di_in相连，该级联输入线通常与上一级的焊盘Di_out相连，以接收上一级中继引脚di_out传输的中继信号，并将该中继信号传输至该驱动芯片的地址引脚di_in来作为该驱动芯片的地址信号。级联输出线被绝缘层105的第一开口1051暴露的部分用作焊盘Di_out，焊盘Di_out与驱动芯片的中继引脚di_out 相连，该级联输出线与下一级焊盘组的焊盘Di_in连接，中继引脚di_out经由该级联输出线将中继信号传输给与该驱动芯片级联的下一级驱动芯片的地址引脚di_in，以作为下一级驱动芯片的地址信号。第一信号通道线、第二信号通道线、第三信号通道线和第四信号通道线被绝缘层105的第一开口1051暴露的一端分别用作焊盘Out1、Out2、Out3、Out4，第一信号通道线、第二信号通道线、第三信号通道线和第四信号通道线的另一端分别与四个发光元件相连，焊盘Out1～Out4与驱动芯片的输出引脚out1～out4分别相连。由此，一个驱动芯片可以同时控制至少四个发光元件发光。
需要说明的是，虽然图4示出了十二个焊盘的布置位置，但这仅是一个示例，焊盘组302的各个焊盘的位置需要适配驱动芯片的各个引脚的位置。当驱动芯片的引脚位置改变时，焊盘组302的各个焊盘的位置也需做出相应的改变。
如图4所示，十二个焊盘的几何中心沿顺时针方向依次连线构成凸多边形。教科书中对“凸多边形”的定义为：把一个多边形的所有边中的任意一条边向两方无限延长成为一条直线，如果其他各边都在此直线的同旁，则该多边形叫做凸多边形。十二个焊盘包括第一类焊盘和第二类焊盘，第一类焊盘的数量为4个，它们分别是焊盘Out1、Out4、Di_out、Di_in，本申请用附图标记3021来表示第一类焊盘。第二类焊盘的数量为8个，它们分别是Out2、Out3、Gnd1、Gnd2、Vcc1、Vcc2、Data1、Data2，本申请用附图标记3022来表示第二类焊盘，相邻两个第一类焊盘3021之间布置有两个第二类焊盘3022。
每个第一类焊盘3021包括四条边，该四条边分别是选定边3021A和3021B以及非选定边3021C以及3021D，即每个第一类焊盘3021包括两个选定边和两个非选定边。以图4中的第一类焊盘Out1为例，该第一类焊盘Out1的选定边3021A面向在第一方向D1上相邻的第二类焊盘Vcc2，并且该第一类焊盘Out1的选定边3021A和第二类焊盘Vcc2的选定边3022A之间的间距T大于或等于30um且小于100um；该第一类焊盘Out1的选定边3021B面向在第二方向D2上相邻的第二类焊盘Out2，并且该第一类焊盘Out1的选定边3021B和第二类焊盘Out2的选定边3022B之间的间距T大于或等于30um且小于100um。第一类焊盘Out1的选定边3021A可以称作第一选定边，第一类焊盘Out1 的选定边3021B可以称作第二选定边，第一选定边和第二选定边的延伸方向具有一定的夹角，例如该夹角可以是大于0度且小于180度的任意角度。在第二方向D2上距该第一类焊盘Out1的非选定边3021C的100um范围内不存在另一焊盘，例如在第二方向D2上与该第一类焊盘Out1相邻的第二类焊盘Out2的选定边3022B与该第一类焊盘Out1的非选定边3021C之间的间距大于100um；并且在第一方向D1上距该第一类焊盘Out1的非选定边3021D的100um范围内不存在另一焊盘，例如在第一方向D1上与该第一类焊盘Out1相邻的第二类焊盘Vcc2的选定边3022A与该第一类焊盘Out1的非选定边3021D之间的间距大于100um。
非选定边3021C和3021D中的至少一个是第一非选定边，该第一非选定边在衬底上的正投影与第一开口1051在衬底上的正投影的部分轮廓重合。在图4的示例中，非选定边3021C是第一非选定边，其在衬底上的正投影与第一开口1051在衬底上的正投影的部分轮廓重合。非选定边3021D是第二非选定边，该第二非选定边在衬底上的正投影与第一开口1051在衬底上的正投影的轮廓之间的最小间距为T2，T2为30～50um，例如可以是30um，40um，50um等。在替代的实施例中，非选定边3021C和3021D也可以都是第一非选定边，它们在衬底上的正投影与第一开口1051在衬底上的正投影的部分轮廓分别重合。在这种情况下，第一类焊盘3021的非选定边中不存在第二非选定边。
其他三个第一类焊盘中的任一个的四个边的布置方式与以上描述的第一类焊盘Out1的四个边的布置方式相同，为了简洁起见，此处不再赘述。
八个第二类焊盘3022可以细分为两类，一类是沿第一方向D1与第一类焊盘3021间隔设置的第二类焊盘3022，例如焊盘Vcc1、Vcc2、Data1、Data2。另一类是沿第二方向D2与第一类焊盘3021间隔设置的第二类焊盘3022，例如焊盘Out2、Out3、Gnd1、Gnd2。八个第二类焊盘3022中的任一个包括四条边，该四条边分别是选定边3022A和3022B以及非选定边3022C以及3022D，即每个第二类焊盘3022包括两个选定边和两个非选定边。以图4中的第二类焊盘Out2为例，该第二类焊盘Out2的选定边3022A面向在第二方向D2上相邻的第二类焊盘Out3，并且该第二类焊盘Out2的选定边3022A和第二类焊盘Out3 的选定边3022B之间的间距T大于或等于30um且小于100um；该第二类焊盘Out2的选定边3022B面向在第二方向D2上相邻的第一类焊盘Out1，并且该第二类焊盘Out2的选定边3022B和第一类焊盘Out1的选定边3021B之间的间距T大于或等于30um且小于100um。第二类焊盘Out2的选定边3022A可以称作第三选定边，第二类焊盘Out2的选定边3022B可以称作第四选定边，第三选定边和第四选定边的延伸方向相互平行。虽然该第二类焊盘Out2在第一方向D1上具有相邻的第二类焊盘Gnd1，但是由于该第二类焊盘Out2的边3022C与该相邻第二类焊盘Gnd1的边在第一方向D1上的间距S1大于100um，因此，该第二类焊盘Out2的边3022C是非选定边。同理，该第二类焊盘Out2的边3022D也是非选定边。类似地，对于沿第一方向D1与第一类焊盘3021间隔设置的第二类焊盘3022，它们的选定边是3022A和3022B，非选定边是3022C和3022D。以第二类焊盘Vcc2为例，虽然该第二类焊盘Vcc2在第二方向D2上具有相邻的第二类焊盘Vcc1，但是由于该第二类焊盘Vcc2的边3022C与该相邻第二类焊盘Vcc1的边在第二方向D2上的间距S2大于100um，因此，该第二类焊盘Vcc2的边3022C是非选定边。同理，该第二类焊盘Vcc2的边3022D也是非选定边。
非选定边3022D是第一非选定边，该第一非选定边在衬底上的正投影与第一开口1051在衬底上的正投影的部分轮廓重合。非选定边3022C是第三非选定边。针对沿第一方向D1与第一类焊盘3021间隔设置的第二类焊盘3022，以第二类焊盘Vcc2为例，该第二类焊盘Vcc2的第三非选定边3022C与第一类焊盘Out1的第二选定边3021B在第二方向D2上的间距T1大于0且小于或等于30um，间距T1例如可以是5um、10um、15um、20um、25um、30um等，第二选定边3021B为该第一类焊盘Out1的面向第二类焊盘Out2的选定边。针对沿第二方向D2与第一类焊盘3021间隔设置的第二类焊盘3022，以第二类焊盘Out2为例，该第二类焊盘Out2的第三非选定边3022C与第一类焊盘Out1的第一选定边3021A在第一方向D1上的间距T1大于0且小于或等于30um，间距T1例如可以是5um、10um、15um、20um、25um、30um等，第一选定边3021A为该第一类焊盘Out1的面向第二类焊盘Vcc2的选定边。
如图4所示，每个第一类焊盘3021的附近有两个第二类焊盘3022，并且每个第一类焊盘3021的选定边和与其相邻的第二类焊盘3022的选定边之间的间距T大于30um且小于100um。第一类焊盘3021与两个第二类焊盘3022分别在第一方向D1和第二方向D2上间隔设置，并且与第二类焊盘3022相邻的任一焊盘沿第一方向D1或第二方向D2和该第二类焊盘3022间隔设置。
需要说明的是，虽然图2至图4以单独的焊盘组102、202、302为例来进行介绍，但是在布线基板100中，可以同时包括它们中的至少两类。在一个实施例中，布线基板100包括多个焊盘组，这些焊盘组中的一些是焊盘组102，每个焊盘组102的两个焊盘1021-P和1021-N配置为与发光元件的两个引脚分别连接；这些焊盘组中的另一些是焊盘组302，每个焊盘组302的十二个焊盘配置为与驱动芯片的十二个引脚分别连接。在替代的一个实施例中，布线基板100包括多个焊盘组，这些焊盘组中的一些是焊盘组102，每个焊盘组102的两个焊盘1021-P和1021-N配置为与发光元件的两个引脚分别连接；这些焊盘组中的另一些是焊盘组202，每个焊盘组202的四个焊盘配置为与驱动芯片的四个引脚分别连接。
在图4的示例中，优化了焊盘的布置方式，使得相邻两个焊盘的相对设置的两个选定边之间的间距T大于或等于30um且小于100um，该间距T的数值的设置为后续与电子器件的引脚焊接提供了合理的空间。在相邻两个焊盘之间没有绝缘层覆盖的前提下，一方面，该间距T可以保证引脚不会与不应当具有电连接关系的其他焊盘发生接触而导致短路；另一方面，该间距T还可以在避免短路的基础上最大程度地增大焊盘的面向电子器件的引脚的表面的面积，从而增大焊盘与引脚的焊接面积，减少甚至避免由于接触面积不足导致的虚焊等焊接不良。
需要说明的是，对于焊盘组102、202、302中的任一个焊盘组而言，除了相邻焊盘之间的间距T需要满足如上所述的要求之外，同一焊盘组中的多个焊盘的形状、尺寸、面积可以彼此相同，也可以彼此不同。同一焊盘组中各个焊盘的面积的范围为8000～14400μm 2，并且同一焊盘组的多个焊盘中任意两个焊盘的面积的比值的范围为0.556～1.800。在一个实施例中，同一焊盘组中的多个焊盘的形状、尺寸、面积可以与连接的电子器件的对应引脚的结构特征相适配，例如 每个焊盘和与之连接的电子器件的引脚互为相似形。
参考图5，布线基板100还可以包括位于每个焊盘组的多个焊盘的背离衬底的表面上的助焊剂109，图5以焊盘组为焊盘组302为例来进行介绍。助焊剂109主要分布在四个区域，每个区域包括一个第一类焊盘3021和两个第二类焊盘3022。在每个区域内，助焊剂109布置在第一类焊盘3021和第二类焊盘3022的背离衬底的表面上以及相邻的第一类焊盘3021和第二类焊盘3022之间的区域。如图5所示，助焊剂109在衬底上的正投影与焊盘组302的中心区在衬底上的正投影不重叠，即助焊剂109不设置在焊盘组302的中心区，并且多个焊盘也未设置在焊盘组302的中心区。助焊剂109的这种布置方式依赖于制造工艺中使用的网板的开口的形状，关于网板的结构将在后文有详细的描述，此处不过多赘述。
助焊剂109在回流焊工艺中能够帮助和促进焊盘与引脚的焊接，同时具有保护和阻止氧化的作用。由于焊盘组302的中心区没有设置焊盘，因此无需在中心区形成助焊剂109。相关技术中，利用网板来设置助焊剂，网板的开口对应整个焊盘组302所在的区域，这样助焊剂109不仅形成在焊盘组的所有焊盘的背离衬底的表面上，还会形成在焊盘组的未设置有焊盘的中心区内，在焊盘组包括数目较多的焊盘时，会出现助焊剂留在焊盘组的中心区无法有效排出的情况，这样会导致留在中心区的助焊剂腐蚀焊盘组和/或与焊盘连接的引脚。相比之下，在本公开的实施例中，助焊剂109仅布置在焊盘组302的多个焊盘的背离衬底的表面上以及相邻的第一类焊盘3021和第二类焊盘3022之间的区域内，而不设置在焊盘组302的中心区，因此可以避免助焊剂109残留在焊盘组302的中心区，从而可以避免助焊剂109腐蚀焊盘组302和/或与焊盘组302的各个焊盘连接的对应引脚。
图6示出了相关技术中发光基板10的一个焊盘组中的各个焊盘11与对应电子器件的各个引脚12焊接后的相对位置关系，其中，各个焊盘11的大小和形状基本一致。图6中的线B1B1'和线B2B2'互相垂直，其构成的十字虚线表示参考坐标轴，线B1B1'和线B2B2'的交点可以理解为一个焊盘组的几何中心，一个焊盘组中的各个焊盘11以参考坐标轴为基准阵列排布，其中线B1B1'平行于第二方向D2，线B2B2'平行于第一方向D1；电子器件的多个引脚12与上述焊盘组中的各个焊盘 11一一对应连接，线C1C1'和C2C2'互相垂直，线C1C1'和线C2C2'的交点可以理解为与上述焊盘组焊接连接的电子器件的几何中心，且电子器件的多个引脚12以线C1C1'和线C2C2'构成的十字虚线构成的坐标轴为基准阵列分布，其中线C1C1'与线B1B1'(即第二方向D2)的夹角为锐角，线C2C2'与线B2B2'(即第一方向D1)的夹角为锐角，即每个引脚12相对于对应的焊盘11均有偏转。焊接工艺包括引脚与焊盘的对位以及引脚与焊盘的焊接等步骤。在理想情况下，引脚12与焊盘11对位后，引脚12将会被精确地焊接到焊盘11的预定位置处，即线B1B1'和线B2B2'的交点和线C1C1'和线C2C2'的交点基本重合，且线C1C1'与线B1B1'(即第二方向D2)的夹角几乎为0，线C2C2'与线B2B2'(即第一方向D1)的夹角几乎为0；也就是引脚12不会相对于焊盘11发生不期望的旋转和/或偏移。然而，受限于对位精度以及工艺的偏差等因素，在实际的焊接过程中，焊接到焊盘11上的引脚12相对于焊盘11总是不可避免地发生一定程度的旋转及偏移，像图6示出的那样。因此，在实际工艺中，允许焊接到焊盘11上的引脚12相对于焊盘11具有一定程度的旋转及偏移。但是，如果引脚12的旋转和偏移角度过大，则会导致引脚12与焊盘11的接触面积低于要求的下限值，使得引脚12与焊盘11的焊接搭接面积不足，产生虚焊等焊接不良，从而影响焊接良率。相比于具有四个引脚的驱动芯片，具有十二个引脚的驱动芯片的尺寸更大，在相同的旋转角度下，该驱动芯片的边缘引脚的相对偏移会显著增大，从而导致焊接搭接面积更加不足，进而更加容易导致虚焊等焊接不良。
如图6所示，相关技术通过将每个焊盘11的四个边相对于引脚12的四个边进行外扩设计以增大引脚12与焊盘11的接触面积，例如焊盘11的每条边的长度相对于引脚12的相应一条边的长度延长了15μm。焊盘11的每条边均进行外扩设计，会导致相邻两个焊盘11之间的间距变小，尤其是对于图6的第1行的焊盘11而言，第1行第2列的引脚12的靠近第1行第1列的焊盘11的侧边在基板上的正投影的一部分与第1行第1列的焊盘11的靠近第1行第2列的引脚12的侧边在基板上的正投影的一部分基本上重叠，第1行第3列的引脚12的靠近第1行第2列的焊盘11的侧边在基板上的正投影的一部分与第1行第2列的焊盘11的靠近第1行第3列的引脚12的侧边在基板上的正投影 的一部分基本上重叠。在发光基板10同时设置有第一绝缘层14和第二绝缘层15的情况下，第一绝缘层14可以布置在相邻两个焊盘11之间的区域以使引脚12与相邻的焊盘11彼此绝缘，那么即使由于焊盘11的外扩导致相邻两个焊盘11之间的间距变小，也基本上不会导致引脚12与相邻的焊盘11发生短路问题。
针对本公开实施例提供的布线基板100，如前所述，为了减少布线基板100的厚度并且降低生产成本，仅设置一个兼具反射和绝缘作用的绝缘层105，并且绝缘层105的第一开口1051暴露多条信号线的部分以构成多个焊盘，因此，相邻焊盘之间没有绝缘层间隔。如果在本申请中继续沿用相关技术的焊盘的每条边均进行均等外扩的设计方案，则相邻焊盘之间的较小间距会导致引脚与相邻的焊盘发生接触从而产生短路。另外，由于绝缘层105的第一开口1051暴露每个焊盘，如果由于外扩导致焊盘的面积显著大于引脚的面积，则意味着焊盘将具有较大的非焊接表面面积并且该非焊接表面将被第一开口1051暴露，这容易导致环境中的水氧入侵到焊盘11的被暴露的非焊接表面，从而增加腐蚀风险。
鉴于此，本公开的实施例提供了一种电子装置，图7示出了电子装置200的框图，图8示出了电子装置200的部分结构的剖面示意图，其中沿着图9的AA'线剖切可以得到图8的结构，不过为了简洁起见，图9省略了衬底101、多条信号线等结构。参考图7-9，该电子装置200包括在前面任一实施例描述的布线基板100以及多个电子器件103。多个电子器件103位于多个焊盘组远离衬底的一侧，多个电子器件103中的任一个电子器件103与多个焊盘组中的一个焊盘组对应。每个电子器件103包括引脚组104，引脚组104包括至少两个引脚1041，至少两个引脚1041中的任一个引脚与至少两个焊盘中的一个焊盘对应，并且每个电子器件103的引脚1041与相应一个焊盘连接。焊盘组可以是前面实施例描述的焊盘组102、202、302中的任一种，电子器件103可以包括发光元件和驱动芯片。发光元件可以是百微米及以下量级的微型发光二极管(Micro-LED)或次毫米发光二极管(Mini-LED)。驱动芯片可以用来向发光元件提供信号以使发光元件发光。
电子装置200可以是各种适当类型的电子装置，例如，其可以是电视机、笔记本电脑、平板电脑、可穿戴显示设备、手机、车载显示、 导航、电子书、数码相框、广告灯箱等任何具有显示功能的产品或部件。在一个实施例中，电子装置200可作为液晶显示面板的背光源使用。在另一个实施例中，电子装置200可以为液晶显示装置，该液晶显示装置可以具有更均匀的背光亮度，具有更好的显示对比度。
图9示出了在制造工艺的对位过程中(焊接之前)引脚1041与相应焊盘的相对位置关系。为了简洁起见，图9省略了多条信号线和衬底101等结构，但是如前所述，焊盘是通过绝缘层105的第一开口1051暴露信号线的一部分而得到。在图9中，作为示例，焊盘组是前面实施例描述的焊盘组302，并且电子器件103是具有十二个引脚1041的驱动芯片1031。如图9所示，驱动芯片1031包括四个输出引脚out1、out2、out3、out4，两个电源引脚vcc1和vcc2，两个数据引脚data1和data2，两个接地引脚gnd1和gnd2、一个地址引脚di_in和一个中继引脚di_out。每个输出引脚可以连接至少一个发光元件(未示出)，所以一个驱动芯片1031可以驱动至少四个发光元件。相较于一个驱动芯片只有一个输出引脚的方案，驱动芯片1031的数量可以成倍的减少，这大大减少了驱动芯片1031的用量，进而降低了电子装置200的成本。地址引脚di_in配置为接收地址信号，根据地址信号配置驱动芯片1031的地址信息，并生成中继信号。中继引脚di_out与和该驱动芯片1031级联的下一级驱动芯片1031的地址引脚di_in连接，并且配置为输出中继信号以作为下一级驱动芯片1031的地址信号。数据引脚data1和data2配置为接收驱动数据，驱动数据包括驱动信息和地址验证信息等信息。电源引脚vcc1和vcc2配置为接收电源信号，以提供驱动芯片1031工作所需的电压，保证驱动芯片1031的正常工作。接地引脚gnd1和gnd2配置为接收接地信号。
需要说明的是，虽然图9示出了驱动芯片1031的十二个引脚1041的布置位置，但这仅是一个示例，驱动芯片1031的十二个引脚的布置位置可以根据具体需求而灵活改变。
如图9所示，每个引脚1041在衬底上的正投影不超出与其对应的焊盘在衬底上的正投影。如前所述，焊盘组302包括第一类焊盘3021和第二类焊盘3022，第一类焊盘3021分别是与引脚out1、out4、di_out、di_in焊接的焊盘，第二类焊盘3022分别是与引脚out2、out3、gnd1、gnd2、vcc1、vcc2、data1、data2焊接的焊盘。
如前所述，每个第一类焊盘3021包括第一选定边3021A、第二选定边3021B、第一非选定边3021C以及第二非选定边3021D。与第一类焊盘3021焊接的引脚1041包括四条侧边，图9的右上侧是左侧图中输出引脚out1和与其对应的第一类焊盘3021的放大示意图，以引脚out1为例，该引脚包括第一侧边1041A、第二侧边1041B、第三侧边1041C以及第四侧边1041D，其他三个引脚out4、di_out、di_in包括同样的四条侧边。在对位时，以引脚out1和第一类焊盘3021(即焊盘Out1)为例，第一类焊盘3021的第一选定边3021A和第二选定边3021B与引脚out1的第一侧边1041A和第二侧边1041B在垂直于衬底的方向上分别对准，第一类焊盘3021的第一非选定边3021C在衬底上的正投影与引脚out1的第三侧边1041C在衬底上的正投影相距D5，第一类焊盘3021的第二非选定边3021D在衬底上的正投影与引脚out1的第四侧边1041D在衬底上的正投影相距D5，D5在20～50μm的范围内，例如可以是20μm，25μm，30μm，35μm，40μm，45μm，50μm等。换句话说，对于第一类焊盘3021而言，由于在第一方向D1上在第一选定边3021A的100μm范围内存在相邻的第二类焊盘3022，因此该第一选定边3021A相对于引脚1041的第一侧边1041A不外扩；由于在第二方向D2上在第二选定边3021B的100μm范围内存在相邻的第二类焊盘3022，因此该第二选定边3021B相对于引脚out1的第二侧边1041B不外扩；由于在第二方向D2上在第一非选定边3021C的100μm范围内不存在另一相邻焊盘，因此该第一非选定边3021C相对于引脚out1的第三侧边1041C可以外扩距离D5；由于在第一方向D1上在第二非选定边3021D的100μm范围内不存在另一相邻焊盘，因此该第二非选定边3021D相对于引脚out1的第四侧边1041D可以外扩距离D5。其他三个引脚out4、di_out、di_in及其对应焊盘的相对位置关系与引脚out1和第一类焊盘3021的相对位置关系相同，为了简洁起见，不再赘述。
通过使第一类焊盘3021的与相邻焊盘间距小于100μm的边(即选定边3021A和3021B)不做外扩设计，这样可以避免由于相邻两个焊盘间距过小而导致引脚与不应当具有电连接关系的其他焊盘发生接触从而引起短路；通过使第一类焊盘的与相邻焊盘间距大于100μm的边(即非选定边3021C和3021D)相对于引脚的侧边外扩D5，可以在保 证避免短路的前提下尽量增大第一类焊盘3021的面向引脚的表面积，从而增大第一类焊盘3021与引脚的焊接接触面积，减少甚至避免由于引脚与第一类焊盘3021的接触面积不足导致的虚焊等焊接不良，从而提高焊接良率。
如前所述，每个第二类焊盘3022包括第三选定边3022A、第四选定边3022B、第一非选定边3022D以及第三非选定边3022C。与第二类焊盘3022对应的引脚1041包括四条侧边，图9的右下侧是左侧图中输出引脚out2和与其焊接的第二类焊盘3022(即焊盘Out2)的放大示意图，以引脚out2为例，该引脚包括第五侧边1041E、第六侧边1041F、第七侧边1041G以及第八侧边1041H，其他七个引脚out3、gnd1、gnd2、vcc1、vcc2、data1、data2包括同样的四条侧边。在对位时，第二类焊盘3022的第三选定边3022A和第四选定边3022B与引脚out2的第五侧边1041E和第六侧边1041F在垂直于衬底的方向上分别对准，第二类焊盘3022的第一非选定边3022D在衬底上的正投影与引脚out2的第八侧边1041H在衬底上的正投影相距D3，D3在20～50μm的范围内，例如可以是20μm，25μm，30μm，35μm，40μm，45μm，50μm等，第二类焊盘3022的第三非选定边3022C在衬底上的正投影与引脚out2的第七侧边1041G在衬底上的正投影相距D4，D4在0～30μm的范围内，例如可以是5μm，10μm，15μm，20μm，25μm，30μm等，第二类焊盘3022的第三非选定边3022C相对于第一非选定边3022D更靠近焊盘组302的中心O。换句话说，对于第二类焊盘3022而言，由于在沿第二方向D2上距第三选定边3022A的100μm范围内存在相邻的另一第二类焊盘3022，因此该第三选定边3022A相对于引脚out2的第五侧边1041E不外扩；由于在沿第二方向D2上距第四选定边3022B的100μm范围内存在相邻的另一第一类焊盘3021，因此该第四选定边3022B相对于引脚out2的第六侧边1041F不外扩；由于在沿第一方向D1上距第一非选定边3022D的100μm范围内不存在另一相邻的焊盘，因此该第一非选定边3022D相对于引脚out2的第八侧边1041H可以外扩距离D3；由于在沿第一方向D1上距第三非选定边3022C的100μm范围内不存在另一相邻的焊盘，因此该第三非选定边3022C相对于引脚out2的第七侧边1041G可以外扩距离D4。其他七个引脚out3、gnd1、gnd2、vcc1、vcc2、data1、data2及其对应焊盘的相对位置关系与引脚 out2和第二类焊盘3022的相对位置关系相同，为了简洁起见，不再赘述。
通过使第二类焊盘3022的与相邻焊盘间距小于100μm的边(即选定边3022A和3022B)不做外扩设计，这样可以避免由于相邻两个焊盘间距过小而导致引脚与不应当具有电连接关系的其他焊盘发生接触从而引起短路；通过使第二类焊盘3022的与相邻焊盘间距大于100μm的边(即非选定边3022C和3022D)相对于引脚的侧边分别外扩D3和D4，可以在保证避免短路的前提下尽量增大第二类焊盘3022的面向引脚的表面积，从而增大第二类焊盘3022与引脚的焊接接触面积，减少甚至避免由于引脚与第二类焊盘3022的接触面积不足导致的虚焊等焊接不良，从而提高焊接良率。进一步地，由于第三非选定边3022C相对于第一非选定边3022D更靠近焊盘组302的中心O，因此，第三非选定边3022C相对于引脚的第七侧边1041G的外扩距离D4可以小于第一非选定边3022D相对于引脚的第八侧边1041H的外扩距离D3，从而可以使得相邻两个第二类焊盘3022的相对设置的两个第三非选定边3022C之间的间距不会太小。
如图9所示，每个引脚1041的面向相应一个焊盘的表面的面积为C1，C1的范围为6400～12100μm 2，该相应一个焊盘的面向引脚1041的表面的面积为C2，C2的范围为8000～14400μm 2，C1与C2的比值为0.4～1.0，例如C1与C2的比值可以是0.4，0.6，0.8，1.0等。
如图9所示，第一类焊盘3021的第一非选定边3021C在衬底上的正投影与绝缘层105的第一开口1051在衬底上的正投影的部分轮廓重合，第一类焊盘3021的第二非选定边3021D在衬底上的正投影与绝缘层105的第一开口1051在衬底上的正投影的轮廓之间的最小间距为T2，T2的范围是30～50um，例如T2可以为30um，40um，50um等。图10是图9的一种变型，除了第一类焊盘3021之外，图10的其他结构与图9的结构相同。在图10中，第一类焊盘3021的第一非选定边3021C和第二非选定边3021D在衬底上的正投影与绝缘层105的第一开口1051在衬底上的正投影的部分轮廓分别重合。
图11示出了本公开实施例提供的电子装置200的一个焊盘组302中的各个焊盘(参考图4，包括四个第一类焊盘3021和八个第二类焊盘3022)与对应电子器件的各个引脚1041焊接后的相对位置关系。图 11中的线E1E1'和线E2E2'互相垂直，其构成的十字虚线表示参考坐标轴，线E1E1'和线E2E2'的交点可以理解为一个焊盘组302的几何中心，一个焊盘组302中的每个焊盘以参考坐标轴为基准阵列排布，其中线E1E1'平行于第二方向D2，线E2E2'平行于第一方向D1。电子器件的多个引脚1041与上述焊盘组302中的各个焊盘一一对应连接，线F1F1'和线F2F2'互相垂直，线F1F1'和线F2F2'的交点可以理解为与上述焊盘组302焊接连接的电子器件的几何中心，且电子器件的多个引脚1041以线线F1F1'和线F2F2'构成的十字虚线构成的坐标轴为基准阵列分布。其中线F1F1'与线E1E1'的夹角为锐角，线F2F2'与线E2E2'的夹角为锐角。可以看出，引脚1041相对于焊盘组302的第一类焊盘3021或第二类焊盘3022具有一定的旋转和偏移(例如，与图6中所示相关技术中的旋转和偏移的角度相同)。引脚1041相对于与之连接的第一类焊盘3021或第二类焊盘3022的旋转角度不大于3度，并且引脚1041相对于与之连接的第一类焊盘3021或第二类焊盘3022的偏移尺寸不大于36微米。在该旋转角度和偏移尺寸情况下，引脚1041与焊盘组中的焊盘的接触面积能够满足要求，使得二者能够实现可靠连接。如图11所示，每个引脚1041在衬底上的正投影为第一正投影B1，与该引脚1041焊接的焊盘3021或3022在衬底上的正投影为第二正投影B2，第一正投影B1与第二正投影B2至少部分地重叠，第一正投影B1与第二正投影B2重叠的区域构成重叠区B3，重叠区B3的面积与第二正投影B2的面积的比值大于或等于39％。在一些实施例中，重叠区B3的面积与第二正投影B2的面积的比值的范围是39％～100％，即，重叠区B3的面积与第二正投影B2的面积的比值的最小值是39％，最大值是100％；对于一个焊盘组，各个重叠区B3的面积中的最小者与最大者的比值大约为0.5。相比之下，在相关技术中，参考图6，每个引脚12在基板上的正投影为第一正投影A1，与该引脚12焊接的焊盘11在基板上的正投影为第二正投影A2，第一正投影A1与第二正投影A2至少部分地重叠以构成重叠区A3，重叠区A3的面积与第二正投影A2的面积的比值大于或等于31％；对于一个焊盘组，各个重叠区A3的面积中的最小者与最大者的比值的最小值例如为0.25。。相比于相关技术，本公开的实施例通过对第一类焊盘3021和第二类焊盘3022的选定边和非选定边分别进行如前所述的设计，不仅可以避免出现短路风险， 还可以显著增大引脚1041与第一类焊盘3021或第二类焊盘3022的焊接接触面积，减少甚至避免由于引脚1041与第一类焊盘3021或第二类焊盘3022的接触面积不足导致的虚焊等焊接不良，从而有助于提高焊接良率。另外，参考图6，在相关技术中，在十二个焊盘11中，只有4个焊盘满足重叠区A3的面积与第二正投影A2的面积的比值大于40％，其他八个焊盘的重叠区A3的面积与第二正投影A2的面积的比值均明显小于40％，尤其是位于第1行第4列的焊盘11和引脚12，其重叠区A3的面积与第二正投影A2的面积的比值最小，例如不足20％。在图6的示例中，重叠区A3的面积与第二正投影A2的面积的比值的范围大约在20％～100％。而在本公开的实施例中，参考图11，在十二个焊盘中，至少有十一个焊盘满足重叠区B3的面积与第二正投影B2的面积的比值大于40％，只有一个焊盘的重叠区B3的面积与第二正投影B2的面积的比值略微小于40％。因此，与相关技术相比，更多数量的焊盘满足重叠区B3的面积与第二正投影B2的面积的比值大于40％，这进一步确保了引脚1041与第一类焊盘3021或第二类焊盘3022的焊接接触面积，避免引脚1041与第一类焊盘3021或第二类焊盘3022的焊接接触面积不足，从而有助于进一步提高焊接良率。
参考图8，绝缘层105位于多个焊盘组和多个电子器件103之间，并且多个电子器件103中的任一个电子器件103与绝缘层105的多个第一开口1051中的一个第一开口1051对应。在一个实施例中，如图9所示，当焊盘组为焊盘组302且电子器件103为驱动芯片1031时，绝缘层105位于多个焊盘组302和多个驱动芯片1031之间，并且多个驱动芯片1031中的任一个驱动芯片1031与绝缘层105的多个第一开口1051中的一个第一开口1051对应，每个驱动芯片1031在衬底上的第三正投影落在相应一个第一开口1051在衬底上的第四正投影内，并且第三正投影的轮廓与第四正投影的轮廓之间的间距为D8，D8可以是20～40μm，例如20μm，25μm，30μm，35μm，40μm等。绝缘层105的第一开口1051相对于驱动芯片1031的外形轮廓外扩D8，可以提供一定的冗余量，以便在工艺过程中提供公差范围，同时还可以在固晶过程中从第一方向D1和第二方向D2上对驱动芯片1031进行限位。在另一个实施例中，如图12所示，当焊盘组为具有两个焊盘的焊盘组102且电子器件103为发光元件1032时，绝缘层105位于多个焊盘组 102和多个发光元件1032之间，并且多个发光元件1032中的任一个发光元件1032与绝缘层105的多个第一开口1051中的一个第一开口1051对应，每个发光元件1032在衬底上的第三正投影落在相应一个第一开口1051在衬底上的第四正投影内，并且第三正投影的轮廓与第四正投影的轮廓之间的间距为D8，D8可以是20～40μm，例如20μm，25μm，30μm，35μm，40μm等。绝缘层105的第一开口1051相对于发光元件1032的外形轮廓外扩D8，可以提供一定的冗余量，以便在第一方向D1和第二方向D2上对发光元件1032具有一定的限位作用。
在一些实施例中，为满足反射要求，通常绝缘层105在垂直于衬底101的方向上的厚度为50～60μm，以满足反射要求；同时，由于绝缘层105的第一开口1051相对于电子器件103的外形轮廓外扩20～40μm，因此绝缘层105在第一方向D1和第二方向D2上可以对电子器件103具有一定的限位作用，避免固晶过程中电子器件103的引脚1041相对于焊盘旋转和偏移较多，因此可以增大引脚1041与焊盘在回流焊后的接触面积，减少甚至避免虚焊等焊接不良。绝缘层105的第一开口1051相对于电子器件103的外形轮廓外扩20～40μm是一个恰当的范围，因为如果外扩的尺寸范围较小，则会导致引脚1041在固晶过程中的可偏移量有限，容易造成电子器件103的局部位置与绝缘层105面向电子器件103的表面出现接触的情形，从而引起电子器件发生侧翻，进而无法实现焊接；如果外扩过大，则绝缘层105基本上失去了限位作用，导致电子器件103的引脚1041相对于焊盘旋转和/或偏移会过多，从而容易导致引脚1041与焊盘的接触面积减小，引起虚焊，并且可能带来引脚1041与相邻焊盘的短路风险。
发光元件1032可以是百微米及以下量级的微型发光二极管(Micro-LED)或次毫米发光二极管(Mini-LED)。驱动芯片1031可以用来向发光元件1032提供信号以使发光元件1032发光。
图13示出了电子装置200的剖面结构示意图。如图13所示，除了衬底101、绝缘层105、电子器件103之外，电子装置200还可以包括支撑柱111、扩散板112、波长转换层113、扩散片114以及复合膜115等结构。支撑柱111固定在绝缘层105上，其可以使扩散板112与绝缘层105之间具有一定的空间间隔，从而获得一定的混光距离，减少或消除发光元件产生的灯影。扩散板112和扩散片114可以用来进 一步消除潜在的灯影，提高画面的均一性。波长转换层113例如可以将发光元件发射的蓝光转换为白光。在一些实施例中，波长转换层113是量子点膜。复合膜115可以用来增加出射光的亮度。焊接后的电子器件(例如发光元件、驱动芯片等)由封装胶保护。
图14示出了一种制造电子装置的方法400的流程图，该方法400适用于前面任一个实施例描述的电子装置。方法400包括以下步骤：
S401：提供衬底。
S402：在衬底上形成多个焊盘组，多个焊盘组中的每一个包括至少两个焊盘。
S403：将多个电子器件固定在多个焊盘组远离衬底的一侧，其中，多个电子器件中的任一个电子器件与多个焊盘组中的一个焊盘组对应，多个电子器件中的每一个包括至少两个引脚，至少两个引脚中的任一个引脚与至少两个焊盘中的一个焊盘对应，并且电子器件的每个引脚与相应一个焊盘连接。
下面，详细描述步骤S401-S403涉及的一些工艺细节。
S401：提供衬底。
衬底可以为柔性或刚性材料，具体的，可以为PEN树脂、硅胶树脂、聚酰亚胺、玻璃、石英、塑料等，本公开的实施例对衬底的材料不作限制。
S402：在衬底上形成多个焊盘组，多个焊盘组中的每一个包括至少两个焊盘。
具体地，在衬底上形成导电层，对该导电层进行构图以形成多条信号线；在多条信号线远离衬底的一侧形成包括多个第一开口1051的绝缘层105，利用第一开口1051暴露每条信号线的一部分以形成焊盘。多条信号线可以包括配置为向发光元件1032提供电压的电源电压信号线、配置为向驱动芯片的接地引脚gnd提供接地电压的接地信号线、配置为向驱动芯片的数据引脚data提供数据信号的传输信号线、配置为向驱动芯片的电源引脚vcc提供电压的电源电压信号线等。焊盘组可以是前面实施例描述的焊盘组102、202、302。
在步骤S402和S403之间，还包括向引脚1041或焊盘施加助焊剂的步骤。助焊剂在后续的回流焊工艺中能够帮助和促进焊盘与引脚的焊接，同时具有保护和阻止氧化的作用。施加助焊剂的方法主要有两 种。一种方法是：将数颗驱动芯片粘附且排布在UV膜上，驱动芯片的引脚1041位于背离UV膜的一侧，将UV膜上所有驱动芯片的引脚1041蘸在设置有助焊剂的槽体中，使得所有引脚1041的背离UV膜的表面均被助焊剂包覆。这种施加助焊剂的方法通常称为“蘸助焊剂工艺”。对应地，可以在焊盘的面向引脚1041的表面上施加焊料。当驱动芯片为如前所述的具有十二个引脚的驱动芯片时，采取这种蘸助焊剂工艺，不仅所有引脚1041的背离UV膜的表面会蘸有助焊剂，该驱动芯片的背离UV膜的表面的中心区也会蘸有助焊剂。而驱动芯片的中心区没有设置任何引脚1041，因此事实上该中心区不需要助焊剂。而该蘸助焊剂工艺会导致助焊剂残留在驱动芯片的中心区，无法有效排出，从而导致助焊剂腐蚀驱动芯片的引脚和与引脚连接的焊盘。
施加助焊剂的另一种方法是：利用具有开口的网，例如钢网，将助焊剂印刷到焊盘组的每个焊盘的面向引脚1041的表面上，并且例如可以采用蘸取方式使得引脚1041面向焊盘的表面上蘸有焊锡。这种施加助焊剂的方法通常称为“印刷助焊剂工艺”。
利用印刷助焊剂工艺来在焊盘组的多个焊盘上形成助焊剂，相关技术中有两种方案。一种方案是，如图15所示，使网板120在对应每个焊盘组的位置处包括一个开口122，该开口122暴露焊盘组的所有十二个焊盘11以及焊盘组的中心区，透过该开口122将助焊剂印刷到每个焊盘组的十二个焊盘11上以及焊盘组的中心区内。但是这种方法与蘸助焊剂工艺类似，会导致助焊剂残留在焊盘组的未设置有焊盘11的中心区。另一种方案是，如图16所示，使网板220在对应焊盘组的每个焊盘11的位置处设置一个开口222，该开口222暴露焊盘11的面向引脚1041的表面的一部分，透过该开口222将助焊剂印刷到每个焊盘11的面向引脚1041的部分表面上。虽然该方法可以避免将助焊剂印刷到焊盘组的中心区，但是由于网板220在对应每个焊盘组的位置处包括十二个开口222，而发光基板上设置有众多数量的焊盘组，这就会导致整张网板220具有相应众多数目的开口222。当助焊剂印刷完成后需要将网板220与基板脱离时，由于开口222的数目较多，助焊剂与网板220和/或基板之间的粘附力会显著增大，加之对应同一个焊盘组的相邻两个开口222之间的间距较小，会使得网板220的强度不足、张力下降，从而难以保证网板220从基板移除的精度，并且降低的强度 和张力还会加快网板220的磨损，缩短其寿命。
鉴于此，本公开的实施例提供了一种改进的网板，以优化助焊剂的印刷工艺。
如图17所示，当焊盘组是包括四个焊盘的焊盘组202时，网板320在对应每个焊盘组202的位置处包括四个第二开口322，每个开口322在衬底上的正投影落在相应一个焊盘在衬底上的正投影内。通过第二开口322可以向每个焊盘的面向引脚1041的表面印刷助焊剂，而不会将助焊剂印刷到焊盘组202的中心区，从而避免助焊剂残留在焊盘组202的中心区，进而避免助焊剂腐蚀焊盘组202的各个焊盘和与各个焊盘连接的电子器件的对应引脚。相邻两个焊盘的相对设置的两条边之间的间距D7较大，约为140μm，而相邻两个第二开口322的相对设置的两个轮廓之间的间距D6可增大至160μm。该较大的间距D6可以保证网板320具有较高的强度和张力。
如图18所示，当焊盘组是包括十二个焊盘的焊盘组302时，每个焊盘组302包括中心区和围绕在中心区外围的四个角落区，每个角落区布置有一个第一类焊盘3021和两个第二类焊盘3022。网板420包括多个第二开口422，多个第二开口422中的任一个第二开口422与多个焊盘组302的多个角落区中的一个角落区对应，并且每个第二开口422在衬底上的正投影与相应一个角落区内的一个第一类焊盘3021和两个第二类焊盘3022在衬底上的正投影部分地重叠，即网板420在对应每个焊盘组302的位置处包括四个第二开口422。在一些实施例中，第二开口422的形状为类“L”形，每个第二开口422应露出焊盘组302中的至少一个第一类焊盘3021和至少两个第二类焊盘3022。当利用网板420印刷助焊剂时，透过网板420的第二开口422将助焊剂印刷到第一类焊盘3021和第二类焊盘3022的背离衬底的表面上，印刷完成之后，移除该网板420。
由于网板420在对应焊盘组302的中心区的位置没有设置开口，因此助焊剂不会被印刷到焊盘组302的中心区，从而不会导致助焊剂残留在焊盘组302的中心区，进而避免助焊剂腐蚀焊盘组302的各个焊盘和与各个焊盘连接的电子器件的对应引脚。在相关技术中，在对应每个焊盘组的位置处，网板220的开口222的数量为十二个；而在本公开的实施例中，在对应每个焊盘组302的位置处，网板420的第 二开口422的数量由十二个降低为四个，因此网板420的强度和张力相比于网板220的强度和张力有了显著提升。进一步地，第二开口422的数量的减少，可以有效保证网板420与基板脱离的精度。
S403：将多个电子器件固定在多个焊盘组远离衬底的一侧。
具体地，该步骤可以包括：将电子器件的每个引脚1041与相应一个焊盘对位，使电子器件的每个引脚1041在衬底上的第一正投影不超出相应一个焊盘在衬底上的第二正投影；利用焊料将电子器件的每个引脚1041焊接到相应一个焊盘。由于引脚1041的面向焊盘的表面已在前述步骤中蘸有包括锡的焊料，并且焊盘面向引脚1041的表面已被印刷有助焊剂，因此在引脚与焊盘的回流焊过程中，焊料中的锡与焊盘的表面材料可以生成金属间化合物，加之助焊剂的促进作用，因此引脚1041可以与焊盘实现可靠的电气连接。
参考图9，当焊盘组为焊盘组302时，将电子器件的每个引脚1041与相应一个焊盘对位的步骤可以包括以下子步骤：
使每个第一类焊盘3021的第一选定边3021A和第二选定边3021B与相应一个引脚1041的第一侧边1041A和第二侧边1041B在垂直于衬底的方向上分别对准，使每个第一类焊盘3021的第一非选定边3021C在衬底上的正投影与相应一个引脚1041的第三侧边1041C在衬底上的正投影相距D5，并且使每个第一类焊盘3021的第二非选定边3021D在衬底上的正投影与相应一个引脚1041的第四侧边1041D在衬底上的正投影相距D5，D5在20～50μm的范围内，例如可以是20μm，25μm，30μm，35μm，40μm，45μm，50μm等。另外，使每个第二类焊盘3022的第三选定边3022A和第四选定边3022B与相应一个引脚1041的第五侧边1041E和第六侧边1041F在垂直于衬底的方向上分别对准，使每个第二类焊盘3022的第一非选定边3022D在衬底上的正投影与相应一个引脚1041的第八侧边1041H在衬底上的正投影相距D3，D3在20～50μm的范围内，例如可以是20μm，25μm，30μm，35μm，40μm，45μm，50μm等，以及使每个第二类焊盘3022的第三非选定边3022C在衬底上的正投影与相应一个引脚1041的第七侧边1041G在衬底上的正投影相距D4，D4在0～30μm的范围内，例如可以是5μm，10μm，15μm，20μm，25μm，30μm等。
通过使第一类焊盘3021和第二类焊盘3022的选定边相对于引脚 1041的侧边不做外扩设计，可以避免由于相邻焊盘间距过小而导致引脚1041与相邻的焊盘发生接触从而引起短路；通过使第一类焊盘3021和第二类焊盘3022的非选定边相对于引脚1041的侧边分别进行一定程度的外扩，可以在保证避免短路的前提下尽量增大第一类焊盘3021和第二类焊盘3022的面向引脚1041的表面积，从而增大第一类焊盘3021和第二类焊盘3022与引脚1041的焊接接触面积，减少甚至避免由于引脚1041与第一类焊盘3021和第二类焊盘3022的接触面积不足导致的虚焊等焊接不良，从而提高焊接良率。
将理解的是，尽管术语第一、第二、第三等在本文中可以用来描述各种元件、部件、区、层和/或部分，但是这些元件、部件、区、层和/或部分不应当由这些术语限制。这些术语仅用来将一个元件、部件、区、层或部分与另一个区、层或部分相区分。因此，上面讨论的第一元件、部件、区、层或部分可以被称为第二元件、部件、区、层或部分而不偏离本公开的教导。
诸如“行”、“列”、“在…之下”、“在…之上”、“左”、“右”等等之类的空间相对术语在本文中可以为了便于描述而用来描述如图中所图示的一个元件或特征与另一个(些)元件或特征的关系。将理解的是，这些空间相对术语意图涵盖除了图中描绘的取向之外在使用或操作中的器件的不同取向。例如，如果翻转图中的器件，那么被描述为“在其他元件或特征之下”的元件将取向为“在其他元件或特征之上”。因此，示例性术语“在…之下”可以涵盖在…之上和在…之下的取向两者。器件可以取向为其他方式(旋转90度或以其他取向)并且相应地解释本文中使用的空间相对描述符。另外，还将理解的是，当层被称为“在两个层之间”时，其可以是在该两个层之间的唯一的层，或者也可以存在一个或多个中间层。
本文中使用的术语仅出于描述特定实施例的目的并且不意图限制本公开。如本文中使用的，单数形式“一个”、“一”和“该”意图也包括复数形式，除非上下文清楚地另有指示。将进一步理解的是，术语“包括”和/或“包含”当在本说明书中使用时指定所述特征、整体、步骤、操作、元件和/或部件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组的存在或添加一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组。如本文 中使用的，术语“和/或”包括相关联的列出项目中的一个或多个的任意和全部组合。在本说明书的描述中，参考术语“一个实施例”、“另一个实施例”等的描述意指结合该实施例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
将理解的是，当元件或层被称为“在另一个元件或层上”、“连接到另一个元件或层”、“耦合到另一个元件或层”或“邻近另一个元件或层”时，其可以直接在另一个元件或层上、直接连接到另一个元件或层、直接耦合到另一个元件或层或者直接邻近另一个元件或层，或者可以存在中间元件或层。相反，当元件被称为“直接在另一个元件或层上”、“直接连接到另一个元件或层”、“直接耦合到另一个元件或层”、“直接邻近另一个元件或层”时，没有中间元件或层存在。然而，在任何情况下“在…上”或“直接在…上”都不应当被解释为要求一个层完全覆盖下面的层。
本文中参考本公开的理想化实施例的示意性图示(以及中间结构)描述本公开的实施例。正因为如此，应预期例如作为制造技术和/或公差的结果而对于图示形状的变化。因此，本公开的实施例不应当被解释为限于本文中图示的区的特定形状，而应包括例如由于制造导致的形状偏差。因此，图中图示的区本质上是示意性的，并且其形状不意图图示器件的区的实际形状并且不意图限制本公开的范围。
除非另有定义，本文中使用的所有术语(包括技术术语和科学术语)具有与本公开所属领域的普通技术人员所通常理解的相同含义。将进一步理解的是，诸如那些在通常使用的字典中定义的之类的术语应当被解释为具有与其在相关领域和/或本说明书上下文中的含义相一致的含义，并且将不在理想化或过于正式的意义上进行解释，除非本文中明确地如此定义。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此。任何熟悉本技术领域的技术人员在本公开揭露的技术范 围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种布线基板，包括：
    衬底；
    多个焊盘组，位于所述衬底上，所述多个焊盘组中的每一个包括至少两个焊盘；
    其中，
    所述至少两个焊盘中的在第一方向或第二方向上相邻的两个焊盘间隔设置，所述第一方向与所述第二方向相交，
    所述至少两个焊盘中的每一个包括多条边，所述多条边包括至少一个选定边和至少一个非选定边，所述任一焊盘沿所述第一方向或所述第二方向与另一焊盘相邻，所述任一焊盘的选定边为所述多条边中面向相邻另一焊盘的边，并且所述任一焊盘的面向所述相邻另一焊盘的选定边和所述相邻另一焊盘的面向所述任一焊盘的选定边之间的间距大于或等于30um且小于100um。
  2. 根据权利要求1所述的布线基板，还包括位于所述多个焊盘组远离所述衬底一侧的绝缘层，其中，所述绝缘层包括多个第一开口，所述多个第一开口中的任一个第一开口与所述多个焊盘组中的一个焊盘组对应。
  3. 根据权利要求2所述的布线基板，其中，所述多个焊盘组中的任意一个焊盘组包括沿所述第一方向或所述第二方向间隔设置的两个焊盘，所述两个焊盘中的每一个的非选定边在所述衬底上的正投影与相应一个第一开口在所述衬底上的正投影的部分轮廓重合。
  4. 根据权利要求2所述的布线基板，其中，所述多个焊盘组中的任意一个焊盘组包括沿所述第一方向和所述第二方向阵列排布且间隔设置的四个焊盘，所述四个焊盘中的每一个的非选定边包括至少一个第一非选定边，所述第一非选定边在所述衬底上的正投影与相应一个第一开口在所述衬底上的正投影的部分轮廓重合。
  5. 根据权利要求4所述的布线基板，其中，每个焊盘的非选定边还包括一个第二非选定边，所述第二非选定边在所述衬底上的正投影与所述相应一个第一开口在所述衬底上的正投影的轮廓之间的最小间距为30～50um。
  6. 根据权利要求2所述的布线基板，其中，所述多个焊盘组中的任意一个焊盘组包括沿所述第一方向或所述第二方向间隔设置的多个焊盘，所述多个焊盘的几何中心沿顺时针方向依次连线构成凸多边形，所述多个焊盘中的每一个的非选定边包括至少一个第一非选定边，所述第一非选定边在所述衬底上的正投影与相应一个第一开口在所述衬底上的正投影的部分轮廓重合。
  7. 根据权利要求6所述的布线基板，其中，所述多个焊盘包括第一类焊盘和第二类焊盘，所述第一类焊盘的选定边包括第一选定边和第二选定边，所述第一选定边的延伸方向和所述第二选定边的延伸方向具有夹角，所述第二类焊盘的选定边包括第三选定边和第四选定边，所述第三选定边的延伸方向和所述第四选定边的延伸方向平行。
  8. 根据权利要求7所述的布线基板，其中，所述第一类焊盘与两个第二类焊盘分别在所述第一方向和所述第二方向上间隔设置，并且与所述第二类焊盘相邻的任一焊盘沿第一方向或第二方向和该第二类焊盘间隔设置。
  9. 根据权利要求7或8所述的布线基板，其中，每个第一类焊盘的非选定边还包括一个第二非选定边，所述第二非选定边在所述衬底上的正投影与所述相应一个第一开口在所述衬底上的正投影的轮廓之间的最小间距为30～50um。
  10. 根据权利要求7-9中任一项所述的布线基板，其中，每个第二类焊盘的非选定边还包括一个第三非选定边，所述第二类焊盘沿所述第一方向与一个第一类焊盘间隔设置，所述第二类焊盘的第三非选定边与所述第一类焊盘的第二选定边在所述第二方向上的间距大于0且小于或等于30um，所述第一类焊盘的第二选定边为该第一类焊盘的面向该第一类焊盘沿所述第二方向间隔设置的第二类焊盘的选定边。
  11. 根据权利要求7-9中任一项所述的布线基板，其中，每个第二类焊盘的非选定边还包括一个第三非选定边，所述第二类焊盘沿所述第二方向与一个第一类焊盘间隔设置，所述第二类焊盘的第三非选定边与所述第一类焊盘的第一选定边在所述第一方向上的间距大于0且小于或等于30um，所述第一类焊盘的第一选定边为该第一类焊盘的面向该第一类焊盘沿所述第一方向间隔设置的第二类焊盘的选定边。
  12. 根据权利要求2-11中任一项所述的布线基板，其中，所述绝 缘层所在层与所述多个焊盘组所在层之间没有设置其他膜层。
  13. 一种电子装置，包括根据权利要求1-12中任一项所述的布线基板以及多个电子器件，其中，所述多个电子器件位于所述多个焊盘组远离所述衬底的一侧，所述多个电子器件中的任一个电子器件与所述多个焊盘组中的一个焊盘组对应，所述多个电子器件中的每一个包括至少两个引脚，所述至少两个引脚中的任一个引脚与所述至少两个焊盘中的一个焊盘对应，并且电子器件的每个引脚与相应一个焊盘连接。
  14. 根据权利要求13所述的电子装置，其中，每个电子器件的引脚面向所述相应一个焊盘的表面的面积与所述相应一个焊盘面向所述引脚的表面的面积的比值为0.4～1.0。
  15. 根据权利要求13或14所述的电子装置，其中，每个电子器件的引脚在所述衬底上的第一正投影与所述相应一个焊盘在所述衬底上的第二正投影至少部分地重叠，所述第一正投影与所述第二正投影重叠的区域构成重叠区，所述重叠区的面积与所述第二正投影的面积的比值大于或等于39％。
  16. 根据权利要求13-15中任一项所述的电子装置，其中，绝缘层位于所述多个焊盘组和所述多个电子器件之间，所述多个电子器件中的任一个电子器件与所述绝缘层的多个第一开口中的一个第一开口对应，每个电子器件在所述衬底上的第三正投影落在相应一个第一开口在所述衬底上的第四正投影内，并且所述第三正投影的轮廓与所述第四正投影的轮廓之间的间距为20～40μm。
  17. 一种制造电子装置的方法，包括：
    提供衬底；
    在所述衬底上形成多个焊盘组，所述多个焊盘组中的每一个包括至少两个焊盘；以及
    将多个电子器件固定在所述多个焊盘组远离所述衬底的一侧，
    其中，所述多个电子器件中的任一个电子器件与所述多个焊盘组中的一个焊盘组对应，所述多个电子器件中的每一个包括至少两个引脚，所述至少两个引脚中的任一个引脚与所述至少两个焊盘中的一个焊盘对应，并且电子器件的每个引脚与相应一个焊盘连接。
  18. 根据权利要求17所述的方法，其中，在所述衬底上形成多个 焊盘组的步骤包括：
    在所述衬底上施加导电层，对所述导电层进行构图以形成多条信号线；
    在所述多条信号线远离所述衬底的一侧形成包括多个第一开口的绝缘层，利用所述第一开口暴露所述多条信号线中的每一条的一部分以形成所述焊盘。
  19. 根据权利要求18所述的方法，其中，将多个电子器件固定在所述多个焊盘组远离所述衬底的一侧的步骤包括：
    将电子器件的每个引脚与所述相应一个焊盘对位，使电子器件的每个引脚在所述衬底上的第一正投影不超出所述相应一个焊盘在所述衬底上的第二正投影；
    利用焊料将电子器件的每个引脚焊接到所述相应一个焊盘。
  20. 根据权利要求19所述的方法，其中，每个焊盘组包括沿所述第一方向或所述第二方向间隔设置的多个焊盘，所述多个焊盘包括第一类焊盘，所述第一类焊盘包括第一选定边和第二选定边以及第一非选定边和第二非选定边，所述第一选定边的延伸方向和所述第二选定边的延伸方向具有夹角，所述第一非选定边的延伸方向和所述第二非选定边的延伸方向具有夹角，
    其中，将电子器件的每个引脚与所述相应一个焊盘对位的步骤包括：
    使每个第一类焊盘的所述第一选定边和所述第二选定边与相应一个引脚的第一侧边和第二侧边在垂直于所述衬底的方向上分别对准，并且使每个第一类焊盘的所述第一非选定边和所述第二非选定边在所述衬底上的正投影与相应一个引脚的第三侧边和第四侧边在所述衬底上的正投影分别相距20～50μm。
  21. 根据权利要求20所述的方法，其中，所述多个焊盘还包括第二类焊盘，所述第二类焊盘包括第三选定边和第四选定边以及第一非选定边和第三非选定边，所述第三选定边的延伸方向和所述第四选定边的延伸方向平行，所述第一非选定边的延伸方向和所述第三非选定边的延伸方向平行，
    其中，将电子器件的每个引脚与所述相应一个焊盘对位的步骤还包括：
    使每个第二类焊盘的所述第三选定边和所述第四选定边与相应一个引脚的第五侧边和第六侧边在垂直于所述衬底的方向上分别对准，使每个第二类焊盘的所述第三非选定边在所述衬底上的正投影与相应一个引脚的第七侧边在所述衬底上的正投影相距0～30μm，并且使每个第二类焊盘的所述第一非选定边在所述衬底上的正投影与相应一个引脚的第八侧边在所述衬底上的正投影相距20～50μm，所述第三非选定边相对于所述第一非选定边更靠近所述焊盘组的中心。
  22. 根据权利要求21所述的方法，其中，每个焊盘组包括中心区和围绕在所述中心区外围的多个角落区，多个角落区中的每一个布置有至少一个第一类焊盘和至少一个第二类焊盘，
    其中，在将电子器件的每个引脚与所述相应一个焊盘对位之前，还包括：
    将网放置在所述多个焊盘组远离所处衬底的一侧，所述网包括多个第二开口，所述多个第二开口中的任一个第二开口与所述多个焊盘组的多个角落区中的一个角落区对应，所述多个第二开口中的每一个在所述衬底上的正投影与相应一个角落区内的至少一个第一类焊盘和至少一个第二类焊盘在所述衬底上的正投影部分地重叠；
    透过所述网板的第二开口将助焊剂印刷到第一类焊盘和第二类焊盘的远离所述衬底的表面上；
    移除所述网板。
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