WO2024046026A1 - 一种制备半导体器件的方法和装置以及半导体器件 - Google Patents

一种制备半导体器件的方法和装置以及半导体器件 Download PDF

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WO2024046026A1
WO2024046026A1 PCT/CN2023/111048 CN2023111048W WO2024046026A1 WO 2024046026 A1 WO2024046026 A1 WO 2024046026A1 CN 2023111048 W CN2023111048 W CN 2023111048W WO 2024046026 A1 WO2024046026 A1 WO 2024046026A1
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layer
ions
ion implantation
semiconductor body
contact surface
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PCT/CN2023/111048
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English (en)
French (fr)
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苏帅
何林峰
魏巍
张亚文
武龙
侯明辰
冯鹏
韩明涛
李皓天
周瑞
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华为技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Definitions

  • the present application relates to the technical field of semiconductor manufacturing, and more specifically, to a method and apparatus for preparing a semiconductor device and a semiconductor device.
  • HEMT high electron mobility transistor
  • the existing HEMT device preparation technology is difficult to further reduce the resistivity of the ohmic contact, or requires multiple ion implantations to form a larger ion peak concentration area in the epitaxial layer of the semiconductor body, but causes greater damage to the crystal lattice and requires longer injection times. It is also longer, which increases the preparation cost.
  • Embodiments of the present application provide a method and apparatus for preparing a semiconductor device and a semiconductor device to solve the problem of how to further reduce the ohmic contact and reduce the number of ion implantations during the preparation process of the HEMT device.
  • a method for preparing a semiconductor device includes: determining an ion implantation area on a cap layer of the semiconductor body.
  • the cap layer is the uppermost layer of the epitaxial layer of the semiconductor body.
  • the epitaxial layer also includes a barrier layer. , insertion layer and channel layer.
  • the ion implantation area is the entrance for ion implantation.
  • the semiconductor body has been completed with ion implantation and ion activation according to the first implantation parameters.
  • the first implantation parameters include: the preset first concentration, the preset third An injection current and a preset first injection energy; according to the first injection parameter, determine the peak concentration area position of ions in the epitaxial layer; determine the first depth according to the peak concentration area position of ions; according to the first depth, implant the ions with The area is the starting area, the epitaxial layer is etched and the first contact surface is exposed; a metal layer is deposited on the first contact surface; the metal layer is converted into an alloy layer through annealing, and an ohmic contact is formed on the first contact surface.
  • the above-mentioned capping layer is the uppermost layer in the epitaxial layer of the semiconductor body, and the epitaxial layer also includes a barrier layer, an insertion layer and a channel layer.
  • the semiconductor body mentioned in the embodiments of this application is a semiconductor device in the above preparation process, and may be a semi-finished product of the semiconductor device.
  • the ions when ions are incident on the epitaxial layer, the ions collide with the materials inside the epitaxial layer, consuming the energy given to the ions during the injection. When the energy is exhausted, the ions stop moving and stay in a certain part of the epitaxial layer. The specific location of the layer.
  • the first ion implantation parameters need to be set for the ion implanter, including a preset first concentration, a preset first implantation current, and a preset first implantation energy.
  • the second concentration of ions corresponding to the specific position of the implanted ions in each layer can be predicted based on the first implantation parameter. Further, the peak concentration can be determined by comparing the second concentration of ions corresponding to the specific position with the first concentration of ion implantation. The corresponding specific position; or, directly sample the material at the specific position in each layer of the semiconductor body, and detect the ion concentration at the corresponding sampling position through the sampled sample.
  • the above etching process may adopt a dry etching method, a wet etching method, or a combination of the two etching methods.
  • the first contact surface in the epitaxial layer due to the position of the first contact surface in the epitaxial layer, it is in the peak concentration region of the above-mentioned implanted ions. is located near 2DEG, that is, the first contact surface is near 2DEG. If the ohmic contact of the semiconductor device is formed here, the contact barrier can be effectively reduced to reduce the contact resistance. Furthermore, after the semiconductor body is annealed, the concentration distribution curve of the implanted ions in the epitaxial layer tends to be flat, so the sensitivity of the ion concentration to the depth of the ions is reduced. For example, the concentration changes extremely within the ⁇ 3 nm range of the peak concentration position.
  • ions forming the first contact surface of the ohmic contact can maintain a higher concentration, thereby further reducing the contact resistance of the ohmic contact of the semiconductor device.
  • a single ion injection can achieve the above effects, which not only saves time, but also avoids large damage to the crystal lattice caused by multiple ion injections.
  • the first cross-section is determined in the peak concentration area of ions, and the first cross-section is parallel to the epitaxial layer; the distance between the first cross-section and the upper surface of the capping layer is determined The vertical distance is the first depth.
  • the first depth is determined based on the position of the peak concentration area, so that the first contact surface exposed through the subsequent etching operation is near 2DEG, so that the contact barrier of the ohmic contact formed on the first contact surface is very low, and thus Reduce the contact resistance of ohmic contacts of semiconductor devices.
  • the above-mentioned ions include any one of the following elements: silicon element Si, germanium element Ge, and carbon element C.
  • the interval range of the first concentration is [10 18 , 10 22 ] cm -3 .
  • the first concentration of 10 22 cm -3 is the limit implantation concentration that the current ion implanter can achieve.
  • ion implanters can also perform ion implantation with a first concentration greater than 10 22 cm -3 , and the range of the first concentration will also be adjusted accordingly.
  • the above first concentration should not be too large.
  • the first concentration of 10 18 cm -3 is not the lower limit of the first concentration.
  • the first concentration can be appropriately lowered according to the specific scenario, such as 10 17 cm -3 .
  • the first concentration is controlled within the above-mentioned appropriate range to avoid that the ion concentration is too low, which will cause poor contact resistance reduction effect of the formed ohmic contact, and also to avoid that the ion concentration is too high, which will cause damage to the crystal lattice during implantation. is too big.
  • a first photoresist is coated on the capping layer, and the capping layer is modified based on the first photoresist.
  • the crystal lattice of the epitaxial layer can be effectively prevented from being damaged during the ion activation process.
  • a first dielectric layer is deposited on the capping layer; a first dielectric layer is coated on the first dielectric layer
  • Photoresist perform a photolithography operation on the first dielectric layer based on the first photoresist to form source and drain patterns on the first dielectric layer; perform ion implantation into the areas of the source and drain patterns; remove the first photoresist resist, and activate ions; remove the first dielectric layer.
  • the epitaxial layer can be effectively prevented from being damaged during the ion activation process.
  • the ions are activated through a rapid thermal treatment RTP annealing method or a laser annealing method.
  • the semiconductor lattice is broken or damaged due to ion implantation, which affects semiconductor parameters such as electron mobility and lifetime, and most of the ions are not located at the target location when injected. Therefore, electron mobility and other material parameters can be effectively restored through ion activation.
  • a second photoresist is coated on the cap layer of the semiconductor body, a photolithography operation is performed on the cap layer based on the first photoresist, and a source is formed on the cap layer.
  • the electrode and drain patterns, and the area of the source and drain patterns are ion implantation areas.
  • the subsequent etching process can be etched based on the ion implantation area, and the first contact surface exposed by subsequent etching can be near the peak concentration, that is, near 2DEG, so as to Contacts that reduce ohmic contact potential barrier, thereby reducing the contact resistance of ohmic contacts. It is an important step to achieve single ion implantation.
  • a metal layer is deposited on the upper surface of the semiconductor body; the metal layer and the second photoresist outside the ion implantation area are removed.
  • the upper surface of the semiconductor body includes the first contact surface and the upper surface of the non-etched area.
  • a metal layer is deposited on at least the first contact surface of the semiconductor body, so that it is subsequently converted into an alloy layer to form an ohmic contact on the first contact surface.
  • the first contact surface is located within ⁇ 10 nm of the heterojunction interface between the barrier layer and the channel layer.
  • the metal layer is four layers of metal, including a titanium Ti layer, an aluminum Al layer, an X layer, and a gold Au layer, where X is any metal element.
  • a semiconductor device including a semiconductor body.
  • the semiconductor body is implanted with ions.
  • the ions are implanted according to first implantation parameters.
  • the first implantation parameters include: a preset first concentration, a preset A first injection current and a preset first injection energy, the semiconductor body includes an epitaxial layer and a substrate, wherein the epitaxial layer is on the substrate, and the epitaxial layer includes a cap layer, a barrier layer, an insertion layer and a channel layer,
  • the cap layer is the uppermost layer of the epitaxial layer, the barrier layer is below the cap layer, the insertion layer is below the barrier layer, the channel layer is below the insertion layer and above the substrate, and the upper surface of the cap layer includes ion implantation area, the ion implantation area is used to inject ions into the semiconductor body.
  • the epitaxial layer includes a peak concentration area, which is the area with the largest ion concentration in the epitaxial layer.
  • the epitaxial layer has an etching area with a depth of the first depth.
  • the etching area includes a first contact surface, which is the lower surface of the etching region and is located below the ion implantation region.
  • the above-mentioned first depth is determined based on the position of the peak concentration region, and the position of the peak concentration region is determined based on the first implantation region.
  • the parameters are determined; the alloy layer is in contact with the first contact surface, and an ohmic contact is formed between the alloy layer and the first contact surface.
  • the alloy layer is a metal layer deposited on the first contact surface through annealing. transformed.
  • the first contact surface of the semiconductor body is located in the epitaxial layer near the peak concentration region of the implanted ions, that is, the first contact surface is near 2DEG. Therefore, the ohmic contact barrier of the manufactured semiconductor device is very small, the contact resistance is also very small, and the performance of the semiconductor device is also very good.
  • the ions implanted into the semiconductor body include any one of the following elements: silicon element Si, germanium element Ge, and carbon element C.
  • the interval range of the first concentration is [10 18 , 10 22 ]cm -3 .
  • the first concentration is controlled within the above appropriate range to avoid the ion concentration being too low, causing the problem of high contact resistance of the ohmic contact of the manufactured semiconductor device, and also to avoid the ion concentration being too high, causing the ohmic contact resistance of the manufactured semiconductor device to be high. Excessive lattice damage of semiconductor devices may cause functional failure.
  • the first contact surface is located within ⁇ 10 nm of the heterojunction interface between the barrier layer and the channel layer.
  • the metal layer is four layers of metal, including a titanium Ti layer, an aluminum Al layer, an X layer, and a gold Au layer, where X is any metal element.
  • a third aspect provides an apparatus for preparing a semiconductor device, which apparatus is used to perform the method in any possible implementation manner of the method design of the first aspect.
  • a device for determining a lighting scheme including a memory for storing computer instructions; and a processor for executing the computer instructions stored in the memory, so that the device executes the method design of the first aspect. method in any of the possible implementations.
  • a computer storage medium which is characterized in that computer instructions are stored in the computer storage medium.
  • the instructions When executed on a computer, they cause the computer to execute any possible implementation of the method design of the first aspect. method within the method.
  • a chip including a processor configured to execute the method in any possible implementation of the method design of the first aspect.
  • a seventh aspect provides a computer program product.
  • the computer program code or instructions are executed on a computer, the computer executes the method in any possible implementation of the method design of the first aspect.
  • Figure 1 is a HEMT device preparation system 100 provided by an embodiment of the present application.
  • FIG. 2 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a method for preparing a semiconductor device according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of the relationship between ion incidence depth and ion concentration during ion implantation according to an embodiment of the present application.
  • FIG. 5 is a schematic block diagram of an apparatus 500 for manufacturing a semiconductor device provided by an embodiment of the present application.
  • FIG. 6 is a schematic block diagram of a computer-readable storage medium 600 provided by an embodiment of the present application.
  • gallium nitride-based HEMT It is a semiconductor body that is composed of junctions between two materials with different band gaps through the use of two-dimensional electron gas (2DEG).
  • 2DEG two-dimensional electron gas
  • HEMT gallium nitride
  • GaN gallium nitride
  • gallium nitride transistors and integrated circuits are often used in circuits to improve efficiency, reduce size, and reduce the cost of various power conversion systems.
  • GaN-based power devices are significantly superior to silicon-based devices due to higher breakdown strength, faster switching, higher thermal conductivity and lower on-resistance.
  • GaN crystals can be grown on a variety of substrates, including sapphire, silicon carbide (SiC) and silicon (Si).
  • SiC silicon carbide
  • Si silicon
  • 2DEG can be created by growing a thin layer of aluminum gallium nitride (AlGaN) on top of a GaN crystal and applying stress at the interface. 2DEG can conduct electrons efficiently under the action of electric field.
  • AlGaN aluminum gallium nitride
  • 2DEG has high conductivity, partly because electrons are trapped in a very small area at the interface, which can increase the mobility of electrons from about 1000cm 2 /V ⁇ s before stress is applied to the 2DEG area. 1500 to 2000cm 2 /V ⁇ s. It can be seen that the high electron mobility of gallium nitride-based HEMT devices can achieve higher breakdown strength, faster switching, higher thermal conductivity and lower on-resistance.
  • a barrier layer is often formed.
  • the doping concentration of the semiconductor is very high, electrons can tunnel through the barrier to form a low-resistance ohmic contact.
  • Ohmic contact is very important to the semiconductor body. Forming a good ohmic contact is beneficial to the input and output of current.
  • alloys with different formulas are often selected as ohmic contact materials.
  • Ion implantation is a process in which ionized impurities are generated in a complex system of high vacuum to form a high-energy ion beam, which is injected into a solid material. During this process, the ions are gradually decelerated by the resistance of the solid material, and finally stay in the solid material. Compared with the diffusion process, ion implantation can control impurity doping more accurately, has strong repeatability, and can be performed at a lower process temperature. However, because high-energy ions lose energy due to collisions with electrons and atomic nuclei in solid materials, and finally stop at a certain depth in the crystal lattice, it inevitably causes fracture or damage to the semiconductor lattice. Therefore, subsequent annealing is required to remove these damages and activate ions.
  • the semiconductor can be annealed at the appropriate time and temperature.
  • the annealing method can also be used to anneal the above-deposited metal layer, so that the metal layer is converted into an alloy layer, and a contact surface between the alloy layer and the semiconductor is formed. Ohmic contact.
  • FIG. 1 shows a HEMT device preparation system 100 provided by an embodiment of the present application.
  • the preparation system 100 includes: a photolithography machine, an ion implanter, a cleaning equipment, a thin film deposition equipment, Etching machines, annealing equipment and control equipment.
  • the photolithography machine is used to coat photoresist on the surface of the epitaxial layer of the semiconductor body.
  • the semiconductor body includes an epitaxial layer and a substrate.
  • the epitaxial layer includes: a cap layer, a barrier layer, an insertion layer, and a trench.
  • channel layer, buffer layer, and the uppermost layer of the epitaxial layer can be the above-mentioned cap layer.
  • the substrate can include Si, C, Al, O, for example, it can be silicon (Si) and silicon carbide (SiC), or it can also be a substrate composed of other materials suitable for GaN crystal production such as sapphire (Al 2 O 3 ). end.
  • the capping layer includes Ga and N, and may be GaN, for example.
  • the barrier layer includes Al, N, and further includes Ga or In.
  • it may be aluminum gallium nitride (AlGaN) or aluminum indium nitride (InAlN).
  • the channel layer includes Ga and N, and may be a GaN channel, for example.
  • the insertion layer includes Al, N, and may be, for example, aluminum nitride (AlN). It should be understood that the insertion layer is very thin, such as 2 ⁇ 3nm, and is a very important layer of material in the process of semiconductor device preparation, because the surfaces of the above-mentioned barrier layer and GaN channel are very rough. If the above-mentioned barrier layer is combined with the above-mentioned Direct contact with the GaN channel will significantly reduce the conductivity of the channel and further reduce the electron mobility. The insertion layer can smooth the rough interface between the barrier layer and the GaN channel, thus improving the efficiency of the channel. electron mobility when the channel is turned on.
  • AlN aluminum nitride
  • the buffer layer is mainly used to bond the chemical bond between the GaN in the above-mentioned GaN channel and the substrate, thereby solving the problems of lattice mismatch, heterogeneous diffusion and polarity when growing GaN on the substrate, and ensuring that GaN can grow normally.
  • the above-mentioned photolithography machine is also used to perform exposure operations and development operations on the above-mentioned cap layer, and photoetch patterns of source and drain electrodes, that is, SD patterns, on the above-mentioned epitaxial layer.
  • the above-mentioned photoresist coating work can be completed by other special equipment or manually, which is not limited in the embodiments of the present application.
  • the ion implanter is used to perform an ion implantation operation on the area of the above-mentioned SD pattern, so that ions can be implanted into the above-mentioned epitaxial layer.
  • the target layer for ion implantation can be predicted, such as a barrier layer, an insertion layer, or a channel layer. It can also predict which layer in the epitaxial layer the peak concentration of implanted ions will be located after ion implantation.
  • the first injection parameters include a preset first concentration, a preset first injection current and a preset first injection energy.
  • the cleaning equipment has two main applications. On the one hand, it is used to clean the photoresist coated on the surface of the epitaxial layer; on the other hand, it is used to subsequently strip off the metal deposited outside the SD pattern area on the surface of the semiconductor body.
  • the two functions of the above-mentioned cleaning equipment can be deployed in two mutually independent devices, which is not limited in the embodiments of the present application.
  • Thin film deposition equipment mainly has two applications. On the one hand, it is used to deposit a dielectric layer on the surface of the above-mentioned cap layer; on the other hand, it is used to deposit a metal layer on the surface of the above-mentioned device.
  • the two functions of the above-mentioned thin film deposition equipment can be deployed in two mutually independent equipment, which is not limited in the embodiments of the present application.
  • the etching machine is used to etch the dielectric layer formed on the surface of the cap layer, and etch the SD pattern area into the barrier layer, the insertion layer, or the channel layer.
  • the annealing equipment is used to anneal the above-mentioned devices, activate the ions injected into the epitaxial layer, and repair the lattice damage caused by the ion injection.
  • the deposited metal layer retained on the surface of the above device is annealed to convert the metal layer into an alloy layer to form an ohmic contact.
  • the control device is used to send instruction information to the above-mentioned device and control the above-mentioned device to perform corresponding operations.
  • the control device can adjust the sequence and specific methods of corresponding operations performed by the above-mentioned device in real time according to the different preparation processes, thereby sending corresponding instruction information to the above-mentioned device.
  • Control devices include processors, memory, communication interfaces, transmitters and receivers.
  • the above computing device may be a server, and the server may be a local server or a cloud server, which is not limited in the embodiments of this application.
  • the above-mentioned processor may be a central processing unit (CPU) used to generate a control strategy to control the above-mentioned device to complete a series of operations.
  • CPU central processing unit
  • the above can be a volatile memory (random access memory, RAM) or a non-volatile memory (non-volatile memory, NVM), etc., which can be used to store the data required by the processor during the calculation process. data.
  • RAM random access memory
  • NVM non-volatile memory
  • the communication interface is used to communicate with the above-mentioned device, send instruction information or receive feedback information from the above-mentioned device.
  • the communication interface can also communicate with other devices, for example, with user devices such as monitors and keyboards.
  • FIG. 2 shows a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present application.
  • FIG. 3 shows a schematic diagram of a method for preparing a semiconductor device according to an embodiment of the present application, showing the state of the semiconductor body after each step in FIG. 2 .
  • the cap layer is the uppermost layer of the epitaxial layer of the semiconductor body, and the epitaxial layer also includes a barrier layer, an insertion layer and a channel layer.
  • the above-mentioned ion implantation area is the entrance position of the ion implanter to inject ions
  • the above-mentioned semiconductor body has previously completed corresponding operations of ion implantation and ion activation according to the first implantation parameter, wherein the first implantation parameter It includes: a preset first concentration, a preset first injection current and a preset first injection energy. It can be seen that before the above S210, the following operations need to be performed:
  • a layer of first photoresist 30 is coated on the capping layer 350 , and a photolithography operation is performed on the capping layer 350 based on the first photoresist 35 .
  • 340 represents the barrier layer
  • 330 represents the insertion layer
  • 320 represents the channel layer
  • 310 represents the buffer layer
  • 10 represents the substrate.
  • the above-mentioned first photoresist 35 includes a designated SD pattern. Therefore, before performing the photolithography operation, the photolithography parameters of the first photoresist 35 and the photolithography machine to be selected are determined according to the size of the semiconductor device itself to be prepared and the type of SD pattern that needs to be prepared. Then, a photolithography operation is performed. During the photolithography process, the photoresist 30 in the SD pattern area is removed, and finally the above-specified SD pattern 20 can be formed on the capping layer 350 . Outside the SD pattern 20 area, part of the first photoresist 30 is still retained.
  • the photolithography operation includes an exposure operation and a development operation.
  • the above SD pattern area is ion implanted based on the current semiconductor body.
  • the exposed areas on the surface of the capping layer are all SD pattern areas. Therefore, the ion implanter only needs to implant ions into the above-mentioned SD pattern area. .
  • N-type doping of GaN in the capping layer 350 can be formed through the above ion implantation operation.
  • the types of implanted ions include but are not limited to silicon (Si), germanium (Ge), carbon (C). ) and other ions that can achieve N-type doping of GaN, this application does not limit this.
  • the first concentration range interval of ion implantation may be [10 18 , 10 22 ] cm -3 .
  • the ions when ions are incident on the epitaxial layer through the SD pattern area, the ions collide with the material inside the epitaxial layer, consuming the energy given to the ions during the implantation. When the energy is exhausted, the ions stop Movement, staying at a specific location on a certain layer of the epitaxial layer.
  • ions are injected into the semiconductor body to change the ion concentration in the epitaxial layer of the semiconductor body, so that the properties of the original materials of each layer of the epitaxial layer are changed, which helps to form an ohmic contact resistance with low contact resistance. touch.
  • the first photoresist 30 outside the above-mentioned SD pattern area is removed to completely expose the upper surface of the capping layer 350 .
  • the first photoresist can be removed by using an organic cleaning agent.
  • the organic cleaning agent can be made by mixing acetone, isopropyl alcohol, absolute ethanol and other organic substances based on a certain ratio.
  • the first dielectric layer 360 is deposited on the capping layer 350 .
  • atomic layer deposition ALD
  • PEALD plasma enhanced atomic layer deposition
  • LPCVD low pressure chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • sputtering deposition and other methods to deposit a silicon dioxide or silicon nitride film with a thickness of 10 to 200 nm on the capping layer 350.
  • the embodiments of this application specifically adopt The deposition method of the first dielectric layer, the material composition of the formed first dielectric layer, and the specific thickness of the first dielectric layer are not limited.
  • the ions implanted into the epitaxial layer are activated.
  • the implanted ions can be activated by annealing in a rapid thermal processing (RTP) annealing furnace or laser annealing. This application does not limit the specific annealing method.
  • RTP rapid thermal processing
  • the above-deposited first dielectric layer 360 is mainly used to protect the above-mentioned semiconductor body during the ion activation process.
  • ion activation is performed through RTP annealing method, due to the annealing process, the direct heating surface of the semiconductor body The first introduction to the above quality layer 360, so the epitaxial layer will not be directly heated.
  • the epitaxial layer can be effectively prevented from being damaged by high temperature.
  • the dielectric layer on the epitaxial layer can be removed by dry etching.
  • a dry etching operation can be performed by an advanced oxide etcher (AOE) to complete the above.
  • AOE advanced oxide etcher
  • the operation of removing the first dielectric layer 360 can also be completed through a wet etching operation.
  • the above-mentioned removal of the first dielectric layer 360 can also be accomplished by a combination of dry etching and wet etching. The embodiments of the present application do not limit this.
  • the related process flow of the above-mentioned ion implantation and ion activation is to first perform ion implantation on the SD pattern area, and then deposit the first dielectric layer 360 on the surface of the above-mentioned capping layer 350, and then perform subsequent steps. Ion activation and corresponding operations of removing first dielectric layer 360 .
  • the related process flow of the above-mentioned ion implantation and ion activation may also be to first deposit the first dielectric layer 360 on the surface of the above-mentioned capping layer 350 .
  • a layer of first photoresist 30 is coated on the surface of the first dielectric layer 360 , and a photolithography operation is performed on the first dielectric layer 360 based on the first photoresist 35 , so that in the first An SD pattern is formed on the dielectric layer.
  • ions are implanted into the SD pattern area on the first dielectric layer 60 .
  • the first dielectric layer 360 is removed to completely expose the upper surface of the capping layer 350 .
  • the ion implantation area on the capping layer of the semiconductor body proposed in S210 can be determined by the following method.
  • the first photoresist 35 is used to perform photolithography on the semiconductor body.
  • a second photoresist 31 can be coated on the capping layer of the semiconductor body, and a second photolithography operation is performed on the capping layer 350 based on the above-mentioned first photoresist 35, so that the capping layer 350 The above-mentioned SD pattern is formed again.
  • the position of the photolithographic SD pattern needs to be aligned so that the positions of the SD patterns of the two photolithographs are consistent. That is, the SD pattern areas of the two lithographs should overlap.
  • the SD pattern area photolithographed on the capping layer 350 for the second time is the above-mentioned ion implantation area.
  • S220 Determine the peak concentration region position of the ions in the epitaxial layer according to the first implantation parameter.
  • a simulation experiment is performed on the ion implantation process, the specific parameter values included in the first implantation parameters are adjusted, and the ions in the epitaxial layer corresponding to each parameter at different values are determined and recorded. The location of the peak concentration area.
  • the value of the first implantation parameter is determined, and then the location of the peak concentration region of ions in the epitaxial layer can be determined based on the first implantation parameter.
  • the above-mentioned first injection parameters include a preset first concentration, a preset first injection current and a preset first injection energy, wherein the first concentration can also be determined by the first injection dose or the first injection dose.
  • an implanted ion areal density instead.
  • the injection current affects the number of implanted ions per unit time, which in turn affects the injection time of a specified dose of ions. The longer the injection time, the higher the cost of manufacturing semiconductors, so the injection current is not easy to be too small. However, it is not easy to be too large. Excessive injection current will cause greater lattice damage to the semiconductor device.
  • the first implantation parameter also includes a first implantation angle, a first temperature, etc., where the first implantation angle is an angle from the vertical direction.
  • these two parameters are usually not adjusted. After the above specific parameters are determined, the location of the peak concentration area of ions in the above epitaxial layer can be determined.
  • the first injection energy is 30keV
  • the first injection dose is e 15 /cm 2
  • the first injection current is 70 ⁇ A
  • the first injection angle is 7°
  • the first injection temperature is 25°C.
  • the first injection energy is 50keV
  • the first injection dose is e 15 /cm 2
  • the first injection current is 100 ⁇ A
  • the first injection angle is 7°
  • the first injection temperature is 25°C.
  • the peak concentration region of ions in the epitaxial layer was determined to be approximately 250 nm from the upper surface of the capping layer.
  • the corresponding first implantation parameters can be preset before ion implantation, so that the peak concentration region position of the ions implanted into the semiconductor body can be predicted.
  • FIG. 4 shows a schematic diagram of the relationship between ion incident depth and ion concentration during the ion implantation process provided by the embodiment of the present application.
  • the ordinate of the two-dimensional coordinate system is the ion incident depth
  • the abscissa is the second concentration of ions at this depth. It can be seen that the second concentration of ions and the ion incident depth present a Gaussian distribution as a whole. Therefore, there is a position corresponding to the peak concentration in the ion incident area, and 2DEG is gathered at this position. If an ohmic contact is formed here , it is helpful to reduce the contact barrier, thereby reducing the contact resistance. It can be seen that the greater the ion concentration at the contact surface of ohmic contact, the smaller the contact resistance formed.
  • the peak concentration of ions is located in the channel layer 320, so if the contact surface of the ohmic contact is disposed there, the contact resistance here will be minimum. For this reason, the second concentration of ions in each layer needs to be determined before proceeding to subsequent steps.
  • the first ion implantation parameters need to be set for the ion implanter, including a preset first concentration, a preset first injection current, and a preset first implantation energy. wait.
  • the second concentration of ions corresponding to specific positions of the implanted ions in each layer can be predicted based on the first ion implantation parameters.
  • the peak value can be determined by comparing the second concentration of ions corresponding to the specific position with the first concentration of ion implantation.
  • the specific location corresponding to the concentration is directly sampled at specific locations in each layer of the semiconductor body, and the ion concentration corresponding to the sampling location is detected through the sampled sample.
  • the first contact surface exposed through the subsequent etching operation is located near the 2DEG, so that the contact barrier of the ohmic contact formed on the first contact surface is very low, thereby reducing the contact resistance of the ohmic contact of the semiconductor device.
  • a first cross-section is determined in a peak concentration region of ions in the epitaxial layer, and the first cross-section is parallel to the epitaxial layer;
  • the vertical distance between the first cross-section and the above-mentioned capping layer 350 can be determined as the above-mentioned first depth.
  • the above-mentioned epitaxial layer can be etched starting from the ion implantation region through dry etching.
  • the epitaxial layer can be etched by an advanced oxide etching machine ( Advanced oxide etcher (AOE) performs dry etching operations to complete the above etching operations; dry etching operations can also be performed through inductively coupled plasma (inductively coupled plasma, ICP) etching machines; of course, wet etching operations can also be performed
  • AOE Advanced oxide etcher
  • ICP inductively coupled plasma
  • wet etching operations can also be performed
  • the above etching operation can be completed by performing an etching operation; the above etching operation can also be completed by a combination of dry etching and wet etching, which is not limited in the embodiments of the present application.
  • the epitaxial layer is etched into the channel layer 320 determined in the above process, and at this time, the upper surface of the channel layer 320 exposed in the etched area is the above-mentioned
  • the first contact surface in the epitaxial layer is near the peak concentration of the implanted ions, the first contact surface is located near 2DEG. If the ohmic contact of the semiconductor device is formed here, the contact barrier can be effectively reduced to reduce the contact resistance.
  • the first contact surface is usually located ⁇ 10 nm from the heterojunction interface between the barrier layer 340 and the channel layer 320 . Therefore, under the premise of limited equipment conditions, there is no need to determine the peak concentration position of implanted ions in the epitaxial layer, and the epitaxial layer can be etched to the barrier by calculating the position of the heterojunction interface between the barrier layer 340 and the channel layer 320 ⁇ 10 nm from the heterojunction interface between layer 340 and channel layer 320, the exposed first contact surface at this time is usually also near 2DEG.
  • methods such as electron beam evaporation or sputter deposition can be used to deposit a metal layer 40 on the upper surface of the current state of the epitaxial layer, where the metal layer consists of a four-layer metal structure. It is composed of, for example, Ti/Al/X/Au, where X can be any metal, for example, X can be Ti, etc.
  • the above-mentioned metal layer 40 first needs to be deposited on the upper surface of the epitaxial layer in its current state, that is, in the non-etched area of the epitaxial layer, corresponding to the upper surface of the second photoresist 30, and the etched area of the epitaxial layer, Corresponding to the exposed first contact surface of the channel layer 320 .
  • the metal layer 40 deposited on the surface of the non-etched area is not useful for semiconductor device preparation, so the metal layer 40 deposited on the surface of the non-etched area can be removed.
  • the third photoresist can be removed by using the above-mentioned organic solvent.
  • the metal 40 layer deposited on the second photoresist 30 is peeled off.
  • the metal layer 40 in the non-etched area can be peeled off by heating the N-methylpyrrolidone (NMP) solution water.
  • NMP N-methylpyrrolidone
  • the etching method can be used to The metal layer 40 in the non-etched area is removed.
  • S260 Convert the metal layer into an alloy layer through annealing, and form ohmic contact on the first contact surface.
  • metal annealing can be performed through an RTP rapid annealing furnace or laser annealing, as shown in (p) of FIG. 3 , to convert the above metal layer 40 into an alloy layer 50 to achieve the above first contact surface. Form ohmic contact.
  • the first contact surface in the epitaxial layer is located near 2DEG. If the ohmic contact of the semiconductor device is formed here, the contact barrier can be effectively reduced to reduce the contact resistance. Furthermore, after the semiconductor body is annealed, the concentration distribution curve of the implanted ions in the epitaxial layer tends to be flat, so the sensitivity of the ion concentration to the depth of the ions is reduced. For example, the concentration changes extremely within the ⁇ 3 nm range of the peak concentration position.
  • ions forming the first contact surface of the ohmic contact can maintain a higher concentration, thereby further reducing the contact resistance of the ohmic contact of the semiconductor device.
  • a single ion injection can achieve the above effects, which not only saves time, but also avoids large damage to the crystal lattice caused by multiple ion injections.
  • the embodiment of the present application proposes a semiconductor device.
  • the semiconductor device can be a final semiconductor device as shown in Figure 1, or can be as shown in Figure 3 (( The semiconductor device shown in p), the semiconductor device includes:
  • a semiconductor body the semiconductor body is implanted with ions, and the ions are implanted according to first implantation parameters.
  • the first implantation parameters include: a preset first concentration, a preset first injection current, and a preset first injection energy.
  • the semiconductor body includes an epitaxial layer and a substrate, where the epitaxial layer is on the substrate, the epitaxial layer includes a cap layer, a barrier layer, an insertion layer and a channel layer, the cap layer is the uppermost layer of the epitaxial layer, and the barrier layer Below the capping layer, the insertion layer is below the barrier layer, the channel layer is below the insertion layer and above the substrate, the upper surface of the capping layer includes an ion implantation region, and the ion implantation region is used to inject ions into the semiconductor body.
  • the epitaxial layer includes a peak concentration area, which is the area with the largest ion concentration in the epitaxial layer, the epitaxial layer has an etching area with a first depth, the etching area includes a first contact surface, and the first contact surface is the lower surface of the etching area, located below the ion implantation area, the above-mentioned first depth is determined based on the position of the peak concentration area, and the location of the peak concentration area is determined based on the first implantation parameter;
  • An alloy layer is in contact with the first contact surface, and an ohmic contact is formed between the alloy layer and the first contact surface.
  • the alloy layer is transformed from the metal layer deposited on the first contact surface through annealing.
  • the first contact surface of the semiconductor body is located in the epitaxial layer near the peak concentration region of the implanted ions, that is, the first contact surface is near 2DEG. Therefore, the ohmic contact barrier of the manufactured semiconductor device is very small, the contact resistance is also very small, and the performance of the semiconductor device is also very good.
  • the above-mentioned first depth is the vertical distance between the first cross-section and the upper surface of the capping layer, the first cross-section is parallel to the epitaxial layer, and the first cross-section is determined according to the peak concentration of ions. area determined.
  • the first contact surface of the semiconductor body exposed through the etching operation is near the 2DEG, so that the contact barrier of the ohmic contact formed on the first contact surface is very low, and thus the ohmic contact of the manufactured semiconductor device is The resistance is very low and the performance of the semiconductor device is also very good.
  • the ions implanted into the semiconductor body include any one of the following elements: silicon element Si, germanium element Ge, and carbon element C.
  • the interval range of the first concentration is [10 18 , 10 22 ] cm -3 .
  • the first concentration is controlled within the above appropriate range to avoid the ion concentration being too low, causing the problem of high contact resistance of the ohmic contact of the manufactured semiconductor device, and also to avoid the ion concentration being too high, causing the ohmic contact resistance of the manufactured semiconductor device to be high. Excessive lattice damage of semiconductor devices may cause functional failure.
  • the first contact surface is located within ⁇ 10 nm of the heterojunction interface between the barrier layer and the channel layer.
  • the above metal layer is four layers of metal, including a titanium Ti layer, an aluminum Al layer, an X layer, and a gold Au layer, where X is any metal element.
  • embodiments of the present application also provide a device for implementing any of the above methods.
  • a device for preparing a semiconductor device is provided.
  • the device includes a unit (or means) for implementing any of the above methods for preparing a semiconductor device. ).
  • FIG. 5 shows a schematic block diagram of an apparatus 500 for manufacturing a semiconductor device provided by an embodiment of the present application.
  • the Device 500 includes:
  • Determining unit 510 is used to determine the ion implantation area on the cap layer of the semiconductor body.
  • the cap layer is the uppermost layer of the epitaxial layer of the semiconductor body.
  • the epitaxial layer also includes a barrier layer, an insertion layer and a channel layer.
  • the ion implantation area is Is the entrance for ion implantation.
  • the semiconductor body has been implanted and activated according to the first implantation parameters.
  • the first implantation parameters include: a preset first concentration, a preset first injection current and a preset first implantation. Energy; determine the location of the peak concentration area of ions in the epitaxial layer according to the first injection parameter; determine the first depth based on the location of the peak concentration area of ions.
  • the operation unit 520 is used to etch the epitaxial layer and expose the first contact surface according to the first depth, using the ion implantation area as the starting area; deposit a metal layer on the first contact surface; and transform the metal layer through annealing. It is an alloy layer and forms ohmic contact on the first contact surface.
  • the above-mentioned determination unit 510 is specifically configured to determine a first cross-section in the peak concentration area of ions, where the first cross-section is parallel to the epitaxial layer; determine the relationship between the first cross-section and the upper surface of the capping layer. The vertical distance between them is the first depth.
  • the above-mentioned operating unit 520 is also used to coat the first photoresist on the capping layer, and perform the first photoresist on the capping layer based on the first photoresist.
  • Photolithography operation forming source and drain patterns on the cap layer; performing ion implantation on the regions of the source and drain patterns; removing the first photoresist; depositing the first dielectric layer on the cap layer and activating the ions; Remove the first dielectric layer.
  • the above-mentioned operation unit 520 is also used to deposit a first dielectric layer on the cap layer; coat the first dielectric layer with the first light Resist: perform a photolithography operation on the first dielectric layer based on the first photolithography plate to form source and drain patterns on the first dielectric layer; perform ion implantation on the regions of the source and drain patterns; remove the first photolithography glue, and activate ions; remove the first dielectric layer.
  • the above-mentioned operating unit 520 is specifically configured to activate ions through an RTP annealing method or a laser annealing method.
  • the above-mentioned operation unit 520 is specifically used to apply a second photoresist on the cap layer of the semiconductor body, perform a photolithography operation on the cap layer based on the first photoresist, and form a source on the cap layer. and drain patterns, and the regions of the source and drain patterns are ion implantation regions.
  • the above-mentioned operation unit 520 is specifically used to deposit a metal layer on the upper surface of the semiconductor body and remove the metal layer and the second photoresist outside the ion implantation area.
  • FIG. 6 is a schematic block diagram of a computer-readable storage medium 600 provided by an embodiment of the present application.
  • the computer-readable storage medium 600 shown in FIG. 6 stores computer instructions 610.
  • the computer instructions 610 are executed by the processor, the method shown in FIG. 2 can be implemented.
  • the computer-readable storage medium 600 can be any available media that can be accessed by a computer or a data storage device such as a server or a data center that contains one or more sets of available media.
  • Usable media may be magnetic media (eg, floppy disk, hard disk, magnetic tape), optical media (eg, DVD), or semiconductor media.
  • the semiconductor medium may be a solid state drive.
  • the above embodiments may be implemented in whole or in part by software, hardware, firmware, or any other combination.
  • the above-described embodiments may be implemented in whole or in part in the form of a computer program product.
  • a computer program product includes one or more computer instructions or computer programs. When computer instructions or computer programs are loaded or executed on a computer, processes or functions according to embodiments of the present application are generated in whole or in part.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device.
  • Computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, e.g., computer instructions may be transmitted from a website, computer, server or data center via a wired link (e.g. Infrared, wireless, microwave, etc.) method to transmit to another website, computer, server or data center.
  • a wired link e.g. Infrared, wireless, microwave, etc.
  • the disclosed systems, devices and methods can be implemented through other methods.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or can be integrated into another system, or some features can be ignored, or not implemented.
  • the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application can be integrated into one processing unit, each unit can exist physically alone, or two or more units can be integrated into one unit.
  • the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product.
  • the computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory, magnetic disk or optical disk and other media that can store program code.

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Abstract

本申请实施例提供了一种制备半导体器件的方法和装置以及半导体器件。涉及半导体制造技术领域，该方法包括：确定半导体本体的盖帽层上的离子注入区域，半导体本体已被按照第一注入参数完成所述离子注入和离子激活；根据第一注入参数，确定外延层中离子的峰值浓度区域位置；根据离子的峰值浓度区域位置，确定第一深度；根据第一深度，以离子注入区域为起始区域，刻蚀外延层并暴露第一接触面；在第一接触面上沉积金属层；通过退火的方法，将金属层转化为合金层，并在第一接触面形成欧姆接触。基于该方法，使形成欧姆接触的第一接触面处于2DEG附近，能够降低接触势垒，减小接触电阻，且单次注入即可完成，避免多次注入对晶格造成较大损伤。

Description

一种制备半导体器件的方法和装置以及半导体器件
本申请要求于2022年8月31日提交中国专利局、申请号为202211053439.1、发明名称为“一种制备半导体器件的方法和装置以及半导体器件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体制造技术领域，并且更具体地，涉及一种制备半导体器件的方法和装置以及半导体器件。
背景技术
高电子迁移率晶体管(high electron mobility transistor，HEMT)器件因其优异的材料及器件特性，使其应用于微波射频领域可以在高频特性下实现更高的输出功率和效率，同时其更大的带宽可以有效减小当前传统射频功率放大器的数量，有利于减小体积和优化成本。欧姆接触是HEMT半导体本体制备过程中最关键的工艺之一，欧姆接触电阻率的大小直接决定着器件的输出性能，制备低接触电阻率、高可靠性、高均匀性的欧姆接触工艺是器件制备中追求的重要目标。但是，现有的HEMT器件制备技术难以进一步降低欧姆接触的电阻率，或者需要进行多次离子注入，在半导体本体外延层中形成较大离子峰值浓度区域，但对晶格损伤较大，注入时间也较长，增加了制备成本。
因此，如何在HEMT器件制备过程中在减少离子注入次数的同时，进一步降低欧姆接触是现阶段亟需解决的技术问题。
发明内容
本申请实施例提供一种制备半导体器件的方法和装置以及半导体器件，以解决如何在HEMT器件制备过程中进一步降低欧姆接触，并减少离子注入次数的问题。
第一方面，提供了一种制备半导体器件的方法，该方法包括：确定半导体本体的盖帽层上的离子注入区域，盖帽层是半导体本体的外延层中的最上层，外延层还包括势垒层、插入层和沟道层，离子注入区域是离子注入的入口，半导体本体已被按照第一注入参数完成离子注入和离子激活，第一注入参数包括：预设的第一浓度、预设的第一注入电流和预设的第一注入能量；根据第一注入参数，确定外延层中离子的峰值浓度区域位置；根据离子的峰值浓度区域位置，确定第一深度；根据第一深度，以离子注入区域为起始区域，刻蚀外延层并暴露第一接触面；在第一接触面上沉积金属层；通过退火的方法，将金属层转化为合金层，并在第一接触面形成欧姆接触。
示例地，上述盖帽层是半导体本体的外延层中的最上层，外延层还包括势垒层、插入层和沟道层。应理解，本申请实施例提及的半导体本体为上述制备过程中的半导体器件，可以是半导体器件的半成品。
示例地，在离子入射到外延层时，离子与外延层内部的材料进行碰撞，消耗离子在注入时所被赋予的能量，当能量消耗殆尽时，离子停止运动，停留在外延层的某一层的具体位置。
示例地，在上述进行离子注入之前，需要为离子注入机设置离子第一注入参数，包括预设的第一浓度、预设的第一注入电流和预设的第一注入能量。可以基于第一注入参数，预测注入的离子在各层中具体位置对应的离子的第二浓度，进一步地，通过比较具体位置对应的离子的第二浓度与离子注入的第一浓度能够确定峰值浓度对应的具体位置；或者，直接对半导体本体各层中具体位置进行物质采样，通过采样的样本检测其对应采样位置的离子浓度。
示例地，上述刻蚀的过程可以采用干法刻蚀的方法，也可以采用湿法刻蚀的方法，还可以将两种刻蚀的方法相结合。
基于上述技术方案，由于第一接触面在外延层内的位置，正处于上述注入离子的峰值浓度区域位 置附近，即第一接触面处于2DEG附近。若在此处形成半导体器件的欧姆接触，可以有效降低接触势垒，以减小接触电阻。进一步地，由于半导体本体经过退火后，其外延层内注入离子的浓度分布曲线趋于平缓，所以使离子浓度对离子所处深度的敏感度降低，例如，峰值浓度位置±3nm范围内浓度变化极小，使形成欧姆接触的第一接触面的离子能够维持较高浓度，从而进一步降低半导体器件欧姆接触的接触电阻。并且单次离子注入即可达到上述效果，不仅节省时间，还避免多次离子注入对晶格造成较大的损伤。
结合第一方面，在第一方面的某些实现方式中，在离子的峰值浓度区域中确定第一横截面，第一横截面与外延层平行；确定第一横截面与盖帽层上表面之间的垂直距离为第一深度。
基于上述技术方案，基于峰值浓度区域位置确定第一深度，使后续经过刻蚀操作暴露的第一接触面处于2DEG附近，从而使在第一接触面形成的欧姆接触的接触势垒很低，进而降低半导体器件欧姆接触的接触电阻。
结合第一方面，在第一方面的某些实现方式中，上述离子包括以下任一种元素：硅元素Si、锗元素Ge、碳元素C。
结合第一方面，在第一方面的某些实现方式中，第一浓度的区间范围是[1018,1022]cm-3。
示例地，第一浓度为1022cm-3是现阶段离子注入机能够达到的极限注入浓度。但是，随着技术发展，离子注入机也可以实现以大于1022cm-3的第一浓度进行离子注入，届时第一浓度的区间范围也会随之调整。
应理解，对于形成良好的欧姆接触，离子注入的第一浓度是越大越好，但是过高的离子浓度会导致在离子注入期间对半导体本体的晶格损伤过大，所以，综合上述两方面的因素，上述第一浓度不宜过大。
示例地，第一浓度为1018cm-3也不是第一浓度的下限，可以根据具体场景，适当下调第一浓度，例如1017cm-3。
基于上述技术方案，将第一浓度控制在上述合适的范围内，避免离子浓度过低，使形成的欧姆接触的接触电阻下降效果差，也避免离子浓度过高，在注入的时候对晶格损伤过大。
结合第一方面，在第一方面的某些实现方式中，在确定半导体本体的盖帽层上的离子注入区域之前，在盖帽层上涂覆第一光刻胶，基于第一光刻板对盖帽层进行光刻操作，在盖帽层上形成源极和漏极图案；对源极和漏极图案的区域进行离子注入；去除第一光刻胶；在盖帽层上沉积第一介质层，并激活离子；去除第一介质层。
基于上述技术方案，能够有效防止外延层的晶格在离子激活过程中损伤。
结合第一方面，在第一方面的某些实现方式中，在确定半导体本体的盖帽层上的离子注入区域之前，在盖帽层上沉积第一介质层；在第一介质层上涂覆第一光刻胶，基于第一光刻板对第一介质层进行光刻操作，在第一介质层上形成源极和漏极图案；对源极和漏极图案的区域进行离子注入；去除第一光刻胶，并激活离子；去除第一介质层。
基于上述技术方案，能够有效防止外延层在离子激活过程中损伤。
结合第一方面，在第一方面的某些实现方式中，通过快速热处理RTP退火的方法或者激光退火的方法，激活离子。
基于上述技术方案，由于离子注入造成了半导体晶格断裂或损伤，使电子迁移率和寿命等半导体参数都受到了影响，而且大部分的离子在被注入时并不位于目标位置。因此，通过离子激活的方式，能够有效恢复电子迁移率与其他材料参数。
结合第一方面，在第一方面的某些实现方式中，在半导体本体的盖帽层上涂覆第二光刻胶，基于第一光刻板对盖帽层进行光刻操作，在盖帽层上形成源极和漏极图案，源极和漏极图案的区域为离子注入区域。
应理解，两次基于第一光刻板对半导体本体进行光刻的过程中，需要对准光刻源极和漏极图案的区域，使两次光刻的源极和漏极图案的区域的位置是一致的，即两次光刻的源极和漏极图案的区域应该是重合的。
基于上述技术方案，通过复用第一光刻板，保障了后续刻蚀过程中能够基于离子注入区域进行刻蚀，保障后续刻蚀暴露的第一接触面能够处于峰值浓度附近，即2DEG附近，以降低欧姆接触的接触 势垒，从而降低欧姆接触的接触电阻。是实现单次离子注入的重要步骤。
结合第一方面，在第一方面的某些实现方式中，在半导体本体的上表面沉积金属层；去除离子注入区域之外的金属层和第二光刻胶。
应理解，半导体本体的上表面包括第一接触面和非刻蚀区域的上表面。
基于上述技术方案，至少在半导体本体的第一接触面沉积金属层，以使得后续将其转化为合金层，在第一接触面上形成欧姆接触。
结合第一方面，在第一方面的某些实现方式中，上述第一接触面位于势垒层与沟道层之间的异质结界面±10nm范围内。
结合第一方面，在第一方面的某些实现方式中，金属层为四层金属，包括钛Ti层、铝Al层、X层、金Au层，其中X为任一种金属元素。
第二方面，提供了一种半导体器件，包括半导体本体，该半导体本体注入有离子，该离子是按照第一注入参数注入的，该第一注入参数包括：预设的第一浓度、预设的第一注入电流和预设的第一注入能量，该半导体本体包括外延层和衬底，其中，外延层在衬底之上，外延层包括盖帽层、势垒层、插入层和沟道层，盖帽层为外延层的最上层，势垒层在盖帽层之下，插入层在势垒层之下，沟道层在插入层之下且在衬底之上，盖帽层的上表面包括离子注入区域，离子注入区域用于向半导体本体注入离子，外延层中包括峰值浓度区域，该峰值浓度区域是外延层中离子浓度最大的区域，外延层具有深度为第一深度的刻蚀区域，刻蚀区域包括第一接触面，该第一接触面为刻蚀区域的下表面，位于离子注入区域的下方，上述第一深度是根据峰值浓度区域位置确定的，该峰值浓度区域位置是根据第一注入参数确定的；合金层，该合金层与第一接触面接触，该合金层与第一接触面之间形成有欧姆接触，该合金层是在第一接触面上沉积的金属层通过退火的方法转化的。
基于上述技术方案，该半导体本体的第一接触面在外延层内的位置，正处于上述注入离子的峰值浓度区域位置附近，即第一接触面处于2DEG附近。因此制成后的半导体器件的欧姆接触接触势垒很小，进而接触电阻也很小，半导体器件的性能也很好。
结合第二方面，在第二方面的某些实现方式中，注入半导体本体的离子包括以下任一种元素：硅元素Si、锗元素Ge、碳元素C。
结合第二方面，在第二方面的某些实现方式中，第一浓度的区间范围是[1018,1022]cm-3。
基于上述技术方案，将第一浓度控制在上述合适的范围内，避免离子浓度过低，造成制成的半导体器件的欧姆接触的接触电阻较高的问题，也避免离子浓度过高，造成制成的半导体器件晶格损伤过大致使功能失效的问题。
结合第二方面，在第二方面的某些实现方式中，第一接触面位于势垒层与沟道层之间的异质结界面±10nm范围内。
结合第二方面，在第二方面的某些实现方式中，金属层为四层金属，包括钛Ti层、铝Al层、X层、金Au层，其中X为任一种金属元素。
第三方面，提供了一种制备半导体器件的装置，该装置用于执行上述第一方面的方法设计中任意一种可能的实现方式中的方法。
第四方面，提供了一种确定打光方案的装置，包括存储器，用于存储计算机指令；还包括处理器，用于执行存储器中存储的计算机指令，以使得装置执行上述第一方面的方法设计中任意一种可能的实现方式中的方法。
第五方面，提供了一种计算机存储介质，其特征在于，计算机存储介质中存储有计算机指令，该指令在计算机上执行时，使得计算机执行上述第一方面的方法设计中任意一种可能的实现方式中的方法。
第六方面，提供了一种芯片，包括处理器，该处理器用于执行上述第一方面的方法设计中任意一种可能的实现方式中的方法。
第七方面，提供了一种计算机程序产品，该计算机程序代码或指令在计算机上执行时，使得计算机执行上述第一方面的方法设计中任意一种可能的实现方式中的方法。
附图说明
图1是本申请实施例提供的一种HEMT器件的制备系统100。
图2是本申请实施例提供的一种制备半导体器件的方法流程图。
图3是本申请实施例提供的一种制备半导体器件的方法示意图。
图4是本申请实施例提供的离子注入过程中离子入射深度与离子浓度的关系示意图。
图5是本申请实施例提供的一种制备半导体器件的装置500的示意性框图。
图6是本申请实施例提供的一种计算机可读存储介质600的示意性框图。
具体实施方式
为了便于理解本申请实施例，首先对本申请实施例涉及的相关概念进行简要介绍：
(1)HEMT器件：
是一种半导体本体，是通过使用二维电子气(two-dimensional electron gas，2DEG)，由不同带隙的两种材料之间的结点构成。包括：等效硅基HEMT、氮化镓(GaN)基HEMT等，其中，与等效硅基解决方案相比，氮化镓基HEMT的开关更快、热导率更高和导通电阻更低，因此，在电路中通常采用氮化镓晶体管和集成电路以提高效率、缩小尺寸并降低各种电源转换系统的成本。
(2)氮化镓
是一种非常坚硬且在机械方面非常稳定的宽带隙半导体材料。由于具有更高的击穿强度、更快的开关，更高的热导率和更低的导通电阻，氮化镓基功率器件明显比硅基器件更优越。GaN晶体可以在各种衬底上生长，包括蓝宝石、碳化硅(SiC)和硅(Si)。并且，通过在GaN晶体的顶部生长氮化铝镓(AlGaN)薄层并在界面施加应力，能够产生2DEG。而2DEG在电场作用下，能够高效地传导电子。可见，2DEG具有高导电性，部分原因是由于电子被困在界面处的非常细小的区域，从而能够将电子的迁移率从未施加应力前的约1000cm2/V·s，增加到2DEG区域中的1500至2000cm2/V·s。由此可见，氮化镓基HEMT器件具有的高电子迁移率，可实现更高的击穿强度、更快的开关、更高的导热率和更低的导通电阻。
(3)欧姆接触
半导体与金属接触时，多会形成势垒层，但当半导体掺杂浓度很高时，电子可借隧道效应穿过势垒，从而形成低阻值的欧姆接触。欧姆接触对半导体本体非常重要，形成良好的欧姆接触有利于电流的输入和输出，对不同半导体材料常选择不同配方的合金作欧姆接触材料。
(4)离子注入
离子注入是在高真空的复杂系统中，产生电离杂质并形成高能量的离子束，入射到一块固体材料中的过程。该过程中，离子受到固体材料的抵抗而逐渐减速，最终停留在固体材料中。相较于扩散工艺，离子注入的能够更准确地控制杂质掺杂，并且可重复性强，并且可以在较低的工艺温度中进行。但是，由于高能的离子由于与固体材料中的电子和原子核的碰撞而失去能量，最后停在晶格内的某一深度，不可避免地造成了半导体晶格断裂或损伤。所以，后续需要通过退火的方法，以去除这些损伤并且激活离子。
(5)离子激活
由于离子注入造成了半导体晶格断裂或损伤，使电子迁移率和寿命等半导体参数都受到了影响，而且大部分的离子在被注入时并不位于目标位置。因此，为了激活被注入的离子并恢复电子迁移率与其他材料参数，可以在适当的时间与温度下将半导体进行退火操作。
(6)金属沉积
是指简单金属离子或络离子通过电化学方法在固体(导体或半导体)表面上还原为金属原子附着于电极表面，从而获得一金属层的过程。
(7)退火
退火的方式除了可以应用于上述离子激活的操作，还可以应用于对上述沉积的金属层进行退火的操作，使该金属层转化为合金层，并且在该合金层与半导体之间的接触面形成欧姆接触。
下面将结合附图，对本申请实施例中的技术方案进行描述。
图1示出了本申请实施例提供的一种HEMT器件的制备系统100。
在一些可能的实施例中，该制备系统100包括：光刻机、离子注入机、清洗设备、薄膜沉积设备、 刻蚀机、退火设备以及控制设备。
其中，光刻机用于在半导体本体的外延层表面涂覆光刻胶，如图1所示，半导体本体包括外延层和衬底，外延层包括：盖帽层、势垒层、插入层、沟道层、缓冲层，而外延层最上层可以是的上述盖帽层。
其中，衬底可以包括Si、C、Al、O，例如：可以是硅(Si)和碳化硅(SiC)，还可以是蓝宝石(Al2O3)等其他适合GaN晶体生产的物质构成的衬底。
盖帽层包括Ga和N，示例地，可以是GaN。
势垒层包括Al、N，进一步地还包括Ga或In，示例地，可以是氮化铝镓(AlGaN)或者氮化铝铟(InAlN)。
沟道层包括Ga和N，示例地，可以是一种GaN channel。
插入层包括Al、N，示例地，可以是氮化铝(AlN)。应理解，插入层很薄，例如2～3nm，在半导体器件制备的过程中是非常重要的一层物质，因为上述势垒层和GaN channel的表面都非常粗糙，如果将上述势垒层与上述GaN channel直接接触，会大幅降低沟道的导通率，进一步降低了电子迁移率，而插入层则可以将上述势垒层与上述GaN channel之间的粗糙界面填补光滑，从而提升了使在沟道导通时的电子迁移率。
缓冲层主要用于将上述GaN channel中的GaN与衬底之间的化学键进行粘合，从而解决衬底上生长GaN时晶格失配、异质扩散和极性问题，保障GaN能够正常生长。
此外，上述光刻机还用于在上述盖帽层进行曝光操作以及显影操作，在上述外延层上光刻出源极(source)和漏极(drain)的图案，即SD图案。
在一些可能的实施例中，上述涂覆光刻胶的工作可以通过其他专用设备完成或者人工完成，本申请实施例对此不作限定。
离子注入机用于对上述SD图案的区域进行离子注入操作，使离子注入到上述外延层中。
在一些可能的实施例中，通过设置离子注入机的第一注入参数，能够预测出离子注入的目标层，例如势垒层，或者插入层，或者沟道层。还能够预测出离子注入后，注入离子的峰值浓度位于外延层中的哪一层。其中，第一注入参数包括预设的第一浓度、预设的第一注入电流和预设的第一注入能量。
清洗设备主要有两方面的应用，一方面用于将上述涂覆在外延层表面的光刻胶清理干净；另一方面用于后续剥离沉积在半导体本体表面的SD图案区域之外的金属。在一些可能的实施例中，上述清洗设备的两个功能可以分别部署于两个相互独立的设备当中，本申请实施例对此不作限定。
薄膜沉积设备主要有两方面的应用，一方面用于在上述盖帽层表面沉积一层介质层；另一方面用于在上述器件表面沉积一层金属层。在一些可能的实施例中，上述薄膜沉积设备的两个功能可以分别部署于两个相互独立的设备当中，本申请实施例对此不作限定。
刻蚀机用于刻蚀上述盖帽层表面形成的介质层，以及将上述SD图案区域进行刻蚀，刻蚀至上述势垒层中，或者插入层中，或者沟道层中。
退火设备用于对上述器件进行退火操作，将注入到外延层的离子激活，同时修复离子注入造成的晶格损伤。此外，将上述器件表面保留的沉积的金属层进行退火，将金属层转化为合金层，以形成欧姆接触。
控制设备用于向上述设备发送指示信息，控制上述设备进行相应操。在一些可能的实施例中，控制设备可以根据采取的制备工艺的不同，实时调整上述设备进行相应操作的顺序以及具体方法，从而向上述设备发送相应的指示信息。控制设备包括处理器、存储器、通信接口、发送器和接收器。
在一些可能的实施例中，上述计算设备可以是一种服务器，该服务器可以是本地服务器，也可以是云端服务器，本申请实施例对此不作限定。
在一些可能的实施例中，上述处理器可以是中央处理器(central processing unit，CPU)用于生成控制策略，从而控制上述设备完成一系列操作。
在一些可能的实施例中，上述可以是易失性存储器(random access memory，RAM)或非易失性存储器(non-volatile memory，NVM)等，可以用于存储处理器在计算过程所需的数据。
在一些可能的实施例中，通信接口用于与上述设备进行通信，发送指示信息或者接收上述设备的反馈信息。此外，通信接口还可以其他设备进行通信，例如，与显示器、键盘等用户设备。
图2示出了本申请实施例提供的一种制备半导体器件的方法流程图。对应地，图3示出了本申请实施例提供的一种制备半导体器件的方法示意图，展示了图2中每一个步骤操作后，半导体本体所呈现的状态。
S210：确定半导体本体的盖帽层上的离子注入区域。
基于上述本申请实施例的说明可知，盖帽层是半导体本体的外延层中的最上层，外延层还包括势垒层、插入层和沟道层。
在一些可能的实施例中，上述离子注入区域是离子注入机注入离子的入口位置，而上述半导体本体此前已被按照第一注入参数完成离子注入和离子激活的相应操作，其中，第一注入参数包括：预设的第一浓度、预设的第一注入电流和预设的第一注入能量。由此可知，在上述S210之前，还需要进行如下操作：
如图3中的(a)所示，在盖帽层350上涂覆一层第一光刻胶30，基于第一光刻板35对盖帽层350进行光刻操作。其中，340表示势垒层，330表示插入层，320表示沟道层，310表示缓冲层，10表示衬底。
应理解，上述第一光刻板35包括指定的SD图案。因此，在进行光刻操作之前，根据制备的半导体器件本身的尺寸以及需要制备的SD图案类型确定所要选用的第一光刻板35和光刻机的光刻参数。然后进行光刻操作，在光刻的过程中会去除SD图案区域的光刻胶30，最终在盖帽层350上能够形成上述指定的SD图案20。而在SD图案20区域之外，还保留着部分第一光刻胶30。
一个实施例中，上述光刻操作包括曝光操作、显影操作。
如图3中的(b)所示，在完成上述光刻操作后，基于当前的半导体本体，对上述SD图案区域进行离子注入。
由于非SD图案区域的部分已经由第一光刻胶所涂覆，所以盖帽层表面露出的区域均为SD图案区域，因此，离子注入机仅需要地将离子注入到上述SD图案区域中即可。
在一些可能的实施例中，可以通过上述离子注入操作形成盖帽层350的GaN的N型掺杂，基于此，注入离子的种类包括但不限于硅(Si)、锗(Ge)、碳(C)等能够实现GaN的N型掺杂的离子，本申请对此不做限定。进一步地，离子注入的第一浓度范围区间可以是[1018,1022]cm-3。
在一些可能的实施例中，在离子通过SD图案区域入射到外延层时，离子与外延层内部的材料进行碰撞，消耗离子在注入时所被赋予的能量，当能量消耗殆尽时，离子停止运动，停留在外延层的某一层的具体位置。
基于上述技术方案，在半导体器件制备过程中，向半导体本体注入离子，改变半导体本体外延层内的离子浓度，使外延层各个层的原生材料性能发生改变，有助于形成接触电阻较低的欧姆接触。
如图3中的(c)所示，在完成上述离子注入后，将上述SD图案区域之外的第一光刻胶30去除，完整露出盖帽层350的上表面。
在一些可能的实施例中，可以通过有机清洗剂去除上述第一光刻胶，该有机清洗剂可以是由丙酮、异丙醇、无水乙醇等有机物基于一定配比混合制成的。
如图3中的(d)所示，在完成上述离子注入后，在上述盖帽层350上沉积第一介质层360。
在一些可能的实施例中，可以通过原子层沉积(atomic layer deposition，ALD)、等离子体增强原子层沉积(plasma enhanced atomic layer deposition，PEALD)、低压化学气相沉积(low pressure chemical vapor deposition，LPCVD)、等离子体增强化学气相沉积(plasma enhanced chemical vapor deposition，PECVD)、溅射沉积等方法在盖帽层350上沉积厚度10～200nm的二氧化硅或氮化硅薄膜，本申请实施例对具体采用的第一介质层沉积方法、形成的第一介质层材质构成以及第一介质层具体的厚度不作限定。
如图3中的(e)所示，在形成上述第一介质层360之后，激活上述注入到外延层中的离子。在一些可能的实施例中，可以通过快速热处理(rapid thermal processing，RTP)退火炉进行退火或者激光退火等方法激活注入的离子。本申请对具体退火的方式不作限定。
基于上述技术方案，在激活注入的离子同时，还修复了由于离子注入造成的外延层晶格损伤。
应理解，上述沉积的第一介质层360主要用于在离子激活的过程中保护上述半导体本体，例如，在通过RTP退火的方法进行离子激活时，由于退火的过程中，半导体本体的直接受热面为上述第一介 质层360，所以不会对外延层直接进行加热。
基于上述技术方案，能够有效防止外延层被高温损伤。
如图3中的(f)所示，在完成上述离子激活操作后，去除上述第一介质层360，完整露出盖帽层350的上表面。
在一些可能的实施例中，可以通过干法刻蚀，去除上述外延层上的介质层，例如，可以通过高级氧化物蚀刻机(advanced oxide etcher，AOE)进行干法刻蚀操作，以完成上述去除第一介质层360的操作。当然，还可以通过湿法刻蚀操作，完成上述去除第一介质层360的操作。还可以通过干法刻蚀和湿法刻蚀相结合的方法完成上述去除第一介质层360的操作。本申请实施例对此不作限定。
通过上述本申请实施例的说明可知，上述离子注入和离子激活的相关工艺流程，是先对SD图案区域进行离子注入，再在上述盖帽层350表面沉积第一介质层360，然后再进行后续的离子激活以及去除第一介质层360的相应操作。
此外，如图3中的(g)所示，对于上述离子注入和离子激活的相关工艺流程还可以是先在上述盖帽层350表面沉积第一介质层360。
如图3中的(h)所示，在第一介质层360表面涂覆一层第一光刻胶30，基于第一光刻板35对第一介质层360进行光刻操作，从而在第一介质层上形成SD图案。
如图3中的(i)所示，对第一介质层60上的SD图案区域进行离子注入。
如图3中的(j)所示，去除第一光刻胶，并激活离子。
如图3中的(k)所示，去除第一介质层360，完整露出盖帽层350的上表面。
经过上述离子注入和离子激活的相关工艺流程后，对于S210中提出的确定半导体本体的盖帽层上的离子注入区域，可以通过如下方法确定。
在一些可能的实施例中，如图3中的(l)所示，由于上述对半导体本体进行光刻操作时，使用的是第一光刻板35对半导体本体进行光刻，为了确定半导体本体的盖帽层上的离子注入区域，可以在半导体本体的盖帽层上涂覆第二光刻胶31，基于上述第一光刻板35对盖帽层350进行第二次光刻操作，从而使盖帽层350上再次形成了上述SD图案。
在一些可能的实施例中，两次基于第一光刻板35对半导体本体进行光刻的过程中，需要对准光刻SD图案的位置，使两次光刻的SD图案的位置是一致的，即两次光刻的SD图案区域应该是重合的。
基于上述技术方案，通过复用第一光刻板35，保障了后续刻蚀过程中能够基于离子注入区域进行刻蚀，保障后续刻蚀暴露的第一接触面能够处于峰值浓度附近，即2DEG附近，以降低欧姆接触的接触势垒，从而降低欧姆接触的接触电阻。是实现单次离子注入的重要步骤。
基于上述技术方案可知，第二次在盖帽层350光刻出的SD图案区域，就是上述离子注入区域。
S220：根据上述第一注入参数，确定上述外延层中上述离子的峰值浓度区域位置。
在一些可能的实施例中，在进行离子注入前，会对离子注入过程进行仿真实验，调节第一注入参数中包括的具体参数值，确定并记录各个参数在不同数值下对应的外延层中离子的峰值浓度区域位置。当后续实际半导体制造过程中，确定第一注入参数的值，进而能够根据第一注入参数确定外延层中离子的峰值浓度区域位置。
在一些可能的实施例中，上述第一注入参数包括预设的第一浓度、预设的第一注入电流和预设的第一注入能量，其中第一浓度还可以通过第一注入剂量或者第一注入离子面密度来代替。其中，注入电流影响着单位时间内注入离子的数量，进而影响指定剂量离子的注入时间，而注入时间越长，制造半导体的成本就越高，所以注入电流不易过小。但是也不易过大，注入电流过大会对半导体器件造成较大的晶格损伤。
此外，第一注入参数还包括第一注入角度和第一温度等，其中第一注入角度为与垂直方向上的夹角。但是在仿真实验中，通常不对这两种参数进行调节。当确定上述具体参数后，即可确定上述外延层中离子的峰值浓度区域位置。
示例地，第一注入能量为30keV，第一注入剂量为e15个/cm2，第一注入电流为70μA，第一注入角度为7°，第一注入温度为25℃。确定外延层中离子的峰值浓度区域位置在距离盖帽层350的上表面40nm附近；
第一注入能量为50keV，第一注入剂量为e15个/cm2，第一注入电流为100μA，第一注入角度为7°， 第一注入温度为25℃。确定外延层中离子的峰值浓度区域位置在距盖帽层的上表面250nm附近。
经过多次上述实验，即可通过在离子注入前，预设相应的第一注入参数，从而能够预测出注入到半导体本体的离子的峰值浓度区域位置。
图4示出了本申请实施例提供的离子注入过程中离子入射深度与离子浓度的关系示意图。
其中，二维坐标系的纵坐标为离子入射深度，横坐标为该深度下离子的第二浓度。可见，离子的第二浓度与离子入射深度整体上呈现为一种高斯分布，因此，在离子入射的区域内存在一个对应于峰值浓度的位置，该位置则聚集着2DEG，若在此形成欧姆接触，则有利于降低接触势垒，进而减小接触电阻。可见，欧姆接触的接触面所在位置的离子浓度越大，其形成的接触电阻就越小。
如图4所示，离子的峰值浓度位于沟道层320中，所以如果将欧姆接触的接触表面设置在该处，则此处的接触电阻最小。鉴于此，在进行后续步骤之前，需要确定各层中离子的第二浓度。
在一些可能的实施例中，在上述进行离子注入之前，需要为离子注入机设置离子第一注入参数，包括预设的第一浓度、预设的第一注入电流和预设的第一注入能量等。可以基于离子第一注入参数，预测注入的离子在各层中具体位置对应的离子的第二浓度，进一步地，通过比较具体位置对应的离子的第二浓度与离子注入的第一浓度能够确定峰值浓度对应的具体位置。或者，直接对半导体本体各层中具体位置进行物质采样，通过采样的样本检测其对应采样位置的离子浓度。
基于上述技术方案，使后续经过刻蚀操作暴露的第一接触面处于2DEG附近，从而使在第一接触面形成的欧姆接触的接触势垒很低，进而降低半导体器件欧姆接触的接触电阻。
S230：根据上述离子的峰值浓度区域位置，确定第一深度。
在一些可能的实施例中，在上述外延层中离子的峰值浓度区域中确定第一横截面，该第一横截面与所述外延层平行；
在获得上述第一横截面之后，能够确定该第一横截面与上述盖帽层350之间的垂直距离为上述第一深度。
S240：根据上述第一深度，以上述离子注入区域为起始区域，刻蚀上述外延层并暴露第一接触面。
在一些可能的实施例中，如图3的(m)所示，可以通过干法刻蚀，对从离子注入区域开始，对上述外延层进行刻蚀，例如，可以通过高级氧化物蚀刻机(advanced oxide etcher，AOE)进行干法刻蚀操作，以完成上述刻蚀操作；也可以通过电感耦合等离子体(inductively coupled plasma，ICP)刻蚀机进行干法刻蚀操作；当然，还可以通过湿法刻蚀操作，完成上述刻蚀操作；还可以通过干法刻蚀和湿法刻蚀相结合的方法完成上述刻蚀操作，本申请实施例对此不作限定。最终将外延层刻蚀至上述过程中确定的沟道层320中，而此时沟道层320在刻蚀区域中暴露的上表面就是上述第一接触面。
应理解，由于第一接触面在外延层内的位置，正处于上述注入离子的峰值浓度附近，所以，第一接触面则处于2DEG附近。若在此处形成半导体器件的欧姆接触，可以有效降低接触势垒，以减小接触电阻。
在一些可能的实施例中，上述第一接触面通常位于上述势垒层340与沟道层320的异质结界面的±10nm处。所以，在设备条件有限的前提下，可以无需确定外延层中注入离子的峰值浓度位置，通过推算势垒层340与沟道层320的异质结界面的位置，将外延层刻蚀至势垒层340与沟道层320的异质结界面的±10nm处，此时暴露的第一接触面通常也在2DEG附近。
在上述第一接触面暴露之后，需要在第一接触面形成欧姆接触，进入到S250。
S250：在上述第一接触面上沉积金属层。
在一些可能的实施例中，如图3的(n)所示，可以使用电子束蒸发或溅射沉积等方法在外延层当前状态的上表面沉积金属层40，其中金属层由四层金属结构构成，示例地，Ti/Al/X/Au，其中X可以是任意一种金属，示例地，X可以是Ti等。
应理解，上述金属层40首先需要在外延层当前状态的上表面进行沉积，即在外延层的非刻蚀区域，对应于第二光刻胶30的上表面，以及外延层的刻蚀区域，对应于沟道层320暴露的第一接触面。但是，在非刻蚀区域表面沉积的金属层40对于半导体器件制备是没有用处的，所以可以将非刻蚀区域表面沉积的金属层40去除。
在一些可能的实施例中，如图3的(o)所示，由于沉积在非刻蚀区域的金属层40位于第二光刻胶30的上表面，所以，可以通过上述有机溶剂，将第二光刻胶30上面沉积的金属40层剥离。示例地， 可以丙酮超声清洗后，通过N-甲基吡咯烷酮(N-methylpyrrolidone，NMP)溶液水域加热，即可剥离非刻蚀区域的金属层40。若在沉积金属层40之前，已经去除了盖帽层350上端的第二光刻胶30，即外延层的刻蚀区域对应于盖帽层350的上表面，此时则可以使用刻蚀的方法，将非刻蚀区域的金属层40去除。
S260：通过退火的方法，将上述金属层转化为合金层，并在上述第一接触面形成欧姆接触。
在一些可能的实施例中，可以通过RTP快速退火炉或激光退火进行金属退火，如图3的(p)所示，将上述金属层40转化为合金层50，以实现在上述第一接触面形成欧姆接触。
基于上述技术方案，由于第一接触面在外延层内的位置，正处于上述注入离子的峰值浓度附近，所以，第一接触面则处于2DEG附近。若在此处形成半导体器件的欧姆接触，可以有效降低接触势垒，以减小接触电阻。进一步地，由于半导体本体经过退火后，其外延层内注入离子的浓度分布曲线趋于平缓，所以使离子浓度对离子所处深度的敏感度降低，例如，峰值浓度位置±3nm范围内浓度变化极小，使形成欧姆接触的第一接触面的离子能够维持较高浓度，从而进一步降低半导体器件欧姆接触的接触电阻。并且单次离子注入即可达到上述效果，不仅节省时间，还避免多次离子注入对晶格造成较大的损伤。
基于本申请实施例提出的上述半导体器件制备方法，本申请实施例提出了一种半导体器件，该半导体器件可以如图1中所示的最终制成的半导体器件，也可以如图3中的(p)所示的半导体器件，该半导体器件包括：
半导体本体，该半导体本体注入有离子，该离子是按照第一注入参数注入的，该第一注入参数包括：预设的第一浓度、预设的第一注入电流和预设的第一注入能量，该半导体本体包括外延层和衬底，其中，外延层在衬底之上，外延层包括盖帽层、势垒层、插入层和沟道层，盖帽层为外延层的最上层，势垒层在盖帽层之下，插入层在势垒层之下，沟道层在插入层之下且在衬底之上，盖帽层的上表面包括离子注入区域，离子注入区域用于向半导体本体注入离子，外延层中包括峰值浓度区域，该峰值浓度区域是外延层中离子浓度最大的区域，外延层具有深度为第一深度的刻蚀区域，刻蚀区域包括第一接触面，该第一接触面为刻蚀区域的下表面，位于离子注入区域的下方，上述第一深度是根据峰值浓度区域位置确定的，该峰值浓度区域位置是根据第一注入参数确定的；
合金层，该合金层与第一接触面接触，该合金层与第一接触面之间形成有欧姆接触，该合金层是在第一接触面上沉积的金属层通过退火的方法转化的。
基于上述技术方案，该半导体本体的第一接触面在外延层内的位置，正处于上述注入离子的峰值浓度区域位置附近，即第一接触面处于2DEG附近。因此制成后的半导体器件的欧姆接触接触势垒很小，进而接触电阻也很小，半导体器件的性能也很好。
在一些可能实现的实施例中，上述第一深度为第一横截面与盖帽层上表面之间的垂直距离，该第一横截面与外延层平行，该第一横截面是根据离子的峰值浓度区域确定的。
基于上述技术方案，半导体本体经过刻蚀操作暴露的第一接触面处于2DEG附近，从而使在第一接触面形成的欧姆接触的接触势垒很低，进而使制成的半导体器件欧姆接触的接触电阻很低，半导体器件的性能也很好。
在一些可能的实施例中，上述注入半导体本体的离子包括以下任一种元素：硅元素Si、锗元素Ge、碳元素C。
在一些可能的实施例中，第一浓度的区间范围是[1018,1022]cm-3。
基于上述技术方案，将第一浓度控制在上述合适的范围内，避免离子浓度过低，造成制成的半导体器件的欧姆接触的接触电阻较高的问题，也避免离子浓度过高，造成制成的半导体器件晶格损伤过大致使功能失效的问题。
在一些可能的实施例中，第一接触面位于势垒层与沟道层之间的异质结界面±10nm范围内。
在一些可能的实施例中，上述金属层为四层金属，包括钛Ti层、铝Al层、X层、金Au层，其中X为任一种金属元素。
此外，本申请实施例还提供用于实现以上任一种方法的装置，例如，提供一种制备半导体器件的装置，该装置包括用以实现以上任一种制备半导体器件的方法的单元(或手段)。
图5示出了本申请实施例提供的一种制备半导体器件的装置500的示意性框图。如图5所示，该 装置500包括：
确定单元510，用于确定半导体本体的盖帽层上的离子注入区域，盖帽层是半导体本体的外延层中的最上层，外延层还包括势垒层、插入层和沟道层，该离子注入区域是离子注入的入口，该半导体本体已被按照第一注入参数完成离子注入和离子激活，第一注入参数包括：预设的第一浓度、预设的第一注入电流和预设的第一注入能量；根据第一注入参数，确定外延层中离子的峰值浓度区域位置；根据离子的峰值浓度区域位置，确定第一深度。
操作单元520，用于根据第一深度，以离子注入区域为起始区域，刻蚀外延层并暴露第一接触面；在第一接触面上沉积金属层；通过退火的方法，将金属层转化为合金层，并在第一接触面形成欧姆接触。
在一些可能的实施例中，上述确定单元510具体用于，在离子的峰值浓度区域中确定第一横截面，该第一横截面与外延层平行；确定第一横截面与盖帽层上表面之间的垂直距离为第一深度。
在一些可能的实施例中，上述操作单元520在确定半导体本体的盖帽层上的离子注入区域之前，还用于在盖帽层上涂覆第一光刻胶，基于第一光刻板对盖帽层进行光刻操作，在盖帽层上形成源极和漏极图案；对源极和漏极图案的区域进行离子注入；去除第一光刻胶；在盖帽层上沉积第一介质层，并激活离子；去除第一介质层。
在一些可能的实施例中，上述操作单元520在确定半导体本体的盖帽层上的离子注入区域之前，还用于在盖帽层上沉积第一介质层；在第一介质层上涂覆第一光刻胶，基于第一光刻板对第一介质层进行光刻操作，在第一介质层上形成源极和漏极图案；对源极和漏极图案的区域进行离子注入；去除第一光刻胶，并激活离子；去除第一介质层。
在一些可能的实施例中，上述操作单元520具体用于通过RTP退火的方法或者激光退火的方法，激活离子。
在一些可能的实施例中，上述操作单元520具体用于在半导体本体的盖帽层上涂覆第二光刻胶，基于第一光刻板对盖帽层进行光刻操作，在盖帽层上形成源极和漏极图案，源极和漏极图案的区域为离子注入区域。
在一些可能的实施例中，上述操作单元520具体用于在半导体本体的上表面沉积金属层；去除离子注入区域之外的金属层和第二光刻胶。
图6为本申请实施例提供的一种计算机可读存储介质600的示意性框图。图6所示的计算机可读存储介质600，该计算机可读存储介质600存储有计算机指令610。该计算机指令610被处理器执行时可实现上述图2所示的方法。
在一些可能的实施例中，计算机可读存储介质600可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集合的服务器、数据中心等数据存储设备。可用介质可以是磁性介质(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质。半导体介质可以是固态硬盘。
在本申请实施例中，上述实施例可以全部或部分地通过软件、硬件、固件或其他任意组合来实现。当使用软件实现时，上述实施例可以全部或部分地以计算机程序产品的形式实现。计算机程序产品包括一个或多个计算机指令或计算机程序。在计算机上加载或执行计算机指令或计算机程序时，全部或部分地产生按照本申请实施例的流程或功能。计算机可以为通用计算机、专用计算机、计算机网络、或者其他可编程装置。计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方 式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (21)

  1. 一种制备半导体器件的方法，其特征在于，包括：
    确定半导体本体的盖帽层上的离子注入区域，所述盖帽层是所述半导体本体的外延层中的最上层，所述外延层还包括势垒层、插入层和沟道层，所述离子注入区域是离子注入的入口，所述半导体本体已被按照第一注入参数完成所述离子注入和离子激活，所述第一注入参数包括：预设的第一浓度、预设的第一注入电流和预设的第一注入能量；
    根据所述第一注入参数，确定所述外延层中所述离子的峰值浓度区域位置；
    根据所述离子的峰值浓度区域位置，确定第一深度；
    根据所述第一深度，以所述离子注入区域为起始区域，刻蚀所述外延层并暴露第一接触面；
    在所述第一接触面上沉积金属层；
    通过退火的方法，将所述金属层转化为合金层，并在所述第一接触面形成欧姆接触。
  2. 根据权利要求1所述的方法，其特征在于，所述根据所述离子的峰值浓度区域位置，确定第一深度包括：
    在所述离子的峰值浓度区域中确定第一横截面，所述第一横截面与所述外延层平行；
    确定所述第一横截面与所述盖帽层上表面之间的垂直距离为所述第一深度。
  3. 根据权利要求1或2所述的方法，其特征在于，所述离子包括以下任一种元素：硅元素Si、锗元素Ge、碳元素C。
  4. 根据权利要求1至3中任一项所述的方法，其特征在于，所述第一浓度的区间范围是[1018,1022]cm-3。
  5. 根据权利要求1至4中任一项所述的方法，其特征在于，在所述确定半导体本体的盖帽层上的离子注入区域之前，所述方法还包括：
    在所述盖帽层上涂覆第一光刻胶，基于第一光刻板对所述盖帽层进行光刻操作，在所述盖帽层上形成源极和漏极图案；
    对所述源极和漏极图案的区域进行离子注入；
    去除所述第一光刻胶；
    在所述盖帽层上沉积第一介质层，并激活所述离子；
    去除所述第一介质层。
  6. 根据权利要求1至4中任一项所述的方法，其特征在于，在所述确定半导体本体的盖帽层上的离子注入区域之前，所述方法还包括：
    在所述盖帽层上沉积第一介质层；
    在所述第一介质层上涂覆第一光刻胶，基于第一光刻板对所述第一介质层进行光刻操作，在所述第一介质层上形成源极和漏极图案；
    对所述源极和漏极图案的区域进行离子注入；
    去除所述第一光刻胶，并激活所述离子；
    去除所述第一介质层。
  7. 根据权利要求5或6所述的方法，其特征在于，所述激活所述离子包括：
    通过快速热处理RTP退火的方法或者激光退火的方法，激活所述离子。
  8. 根据权利要求5至7中任一项所述的方法，其特征在于，所述确定半导体本体的盖帽层上的离子注入区域包括：
    在所述半导体本体的所述盖帽层上涂覆第二光刻胶，基于所述第一光刻板对所述盖帽层进行光刻操作，在所述盖帽层上形成源极和漏极图案，所述源极和漏极图案的区域为所述离子注入区域。
  9. 根据权利要求8所述的方法，其特征在于，所述在所述第一接触面上沉积金属层包括：
    在所述半导体本体的上表面沉积所述金属层；
    去除所述离子注入区域之外的所述金属层和所述第二光刻胶。
  10. 根据权利要求1至9中任一项所述的方法，其特征在于，所述第一接触面位于所述势垒层与 所述沟道层之间的异质结界面±10nm范围内。
  11. 根据权利要求1至10中任一项所述的方法，其特征在于，所述金属层为四层金属，包括钛Ti层、铝Al层、X层、金Au层，其中X为任一种金属元素。
  12. 一种半导体器件，其特征在于，包括：
    半导体本体，所述半导体本体注入有离子，所述离子是按照第一注入参数注入的，所述第一注入参数包括：预设的第一浓度、预设的第一注入电流和预设的第一注入能量，所述半导体本体包括外延层和衬底，所述外延层在所述衬底之上，所述外延层包括盖帽层、势垒层、插入层和沟道层，所述盖帽层为所述外延层的最上层，所述势垒层在所述盖帽层之下，所述插入层在所述势垒层之下，所述沟道层在所述插入层之下且在所述衬底之上，所述盖帽层的上表面包括离子注入区域，所述离子注入区域用于向所述半导体本体注入所述离子，所述外延层中包括峰值浓度区域，所述峰值浓度区域是所述外延层中离子浓度最大的区域，所述外延层具有深度为第一深度的刻蚀区域，所述刻蚀区域包括第一接触面，所述第一接触面为所述刻蚀区域的下表面，位于所述离子注入区域的下方，所述第一深度是根据所述峰值浓度区域位置确定的，所述峰值浓度区域位置是根据所述第一注入参数确定的；
    合金层，所述合金层与所述第一接触面接触，所述合金层与所述第一接触面之间形成有欧姆接触，所述合金层是在所述第一接触面上沉积的金属层通过退火的方法转化的。
  13. 根据权利要求12所述的半导体器件，其特征在于，注入所述半导体本体的所述离子包括以下任一种元素：硅元素Si、锗元素Ge、碳元素C。
  14. 根据权利要求12或13所述的半导体器件，其特征在于，所述第一浓度的区间范围是[1018,1022]cm-3。
  15. 根据权利要求12至14中任一项所述的半导体器件，其特征在于，所述第一接触面位于所述势垒层与所述沟道层之间的异质结界面±10nm范围内。
  16. 根据权利要求12至15中任一项所述的半导体器件，其特征在于，所述金属层为四层金属，包括钛Ti层、铝Al层、X层、金Au层，其中X为任一种金属元素。
  17. 一种制备半导体器件的装置，其特征在于，所述装置用于执行如权利要求1至11中任一项所述的方法。
  18. 一种制备半导体器件的装置，其特征在于，包括：
    存储器，用于存储计算机指令；
    处理器，用于执行所述存储器中存储的计算机指令，以使得所述装置执行如权利要求1至11中任一项所述的方法。
  19. 一种计算机存储介质，其特征在于，所述计算机存储介质中存储有计算机指令，所述指令在计算机上执行时，使得所述计算机执行如权利要求1至11中任一项所述的方法。
  20. 一种芯片，其特征在于，包括处理器，所述处理器用于执行如权利要求1至11中任一项所述的方法。
  21. 一种计算机程序产品，其特征在于，所述计算机程序代码或指令在计算机上执行时，使得所述计算机执行如权利要求1至11中任意一项所述的方法。
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