WO2024045977A1 - 印刷电路板、电子设备及印刷电路板制备方法 - Google Patents

印刷电路板、电子设备及印刷电路板制备方法 Download PDF

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Publication number
WO2024045977A1
WO2024045977A1 PCT/CN2023/110102 CN2023110102W WO2024045977A1 WO 2024045977 A1 WO2024045977 A1 WO 2024045977A1 CN 2023110102 W CN2023110102 W CN 2023110102W WO 2024045977 A1 WO2024045977 A1 WO 2024045977A1
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WIPO (PCT)
Prior art keywords
thickness
transmission line
layer structure
region
structure body
Prior art date
Application number
PCT/CN2023/110102
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English (en)
French (fr)
Inventor
谢剑
魏仲民
尹昌刚
Original Assignee
中兴通讯股份有限公司
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Publication of WO2024045977A1 publication Critical patent/WO2024045977A1/zh

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting

Definitions

  • the present disclosure relates to the technical field of printed circuits, and specifically to printed circuit boards, electronic equipment and printed circuit board preparation methods.
  • PCB Print Circuit Board, printed circuit board 112Gbps rate products have begun to be commercialized, and 224Gbps rate products are under research.
  • SI Signal Integrity, signal integrity
  • Bandwidth printed circuit board
  • the pin pitch of the 224Gbps chip is smaller, and the pitch of the corresponding BGA (Ball Grid Array, ball pin grid array) area is also smaller.
  • the pitch of the BGA area of the 112Gbps chip is 1.0 millimeters (mm), with 3.5/3.5 mil (mil) double lines, while the pitch of the BGA area of the 224Gbps chip is reduced to 0.6mm for double lines.
  • a printed circuit board including a layer structure body and a transmission line for transmitting signals, the transmission line is located in the layer structure body, and the The layer structure body includes a first region and a second region, the first region is a region for inter-layer signal transmission within the layer structure body, and the second region is a region other than the first region; The first thickness of the transmission line in the first region is less than the second thickness of the transmission line in the second region, and the first thickness is less than or equal to a preset first threshold.
  • an embodiment of the present disclosure also provides an electronic device, including the printed circuit board as mentioned above.
  • an embodiment of the present disclosure also provides a printed circuit board preparation method for preparing the printed circuit board as mentioned above, including: in the process of forming the layer structure body, in the first step of the layer structure body A first transmission line pattern with a first thickness is formed in a region, and a second transmission line pattern with a second thickness is formed in a second region of the layer structure body, thereby obtaining a transmission line pattern including the first transmission line pattern and the second transmission line pattern. ;
  • the first area is an area for inter-layer signal transmission within the layer structure body, and the second area is an area other than the first area; the first thickness is smaller than the second thickness , and the first thickness is less than or equal to the preset first threshold.
  • Figure 1 is a schematic cross-sectional structural diagram of a printed circuit board provided by an embodiment of the present disclosure
  • Figure 2 is a top view of a first area of a printed circuit board provided by an embodiment of the present disclosure
  • Figure 3 is a schematic flow chart of a printed circuit board preparation method provided by an embodiment of the present disclosure
  • Figure 4 is a schematic flowchart of forming a transmission line pattern provided by an embodiment of the present disclosure
  • Figure 5 is a schematic flowchart of forming a transmission line pattern provided by an embodiment of the present disclosure
  • Figure 6 is a schematic diagram comparing the insertion loss effect of a printed circuit board in the related art and a printed circuit board provided by an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram comparing the return loss effects of a printed circuit board in the related art and a printed circuit board provided by an embodiment of the present disclosure.
  • Embodiments described herein may be described with reference to plan and/or cross-sectional illustrations, with the aid of idealized schematic illustrations of the present disclosure. Accordingly, example illustrations may be modified based on manufacturing techniques and/or tolerances. Therefore, the embodiments are not limited to those shown in the drawings but include modifications of configurations formed based on the manufacturing process. Therefore, the regions illustrated in the figures are of a schematic nature, and the shapes of the regions shown in the figures are illustrative of the specific shapes of the regions of the element, but are not limiting.
  • Embodiments of the present disclosure provide a printed circuit board and a printed circuit board preparation method that locally reduce the thickness of transmission lines (dimensions along the up and down direction in Figure 1) in areas where inter-layer signal transmission is performed, thereby achieving the production of precision pins. small spacing requirements.
  • Figure 1 is a schematic cross-sectional structural view of a printed circuit board provided by an embodiment of the present disclosure.
  • Figure 2 is a top view of a printed circuit board provided by an embodiment of the present disclosure.
  • the printed circuit board provided by an embodiment of the present disclosure including a layer structure body 1 and a transmission line 2 for transmitting signals.
  • the transmission line 2 is located in the layer structure body 1.
  • the layer structure body 1 includes a first region and a second region.
  • the first region is for inter-layer processing in the layer structure body 1.
  • the area for signal transmission, the second area is an area other than the first area.
  • the first thickness d1 of the transmission line 2 in the first area is smaller than the second thickness d2 of the transmission line 2 in the second area, and the first thickness d1 Less than or equal to the preset first threshold.
  • the transmission line 2 may be made of metal copper, may be formed by etching a copper-containing core plate, or may be a copper line.
  • the printed circuit board provided by the embodiment of the present disclosure includes a layer structure body 1 and a transmission line 2 for transmitting signals.
  • the transmission line 2 is located in the layer structure body 1.
  • the layer structure body 1 includes a first area and a second area.
  • the first area is The area within the layer structure body 1 for inter-layer signal transmission
  • the second area is the area within the layer structure body 1 except the first area;
  • the first thickness d1 of the transmission line 2 in the first area is smaller than the first thickness d1 of the transmission line 2 in the second area
  • the second thickness d2, and the first thickness d1 is less than or equal to the preset first threshold;
  • the embodiment of the present disclosure forms thickness differences of the transmission line 2 in different areas, which can not only satisfy the manufacturability of small-pitch pins, but also satisfy
  • the signal integrity required by high-speed products can take into account signal integrity and the design and processability of printed circuit boards.
  • the transmission line 2 is a copper wire
  • the first threshold is 0.5 ounces of copper foil thickness (OZ). That is to say, the first thickness d1 of the transmission line 2 in the first region is ⁇ 0.5 OZ.
  • the second thickness d2 is greater than or equal to the preset second threshold.
  • the second threshold is a copper foil thickness of 1 ounce, that is, the thickness d2 of the transmission line 2 in the second area is ⁇ 1OZ.
  • the first area includes a BGA area and/or a connector area
  • a metallized hole penetrating the layer structure body is provided in the first area (not shown in FIGS. 1 and 2 ), and the metallized hole is connected to the transmission line 2
  • the transmission line 2 inside the PCB board is introduced into the outer layer of the PCB board through the metallized hole, and connected to the chip pin or connector pin, etc., to form a complete signal transmission path.
  • the layer structure body can be a single-layer structure or a multi-layer structure.
  • a single-layer structure is a single-layer PCB board, and a multi-layer structure is a multi-layer PCB board.
  • the printed circuit board is a three-layer board.
  • the layer structure body 1 includes a first layer structure 11, a second layer structure 12 and a third layer structure 13.
  • the second layer structure 12 and the third layer structure 13 are stacked.
  • Each layer structure is a copper-containing core board.
  • the two transmission lines 2 are located in the first layer structure 11 and the second layer structure 12 respectively.
  • the first layer structure 11 includes a stacked copper layer 111, a first dielectric layer 112 and a second dielectric layer 113.
  • the transmission line 2 is located in the second dielectric layer 113.
  • the second layer structure 12 has the same structure as the first layer structure 11, The difference between the third layer structure 13 and the first layer structure 11 is that there is no transmission line 2 in the second dielectric layer of the third layer structure 13 .
  • outer layer circuits 14 are also provided on the side of the first layer structure 11 away from the second layer structure 12 and on the side of the third layer structure 13 away from the second layer structure 12 .
  • the first dielectric layer 112 and the second dielectric layer 113 are usually composed of resin, glass fiber, filler and other components.
  • the disclosed embodiment achieves signal integrity and design and processability that take into account the small pitch of the pins.
  • An embodiment of the present disclosure also provides an electronic device, which includes the printed circuit board as mentioned above.
  • Embodiments of the present disclosure also provide a printed circuit board preparation method for preparing the printed circuit board as described above. As shown in FIG. 3 , the printed circuit board preparation method includes the following step S11.
  • Step S11 in the process of forming the layer structure body, form a first transmission line pattern with a first thickness in the first region of the layer structure body, and form a second transmission line pattern with a second thickness in the second region of the layer structure body, to obtain A transmission line pattern including a first transmission line pattern and a second transmission line pattern.
  • the first area is an area for inter-layer signal transmission within the layer structure body, and the second area is an area other than the first area; the first thickness is less than the second thickness, and the first thickness is less than or equal to the preset first threshold.
  • the first thickness d1 of the transmission line 2 can be smaller than the second thickness d2 in the following two ways: 1. Reduce the initial thickness of the transmission line 2 in the first region; 2. Increase the initial thickness of the transmission line 2 in the second region. The two methods will be described in detail below.
  • step S11 design PCB data is first produced.
  • the area with thin copper plating is the designated BGA area or connector area (first area), and the area with thick copper plating is other areas (second area).
  • a first transmission line pattern of a first thickness is formed in a first region of the layer structure body, and a second transmission line pattern of a second thickness is formed in a second region of the layer structure body. (i.e. step S11) includes the following steps S111 to S113.
  • Step S111 forming a first copper layer with a second thickness in the first region and the second region of the layer structure body, and forming a first transmission line pattern on the first copper layer in the first region.
  • the initial thickness of the transmission line 2 is the second thickness d2, for example, 1OZ.
  • a first copper layer is formed in the first region and the second region.
  • the thickness of the first copper layer is the second thickness d2
  • a first transmission pattern is formed on the second copper layer in the first region.
  • the thickness of the first transmission line pattern is the second thickness d2.
  • the copper-reduced film is used for exposure processing, and the copper-reduced pattern is transferred to form a first transmission line pattern with a second thickness d2.
  • Step S112 Reduce the thickness of the first transmission line pattern from the second thickness to the first thickness to obtain the first transmission line pattern with the first thickness.
  • the thickness of the first transmission line pattern is reduced from the second thickness d2 to the first thickness d1 through local copper reduction, for example, 0.5OZ.
  • the first transmission line pattern formed on the inner core board is etched to reduce the thickness of the first transmission pattern from the second thickness d2 to the first thickness d1, and a film stripping process is performed to remove excess photoresist.
  • Step S113 Form a second transmission line pattern in the second area of the layer structure body.
  • a second transmission line pattern is formed in the second area of the layer structure body, and the thickness of the second transmission pattern is the second thickness d2.
  • film processing is performed, photoresist is applied, and the inner layer is exposed using conventional methods.
  • the inner core board with copper thickness and height difference is placed in an exposure machine containing a halogen lamp for exposure to achieve pattern transfer. Etch the inner core board after the circuit exposure is completed. Due to the different thickness of the bottom copper, the etching parameters need to be adjusted appropriately to take into account both 0.5OZ and 1OZ copper etching to obtain the second transmission line pattern.
  • step S113 forming the second transmission line pattern in the second area of the layer structure body includes the following steps: forming the second transmission line pattern in the second area of the layer structure body through exposure, development, and etching. For the second transmission line pattern, the photoresist is bonded to the second area of the layer structure body by vacuum lamination before exposure.
  • a first transmission line pattern of a first thickness is formed in a first region of the layer structure body, and a second transmission line pattern of a second thickness is formed in a second region of the layer structure body.
  • step S11 includes the following steps S111' to S113'.
  • Step S111' forming a second copper layer of first thickness in the first region and the second region of the layer structure body, and forming a second transmission line pattern on the second copper layer in the second region.
  • the initial thickness of the transmission line 2 is the first thickness d1, for example, 0.5OZ.
  • a second copper layer is formed in the first region and the second region.
  • the thickness of the second copper layer is the first thickness d1
  • a second transmission layer is formed on the second copper layer in the second region. pattern, the thickness of the second transmission pattern is the first thickness d1.
  • Step S112' increase the thickness of the second transmission line pattern from the first thickness to the second thickness to obtain a second transmission line pattern with a second thickness.
  • the thickness of the first transmission line pattern is increased from the first thickness d1 to the second thickness d2 by locally adding copper, for example, 1OZ.
  • the second transmission line pattern formed on the inner core board increase the thickness of the second transmission pattern from the first thickness d1 to the second thickness d2 through electroplating or other methods, and perform a film stripping process to remove excess photoresist.
  • Step S113' forming a first transmission line pattern in the first area of the layer structure body.
  • a first transmission line pattern is formed in the first region of the layer structure body, and the thickness of the first transmission pattern is the first thickness d1.
  • film processing is performed, photoresist is applied, and the inner layer is exposed using conventional methods.
  • the inner core board with the thickness difference of the transmission line 2 into an exposure machine containing a halogen lamp for exposure to achieve pattern transfer.
  • Etch the inner core board after the line exposure is completed. Due to the different thickness of the bottom copper, the etching parameters need to be adjusted appropriately to take into account both 0.5OZ and 1OZ copper etching to obtain the first transmission line pattern.
  • step S112' After the processing in step S112', the thickness of the copper on the inner core board will vary, which may easily lead to the film not being firmly adhered. Therefore, in the embodiment of the present disclosure, a vacuum lamination process is added to ensure complete dry film lamination.
  • forming the first transmission line pattern in the first area of the layer structure body includes the following steps: forming a first transmission line pattern in the first area of the layer structure body through exposure, development, and etching.
  • the photoresist is bonded to the first area of the layer structure body by vacuum lamination before exposure.
  • Embodiments of the present disclosure provide two ways to form the thickness difference of the transmission line in the first area and the second area, which can not only meet the manufacturability of small-pitch pins, but also meet the signal integrity required by high-speed products.
  • One way is: the original copper thickness is 1OZ, first reduce the copper thickness of the transmission line 2 in the first area from 1OZ to 0.5OZ, and keep the original copper thickness in the second area unchanged; the second way is: the original copper thickness The thickness is 0.5OZ. Increase the copper thickness of the transmission line 2 in the second area from 0.5OZ to 1OZ. The copper thickness in the first area remains unchanged.
  • the copper thickness in the first area is reduced to 0.5OZ, which can etch 2/2mil or even 1.5/1.5mil ultra-precision lines, greatly reducing the space required for differential lines and making 0.6mm pin spacing possible.
  • FIG. 6 is a schematic diagram comparing the insertion loss effects of a printed circuit board in the related art and a printed circuit board provided by an embodiment of the present disclosure.
  • FIG. 7 is an echo of a printed circuit board in the related art and a printed circuit board provided by an embodiment of the present disclosure. Comparison diagram of loss effect. The test experimental effect of the printed circuit board provided by the embodiment of the present disclosure will be described below with reference to FIGS. 6 and 7 .
  • the long dotted line curve in the figure is the signal insertion loss curve of the PCB board with 0.8mm pin spacing in the related technology
  • the short dotted line curve in the figure is the 1mm pin spacing in the related technology.
  • the signal insertion loss curve of the PCB board with a pin pitch of 0.6mm is the signal insertion loss curve of the PCB board with a pin pitch of 0.6mm according to the embodiment of the present disclosure.
  • the x-axis is frequency and the y-axis is insertion loss. It can be seen from Figure 6 that when the frequency reaches a certain value, the signal insertion loss curve of the PCB board with a 0.6mm pin spacing according to the embodiment of the present disclosure is closer to 0, and the signal loss is smaller.
  • the long dotted line curve in the figure is the signal return loss curve of a PCB board with a pin pitch of 0.8mm in the related art
  • the short dotted line curve in the figure is the signal echo of a PCB board with a pin pitch of 1mm in the related art.
  • Loss curve, the solid line curve in the figure is the signal return loss curve of the PCB board with a pin pitch of 0.6mm according to the embodiment of the present disclosure.
  • the x-axis is frequency and the y-axis is return loss.
  • the printed circuit board of the embodiment of the present disclosure solves the problem of taking into account the signal integrity and designability of metallized holes under high-speed transmission requirements.
  • the disclosed embodiments are suitable for high-speed printed circuit board design products, especially for wired products and wireless products with a speed of 224Gbps and above, and can be applied to printed circuit boards with a design speed of 224Gbps and above.
  • Such software may be distributed on computer-readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media).
  • computer storage medium includes any method or technology implemented for storage of information, such as computer readable instructions, data structures, program modules or other data. of volatile and non-volatile, removable and non-removable media.
  • Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disk (DVD) or other optical disk storage, magnetic cassettes, tapes, disk storage or other magnetic storage devices, or may Any other medium used to store the desired information and that can be accessed by a computer.
  • communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media .
  • Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted in a general illustrative sense only and not for purpose of limitation. In some instances, it will be apparent to those skilled in the art that, unless expressly stated otherwise, features, characteristics, and/or elements described in connection with a particular embodiment may be used alone, or may be used with features, characteristics, and/or elements described in connection with other embodiments. and/or used in combination with components. Accordingly, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the present disclosure as set forth in the appended claims.

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  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

一种印刷电路板，包括层结构本体(1)和用于传输信号的传输线(2)，传输线(2)位于层结构本体(1)内，层结构本体(1)包括第一区域和第二区域，第一区域为在层结构本体(1)内进行层间信号传输的区域，第二区域为除第一区域之外的区域；传输线(2)在第一区域的第一厚度(d1)小于传输线(2)在第二区域的第二厚度(d2)，且第一厚度(d1)小于或等于预设的第一阈值。一种电子设备和一种印刷电路板制备方法。

Description

印刷电路板、电子设备及印刷电路板制备方法
相关申请的交叉引用
本申请要求于2022年8月29日提交的中国专利申请NO.202211040198.7的优先权，该中国专利申请的内容通过引用的方式整体合并于此。
技术领域
本公开涉及印刷电路技术领域，具体涉及印刷电路板、电子设备及印刷电路板制备方法。
背景技术
PCB(Printed Circuit Board，印刷电路板)的112Gbps速率产品已开始商用化，224Gbps速率产品正在研究，遇到了较大的技术难题是：如何提升系统的SI(Signal Integrity，信号完整性)性能及提高带宽，印刷电路板作为系统中的重要组成部分，很大程度上决定了系统性能。
224Gbps芯片的引脚间距更小，对应的BGA(Ball Grid Array，球状引脚栅格阵列)区域的间距也更小。112Gbps芯片BGA区域的间距是1.0毫米(mm)，走3.5/3.5密尔(mil)双线，而224Gbps芯片BGA区域的间距减小到0.6mm布局双线。这就意味着，在0.6mm狭小的空间内且引脚厚度仍为1盎司(OZ)的情况下，需要布局2/2mil极小差分信号线，且不能影响信号传输可靠性，也不能提高PCB加工难度。因此，需要研究0.6mm小间距引脚的加工工艺。
公开内容
一方面，本公开实施例提供一种印刷电路板，包括层结构本体和用于传输信号的传输线，所述传输线位于所述层结构本体内，所述 层结构本体包括第一区域和第二区域，所述第一区域为在所述层结构本体内进行层间信号传输的区域，所述第二区域为除所述第一区域之外的区域；所述传输线在所述第一区域的第一厚度小于所述传输线在所述第二区域的第二厚度，且所述第一厚度小于或等于预设的第一阈值。
又一方面，本公开实施例还提供一种电子设备，包括如前所述的印刷电路板。
又一方面，本公开实施例还提供一种印刷电路板制备方法，用于制备如前所述的印刷电路板，包括：在形成层结构本体的过程中，在所述层结构本体的第一区域形成第一厚度的第一传输线图形，并在所述层结构本体的第二区域形成第二厚度的第二传输线图形，得到包括所述第一传输线图形和所述第二传输线图形的传输线图形；所述第一区域为在所述层结构本体内进行层间信号传输的区域，所述第二区域为除所述第一区域之外的区域；所述第一厚度小于所述第二厚度，且所述第一厚度小于或等于预设的第一阈值。
附图说明
图1为本公开实施例提供的印刷电路板的剖面结构示意图；
图2为本公开实施例提供的印刷电路板第一区域的俯视图；
图3为本公开实施例提供的印刷电路板制备方法流程示意图；
图4为本公开实施例提供的形成传输线图形的流程示意图；
图5为本公开实施例提供的形成传输线图形的流程示意图；
图6为相关技术中的印刷电路板与本公开实施例提供的印刷电路板的插入损耗效果对比示意图；
图7为相关技术中的印刷电路板与本公开实施例提供的印刷电路板的回波损耗效果对比示意图。
具体实施方式
在下文中将参考附图更充分地描述示例实施例，但是所述示例实施例可以以不同形式来体现，且本公开不应当被解释为限于本文阐 述的实施例。提供这些实施例的目的在于使本公开更加透彻和完整，并使本领域技术人员充分理解本公开的范围。
如本文所使用的，术语“和/或”包括一个或多个相关列举条目的任何和所有组合。
本文所使用的术语仅用于描述特定实施例，且不限制本公开。如本文所使用的，单数形式“一个”和“该”也包括复数形式，除非上下文另外清楚指出。还将理解的是，当本说明书中使用术语“包括”和/或“由……制成”时，指定存在特定特征、整体、步骤、操作、元件和/或组件，但不排除存在或可添加一个或多个其他特征、整体、步骤、操作、元件、组件和/或其群组。
本文所述实施例可借助本公开的理想示意图而参考平面图和/或截面图进行描述。因此，可根据制造技术和/或容限来修改示例图示。因此，实施例不限于附图中所示的实施例，而是包括基于制造工艺而形成的配置的修改。因此，附图中例示的区具有示意性属性，并且图中所示区的形状例示了元件的区的具体形状，但并不是限制性的。
除非另外限定，否则本文所用的所有术语(包括技术术语和科学术语)的含义与本领域普通技术人员通常理解的含义相同。还将理解，诸如在常用字典中限定的那些术语应当被解释为具有与其在相关技术以及本公开的背景下的含义一致的含义，且将不解释为具有理想化或过度形式上的含义，除非本文明确如此限定。
本公开实施例提供一种印刷电路板及一种印刷电路板制备方法，局部降低进行层间信号传输的区域位置的传输线的厚度(沿图1中上下方向的尺寸)，从而达到制作精密引脚的小间距要求。
图1为本公开实施例提供的印刷电路板的剖面结构示意图，图2为本公开实施例提供的印刷电路板的俯视图，结合图1和图2所示，本公开实施例提供的印刷电路板，包括层结构本体1和用于传输信号的传输线2，传输线2位于层结构本体1内，层结构本体1包括第一区域和第二区域，第一区域为在层结构本体1内进行层间信号传输的区域，第二区域为除第一区域之外的区域。传输线2在第一区域的第一厚度d1小于传输线2在第二区域的第二厚度d2，且第一厚度d1 小于或等于预设的第一阈值。
传输线2可以由金属铜制备形成，可以利用含铜芯板刻蚀形成，也可以是铜线路。
本公开实施例提供的印刷电路板，包括层结构本体1和用于传输信号的传输线2，传输线2位于层结构本体1内，层结构本体1包括第一区域和第二区域，第一区域为在层结构本体1内进行层间信号传输的区域，第二区域为层结构本体1内除第一区域之外的区域；传输线2在第一区域的第一厚度d1小于传输线2在第二区域的第二厚度d2，且第一厚度d1小于或等于预设的第一阈值；本公开实施例将传输线2在不同区域形成厚度差，既可满足小间距引脚的可制作性，又可满足高速率产品要求的信号完整性，能够兼顾信号完整性和印刷电路板的可设计加工性。
在一些实施方式中，传输线2为铜线，第一阈值为0.5盎司铜箔厚度(OZ)，也就是说，传输线2在第一区域的第一厚度d1≤0.5OZ。
在一些实施方式中，第二厚度d2大于或等于预设的第二阈值。在传输线2为铜线的情况下，第二阈值为1盎司铜箔厚度，也就是说，传输线2在第二区域的厚度d2≥1OZ。
在一些实施方式中，第一区域包括BGA区域和/或连接器区域，第一区域内设置有贯穿层结构本体的金属化孔(图1和2中未绘示)，金属化孔与传输线2连接，通过金属化孔将PCB板内部的传输线2引入PCB板的外层，与芯片引脚或连接器引脚等相连，形成完整的信号传输路径。
层结构本体可以是单层结构，也可以是多层结构，单层结构即为单层PCB板，多层结构即为多层PCB板。在本公开实施例中，如图1所示，所述印刷电路板为三层板，层结构本体1包括第一层结构11、第二层结构12和第三层结构13，第一层结构11、第二层结构12和第三层结构13层叠设置，各个层结构均为含铜芯板，两条传输线2分别位于第一层结构11和第二层结构12内。第一层结构11包括层叠设置的铜层111、第一介质层112和第二介质层113，传输线2位于第二介质层113内。第二层结构12与第一层结构11的结构相同， 第三层结构13与第一层结构11的区别在于，在第三层结构13的第二介质层内没有传输线2。需要说明的是，在第一层结构11远离第二层结构12的一侧以及第三层结构13远离第二层结构12的一侧还设置有外层线路14。第一介质层112和第二介质层113通常由树脂、玻璃纤维、填料等成分组成。
本公开实施例从传输线厚度差的设计角度出发，实现了兼顾引脚小间距的信号完整性和可设计加工性。
本公开实施例还提供一种电子设备，所述电子设备包括如前所述的印刷电路板。
本公开实施例还提供一种印刷电路板制备方法，用于制备如前所述的印刷电路板，如图3所示，所述印刷电路板制备方法包括以下步骤S11。
步骤S11，在形成层结构本体的过程中，在层结构本体的第一区域形成第一厚度的第一传输线图形，并在层结构本体的第二区域形成第二厚度的第二传输线图形，得到包括第一传输线图形和第二传输线图形的传输线图形。
第一区域为在层结构本体内进行层间信号传输的区域，第二区域为除第一区域之外的区域；第一厚度小于第二厚度，且第一厚度小于或等于预设的第一阈值。
需要说明的是，对于多层PCB板而言，在形成包括第一传输线图形和第二传输线图形的传输线图形之后，还要进行压合处理，把半固化片和制作好的内层芯板进行叠合层压，从而形成多层PCB。
在本公开实施例提供的印刷电路板制备方法中，可以通过以下两种方式实现传输线2的第一厚度d1小于第二厚度d2：1、减小传输线2在第一区域的初始厚度；2、增加传输线2在第二区域的初始厚度，以下分别对这两种方式进行详细说明。
需要说明的是，在执行步骤S11之前，先制作设计PCB资料。
1、在EDA(电子设计自动化)制作资料前，进行信号仿真。针对PCB上对信号完整性有瓶颈的BGA和连接器区域，进行薄铜/厚铜设计。
2、在PCB设计资料中，找到需要制作局部镀薄铜/厚铜的区域。镀薄铜的区域是指定的BGA区域或连接器区域(第一区域)，镀厚铜的区域是其他区域(第二区域)。
3、对上述区域(第一区域/第二区域)分别标记薄铜/厚铜标识。
4、制作减铜/加铜菲林资料。仅把需要减铜/加铜的区域露出来。
5、增加减铜/加铜流程。针对减铜方式，在内层刻蚀前增加贴膜曝光减铜的流程；针对加铜方式，在内层刻蚀前增加贴膜曝光电镀的流程，再进行正常的内层刻蚀、棕化、层压及钻孔等后续流程。
在一些实施方式中，如图4所示，所述在层结构本体的第一区域形成第一厚度的第一传输线图形，并在层结构本体的第二区域形成第二厚度的第二传输线图形(即步骤S11)包括以下步骤S111至S113。
步骤S111，在层结构本体的第一区域和第二区域形成第二厚度的第一铜层，并在第一区域内在第一铜层上形成第一传输线图形。
传输线2的初始厚度为第二厚度d2，例如为1OZ。在本步骤S111中，在第一区域和第二区域形成第一铜层，该第一铜层的厚度为第二厚度d2，并在第一区域内的第二铜层上形成第一传输图形,该第一传输线图形的厚度为第二厚度d2。在内层芯板(未形成内层图形转移的芯板)的表面覆盖一层干膜(即光刻胶)，将贴好干膜的内层芯板在曝光机台上在第一区域位置采用减铜菲林进行曝光处理，进行减铜图形转移，形成第二厚度d2的第一传输线图形。
步骤S112，将第一传输线图形的厚度从第二厚度减小到第一厚度，得到第一厚度的第一传输线图形。
在本步骤S112中，通过局部减铜的方式将第一传输线图形的厚度从第二厚度d2减小至第一厚度d1，例如为0.5OZ。对内层芯板上形成的第一传输线图形通过刻蚀等方式，将第一传输图形的厚度从第二厚度d2减至第一厚度d1，并进行退膜处理，去除多余的光刻胶。
步骤S113，在层结构本体的第二区域形成第二传输线图形。
在本步骤S113中，在层结构本体的第二区域形成第二传输线图形，第二传输图形的厚度即为第二厚度d2。先进行贴膜处理，涂覆光刻胶，并采用常规方式进行内层曝光。把完成贴膜的具有传输线2 铜厚高低差的内层芯板放入含有卤素灯的曝光机台中进行曝光，实现图形转移。对完成线路曝光的内层芯板进行刻蚀，因底铜厚度不同，刻蚀参数需适当调整，以兼顾0.5OZ和1OZ铜刻蚀，得到第二传输线图形。
由于经过步骤S112的处理后，内层芯板上的铜厚度出现高低差，容易导致贴膜不牢。因此，在本公开实施例中增加真空压膜流程，使干膜贴合完整。相应的，在一些实施方式中，所述在层结构本体的第二区域形成第二传输线图形(即步骤S113)包括以下步骤：通过曝光、显影、刻蚀在层结构本体的第二区域形成第二传输线图形，在曝光之前采用真空压膜的方式将光刻胶贴合在层结构本体的述第二区域。
在一些实施方式中，如图5所示，所述在层结构本体的第一区域形成第一厚度的第一传输线图形，并在层结构本体的第二区域形成第二厚度的第二传输线图形(即步骤S11)包括以下步骤S111’至S113’。
步骤S111’，在层结构本体的第一区域和第二区域形成第一厚度的第二铜层，并在第二区域内在第二铜层上形成第二传输线图形。
传输线2的初始厚度为第一厚度d1，例如为0.5OZ。在本步骤S111’中，在第一区域和第二区域形成第二铜层，该第二铜层的厚度为第一厚度d1，并在第二区域内的第二铜层上形成第二传输图形，该第二传输图形的厚度为第一厚度d1。在内层芯板(未形成内层图形转移的芯板)的表面覆盖一层干膜(即光刻胶)，将贴好干膜的内层芯板，在曝光机台上在第二区域位置采用加铜菲林进行曝光处理，进行加镀铜图形转移，形成第一厚度d1的第二传输线图形。
步骤S112’，将第二传输线图形的厚度从第一厚度增加到第二厚度，得到第二厚度的第二传输线图形。
在本步骤S112’中，通过局部加铜的方式将第一传输线图形的厚度从第一厚度d1增加至第二厚度d2，例如为1OZ。对内层芯板上形成的第二传输线图形通过电镀等方式，将第二传输图形的厚度从第一厚度d1增加第二厚度d2，并进行退膜处理，去除多余的光刻胶。
步骤S113’，在层结构本体的第一区域形成第一传输线图形。
在本步骤S113’中，在层结构本体的第一区域形成第一传输线图形，第一传输图形的厚度即为第一厚度d1。先进行贴膜处理，涂覆光刻胶，并采用常规方式进行内层曝光。把完成贴膜的具有传输线2铜厚高低差的内层芯板放入含有卤素灯的曝光机台中进行曝光，实现图形转移。对完成线路曝光的内层芯板进行刻蚀，因底铜厚度不同，刻蚀参数需适当调整，以兼顾0.5OZ和1OZ铜刻蚀，得到第一传输线图形。
由于经过步骤S112’的处理后，内层芯板上的铜厚度出现高低差，容易导致贴膜不牢。因此，在本公开实施例中增加真空压膜流程，使干膜贴合完整。
相应的，在一些实施方式中，所述在层结构本体的第一区域形成第一传输线图形(即步骤S113’)包括以下步骤：通过曝光、显影、刻蚀在层结构本体的第一区域形成第一传输线图形，在曝光之前采用真空压膜的方式将光刻胶贴合在层结构本体的第一区域。
本公开实施例提供两种方式形成传输线在第一区域和第二区域的厚度差，既可满足小间距引脚的可制作性，又可满足高速率产品要求的信号完整性。一种方式是：原始铜厚为1OZ，先把传输线2在第一区域的铜厚从1OZ降低到0.5OZ，第二区域的铜厚保持原始铜厚不变；第二种方式是：原始铜厚为0.5OZ，把传输线2在第二区域的铜厚从0.5OZ增加到1OZ，第一区域的铜厚保持原始铜厚不变。第一区域的铜厚降低到0.5OZ，可刻蚀出2/2mil甚至1.5/1.5mil超精密线路，大大缩小了差分线需要的空间，使0.6mm引脚间距成为可能。
图6为相关技术中的印刷电路板与本公开实施例提供的印刷电路板的插入损耗效果对比示意图，图7为相关技术中的印刷电路板与本公开实施例提供的印刷电路板的回波损耗效果对比示意图。以下结合图6和图7对本公开实施例提供的印刷电路板的测试实验效果进行说明。
如图6所示，图中长虚线曲线为相关技术中0.8mm引脚间距的PCB板的信号插入损耗曲线，图中短虚线曲线为相关技术中1mm引脚 间距的PCB板的信号插入损耗曲线，图中实线曲线为本公开实施例0.6mm引脚间距的PCB板的信号插入损耗曲线。图6中x轴为频率，y轴为插入损耗。从图6中可以看出，当频率达到一定值时，本公开实施例0.6mm引脚间距的PCB板的信号插入损耗曲线更接近0，信号损耗更小。
如图7所示，图中长虚线曲线为相关技术中0.8mm引脚间距的PCB板的信号回波损耗曲线，图中短虚线曲线为相关技术中1mm引脚间距的PCB板的信号回波损耗曲线，图中实线曲线为本公开实施例0.6mm引脚间距的PCB板的信号回波损耗曲线。图7中x轴为频率，y轴为回波损耗。从图7中可以看出，当频率达到一定值时，相关技术的0.8mm引脚间距和1mm引脚间距的PCB板的信号回波损耗相对于本公开实施例0.6mm引脚间距的PCB板的信号回波损耗更接近0，信号损耗更大。
本公开实施例的印刷电路板，解决了高速率传输要求下，兼顾金属化孔的信号完整性和可设计加工性的问题。
本公开实施例适用于有高速率的印刷电路板设计产品，尤其适合224Gbps速率及以上的有线产品和无线产品，可以应用于设计速率达到224Gbps及以上的印刷电路板。
本领域普通技术人员可以理解，上文中所公开方法中的全部或某些步骤、装置中的功能模块/单元可以被实施为软件、固件、硬件及其适当的组合。在硬件实施方式中，在以上描述中提及的功能模块/单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由若干物理组件合作执行。某些物理组件或所有物理组件可以被实施为由处理器(如中央处理器、数字信号处理器或微处理器)执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其他数据)的任何方法或技术中实施 的易失性和非易失性、可移除和不可移除介质。计算机存储介质包括但不限于RAM、ROM、EEPROM、闪存或其他存储器技术、CD-ROM、数字多功能盘(DVD)或其他光盘存储、磁盒、磁带、磁盘存储或其他磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的任何其他的介质。此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。
本文已经公开了示例实施例，并且虽然采用了具体术语，但它们仅用于并仅应当被解释为一般说明性含义，并且不用于限制的目的。在一些实例中，对本领域技术人员显而易见的是，除非另外明确指出，否则与特定实施例相结合描述的特征、特性和/或元素可单独使用，或可与结合其他实施例描述的特征、特性和/或元件组合使用。因此，本领域技术人员将理解，在不脱离由所附的权利要求阐明的本公开的范围的情况下，可进行各种形式和细节上的改变。

Claims (10)

  1. 一种印刷电路板，包括层结构本体和用于传输信号的传输线，所述传输线位于所述层结构本体内，所述层结构本体包括第一区域和第二区域，所述第一区域为在所述层结构本体内进行层间信号传输的区域，所述第二区域为除所述第一区域之外的区域；
    所述传输线在所述第一区域的第一厚度小于所述传输线在所述第二区域的第二厚度，且所述第一厚度小于或等于预设的第一阈值。
  2. 如权利要求1所述的印刷电路板，其中，所述传输线为铜线，所述第一阈值为0.5盎司铜箔厚度。
  3. 如权利要求1所述的印刷电路板，其中，所述第二厚度大于或等于预设的第二阈值。
  4. 如权利要求3所述的印刷电路板，其中，所述传输线为铜线，所述第二阈值为1盎司铜箔厚度。
  5. 一种电子设备，包括如权利要求1至4中任一项所述的印刷电路板。
  6. 一种印刷电路板制备方法，用于制备如权利要求1至4中任一项所述的印刷电路板，包括：
    在形成层结构本体的过程中，在所述层结构本体的第一区域形成第一厚度的第一传输线图形，并在所述层结构本体的第二区域形成第二厚度的第二传输线图形，得到包括所述第一传输线图形和所述第二传输线图形的传输线图形；
    其中，所述第一区域为在所述层结构本体内进行层间信号传输的区域，所述第二区域为除所述第一区域之外的区域；所述第一厚度小于所述第二厚度，且所述第一厚度小于或等于预设的第一阈值。
  7. 如权利要求6所述的方法，其中，所述在所述层结构本体的第一区域形成第一厚度的第一传输线图形，并在所述层结构本体的第二区域形成第二厚度的第二传输线图形包括：
    在所述层结构本体的所述第一区域和所述第二区域形成第二厚度的第一铜层，并在所述第一区域内在所述第一铜层上形成第一传输线图形；
    将所述第一传输线图形的厚度从所述第二厚度减小到第一厚度，得到所述第一厚度的第一传输线图形；以及
    在所述层结构本体的所述第二区域形成第二传输线图形。
  8. 如权利要求7所述的方法，其中，所述在所述层结构本体的所述第二区域形成第二传输线图形包括：
    通过曝光、显影、刻蚀在所述层结构本体的所述第二区域形成第二传输线图形，其中，在曝光之前采用真空压膜的方式将光刻胶贴合在所述层结构本体的所述第二区域。
  9. 如权利要求6所述的方法，其中，所述在所述层结构本体的第一区域形成第一厚度的第一传输线图形，并在所述层结构本体的第二区域形成第二厚度的第二传输线图形包括：
    在所述层结构本体的所述第一区域和所述第二区域形成第一厚度的第二铜层，并在所述第二区域内在所述第二铜层上形成第二传输线图形；
    将所述第二传输线图形的厚度从所述第一厚度增加到第二厚度，得到所述第二厚度的第二传输线图形；以及
    在所述层结构本体的所述第一区域形成第一传输线图形。
  10. 如权利要求9所述的方法，其中，所述在所述层结构本体的所述第一区域形成第一传输线图形包括：
    通过曝光、显影、刻蚀在所述层结构本体的所述第一区域形成 第一传输线图形，其中，在曝光之前采用真空压膜的方式将光刻胶贴合在所述层结构本体的所述第一区域。
PCT/CN2023/110102 2022-08-29 2023-07-31 印刷电路板、电子设备及印刷电路板制备方法 WO2024045977A1 (zh)

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