WO2024041089A1 - 一种半导体结构及其制备方法、半导体存储器 - Google Patents

一种半导体结构及其制备方法、半导体存储器 Download PDF

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Publication number
WO2024041089A1
WO2024041089A1 PCT/CN2023/098559 CN2023098559W WO2024041089A1 WO 2024041089 A1 WO2024041089 A1 WO 2024041089A1 CN 2023098559 W CN2023098559 W CN 2023098559W WO 2024041089 A1 WO2024041089 A1 WO 2024041089A1
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Prior art keywords
bit line
staggered
structures
substrate
line structures
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PCT/CN2023/098559
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English (en)
French (fr)
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黄猛
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长鑫存储技术有限公司
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Publication of WO2024041089A1 publication Critical patent/WO2024041089A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to, but is not limited to, a semiconductor structure, a preparation method thereof, and a semiconductor memory.
  • Sensing Margin is one of the important characteristic parameters of Dynamic Random Access Memory (DRAM).
  • DRAM Dynamic Random Access Memory
  • Embodiments of the present disclosure provide a semiconductor structure, a preparation method thereof, and a semiconductor memory.
  • embodiments of the present disclosure provide a semiconductor structure, including:
  • a stacked structure formed above the substrate wherein the stacked structure includes a plurality of device structures and a plurality of word line structures, the device structures extend along a first direction, and the word line structures extend along a second direction;
  • the device structure includes a capacitive region and an active region in sequence;
  • a plurality of bit line structures are formed in the stacked structure, and the bit line structures extend along a third direction; wherein the bit line structures sequentially pass through the bit line structures arranged along the third direction in different stacked layers.
  • Source region wherein any two adjacent bit line structures are at least partially staggered along a second direction, and the first direction and the second direction are located parallel to the plane where the surface of the substrate is located, so The third direction is perpendicular to the surface of the substrate.
  • embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, including:
  • the device structure extends along a first direction
  • the word line structure extends along a second direction
  • the bit line structure extends along a third direction
  • the device structure sequentially includes a capacitive region and an active region
  • the bit The line structures pass through the active areas arranged along the third direction in different stacked layers in sequence, wherein any two adjacent bit line structures are at least partially staggered along the second direction, and the first direction and The second direction is located parallel to the plane of the surface of the substrate, and the third direction is perpendicular to the surface of the substrate. surface.
  • embodiments of the present disclosure provide a semiconductor memory, including the semiconductor structure according to any one of the first aspects.
  • Figure 1 is a schematic three-dimensional structural diagram of a semiconductor structure
  • Figure 2 is a schematic three-dimensional structural diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 3 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 4 is a schematic diagram 1 of a staggered unit provided by an embodiment of the present disclosure.
  • Figure 5 is a schematic diagram 2 of a staggered unit provided by an embodiment of the present disclosure.
  • Figure 6 is a comparative schematic diagram of a bit line structure provided by an embodiment of the present disclosure.
  • Figure 7 is a schematic flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 8 is a schematic diagram of the preparation process of a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 9 is a schematic diagram 2 of the preparation process of a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 10 is a schematic diagram 3 of the preparation process of a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 11 is a schematic diagram 4 of the preparation process of a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 12 is a schematic diagram 5 of the preparation process of a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 13 is a schematic diagram 6 of the preparation process of a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 14 is a schematic diagram 7 of the preparation process of a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 15 is a schematic diagram 8 of the preparation process of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 16 is a schematic structural diagram of a semiconductor memory provided by an embodiment of the present disclosure.
  • first ⁇ second ⁇ third involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understandable that "first ⁇ second ⁇ third” Where permitted, the specific order or sequence may be interchanged so that the disclosed embodiments described herein can be practiced in other sequences than illustrated or described herein.
  • the semiconductor structure includes a substrate (not shown), a word line structure 101 , a capacitor region 102 , and a bit line structure 103 .
  • the word line structure 101 and the active region below it together form a transistor.
  • the pseudocapacitance of the bit line structure 103 is large, reducing the sensing margin of the device.
  • a semiconductor structure including: a substrate; a stacked structure formed above the substrate; wherein the stacked structure includes a plurality of device structures and a plurality of word line structures, and the device structures are along a first direction.
  • the word line structure extends along the second direction; the device structure sequentially includes a capacitor region and an active region; multiple bit line structures are formed in the stacked structure, and the bit line structure extends along the third direction; wherein, the bit line structure sequentially Passing through the active areas arranged along the third direction in different stacked layers, wherein any two adjacent bit line structures are at least partially staggered along the second direction, and the first direction and the second direction are located parallel to the substrate The plane in which the surface lies, with the third direction perpendicular to the surface of the substrate. In this way, a bit line structure at least partially staggered along the second direction is formed in the semiconductor structure, which can reduce the bit line capacitance, thereby improving the sensing margin of the device.
  • FIG. 2 shows a schematic three-dimensional structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • the semiconductor structure 200 may include:
  • a stacked structure formed above the substrate wherein the stacked structure includes a plurality of device structures 21 and a plurality of word line structures 22, the device structures 21 extend along the first direction, and the word line structures 22 extend along the second direction; the device structures 21 sequentially Includes active area 211 and capacitive area 212;
  • a plurality of bit line structures 23 are formed in the stacked structure, and the bit line structures 23 extend along the third direction; wherein, the bit line structures 23 sequentially pass through the active areas 211 arranged along the third direction in different stacked layers, wherein , any two adjacent bit line structures 23 are arranged at least partially staggered along the second direction, the first direction and the second direction are located parallel to the plane where the surface of the substrate is located, and the third direction is perpendicular to the surface of the substrate.
  • the semiconductor structure 200 can be applied to dynamic random access memory (Dynamic Random Access Memory, DRAM), such as three-dimensional DRAM (Three Dimensional DRAM, 3D DRAM). In the 3D DRAM, multiple spatial stacks are formed. Semiconductor structure 200.
  • DRAM Dynamic Random Access Memory
  • 3D DRAM Three-dimensional DRAM (Three Dimensional DRAM, 3D DRAM).
  • multiple spatial stacks are formed.
  • Semiconductor structure 200 In order to improve the sensing margin of the device, the sensing margin of the device can be improved by increasing the capacitance of the capacitor or by reducing the capacitance of the bit line. In the embodiment of the present disclosure, it is expected that the bit line structure 23 will be staggered. Reduce the bit line capacitance, thereby improving the device's sensing margin.
  • the substrate may be a silicon substrate or other semiconductor elements, such as germanium (Ge), or include semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), and gallium phosphide (GaP).
  • germanium germanium
  • semiconductor compounds such as silicon carbide (SiC), gallium arsenide (GaAs), and gallium phosphide (GaP).
  • indium phosphide InP
  • indium arsenide InAs
  • indium antimonide InSb
  • other semiconductor alloys such as: silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs) ), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), and/or indium gallium arsenide phosphide (GaInAsP) or combinations thereof, which are not specifically limited in the embodiments of the present disclosure. .
  • the stacked structure may include a device structure 21, a word line structure 22 and a bit line structure 23.
  • the device structure 21 may also include an active region 211 and a capacitive region 212; wherein, the first direction is It refers to the direction extending along the device structure 21 , the second direction refers to the direction extending along the word line structure 22 , and the third direction refers to the direction extending along the bit line structure 23 .
  • the material of the active region 211 can be silicon (Si), which can be divided into a plurality of doped regions, with different doping regions.
  • the impurity region has different doping types, such as N-type doping (providing free electrons) and P-type doping (providing holes); among them, N-type doping can be doped with pentavalent impurity elements such as phosphorus, antimony, and arsenic; P Type doping can be doped with trivalent impurity elements such as boron, gallium, and indium.
  • each word line structure 22 passes through multiple active areas 211 of the same stacked layer.
  • the active areas 211 located below the word line structure 22 and the active areas 211 located on both sides of the word line structure 22 The source region 211 has different doping types to form a transistor, while the word line structure 22 leads to the gate of the transistor; the bit line structure 23 passes through multiple active regions 211 of different stacked layers, thereby leading to the drain/source of the transistor. pole.
  • two adjacent transistors share a bit line structure 23 .
  • the bit line structures 23 are arranged in a staggered manner, which can reduce the bit line capacitance and improve the sensing margin of the device.
  • every n bit line structures 23 may form a staggered unit.
  • the distance from each bit line structure 23 to the word line structure 22 on the first side gradually increases;
  • the distance from each bit line structure 23 to the word line structure 22 on the first side gradually decreases from the a to nth bit line structures 23; wherein, the first side is against the extension direction of the first direction or along the extension direction of the first side.
  • the extension direction of one direction; a and n are both integers greater than 1, and a is less than n.
  • FIG. 4 shows a schematic diagram 1 of a staggered unit provided by an embodiment of the present disclosure.
  • FIG. 4 is a top view of a staggered unit in FIG. 2 .
  • the staggered unit may also include seven bit line structures 23; accordingly, for the first to fourth bit line structures 23, the distance from each bit line structure 23 to the word line structure 22 gradually increases.
  • the staggered unit may also include 8 bit line structures 23; accordingly, for the 4th to 7th bit line structures 23, For the 1st to 4th bit line structures 23, the distance between each bit line structure 23 and the word line structure 22 gradually increases; for the 4th to 8th bit line structures 23, the distance between each bit line structure 23 and the word line structure 23 gradually increases. The distance of 22 gradually decreases.
  • the distance between each bit line structure 23 and the word line structure 22 on the first side gradually increases; wherein the first side is opposite to the first side.
  • the extension direction in one direction or the extension direction along the first direction; n is an integer greater than 1.
  • FIG. 5 shows a second schematic diagram of staggered units provided by an embodiment of the present disclosure.
  • the distance from each bit line structure 23 to the word line structure 22 gradually increases, that is, a similar ladder-like arrangement is formed.
  • two adjacent bit line structures 23 are partially staggered; wherein the relative area of the two adjacent bit line structures 23 is less than one-third of the projected area of the bit line structure 23 one.
  • bit line structures 23 can be partially interleaved while keeping the relative area at a low level, which not only reduces the capacitance but also reduces the area occupied by the bit line structures 23 .
  • two adjacent bit line structures 23 are completely staggered; wherein the relative area of the two adjacent bit line structures 23 is zero.
  • bit line structures 23 can be completely interleaved, which can achieve the best capacitance reduction effect.
  • the bit line structure 23 further includes an outer wall of a barrier layer and a metal material filled in the outer wall of the barrier layer; wherein the barrier layer material includes titanium nitride (TiN) and the metal material includes tungsten (W).
  • the barrier layer material includes titanium nitride (TiN) and the metal material includes tungsten (W).
  • the metal materials may also include cobalt (Co), copper (Cu), aluminum (Al), etc.
  • the material forming the bit line structure 23 may be a combination of titanium nitride and tungsten, or a combination of other materials. , the embodiment of the present disclosure does not specifically limit this.
  • FIG. 6 a comparative schematic diagram of a bit line structure provided by an embodiment of the present disclosure is shown. Specifically, (a) in FIG. 6 shows a bit line structure without staggering, and (b) in FIG. 6 shows a bit line structure 23 with staggering.
  • the capacitance value of the bit line structure 23 in (b) in FIG. 6 after staggering is 58.4% of the capacitance value of the bit line structure in (a) in FIG. 6 .
  • the bit line capacitance becomes smaller, and thus can be improved. Sensing margin of semiconductor structure 200 .
  • Embodiments of the present disclosure provide a semiconductor structure, including: a substrate; a stacked structure formed above the substrate; wherein the stacked structure includes a plurality of device structures and a plurality of word line structures, the device structures extend along a first direction, and the words The line structure extends along the second direction; the device structure sequentially includes a capacitor region and an active region; multiple bit line structures are formed in the stacked structure, and the bit line structure extends along the third direction; wherein the bit line structures pass through different The active area arranged along the third direction in the stacked layer, wherein any two adjacent bit line structures are at least partially staggered along the second direction, and the first direction and the second direction are located parallel to the surface of the substrate. plane, the third direction is perpendicular to the surface of the substrate. In this way, a bit line structure at least partially staggered along the second direction is formed in the semiconductor structure, which can reduce the bit line capacitance and improve the sensing margin of the device.
  • FIG. 7 shows a schematic flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure. As shown in Figure 7, the method may include:
  • the preparation method provided by the embodiment of the present disclosure is applied to prepare the aforementioned semiconductor structure 200, and the semiconductor structure 200 can be applied in DRAM, such as 3D DRAM.
  • the substrate may be a silicon substrate.
  • the substrate may also include other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC). , gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb), or include other semiconductor alloys, such as silicon germanium (SiGe), Gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and/or gallium indium arsenide phosphide (GaInAsP ) or combinations thereof, the embodiments of the present disclosure do not specifically limit this.
  • FIG. 8 shows a schematic diagram 1 of the preparation process of a semiconductor structure provided by an embodiment of the present disclosure.
  • (a) is along the line in Figure 3
  • the cross-sectional views of a-a' and (b) are both along the cross-section of b-b' in Figure 3.
  • the hollow portion in Figure 3 is also filled with material.
  • the substrate 401 may first be pre-cleaned, and then an initial stack structure 40 is formed over the substrate 401 , and the initial stack structure 40 includes at least one stack layer.
  • forming an initial stack structure above the substrate includes:
  • a plurality of silicide regions arranged along the second direction are formed in the silicon layer, and the bit line structures pass through the silicide regions in different stacked layers in sequence.
  • each stacked layer includes an insulating layer 402 and a silicon layer 403, and the silicon layer 403 is formed above the insulating layer 402. Specifically, the steps of forming an insulating layer 402 and a silicon layer 403 over the substrate 401 are repeated until a required number of stacked layers is obtained. In practical applications, the number of stacked layers may be any required number, which is not specifically limited in the embodiments of the present disclosure.
  • the material of the insulating layer 402 may be silicon oxide, and the material of the silicon layer 403 may be polysilicon.
  • the insulating layer 402 and the silicon layer 403 can be formed by any of the following deposition processes: epitaxial process, chemical vapor deposition (Chemical Vapor Deposition, CVD) process, physical vapor deposition (Physical Vapor Deposition, PVD) process, atomic layer deposition (Atomic Layer Deposition) , ALD) process, spin coating process, coating process or thin film process, etc.; for example, the insulating layer 402 and the silicon layer 403 can be sequentially formed on the semiconductor substrate 401 through an epitaxial process.
  • S303 Form multiple device structures, multiple word line structures and multiple bit line structures in the initial stacked structure; wherein the device structures extend along the first direction, the word line structures extend along the second direction, and the bit line structures extend along the third direction. direction extends; the device structure includes a capacitive region and an active region in sequence; the bit line structure sequentially passes through the active regions arranged along the third direction in different stacked layers, wherein any two adjacent bit line structures are arranged along the second direction.
  • the arrangement is at least partially staggered, with the first direction and the second direction being parallel to a plane where the surface of the substrate is located, and the third direction being perpendicular to the surface of the substrate.
  • the silicon layer 403 is subsequently used to form the active region 211 in the device structure 21 .
  • Each word line structure 22 passes through multiple active regions 211 of the same stacked layer.
  • the active regions 211 located below the word line structure 22 and the active regions 211 located on both sides of the word line structure 22 have different doping types.
  • a transistor is formed, and at the same time, the word line structure 22 leads to the gate of the transistor; the bit line structure 23 passes through multiple active regions 211 of different stacked layers, thereby leading to the drain/source of the transistor.
  • two adjacent transistors share a bit line structure 23 .
  • a plurality of silicide regions 404 arranged along the second direction need to be formed in each silicon layer 403 , and the silicide regions 404 are subsequently used to form the bit line structure 23 .
  • the following provides an exemplary method for forming the silicide region 404 .
  • Figure 9 shows a semi-automatic method provided by an embodiment of the present disclosure.
  • a patterning process or other processes may be performed on the initial stacked structure 40 to form a first trench 406 in the initial stacked structure 40 .
  • the method of patterning the initial stacked structure 40 may be as follows: first forming a first mask layer above the initial stacked structure 40, and then forming a first photoresist layer above the first mask layer.
  • the photoresist layer has the first pattern required to form the first trench 406, transfer the first pattern to the first mask layer, remove the first photoresist layer, and then continue using the first mask layer as a mask.
  • the first pattern is transferred to the initial stack structure 40 and the first mask layer is removed to form the first trench 406 .
  • the method of removing the first photoresist layer and the first mask layer may be etching, and the method of transferring the first pattern to the initial stacked structure 40 may also be etching.
  • FIG. 10 shows a schematic diagram 3 of the preparation process of a semiconductor structure provided by an embodiment of the present disclosure.
  • the first trench 406 needs to be filled with an insulating material.
  • the filled insulating material is the same as the material of the insulating layer 402 , and may be silicon oxide.
  • the method of filling the first trench 406 may be a variety of deposition processes.
  • FIG. 11 shows a schematic diagram 4 of the preparation process of a semiconductor structure provided by an embodiment of the present disclosure.
  • the method of forming the second trench 407 can be etching.
  • An appropriate etching selectivity can be selected to remove only part of the silicon.
  • the layer 403 is removed by etching, but the insulating layer 402 will not be removed by etching.
  • FIG. 12 shows a schematic diagram 5 of the preparation process of a semiconductor structure provided by an embodiment of the present disclosure.
  • conductive material such as metal, polysilicon, etc.
  • the method of filling the second trench 407 can be for deposition.
  • the silicide region 404 can also be formed by subjecting the silicon layer 403 where the bit line structure 23 needs to be formed to a metal silicide treatment, and then drilling the silicide regions 404 arranged along the second direction to subsequently form the bit lines. Structure 23. In this way, multiple silicide regions 404 are formed through the above method, which can reduce the contact resistance between the bit line structure 23 and the transistor.
  • the silicide region 404 may not be formed, but holes may be directly drilled in the silicon layer 403, and then the bit line structure 23 may be formed.
  • those skilled in the art can also use any feasible method in the art to implement, and there is no specific limitation on this.
  • the method further includes:
  • the mask layer is used to transfer the preset pattern to the initial stack structure, and the mask layer is removed to form multiple trenches; wherein the trenches pass through the insulating layer and the silicide area in sequence;
  • the trenches are filled to form multiple bit line structures.
  • Figure 13 shows a schematic diagram 6 of the preparation process of a semiconductor structure provided by an embodiment of the present disclosure.
  • a mask layer 408 is first formed on the surface of the initial stacked structure 40 , and a mask layer 408 is formed on the mask layer 408 .
  • the preset pattern is at least partially staggered along the second direction; wherein, the material of the mask layer 408 may be silicon oxide, silicon nitride, silicon carbide, oxynitride, etc.
  • the mask layer 408 can be formed by any suitable deposition process.
  • FIG. 14 shows a schematic diagram 7 of the preparation process of a semiconductor structure provided by an embodiment of the present disclosure.
  • the preset pattern is transferred to the initial stack structure 40 using the mask layer 408 as a mask, and the mask layer 408 is removed, as shown in Figure 14.
  • the method of removing the mask layer 408 may be etching
  • the method of transferring the preset pattern to the initial stack structure 40 may also be etching, specifically a dry etching process or a wet etching process.
  • the gas used in dry etching can be trifluoromethane (CHF3), carbon tetrafluoride (CF4), difluoromethane (CH2F2), hydrobromic acid (HBr), chlorine (Cl2) or sulfur hexafluoride (SF6) one or any combination of them.
  • CHF3 trifluoromethane
  • CF4 carbon tetrafluoride
  • CH2F2 difluoromethane
  • HBr hydrobromic acid
  • chlorine Cl2
  • sulfur hexafluoride SF6 one or any combination of them.
  • Wet etching can use strong acids such as concentrated sulfuric acid, hydrofluoric acid, and concentrated nitric acid for etching.
  • FIG. 15 shows a schematic diagram 8 of the preparation process of a semiconductor structure provided by an embodiment of the present disclosure.
  • the trench 409 needs to be filled to form the bit line structure 23 .
  • a chemical mechanical polishing (CMP) process may also be performed to make the top surface of the semiconductor structure 200 flat.
  • filling the trenches to form multiple bit line structures may include:
  • the hollow area surrounded by the outer wall of the barrier layer is filled with metal material to form multiple bit line structures.
  • the material of the outer wall 4051 of the barrier layer may include titanium nitride, and the metal material 4052 may include tungsten; the metal material 4052 may also include cobalt (Co), copper (Cu), or aluminum (Al) etc., the material forming the bit line structure 23 may be a combination of titanium nitride and tungsten, or a combination of other materials, which is not specifically limited in the embodiment of the present disclosure.
  • the preset patterns used to form the trenches 409 are staggered, as detailed below.
  • the preset pattern is at least partially staggered along the second direction.
  • the preset pattern includes at least one staggered unit, and each staggered unit includes n bit line patterns.
  • the bit line pattern is consistent with the formed plurality of bit lines. Line structures correspond to each other.
  • the preset pattern includes at least one staggered unit, and each staggered unit includes n bit line patterns; in the first direction, for the 1st to ath bit line patterns of the staggered unit, , the distance from each bit line pattern to the word line structure on the first side gradually increases; for the a-th to n-th bit line patterns of the staggered unit, the distance from each bit line pattern to the word line structure on the first side The distance gradually decreases; wherein, the first side is the extension direction against the first direction or along the first direction; a and n are both integers greater than 1, and a is less than n.
  • the bit line pattern can also form a pattern similar to a ladder arrangement.
  • the preset pattern includes at least one staggered unit, and each staggered unit includes n bit line patterns; in the In one direction, for staggered cells, the distance from each bit line pattern to the word line structure on the first side gradually increases. Increase; wherein, the first side is the extension direction counter to the first direction or the extension direction along the first direction; n is an integer greater than 1.
  • two adjacent bit line patterns are partially staggered; wherein the relative area of the two adjacent bit line patterns is less than one-third of the projected area of the bit line pattern.
  • two adjacent bit line patterns are completely staggered; wherein the relative area of the two adjacent bit line patterns is zero.
  • Embodiments of the present disclosure provide a method for preparing a semiconductor structure.
  • an initial stacked structure is first formed above the substrate, and the initial stacked structure includes a plurality of stacked layers; and then in the initial stacked structure Multiple device structures, multiple word line structures and multiple bit line structures are formed; wherein the device structures extend along the first direction, the word line structures extend along the second direction, and the bit line structures extend along the third direction; the device structures in turn include The capacitive area and the active area; the bit line structures pass through the active areas arranged along the third direction in different stacked layers in sequence, wherein any two adjacent bit line structures are at least partially staggered along the second direction, and the first The first and second directions lie parallel to a plane in which the surface of the substrate lies, and the third direction is perpendicular to the surface of the substrate. In this way, a bit line structure at least partially staggered along the second direction is formed in the semiconductor structure, which can reduce the bit line capacitance, thereby improving the sensing margin of
  • FIG. 16 shows a schematic structural diagram of a semiconductor memory 400 provided by an embodiment of the present disclosure.
  • the semiconductor memory 400 includes the semiconductor structure 200 described in any of the previous embodiments.
  • the semiconductor memory 400 may be 3D DRAM.
  • the semiconductor structure includes: a substrate; a stacked structure formed above the substrate; wherein the stacked structure includes a plurality of device structures and a plurality of A word line structure, the device structure extends along the first direction, and the word line structure extends along the second direction; the device structure sequentially includes a capacitor region and an active region; multiple bit line structures are formed in the stacked structure, and the bit line structures extend along the second direction.
  • bit line structures sequentially pass through the active areas arranged along the third direction in different stacked layers, wherein any two adjacent bit line structures are at least partially staggered along the second direction, and the first direction and the second direction is located parallel to a plane in which the surface of the substrate lies, and the third direction is perpendicular to the surface of the substrate.
  • a bit line structure at least partially staggered along the second direction is formed in the semiconductor structure, which can reduce the bit line capacitance and improve the sensing margin of the device.
  • Embodiments of the present disclosure provide a semiconductor structure, a preparation method thereof, and a semiconductor memory.
  • the semiconductor structure includes: a substrate; a stacked structure formed above the substrate; wherein the stacked structure includes a plurality of device structures and a plurality of word line structures. , the device structure extends along the first direction, and the word line structure extends along the second direction; the device structure sequentially includes a capacitor region and an active region; multiple bit line structures are formed in the stacked structure, and the bit line structure extends along the third direction.
  • bit line structures pass through active areas arranged along the third direction in different stacked layers in sequence, wherein any two adjacent bit line structures are at least partially staggered along the second direction, and the first direction and the second direction One direction lies parallel to the plane in which the surface of the substrate lies, and a third direction is perpendicular to the surface of the substrate.
  • a bit line structure at least partially staggered along the second direction is formed in the semiconductor structure, which can reduce the bit line capacitance and improve the sensing margin of the device.

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Abstract

本公开实施例提供了一种半导体结构及其制备方法、半导体存储器，该半导体结构包括：多个器件结构和多个字线结构，器件结构沿第一方向延伸，字线结构沿第二方向延伸；多个位线结构，且位线结构沿第三方向延伸；其中，任意相邻的两个位线结构沿第二方向至少部分错开排列。

Description

一种半导体结构及其制备方法、半导体存储器
相关申请的交叉引用
本公开要求在2022年08月23日提交中国专利局、申请号为202211012366.1、申请名称为“一种半导体结构及其制备方法、半导体存储器”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及但不限于一种半导体结构及其制备方法、半导体存储器。
背景技术
感应裕度(Sensing Margin)是动态随机存取存储器(Dynamic Random Access Memory，DRAM)的重要特性参数之一。目前，随着DRAM器件尺寸不断缩小，感应裕度变差，限制了存储器性能的进一步提高。
发明内容
本公开实施例提供了一种半导体结构及其制备方法、半导体存储器。
第一方面，本公开实施例提供了一种半导体结构，包括：
衬底；
形成于所述衬底上方的堆叠结构；其中，所述堆叠结构包括多个器件结构和多个字线结构，所述器件结构沿第一方向延伸，所述字线结构沿第二方向延伸；所述器件结构依次包括电容区和有源区；
形成于所述堆叠结构中的多个位线结构，且所述位线结构沿第三方向延伸；其中，所述位线结构依次穿过不同堆叠层中沿第三方向排布的所述有源区，其中，任意相邻的两个所述位线结构沿第二方向至少部分错开排列，所述第一方向和所述第二方向位于平行于所述衬底的表面所在的平面，所述第三方向垂直于所述衬底的表面。
第二方面，本公开实施例提供了一种半导体结构的制备方法，包括：
提供衬底；
于所述衬底上方形成初始堆叠结构，且所述初始堆叠结构包括多个堆叠层；
于所述初始堆叠结构中形成多个器件结构、多个字线结构和多个位线结构；
其中，所述器件结构沿第一方向延伸，所述字线结构沿第二方向延伸，所述位线结构沿第三方向延伸；所述器件结构依次包括电容区和有源区；所述位线结构依次穿过不同堆叠层中沿第三方向排布的所述有源区，其中，任意相邻的两个所述位线结构沿第二方向至少部分错开排列，所述第一方向和所述第二方向位于平行于所述衬底的表面所在的平面，所述第三方向垂直于所述衬底的 表面。
第三方面，本公开实施例提供了一种半导体存储器，包括如第一方面任一项所述的半导体结构。
附图说明
图1为一种半导体结构的立体结构示意图；
图2为本公开实施例提供的一种半导体结构的立体结构示意图；
图3为本公开实施例提供的一种半导体结构的组成结构示意图；
图4为本公开实施例提供的一种错排单元的示意图一；
图5为本公开实施例提供的一种错排单元的示意图二；
图6为本公开实施例提供的一种位线结构的对比示意图；
图7为本公开实施例提供的一种半导体结构的制备方法的流程示意图；
图8为本公开实施例提供的一种半导体结构的制备过程示意图一；
图9为本公开实施例提供的一种半导体结构的制备过程示意图二；
图10为本公开实施例提供的一种半导体结构的制备过程示意图三；
图11为本公开实施例提供的一种半导体结构的制备过程示意图四；
图12为本公开实施例提供的一种半导体结构的制备过程示意图五；
图13为本公开实施例提供的一种半导体结构的制备过程示意图六；
图14为本公开实施例提供的一种半导体结构的制备过程示意图七；
图15为本公开实施例提供的一种半导体结构的制备过程示意图八；
图16为本公开实施例提供的一种半导体存储器的组成结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅用于解释相关公开，而非对该公开的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关公开相关的部分。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
需要指出，本公开实施例所涉及的术语“第一\第二\第三”仅仅是区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
随着DRAM器件尺寸不断缩小，其各部分结构之间的距离越来越小，给半导体存储器的生产带来了挑战。参见图1，其示出了一种半导体结构的立体结 构示意图。如图1所示，该半导体结构包括衬底(图中未示出)、字线结构101、电容区102、位线结构103，字线结构101及其下方的有源区共同形成晶体管。在这种情况下，位线结构103的赝电容较大，降低了器件的感应裕度。
基于此，本公开实施例提供了一种半导体结构，包括：衬底；形成于衬底上方的堆叠结构；其中，堆叠结构包括多个器件结构和多个字线结构，器件结构沿第一方向延伸，字线结构沿第二方向延伸；器件结构依次包括电容区和有源区；形成于堆叠结构中的多个位线结构，且位线结构沿第三方向延伸；其中，位线结构依次穿过不同堆叠层中沿第三方向排布的有源区，其中，任意相邻的两个位线结构沿第二方向至少部分错开排列，第一方向和第二方向位于平行于衬底的表面所在的平面，第三方向垂直于衬底的表面。这样，在半导体结构中形成了沿第二方向至少部分错开排列的位线结构，可以减小位线电容，从而提高器件的感应裕度。
下面将结合附图对本公开各实施例进行详细说明。
本公开的一实施例中，参见图2，其示出了本公开实施例提供的一种半导体结构的立体结构示意图。如图2所示，该半导体结构200可以包括：
衬底(图2未示出)；
形成于衬底上方的堆叠结构；其中，堆叠结构包括多个器件结构21和多个字线结构22，器件结构21沿第一方向延伸，字线结构22沿第二方向延伸；器件结构21依次包括有源区211和电容区212；
形成于堆叠结构中的多个位线结构23，且位线结构23沿第三方向延伸；其中，位线结构23依次穿过不同堆叠层中沿第三方向排布的有源区211，其中，任意相邻的两个位线结构23沿第二方向至少部分错开排列，第一方向和第二方向位于平行于衬底的表面所在的平面，第三方向垂直于衬底的表面。
需要说明的是，该半导体结构200可以应用于动态随机存取存储器(Dynamic Random Access Memory，DRAM)中，例如三维DRAM(Three Dimensional DRAM，3D DRAM)，在3D DRAM中形成有多个空间堆叠的半导体结构200。目前，为了提高器件的感应裕度，可以通过增大电容器电容或者通过减小位线电容的方式来提高器件的感应裕度，本公开实施例期望通过将位线结构23进行错排的方式来减小位线电容，从而改善器件的感应裕度。
需要说明的是，衬底可以为硅衬底或者其它半导体元素，例如：锗(Ge)，或包括半导体化合物，例如：碳化硅(SiC)、砷化镓(GaAs)、磷化镓(GaP)、磷化铟(InP)、砷化铟(InAs)或锑化铟(InSb)，或包括其它半导体合金，例如：硅锗(SiGe)、磷化砷镓(GaAsP)、砷化铟铝(AlInAs)、砷化镓铝(AlGaAs)、砷化铟镓(GaInAs)、磷化铟镓(GaInP)、和/或磷砷化铟镓(GaInAsP)或其组合，本公开实施例对此不作具体限定。
需要说明的是，如图2所示，堆叠结构可以包括器件结构21、字线结构22和位线结构23，器件结构21还可以包括有源区211和电容区212；其中，第一方向是指沿器件结构21延伸的方向，第二方向是指沿字线结构22延伸的方向，第三方向是指沿位线结构23延伸的方向。
有源区211的材料可以为硅(Si)，其中又可划分为多个掺杂区域，不同掺 杂区域的掺杂类型不同，例如N型掺杂(提供自由电子)和P型掺杂(提供空穴)；其中，N型掺杂可以掺杂磷、锑、砷等五价杂质元素；P型掺杂可以掺杂硼、镓、铟等三价杂质元素。
参见图3，其示出了本公开实施例提供的一种半导体结构的组成结构示意图。如图2和图3所示，每一字线结构22均穿过同一堆叠层的多个有源区211，位于字线结构22下方的有源区211与位于字线结构22两侧的有源区211的掺杂类型不同，从而构成一个晶体管，同时字线结构22引出晶体管的栅极；位线结构23穿过不同堆叠层的多个有源区211，从而引出晶体管的漏极/源极。特别地，在图2中，相邻的两个晶体管复用一个位线结构23。在本公开实施例中，位线结构23是交错排列的，可以减小位线电容，提高器件的感应裕度。
在一种具体的示例中，每n个位线结构23可以组成一个错排单元。在第一方向上，对于错排单元的第1个～第a个位线结构23，每一位线结构23至第一侧的字线结构22的距离逐步增大；对于错排单元的第a个～第n个位线结构23，每一位线结构23至第一侧的字线结构22的距离逐步减小；其中，第一侧为逆着第一方向的延伸方向或顺着第一方向的延伸方向；a和n均为大于1的整数，且a小于n。
需要说明的是，以n＝5，a＝3为例，参见图4，其示出了本公开实施例提供的一种错排单元的示意图一。应理解，图4为图2中一个错排单元的俯视图。如图4所示，对于第1个～第3个位线结构23，每一位线结构23至字线结构22的距离逐步增大；对于第3～第5个位线结构23，每一位线结构23至字线结构22的距离逐步减小。除此之外，错排单元也可以包括7个位线结构23；相应的，对于第1个～第4个位线结构23，每一位线结构23至字线结构22的距离逐步增大；对于第4～第7个位线结构23，每一位线结构23至字线结构22的距离逐步减小；或者，错排单元也可以包括8个位线结构23；相应的，对于第1个～第4个位线结构23，每一位线结构23至字线结构22的距离逐步增大；对于第4～第8个位线结构23，每一位线结构23至字线结构22的距离逐步减小。
在另一种具体的示例中，在第一方向上，对于错排单元，每一位线结构23至第一侧的字线结构22的距离逐步增大；其中，第一侧为逆着第一方向的延伸方向或顺着第一方向的延伸方向；n为大于1的整数。
需要说明的是，以n＝5为例，参见图5，其示出了本公开实施例提供的一种错排单元的示意图二。如图5所示，每一位线结构23至字线结构22的距离逐步增大，即形成类似阶梯状排列方式。
除了图4或者图5类似的结构外，位线结构23的错排方式还具有更多可能，而且对于同一个半导体结构，不同的错排单元的错排形式可以不同，本公开实施例不做具体限定。
在一些实施例中，在第二方向上，相邻的两个位线结构23部分交错排列；其中，相邻的两个位线结构23的相对面积小于位线结构23的投影面积的三分之一。
需要说明的是，相邻的两个位线结构23可以部分交错，同时相对面积保持在较低水平，不仅减小电容，而且降低位线结构23占用的面积。
在另一些实施例中，在第二方向上，相邻的两个位线结构23完全交错排列；其中，相邻的两个位线结构23的相对面积为零。
需要说明的是，相邻的两个位线结构23可以完全交错，能够达到最好的电容减小效果。
在一些实施例中，位线结构23还包括阻挡层外壁和填充于阻挡层外壁的金属材料；其中，阻挡层材料包括氮化钛(TiN)，金属材料包括钨(W)。
需要说明的是，金属材料还可以包括钴(Co)、铜(Cu)、铝(Al)等，形成位线结构23的材料可以为氮化钛和钨的组合，也可以为其他材料的组合，本公开实施例对此不作具体限定。
从以上可以看出，对于半导体结构200来说，位线结构23进行交错排列。参见图6，其示出了本公开实施例提供的一种位线结构的对比示意图。具体来说，图6中的(a)示出了不进行交错排列的位线结构，图6中的(b)示出了进行交错排列的位线结构23。经过错排后的图6中的(b)中的位线结构23的电容值为图6中的(a)中的位线结构的电容值的58.4％，位线电容变小，进而能够提高半导体结构200的感应裕度。
本公开实施例提供了一种半导体结构，包括：衬底；形成于衬底上方的堆叠结构；其中，堆叠结构包括多个器件结构和多个字线结构，器件结构沿第一方向延伸，字线结构沿第二方向延伸；器件结构依次包括电容区和有源区；形成于堆叠结构中的多个位线结构，且位线结构沿第三方向延伸；其中，位线结构依次穿过不同堆叠层中沿第三方向排布的有源区，其中，任意相邻的两个位线结构沿第二方向至少部分错开排列，第一方向和第二方向位于平行于衬底的表面所在的平面，第三方向垂直于衬底的表面。这样，在半导体结构中形成了沿第二方向至少部分错开排列的位线结构，可以减小位线电容，提高器件的感应裕度。
本公开的另一实施例中，参见图7，其示出了本公开实施例提供的一种半导体结构的制备方法的流程示意图。如图7所示，该方法可以包括：
S301、提供衬底。
需要说明的是，本公开实施例提供的制备方法应用于制备前述的半导体结构200，该半导体结构200可以应用于DRAM中，例如3D DRAM中。
在制备该半导体结构200时，首先提供一衬底，衬底可以是硅衬底，衬底也可以包括其它半导体元素，例如：锗(Ge)，或包括半导体化合物，例如：碳化硅(SiC)、砷化镓(GaAs)、磷化镓(GaP)、磷化铟(InP)、砷化铟(InAs)或锑化铟(InSb)，或包括其它半导体合金，例如：硅锗(SiGe)、磷化砷镓(GaAsP)、砷化铟铝(AlInAs)、砷化镓铝(AlGaAs)、砷化铟镓(GaInAs)、磷化铟镓(GaInP)、和/或磷砷化铟镓(GaInAsP)或其组合，本公开实施例对此不作具体限定。
S302、于衬底上方形成初始堆叠结构，且初始堆叠结构包括多个堆叠层。
需要说明的是，参见图8，其示出了本公开实施例提供的一种半导体结构的制备过程示意图一。在图8、以及后续的图9～图15中，(a)均是沿图3中 a-a’的剖面图，(b)均是沿图3中b-b’的剖面图。应理解，图3中的镂空部分也是存在材料填充的。
如图8所示，在提供衬底401之后，首先可以对衬底401进行预清洁，然后在衬底401上方形成初始堆叠结构40，初始堆叠结构40包括至少一个堆叠层。
在一些实施例中，所述于衬底上方形成初始堆叠结构，包括：
于衬底上方依次形成绝缘层和硅层，得到一个堆叠层；
重复执行于衬底上方依次形成绝缘层和硅层的步骤，形成初始堆叠结构；
于硅层中形成沿第二方向排列的多个硅化物区域，且位线结构依次穿过不同堆叠层中硅化物区域。
需要说明的是，如图8所示，每一堆叠层均包括一绝缘层402和一硅层403，且硅层403形成在绝缘层402的上方。具体来说，在衬底401的上方重复形成一层绝缘层402和一层硅层403的步骤，直至得到所需层数的堆叠层。在实际应用中，堆叠层的层数可以为任意所需的数量，本公开实施例对此不作具体限定。
需要说明的是，绝缘层402的材料可以为氧化硅，硅层403的材料可以为多晶硅。绝缘层402和硅层403可以通过以下任一沉积工艺形成：外延工艺、化学气相沉积(Chemical Vapor Deposition，CVD)工艺、物理气相沉积(Physical Vapor Deposition，PVD)工艺、原子层沉积(Atomic Layer Deposition，ALD)工艺、旋涂工艺、涂敷工艺或薄膜工艺等；例如可以通过外延工艺在半导体衬底401上依次形成绝缘层402和硅层403。
S303、于初始堆叠结构中形成多个器件结构、多个字线结构和多个位线结构；其中，器件结构沿第一方向延伸，字线结构沿第二方向延伸，位线结构沿第三方向延伸；器件结构依次包括电容区和有源区；位线结构依次穿过不同堆叠层中沿第三方向排布的有源区，其中，任意相邻的两个位线结构沿第二方向至少部分错开排列，第一方向和第二方向位于平行于衬底的表面所在的平面，第三方向垂直于衬底的表面。
需要说明的是，在初始堆叠结构中形成多个器件结构、多个字线结构和多个位线结构的顺序可以具有多种可能，需要根据实际选用工艺确定。
需要说明的是，请参考图2、图3和图8，硅层403后续用于形成器件结构21中的有源区211。每一字线结构22均穿过同一堆叠层的多个有源区211，位于字线结构22下方的有源区211与位于字线结构22两侧的有源区211的掺杂类型不同，从而构成一个晶体管，同时字线结构22引出晶体管的栅极；位线结构23穿过不同堆叠层的多个有源区211，从而引出晶体管的漏极/源极。特别地，在图2中，相邻的两个晶体管共享一个位线结构23。
在一些实施例中，在形成初始堆叠结构40之后，需要在每一硅层403中形成沿第二方向排列的多个硅化物区域404，硅化物区域404后续用于形成位线结构23。
以下示例性的提供一种硅化物区域404的形成方法。
首先，在图8的基础上，参见图9，其示出了本公开实施例提供的一种半 导体结构的制备过程示意图二。如图9所示，在形成初始堆叠结构40之后，可以对初始堆叠结构40进行图案化处理等工艺，在初始堆叠结构40中形成第一沟槽406。其中，对初始堆叠结构40进行图案化处理的方式可以为：首先在初始堆叠结构40的上方形成第一掩模层，然后在第一掩模层的上方形成第一光刻胶层，第一光刻胶层具有形成第一沟槽406所需的第一图案，将第一图案转移至第一掩膜层，并去除第一光刻胶层，然后以第一掩膜层为掩模继续将第一图案转移至初始堆叠结构40中，并去除第一掩膜层，形成第一沟槽406。去除第一光刻胶层和第一掩膜层的方式可以为刻蚀，将第一图案转移至初始堆叠结构40方式也可以为刻蚀。
其次，在图9的基础上，参见图10，其示出了本公开实施例提供的一种半导体结构的制备过程示意图三。如图10所示，在形成第一沟槽406后，需要在第一沟槽406中填充绝缘材料，其中，填充的绝缘材料与绝缘层402的材料相同，可以为氧化硅。填充第一沟槽406的方式可以为多种沉积工艺。
然后，在图10的基础上，参见图11，其示出了本公开实施例提供的一种半导体结构的制备过程示意图四。如图11所示，在填充第一沟槽406后，需要继续形成第二沟槽407，形成第二沟槽407的方式可以为刻蚀，可以选择合适的刻蚀选择比，只将部分硅层403刻蚀去除，绝缘层402不会被刻蚀去除。
最后，在图11的基础上，参见图12，其示出了本公开实施例提供的一种半导体结构的制备过程示意图五。如图12所示，在形成第二沟槽407后，需要在第二沟槽407中填充导电材料，例如金属、多晶硅等，形成硅化物区域404，其中，填充第二沟槽407的方式可以为沉积。
需要说明的是，硅化物区域404也可以是将需要形成位线结构23处的硅层403进行金属硅化处理后形成，然后对沿第二方向排列的硅化物区域404进行打孔后续形成位线结构23。这样，通过上述方法形成了多个硅化物区域404，可以降低位线结构23与晶体管之间的接触电阻。
还需要说明的是，本申请也可以不形成硅化物区域404，通过直接在硅层403处打孔，然后形成位线结构23。另外，本领域技术人员也可以使用本领域任何可行的方式实施，对此不作具体限定。
在一些实施例中，在所述于每一硅层中形成沿第二方向排列的多个硅化物区域之后，该方法还包括：
于初始堆叠结构的上方形成掩膜层，并在掩膜层上形成预设图案；其中，预设图案沿第二方向至少部分错开排列；
利用掩膜层将预设图案转移至初始堆叠结构中，并去除掩膜层，形成多个沟槽；其中，沟槽依次穿过绝缘层和硅化物区域；
对沟槽进行填充处理，形成多个位线结构。
需要说明的是，在图12的基础上，参见图13，其示出了本公开实施例提供的一种半导体结构的制备过程示意图六。如图13所示，在于每一硅层403中形成沿第二方向排列的多个硅化物区域404之后，首先在初始堆叠结构40的表面形成掩膜层408，并在掩膜层408上形成沿第二方向至少部分错开排列的预设图案；其中，掩膜层408的材料可以是氧化硅、氮化硅、碳化硅、氮氧 化硅中的一种或几种；掩膜层408可以通过任意一种合适的沉积工艺形成。
在图13的基础上，参见图14，其示出了本公开实施例提供的一种半导体结构的制备过程示意图七。如图14所示，在掩膜层408上形成预设图案之后，以掩膜层408为掩膜，将预设图案转移至初始堆叠结构40中，并将掩膜层408去除，得到如图14所示的多个沟槽409。在这里，去除掩膜层408的方式可以为刻蚀，将预设图案转移至初始堆叠结构40的方式也可以为刻蚀，具体为干法刻蚀工艺或者湿法刻蚀工艺。干法刻蚀采用的气体可以为三氟甲烷(CHF3)、四氟化碳(CF4)、二氟甲烷(CH2F2)、氢溴酸(HBr)、氯气(Cl2)或六氟化硫(SF6)中的一种或任意组合。湿法刻蚀可以采用浓硫酸、氢氟酸、浓硝酸等强酸进行刻蚀。
还需要说明的是，在图14中，初始堆叠结构40中位于预设图案正下方的部分被全部刻蚀，形成具有高纵深比(High Aspect Ratio，HAR)的多个沟槽409，且每一沟槽409依次穿过绝缘层402和硅化物区域404。
在图14的基础上，参见图15，其示出了本公开实施例提供的一种半导体结构的制备过程示意图八。如图15所示，在形成沟槽409后，需要对沟槽409中进行填充处理，形成位线结构23。在形成位线结构23之后，还可以进行化学机械研磨(Chemical Mechanical Polish，CMP)处理，使得半导体结构200的顶面平整。
在一些实施例中，所述对沟槽进行填充处理，形成多个位线结构，可以包括：
在沟槽中形成阻挡层外壁；
于阻挡层外壁包围的中空区域内填充金属材料，形成多个位线结构。
需要说明的是，如图15所示，阻挡层外壁4051的材料可以包括氮化钛，金属材料4052可以包括钨；金属材料4052还可以包括钴(Co)、铜(Cu)、铝(Al)等，形成位线结构23的材料可以为氮化钛和钨的组合，也可以为其他材料的组合，本公开实施例对此不作具体限定。
特别地，为了形成错排的位线结构，用于形成沟槽409(后续形成位线结构23)的预设图案是错开排列的，具体说明如下。
在一些实施例中，预设图案沿第二方向至少部分错开排列，预设图案包括至少一个错排单元，且每一错排单元包括n个位线图案，位线图案与形成的多个位线结构相互对应。
在一些实施例中，预设图案包括至少一个错排单元，且每一错排单元包括n个位线图案；在第一方向上，对于错排单元的第1个～第a个位线图案，每一位线图案至第一侧的字线结构的距离逐步增大；对于错排单元的第a个～第n个位线图案，每一位线图案至第一侧的字线结构的距离逐步减小；其中，第一侧为逆着第一方向的延伸方向或顺着第一方向的延伸方向；a和n均为大于1的整数，且a小于n。
在一些实施例中，位线图案还可以形成类似阶梯状排列的图案，在一些实施例中，预设图案包括至少一个错排单元，且每一错排单元包括n个位线图案；在第一方向上，对于错排单元，每一位线图案至第一侧的字线结构的距离逐步 增大；其中，第一侧为逆着第一方向的延伸方向或顺着第一方向的延伸方向；n为大于1的整数。
在一些实施例中，在第二方向上，相邻的两个位线图案部分交错排列；其中，相邻的两个位线图案的相对面积小于位线图案的投影面积的三分之一。
在一些实施例中，在第二方向上，相邻的两个位线图案完全交错排列；其中，相邻的两个位线图案的相对面积为零。
本公开实施例提供了一种半导体结构的制备方法，利用该方法制得的半导体结构中，首先在衬底上方形成初始堆叠结构，且初始堆叠结构包括多个堆叠层；然后在初始堆叠结构中形成多个器件结构、多个字线结构和多个位线结构；其中，器件结构沿第一方向延伸，字线结构沿第二方向延伸，位线结构沿第三方向延伸；器件结构依次包括电容区和有源区；位线结构依次穿过不同堆叠层中沿第三方向排布的有源区，其中，任意相邻的两个位线结构沿第二方向至少部分错开排列，第一方向和第二方向位于平行于衬底的表面所在的平面，第三方向垂直于衬底的表面。这样，在半导体结构中形成了沿第二方向至少部分错开排列的位线结构，可以减小位线电容，从而提高器件的感应裕度。
本公开的再一实施例中，参见图16，其示出了本公开实施例提供的一种半导体存储器400的组成结构示意图。如图16所示，该半导体存储器400包括前述实施例任一项所述的半导体结构200。
在一些实施例中，该半导体存储器400可以为3D DRAM。
对于该半导体存储器400而言，由于其包括前述实施例所述的半导体结构200，该半导体结构包括：衬底；形成于衬底上方的堆叠结构；其中，堆叠结构包括多个器件结构和多个字线结构，器件结构沿第一方向延伸，字线结构沿第二方向延伸；器件结构依次包括电容区和有源区；形成于堆叠结构中的多个位线结构，且位线结构沿第三方向延伸；其中，位线结构依次穿过不同堆叠层中沿第三方向排布的有源区，其中，任意相邻的两个位线结构沿第二方向至少部分错开排列，第一方向和第二方向位于平行于衬底的表面所在的平面，第三方向垂直于衬底的表面。这样，在半导体结构中形成了沿第二方向至少部分错开排列的位线结构，可以减小位线电容，提高器件的感应裕度。
对于本公开实施例未披露的细节，可以参照前述实施例的描述而理解。
以上所述，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围。
需要说明的是，在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。
本公开所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。
本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
本公开实施例提供了一种半导体结构及其制备方法、半导体存储器，该半导体结构包括：衬底；形成于衬底上方的堆叠结构；其中，堆叠结构包括多个器件结构和多个字线结构，器件结构沿第一方向延伸，字线结构沿第二方向延伸；器件结构依次包括电容区和有源区；形成于堆叠结构中的多个位线结构，且位线结构沿第三方向延伸；其中，位线结构依次穿过不同堆叠层中沿第三方向排布的有源区，其中，任意相邻的两个位线结构沿第二方向至少部分错开排列，第一方向和第二方向位于平行于衬底的表面所在的平面，第三方向垂直于衬底的表面。这样，在半导体结构中形成了沿第二方向至少部分错开排列的位线结构，可以减小位线电容，提高器件的感应裕度。

Claims (15)

  1. 一种半导体结构(200)，包括：
    衬底；
    形成于所述衬底上方的堆叠结构；其中，所述堆叠结构包括多个器件结构(21)和多个字线结构(22)，所述器件结构(21)沿第一方向延伸，所述字线结构(22)沿第二方向延伸；所述器件结构(21)依次包括电容区(212)和有源区(211)；
    形成于所述堆叠结构中的多个位线结构(23)，且所述位线结构(23)沿第三方向延伸；其中，所述位线结构(23)依次穿过不同堆叠层中沿第三方向排布的所述有源区(211)，其中，任意相邻的两个所述位线结构(23)沿第二方向至少部分错开排列，所述第一方向和所述第二方向位于平行于所述衬底的表面所在的平面，所述第三方向垂直于所述衬底的表面。
  2. 根据权利要求1所述的半导体结构(200)，其中，每n个所述位线结构(23)组成一个错排单元；
    在第一方向上，对于所述错排单元的第1个～第a个所述位线结构(23)，每一位线结构(23)至第一侧的字线结构(22)的距离逐步增大；对于所述错排单元的第a个～第n个位线结构(23)，每一位线结构(23)至第一侧的字线结构(22)的距离逐步减小；
    其中，所述第一侧为逆着所述第一方向的延伸方向或顺着所述第一方向的延伸方向；a和n均为大于1的整数，且a小于n。
  3. 根据权利要求1或2所述的半导体结构(200)，其中，每n个所述位线结构(23)组成一个错排单元；
    在第一方向上，对于所述错排单元，每一位线结构(23)至第一侧的字线结构(22)的距离逐步增大；其中，所述第一侧为逆着所述第一方向的延伸方向或顺着所述第一方向的延伸方向；n为大于1的整数。
  4. 根据权利要求2或3所述的半导体结构(200)，其中，
    在所述第二方向上，相邻的两个位线结构(23)部分交错排列；
    其中，相邻的两个位线结构(23)的相对面积小于所述位线结构(23)的投影面积的三分之一。
  5. 根据权利要求1至4中任一项所述的半导体结构(200)，其中，
    在所述第二方向上，相邻的两个位线结构(23)完全交错排列；
    其中，相邻的两个位线结构(23)的相对面积为零。
  6. 根据权利要求1至5中任一项所述的半导体结构(200)，其中，所述位线结构(23)包括阻挡层外壁(4051)和填充于所述阻挡层外壁(4051)的金属材料(4052)；其中，所述阻挡层材料包括氮化钛，所述金属材料(4052)包括钨。
  7. 一种半导体结构(200)的制备方法，其中，所述方法包括：
    提供衬底(401)；
    于所述衬底(401)上方形成初始堆叠结构(40)，且所述初始堆叠结构(40)包括多个堆叠层；
    于所述初始堆叠结构(40)中形成多个器件结构(21)、多个字线结构(22)和多个位线结构(23)；
    其中，所述器件结构(21)沿第一方向延伸，所述字线结构(22)沿第二方向延伸，所述位线结构(23)沿第三方向延伸；所述器件结构(21)依次包括电容区(212)和有源区(211)；所述位线结构(23)依次穿过不同堆叠层中沿第三方向排布的所述有源区(211)，其中，任意相邻的两个所述位线结构(23)沿第二方向至少部分错开排列，所述第一方向和所述第二方向位于平行于所述衬底(401)的表面所在的平面，所述第三方向垂直于所述衬底(401)的表面。
  8. 根据权利要求7所述的方法，其中，所述于所述衬底(401)上方形成初始堆叠结构(40)，包括：
    于所述衬底(401)上方依次形成绝缘层(402)和硅层(403)，得到一个所述堆叠层；
    重复执行所述于所述衬底上方依次形成绝缘层(402)和硅层(403)的步骤，形成所述初始堆叠结构(40)；
    于所述硅层(403)中形成沿第二方向排列的多个硅化物区域(404)，且位线结构(23)依次穿过不同堆叠层中硅化物区域(404)。
  9. 根据权利要求8所述的方法，其中，在所述于所述硅层(403)中形成沿第二方向排列的多个硅化物区域(404)之后，所述方法还包括：
    于所述初始堆叠结构(40)的上方形成掩膜层(408)，并在所述掩膜层(408)上形成预设图案；其中，所述预设图案沿第二方向至少部分错开排列；
    利用所述掩膜层(408)将所述预设图案转移至所述初始堆叠结构(40)中，并去除所述掩膜层(408)，形成多个沟槽(409)；其中，所述沟槽(409)依次穿过所述绝缘层(402)和所述硅化物区域(404)；
    对所述沟槽(409)进行填充处理，形成多个所述位线结构(23)。
  10. 根据权利要求9所述的方法，其中，所述预设图案包括至少一个错排单元，且每一所述错排单元包括n个位线图案；
    在第一方向上，对于所述错排单元的第1个～第a个所述位线图案，每一位线图案至第一侧的字线结构(22)的距离逐步增大；对于所述错排单元的第a个～第n个位线图案，每一位线图案至第一侧的字线结构(22)的距离逐步减小；
    其中，所述第一侧为逆着所述第一方向的延伸方向或顺着所述第一方向的延伸方向；a和n均为大于1的整数，且a小于n。
  11. 根据权利要求9或10所述的方法，其中，所述预设图案包括至少一个错排单元，且每一所述错排单元包括n个位线图案；
    在第一方向上，对于所述错排单元，每一位线图案至第一侧的字线结构(22)的距离逐步增大；其中，所述第一侧为逆着所述第一方向的延伸方向或顺着所述第一方向的延伸方向；n为大于1的整数。
  12. 根据权利要求10或11所述的方法，其中，
    在所述第二方向上，相邻的两个所述位线图案部分交错排列；
    其中，相邻的两个所述位线图案的相对面积小于所述位线图案的投影面积的三分之一。
  13. 根据权利要求7至12中任一项所述的方法，其中，
    在所述第二方向上，相邻的两个位线图案完全交错排列；
    其中，相邻的两个位线图案的相对面积为零。
  14. 根据权利要求9至12中任一项所述的方法，其中，所述对所述沟槽(409)进行填充处理，形成多个所述位线结构(23)，包括：
    在所述沟槽(409)中形成阻挡层外壁(4051)；
    于所述阻挡层外壁(4051)包围的中空区域内填充金属材料(4052)，形成多个所述位线结构(23)。
  15. 一种半导体存储器(400)，其中，包括如权利要求1至6任一项所述的半导体结构(200)。
PCT/CN2023/098559 2022-08-23 2023-06-06 一种半导体结构及其制备方法、半导体存储器 WO2024041089A1 (zh)

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