WO2024040643A1 - 磁性存储结构、磁性存储阵列结构及其控制方法及存储器 - Google Patents

磁性存储结构、磁性存储阵列结构及其控制方法及存储器 Download PDF

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WO2024040643A1
WO2024040643A1 PCT/CN2022/118569 CN2022118569W WO2024040643A1 WO 2024040643 A1 WO2024040643 A1 WO 2024040643A1 CN 2022118569 W CN2022118569 W CN 2022118569W WO 2024040643 A1 WO2024040643 A1 WO 2024040643A1
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transistor
magnetic
tunnel junction
magnetic tunnel
magnetic storage
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PCT/CN2022/118569
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English (en)
French (fr)
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刘晓阳
王晓光
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长鑫存储技术有限公司
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Priority to US18/153,350 priority Critical patent/US20240065111A1/en
Publication of WO2024040643A1 publication Critical patent/WO2024040643A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductors, and in particular to a magnetic storage structure, a magnetic storage array structure, a control method thereof, and a memory.
  • Magnetic Random Access Memory Magnetic Random Access Memory
  • MRAM Magnetic Random Access Memory
  • MTJ Magnetic Tunnel Junction
  • MRAM relies on magnetic field polarization rather than charges to store data.
  • MTJ is composed of a free layer, a tunneling layer, and a fixed layer.
  • the direction of the magnetic field of the free layer can be changed, while the direction of the magnetic field of the fixed layer remains unchanged.
  • the MTJ presents a low resistance state; when the magnetic field directions of the free layer and the fixed layer are opposite, the MTJ presents a high resistance state.
  • By detecting the resistance of the MTJ it can be determined whether the stored data is "0" or "1" .
  • STT-MRAM Spin-Transfer Torque Magnetic Random Access Memory
  • SOT-MRAM Spin-Transfer Torque Magnetic Random Access Memory
  • SOT-MRAM Spin-Orbit Torque Magnetic Random Access Memory
  • Embodiments of the present disclosure provide a magnetic storage structure, a magnetic storage array structure, a control method thereof, and a memory, which are at least conducive to improving the layout density of magnetic tunnel junctions and transistors in the magnetic storage structure, so as to improve the performance of the magnetic storage structure in unit space.
  • the amount of data stored is not limited to, but not limited to, but not limited to, but not limited to, but not limited to, but not limited to, but not limited to improve the layout density of magnetic tunnel junctions and transistors in the magnetic storage structure, so as to improve the performance of the magnetic storage structure in unit space. The amount of data stored.
  • embodiments of the present disclosure provide a magnetic storage structure, including: two magnetic tunnel junctions, the magnetic tunnel junctions including a fixed layer and a free layer; one-to-one correspondence with the magnetic tunnel junctions.
  • a spin orbit coupling layer, the spin orbit coupling layer is located on the side of the free layer away from the fixed layer, a first transistor and a second transistor, a connection between the spin orbit coupling layer and the first transistor.
  • the source end or drain end is electrically connected, and the other spin orbit coupling layer is electrically connected to the source end or drain end of the second transistor; the third transistor, the source end or drain end of the third transistor is electrically connected to two The fixed layers in the magnetic tunnel junction are all electrically connected.
  • the first transistor, the second transistor and the third transistor are all vertical all-around gate transistor structures.
  • the first transistor and the third transistor are arranged along a first direction
  • the first transistor and the second transistor are arranged along a second direction
  • the first direction and the The second direction is vertical.
  • the magnetic tunnel junction electrically connected to the first transistor and the first transistor are spaced apart along the first direction, and the magnetic tunnel junction electrically connected to the second transistor is electrically connected to the first transistor.
  • the second transistors are arranged at intervals along the first direction.
  • the magnetic tunnel junction is located between the first transistor and the third transistor.
  • the material of the spin-orbit coupling layer is at least one of platinum, tantalum, tungsten, iridium, gold, and titanium.
  • the material of the free layer and the material of the fixed layer each include at least one of cobalt iron boron, cobalt or nickel iron.
  • the embodiments of the present disclosure further provide a magnetic storage array structure, including a plurality of magnetic storage structures as described in any one of the foregoing, characterized in that at least two of the magnetic storage structures Arranged at intervals along the first direction; at least two of the magnetic storage structures are arranged at intervals along the second direction, wherein the two adjacent magnetic storage structures along the second direction are centrally symmetrical, and the two magnetic storage structures are arranged at intervals along the second direction.
  • the third transistor of one of the magnetic storage structures and the first transistor of the other are arranged at intervals along the second direction, or two adjacent magnetic storage structures are arranged along the first direction.
  • the structure is centrally symmetrical, and the third transistor of one of the two magnetic storage structures and the third transistor of the other are arranged at intervals along the second direction;
  • the magnetic storage array structure also includes : a first signal line and a second signal line extending along the first direction, the magnetic storage structure arranged along the first direction is electrically connected to the same first signal line, and is electrically connected to the same first signal line.
  • Two signal lines are electrically connected; a first control line and a second control line extending along the second direction, the magnetic storage structure arranged along the second direction are electrically connected to the same first control line, and electrically connected to the same second control line.
  • the magnetic tunnel junction electrically connected to the first transistor is a first magnetic tunnel junction
  • the magnetic tunnel junction electrically connected to the second transistor is a second magnetic tunnel junction
  • along the The first magnetic tunnel junction in the magnetic storage structure arranged in the first direction is electrically connected to the same first signal line
  • the first magnetic tunnel junction in the magnetic storage structure arranged in the first direction The second magnetic tunnel junction is electrically connected to the same second signal line.
  • the two adjacent magnetic storage structures along the second direction are a first magnetic storage structure and a second magnetic storage structure respectively; the same first control line is electrically connected to the first The first transistor and the second transistor in the magnetic storage structure and the third transistor in the second magnetic storage structure; the same second control line is electrically connected to the second transistor in the second magnetic storage structure. the first transistor and the second transistor and the third transistor in the first magnetic storage structure.
  • the same first control line is electrically connected to the first transistor and the second transistor in the magnetic memory structure arranged along the second direction; along the first direction
  • the two adjacent magnetic storage structures are a first magnetic storage structure and a second magnetic storage structure respectively; the same second control line is electrically connected to the third transistor in the first magnetic storage structure and the The third transistor in the second magnetic storage structure.
  • the magnetic memory array structure further includes: a first electrical connection layer contact-connected with the fixed layer of a plurality of the magnetic tunnel junctions arranged along the second direction; a second electrical connection layer.
  • a connection layer, one end of the second electrical connection layer is in contact with the first electrical connection layer, and the other end is in contact with the source end or the drain end of the third transistor.
  • the direction of the magnetization structure of the magnetic tunnel junction is perpendicular to the surface of the spin-orbit coupling layer, and the free layer is located on the surface of the spin-orbit coupling layer.
  • the direction of the magnetization structure of the magnetic tunnel junction is parallel to the surface of the spin-orbit coupling layer, and the free layer is located on the surface of the spin-orbit coupling layer.
  • another aspect of the embodiments of the present disclosure further provides a memory, the array structure of the memory is based on the magnetic storage array structure described in any one of the preceding items.
  • the embodiments of the present disclosure also provide a read and write control method for a magnetic storage array structure, including: controlling one of the first transistor and the second transistor to be in a conductive state; controlling the flow through The current of the spin-orbit coupling layer sets one of the two magnetic tunnel junctions to a high-resistance state or a low-resistance state to implement a write operation on the magnetic tunnel junction, wherein the write operation is implemented
  • the magnetic tunnel junction corresponds to the first transistor in a conductive state or the second transistor in a conductive state; controlling the third transistor to be in a conductive state; reading the flow through the two magnetic tunnel junctions
  • the magnitude of one of the currents is used to determine whether the magnetic tunnel junction is in a high-resistance state or a low-resistance state, so as to implement a read operation on the magnetic tunnel junction.
  • the magnetic tunnel junction electrically connected to the first transistor is a first magnetic tunnel junction
  • the spin orbit coupling layer corresponding to the first magnetic tunnel junction is a first spin orbit coupling layer
  • the magnetic tunnel junction electrically connected to the second transistor is a second magnetic tunnel junction
  • the spin orbit coupling layer corresponding to the second magnetic tunnel junction is a second spin orbit coupling layer; realizing the reading
  • the steps of the operation and the write operation include: controlling the current flowing through the first spin-orbit coupling layer through a first signal line to set the state of the first magnetic tunnel junction to a high resistance state or a low resistance state; by The second signal line controls the current flowing through the second spin-orbit coupling layer to set the state of the second magnetic tunnel junction to a high resistance state or a low resistance state; the first control line and the second control line are used to control the state of the second magnetic tunnel junction.
  • the first transistor, the second transistor and the third transistor are turned on or off.
  • the step of controlling part of the magnetic storage structure to perform the write operation includes: strobing the first signal line and the first control line to turn on the first transistor, and controlling flow
  • the current passing through the first spin-orbit coupling layer sets the state of the first magnetic tunnel junction to a high resistance state or a low resistance state to implement the write operation on the first magnetic tunnel junction; or, Gating the second signal line and the first control line to turn on the second transistor, and controlling the current flowing through the second spin orbit coupling layer to set the second magnetic tunnel junction
  • the state is a high resistance state or a low resistance state to implement the writing operation on the second magnetic tunnel junction.
  • the step of controlling part of the magnetic storage structure to perform the read operation includes: strobing the first signal line and the second control line to turn on the third transistor, and reading The magnitude of the current flowing through the first magnetic tunnel junction is used to determine whether the first magnetic tunnel junction is in a high-resistance state or a low-resistance state, so as to implement the read operation on the first magnetic tunnel junction; or, optionally, Pass the second signal line and the second control line to turn on the third transistor, and read the magnitude of the current flowing through the second magnetic tunnel junction to determine whether the second magnetic tunnel junction is A high-resistance state or a low-resistance state to achieve the read operation of the second magnetic tunnel junction.
  • the first transistor is electrically connected to a spin orbit coupling layer.
  • the first transistor When the first transistor is turned on, current flows through the spin orbit coupling layer to change the free layer of the magnetic tunnel junction corresponding to the spin orbit coupling layer.
  • the second transistor is electrically connected to another spin-orbit coupling layer, and when the second transistor is turned on, the current flows through the other spin-orbit coupling layer a spin-orbit coupling layer to change the magnetic field direction of the free layer of the magnetic tunnel junction corresponding to the other spin-orbit coupling layer, thereby adjusting the resistance value of the magnetic tunnel junction to achieve a write operation on the magnetic tunnel junction;
  • third The transistor is electrically connected to the fixed layers in the two magnetic tunnel junctions. When the third transistor is turned on, the resistance value of one of the two magnetic tunnel junctions is detected to achieve reading of one of the two magnetic tunnel junctions. operate.
  • the same transistor is used to realize the read operation of the two magnetic tunnel junctions, and the overall use of three transistors is used to realize the write operation and the read operation of the two magnetic tunnel junctions, that is, three transistors and two magnetic tunnel junctions are used to realize 2 bytes
  • the storage and reading of data is conducive to reducing the number of transistors required to store and read 2-byte data, thereby increasing the layout density of magnetic tunnel junctions and transistors in the magnetic storage structure to improve the magnetic storage structure within unit space. The amount of data stored.
  • Figure 1 is a schematic three-dimensional structural diagram of a magnetic storage structure provided by an embodiment of the present disclosure
  • Figure 2 is another three-dimensional structural schematic diagram of a magnetic storage structure provided by an embodiment of the present disclosure
  • Figure 3 is a top structural schematic diagram of the magnetic storage structure corresponding to Figure 1;
  • Figure 4 is another top structural schematic diagram of the magnetic storage structure corresponding to Figure 2;
  • FIG. 5 is a flow chart of a read and write control method for a magnetic storage array structure provided by yet another embodiment of the present disclosure.
  • SOT-MRAM has better performance than STT-MRAM.
  • SOT-MRAM has faster writing speed, longer breakdown resistance, better device reliability, and is non-volatile.
  • Many advantages in SOT-MRAM, the current path for writing operations to SOT-MRAM and the current path for reading operations to SOT-MRAM are separated, so that a magnetic memory unit requires two transistors to control the read operation and write operation respectively, that is, SOT-MARM usually uses a 2T-1R unit structure to store and read 1-byte data. This results in a large layout area for a single magnetic storage unit in SOT-MRAM, which is not conducive to improving the magnetic properties of SOT-MRAM.
  • the present disclosure provides a magnetic storage structure, a magnetic storage array structure and a control method thereof, and a memory.
  • the first transistor, the second transistor and the third transistor share two magnetic tunnel junctions.
  • the third transistor is used to realize the pairing of the two magnetic tunnel junctions.
  • the first transistor and the second transistor are used to realize the write operation of the two magnetic tunnel junctions respectively, and the overall use of three transistors is used to realize the write operation and the read operation of the two magnetic tunnel junctions, that is, three transistors are used to realize the write operation and the read operation of the two magnetic tunnel junctions.
  • a transistor and two magnetic tunnel junctions realize the storage and reading of 2-byte data, which is beneficial to reducing the number of transistors required to store and read 2-byte data, thereby helping to improve the performance of magnetic tunnel junctions and transistors in magnetic storage structures Layout density in the magnetic storage structure to increase the amount of data stored in the unit space.
  • FIGS. 1 to 4 An embodiment of the present disclosure provides a magnetic storage structure.
  • the magnetic storage structure provided by an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.
  • Figure 1 is a schematic three-dimensional structural diagram of a magnetic storage structure provided by an embodiment of the present disclosure
  • Figure 2 is a schematic three-dimensional structural diagram of a magnetic storage structure provided by an embodiment of the present disclosure
  • Figure 3 is a magnetic structure corresponding to Figure 1
  • Figure 4 is another schematic top view of the magnetic storage structure corresponding to Figure 2. It should be noted that multiple magnetic storage structures are illustrated in FIGS. 1 to 4 .
  • the magnetic memory structure 100 includes: two magnetic tunnel junctions 110.
  • the magnetic tunnel junctions 110 include a fixed layer 120 and a free layer 130; a spin-orbit coupling layer 140 corresponding to the magnetic tunnel junctions 110.
  • the spin-orbit coupling layer 140 is located on the side of the free layer 130 away from the fixed layer 120, the first transistor 101 and the second transistor 102.
  • One spin-orbit coupling layer 140 is electrically connected to the source end or drain end of the first transistor 101, and the other
  • the spin orbit coupling layer 140 is electrically connected to the source end or drain end of the second transistor 102; the third transistor 103, the source end or the drain end of the first transistor 101 are electrically connected to the fixed layers 120 in the two magnetic tunnel junctions 110. .
  • the first transistor 101, the second transistor 102 and the third transistor 103 share two magnetic tunnel junctions 110.
  • the third transistor 103 is used to realize the read operation of the two magnetic tunnel junctions 110
  • the third transistor 103 is used to realize the read operation of the two magnetic tunnel junctions 110.
  • One transistor 101 and the second transistor 102 respectively realize the writing operation of the two magnetic tunnel junctions 110.
  • the overall use of three transistors realizes the writing operation and the reading operation of the two magnetic tunnel junctions 110, that is, three transistors and two magnetic tunnel junctions are used.
  • the tunnel junction 110 implements the storage and reading of 2-byte data, which is beneficial to reducing the number of transistors required to store and read 2-byte data, thereby helping to improve the layout of the magnetic tunnel junction 110 and transistors in the magnetic storage structure 100 Density to increase the amount of data stored by the magnetic storage structure 100 in unit space.
  • the first transistor 101 , the second transistor 102 and the third transistor 103 are all vertical gate-all-around (VGAA, Vertical Gate-All-Around) transistor structures.
  • VGAA Vertical Gate-All-Around
  • the magnetic tunnel junction 110, the first transistor 101, the second transistor 102 and the third transistor 103 are described in detail below.
  • the magnetic tunnel junction 110 includes a fixed layer 120 , a tunneling layer 150 and a Free layer 130.
  • the fixed layer 120 and the free layer 130 are ferromagnetic layers, and the coercive force of the free layer 130 is smaller than the coercive force of the fixed layer 120.
  • the tunnel layer 150 is a non-magnetic insulating layer. It can be understood that the magnetic tunnel junction 110 During saturation magnetization, the magnetization directions of the fixed layer 120 and the free layer 130 are parallel to each other.
  • the coercive force of the free layer 130 is smaller than the coercive force of the fixed layer 120, so the coercive force of the free layer is smaller.
  • the magnetization vector of 130 is first flipped so that the magnetization directions of fixed layer 120 and free layer 130 become anti-parallel.
  • the tunneling probability of electrons tunneling from one ferromagnetic layer to another is related to the magnetization directions of the two ferromagnetic layers.
  • the magnetization directions of the fixed layer 120 and the free layer 130 are parallel to each other, the electrons in the fixed layer 120 and the free layer 130 will The probability of tunneling in the free layer 130 is high, making the magnetic tunnel junction 110 present a low resistance state; if the magnetization directions of the fixed layer 120 and the free layer 130 are opposite, the probability of electrons tunneling in the fixed layer 120 and the free layer 130 is small, making the magnetic tunnel junction Junction 110 assumes a high resistance state.
  • the material of the free layer 130 and the material of the fixed layer 120 both include at least one of cobalt-iron-boron, cobalt, or nickel-iron, and the material of the tunneling layer 150 may be magnesium oxide.
  • the material of the spin-orbit coupling layer 140 may be at least one of platinum, tantalum, tungsten, iridium, gold, and titanium. It can be understood that the spin orbit coupling layer 140 is located on the side of the free layer 130 away from the fixed layer 120.
  • the spin orbit coupling layer 140 uses the interlayer exchange coupling (IEC, Interlayer Exchange Coupling) effect to generate exchange coupling in the free layer 130.
  • IEC Interlayer Exchange Coupling
  • the field through the spin-orbit interaction generated by the current flowing through the spin-orbit coupling layer 140, injects spin current into the free layer 130 to quickly flip the magnetic moment in the free layer 130, thereby not damaging the freedom of the free layer 130.
  • the magnetic tunnel junction 110 presents a low resistance state; when the direction of the magnetic field in the free layer 130 is the same as the direction of the magnetic field in the fixed layer 120 When the direction of the magnetic field is opposite, the magnetic tunnel junction 110 presents a high resistance state. By detecting the resistance of the magnetic tunnel junction 110, it can be determined whether the data stored in the magnetic tunnel junction 110 is "0" or "1".
  • the first transistor 101 includes a first semiconductor channel 111 extending along the direction Z.
  • the first semiconductor channel 111 is divided into three sections along the direction Z. The first section located in the middle is the first.
  • the semiconductor channel 111 serves as the first channel region of the first transistor 101, and the two sections of the first semiconductor channel 111 located on both sides of the first channel region serve as the source end and the drain end of the first transistor 101 respectively.
  • the first transistor 101 also includes a first gate dielectric layer 121 and a first gate electrode 131 that sequentially surround the sidewalls extending in the direction Z of the first channel region.
  • the second transistor 102 includes a second semiconductor channel 112 extending along the direction Z.
  • the second semiconductor channel 112 is divided into three sections along the direction Z.
  • the middle section of the second semiconductor channel 112 serves as the third section of the second transistor 102 .
  • the two sections of second semiconductor channels 112 located on both sides of the second channel region serve as the source end and the drain end of the second transistor 102 respectively.
  • the second transistor 102 further includes a second gate dielectric layer 122 and a second gate electrode 132 that sequentially surround sidewalls extending in the direction Z of the second channel region.
  • the third transistor 103 includes a third semiconductor channel 113 extending along the direction Z.
  • the third semiconductor channel 113 is divided into three sections along the direction Z.
  • the third semiconductor channel 113 located in the middle serves as the third section of the third transistor 103 .
  • the two sections of third semiconductor channels 113 located on both sides of the third channel region serve as the source end and the drain end of the third transistor 103 respectively.
  • the third transistor 103 further includes a third gate dielectric layer 123 and a third gate electrode 133 that sequentially surround the sidewalls extending in the direction Z of the third channel region.
  • the gate dielectric layers of the first transistor 101, the second transistor 102 and the third transistor 103 are not shown in FIGS. 3 and 4, that is, the first gate dielectric layer 121 is not shown. , the second gate dielectric layer 122, and the third gate dielectric layer 123. It can be understood that in FIGS. 3 and 4 , the first semiconductor channel 111 and the first gate 131 are used to illustrate the first transistor 101 , the second semiconductor channel 112 and the second gate 132 are used to illustrate the second transistor 102 , and the third semiconductor channel 112 and the second gate 132 are used to illustrate the second transistor 102 .
  • the semiconductor channel 113 and the third gate 133 represent the third transistor 103 .
  • first semiconductor channel 111, the second semiconductor channel 112 and the third semiconductor channel 113 are respectively illustrated in FIGS. 1 to 4 in three different filling modes to separate the first transistor 101, the second transistor 102 and the third semiconductor channel 113.
  • the third transistor 103 is distinguished. In practical applications, there is no difference in the structure of the first transistor 101 , the second transistor 102 and the third transistor 103 , and they can be formed simultaneously. They just implement different functions in the magnetic storage structure 100 . Moreover, in order to show the positional relationship between various structures in the magnetic storage structure 100, some structures are drawn in perspective in FIGS. 1 to 4 .
  • the arrangement direction of the first transistor 101 and the second transistor 102 , the arrangement direction of the first transistor 101 and the third transistor 103 , the arrangement direction of the second transistor 102 and the third transistor 103 The arrangement directions intersect in pairs.
  • the first transistor 101 , the second transistor 102 and the third transistor 103 are all regarded as individual transistors.
  • the plurality of individual transistors appear in a parallelogram shape. Array arrangement, the arrangement of multiple individual transistors will be described in detail later in the second embodiment of the present disclosure.
  • the first transistor 101 and the third transistor 103 are arranged along the first direction X
  • the first transistor 101 and the second transistor 102 are arranged along the second direction Y
  • the first direction The two directions Y are vertical.
  • the connecting lines intersect two by two, and the three connecting lines form a right triangle.
  • the first transistor 101 , the second transistor 102 and the third transistor 103 are all regarded as individual transistors.
  • the plurality of individual transistors present a rectangular array. Arrangement, the arrangement of multiple individual transistors will be described in detail later in the second embodiment of the present disclosure.
  • the magnetic tunnel junction 110 electrically connected to the first transistor 101 is spaced apart from the first transistor 101 along the first direction X, and the magnetic tunnel junction electrically connected to the second transistor 102 110 and the second transistor 102 are arranged at intervals along the first direction X.
  • the spin orbit coupling layer 140 also extends along the first direction A semiconductor channel 111 is electrically connected to realize the electrical connection between the first transistor 101 and the magnetic tunnel junction 110; or a spin-orbit coupling layer 140 is simultaneously connected to a free layer 130 and a second semiconductor channel 112 of the second transistor 102 Electrical connection to achieve electrical connection between the second transistor 102 and the magnetic tunnel junction 110 .
  • the magnetic tunnel junction 110 is located between the first transistor 101 and the third transistor 103 .
  • the first transistor 101 and the second transistor 102 are arranged in an array along the second direction Y, and along the first direction X, the first transistor 101, the magnetic tunnel junction 110 and the third transistor 103 are arranged in sequence, such that The magnetic tunnel junction 110 is located between the first transistor 101 and the third transistor 103 .
  • the two free layers 130 of the two magnetic tunnel junctions 110 are required to be electrically connected to the first transistor 101 and the second transistor 102 respectively, and the two fixed layers 120 of the two magnetic tunnel junctions 110 are both connected to the third transistor.
  • the magnetic tunnel junction 110 is located between the first transistor 101 and the third transistor 103, which is beneficial to reducing the wiring length of the wiring layer provided in the magnetic memory structure 100.
  • the magnetic tunnel junction 110 is connected to the first transistor 103.
  • the distance between the transistor 101, the second transistor 102 and the third transistor 103 is short, which is beneficial to reducing the spin of the wiring layer that realizes the electrical connection between the magnetic tunnel junction 110 and the first transistor 101 and the second transistor 102.
  • the wiring length of the track coupling layer 140 , and the wiring length of the wiring layer that realizes the electrical connection between the magnetic tunnel junction 110 and the third transistor 103 is reduced.
  • two magnetic tunnel junctions may be spaced apart along the second direction Y.
  • the magnetic memory structure may further include: a first conductive pillar 117 located between the first transistor 101 and the spin-orbit coupling layer 140 , respectively connected to the first conductive pillar 117 of the first transistor 101 .
  • a semiconductor channel 111 is in contact with the spin-orbit coupling layer 140;
  • the second conductive pillar 127 is located between the second transistor 102 and the spin-orbit coupling layer 140, and is respectively connected to the second semiconductor channel 112 and the spin-orbit coupling layer 140 in the second transistor 102.
  • the spin-orbital coupling layer 140 is in contact connection.
  • the first semiconductor channel 111 in the first transistor 101 can be directly connected to the spin-orbit coupling layer 140, and the second semiconductor channel 112 in the second transistor 102 can also be connected to the spin-orbit coupling layer 140.
  • the coupling layer 140 is connected in direct contact.
  • the electrical connection between the two magnetic tunnel junctions 110 and the third transistor 103 is achieved as follows: Referring to Figures 1 to 4, the magnetic memory structure may also include: a first electrical connection layer 116, and two The fixed layer 120 of the magnetic tunnel junction 110 is all in contact with the second electrical connection layer 126. One end of the second electrical connection layer 126 is in contact with the first electrical connection layer 116, and the other end is in contact with the source or drain end of the third transistor 103. Electrical connection.
  • the magnetic memory structure may further include: a third conductive pillar 137 located between the third transistor 103 and the second electrical connection layer 126, respectively connected to the third semiconductor channel 113 and the second semiconductor channel 113 in the third transistor 103.
  • the electrical connection layer 126 makes contact connections. It should be noted that in practical applications, the third semiconductor channel 113 in the third transistor 103 may be directly connected to the second electrical connection layer 126 .
  • the first transistor 101, the second transistor 102 and the third transistor 103 share two magnetic tunnel junctions 110, and the third transistor 103 is used to realize the control of the two magnetic tunnel junctions 110.
  • the first transistor 101 and the second transistor 102 are used to implement the write operation on the two magnetic tunnel junctions 110 respectively.
  • the overall use of three transistors is used to implement the write operation and the read operation on the two magnetic tunnel junctions 110, that is, three transistors are used to implement the write operation and the read operation on the two magnetic tunnel junctions 110.
  • the transistor and the two magnetic tunnel junctions 110 realize the storage and reading of 2-byte data, which is beneficial to reducing the number of transistors required to store and read 2-byte data, thereby helping to improve the performance of the magnetic tunnel junction 110 and the transistor in magnetic storage.
  • the layout density in the structure 100 is to increase the amount of data that the magnetic storage structure 100 can store in a unit space.
  • Another embodiment of the present disclosure also provides a magnetic storage array structure, including a plurality of magnetic storage structures 100 as described in an embodiment of the present disclosure.
  • the magnetic memory array structure provided by another embodiment of the present disclosure will be described in detail below with reference to FIGS. 1 to 4 . It should be noted that the parts that are the same as or corresponding to the previous embodiments will not be described again here.
  • the magnetic storage array structure includes a magnetic storage structure 100, wherein at least two magnetic storage structures 100 are spaced apart along the first direction X; at least two magnetic storage structures 100 are spaced apart along the second direction Y. .
  • two adjacent magnetic storage structures 100 along the second direction Y are centrally symmetrical, and the third transistor 103 of one of the two magnetic storage structures 100 is different from the other.
  • the first transistors 101 are arranged at intervals along the second direction Y. It can be understood that for two adjacent magnetic memory structures 100 along the second direction Y, the four magnetic tunnel junctions 110 are all arranged at intervals along the second direction Y, and the third transistor 103 of one is connected to the third transistor 103 of the other.
  • the first transistor 101 is directly opposite along the second direction Y, and the second transistor 102 of one is directly opposite to the third transistor 103 of the other one along the second direction Y. In this way, it is beneficial to realize the magnetic tunnel junction 110 along the first direction Y. In the direction layout space in the structure to increase the integration density of the magnetic storage structure 100 in the magnetic storage array structure.
  • the first transistor 101, the second transistor 102 and the third transistor 103 are all used as individual transistors, so that the individual transistors are arranged in a parallelogram array, which can Arranging the magnetic storage structures 100 in a regular manner facilitates the production of the magnetic storage array structure, and also facilitates the subsequent unified control of multiple magnetic storage structures 100, and at the same time achieves the most densely packed hexagonal form.
  • the two adjacent magnetic storage structures 100 along the second direction Y can be regarded as a whole, that is, the partial structure shown in FIG. The Y-spaced arrangement is beneficial to further improving the integration density of the magnetic storage structure 100 in the magnetic storage array structure.
  • two adjacent magnetic storage structures 100 along the first direction The third transistors 103 are arranged at intervals along the second direction Y. It can be understood that for two adjacent magnetic memory structures 100 along the first direction The second transistors 102 face each other along the first direction X. One second transistor 102 and the other first transistor 101 face each other along the first direction right. In this way, it is beneficial to realize the layout of two transistors on both sides of the magnetic tunnel junction 110 along the first direction X, thereby helping to reduce the layout of the two adjacent magnetic memory structures 100 along the first direction space to increase the integration density of the magnetic storage structure 100 in the magnetic storage array structure.
  • the first transistor 101, the second transistor 102 and the third transistor 103 are all used as individual transistors, so that the individual transistors are arranged in a rectangular array, so that The regular arrangement of the magnetic storage structures 100 facilitates the production of the magnetic storage array structure, and also facilitates subsequent unified control of multiple magnetic storage structures 100, while achieving the most densely packed form in four directions. Moreover, the two adjacent magnetic storage structures 100 along the first direction The Y-spaced arrangement is beneficial to further improving the integration density of the magnetic storage structure 100 in the magnetic storage array structure.
  • the magnetic storage array structure may further include: a first signal line 114 and a second signal line 124 extending along the first direction X, and magnetic storage arrays arranged along the first direction X.
  • the structure 100 is electrically connected to the same first signal line 114 and to the same second signal line 124 .
  • the spin orbit coupling layers 140 corresponding to the first transistors 101 arranged along the first direction The corresponding spin orbit coupling layers 140 of the second transistors 102 are all electrically connected to the same second signal line 124 .
  • the first transistors 101 and the second transistors 102 are staggered along the first direction X.
  • the first transistors 101 and the second transistors 102 staggered along the first direction
  • the same first signal line 114 or the same second signal line 124 is electrically connected.
  • the storage magnetic memory array structure also includes: a fourth conductive pillar 147, wherein the fourth conductive pillar 147 is located between the spin orbit coupling layer 140 and the first signal line 114. To realize the electrical connection between the spin orbit coupling layer 140 and the first signal line 114; or, the fourth conductive pillar 147 is located between the spin orbit coupling layer 140 and the second signal line 124 to realize the spin orbit coupling layer 140 electrical connection with the second signal line 124 .
  • the magnetic storage array structure may further include: a first control line 115 and a second control line 125 extending along the second direction Y.
  • the magnetic storage structure 100 arranged along the second direction Y is connected to the same first control line 115 and a second control line 125 .
  • the control line 115 is electrically connected to the same second control line 125 .
  • the arrangement order of the transistors located on one side of the magnetic tunnel junction 110 is the first transistor 101 , the second transistor 102 and the third transistor 103 , and by analogy, the transistors are alternately arranged in the second direction Y. cloth; the arrangement order of the transistors located on the other side of the magnetic tunnel junction 110 is the third transistor 103, the second transistor 102 and the first transistor 101, and by analogy, they are alternately arranged in the second direction Y.
  • the gates of the plurality of transistors arranged alternately along the second direction Y of the first transistor 101, the second transistor 102 and the third transistor 103 are all electrically connected to the first control line 115, and the order of arrangement is:
  • the gates of the three transistors 103 , the second transistor 102 and the plurality of transistors alternately arranged along the second direction Y of the first transistor 101 are all electrically connected to the second control line 125 .
  • the first transistors 101 and the second transistors 102 alternately arranged along the second direction Y are both electrically connected to the same first control line 115
  • the first transistors 101 and the second transistors 102 arranged alternately along the second direction Y are
  • the third transistors 103 are all electrically connected to the same second control line 125 .
  • the two third transistors 103 of the two adjacent and centrally symmetrical magnetic memory structures 100 in the first direction The ability to control magnetic storage arrays.
  • multiple magnetic storage structures 100 arranged along the second direction Y can share a first control line 115 and a second control line 125 , which is beneficial to reducing the first control line.
  • the control port of the line 115 and the second control line 125 improves the control capability of the magnetic storage array.
  • first control line 115 and the second control line 125 are not shown in FIGS. 1 and 2 .
  • first control line 115 is in contact with a plurality of gate electrodes arranged along the second direction Y
  • second control line 125 is also in contact with a plurality of gate electrodes arranged along the second direction Y. connect.
  • the magnetic tunnel junction 110 electrically connected to the first transistor 101 is a first magnetic tunnel junction 110 a
  • the magnetic tunnel junction 110 electrically connected to the second transistor 102 is a second magnetic tunnel.
  • Junction 110b; the first magnetic tunnel junction 110a in the magnetic storage structure 100 arranged along the first direction X is electrically connected to the same first signal line 114; the second magnetic tunnel junction 110a in the magnetic storage structure 100 arranged along the first direction X
  • the tunnel junction 110b is electrically connected to the same second signal line 124. It can be understood that the first signal line 114 is used for writing or reading the first magnetic tunnel junction 110a, and the second signal line 124 is used for writing or reading the second magnetic tunnel junction 110b.
  • two adjacent magnetic storage structures 100 along the second direction Y are a first magnetic storage structure 100a and a second magnetic storage structure 100b respectively; the same first control line 115 The first transistor 101 and the second transistor 102 in the first magnetic storage structure 100a and the third transistor 103 in the second magnetic storage structure 100b are electrically connected to control the above three transistors to be in an on state or an off state; the same The two control lines 125 are electrically connected to the first transistor 101 and the second transistor 102 in the second magnetic storage structure 100b and the third transistor 103 in the first magnetic storage structure 100a to control the above three transistors to be in an on state or off. state.
  • the same first control line 115 is electrically connected to the first transistor 101 and the second transistor 102 in the magnetic memory structure 100 arranged along the second direction Y to control the first The transistor 101 and the second transistor 102 are in an on state or an off state; the two adjacent magnetic storage structures 100 along the first direction X are the first magnetic storage structure 100a and the second magnetic storage structure 100b respectively; the same second The control line 125 is electrically connected to the third transistor 103 in the first magnetic storage structure 100a and the third transistor 103 in the second magnetic storage structure 100b to control the third transistor 103 to be in an on state or an off state.
  • the magnetic memory array structure may further include: a first electrical connection layer 116 that is in contact with the fixed layer 120 of a plurality of magnetic tunnel junctions 110 arranged along the second direction Y; a second electrical connection layer 126 , one end of the second electrical connection layer 126 is in contact with the first electrical connection layer 116 , and the other end is in contact with the source end or the drain end of the third transistor 103 .
  • the first electrical connection layer 116 may extend along the second direction Y, and A first electrical connection layer 116 may correspond to multiple magnetic storage structures 100 arranged along the second direction Y, that is, multiple magnetic storage structures 100 arranged along the second direction Y may share a first electrical connection layer. 116.
  • the first gate 131 of the first transistor 101 and the second gate 132 of the second transistor 102 are connected to the first control line 115, so that the first control line 115 controls the first transistor 101 and
  • the third gate 133 of the third transistor 103 is connected to the second control line 125, so that the second control line 125 controls the turning on or off of the third transistor 103;
  • the first transistor 101 The source end or drain end of the second transistor 102 is electrically connected to the spin orbit coupling layer 140 corresponding to the first magnetic tunnel junction 110a, and the first magnetic tunnel junction 110a corresponds to the first signal line 114.
  • the source end or drain end of the second transistor 102 is electrically connected to the spin orbit coupling layer 140.
  • the spin orbit coupling layer 140 corresponding to the second magnetic tunnel junction 110b is connected, and the second magnetic tunnel junction 110b corresponds to the second signal line 124.
  • writing to the first magnetic tunnel junction 110a can be controlled through the first transistor 101 and the first signal line 114
  • writing to the second magnetic tunnel junction 110b can be controlled through the second transistor 102 and the second signal line 124.
  • the third transistor 103 and the first signal line 114 control the reading of the first magnetic tunnel junction 110a
  • the third transistor 103 and the second signal line 124 control the reading of the second magnetic tunnel junction 110b, thereby distinguishing the read and write paths. , to facilitate separate optimizations for reads and writes.
  • the direction of the magnetization structure of the magnetic tunnel junction 110 is perpendicular to the surface of the spin-orbit coupling layer 140 , and the free layer 130 is located on the surface of the spin-orbit coupling layer 140 . In other embodiments, the direction of the magnetization structure of the magnetic tunnel junction 110 is parallel to the surface of the spin-orbit coupling layer 140 , and the free layer 130 is located on the surface of the spin-orbit coupling layer 140 .
  • the direction of the magnetic field in the free layer 130 can be transformed into a direction that is perpendicular and toward the surface of the spin-orbit coupling layer 140, or transformed into a vertical direction. and away from the surface of the spin-orbit coupling layer 140; the direction of the magnetic field in the fixed layer 120 can be fixed to be vertical and away from the surface of the spin-orbit coupling layer 140, or fixed to be vertical and toward the direction of the surface of the spin-orbit coupling layer 140 .
  • the direction of the magnetic field in the free layer 130 is converted by the spin-orbit interaction in the spin-orbit coupling layer 140, the direction of the magnetic field in the free layer 130 is converted to the same direction as that of the fixed layer 120, and the magnetic tunnel junction 110 exhibits low resistance. state; when the direction of the magnetic field in the free layer 130 is switched to be opposite to the direction of the magnetic field in the fixed layer 120, the magnetic tunnel junction 110 exhibits a high resistance state.
  • the direction of the magnetization structure of the magnetic tunnel junction 110 can also be parallel to the surface of the spin-orbit coupling layer 140 , that is, the direction of the magnetic field in the fixed layer 120 of the magnetic tunnel junction 110 is parallel to the surface of the spin-orbit coupling layer 140 , and the free layer 130
  • the magnetic field in the free layer 130 and the fixed layer 120 may have the same or opposite direction.
  • the corresponding magnetic field directions of the free layer 130 and the fixed layer 120 determine the resistance state of the magnetic tunnel junction 110 . It can be understood that the direction of the magnetization structure of the magnetic tunnel junction 110 can be selected and formulated according to the actual situation. This embodiment does not excessively limit the direction of the magnetization structure of the magnetic tunnel junction 110 .
  • the magnetic storage structure 100 in the magnetic storage array structure can store a high amount of data per unit space, and can reduce the number of transistors required to store and read 2-byte data, thereby conducive to improving the efficiency of magnetic storage.
  • the array structure stores the amount of data per unit space and reduces the number of transistors required to store and read data of a certain size.
  • adopting the arrangement of the magnetic storage structure 100 in the magnetic storage array structure as shown in FIG. 3 or FIG. 4 is beneficial to improving the integration density of the magnetic storage structure 100 in the magnetic storage array structure and reducing the number of required third components.
  • the number of the first signal line 114, the second signal line 124, the first control line 115 and the second control line 125 is reduced to reduce the number of the first signal line 114, the second signal line 124, the first control line 115 and the second control line 125 control port to improve the control capabilities of magnetic storage arrays.
  • Another embodiment of the present disclosure also provides a memory, the array structure of the memory is based on the magnetic storage array structure described in another embodiment of the present disclosure. It should be noted that the parts that are the same as or corresponding to the previous embodiments will not be described again here.
  • the array structure of the memory is based on the magnetic storage array structure described in another embodiment of the present disclosure, it is beneficial to increase the amount of data stored by the memory in the unit space, improve the memory's ability to control the magnetic storage array, and Improve the integration density of magnetic storage array structures in memories.
  • the memory may be a memory unit or device based on a semiconductor device or component.
  • the memory may be a volatile memory such as dynamic random access memory DRAM or may be a non-volatile memory such as phase change random access memory PRAM, magnetic random access memory MRAM, resistive random access memory RRAM, etc.
  • Yet another embodiment of the present disclosure also provides a read and write control method for a magnetic storage array structure, which is used to control the magnetic storage array structure provided in the previous embodiment or the magnetic storage structure in the magnetic storage array structure.
  • the read and write control method of the magnetic storage array structure provided by yet another embodiment of the present disclosure will be described in detail below with reference to FIGS. 1 to 5 . It should be noted that the parts that are the same as or corresponding to the previous embodiments will not be described again here.
  • FIG. 5 is a flow chart of a read and write control method for a magnetic storage array structure provided by yet another embodiment of the present disclosure.
  • the read and write control method of the magnetic storage array structure includes the following steps:
  • S101 Control one of the first transistor 101 and the second transistor 102 to be in a conductive state; control the current flowing through the spin-orbit coupling layer 140 to set the state of one of the two magnetic tunnel junctions 110 to a high resistance state. or a low-resistance state to implement a write operation on the magnetic tunnel junction 110 , wherein the magnetic tunnel junction 110 that implements the write operation corresponds to the first transistor 101 in the conductive state or the second transistor 102 in the conductive state.
  • S102 Control the third transistor 103 to be in a conductive state; read the magnitude of the current flowing through one of the two magnetic tunnel junctions 110 to determine whether the magnetic tunnel junction 110 is in a high-resistance state or a low-resistance state, so as to realize the control of the magnetic tunnel junction. 110 read operations.
  • the magnetic tunnel junction 110 electrically connected to the first transistor 101 is the first magnetic tunnel junction 110a
  • the spin orbit coupling layer 140 corresponding to the first magnetic tunnel junction 110a is the first spin orbit coupling layer 140a
  • the magnetic tunnel junction 110 electrically connected to the second transistor 102 is the second magnetic tunnel junction 110b
  • the spin orbit coupling layer 140 corresponding to the second magnetic tunnel junction 110b is the second spin orbit coupling layer 140b.
  • the steps of implementing the read operation and the write operation may include: with reference to FIGS. 1 to 4 , controlling the current flowing through the first spin-orbit coupling layer 140a through the first signal line 114 to set the state of the first magnetic tunnel junction 110a is a high resistance state or a low resistance state; the current flowing through the second spin orbit coupling layer 140b is controlled through the second signal line 124 to set the state of the second magnetic tunnel junction 110b to a high resistance state or a low resistance state; through the first The control line 115 and the second control line 125 control the first transistor 101, the second transistor 102 and the third transistor 103 to be turned on or off.
  • the step of controlling part of the magnetic storage structure 100 to perform a write operation may include the following two methods:
  • the first signal line 114 and the first control line 115 are gated to turn on the first transistor 101, and the current flowing through the first spin-orbit coupling layer 140a is controlled to set the first magnetic tunnel junction 110a
  • the state is a high-resistance state or a low-resistance state to implement the writing operation on the first magnetic tunnel junction 110a.
  • a turn-on voltage is applied on the first control line 115 corresponding to the first magnetic storage structure 100a, that is, The first control line 115 is turned on to turn on the first transistor 101, and then a voltage is applied to the first signal line 114, that is, the first signal line 114 is turned on. At this time, the current passes through the first signal line 114 and the first spindle. Track coupling layer 140a and first transistor 101.
  • applying a positive writing voltage or a negative writing voltage to the first signal line 114 causes the current flowing through the first spin-orbit coupling layer 140a to generate spin-orbit interaction, thereby flowing into the free layer 130
  • the spin current is injected and the magnetic moment in the free layer 130 is rapidly flipped, so that the state of the first magnetic tunnel junction 110a is a high resistance state or a low resistance state.
  • the second signal line 124 and the first control line 115 are gated to turn on the second transistor 102, and the current flowing through the second spin orbit coupling layer 140b is controlled to set the second magnetic tunnel junction.
  • the state of 110b is a high-resistance state or a low-resistance state to implement a writing operation on the second magnetic tunnel junction 110b.
  • a conduction voltage is applied on the first control line 115 corresponding to the second magnetic tunnel junction 110b, that is, The first control line 115 is turned on to turn on the second transistor 102, and then a voltage is applied to the second signal line 124, that is, the second signal line 124 is turned on. At this time, the current passes through the second signal line 124 and the second spindle. Track coupling layer 140b and second transistor 102.
  • applying a positive writing voltage or a negative writing voltage to the second signal line 124 causes the current flowing through the second spin-orbit coupling layer 140b to generate spin-orbit interaction, thereby flowing into the free layer 130
  • the spin current is injected and the magnetic moment in the free layer 130 is rapidly flipped, so that the state of the second magnetic tunnel junction 110b is a high resistance state or a low resistance state.
  • the step of controlling part of the magnetic storage structure 100 to perform a read operation may include the following two methods:
  • the first signal line 114 and the second control line 125 are gated to turn on the third transistor 103, and the magnitude of the current flowing through the first magnetic tunnel junction 110a is read to determine the first magnetic tunnel junction.
  • 110a is in a high-resistance state or a low-resistance state to implement a read operation on the first magnetic tunnel junction 110a.
  • a guide is applied to the second control line 125 corresponding to the first magnetic storage structure 100a. Turn on the voltage, that is, turn on the second control line 125 to turn on the third transistor 103, and then turn on the first signal line 114 so that the current can pass through the first signal line 114, the first magnetic tunnel junction 110a, and the first electrical connection. layer 116 , the second electrical connection layer 126 and the third transistor 103 . In this way, the resistance of the first magnetic tunnel junction 110a can be detected through the first signal line 114 and the end of the third transistor 103 away from the second electrical connection layer 126. If the first magnetic tunnel junction 110a presents a high resistance state, the stored data is "1"; if the first magnetic tunnel junction 110a presents a low configuration, the stored data is "0".
  • the step of controlling part of the magnetic storage structure 100 to perform a read operation may include: strobing the second signal line 124 and the second control line 125 to turn on the third transistor 103, and reading the flow through the second The magnitude of the current of the magnetic tunnel junction 110b is used to determine whether the second magnetic tunnel junction 110b is in a high-resistance state or a low-resistance state, so as to implement a read operation on the second magnetic tunnel junction 110b.
  • a guide is applied to the second control line 125 corresponding to the second magnetic storage structure 100b. Turn on the voltage, that is, turn on the second control line 125 to turn on the third transistor 103, and then turn on the second signal line 124 so that the current can pass through the second signal line 124, the second magnetic tunnel junction 110b, and the first electrical connection. layer 116 , the second electrical connection layer 126 and the third transistor 103 . In this way, the resistance of the second magnetic tunnel junction 110b can be detected through the second signal line 124 and the end of the third transistor 103 away from the second electrical connection layer 126. If the second magnetic tunnel junction 110b presents a high resistance state, the stored data is "1"; if the second magnetic tunnel junction 110b presents a low configuration, the stored data is "0".
  • three transistors and two magnetic tunnel junctions 110 can be used to realize the storage and reading of 2-byte data, which is beneficial to improving
  • the magnetic storage structure 100 and/or the magnetic storage array structure can store the amount of data in a unit space, and reduce the number of transistors required to store and read data of a certain size; in addition, it is beneficial to reduce the need to use the first signal line 114 , the number of the second signal line 124, the first control line 115 and the second control line 125, so as to reduce the control ports of the first signal line 114, the second signal line 124, the first control line 115 and the second control line 125, Reduce the complexity of read and write control of magnetic storage array structures.

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Abstract

本公开实施例涉及半导体技术领域，提供一种磁性存储结构、磁性存储阵列结构及其控制方法及存储器，磁性存储结构包括：两个磁性隧道结，磁性隧道结包括固定层和自由层；与磁性隧道结一一对应的自旋轨道耦合层，自旋轨道耦合层位于自由层远离固定层的一侧，第一晶体管和第二晶体管，一自旋轨道耦合层与第一晶体管的源端或漏端电连接，另一自旋轨道耦合层与第二晶体管的源端或漏端电连接；第三晶体管，第一晶体管的源端或漏端与两个磁性隧道结中的固定层均电连接。本公开实施例至少有利于提高磁性隧道结和晶体管在磁性存储结构中的布局密度，以提高磁性存储结构在单位空间内存储的数据量。

Description

磁性存储结构、磁性存储阵列结构及其控制方法及存储器
交叉引用
本申请要求于2022年08月22日递交的名称为“磁性存储结构、磁性存储阵列结构及其控制方法及存储器”、申请号为202211009132.1的中国专利申请的优先权，其通过引用被全部并入本申请。
技术领域
本公开实施例涉及半导体领域，特别涉及一种磁性存储结构、磁性存储阵列结构及其控制方法及存储器。
背景技术
磁性随机存储器(MRAM，Magnetic Random Access Memory)是一种新型固态非易失性记忆体，具有高速读写的特性，利用磁性隧道结(MTJ，Magnetic Tunnel Junction)的特性形成。其中，MRAM靠磁场极化而非电荷以存储数据，MTJ由自由层、隧穿层、固定层组成，自由层的磁场方向可以改变，固定层的磁场方向不变，当自由层与固定层的磁场方向相同时，MTJ呈现低电阻状态；当自由层与固定层的磁场方向相反时，MTJ呈现高电阻状态，则通过检测MTJ电阻的高低，即可判断所存数据是“0”还是“1”。
传统的自旋转移力矩磁性存储(STT-MRAM，Spin-Transfer Torque Magnetic Random Access Memory)利用电子的自旋角动量转移，即自旋极化的电子流将其角动量转移给自由层中的磁性材料。随着自旋轨道矩效应的发现，提出了一种自旋轨道矩磁性存储器(SOT-MRAM，Spin-Orbit Torque Magnetic Random Access Memory)，SOT-MRAM基于自旋轨道耦合，利用电荷流诱导的自旋流来产生自旋转移力矩，进而达到调控磁性存储单元的目的。但是，如何实现提高MRAM中MTJ的布局密度成为亟待解决的问题。
发明内容
本公开实施例提供一种磁性存储结构、磁性存储阵列结构及其控制方法及存储器，至少有利于提高磁性隧道结和晶体管在磁性存储结构中的布局密度，以在提高磁性存储结构在单位空间内存储的数据量。
根据本公开一些实施例，本公开实施例一方面提供一种磁性存储结构，包括：两个磁性隧道结，所述磁性隧道结包括固定层和自由层；与所述磁性隧道结一一对应的自旋轨道耦合层，所述自旋轨道耦合层位于所述自由层远离所述固定层的一侧，第一晶体管和第二晶体管，一所述自旋轨道耦合层与所述第一晶体管的源端或漏端电连接，另一所述自旋轨道耦合层与所述第二晶体管的源端或漏端电连接；第三晶体管，所述第三晶体管的源端或漏端与两个所述磁性隧道结中的所述固定层均电连接。
在一些实施例中，所述第一晶体管、所述第二晶体管和所述第三晶体管均为垂直的全环绕栅极晶体管结构。
在一些实施例中，所述第一晶体管与所述第二晶体管的排布方向、所述第一晶体管与所述第三晶体管的排布方向、所述第二晶体管与所述第三晶体管的排布方向两两相交。
在一些实施例中，所述第一晶体管和所述第三晶体管沿第一方向排布，所述第一晶体管与所述第二晶体管沿第二方向排布，所述第一方向和所述第二方向垂直。
在一些实施例中，与所述第一晶体管电连接的所述磁性隧道结与所述第一晶体管沿第一方向间隔排布，与所述第二晶体管电连接的所述磁性隧道结与所述第二晶体管沿第一方向间隔排布。
在一些实施例中，所述磁性隧道结位于所述第一晶体管和所述第三晶体管之间。
在一些实施例中，所述自旋轨道耦合层的材料为铂、钽、钨、铱、金和钛中的至少一种。
在一些实施例中，所述自由层的材料和所述固定层的材料均包括钴铁硼、钴或镍铁中的至少一种。
根据本公开一些实施例，本公开实施例另一方面还提供一种磁性存储阵列结构，包括多个如前述任一项所述的磁性存储结构，其特征在于，至少两个所述磁性存储结构沿第一方向间隔排布；至少两个所述磁性存储结构沿第二方向间隔排布，其中，沿所述第二方向相邻的两个所述磁性存储结构呈中心对称，且两个所述磁性存储结构中一者的所述第三晶体管与另一者的所述第一晶体管沿所述第二方向间隔排布，或者，沿所述第一方向相邻的两个所述磁性存储结构呈中心对称，且两个所述磁性存储结构中一者的所述第三晶体管与另一者的所述第三晶体管沿所述第二方向间隔排布；所述磁性存储阵列结构还包括：沿所述第一方向延伸的第一信号线和第二信号线，沿所述第一方向排布的所述磁性存储结构与同一所述第一信号线电连接，且与同一所述第二信号线电连接；沿所述第二方向延伸的第一控制线和第二控制线，沿所述第二方向排布的所述磁性存储结构与同一所述第一控制线电连接，且与同一所述第二控制线电连接。
在一些实施例中，与所述第一晶体管电连接的所述磁性隧道结为第一磁性隧道结，与所述第二晶体管电连接的所述磁性隧道结为第二磁性隧道结；沿所述第一方向排布的所述磁性存储结构中的所述第一磁性隧道结与同一所述第一信号线电连接；沿所述第一方向排布的所述磁性存储结构中的所述第二磁性隧道结与同一所述第二信号线电连接。
在一些实施例中，沿所述第二方向上相邻的两个所述磁性存储结构分别为第一磁性存储结构和第二磁性存储结构；同一所述第一控制线电连接所述第一磁性存储结构中的所述第一晶体管和所述第二晶体管以及所述第二磁性存储结构中的所述第三晶体管；同一所述第二控制线电连接所述第二磁性存储结构中的所述第一晶体管和所述第二晶体管以及所述第一磁 性存储结构中的所述第三晶体管。
在一些实施例中，同一所述第一控制线电连接沿所述第二方向排布的所述磁性存储结构中的所述第一晶体管和所述第二晶体管；沿所述第一方向上相邻的两个所述磁性存储结构分别为第一磁性存储结构和第二磁性存储结构；同一所述第二控制线电连接所述第一磁性存储结构中的所述第三晶体管以及所述第二磁性存储结构中的所述第三晶体管。
在一些实施例中，所述磁性存储阵列结构还包括：第一电连接层，与沿所述第二方向上排布的多个所述磁性隧道结的所述固定层接触连接；第二电连接层，所述第二电连接层的一端与所述第一电连接层接触连接，另一端与所述第三晶体管的源端或漏端接触连接。
在一些实施例中，所述磁性隧道结的磁化结构方向与所述自旋轨道耦合层的表面垂直，所述自由层位于所述自旋轨道耦合层的表面。
在一些实施例中，所述磁性隧道结的磁化结构方向与所述自旋轨道耦合层的表面平行，所述自由层位于所述自旋轨道耦合层的表面。
根据本公开一些实施例，本公开实施例又一方面还提供一种存储器，所述存储器的阵列结构基于前述任一项所述的磁性存储阵列结构设置。
根据本公开一些实施例，本公开实施例再一方面还提供一种磁性存储阵列结构的读写控制方法，包括：控制第一晶体管和第二晶体管中的一者处于导通状态；控制流经自旋轨道耦合层的电流以设置两个所述磁性隧道结中的一者的状态为高阻态或低阻态，以实现对所述磁性隧道结的写操作，其中，实现所述写操作的所述磁性隧道结与处于导通状态的所述第一晶体管或者处于导通状态的所述第二晶体管对应；控制第三晶体管处于导通状态；读取流经两个所述磁性隧道结中一者的电流的大小以判断所述磁性隧道结为高阻态还是低阻态，以实现对所述磁性隧道结的读操作。
在一些实施例中，与所述第一晶体管电连接的磁性隧道结为第一磁性隧道结，与所述第一磁性隧道结对应的所述自旋轨道耦合层为第一自旋轨道耦合层，与所述第二晶体管电连接的磁性隧道结为第二磁性隧道结，与所述第二磁性隧道结对应的所述自旋轨道耦合层为第二自旋轨道耦合层；实现所述读操作和所述写操作的步骤包括：通过第一信号线控制流经所述第一自旋轨道耦合层的电流以设置所述第一磁性隧道结的状态为高阻态或低阻态；通过第二信号线控制流经所述第二自旋轨道耦合层的电流以设置所述第二磁性隧道结的状态为高阻态或低阻态；通过第一控制线和第二控制线控制所述第一晶体管、所述第二晶体管以及所述第三晶体管的导通或关闭。
在一些实施例中，控制部分所述磁性存储结构进行所述写操作的步骤包括：选通所述第一信号线和所述第一控制线，以导通所述第一晶体管，以及控制流经所述第一自旋轨道耦合层的电流以设置所述第一磁性隧道结的状态为高阻态或低阻态，以实现对所述第一磁性隧道结的所述写操作；或者，选通所述第二信号线和所述第一控制线，以导通所述第二晶体管， 以及控制流经所述第二自旋轨道耦合层的电流以设置所述第二磁性隧道结的状态为高阻态或低阻态，以实现对所述第二磁性隧道结的所述写操作。
在一些实施例中，控制部分所述磁性存储结构进行所述读操作的步骤包括：选通所述第一信号线和所述第二控制线，以导通所述第三晶体管，以及读取流经所述第一磁性隧道结的电流的大小以判断所述第一磁性隧道结为高阻态还是低阻态，以实现对所述第一磁性隧道结的所述读操作；或者，选通所述第二信号线和所述第二控制线，以导通所述第三晶体管，以及读取流经所述第二磁性隧道结的电流的大小以判断所述第二磁性隧道结为高阻态还是低阻态，以实现对所述第二磁性隧道结的所述读操作。
本公开实施例提供的技术方案至少具有以下优点：
磁性存储结构中，三个晶体管共用两个磁性隧道结，即第一晶体管、第二晶体管和第三晶体管共用两个磁性隧道结。具体的，第一晶体管与一自旋轨道耦合层电连接，在第一晶体管导通时，电流流经该自旋轨道耦合层以改变与该自旋轨道耦合层对应的磁性隧道结的自由层的磁场方向，从而调节磁性隧道结的电阻值以实现对该磁性隧道结的写操作；第二晶体管与另一自旋轨道耦合层电连接，在第二晶体管导通时，电流流经该另一自旋轨道耦合层以改变与该另一自旋轨道耦合层对应的磁性隧道结的自由层的磁场方向，从而调节磁性隧道结的电阻值以实现对该磁性隧道结的写操作；第三晶体管与两个磁性隧道结中的固定层均电连接，在第三晶体管导通时对两个磁性隧道结中一者的电阻值进行检测，以实现对两个磁性隧道结中一者的读操作。如此，利用同一晶体管实现对两个磁性隧道结的读操作，整体利用三个晶体管实现对两个磁性隧道结的写操作和读操作，即利用三个晶体管和两个磁性隧道结实现2字节数据的存储和读取，有利于降低存储和读取2字节数据所需的晶体管的数量，从而提高磁性隧道结和晶体管在磁性存储结构中的布局密度，以提高磁性存储结构在单位空间内存储的数据量。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制。一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一实施例提供的磁性存储结构的一种立体结构示意图；
图2为本公开一实施例提供的磁性存储结构的另一种立体结构示意图；
图3为与图1对应的磁性存储结构的一种俯视结构示意图；
图4为与图2对应的磁性存储结构的另一种俯视结构示意图；
图5为本公开再一实施例提供的磁性存储阵列结构的读写控制方法的一种流程图。
具体实施方式
经分析发现，SOT-MRAM的性能较之STT-MRAM的性能更优，SOT-MRAM具有更快的写入速度、更长的耐击穿性能以及器件可靠性更佳，同时具备不可挥发性等众多优点。然而，SOT-MRAM中，对SOT-MRAM进行写操作的电流路径和对SOT-MRAM进行读操作的电流路径分开，使得一个磁性存储单元需要2个晶体管分别控制读取操作和写入操作，即SOT-MARM通常采用的是2T-1R的单元结构，以实现对1字节数据的存储和读取，造成SOT-MRAM中单个磁性存储单元的布局面积较大，不利于提高SOT-MRAM中磁性存储单元的集成密度以及存储的数据量。
本公开实施提供一种磁性存储结构、磁性存储阵列结构及其控制方法及存储器，磁性存储结构中第一晶体管、第二晶体管和第三晶体管共用两个磁性隧道结，利用第三晶体管实现对两个磁性隧道结的读操作，利用第一晶体管和第二晶体管分别实现对两个磁性隧道结的写操作，整体利用三个晶体管实现对两个磁性隧道结的写操作和读操作，即利用三个晶体管和两个磁性隧道结实现2字节数据的存储和读取，有利于降低存储和读取2字节数据所需的晶体管的数量，从而有利于提高磁性隧道结和晶体管在磁性存储结构中的布局密度，以提高磁性存储结构在单位空间内存储的数据量。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开实施例而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开实施例所要求保护的技术方案。
本公开一实施例提供一种磁性存储结构，以下将结合附图对本公开一实施例提供的磁性存储结构进行详细说明。图1为本公开一实施例提供的磁性存储结构的一种立体结构示意图；图2为本公开一实施例提供的磁性存储结构的另一种立体结构示意图；图3为与图1对应的磁性存储结构的一种俯视结构示意图；图4为与图2对应的磁性存储结构的另一种俯视结构示意图。需要说明的是图1至图4中均示意出多个磁性存储结构。
参考图1至图4，磁性存储结构100包括：两个磁性隧道结110，磁性隧道结110包括固定层120和自由层130；与磁性隧道结110一一对应的自旋轨道耦合层140，自旋轨道耦合层140位于自由层130远离固定层120的一侧，第一晶体管101和第二晶体管102，一自旋轨道耦合层140与第一晶体管101的源端或漏端电连接，另一自旋轨道耦合层140与第二晶体管102的源端或漏端电连接；第三晶体管103，第一晶体管101的源端或漏端与两个磁性隧道结110中的固定层120均电连接。
对于单个磁性存储结构100而言，第一晶体管101、第二晶体管102和第三晶体管103 共用两个磁性隧道结110，利用第三晶体管103实现对两个磁性隧道结110的读操作，利用第一晶体管101和第二晶体管102分别实现对两个磁性隧道结110的写操作，整体利用三个晶体管实现对两个磁性隧道结110的写操作和读操作，即利用三个晶体管和两个磁性隧道结110实现2字节数据的存储和读取，有利于降低存储和读取2字节数据所需的晶体管的数量，从而有利于提高磁性隧道结110和晶体管在磁性存储结构100中的布局密度，以提高磁性存储结构100在单位空间内存储的数据量。
在一些实施例中，继续参考图1和图2，第一晶体管101、第二晶体管102和第三晶体管103均为垂直的全环绕栅极(VGAA，Vertical Gate-All-Around)晶体管结构。如此，有利于降低晶体管在水平方向，即垂直于方向Z的平面上的布局面积，使得用于控制晶体管沟道区的字线以及与晶体管源端或漏端连接的位线沿方向Z上排布，有利于构成3D堆叠的磁性存储结构100，从而有利于提高磁性存储结构100的集成密度。
以下对磁性隧道结110、第一晶体管101、第二晶体管102和第三晶体管103进行详细说明。
在一些实施例中，参考图1和图2，沿磁性隧道结110指向自旋轨道耦合层140的方向，即方向Z上，磁性隧道结110包括依次堆叠的固定层120、隧穿层150和自由层130。其中，固定层120和自由层130为铁磁层，且自由层130的矫顽力小于固定层120的矫顽力，隧穿层150为非磁绝缘层，可以理解的是，磁性隧道结110饱和磁化时，固定层120和自由层130的磁化方向互相平行，磁性隧道结110反向磁化时，自由层130的矫顽力小于固定层120的矫顽力，则矫顽力小的自由层130的磁化矢量首先翻转，使得固定层120和自由层130的磁化方向变成反平行。此外，电子从一个铁磁层隧穿到另一个铁磁层的隧穿几率与两铁磁层的磁化方向有关，若固定层120和自由层130的磁化方向互相平行，电子在固定层120和自由层130隧穿的几率大，使得磁性隧道结110呈现低电阻状态；若固定层120和自由层130的磁化方向相反，电子在固定层120和自由层130隧穿的几率小，使得磁性隧道结110呈现高电阻状态。
在一些实施例中，自由层130的材料和固定层120的材料均包括钴铁硼、钴或镍铁中的至少一种，隧穿层150的材料可以为氧化镁。
在一些实施例中，自旋轨道耦合层140的材料可以为铂、钽、钨、铱、金和钛中的至少一种。可以理解的是，自旋轨道耦合层140位于自由层130远离固定层120的一侧，自旋轨道耦合层140利用层间交换耦合(IEC，Interlayer Exchange Coupling)效应在自由层130中产生交换耦合场，通过流经该自旋轨道耦合层140的电流所产生的自旋轨道交互作用，向自由层130中注入自旋电流以令自由层130内的磁矩快速地翻转，从而不损及自由层130与隧穿层150，当自由层130内的磁场方向与固定层120内的磁场方向相同时，磁性隧道结110呈现低电阻状态；当自由层130内的磁场方向与固定层120内的磁场方向相反时，磁性隧道结110呈现高电阻状态，通过检测磁性隧道结110电阻的高低，即可判断磁性隧道结110所 存的数据是“0”还是“1”。
在一些实施例中，参考图1和图2，第一晶体管101包括沿方向Z上延伸的第一半导体通道111，第一半导体通道111沿方向Z上分为三段，位于中间的一段第一半导体通道111作为第一晶体管101的第一沟道区，位于第一沟道区两侧的两段第一半导体通道111分别作为第一晶体管101的源端和漏端。第一晶体管101还包括依次环绕第一沟道区沿方向Z上延伸的侧壁的第一栅介质层121和第一栅极131。
类似的，第二晶体管102包括沿方向Z上延伸的第二半导体通道112，第二半导体通道112沿方向Z上分为三段，位于中间的一段第二半导体通道112作为第二晶体管102的第二沟道区，位于第二沟道区两侧的两段第二半导体通道112分别作为第二晶体管102的源端和漏端。第二晶体管102还包括依次环绕第二沟道区沿方向Z上延伸的侧壁的第二栅介质层122和第二栅极132。
类似的，第三晶体管103包括沿方向Z上延伸的第三半导体通道113，第三半导体通道113沿方向Z上分为三段，位于中间的一段第三半导体通道113作为第三晶体管103的第三沟道区，位于第三沟道区两侧的两段第三半导体通道113分别作为第三晶体管103的源端和漏端。第三晶体管103还包括依次环绕第三沟道区沿方向Z上延伸的侧壁的第三栅介质层123和第三栅极133。
需要说明的是，为了图示的简洁性，图3和图4中未示意出第一晶体管101、第二晶体管102和第三晶体管103的栅介质层，即未示意出第一栅介质层121、第二栅介质层122，第三栅介质层123。可以理解的是，图3和图4中以第一半导体通道111和第一栅极131示意第一晶体管101，以第二半导体通道112和第二栅极132示意第二晶体管102，以第三半导体通道113和第三栅极133示意第三晶体管103。
此外，图1至图4中均以三种不同的填充方式分别示意出第一半导体通道111、第二半导体通道112和第三半导体通道113，以将出第一晶体管101、第二晶体管102和第三晶体管103区分开来，实际应用中，第一晶体管101、第二晶体管102和第三晶体管103自身的构造没有差别，可以同步形成，只是在磁性存储结构100中实现不同的功能。而且，为了显示磁性存储结构100中各个结构之间的位置关系，图1至图4中均对部分结构采用透视的绘制方式。
在一些实施例中，参考图3和图4，第一晶体管101与第二晶体管102的排布方向、第一晶体管101与第三晶体管103的排布方向、第二晶体管102与第三晶体管103的排布方向两两相交。
在一个例子中，参考图3，对于单个磁性存储结构100而言，第一晶体管101与第二晶体管102之间的连线、第一晶体管101与第三晶体管103之间的连线、第二晶体管102与第三晶体管103之间的连线两两相交，且三条连线构成一锐角三角形。可以理解的是，将第 一晶体管101、第二晶体管102和第三晶体管103均作为一个个晶体管个体，在包含多个按预设规则排列的磁性存储结构100时，多个晶体管个体呈现平行四边形阵列排布，后续在本公开第二实施例中对多个晶体管个体的排布方式进行详细说明。
在另一个例子中，参考图4，第一晶体管101和第三晶体管103沿第一方向X排布，第一晶体管101与第二晶体管102沿第二方向Y排布，第一方向X和第二方向Y垂直。如此，对于单个磁性存储结构100而言，第一晶体管101与第二晶体管102之间的连线、第一晶体管101与第三晶体管103之间的连线、第二晶体管102与第三晶体管103之间的连线两两相交，且三条连线构成一直角三角形。可以理解的是，将第一晶体管101、第二晶体管102和第三晶体管103均作为一个个晶体管个体，在包含多个按预设规则排列的磁性存储结构100时，多个晶体管个体呈现矩形阵列排布，后续在本公开第二实施例中对多个晶体管个体的排布方式进行详细说明。
在一些实施例中，参考图1至图4，与第一晶体管101电连接的磁性隧道结110与第一晶体管101沿第一方向X间隔排布，与第二晶体管102电连接的磁性隧道结110与第二晶体管102沿第一方向X间隔排布。在一个例子中，自旋轨道耦合层140也沿第一方向X延伸，且与磁性隧道结110一一对应，一自旋轨道耦合层140同时与一自由层130和一第一晶体管101的第一半导体通道111电连接，以实现第一晶体管101与磁性隧道结110之间的电连接；或者一自旋轨道耦合层140同时与一自由层130和一第二晶体管102的第二半导体通道112电连接，以实现第二晶体管102与磁性隧道结110之间的电连接。
在一些实施例中，参考图1至图4，磁性隧道结110位于第一晶体管101和第三晶体管103之间。在一个例子中，第一晶体管101和第二晶体管102沿第二方向Y阵列排布，沿第一方向X上，第一晶体管101、磁性隧道结110和第三晶体管103依次间隔排布，使得磁性隧道结110位于第一晶体管101和第三晶体管103之间。可以理解的是，在需要两个磁性隧道结110的两个自由层130分别与第一晶体管101和第二晶体管102电连接，且两个磁性隧道结110的两个固定层120均与第三晶体管103电连接时，磁性隧道结110位于第一晶体管101和第三晶体管103之间有利于降低在磁性存储结构100中设置的布线层的布线长度，具体的，使得磁性隧道结110与第一晶体管101、第二晶体管102和第三晶体管103之间的距离均较短，则有利于降低实现磁性隧道结110与第一晶体管101和第二晶体管102之间电连接的布线层，即自旋轨道耦合层140的布线长度，以及降低实现磁性隧道结110与第三晶体管103之间电连接的布线层的布线长度。在一个例子中，两个磁性隧道结可以沿第二方向Y间隔排布。
在一些实施例中，参考图1和图2，磁性存储结构还可以包括：第一导电柱117，位于第一晶体管101与自旋轨道耦合层140之间，分别与第一晶体管101中的第一半导体通道111和自旋轨道耦合层140接触连接；第二导电柱127，位于第二晶体管102与自旋轨道耦合层140之间，分别与第二晶体管102中的第二半导体通道112和自旋轨道耦合层140接触连 接。需要说明的是，在实际应用中，第一晶体管101中的第一半导体通道111可以和自旋轨道耦合层140直接接触连接，第二晶体管102中的第二半导体通道112也可以和自旋轨道耦合层140直接接触连接。
在一些实施例中，实现两个磁性隧道结110与第三晶体管103之间电连接的方式如下：参考图1至图4，磁性存储结构还可以包括：第一电连接层116，与两个磁性隧道结110的固定层120均接触连接；第二电连接层126，第二电连接层126的一端与第一电连接层116接触连接，另一端与第三晶体管103的源端或漏端电连接。
在一些实施例中，磁性存储结构还可以包括：第三导电柱137，位于第三晶体管103与第二电连接层126之间，分别与第三晶体管103中的第三半导体通道113和第二电连接层126接触连接。需要说明的是，在实际应用中，第三晶体管103中的第三半导体通道113可以和第二电连接层126直接接触连接。
综上所述，对于单个磁性存储结构100而言，第一晶体管101、第二晶体管102和第三晶体管103共用两个磁性隧道结110，利用第三晶体管103实现对两个磁性隧道结110的读操作，利用第一晶体管101和第二晶体管102分别实现对两个磁性隧道结110的写操作，整体利用三个晶体管实现对两个磁性隧道结110的写操作和读操作，即利用三个晶体管和两个磁性隧道结110实现2字节数据的存储和读取，有利于降低存储和读取2字节数据所需的晶体管的数量，从而有利于提高磁性隧道结110和晶体管在磁性存储结构100中的布局密度，以提高磁性存储结构100在单位空间内存储的数据量。
本公开另一实施例还提供一种磁性存储阵列结构，包括多个如本公开一实施例所述的磁性存储结构100。以下将结合图1至图4对本公开另一实施例提供的磁性存储阵列结构进行详细说明。需要说明的是，与前述实施例相同或相应的部分在此不再赘述。
参考图3和图4，磁性存储阵列结构包括磁性存储结构100，其中，至少两个磁性存储结构100沿第一方向X间隔排布；至少两个磁性存储结构100沿第二方向Y间隔排布。
以下通过两种实施例对多个磁性存储结构100的排布方式进行详细说明。
在一些实施例中，参考图1和图3，沿第二方向Y相邻的两个磁性存储结构100呈中心对称，且两个磁性存储结构100中一者的第三晶体管103与另一者的第一晶体管101沿第二方向Y间隔排布。可以理解的是，对于沿第二方向Y相邻的两个磁性存储结构100而言，四个磁性隧道结110均沿第二方向Y间隔排布，一者的第三晶体管103与另一者的第一晶体管101沿第二方向Y正对，一者的第二晶体管102与另一者的第三晶体管103沿第二方向Y正对，如此，有利于实现在磁性隧道结110沿第一方向X是两侧均布局三个晶体管，分别是第一晶体管101、第二晶体管102和第三晶体管103，从而有利于降低沿第二方向Y相邻的两个磁性存储结构100在磁性存储阵列结构中的布局空间，以提高磁性存储结构100在磁性存储阵列结构中的集成密度。
此外，在图1和图3所示的磁性存储阵列结构中，将第一晶体管101、第二晶体管102和第三晶体管103均作为一个个晶体管个体，使得晶体管个体呈现平行四边形阵列排布，可以使磁性存储结构100的排列规整，便于磁性存储阵列结构的制作，也便于后续对多个磁性存储结构100实现统一的控制，同时实现六方最密堆积的形式。而且，可以将沿第二方向Y相邻的两个磁性存储结构100作为一个整体，即图1所示的局部结构，在磁性存储阵列结构中，将上述整体沿第一方向X和第二方向Y间隔排布，有利于进一步提高磁性存储结构100在磁性存储阵列结构中的集成密度。
在另一些实施例中，参考图2和图4，沿第一方向X相邻的两个磁性存储结构100呈中心对称，且两个磁性存储结构100中一者的第三晶体管103与另一者的第三晶体管103沿第二方向Y间隔排布。可以理解的是，对于沿第一方向X相邻的两个磁性存储结构100而言，两个第三晶体管103沿第二方向Y间隔排布，一者的第一晶体管101与另一者的第二晶体管102沿第一方向X正对，一者的第二晶体管102与另一者的第一晶体管101沿第一方向X正对，两者的磁性隧道结110也沿第一方向X正对。如此，有利于实现在磁性隧道结110沿第一方向X是两侧均布局两个晶体管，从而有利于降低沿第一方向X相邻的两个磁性存储结构100在磁性存储阵列结构中的布局空间，以提高磁性存储结构100在磁性存储阵列结构中的集成密度。
此外，在图2和图4所示的磁性存储阵列结构中，将第一晶体管101、第二晶体管102和第三晶体管103均作为一个个晶体管个体，使得晶体管个体呈现矩形阵列排布，可以使磁性存储结构100的排列规整，便于磁性存储阵列结构的制作，也便于后续对多个磁性存储结构100实现统一的控制，同时实现四方最密堆积的形式。而且，可以将沿第一方向X相邻的两个磁性存储结构100作为一个整体，即图2所示的局部结构，在磁性存储阵列结构中，将上述整体沿第一方向X和第二方向Y间隔排布，有利于进一步提高磁性存储结构100在磁性存储阵列结构中的集成密度。
在上述实施例中，参考图1至图4，磁性存储阵列结构还可以包括：沿第一方向X延伸的第一信号线114和第二信号线124，沿第一方向X排布的磁性存储结构100与同一第一信号线114电连接，且与同一第二信号线124电连接。
在一个例子中，参考图3，与沿第一方向X排布的第一晶体管101对应的自旋轨道耦合层140均与同一第一信号线114电连接，与沿第一方向X排布的第二晶体管102对应的自旋轨道耦合层140均与同一第二信号线124电连接。在另一个例子中，参考图4，第一晶体管101和第二晶体管102沿第一方向X上交错排布，沿第一方向X上交错排布的第一晶体管101和第二晶体管102均与同一第一信号线114或者同一第二信号线124电连接。
可以理解的是，沿第一方向X上排布的多个磁性存储结构100可以共用一第一信号线114和一第二信号线124，有利于减少第一信号线114和第二信号线124的控制端口，提高对磁性存储阵列的控制能力。
需要说明的是，参考图1和图2，存储磁性存储阵列结构还包括：第四导电柱147，其中，第四导电柱147位于自旋轨道耦合层140和第一信号线114之间，以实现自旋轨道耦合层140与第一信号线114之间的电连接；或者，第四导电柱147位于自旋轨道耦合层140和第二信号线124之间，以实现自旋轨道耦合层140与第二信号线124之间的电连接。
参考图3和图4，磁性存储阵列结构还可以包括：沿第二方向Y延伸的第一控制线115和第二控制线125，沿第二方向Y排布的磁性存储结构100与同一第一控制线115电连接，且与同一第二控制线125电连接。
在一个例子中，参考图3，位于磁性隧道结110一侧的晶体管的排列顺序为第一晶体管101、第二晶体管102和第三晶体管103，并以此类推，在第二方向Y上交替排布；位于磁性隧道结110另一侧的晶体管的排列顺序为第三晶体管103、第二晶体管102和第一晶体管101，并以此类推，在第二方向Y上交替排布。其中，排列顺序为第一晶体管101、第二晶体管102和第三晶体管103的沿第二方向Y上交替排布的多个晶体管的栅极均与第一控制线115电连接，排列顺序为第三晶体管103、第二晶体管102和第一晶体管101的沿第二方向Y上交替排布的多个晶体管的栅极均与第二控制线125电连接。
在另一个例子中，参考图4，沿第二方向Y上交替排布的第一晶体管101和第二晶体管102均与同一第一控制线115电连接，沿第二方向Y上间隔排布的第三晶体管103均与同一第二控制线125电连接。如此，在第一方向X上相邻且呈中心对称的两个磁性存储结构100的两个第三晶体管103可以共用第二控制线125，有利于进一步减少第二控制线125的控制端口，提高对磁性存储阵列的控制能力。
此外，图3和图4所示的示例中，沿第二方向Y上排布的多个磁性存储结构100可以共用一第一控制线115和一第二控制线125，有利于减少第一控制线115和第二控制线125的控制端口，提高对磁性存储阵列的控制能力。
需要说明的是，为了图示的清晰性，图1和图2中未示意出第一控制线115和第二控制线125。参考图3和图4，第一控制线115与沿第二方向Y上排布的多个栅极接触连接，第二控制线125也与沿第二方向Y上排布的多个栅极接触连接。
在一些实施例中，参考图1至图4，与第一晶体管101电连接的磁性隧道结110为第一磁性隧道结110a，与第二晶体管102电连接的磁性隧道结110为第二磁性隧道结110b；沿第一方向X排布的磁性存储结构100中的第一磁性隧道结110a与同一第一信号线114电连接；沿第一方向X排布的磁性存储结构100中的第二磁性隧道结110b与同一第二信号线124电连接。可以理解的是，第一信号线114用于对第一磁性隧道结110a进行写操作或者读操作，第二信号线124用于对第二磁性隧道结110b进行写操作或者读操作。
在一些实施例中，参考图1和图3，沿第二方向Y上相邻的两个磁性存储结构100分别为第一磁性存储结构100a和第二磁性存储结构100b；同一第一控制线115电连接第一磁性 存储结构100a中的第一晶体管101和第二晶体管102以及第二磁性存储结构100b中的第三晶体管103，以控制上述三个晶体管处于导通状态或关断状态；同一第二控制线125电连接第二磁性存储结构100b中的第一晶体管101和第二晶体管102以及第一磁性存储结构100a中的第三晶体管103，以控制上述三个晶体管处于导通状态或关断状态。
在另一些实施例中，参考图2和图4，同一第一控制线115电连接沿第二方向Y排布的磁性存储结构100中的第一晶体管101和第二晶体管102，以控制第一晶体管101和第二晶体管102处于导通状态或关断状态；沿第一方向X上相邻的两个磁性存储结构100分别为第一磁性存储结构100a和第二磁性存储结构100b；同一第二控制线125电连接第一磁性存储结构100a中的第三晶体管103以及第二磁性存储结构100b中的第三晶体管103，以控制第三晶体管103处于导通状态或关断状态。
在一些实施例中，磁性存储阵列结构还可以包括：第一电连接层116，与沿第二方向Y上排布的多个磁性隧道结110的固定层120接触连接；第二电连接层126，第二电连接层126的一端与第一电连接层116接触连接，另一端与第三晶体管103的源端或漏端接触连接。
需要说明的是，图1至图4中均以第一电连接层116与磁性存储结构100一一对应为示例，在实际应用中，第一电连接层116可以沿第二方向Y延伸，且一第一电连接层116可以与沿第二方向Y上排布的多个磁性存储结构100对应，即沿第二方向Y上排布的多个磁性存储结构100可以共用一个第一电连接层116。
以下结构图1至图4，对磁性存储结构100进行读操作和写操作的原理进行详细说明。
对于第一磁性存储结构100a而言，第一晶体管101的第一栅极131和第二晶体管102的第二栅极132连接第一控制线115，使第一控制线115控制第一晶体管101和第二晶体管102的导通或关断，第三晶体管103的第三栅极133连接第二控制线125，使第二控制线125控制第三晶体管103的导通或关断；第一晶体管101的源端或漏端电连接与第一磁性隧道结110a对应的自旋轨道耦合层140，且第一磁性隧道结110a与第一信号线114对应，第二晶体管102的源端或漏端电连接与第二磁性隧道结110b对应的自旋轨道耦合层140，且第二磁性隧道结110b与第二信号线124对应。如此，可以通过第一晶体管101和第一信号线114控制对第一磁性隧道结110a的写入，通过第二晶体管102和第二信号线124控制对第二磁性隧道结110b的写入，通过第三晶体管103和第一信号线114控制对第一磁性隧道结110a的读取，通过第三晶体管103和第二信号线124控制对第二磁性隧道结110b的读取，从而区分读写路径，以便于对读取和写入进行单独的优化。
在一些实施例中，磁性隧道结110的磁化结构方向与自旋轨道耦合层140的表面垂直，自由层130位于自旋轨道耦合层140的表面。在另一些实施例中，磁性隧道结110的磁化结构方向与自旋轨道耦合层140的表面平行，自由层130位于自旋轨道耦合层140的表面。
例如，当磁性隧道结110的磁化结构方向垂直于自旋轨道耦合层140的表面时，自由 层130内的磁场方向可以转化为垂直并朝向自旋轨道耦合层140表面的方向，或者转化为垂直并远离自旋轨道耦合层140表面的方向；固定层120内的磁场方向可以固定为垂直并远离自旋轨道耦合层140表面的方向，或者固定为垂直并朝向自旋轨道耦合层140表面的方向。当自由层130受到自旋轨道耦合层140中自旋轨道交互作用发生磁场方向的转换时，自由层130内的磁场方向转换为与固定层120的磁场方向相同，则磁性隧道结110呈现低阻态；当自由层130内的磁场方向转换为与固定层120的磁场方向相反，则磁性隧道结110呈现高阻态。另外，磁性隧道结110的磁化结构方向也可以与自旋轨道耦合层140的表面平行，即磁性隧道结110的固定层120内的磁场方向与自旋轨道耦合层140的表面平行，自由层130内的磁场可以与固定层120的磁场方向相同或者相反，相应的自由层130与固定层120的磁场方向决定磁性隧道结110的阻态大小。可以理解的是，磁性隧道结110的磁化结构方向可以根据实际情况进行选择制定，本实施例不对磁性隧道结110的磁化结构方向做过度的限定。
综上所述，磁性存储阵列结构中的磁性存储结构100在单位空间内存储的数据量较高，且能够降低存储和读取2字节数据所需的晶体管的数量，从而有利于提高磁性存储阵列结构在单位空间内存储的数据量，以及降低存储和读取一定大小数据所需的晶体管的数量。此外，采用图3或图4所示的磁性存储结构100在磁性存储阵列结构中的排布方式，有利于提高磁性存储结构100在磁性存储阵列结构中的集成密度，以及降低所需使用的第一信号线114、第二信号线124、第一控制线115和第二控制线125的数量，以减少第一信号线114、第二信号线124、第一控制线115和第二控制线125的控制端口，提高对磁性存储阵列的控制能力。
本公开又一实施例还提供一种存储器，存储器的阵列结构基于本公开另一实施例所述的磁性存储阵列结构设置。需要说明的是，与前述实施例相同或相应的部分在此不再赘述。
可以理解的时，存储器的阵列结构基于本公开另一实施例所述的磁性存储阵列结构设置，则有利于提高存储器在单位空间内存储的数据量，提高存储器对磁性存储阵列的控制能力，以及提高磁性存储阵列结构在存储器中的集成密度。
具体地，存储器可以是基于半导体装置或组件的存储单元或装置。例如，存储器可以是易失性存储器，例如动态随机存取存储器DRAM或者可以是非易失性存储器，例如相变随机存取存储器PRAM、磁性随机存取存储器MRAM、电阻式随机存取存储器RRAM等。
本公开再一实施例还提供一种磁性存储阵列结构的读写控制方法，用于控制前述实施例提供的磁性存储阵列结构或者磁性存储阵列结构中的磁性存储结构。以下将结合图1至图5对本公开再一实施例提供的磁性存储阵列结构的读写控制方法进行详细说明。需要说明的是，与前述实施例相同或相应的部分在此不再赘述。
图5为本公开再一实施例提供的磁性存储阵列结构的读写控制方法的一种流程图。
参考图5，磁性存储阵列结构的读写控制方法包括如下步骤：
S101：控制第一晶体管101和第二晶体管102中的一者处于导通状态；控制流经自旋轨道耦合层140的电流以设置两个磁性隧道结110中的一者的状态为高阻态或低阻态，以实现对磁性隧道结110的写操作，其中，实现写操作的磁性隧道结110与处于导通状态的第一晶体管101或者处于导通状态的第二晶体管102对应。
S102：控制第三晶体管103处于导通状态；读取流经两个磁性隧道结110中一者的电流的大小以判断磁性隧道结110为高阻态还是低阻态，以实现对磁性隧道结110的读操作。
在一些实施例中，与第一晶体管101电连接的磁性隧道结110为第一磁性隧道结110a，与第一磁性隧道结110a对应的自旋轨道耦合层140为第一自旋轨道耦合层140a，与第二晶体管102电连接的磁性隧道结110为第二磁性隧道结110b，与第二磁性隧道结110b对应的自旋轨道耦合层140为第二自旋轨道耦合层140b。
如此，实现读操作和写操作的步骤可以包括：结合参考图1至图4，通过第一信号线114控制流经第一自旋轨道耦合层140a的电流以设置第一磁性隧道结110a的状态为高阻态或低阻态；通过第二信号线124控制流经第二自旋轨道耦合层140b的电流以设置第二磁性隧道结110b的状态为高阻态或低阻态；通过第一控制线115和第二控制线125控制第一晶体管101、第二晶体管102以及第三晶体管103的导通或关闭。
在一些实施例中，结合参考图1和图3，控制部分磁性存储结构100进行写操作的步骤可以包括以下两种方式：
在一些实施例中，选通第一信号线114和第一控制线115，以导通第一晶体管101，以及控制流经第一自旋轨道耦合层140a的电流以设置第一磁性隧道结110a的状态为高阻态或低阻态，以实现对第一磁性隧道结110a的写操作。
在一个例子中，当需要对第一磁性存储结构100a中的第一磁性隧道结110a进行写操作时，则在与第一磁性存储结构100a对应的第一控制线115上施加导通电压，即选通第一控制线115，使第一晶体管101导通，再向第一信号线114施加电压，即选通第一信号线114，则此时电流经过第一信号线114、第一自旋轨道耦合层140a和第一晶体管101。可以理解的是，在第一信号线114中通入正写入电压或者负写入电压，使流经第一自旋轨道耦合层140a的电流产生自旋轨道交互作用，从而向自由层130中注入自旋电流并令自由层130内的磁矩快速地翻转，使得第一磁性隧道结110a的状态为高阻态或低阻态。
在另一些实施例中，选通第二信号线124和第一控制线115，以导通第二晶体管102，以及控制流经第二自旋轨道耦合层140b的电流以设置第二磁性隧道结110b的状态为高阻态或低阻态，以实现对第二磁性隧道结110b的写操作。
在一个例子中，当需要对第一磁性存储结构100a中的第二磁性隧道结110b进行写操作时，则在与第二磁性隧道结110b对应的第一控制线115上施加导通电压，即选通第一控制线115，使第二晶体管102导通，再向第二信号线124施加电压，即选通第二信号线124，则 此时电流经过第二信号线124、第二自旋轨道耦合层140b和第二晶体管102。可以理解的是，在第二信号线124中通入正写入电压或者负写入电压，使流经第二自旋轨道耦合层140b的电流产生自旋轨道交互作用，从而向自由层130中注入自旋电流并令自由层130内的磁矩快速地翻转，使得第二磁性隧道结110b的状态为高阻态或低阻态。
在一些实施例中，控制部分磁性存储结构100进行读操作的步骤可以包括以下两种方式：
在一些实施例中，选通第一信号线114和第二控制线125，以导通第三晶体管103，以及读取流经第一磁性隧道结110a的电流的大小以判断第一磁性隧道结110a为高阻态还是低阻态，以实现对第一磁性隧道结110a的读操作。
在一个例子中，当需要对第一磁性存储结构100a中的第一磁性隧道结110a中存储的数据进行读取时，则在与第一磁性存储结构100a对应的第二控制线125上施加导通电压，即选通第二控制线125，使第三晶体管103导通，再选通第一信号线114，使得电流可以经过第一信号线114、第一磁性隧道结110a、第一电连接层116、第二电连接层126和第三晶体管103。如此，通过第一信号线114和第三晶体管103远离第二电连接层126的一端可以检测第一磁性隧道结110a电阻的高低，若第一磁性隧道结110a呈现高阻态，则所存数据为“1”；若第一磁性隧道结110a呈现低组态，则所存数据是“0”。
在另一些实施例中，控制部分磁性存储结构100进行读操作的步骤可以包括：选通第二信号线124和第二控制线125，以导通第三晶体管103，以及读取流经第二磁性隧道结110b的电流的大小以判断第二磁性隧道结110b为高阻态还是低阻态，以实现对第二磁性隧道结110b的读操作。
在一个例子中，当需要对第二磁性存储结构100b中的第二磁性隧道结110b中存储的数据进行读取时，则在与第二磁性存储结构100b对应的第二控制线125上施加导通电压，即选通第二控制线125，使第三晶体管103导通，再选通第二信号线124，使得电流可以经过第二信号线124、第二磁性隧道结110b、第一电连接层116、第二电连接层126和第三晶体管103。如此，通过第二信号线124和第三晶体管103远离第二电连接层126的一端可以检测第二磁性隧道结110b电阻的高低，若第二磁性隧道结110b呈现高阻态，则所存数据为“1”；若第二磁性隧道结110b呈现低组态，则所存数据是“0”。
综上所述，本公开再一实施例提供的磁性存储阵列结构的读写控制方法中，可以利用三个晶体管和两个磁性隧道结110实现2字节数据的存储和读取，有利于提高磁性存储结构100和/或磁性存储阵列结构在单位空间内存储的数据量，以及降低存储和读取一定大小数据所需的晶体管的数量；此外，有利于降低所需使用的第一信号线114、第二信号线124、第一控制线115和第二控制线125的数量，以减少第一信号线114、第二信号线124、第一控制线115和第二控制线125的控制端口，降低对磁性存储阵列结构的读写控制复杂程度。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开实施例的精神和范围。任何本领域技术人员，在不脱离本公开实施例的精神和范围内，均可作各自更动与修改，因此本公开实施例的保护范围应当以权利要求限定的范围为准。

Claims (20)

  1. 一种磁性存储结构，包括：
    两个磁性隧道结，所述磁性隧道结包括固定层和自由层；
    与所述磁性隧道结一一对应的自旋轨道耦合层，所述自旋轨道耦合层位于所述自由层远离所述固定层的一侧，
    第一晶体管和第二晶体管，一所述自旋轨道耦合层与所述第一晶体管的源端或漏端电连接，另一所述自旋轨道耦合层与所述第二晶体管的源端或漏端电连接；
    第三晶体管，所述第三晶体管的源端或漏端与两个所述磁性隧道结中的所述固定层均电连接。
  2. 如权利要求1所述的磁性存储结构，其中，所述第一晶体管、所述第二晶体管和所述第三晶体管均为垂直的全环绕栅极晶体管结构。
  3. 如权利要求1或2所述的磁性存储结构，其中，所述第一晶体管与所述第二晶体管的排布方向、所述第一晶体管与所述第三晶体管的排布方向、所述第二晶体管与所述第三晶体管的排布方向两两相交。
  4. 如权利要求3所述的磁性存储结构，其中，所述第一晶体管和所述第三晶体管沿第一方向排布，所述第一晶体管与所述第二晶体管沿第二方向排布，所述第一方向和所述第二方向垂直。
  5. 如权利要求1或2所述的磁性存储结构，其中，与所述第一晶体管电连接的所述磁性隧道结与所述第一晶体管沿第一方向间隔排布，与所述第二晶体管电连接的所述磁性隧道结与所述第二晶体管沿第一方向间隔排布。
  6. 如权利要求1或2所述的磁性存储结构，其中，所述磁性隧道结位于所述第一晶体管和所述第三晶体管之间。
  7. 如权利要求1或2所述的磁性存储结构，其中，所述自旋轨道耦合层的材料为铂、钽、钨、铱、金和钛中的至少一种。
  8. 如权利要求1或2所述的磁性存储结构，其中，所述自由层的材料和所述固定层的材料均包括钴铁硼、钴或镍铁中的至少一种。
  9. 一种磁性存储阵列结构，包括多个如权利要求1至8任一项所述的磁性存储结构，其特征在于，
    至少两个所述磁性存储结构沿第一方向间隔排布；
    至少两个所述磁性存储结构沿第二方向间隔排布，其中，沿所述第二方向相邻的两个所述磁性存储结构呈中心对称，且两个所述磁性存储结构中一者的所述第三晶体管与另一 者的所述第一晶体管沿所述第二方向间隔排布，或者，沿所述第一方向相邻的两个所述磁性存储结构呈中心对称，且两个所述磁性存储结构中一者的所述第三晶体管与另一者的所述第三晶体管沿所述第二方向间隔排布；
    所述磁性存储阵列结构还包括：
    沿所述第一方向延伸的第一信号线和第二信号线，沿所述第一方向排布的所述磁性存储结构与同一所述第一信号线电连接，且与同一所述第二信号线电连接；
    沿所述第二方向延伸的第一控制线和第二控制线，沿所述第二方向排布的所述磁性存储结构与同一所述第一控制线电连接，且与同一所述第二控制线电连接。
  10. 如权利要求9所述的磁性存储阵列结构，其中，与所述第一晶体管电连接的所述磁性隧道结为第一磁性隧道结，与所述第二晶体管电连接的所述磁性隧道结为第二磁性隧道结；
    沿所述第一方向排布的所述磁性存储结构中的所述第一磁性隧道结与同一所述第一信号线电连接；
    沿所述第一方向排布的所述磁性存储结构中的所述第二磁性隧道结与同一所述第二信号线电连接。
  11. 如权利要求9所述的磁性存储阵列结构，其中，沿所述第二方向上相邻的两个所述磁性存储结构分别为第一磁性存储结构和第二磁性存储结构；
    同一所述第一控制线电连接所述第一磁性存储结构中的所述第一晶体管和所述第二晶体管以及所述第二磁性存储结构中的所述第三晶体管；
    同一所述第二控制线电连接所述第二磁性存储结构中的所述第一晶体管和所述第二晶体管以及所述第一磁性存储结构中的所述第三晶体管。
  12. 如权利要求9所述的磁性存储阵列结构，其中，
    同一所述第一控制线电连接沿所述第二方向排布的所述磁性存储结构中的所述第一晶体管和所述第二晶体管；
    沿所述第一方向上相邻的两个所述磁性存储结构分别为第一磁性存储结构和第二磁性存储结构；
    同一所述第二控制线电连接所述第一磁性存储结构中的所述第三晶体管以及所述第二磁性存储结构中的所述第三晶体管。
  13. 如权利要求9所述的磁性存储阵列结构，还包括：
    第一电连接层，与沿所述第二方向上排布的多个所述磁性隧道结的所述固定层接触连接；
    第二电连接层，所述第二电连接层的一端与所述第一电连接层接触连接，另一端与所述 第三晶体管的源端或漏端接触连接。
  14. 如权利要求9所述的磁性存储阵列结构，其中，所述磁性隧道结的磁化结构方向与所述自旋轨道耦合层的表面垂直，所述自由层位于所述自旋轨道耦合层的表面。
  15. 如权利要求9所述的磁性存储阵列结构，其中，所述磁性隧道结的磁化结构方向与所述自旋轨道耦合层的表面平行，所述自由层位于所述自旋轨道耦合层的表面。
  16. 一种存储器，所述存储器的阵列结构基于权利要求9至15任一项所述的磁性存储阵列结构设置。
  17. 一种磁性存储阵列结构的读写控制方法，包括：
    控制第一晶体管和第二晶体管中的一者处于导通状态；
    控制流经自旋轨道耦合层的电流以设置两个所述磁性隧道结中的一者的状态为高阻态或低阻态，以实现对所述磁性隧道结的写操作，其中，实现所述写操作的所述磁性隧道结与处于导通状态的所述第一晶体管或者处于导通状态的所述第二晶体管对应；
    控制第三晶体管处于导通状态；读取流经两个所述磁性隧道结中一者的电流的大小以判断所述磁性隧道结为高阻态还是低阻态，以实现对所述磁性隧道结的读操作。
  18. 如权利要求17所述的读写控制方法，其中，与所述第一晶体管电连接的磁性隧道结为第一磁性隧道结，与所述第一磁性隧道结对应的所述自旋轨道耦合层为第一自旋轨道耦合层，与所述第二晶体管电连接的磁性隧道结为第二磁性隧道结，与所述第二磁性隧道结对应的所述自旋轨道耦合层为第二自旋轨道耦合层；实现所述读操作和所述写操作的步骤包括：
    通过第一信号线控制流经所述第一自旋轨道耦合层的电流以设置所述第一磁性隧道结的状态为高阻态或低阻态；
    通过第二信号线控制流经所述第二自旋轨道耦合层的电流以设置所述第二磁性隧道结的状态为高阻态或低阻态；
    通过第一控制线和第二控制线控制所述第一晶体管、所述第二晶体管以及所述第三晶体管的导通或关闭。
  19. 如权利要求18所述的读写控制方法，其中，控制部分所述磁性存储结构进行所述写操作的步骤包括：
    选通所述第一信号线和所述第一控制线，以导通所述第一晶体管，以及控制流经所述第一自旋轨道耦合层的电流以设置所述第一磁性隧道结的状态为高阻态或低阻态，以实现对所述第一磁性隧道结的所述写操作；
    或者，选通所述第二信号线和所述第一控制线，以导通所述第二晶体管，以及控制流经 所述第二自旋轨道耦合层的电流以设置所述第二磁性隧道结的状态为高阻态或低阻态，以实现对所述第二磁性隧道结的所述写操作。
  20. 如权利要求18所述的读写控制方法，其中，控制部分所述磁性存储结构进行所述读操作的步骤包括：
    选通所述第一信号线和所述第二控制线，以导通所述第三晶体管，以及读取流经所述第一磁性隧道结的电流的大小以判断所述第一磁性隧道结为高阻态还是低阻态，以实现对所述第一磁性隧道结的所述读操作；
    或者，选通所述第二信号线和所述第二控制线，以导通所述第三晶体管，以及读取流经所述第二磁性隧道结的电流的大小以判断所述第二磁性隧道结为高阻态还是低阻态，以实现对所述第二磁性隧道结的所述读操作。
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