WO2024108879A1 - 存储器、存储器的读写方法和制造方法 - Google Patents

存储器、存储器的读写方法和制造方法 Download PDF

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Publication number
WO2024108879A1
WO2024108879A1 PCT/CN2023/088763 CN2023088763W WO2024108879A1 WO 2024108879 A1 WO2024108879 A1 WO 2024108879A1 CN 2023088763 W CN2023088763 W CN 2023088763W WO 2024108879 A1 WO2024108879 A1 WO 2024108879A1
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Prior art keywords
transistor
memory
magnetic tunnel
semiconductor column
tunnel junction
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PCT/CN2023/088763
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English (en)
French (fr)
Inventor
邓杰芳
刘翔
李德斌
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长鑫存储技术有限公司
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Publication of WO2024108879A1 publication Critical patent/WO2024108879A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices

Definitions

  • the embodiments of the present disclosure belong to the field of semiconductors, and specifically relate to a memory, a reading and writing method of the memory, and a manufacturing method.
  • MRAM Magnetic random access memory
  • STT-MRAM Spin transfer torque magnetic random access memory
  • SOT-MRAM spin orbit torque-magnetic random access memory
  • STT-MRAM can use current to directly pass through the magnetic tunnel junction to rewrite the magnetization direction.
  • SOT-MRAM also includes an electrode layer, which can provide a strong spin-orbit effect, thereby improving the magnetic moment reversal efficiency of the magnetic tunnel junction.
  • the embodiments of the present disclosure provide a memory, a method for reading and writing the memory, and a method for manufacturing the memory, which are at least helpful in reducing the size of the memory.
  • a memory comprising: a substrate having a transistor group, an electrode layer, a magnetic tunnel The transistor group, the electrode layer, and the magnetic tunnel junction are stacked in a direction perpendicular to the substrate; the transistor group includes a first semiconductor column and a second semiconductor column arranged at intervals, and the first semiconductor column and the second semiconductor column both have a drain region, a channel region, and a source region arranged in a direction perpendicular to the substrate; the transistor group also includes a word line, and the word line is connected to the channel region of the first semiconductor column and the second semiconductor column; the first semiconductor column and the word line constitute a first transistor; the second semiconductor column and the word line constitute a second transistor; the electrode layer is connected to the source region of the first semiconductor column and the second semiconductor column.
  • an embodiment of the present disclosure further provides a method for reading and writing a memory, and this method can perform read and write operations on the aforementioned memory.
  • Performing a write operation on the memory includes: providing an enable signal to the word line to turn on the first transistor and the second transistor; providing a first current, the first current flowing through the first transistor, the electrode layer and the second transistor.
  • Performing a read operation on the memory includes: providing an enable signal to the word line to turn on the first transistor and the second transistor; providing a second current, the second current flowing through the magnetic tunnel junction and the electrode layer.
  • the embodiments of the present disclosure further provide a method for manufacturing a memory, the manufacturing method comprising: providing a substrate, forming a transistor group, an electrode layer, and a magnetic tunnel junction on the substrate, the transistor group, the electrode layer, and the magnetic tunnel junction are stacked in a direction perpendicular to the substrate; forming the transistor group comprises: forming a first semiconductor column and a second semiconductor column arranged at intervals, the first semiconductor column and the second semiconductor column both having a drain region, a channel region, and a source region arranged in a direction perpendicular to the substrate; forming the transistor group also comprises: forming a word line, the word line is connected to the channel region of the first semiconductor column and the second semiconductor column; the first semiconductor column and the word line constitute a first transistor; the second semiconductor column and the word line constitute a second transistor; the electrode layer is connected to the source region of the first semiconductor column and the second semiconductor column.
  • the drain region, the channel region and the source region are stacked on the substrate, so the first transistor and the second transistor are vertical transistors.
  • the vertical transistor occupies a smaller area on the substrate than the planar transistor.
  • the word line connects the first semiconductor column and the second semiconductor column, that is, the two transistors share a word line. Fewer word lines are needed, which is conducive to reducing the size of the memory.
  • FIG1 shows a partial stereoscopic view of a memory provided by an embodiment of the present disclosure
  • FIG2 shows a top view of a memory provided by an embodiment of the present disclosure
  • FIG3 shows a partial stereoscopic view of another memory provided by an embodiment of the present disclosure
  • FIG4 shows an equivalent circuit diagram of a storage unit of a memory provided by an embodiment of the present disclosure
  • 5-6 respectively show two equivalent circuit diagrams of a storage unit of a memory provided by an embodiment of the present disclosure during a write operation
  • FIG. 7 shows an equivalent circuit diagram of a storage unit of a memory provided by an embodiment of the present disclosure during a read operation.
  • SOT-MRAM requires an additional electrode layer, so that the electrode layer and the magnetic tunnel junction together produce three terminals, and at least two transistors are required to control it, so its size is difficult to reduce.
  • the disclosed embodiment provides a memory, including: a first semiconductor column and a second semiconductor column, both of which have a drain region, a channel region and a source region arranged in a direction perpendicular to a substrate; a word line is connected to the channel region of the first semiconductor column and the second semiconductor column.
  • two transistors share a word line, thereby reducing the number of word lines and reducing the size of the memory; in addition, compared with a planar transistor, a vertical transistor occupies a smaller area on the substrate. Therefore, the size of the memory is smaller.
  • an embodiment of the present disclosure provides a memory, which includes: a substrate 10, on which a transistor group T, an electrode layer 30, and a magnetic tunnel junction MTJ are provided, wherein the transistor group T, the electrode layer 30, and the magnetic tunnel junction MTJ are stacked in a direction perpendicular to the substrate 10;
  • the transistor group T includes a first semiconductor column 21 and a second semiconductor column 22 arranged at intervals, and the first semiconductor column 21 and the second semiconductor column 22 both have a drain region D, a channel region C, and a source region S arranged in a direction perpendicular to the substrate 10;
  • the transistor group T also includes a word line WL, which is connected to the channel region C of the first semiconductor column 21 and the second semiconductor column 22;
  • the first semiconductor column 21 and the word line WL constitute a first transistor T1;
  • the second semiconductor column 22 and the word line WL constitute a second transistor T2;
  • the electrode layer 30 is connected to the source region S of the first semiconductor column 21 and the second semiconductor column 22.
  • both the first transistor T1 and the second transistor T2 are vertical transistors. Compared with planar transistors, vertical transistors occupy a smaller area on the substrate 10, which is conducive to improving the arrangement density and thus improving the integration of the memory.
  • the two being connected to the same word line WL can reduce the number of word lines WL, thereby reducing the size of the memory and improving the integration of the memory.
  • the drain region D, channel region C and source region S of the vertical transistor are arranged in a direction perpendicular to the substrate 10, that is, the channel region C of the vertical transistor is at a different height position from the drain region D and the source region S. Therefore, when the same word line WL is used to connect the channel regions C of two vertical transistors, since the word line WL is easier to avoid the drain region D and the source region S, its routing setting will be simpler, which is conducive to reducing the space occupied by the word line WL, thereby improving the integration of the memory.
  • the drain region D, channel region C and source region S of the planar transistor are arranged side by side on the substrate 10, that is, the three are usually located in the same layer.
  • the routing of the word line WL needs to be more complexly designed to avoid the drain region D and the source region S, and the space occupied by the word line WL will be larger.
  • the electrode layer 30 is connected to two transistors, and the structure is more symmetrical. Compared with the electrode layer 30 connected to a transistor and a signal line, the electrode layer 30 is connected to the transistors to avoid the negative feedback effect, that is, to avoid the phenomenon of asymmetric write current, thereby improving the reliability of the write operation.
  • the memory has a first direction X, a second direction Y and a third direction Z, wherein the first direction X and the second direction Y may be parallel to the upper surface of the substrate 10, and the third direction Z may be perpendicular to the upper surface of the substrate 10.
  • the first direction X and the second direction Y may be perpendicular to each other, or close to a perpendicular relationship.
  • the substrate 10 may be a silicon substrate or a germanium substrate, and the material of the substrate 10 may be the same as the material of the first semiconductor column 21 and the material of the second semiconductor column 22.
  • the transistor group T, the electrode layer 30, and the magnetic tunnel junction MTJ are sequentially stacked on the substrate 10.
  • the magnetic tunnel junction MTJ and the transistor group T may also be arranged on the same side of the electrode layer 30.
  • the transistor group T, the electrode layer 30, and the magnetic tunnel junction MTJ are sequentially stacked on the substrate 10, which is beneficial to reducing the total area occupied by the three on the upper surface of the substrate 10.
  • the magnetic tunnel junction MTJ and the transistor group T are arranged on the same side of the electrode layer 30, the magnetic tunnel junction MTJ needs to be located between the first semiconductor column 21 and the second semiconductor column 22, then the spacing between the first semiconductor column 21 and the second semiconductor column 22 may be increased accordingly to avoid electrical connection between the semiconductor column and the magnetic tunnel junction MTJ, thereby increasing the total area occupied by the two on the upper surface of the substrate 1.
  • the transistor group T is closer to the substrate 10 than the magnetic tunnel junction MTJ, and a single crystal layer can be grown on the substrate 10 using an epitaxial growth process to serve as the first semiconductor column 21 and the second semiconductor column 22 of the transistor group T, thereby reducing the difficulty of producing the single crystal layer and simplifying the production process.
  • the transistor group T and the magnetic tunnel junction MTJ may be both located on the side of the electrode layer 30 facing the substrate 10; or, the transistor group T and the magnetic tunnel junction MTJ may be both located on the side of the electrode layer 30 away from the substrate 10. In other embodiments, the transistor group T may also be located on the side of the electrode layer 30 away from the substrate 10, and the magnetic tunnel junction MTJ may be located on the side of the electrode layer 30 facing the substrate 10, that is, the magnetic tunnel junction MTJ, the electrode layer 30, and the transistor group T are stacked on the substrate 10 in sequence.
  • the first semiconductor pillar 21 and the second semiconductor pillar 22 both extend in the third direction Z, and are arranged in the second direction Y.
  • the first semiconductor pillar 21 and the second semiconductor pillar 22 have the same height in the third direction Z.
  • the drain region D may have
  • the doping ion type of the channel region C may be the same as that of the source region S, for example, both of which are N-type, and the doping ion type of the channel region C may be opposite to that of the source region S and the drain region D, for example, the doping ion type of the channel region C is P-type.
  • the first semiconductor column 21 and the second semiconductor column 22 may both be an integrated structure.
  • the first semiconductor column 21 can be formed by one process step
  • the second semiconductor column 22 can be formed by one process step, thereby improving production efficiency.
  • the first semiconductor column 21 and the second semiconductor column 22 are formed by one epitaxial growth process.
  • the first semiconductor column 21 may not be an integrated structure
  • the second semiconductor column 22 may not be an integrated structure.
  • different process steps are used successively to form the source region S, the channel region C, and the drain region D.
  • the extension direction of the word line WL may be a second direction Y, that is, the extension direction of the word line WL is parallel to the arrangement direction of the first semiconductor column 21 and the second semiconductor column 22.
  • the word line WL serves as the gate of the first transistor T1 and the second transistor T2, and is used to control the switching state of the first transistor T1 and the second transistor T2. Since the two transistors share the same word line WL, the control signals of the two transistors are the same, and the process of controlling the transistors can be simplified, which is beneficial to improve the operation rate of the memory and reduce energy consumption.
  • the material of the word line WL may be tungsten, molybdenum, gold, cobalt or other metals to reduce the resistance of the word line WL.
  • the word line WL may include a gate portion and a connecting portion, wherein the gate portion is connected to the channel region C of the first semiconductor column 21 and the second semiconductor column 22 , the connecting portion is located between adjacent gate portions, and the connecting portion is opposite to the gap between the first semiconductor column 21 and the second semiconductor column 22 .
  • the word line WL is connected to the channel region C of the first semiconductor column 21 and the second semiconductor column 22” does not mean that the word line WL is in direct contact with the channel region C, but means that the word line WL can be located on the sidewall of the channel region C. This is because there is a gate dielectric layer (not shown in the figure) between the word line WL and the channel region C.
  • the word line WL surrounds the channel region C of the first semiconductor column 21 and the channel region C of the second semiconductor column 22, that is, the word line WL covers the middle sidewalls of the first semiconductor column 21 and the second semiconductor column 22. That is, the first transistor T1 and the second transistor T2 are both vertical-gate-all-around (VGAA) structures.
  • the word line WL of the vertical all-around gate structure is connected to the first semiconductor column 21 and the second semiconductor column 22.
  • the contact area between the conductor pillar 21 and the second semiconductor pillar 22 is large, which is beneficial to improving the gate control capability of the transistor and further improving the electrical performance of the memory.
  • the word line WL when the word line WL surrounds the first semiconductor pillar 21 and the second semiconductor pillar 22 , the word line WL can also fully utilize the space between the two semiconductor pillars, thereby improving the arrangement density of each structure and facilitating reducing the resistance of the word line WL.
  • the word line WL may also be connected to only part of the sidewalls of the first semiconductor pillar 21 and the second semiconductor pillar 22.
  • the first semiconductor pillar 21 and the second semiconductor pillar 22 may be quadrangular prisms, and the word line WL may contact one sidewall of the first semiconductor pillar 21 and one sidewall of the second semiconductor pillar 22.
  • the word line WL may also contact two or three sidewalls of the first semiconductor pillar 21 and two or three sidewalls of the second semiconductor pillar 22.
  • the magnetic tunnel junction MTJ Magnetic Tunnel Junction
  • the magnetic tunnel junction MTJ includes a stacked free layer FL (free layer), a non-magnetic isolation layer 5 and a pinned layer PL (pinned layer), and the free layer FL is connected to the electrode layer 30.
  • the magnetization direction of the pinned layer PL is constant, while the magnetization direction of the free layer FL can be changed.
  • the magnetization directions of the pinned layer PL and the free layer FL are consistent, it is called a "parallel state”, and the tunnel magnetoresistance of the magnetic tunnel junction MTJ is low; when the magnetization directions are inconsistent, it is called an "anti-parallel state", and the tunnel magnetoresistance of the magnetic tunnel junction MTJ is low.
  • the two resistance states can represent binary data "0" and "1" for data storage. Therefore, data writing can be achieved by switching the magnetization direction of the free layer FL, and the reading process can measure the current passing through the magnetic tunnel junction MTJ to obtain the magnetoresistance.
  • the material of the non-magnetic isolation layer 5 may be an oxide, such as magnesium oxide.
  • the materials of the free layer FL and the pinned layer PL may be typical transition metal ferromagnets such as iron, cobalt, and nickel.
  • the current flowing through the electrode layer 30 can induce a torque effect to drive the magnetization reversal of the free layer FL.
  • the cause of the torque may be the Rashba Effect, the Spin Hall Effect (SHE), or both.
  • passing a current through the electrode layer 30 can generate a spin current and inject it into the free layer FL, using the spin-orbit torque to disturb the magnetization direction of the free layer FL, and combining a variety of methods to make the magnetization direction deterministically flipped. This will be described in detail later in conjunction with the memory read and write method.
  • the first semiconductor pillar 21 and the first semiconductor pillar 21 are respectively connected to the opposite ends of the electrode layer 30 That is, the first transistor T1 and the second transistor T2 control the direction of the current flowing into the electrode layer 30, so that the current flows from one end of the electrode layer 30 to the other end.
  • the first semiconductor pillar 21 and the second semiconductor pillar 22 are connected to the bottom surface of the electrode layer 30, and the two are respectively located on opposite sides of the bottom surface of the electrode layer 30.
  • the electrode layer 30 includes a heavy metal material.
  • the heavy metal may be tungsten, platinum, or tantalum.
  • the heavy metal material has a high spin-orbit coupling effect.
  • the heavy metal layer is easy to match the semiconductor back-end process.
  • the material of the electrode layer 30 may also include topological insulators, such as bismuth and antimony sulfides.
  • the material of the electrode layer 30 may also include antiferromagnetic metals, such as iridium-manganese alloys, platinum-manganese alloys, and the like.
  • the electrode layer 30 may be a single-layer structure, such as including only a heavy metal layer; in other embodiments, the electrode layer 30 may also be a multi-layer composite structure, such as including a heavy metal layer and a ferromagnetic layer.
  • the magnetic tunnel junction MTJ is a parallel magnetic tunnel junction, and the direction of its magnetic moment is parallel to the upper surface of the substrate 10.
  • the direction of its magnetic moment is perpendicular to the upper surface of the substrate 10.
  • the magnetic moment of the perpendicular magnetic tunnel junction to flip current needs to be passed to both the electrode layer 30 and the magnetic tunnel junction MTJ. Under the action of the two currents, the magnetic moment can be reversed in a directional manner. This is because the magnetic damping coefficient of the parallel magnetic tunnel junction is usually smaller than the magnetic damping coefficient of the perpendicular magnetic tunnel junction. Therefore, under the superposition of the two currents, the difficulty of flipping the perpendicular magnetic tunnel junction can be reduced.
  • the memory further includes: a first bit line BL1 and a second bit line BL2 arranged at intervals; a first semiconductor column 21 is located on the upper surface of the first bit line BL1, and a second semiconductor column 22 is located on the upper surface of the second bit line BL2.
  • the word line WL is insulated from the first bit line BL1 and the second bit line BL2.
  • the drain region D of the first semiconductor column 21 is connected to the first bit line BL1
  • the drain region D of the second semiconductor column 22 is connected to the second bit line BL2.
  • the first bit line BL1 and the second bit line BL2 extend in the same direction.
  • the extension direction of the two is the first direction X
  • the extension direction of the two is perpendicular to the extension direction of the word line WL. That is, the first direction X is perpendicular to the second direction Y.
  • the extension direction of the first bit line BL1 and the second bit line BL2 may not be completely perpendicular to the extension direction of the word line WL, but is close to a perpendicular relationship. In this way, the area can be saved at the edge of the storage area of the memory.
  • the memory also includes: a source line SL, and the source line SL is located on the upper surface of the magnetic tunnel junction MTJ.
  • the source line SL can provide current to the magnetic tunnel junction MTJ to read or store data.
  • the extension direction of the source line SL can be perpendicular to the arrangement direction of the first semiconductor column 21 and the second semiconductor column 22, and the extension direction of the source line SL can also be parallel to the extension direction of the first bit line BL1 and the extension direction of the second bit line BL2. That is, the extension direction of the source line SL can be the first direction X, and is perpendicular to the second direction Y.
  • first transistor T1, the second transistor T2, the electrode layer 30, and the magnetic tunnel junction MTJ can constitute a basic memory cell 4, and the first transistor T1 and the second transistor T2 of the same memory cell 4 share the same word line WL.
  • a plurality of first semiconductor pillars 21 are arranged in an array on a substrate 10, and a plurality of second semiconductor pillars 22 are arranged in an array on a substrate 10.
  • There are a plurality of word lines WL the plurality of word lines WL are parallel to each other, and the plurality of word lines WL are arranged along a first direction X.
  • One word line WL can be used as a gate of a plurality of memory cells 4, that is, the same word line WL can connect a plurality of first semiconductor pillars 21 and a plurality of second semiconductor pillars 22, and the plurality of first semiconductor pillars 21 and a plurality of second semiconductor pillars 22 connected to the same word line WL are arranged alternately. In this way, the number of word lines WL can be reduced, and the connection ports of the word lines WL and the peripheral control circuit can be reduced, thereby reducing the size of the memory.
  • first bit lines BL1 and a plurality of second bit lines BL2 there are a plurality of first bit lines BL1 and a plurality of second bit lines BL2, and the plurality of first bit lines BL1 are parallel to each other, and the plurality of second bit lines BL2 are parallel to each other. That is, the first bit lines BL1 and the second bit lines BL2 are connected to a plurality of first semiconductor pillars 21 in the first direction X.
  • the plurality of first bit lines BL1 and the plurality of second bit lines BL2 are arranged alternately, and the arrangement direction is the second direction Y.
  • the plurality of storage cells 4 share the first bit lines BL1 and the second bit lines BL2, which is conducive to reducing the number of the first bit lines BL1 and the second bit lines BL2, and reducing the bit lines and the peripheral control circuit. connection ports, thereby reducing the size of the memory.
  • multiple electrode layers 30, and the multiple electrode layers 30 are arranged at intervals; there are multiple magnetic tunnel junctions MTJ, and the multiple magnetic tunnel junctions MTJ are arranged at intervals, and the multiple magnetic tunnel junctions MTJ are connected to the multiple electrode layers 30 in a one-to-one correspondence.
  • There are multiple source lines SL and the multiple source lines SL are parallel to each other.
  • the multiple source lines SL are arranged along the second direction Y, and one source line SL is connected to multiple magnetic tunnel junctions MTJ in the first direction X.
  • Multiple memory cells 4 share the source line SL, which is conducive to reducing the number of source lines SL and reducing the connection ports between the source line SL and the peripheral control circuit, thereby reducing the size of the memory.
  • each memory cell 4 can have the same unit area.
  • the total width of a bit line and the bit line spacing area is 2F
  • the total width of a word line WL and the word line spacing area is 2F
  • the area of a memory cell 4 on the substrate 10 is 8F 2 , where F represents the characteristic size of the memory.
  • Figure 4 shows an equivalent circuit diagram of a memory cell of the memory.
  • the word line WL can control the switching state of the first transistor T1 and the second transistor T2, and the first bit line BL1, the second bit line BL2, and the source line SL can provide different voltage signals to the memory cell 4, thereby generating different currents in the memory cell 4. Since the first transistor T1 and the second transistor T2 are connected to the same word line WL, the control process of the transistor is simpler and energy-saving.
  • FIG. 4 to 7 another embodiment of the present disclosure provides a memory read and write method, which can perform read and write operations on the memory provided by the above embodiments. This will be described in detail below with reference to the accompanying drawings.
  • the memory is written, including: providing a start signal to the word line WL to turn on the first transistor T1 and the second transistor T2; providing a first current I1, the first current I1 flows through the first transistor T1, the electrode layer 30 and the second transistor T2.
  • the first current I1 can be understood as a SOT current. It should be noted that the arrowed lines in FIG. 5 and FIG. 6 show the current direction, which is not fixed and can be adjusted according to different situations. all.
  • the current flowing through the storage unit 4 during the write operation may be only the first current I1.
  • the magnetic tunnel junction MTJ can complete the reversal from the parallel state to the antiparallel state, that is, the writing of data 1 is realized;
  • the first current I1 flows from the second transistor T2 through the electrode layer 30 and the first transistor T1 in sequence, and the magnitude of the first current I1 is greater than the threshold current of the magnetization reversal, the magnetic tunnel junction MTJ completes the reversal from the antiparallel state to the parallel state, that is, the writing of data 0 is realized.
  • different data writing can be realized by controlling the direction and magnitude of the first current I1
  • the start signal provided by the word line WL is a high level to turn on the first transistor T1 and the second transistor T2. If the first transistor T1 and the second transistor T2 are both PMOS, the start signal provided by the word line WL is a low level.
  • the current flowing through the memory cell 4 during the write operation includes a first current I1 and a third current I3.
  • the third current I3 flows through the magnetic tunnel junction MTJ, the electrode layer 30 and the first transistor T1, or the third current I3 flows through the magnetic tunnel junction MTJ, the electrode layer 30 and the second transistor T2.
  • the first current I1 can be understood as a SOT current
  • the third current I3 can be understood as a STT current.
  • the synergistic effect of the STT current and the SOT current is used to realize the flipping of the free layer FL, wherein the SOT current can disturb the magnetization direction of the free layer FL, and the different flow directions of the STT current can cause the magnetization direction to be deterministically flipped.
  • This synergistic effect can improve the flipping speed, reduce the driving current, and does not require an auxiliary magnetic field, which is conducive to simplifying the device structure and improving the integration of the memory.
  • the order of applying the first current I1 and the third current I3 can be controlled to improve the writing efficiency of the synergistic effect and improve the tolerance and service life of the storage unit 4.
  • the first current I1 is first applied to disturb the magnetization direction of the free layer FL of the magnetic tunnel junction MTJ.
  • the third current I3 is applied, and the first current I1 and the third current I3 work together to speed up the overall flipping process.
  • the first current I1 is removed, and the third current I3 continues to drive the free layer FL of the magnetic tunnel junction MTJ to complete the flipping process.
  • the first current I1 and the third current I3 may also be applied simultaneously.
  • the memory may further include a first bit line BL1 and a second bit line BL2 arranged at intervals; a first semiconductor column 21 is located on the upper surface of the first bit line BL1, and a second semiconductor column 22 is located on the upper surface of the second bit line BL2; the memory further includes: a source line SL located on the upper surface of the magnetic tunnel junction MTJ.
  • the first bit line BL1 may provide a high level or a low level to the drain region D of the first transistor T1
  • the second bit line BL2 may provide a high level or a low level to the drain region D of the second transistor T2
  • the source line SL may provide a high level or a low level to the side of the magnetic tunnel junction MTJ away from the substrate 10, thereby forming a current in the memory cell 4. This will be described in detail below.
  • a write operation is performed on the memory, including: one of the first bit line BL1 and the second bit line BL2 provides a high level to form a first current I1.
  • the first current I1 flows from the first transistor T1 to the electrode layer 30 and the second transistor T2 in sequence.
  • the first current I1 flows from the second transistor T2 to the electrode layer 30 and the first transistor T1 in sequence.
  • the different flow directions of the first current I1 cause the magnetic moment to flip in different directions, thereby writing different data.
  • the source line SL can be floating.
  • a write operation is performed on the memory, including: one of the first bit line BL1 and the second bit line BL2 provides a high level, the other provides a low level, and the source line SL provides a high level or a low level to form a first current I1 and a third current I3.
  • the third current I3 flows from the magnetic tunnel junction MTJ through the electrode layer 30 and the second transistor T2 in sequence;
  • the source line SL is at a low level, the first bit line BL1 is at a high level, and the second bit line BL2 is at a low level, the third current I3 flows from the first transistor T1 through the electrode layer 30 and the magnetic tunnel junction MTJ in sequence.
  • a read operation is performed on the memory, including: providing an on signal to the word line WL to turn on the first transistor T1 and the second transistor T2; providing a second current I2, the second current I2 flows through the magnetic tunnel junction MTJ and the electrode layer 30. That is, by measuring the magnitude of the second current I2, the magnetic resistance magnitude of the magnetic tunnel junction MTJ can be obtained, thereby reading different data.
  • the first bit line BL1 provides a low level to the drain region D of the first transistor T1
  • the second bit line BL2 provides a low level to the drain region D of the second transistor T2
  • the source line SL provides a low level to the drain region D of the first transistor T1.
  • the side of the magnetic tunnel junction MTJ away from the substrate 10 provides a high level to form the second current I2. That is, since the first transistor T1 and the second transistor T2 are in the on state, the first bit line BL1 and the second bit line BL2 can apply a low level to the opposite ends of the electrode layer 30 through the first transistor T1 and the second transistor T2, respectively. Therefore, the electrode layer 30 is also in a low level state. Since the side of the magnetic tunnel junction MTJ away from the substrate 10 is a high level, the second current I2 can flow from the side of the magnetic tunnel junction MTJ away from the substrate 10 toward the side of the magnetic tunnel junction MTJ close to the substrate 10.
  • a first transistor T1, a second transistor T2, an electrode layer 30 and a magnetic tunnel junction MTJ are used to constitute a memory cell 4; the first transistor T1 and the second transistor T2 of the same memory cell 4 share the same word line WL. Therefore, the control of the first transistor T1 and the second transistor T2 by the word line WL is synchronous. In other words, during the read operation and the write operation, the word line WL simultaneously provides an open signal to the first transistor T1 and the second transistor T2 of the same memory cell 4. In this way, compared with connecting the first transistor T1 and the second transistor T2 to different word lines WL, connecting the same word line WL can simplify the control process and reduce energy consumption. Therefore, the memory provided by the embodiment of the present disclosure has greater advantages in terms of operating speed and energy saving.
  • another embodiment of the present disclosure further provides a method for manufacturing a memory, which can be used to manufacture the memory provided by the above embodiments.
  • a method for manufacturing a memory which can be used to manufacture the memory provided by the above embodiments.
  • a substrate 10 is provided, and a transistor group T, an electrode layer 30, and a magnetic tunnel junction MTJ are formed on the substrate 10.
  • a transistor group T, an electrode layer 30, and a magnetic tunnel junction MTJ are stacked and formed in sequence on the substrate 10.
  • the method before forming the transistor group T, further includes: forming a first bit line BL1 and a second bit line BL2 spaced apart on the substrate 10.
  • a bit line isolation layer is first formed on the substrate 10, wherein the bit line isolation layer has a groove extending along the first direction X, and a plurality of grooves are arranged in the second direction Y.
  • Metal is deposited in the groove to serve as a bit line, and for two adjacent bit lines, one is used as the first bit line BL1, and the other is used as the second bit line BL2.
  • a silicon layer is deposited on the bit line, and the silicon layer is doped by in-situ doping or ion implantation. Thereafter, the silicon layer is patterned to form a plurality of drain regions D spaced apart. Thereafter, a first insulating layer (not shown) is filled between adjacent drain regions D.
  • the drain region D located on the upper surface of the first bit line BL1 serves as the drain region D of the first semiconductor column 21 to be formed subsequently, and the drain region D located on the upper surface of the second bit line BL2 serves as the drain region D of the second semiconductor column 22 to be formed subsequently.
  • a channel region C is formed on the drain region D by an epitaxial growth process or a chemical vapor deposition process.
  • the channel region C directly facing the first bit line BL1 serves as the channel region C of the first semiconductor column 21 to be formed subsequently
  • the channel region C directly facing the second bit line BL2 serves as the channel region C of the second semiconductor column 22 to be formed subsequently.
  • An initial gate dielectric layer (not shown in the figure) is formed on the top surface and sidewall of the channel region C, and then a word line WL connected to the channel region C is formed, that is, the word line WL is located on the sidewall of the channel region C and covers the initial gate dielectric layer.
  • a second insulating layer is formed between adjacent word lines WL to isolate adjacent word lines WL. The initial gate dielectric layer located on the top surface of the channel region C is removed, and the remaining initial gate dielectric layer is used as a gate dielectric layer.
  • a source region S is formed on the top surface of the channel region C, and a third insulating layer (not shown) is filled between the source regions S.
  • the steps for forming the source region S may refer to the steps for forming the drain region D, which will not be repeated here.
  • the transistor group T includes a first semiconductor column 21 and a second semiconductor column 22 that are spaced apart, and a word line WL connected to the channel region C of the first semiconductor column 21 and the second semiconductor column 22.
  • the first semiconductor column 21 and the second semiconductor column 22 both have a drain region D, a channel region C, and a source region S arranged in a direction perpendicular to the substrate 10.
  • the drain region D, the channel region C, and the source region S located on the first bit line BL1 serve as the first semiconductor column 21, and the drain region D, the channel region C, and the source region S located on the second bit line BL2 serve as the second semiconductor column 22.
  • the first semiconductor column 21 and the word line WL constitute a first transistor T1; the second semiconductor column 22 and the word line WL constitute a second transistor T2.
  • the above process steps can form a plurality of memory cells 4 on the substrate 10.
  • the memory cells 4 include: a first transistor T1, a second transistor T2, an electrode layer 30, and a magnetic tunnel junction MTJ.
  • the first transistor T1 and the second transistor T2 of the same memory cell 4 are connected to the same word line WL. This is conducive to reducing the number of word lines WL, thereby saving The area on the substrate 10 is saved, thereby improving the integration of the memory.
  • An electrode layer 30 is formed on the transistor group T. Specifically, an initial electrode layer is formed on the transistor group T arranged in an array, and the initial electrode layer is patterned to form a plurality of electrode layers 30 arranged at intervals.
  • the electrode layer 30 is connected to the source regions S of the first semiconductor column 21 and the second semiconductor column 22. By way of example, both ends of the electrode layer 30 are connected to the first semiconductor column 21 and the second semiconductor column 22, respectively. Thereafter, a fourth insulating layer (not shown in the figure) is filled between adjacent electrode layers 30.
  • a magnetic tunnel junction MTJ is formed on the electrode layer 30. Specifically, an initial free layer, an initial non-magnetic isolation layer, and an initial fixed layer are sequentially deposited on the electrode layer 30; thereafter, a portion of the initial free layer, a portion of the initial non-magnetic isolation layer, and a portion of the initial fixed layer are sequentially etched to form a free layer FL, a non-magnetic isolation layer 5, and a fixed layer PL to form a plurality of spaced magnetic tunnel junctions MTJ. Thereafter, a fifth insulating layer (not shown in the figure) may be filled between adjacent magnetic tunnel junctions MTJ.
  • the manufacturing method of the memory further includes: forming a source line SL on the magnetic tunnel junction MTJ.
  • a layer of metal is deposited on the magnetic tunnel junction MTJ as an initial source line, and the initial source line is etched to form the source line SL.
  • a magnetic tunnel junction MTJ may be formed first, and then the electrode layer 30 and the transistor group T may be formed in sequence.
  • a source line SL may be formed on the substrate 10; after forming the transistor group T, a first bit line BL1 and a second bit line BL2 may be formed at intervals.
  • the transistor group T and the magnetic tunnel junction MTJ may also be formed on the same side of the electrode layer 30.
  • the source line SL, the first bit line BL1, and the second bit line BL2 may be adjusted in manufacturing order according to the actual process to ensure that the source line SL is connected to the fixed layer PL of the magnetic tunnel junction MTJ, the first bit line BL1 is connected to the drain region D of the first semiconductor column 21, and the second bit line BL2 is connected to the drain region D of the second semiconductor column 22.
  • forming a vertical transistor on the substrate 10 and forming a word line WL connected to two vertical transistors of the same memory cell 4 can reduce the size of the memory and improve the integration of the memory.

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Abstract

公开了一种存储器、存储器的读写方法和制造方法，该存储器包括基底，在垂直基底的方向上堆叠设置有晶体管组、电极层、磁隧道结。晶体管组包括间隔设置的第一半导体柱和第二半导体柱，第一半导体柱和第二半导体柱均具有在垂直于基底的方向上排布的漏极区、沟道区和源极区。晶体管组还包括字线，字线与第一半导体柱和第二半导体柱的沟道区相连。第一半导体柱与字线构成第一晶体管，第二半导体柱与字线构成第二晶体管。电极层与第一半导体柱和第二半导体柱的源极区相连。

Description

存储器、存储器的读写方法和制造方法
交叉引用
本申请引用于2022年11月22日递交的名称为“存储器、存储器的读写方法和制造方法”的第202211467791.X号中国专利申请，其通过引用被全部并入本申请。
技术领域
本公开实施例属于半导体领域，具体涉及一种存储器、存储器的读写方法和制造方法。
背景技术
随着物联网技术和人工智能技术的不断发展，存储器与处理器间的吞吐速率不断增大，需要不断提升其读写速度、降低读写功耗。目前，以静态随机存储器和动态随机存储器为代表的易失性存储器仍面临着静态功耗较高的挑战。磁性随机存储器(magnetic random access memory，MRAM)因具有非易失性、高速度、低功耗等优良性能，已成为最具潜力的新型非易失性存储器之一。
自旋转移力矩磁随机存储器(Spin Transfer Torque-magnetic random access memory，STT-MRAM)和自旋轨道扭矩-磁随机存储器(Spin orbit torque-magnetic random access memory，SOT-MRAM)是两种主流的MRAM。其中，STT-MRAM可以利用电流直接通过磁隧道结从而改写磁化方向。而SOT-MRAM还包括了电极层，电极层能够提供的强烈自旋轨道作用，从而提高磁隧道结的磁矩翻转效率。
然而，磁性随机存储器的尺寸还有待进一步降低。
发明内容
本公开实施例提供一种存储器、存储器的读写方法和制造方法，至少有利于缩小存储器的尺寸。
根据本公开一些实施例，本公开实施例一方面提供一种存储器，其中，存储器包括：基底，所述基底上具有晶体管组、电极层、磁隧道 结，所述晶体管组、电极层、磁隧道结在垂直所述基底的方向上堆叠设置；所述晶体管组包括间隔设置的第一半导体柱和第二半导体柱，所述第一半导体柱和所述第二半导体柱均具有在垂直于基底的方向上排布的漏极区、沟道区和源极区；所述晶体管组还包括字线，所述字线与所述第一半导体柱和第二半导体柱的沟道区相连；所述第一半导体柱与所述字线构成第一晶体管；所述第二半导体柱与所述字线构成第二晶体管；所述电极层与所述第一半导体柱和所述第二半导体柱的所述源极区相连。
根据本公开一些实施例，本公开实施例另一方面还提供一种存储器的读写方法，此读写方法可以对前述存储器进行读写操作。对所述存储器进行写操作，包括：向所述字线提供开启信号，以打开所述第一晶体管和所述第二晶体管；提供第一电流，所述第一电流流经所述第一晶体管、所述电极层和所述第二晶体管。对所述存储器进行读操作，包括：向所述字线提供开启信号，以打开所述第一晶体管和所述第二晶体管；提供第二电流，所述第二电流流经所述磁隧道结和所述电极层。
根据本公开一些实施例，本公开实施例又一方面还提供一种存储器的制造方法，制造方法包括：提供基底，在所述基底上形成晶体管组、电极层、磁隧道结，所述晶体管组、电极层、磁隧道结在垂直所述基底的方向上堆叠设置；形成所述晶体管组包括：形成间隔设置的第一半导体柱和第二半导体柱，所述第一半导体柱和所述第二半导体柱均具有在垂直于所述基底的方向上排布的漏极区、沟道区和源极区；形成所述晶体管组还包括：形成字线，所述字线与所述第一半导体柱和第二半导体柱的沟道区相连；所述第一半导体柱与所述字线构成第一晶体管；所述第二半导体柱与所述字线构成第二晶体管；所述电极层与所述第一半导体柱和所述第二半导体柱的所述源极区相连。
本公开实施例提供的技术方案至少具有以下优点：漏极区、沟道区和源极区层叠设置于基底上，因此，第一晶体管和第二晶体管为垂直晶体管。垂直晶体管比平面晶体管在基底上占据的面积更小。另外，字线连接第一半导体柱和第二半导体柱，即两个晶体管共用一条字线。字线数量更少，有利于缩小存储器的尺寸。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了本公开一实施例提供的一种存储器的局部立体图；
图2示出了本公开一实施例提供的一种存储器的俯视图；
图3示出了本公开一实施例提供的另一种存储器的局部立体图；
图4示出了本公开一实施例提供的一种存储器的存储单元的等效电路图；
图5-图6分别示出了本公开一实施例提供的一种存储器的存储单元在写操作时的两种等效电路图；
图7示出了本公开一实施例提供的一种存储器的存储单元在读操作时的等效电路图。
具体实施方式
由背景技术可知，磁性随机存储器的尺寸还有待进一步降低。经分析发现，SOT-MRAM由于需要额外的电极层，使得电极层和磁隧道结共同产生了三个端子，至少需要接入两个晶体管来控制它，因此，其尺寸难以缩小。
本公开实施例提供一种存储器，包括：第一半导体柱和第二半导体柱，二者均具有在垂直于基底的方向上排布的漏极区、沟道区和源极区；字线与第一半导体柱和第二半导体柱的沟道区相连。也就说是，两个晶体管共用字线，因而可以减少字线数量，缩小存储器的尺寸；另外，相比于平面晶体管，垂直晶体管的在基底上所占据的面积更小。因此，存储器的尺寸更小。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开实施例而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开实施例所要求保护的技术方案。
如图1-图4所示，本公开一实施例提供一种存储器，存储器包括：基底10，基底10上具有晶体管组T、电极层30、磁隧道结MTJ，晶体管组T、电极层30、磁隧道结MTJ在垂直基底10的方向上堆叠设置；晶体管组T包括间隔设置的第一半导体柱21和第二半导体柱22，第一半导体柱21和第二半导体柱22均具有在垂直于基底10的方向上排布的的漏极区D、沟道区C和源极区S；晶体管组T还包括字线WL，字线WL与第一半导体柱21和第二半导体柱22的沟道区C相连；第一半导体柱21与字线WL构成第一晶体管T1；第二半导体柱22与字线WL构成第二晶体管T2；电极层30与第一半导体柱21和第二半导体柱22的源极区S相连。
这样的设计至少具有以下好处：
第一，第一晶体管T1和第二晶体管T2均为垂直晶体管，相比于平面晶体管，垂直晶体管在基底10上所占据的面积更小，有利于提高排列密度，进而提高存储器的集成度。
第二、相比于第一半导体柱21和第二半导体柱22连接不同的字线WL，二者连接同一字线WL可以减少字线WL数量，从而缩小存储器的尺寸，提高存储器的集成度。
第三，垂直晶体管的漏极区D、沟道区C和源极区S在垂直于基底10的方向排布，即，垂直晶体管的沟道区C与漏极区D和源极区S处于不同的高度位置，因此，采用同一字线WL连接两个垂直晶体管的沟道区C时，由于字线WL更易避开漏极区D和源极区S，其走线设置会更加简单，有利于减少字线WL所占据的空间位置，从而提高存储器的集成度。而平面晶体管的漏极区D、沟道区C和源极区S在基底10上并排设置，即三者通常位于同一层，因此，若同一字线WL连接两个平面晶体管的沟道区C，则需要对字线WL的走线进行更复杂的设计，以避开漏极区D和源极区S，字线WL所占据的空间位置会更大。
第四，电极层30与两个晶体管相连，结构的对称性更高；相比于电极层30的连接一晶体管和一信号线，电极层30均与晶体管相连能够避免出现负反馈效应，即避免产生写入电流不对称的现象，从而提高了写操作的可靠性。
以下将结合附图对存储器的结构进行详细说明。
首先需要说明的是，存储器内具有第一方向X、第二方向Y和第三方向Z，其中，第一方向X和第二方向Y可以平行于基底10的上表面，而第三方向Z可以垂直于基底10的上表面。在一些实施例中，第一方向X和第二方向Y可以相垂直，或者接近于垂直关系。参考图1-图3，基底10可以为硅基底或锗基底，基底10的材料可以与第一半导体柱21的材料和第二半导体柱22的材料相同。
参考图1-图3，本实施例中，晶体管组T、电极层30、磁隧道结MTJ依次在基底10上堆叠设置。在一些实施例中，磁隧道结MTJ与晶体管组T也可以设置于电极层30的同一侧。相对于磁隧道结MTJ与晶体管组T设置于电极层30的同一侧，晶体管组T、电极层30、磁隧道结MTJ依次在基底10上堆叠设置有利于减少三者在基底10上表面占据的总面积。这是因为，若磁隧道结MTJ与晶体管组T设置于电极层30的同一侧，则磁隧道结MTJ需要位于第一半导体柱21和第二半导体柱22之间，那么第一半导体柱21与第二半导体柱22的间距可能会相应增大以避免半导体柱与磁隧道结MTJ发生电连接，由此，二者在基底1上表面占据的总面积就会增大。
另外，晶体管组T相比于磁隧道结MTJ更靠近基底10，可以利用外延生长工艺在基底10上生长单晶层以作为晶体管组T的第一半导体柱21和第二半导体柱22，从而降低生产单晶层的难度，以简化生产工艺。
在另一些实施例中，晶体管组T可以和磁隧道结MTJ均位于电极层30的朝向基底10的一侧；或者，晶体管组T也可以和磁隧道结MTJ均位于电极层30远离基底10的一侧。在另一些实施例中，晶体管组T也可以位于电极层30远离基底10的一侧，而磁隧道结MTJ位于电极层30朝向基底10的一侧，即磁隧道结MTJ、电极层30、晶体管组T依次在基底10上堆叠设置。
在一些实施例中，第一半导体柱21和第二半导体柱22均在第三方向Z上延伸，且二者在第二方向Y上排列。示例地，第一半导体柱21和第二半导体柱22在第三方向Z上的高度相同。漏极区D中可以具有 与源极区S相同类型的掺杂离子，比如二者的掺杂离子类型均为N型，沟道区C的掺杂离子类型可以与源极区S和漏极区D的掺杂离子类型相反，比如沟道区C的掺杂离子类型为P型。
在一些实施例中，第一半导体柱21和第二半导体柱22可以均为一体式结构，换言之，利用一道工艺步骤即可形成第一半导体柱21，利用一道工艺步骤即可形成第二半导体柱22，从而提高生产效率。示例地，采用一道外延生长工艺形成第一半导体柱21和第二半导体柱22。在另一些实施例中，第一半导体柱21可以不为一体式结构，第二半导体柱22也可以不为一体式结构。换言之，先后利用不同的工艺步骤以形成源极区S、沟道区C、漏极区D。字线WL的延伸方向可以为第二方向Y，即字线WL的延伸方向平行与第一半导体柱21和第二半导体柱22的排列方向相同。如此，有利于减小字线WL的长度，以缩小存储器的尺寸。字线WL作为第一晶体管T1和第二晶体管T2的栅极，用于控制第一晶体管T1和第二晶体管T2的开关状态。由于两个晶体管共用同一字线WL，因而，两个晶体管的控制信号是相同的，控制晶体管的过程可以得到简化，从而有利于提高存储器的运行速率并降低能耗。字线WL的材料可以为钨、钼、金、钴等金属，以降低字线WL的电阻。
换句话说，字线WL可以包括栅极部和连接部，其中，栅极部与第一半导体柱21和第二半导体柱22的沟道区C相连，连接部位于相邻栅极部之间，连接部与第一半导体柱21和第二半导体柱22之间的间隙正对。
需要说明的是，前述“字线WL与第一半导体柱21和第二半导体柱22的沟道区C相连”并不是指字线WL与沟道区C直接接触，而是指字线WL可以位于沟道区C的侧壁。因为字线WL与沟道区C之间还具有栅介质层(图中未示出)。
在一些实施例中，参考图1和图2，字线WL环绕第一半导体柱21的沟道区C，并环绕第二半导体柱22的沟道区C，即字线WL包覆第一半导体柱21和第二半导体柱22的中部侧壁。也就是说，第一晶体管T1和第二晶体管T2均为垂直全环栅结构(Vertical-Gate-All-Around,VGAA)。垂直全环栅结构的字线WL与第一半 导体柱21和第二半导体柱22的接触面积很大，从而有利于提高晶体管的栅控能力，进而提高存储器的电性能。
另外，在字线WL环绕第一半导体柱21和第二半导体柱22时，字线WL还可以充分利用两个半导体柱之间的空间位置，从而提高各结构的排列密度，并有利于降低字线WL的电阻。
参考图3，在另一些实施例中，字线WL也可以只与第一半导体柱21和第二半导体柱22的部分侧壁相连。示例地，第一半导体柱21和第二半导体柱22可以为四棱柱，字线WL与第一半导体柱21的一个侧壁相接触，并与第二半导体柱22的一个侧壁相接触。或者，字线WL也可以与第一半导体柱21的两个或三个侧壁相接触，并与第二半导体柱22的两个或三个侧壁相接触。
磁隧道结MTJ(Magnetic Tunnel Junction)包括层叠设置的自由层FL(free layer)、非磁性隔离层5和固定层PL(pinned layer)，自由层FL与电极层30相连。其中，固定层PL的磁化方向是不变的，而自由层FL的磁化方向可以被改变。当固定层PL和自由层FL磁化方向一致时，称为“平行状态”，磁隧道结MTJ的隧道磁阻为低；当磁化方向不一致时，称为“反平行状态”，磁隧道结MTJ的隧道磁阻为低。两个阻态可分别代表二进制数据“0”和“1”用于数据存储。因此，数据的写入可以通过切换自由层FL的磁化方向来实现，读取过程则可以测量经过磁隧道结MTJ的电流大小，从而获得磁阻大小。
示例地，非磁性隔离层5的材料可以为氧化物，比如氧化镁。自由层FL和固定层PL材料可以是诸如铁、钴、以及镍之类的典型的过渡金属铁磁体。
流经电极层30的电流可引发力矩效应以驱动自由层FL的磁化翻转，该力矩的成因可能是拉什巴效应(RashbaEffect)、自旋霍尔效应(Spin Hall Effect，SHE)或二者兼有。也就是说，向电极层30通入电流可以产生自旋流并注入到自由层FL中，利用自旋轨道矩使自由层FL的磁化方向产生扰动，并结合多种方式让磁化方向产生确定性的翻转，后续将结合存储器的读写方法对此进行详细说明。
第一半导体柱21和第一半导体柱21分别与电极层30的相对两端 相连。即，第一晶体管T1和第二晶体管T2控制通入电极层30的电流流向，使得电流从电极层30的一端流向至另一端。在一些实施例中，第一半导体柱21和第二半导体柱22与电极层30的底面相连，且二者分别位于电极层30的底面的相对两侧。
在一些实施例中，电极层30包括重金属材料。示例地，重金属可以为钨、铂、钽。重金属材料具有较高的自旋轨道耦合作用(Spin Orbit Coupling)。另外，重金属层容易匹配半导体后道工艺。在另一些实施例中，电极层30的材料还可以包括拓扑绝缘体(topological insulators)，例如铋和锑的硫属化物。此外，电极层30的材料还可以包括反铁磁金属，比如铱锰合金、铂锰合金等。
在一些实施例中，电极层30可以为单层结构，比如仅包括重金属层；在另一些实施例中，电极层30还可以为多层复合结构，比如包括重金属层和铁磁层。
在一些实施例中，磁隧道结MTJ为平行磁隧道结，其磁矩的方向平行于基底10的上表面。在驱动平行磁隧道结的磁矩进行翻转时，可以只向电极层30通入电流，而无需向磁隧道结MTJ通入电流。在另一些实施例中，磁隧道结MTJ为垂直磁隧道结时，其磁矩的方向垂直于基底10的上表面，在驱动垂直磁隧道结的磁矩进行翻转时，需要向电极层30和磁隧道结MTJ都通入电流，在两种电流的作用之下，磁矩可以发生定向的翻转。这是因为平行磁隧道结的磁阻尼系数通常小于垂直磁隧道结的磁阻尼系数。因此，在两种电流的叠加作用下，可以降低垂直磁隧道结的翻转难度。
继续参考图1-图3，存储器还包括：间隔设置的第一位线BL1和第二位线BL2；第一半导体柱21位于第一位线BL1的上表面，第二半导体柱22位于第二位线BL2的上表面。字线WL与第一位线BL1和第二位线BL2相互绝缘设置。具体地，第一半导体柱21的漏极区D与第一位线BL1相连，第二半导体柱22的漏极区D与第二位线BL2相连。在第一晶体管T1和第二晶体管T2开启的状态下，第一位线BL1和第二位线BL2可以向电极层30提供电流。
在一些实施例中，第一位线BL1和第二位线BL2的延伸方向相同， 以减少二者在基底10上所占据的总面积。示例地，二者的延伸方向为第一方向X，且二者的延伸方向均垂直于字线WL的延伸方向。即，第一方向X与第二方向Y相垂直。或者，第一位线BL1和第二位线BL2的延伸方向也可以不与字线WL的延伸方向完全垂直，而是接近于垂直的关系。如此，在存储器的存储区的边缘处能够节省面积。
继续参考图1-图3，存储器还包括：源极线SL，源极线SL位于磁隧道结MTJ的上表面。源极线SL可以向磁隧道结MTJ提供电流，以读取或存储数据。在一些实施例中，源极线SL的延伸方向可以与第一半导体柱21和第二半导体柱22的排列方向相垂直，源极线SL的延伸方向还可以平行于第一位线BL1的延伸方向和第二位线BL2的延伸方向。即，源极线SL的延伸方向可以为第一方向X，并与第二方向Y相垂直。由此，能够充分利用基底10上表面的空间位置，以减小存储器的尺寸。
需要说明的是，前述一个第一晶体管T1、一个第二晶体管T2、一个电极层30、一个磁隧道结MTJ可以构成一个基本的存储单元4，同一存储单元4的第一晶体管T1和第二晶体管T2共用同一字线WL。在一些实施例中，存储单元4可以为多个，且多个存储单元4在基底10上阵列排布。下面将对此进行详细说明。
参考图2，多个第一半导体柱21在基底10上阵列排布，多个第二半导体柱22在基底10上阵列排布。字线WL为多条，多条字线WL相互平行，且多条字线WL沿着第一方向X排布。一条字线WL可以作为多个存储单元4的栅极，即同一字线WL可以连接多个第一半导体柱21和多个第二半导体柱22，且与同一字线WL相连的多个第一半导体柱21和多个第二半导体柱22交替排列。如此，可以减少字线WL的数量，减少字线WL与外围控制电路的连接端口，从而减小存储器的尺寸。
继续参考图2，第一位线BL1为多条，第二位线BL2为多条，且多条第一位线BL1相互平行，多条第二位线BL2相互平行。即，第一位线BL1和第二位线BL2均在第一方向X上连接多个第一半导体柱21。其中，多条第一位线BL1和多条第二位线BL2交替排列，且排列方向为第二方向Y。多个存储单元4共用第一位线BL1和第二位线BL2，有利于减少第一位线BL1和第二位线BL2的数量，减少位线与外围控制电路 的连接端口，从而减小存储器的尺寸。
继续参考图2，电极层30为多个，且多个电极层30间隔设置；磁隧道结MTJ为多个，且多个磁隧道结MTJ间隔设置，多个磁隧道结MTJ与多个电极层30一一对应连接。源极线SL为多条，且多条源极线SL相互平行。在一些实施例中，多条源极线SL沿着第二方向Y排布，且一条源极线SL在第一方向X上与多个磁隧道结MTJ相连。多个存储单元4共用源极线SL，有利于减少源极线SL的数量，减少源极线SL与外围控制电路的连接端口，从而减小存储器的尺寸。
需要说明的是，若第一晶体管T1和第二晶体管T2的位置差异过大，则不同存储单元4可能具有不同的单元面积。因此，将第一晶体管T1和第二晶体管T2在存储器内进行同层设置，二者相对于基底10的高度可以相同。由此，可以使得每个存储单元4都具有相同的单位面积。在一些实施例中，参考图2，一条位线和位线间隔区域的总宽度为2F，一条字线WL和字线间隔区域的总宽度为2F，那么一个存储单元4在基底10上的面积为8F2，F表示存储器的特征尺寸。相比于具有平面晶体管以及连接不同字线WL的存储单元4，本公开实施例中的存储单元4的单位面积可以以大大减小。
参考图4，图4示出了存储器的存储单元的等效电路图。字线WL可以控制第一晶体管T1和第二晶体管T2的开关状态，第一位线BL1、第二位线BL2、源极线SL可以向存储单元4提供不同的电压信号，从而在存储单元4产生不同的电流。由于第一晶体管T1和第二晶体管T2连接的是同一字线WL，因而晶体管的控制过程更为简单、节能。
如图4-图7所示，本公开另一实施例提供一种存储器的读写方法，此读写方法可以对前述实施例提供的存储器进行读写操作。下面将结合附图对此进行详细说明。
参考图5-图6，对存储器进行写操作，包括：向字线WL提供开启信号，以打开第一晶体管T1和第二晶体管T2；提供第一电流I1，第一电流I1流经第一晶体管T1、电极层30和第二晶体管T2。第一电流I1可以理解为一种SOT电流。需要说明的是，图5和图6中带箭头的线条示出了电流方向，该电流方向并不固定，可以根据不同的情况进行调 整。
具体地，参考图5，在一些实施例中，存储单元4的磁隧道结MTJ为平行磁隧道结时，写操作时流经存储单元4的电流可以仅为第一电流I1。示例地，当第一电流I1从第一晶体管T1依次流经电极层30和第二晶体管T2，且第一电流I1的大小大于磁化翻转的阈值电流时，磁隧道结MTJ可以完成从平行态到反平行态的翻转，即实现数据1的写入；当第一电流I1从第二晶体管T2依次流经电极层30和第一晶体管T1，且第一电流I1大大小大于磁化翻转的阈值电流时，磁隧道结MTJ完成从反平行态到平行态的翻转，即实现数据0的写入。也就是说，通过控制第一电流I1的方向和大小即可实现不同的数据写入。
另外，若第一晶体管T1和第二晶体管T2均为NMOS，则字线WL提供的开启信号为高电平，以打开第一晶体管T1和第二晶体管T2。若第一晶体管T1和第二晶体管T2均为PMOS，则字线WL提供的开启信号为低电平。
参考图6，在一些实施例中，存储单元4的磁隧道结MTJ为垂直磁隧道结时，写操作时流经存储单元4的电流包括第一电流I1和第三电流I3。第三电流I3流经磁隧道结MTJ、电极层30和第一晶体管T1，或者，第三电流I3流经磁隧道结MTJ、电极层30和第二晶体管T2。其中，第一电流I1可以理解为一种SOT电流，第三电流I3可以理解为一种STT电流。即，利用STT电流和SOT电流的协同作用实现自由层FL的翻转，其中SOT电流可以扰动自由层FL的磁化方向，而STT电流不同的流向可以使得磁化方向产生确定性翻转。这种协同效应可以改善翻转速度，降低驱动电流，且无需辅助磁场，从而有利于简化器件结构，提高存储器的集成度。
在一些实施例中，可以控制第一电流I1和第三电流I3的施加顺序，以提升协同效应的写入效率，并提高存储单元4的耐受性和使用寿命。示例地，首先施加第一电流I1以扰动磁隧道结MTJ的自由层FL的磁化方向。一段时间后，开始施加第三电流I3，此时第一电流I1与第三电流I3协同作用，从而加快整体的翻转过程。再过一段时间后，第一电流I1被撤去，第三电流I3继续驱动磁隧道结MTJ的自由层FL完成翻转过程。 在另一些实施例中，也可以同时施加第一电流I1和第三电流I3。
由前述实施例可知，存储器还可以包括间隔设置的第一位线BL1和第二位线BL2；第一半导体柱21位于第一位线BL1的上表面，第二半导体柱22位于第二位线BL2的上表面；存储器还包括：位于磁隧道结MTJ的上表面的源极线SL。其中，第一位线BL1可以向第一晶体管T1的漏极区D提供高电平或低电平，第二位线BL2可以向第二晶体管T2的漏极区D提供高电平或低电平，源极线SL可以向磁隧道结MTJ远离基底10的一侧提供高电平或低电平，由此可以在存储单元4内形成电流。下面将对此进行具体说明。
参考图5，在磁隧道结MTJ为平行磁隧道结时，对存储器进行写操作，包括：第一位线BL1和第二位线BL2中的一者提供高电平，以形成第一电流I1。在第一位线BL1提供高电平，第二位线BL2提供低电平时，第一电流I1从第一晶体管T1依次流向电极层30和第二晶体管T2。反之，第一电流I1从第二晶体管T2依次流向电极层30和第一晶体管T1。第一电流I1不同的流向使得磁矩向不同方向进行翻转，从而写入不同的数据。在写操作过程中，源极线SL可以是浮置的。
参考图6，在磁隧道结MTJ为垂直磁隧道结时，对存储器进行写操作，包括：第一位线BL1和第二位线BL2中的一者提供高电平，另一者提供低电平，源极线SL提供高电平或低电平，以形成第一电流I1和第三电流I3。示例地，在源极线SL为高电平，第一位线BL1为低电平，第二位线BL2为低电平时，则第三电流I3从磁隧道结MTJ依次流经电极层30和第二晶体管T2；在源极线SL为低电平时，第一位线BL1为高电平，第二位线BL2为低电平时，则第三电流I3从第一晶体管T1依次流经电极层30和磁隧道结MTJ。
参考图7，对存储器进行读操作，包括：向字线WL提供开启信号，以打开第一晶体管T1和第二晶体管T2；提供第二电流I2，第二电流I2流经磁隧道结MTJ和电极层30。即通过测量第二电流I2的大小，可以获得磁隧道结MTJ的磁阻大小，从而读取不同的数据。
具体地，第一位线BL1向第一晶体管T1的漏极区D提供低电平，第二位线BL2向第二晶体管T2的漏极区D提供低电平，源极线SL向 磁隧道结MTJ远离基底10的一侧提供高电平，以形成第二电流I2。也就是说，由于第一晶体管T1和第二晶体管T2处于开启状态，因而，第一位线BL1和第二位线BL2可以分别通过第一晶体管T1和第二晶体管T2将低电平施加到电极层30的相对两端。因而，电极层30也处于低电平的状态。由于磁隧道结MTJ远离基底10的一侧为高电平，因而第二电流I2可以从磁隧道结MTJ远离基底10的一侧朝向磁隧道结MTJ靠近基底10的一侧进行流动。
需要说明的是，一个第一晶体管T1、一个第二晶体管T2、一个电极层30和一个磁隧道结MTJ用于构成存储单元4；同一存储单元4的第一晶体管T1和第二晶体管T2共用同一字线WL。因此，字线WL对第一晶体管T1和第二晶体管T2的控制是同步的。也就是说，在读操作和写操作过程中，字线WL同时向同一存储单元4的第一晶体管T1和第二晶体管T2提供开启信号。如此，相比于第一晶体管T1和第二晶体管T2连接不同字线WL，连接同一字线WL可以简化控制过程，且降低能耗。因此，本公开实施例提供的存储器在运行速度以及节能等方面具有更大的优势。
如图1-图3所示，本公开又一实施例还提供一种存储器的制造方法，此制造方法可以用于制造前述实施例所提供的存储器。有关存储器的详细说明可以参考前述实施例。
以下将结合附图对本申请一实施例提供的存储器的制造方法进行详细说明。
提供基底10，在基底10上形成晶体管组T、电极层30、磁隧道结MTJ。本实施例中，在基底10上依次形成堆叠设置的晶体管组T、电极层30、磁隧道结MTJ。
在一些实施例中，在形成晶体管组T以前还包括：在基底10上形成间隔设置的第一位线BL1和第二位线BL2。示例地，在基底10上先形成位线隔离层，位线隔离层内具有沿着第一方向X延伸的沟槽，且多个沟槽在第二方向Y上排列。在沟槽中沉积金属以作为位线，对于相邻两条位线，其中一条作为第一位线BL1，另一条作为第二位线BL2。
下面将对晶体管组T的形成步骤进行详细说明。
具体地，在位线上沉积硅层，并采用原位掺杂或离子注入的方式对硅层进行掺杂处理。此后对硅层进行图形化处理，从而形成多个间隔设置的漏极区D。此后，在相邻漏极区D之间填充第一绝缘层(图中未示出)。位于第一位线BL1上表面的漏极区D作为后续形成的第一半导体柱21的漏极区D，位于第二位线BL2上表面的漏极区D作为后续形成的第二半导体柱22的漏极区D。
形成第一绝缘层后，通过外延生长工艺或者化学气相沉积工艺在漏极区D上形成沟道区C。与第一位线BL1正对的沟道区C作为后续形成的第一半导体柱21的沟道区C，与第二位线BL2正对的沟道区C作为后续形成的第二半导体柱22的沟道区C。
在沟道区C的顶面和侧壁形成初始栅介质层(图中未示出)，之后，形成与沟道区C相连的字线WL，即字线WL位于沟道区C的侧壁，并覆盖初始栅介质层。在相邻字线WL之间形成第二绝缘层，以隔离相邻字线WL。去除位于沟道区C顶面的初始栅介质层，剩余的初始栅介质层作为栅介质层。
在沟道区C的顶面形成源极区S，并在源极区S之间填充第三绝缘层(图中未示出)，有关源极区S的形成步骤可以参考前述形成漏极区D的步骤，在此不再赘述。
至此，可以形成晶体管组T。晶体管组T包括了间隔设置的第一半导体柱21和第二半导体柱22，以及与第一半导体柱21和第二半导体柱22的沟道区C相连的字线WL。第一半导体柱21和第二半导体柱22均具有在垂直于基底10的方向上排布的漏极区D、沟道区C和源极区S。其中，位于第一位线BL1上的漏极区D、沟道区C和源极区S作为第一半导体柱21，位于第二位线BL2上的漏极区D、沟道区C和源极区S作为第二半导体柱22。第一半导体柱21与字线WL构成第一晶体管T1；第二半导体柱22与字线WL构成第二晶体管T2。
需要说明的是，前述工艺步骤可以在基底10上形成多个存储单元4，存储单元4包括：一个第一晶体管T1、一个第二晶体管T2、一个电极层30和一个磁隧道结MTJ；同一存储单元4的第一晶体管T1和第二晶体管T2连接同一字线WL。由此，有利于减少字线WL的数量，以节 省在基底10上的面积，从而提高存储器的集成度。
在晶体管组T上形成电极层30。具体地，在阵列排布的晶体管组T上形成初始电极层，对初始电极层进行图形化处理以形成多个间隔设置的电极层30。电极层30与第一半导体柱21和第二半导体柱22的源极区S相连。示例地，电极层30的两端分别与第一半导体柱21和第二半导体柱22相连。此后，在相邻电极层30之间填充第四绝缘层(图中未示出)。
在电极层30上形成磁隧道结MTJ。具体地，在电极层30上依次沉积初始自由层、初始非磁性隔离层和初始固定层；此后，依次刻蚀部分初始自由层、部分初始非磁性隔离层和部分初始固定层，从而形成自由层FL、非磁性隔离层5、固定层PL，以构成多个间隔设置的磁隧道结MTJ。此后，还可以在相邻磁隧道结MTJ之间填充第五绝缘层(图中未示出)。
存储器的制造方法还包括：在磁隧道结MTJ上形成源极线SL。示例地，在磁隧道结MTJ上沉积一层金属以作为初始源极线，对初始源极线进行刻蚀可以形成源极线SL。
在一些实施例中，还可以先形成磁隧道结MTJ，此后再依次形成电极层30和晶体管组T。形成磁隧道结MTJ前，可以先在基底10上形成源极线SL；形成晶体管组T后，再形成间隔设置的第一位线BL1和第二位线BL2。
在另外一些实施例中，还可以将晶体管组T与磁隧道结MTJ形成在电极层30的同一侧。源极线SL、第一位线BL1和第二位线BL2可根据实际工艺进行制作顺序调整，保证源极线SL与磁隧道结MTJ的固定层PL连接，第一位线BL1与第一半导体柱21的漏极区D连接，第二位线BL2与第二半导体柱22的漏极区D连接即可。
综上所述，在基底10上形成垂直晶体管，并形成与同一存储单元4的两个垂直晶体管相连的字线WL，可以减小存储器的尺寸，并提高存储器的集成度。
在本说明书的描述中，参考术语“一些实施例”、“示例地”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含 于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本公开的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型，故但凡依本公开的权利要求和说明书所做的变化或修饰，皆应属于本公开专利涵盖的范围之内。

Claims (20)

  1. 一种存储器，其特征在于，包括：
    基底(10)，所述基底(10)上具有晶体管组(T)、电极层(30)、磁隧道结(MTJ)，所述晶体管组(T)、所述电极层(30)、所述磁隧道结(MTJ)在垂直所述基底(10)的方向上堆叠设置；
    所述晶体管组(T)包括间隔设置的第一半导体柱(21)和第二半导体柱(22)，所述第一半导体柱(21)和所述第二半导体柱(22)均具有在垂直于所述基底(10)的方向上排布的漏极区(D)、沟道区(C)和源极区(S)；
    所述晶体管组(T)还包括字线(WL)，所述字线(WL)与所述第一半导体柱(21)和第二半导体柱(22)的沟道区(C)相连；
    所述第一半导体柱(21)与所述字线(WL)构成第一晶体管(T1)；所述第二半导体柱(22)与所述字线(WL)构成第二晶体管(T2)；
    所述电极层(30)与所述第一半导体柱(21)和所述第二半导体柱(22)的所述源极区(S)相连。
  2. 根据权利要求1所述的存储器，其特征在于，
    所述字线(WL)环绕所述第一半导体柱(21)的沟道区(C)，并环绕所述第二半导体柱(22)的沟道区(C)。
  3. 根据权利要求1或2所述的存储器，其特征在于，所述晶体管组(T)、所述电极层(30)、所述磁隧道结(MTJ)依次在所述基底(10)上堆叠设置；或者，
    所述磁隧道结(MTJ)、所述电极层(30)、所述晶体管组(T)依次在所述基底(10)上堆叠设置；或者，
    所述晶体管组(T)和所述磁隧道结(MTJ)位于所述电极层(30)的同一侧。
  4. 根据权利要求1-3中任一项所述的存储器，其特征在于，还包括：间隔设置的第一位线(BL1)和第二位线(BL2)；所述第一半导体柱(21)位于所述第一位线(BL1)的上表面，所述第二半导体柱(22)位于第二位线(BL2)的上表面。
  5. 根据权利要求4所述的存储器，其特征在于，所述第一位线(BL1)的延伸方向和所述第二位线(BL2)的延伸方向均垂直于所述字线(WL)的 延伸方向。
  6. 根据权利要求4或5所述的存储器，其特征在于，还包括：源极线(SL)，所述源极线(SL)位于所述磁隧道结(MTJ)的上表面。
  7. 根据权利要求6所述的存储器，其特征在于，所述源极线(SL)的延伸方向平行于所述第一位线(BL1)的延伸方向和第二位线(BL2)的延伸方向。
  8. 根据权利要求6或7所述的存储器，其特征在于，
    多个所述第一半导体柱(21)在所述基底(10)上阵列排布，多个所述第二半导体柱(22)在所述基底(10)上阵列排布；所述字线(WL)为多条，且同一所述字线(WL)相连的多个所述第一半导体柱(21)和多个所述第二半导体柱(22)交替排列；
    多条所述字线(WL)相互平行，多条所述第一位线(BL1)相互平行，多条所述第二位线(BL2)相互平行，多条所述源极线(SL)相互平行；
    多条所述第一位线(BL1)和多条所述第二位线(BL2)交替排列。
  9. 根据权利要求6-8中任一项所述的存储器，其特征在于，所述磁隧道结(MTJ)包括层叠设置的自由层(FL)、非磁性隔离层(5)和固定层(PL)；所述自由层(FL)与所述电极层(30)相连，所述固定层(PL)与所述源极线(SL)相连。
  10. 根据权利要求1-9中任一项所述的存储器，其特征在于，一个所述第一晶体管(T1)、一个所述第二晶体管(T2)、一个所述电极层(30)和一个所述磁隧道结(MTJ)用于构成存储单元(4)；同一所述存储单元(4)的所述第一晶体管(T1)和所述第二晶体管(T2)共同一所述字线(WL)。
  11. 一种存储器的读写方法，其特征在于，用于对权利要求1-10中任一项所述存储器进行读写操作；
    对所述存储器进行写操作，包括：向所述字线(WL)提供开启信号，以打开所述第一晶体管(T1)和所述第二晶体管(T2)；提供第一电流(I1)，所述第一电流(I1)流经所述第一晶体管(T1)、所述电极层(30)和所述第二晶体管(T2)；
    对所述存储器进行读操作，包括：向所述字线(WL)提供开启信号，以打开所述第一晶体管(T1)和所述第二晶体管(T2)；提供第二电流(I2)， 所述第二电流(I2)流经所述磁隧道结(MTJ)和所述电极层(30)。
  12. 根据权利要求11所述的存储器的读写方法，其特征在于，在所述磁隧道结(MTJ)为垂直磁隧道结时，对所述存储器进行写操作，还包括：提供第三电流(I3)；所述第三电流(I3)流经所述磁隧道结(MTJ)、所述电极层(30)和所述第一晶体管(T1)，或者，所述第三电流(I3)流经所述磁隧道结(MTJ)、所述电极层(30)和所述第二晶体管(T2)。
  13. 根据权利要求12所述的存储器的读写方法，其特征在于，
    所述存储器还包括：间隔设置的第一位线(BL1)和第二位线(BL2)；所述第一半导体柱(21)位于所述第一位线(BL1)的上表面，所述第二半导体柱(22)位于第二位线(BL2)的上表面；所述存储器还包括：位于所述磁隧道结(MTJ)的上表面的源极线(SL)；
    在所述磁隧道结(MTJ)为垂直磁隧道结时，对所述存储器进行写操作，包括：所述第一位线(BL1)和所述第二位线(BL2)中的一者提供高电平，另一者提供低电平，所述源极线(SL)提供高电平或低电平，以形成所述第一电流(I1)和所述第三电流(I3)。
  14. 根据权利要求11所述的存储器的读写方法，其特征在于，
    所述存储器还包括：间隔设置的第一位线(BL1)和第二位线(BL2)；所述第一半导体柱(21)位于所述第一位线(BL1)的上表面，所述第二半导体柱(22)位于第二位线(BL2)的上表面；所述存储器还包括：位于所述磁隧道结(MTJ)的上表面的源极线(SL)；
    在所述磁隧道结(MTJ)为平行磁隧道结时，对所述存储器进行写操作，包括：所述第一位线(BL1)和所述第二位线(BL2)中的一者提供高电平，另一者提供低电平，以形成所述第一电流(I1)。
  15. 根据权利要求11-14中任一项所述的存储器的读写方法，其特征在于，所述存储器还包括：间隔设置的第一位线(BL1)和第二位线(BL2)；所述第一半导体柱(21)位于所述第一位线(BL1)的上表面，所述第二半导体柱(22)位于第二位线(BL2)的上表面；所述存储器还包括：位于所述磁隧道结(MTJ)的上表面的源极线(SL)；
    对所述存储器进行读操作，包括：所述第一位线(BL1)向所述第一晶体管(T1)的所述漏极区(D)提供低电平，所述第二位线(BL2)向所述第二晶 体管(T2)的所述漏极区(D)提供低电平，所述源极线(SL)向所述磁隧道结(MTJ)远离所述基底(10)的一侧提供高电平，以形成所述第二电流(I2)。
  16. 根据权利要求11-15中任一项所述的存储器的读写方法，其特征在于，一个所述第一晶体管(T1)、一个所述第二晶体管(T2)、一个所述电极层(30)和一个所述磁隧道结(MTJ)用于构成存储单元(4)；同一所述存储单元(4)的所述第一晶体管(T1)和所述第二晶体管(T2)连接同一字线(WL)；
    在读操作和写操作过程中，所述字线(WL)同时向同一所述存储单元(4)的所述第一晶体管(T1)和所述第二晶体管(T2)提供开启信号。
  17. 一种存储器的制造方法，其特征在于，包括：
    提供基底(10)，在所述基底(10)上形成晶体管组(T)、电极层(30)、磁隧道结(MTJ)，所述晶体管组(T)、所述电极层(30)、所述磁隧道结(MTJ)在垂直所述基底(10)的方向上堆叠设置；
    形成所述晶体管组(T)包括：形成间隔设置的第一半导体柱(21)和第二半导体柱(22)，所述第一半导体柱(21)和所述第二半导体柱(22)均具有在垂直于所述基底(10)的方向上排布的漏极区(D)、沟道区(C)和源极区(S)；
    形成所述晶体管组(T)还包括：形成字线(WL)，所述字线(WL)与所述第一半导体柱(21)和第二半导体柱(22)的沟道区(C)相连；
    所述第一半导体柱(21)与所述字线(WL)构成第一晶体管(T1)；所述第二半导体柱(22)与所述字线(WL)构成第二晶体管(T2)；
    所述电极层(30)与所述第一半导体柱(21)和所述第二半导体柱(22)的所述源极区(S)相连。
  18. 根据权利要求17所述的存储器的制造方法，其特征在于，
    在所述基底(10)上依次形成堆叠设置的所述晶体管组(T)、所述电极层(30)、所述磁隧道结(MTJ)；或者，
    在所述基底(10)上依次形成堆叠设置的所述磁隧道结(MTJ)、所述电极层(30)、所述晶体管组(T)；或者，
    将所述晶体管组(T)和所述磁隧道结(MTJ)形成在所述电极层(30)的同一侧；
    在形成所述晶体管组(T)之前，还包括：在所述基底(10)上形成间隔设置的第一位线(BL1)和第二位线(BL2)；所述第一半导体柱(21)形成于所述第一位线(BL1)的上表面，所述第二半导体柱(22)形成于所述第二位线(BL2)的上表面；
    所述存储器的制造方法还包括：在所述磁隧道结(MTJ)上形成源极线(SL)。
  19. 根据权利要求17或18所述的存储器的制造方法，其特征在于，形成环绕所述第一半导体柱(21)和所述第二半导体柱(22)的沟道区(C)的所述字线(WL)。
  20. 根据权利要求17-19中任一项所述的存储器的制造方法，其特征在于，在所述基底(10)上形成多个存储单元(4)，所述存储单元(4)包括：一个所述第一晶体管(T1)、一个所述第二晶体管(T2)、一个所述电极层(30)和一个所述磁隧道结(MTJ)；同一所述存储单元(4)的所述第一晶体管(T1)和所述第二晶体管(T2)共用同一所述字线(WL)。
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