WO2022142097A1 - 磁性存储器及其读写方法 - Google Patents

磁性存储器及其读写方法 Download PDF

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Publication number
WO2022142097A1
WO2022142097A1 PCT/CN2021/095841 CN2021095841W WO2022142097A1 WO 2022142097 A1 WO2022142097 A1 WO 2022142097A1 CN 2021095841 W CN2021095841 W CN 2021095841W WO 2022142097 A1 WO2022142097 A1 WO 2022142097A1
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Prior art keywords
wire
magnetic
plane
layer
magnetic memory
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PCT/CN2021/095841
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English (en)
French (fr)
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吴保磊
王晓光
吴玉雷
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长鑫存储技术有限公司
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Priority to US17/480,357 priority Critical patent/US20220208853A1/en
Publication of WO2022142097A1 publication Critical patent/WO2022142097A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/10—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having two electrodes, e.g. diodes or MIM elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1659—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1693—Timing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details

Definitions

  • the present application relates to the field of integrated circuits, and in particular, to a magnetic memory and a method for reading and writing the same.
  • MRAM Magneticoresistive Random Access Memory
  • SRAM static random access memory
  • DRAM volatile dynamic random access memory
  • NVM non-volatile memory
  • the core of the MRAM element is a magnetic tunnel junction (MTJ), which may include a fixed magnetic layer and a free magnetic layer.
  • the magnetization polarity of the fixed magnetic layer cannot be changed, and the magnetization polarity of the free magnetic layer can be changed. Due to the tunneling magnetoresistance effect, the resistance value between the fixed magnetic layer and the free magnetic layer changes as the magnetization polarity is switched in the free magnetic layer, thereby realizing the writing of the magnetic memory.
  • memory density is one of the key limiting factors to push MRAM into the main memory/storage market, so how to increase the density of magnetic memory is an urgent problem to be solved.
  • the technical problem to be solved by the present application is to provide a high-density magnetic memory and a reading and writing method thereof.
  • the present application provides a magnetic memory, which includes at least one unit layer, the unit layer includes: a plurality of parallel first wires located in the first plane; a plurality of parallel second wires located in the first plane In a second plane, and the first plane is parallel to the second plane, the projection of the second wire on the first plane intersects the first wire; a plurality of storage elements are arranged on the Between the first plane and the second plane, the storage element includes a magnetic tunnel junction and a bidirectional gate device arranged in series along a direction perpendicular to the first plane, the magnetic tunnel junction is connected to the first wire, The bidirectional gating device is connected to the second wire, the bidirectional gating device being configured to conduct when a threshold voltage and/or a threshold current is applied.
  • the magnetic tunnel junction includes: a free layer connected to the first wire; a non-magnetic insulating layer arranged on the upper surface of the free layer; a fixed layer arranged on the upper surface of the non-magnetic insulating layer, the The direction of the magnetic moment of the free layer is variable, and the direction of the magnetic moment of the fixed layer is fixed; one end of the bidirectional gating device is connected to the fixed layer, and the other end is connected to the second wire.
  • the first wire includes a first end and a second end
  • the magnetic memory further includes a plurality of write bit lines and a plurality of first selection transistors, the first selection transistors being configured to respond to a first control A signal is used to electrically connect the first end of the first wire and the write bit line.
  • the magnetic memory further includes a source line, the source line is electrically connected to the second end of the first wire.
  • the magnetic memory further includes a plurality of bit lines and a plurality of second selection transistors, the second selection transistors being configured to electrically connect the second conductive lines and the bit lines in response to a second control signal.
  • the projection of the second wire on the first plane intersects the first wire perpendicularly.
  • the magnetic memory includes a plurality of the unit layers, the plurality of the unit layers are arranged in sequence along the direction perpendicular to the first plane, and the adjacent unit layers are connected to the same wire, wherein the wire is in the upper unit layer It is used as the first wire in the middle and the second wire in the lower unit layer.
  • the magnetic memory includes a plurality of the unit layers, the plurality of the unit layers are arranged in sequence along the direction perpendicular to the first plane, and the adjacent unit layers are connected to the same wire, wherein the wire is in the upper unit layer and the lower unit layer are used as the first wire or the second wire.
  • the material of the bidirectional gating device is doped hafnium oxide.
  • the present application also provides a method for reading and writing a magnetic memory.
  • the magnetic memory includes at least one unit layer, and the unit layer includes: a plurality of parallel first wires located in a first plane; a plurality of parallel second wires , located in the second plane, and the first plane is parallel to the second plane, and the projection of the second wire on the first plane intersects the first wire; a number of storage elements are arranged in Between the first plane and the second plane, the storage element includes a magnetic tunnel junction and a bidirectional gate device arranged in series along a direction perpendicular to the first plane, the magnetic tunnel junction and the first wire connected, the bidirectional gating device is connected to the second wire, the bidirectional gating device is configured to conduct when a threshold voltage and/or a threshold current is applied;
  • the read-write method comprises: supplying a first current to the magnetic memory, the first current flowing through the first wire but not through the storage element, so that the storage element is in a first storage state; A second current is provided to the magnetic memory, the second current flowing through the selected storage element to cause the selected storage element to change from the first storage state to the second storage state.
  • the magnetic tunnel junction includes: a free layer connected to the first wire; a non-magnetic insulating layer arranged on the upper surface of the free layer; a fixed layer arranged on the upper surface of the non-magnetic insulating layer, the The direction of the magnetic moment of the free layer is variable, and the direction of the magnetic moment of the fixed layer is fixed; one end of the bidirectional gating device is connected to the fixed layer, and the other end is connected to the second wire; the read-write method includes: : The first current and the second current cause the direction of the magnetic moment of the free layer to change in opposite directions.
  • the first current changes the direction of the magnetic moment of the free layer in a direction opposite to the direction of the magnetic moment of the pinned layer
  • the second current causes the direction of the magnetic moment of the free layer to be opposite to the direction of the magnetic moment of the pinned layer.
  • the direction of the magnetic moment of the pinned layer changes in the same direction.
  • the first current changes the direction of the magnetic moment of the free layer in the same direction as the direction of the magnetic moment of the pinned layer
  • the second current causes the direction of the magnetic moment of the free layer to be in the same direction as the direction of the magnetic moment of the pinned layer.
  • the direction in which the direction of the magnetic moment of the pinned layer is reversed is changed.
  • the first wire includes a first end and a second end
  • the magnetic memory further includes a plurality of write bit lines and a plurality of first selection transistors, the first selection transistors being configured to respond to a first control
  • the first end of the first wire and the write bit line are electrically connected by a signal;
  • the read and write method includes: controlling the first selection transistor through the first control signal to make the first selection transistor In response to the first control signal, a first end of the first wire and the write bit line are electrically connected so that the first current flows through the first wire.
  • the magnetic memory further includes a source line
  • the source line can be electrically connected to the second end of the first wire
  • the read/write method includes: the first current flows from the write bit line Via the first wire to the source line, or the first current flows from the source line to the write bit line through the first wire.
  • the magnetic memory further includes a plurality of bit lines and a plurality of second selection transistors, the second selection transistors being configured to electrically connect the second conductive lines and the bit lines in response to a second control signal; the The read/write method includes: controlling the second selection transistor through a second control signal, so that the second selection transistor is electrically connected to the second wire and the bit line in response to the second control signal, so that all The second current flows through the selected storage element.
  • the read/write method further includes: during a read operation, supplying a third current to the magnetic memory, the third current flows from the second wire to the first wire through the storage element.
  • different storage elements are controlled by the bidirectional gate device as control switches to realize separate control; in the step of supplying the second current to the magnetic memory, the selected storage element is configured to be applied to the bidirectional gate device Storage element at threshold voltage and/or threshold current.
  • the advantage of the present application is that the traditional magnetic memory design is changed, and the storage density of the magnetic field memory is greatly improved.
  • FIG. 1 is a schematic structural diagram of a magnetic memory according to a first embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a magnetic memory according to a second embodiment of the present application.
  • Fig. 3 is the front view of the structure shown in Fig. 2;
  • FIG. 4 is a front view of a magnetic memory according to a third embodiment of the present application.
  • FIG. 5 is a front view of a magnetic memory according to a fourth embodiment of the present application.
  • FIG. 6 is a front view of a magnetic memory according to a fifth embodiment of the present application.
  • FIG. 7 is a timing chart of a method for reading and writing a magnetic memory according to a sixth embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a magnetic memory according to a first embodiment of the present application. Please refer to FIG. 1 .
  • the magnetic memory of the present application includes at least one unit layer 100 .
  • the magnetic memory includes one cell layer 100 .
  • the cell layer 100 includes a plurality of parallel first wires 110 , a plurality of parallel second wires 120 and a plurality of storage elements 130 .
  • the number of the first wires 110, the second wires 120 and the storage elements 130 can be set according to the storage requirements of the magnetic memory.
  • FIG. 1 only two parallel first wires 110 , three parallel second wires 120 and six storage elements 130 are schematically shown, which do not constitute a limitation to the present application.
  • the first wires 110 are located in a first plane (not shown in the figure).
  • the first wires 110 extend along the X direction and are arranged in parallel along the Y direction, so the first plane is an XY plane.
  • the second wire 120 is located in a second plane (not shown in the figure), and the first plane is parallel to the second plane.
  • the second wires 120 extend along the Y direction and are arranged in parallel along the X direction, then the second plane is also an XY plane, and the first plane and the second plane are parallel flat.
  • the projection of the second wire 120 on the first plane intersects the first wire 110, or in other words, the projection of the first wire 110 on the second plane intersects the second wire 120 cross.
  • the projection of the second wire 120 on the first plane intersects the first wire 110, or in other words, in the direction perpendicular to the second plane
  • the projection of the first wire 110 on the second plane intersects with the second wire 120 . Since the first plane and the second plane are parallel, the first wire 110 and the second wire 120 do not directly intersect, but the projections of the two intersect on a certain plane.
  • the projection of the second wire 120 on the first plane intersects the first wire 110 perpendicularly, while in other embodiments of the present application, the second wire 120 is located at the The projection on the first plane and the first wire 110 do not intersect vertically, but intersect at an acute angle or an obtuse angle.
  • the first wire 110 and the second wire 120 can be made of the following materials: heavy metals (eg, Pt, Ta, etc.), semi-metallic Metal (eg, MoTe 2 ) or chalcogenide (eg, Bi x Te 1-x ).
  • heavy metals eg, Pt, Ta, etc.
  • semi-metallic Metal eg, MoTe 2
  • chalcogenide eg, Bi x Te 1-x
  • Each of the storage elements 130 is disposed between the first plane and the second plane. That is, a plurality of the storage elements 130 are disposed in the interlayer formed by the first plane and the second plane.
  • Each of the storage elements 130 includes a magnetic tunnel junction 131 and a bidirectional gate device 132 arranged in series along a direction perpendicular to the first plane.
  • the storage element 130 is disposed at the intersection of the first wire 110 and the second wire 120, the magnetic tunnel junction 131 is connected to the first wire 110, and the bidirectional The gating device 132 is connected to the second wire 120 .
  • the positions of the magnetic tunnel junction 131 and the bidirectional gating device 132 can also be interchanged, that is, the magnetic tunnel junction 131 is connected to the second wire 120 , and the bidirectional gating device 132 is The pass device 132 is connected to the first wire 110 .
  • the bidirectional gating device 132 is configured to be turned on when a threshold voltage and/or a threshold current is applied.
  • the conduction refers to the transition of the bidirectional gate device 132 from a high-resistance state to a low-resistance state.
  • the bidirectional gate device 132 changes from a high resistance state to a low resistance state state, so as to realize the electrical connection between the magnetic tunnel junction 131 and the second wire 120 .
  • the threshold voltage or current depends on the material properties of the magnetic tunnel junction 131 .
  • the material of the bidirectional gate device 132 is doped hafnium oxide, and its turn-on threshold voltage is 0.25V.
  • the voltage applied to the bidirectional gate device 132 is 0.25V or more
  • the bidirectional gate device 132 is turned on, and when the voltage applied to the bidirectional gate device 132 is less than 0.25V, the bidirectional gate device 132 is not turned on.
  • Doped hafnium oxide has high on/off ratio and low on-resistance, and is an ideal material for bidirectional gated devices.
  • other materials that can realize the threshold conduction function can also be used as the material of the bidirectional gate device 132 , and the present application is not limited to this.
  • the bidirectional gate device 132 can be turned on when a threshold voltage and/or a threshold current is applied, different storage elements 130 can be used as control switches through the bidirectional gate device to realize separate control of the storage elements 130 . Specifically, if one or some storage elements 130 need to be operated, the bidirectional gate device 132 corresponding to the one or some storage elements 130 can be controlled to be turned on, while other non-selected storage elements 130 can be controlled to be turned on.
  • the corresponding bidirectional strobe device 132 is non-conductive, thereby realizing selective operation of the storage element 130 .
  • the magnetic tunnel junction 131 includes a free layer 131A connected to the first wire 110 , a non-magnetic insulating layer 131B disposed on the upper surface of the free layer 131A, and a non-magnetic insulating layer 131B disposed on the upper surface of the non-magnetic insulating layer 131B.
  • Fixed layer 131C The direction of the magnetic moment of the free layer 131A is variable, and the direction of the magnetic moment of the fixed layer 131c is fixed. Due to the tunnel magnetoresistance effect, the resistance value between the pinned layer 31C and the free layer 131A changes as the direction of the magnetic moment in the free layer 131A is switched, thereby realizing the writing of the magnetic memory.
  • One end of the bidirectional gating device 132 is connected to the fixed layer 131C, and the other end is connected to the second wire 120 .
  • the first end and the second end of the bidirectional gating device 132 are only provided for the convenience of description.
  • the bidirectional gating device 132 there is no difference between the first end and the second end, that is, the Either end of the bidirectional gate device 132 may be connected to the fixed layer 131C.
  • the magnetic memory of the present application changes the traditional magnetic memory design, and greatly improves the storage density of the magnetic field memory.
  • the first wire 110 includes a first end and a second end.
  • the magnetic memory also includes several write bit lines WBL and several first select transistors WWL.
  • the first selection transistor WWL is configured to electrically connect the first end of the first wire 110 and the write bit line WBL in response to a first control signal.
  • FIG. 1 is the write bit line WBL[00] and the write bit line WBL[01], respectively, The first selection transistor WWL[00] and the first selection transistor WWL[01].
  • the first select transistor WWL[00] is configured to electrically connect the first end of the first wire 110 and the write bit line WBL[00] in response to a first control signal
  • the first select transistor WWL[01] is configured to electrically connect the first end of the other first wire 110 and the write bit line WBL[01] in response to a first control signal.
  • the magnetic memory further includes a source line WSL, and the source line WSL is electrically connected to the second end of the first wire 110 , for example, through a transistor switch.
  • a source line WSL is electrically connected to the second end of the first wire 110 , for example, through a transistor switch.
  • FIG. 1 only two source lines WSL are schematically shown in FIG. 1 , which are the source line WSL[00] and the source line WSL[01], respectively.
  • the source line WSL[ 00 ] is electrically connected to the second end of the first wire 110
  • the source line WSL[ 01 ] is electrically connected to the second end of the other first wire 110 .
  • the magnetic memory further includes a plurality of bit lines BBL and a plurality of second selection transistors BWL, and the second selection transistors BWL are configured to electrically connect the second wire 120 and the second wire 120 in response to a second control signal.
  • bit line BBL bit line
  • FIG. 1 bit line BBL[00], bit line BBL[01], bit line BBL[02], The second selection transistor BWL[00], the second selection transistor BWL[01], and the second selection transistor BWL[02].
  • the second selection transistor BWL[00] is configured to electrically connect the second wire 120 and the bit line BBL[00] in response to a second control signal
  • the second selection transistor BWL[01] is configured To electrically connect the second wire 120 and the bit line BBL[01] in response to a second control signal
  • the second selection transistor BWL[02] is configured to electrically connect the bit line BBL[02] in response to a second control signal
  • the second wire 120 is connected to the bit line BBL[02].
  • the present application also provides a second embodiment.
  • the difference between the second embodiment and the first embodiment is that the second embodiment includes a plurality of unit layers, and the unit layers are stacked.
  • FIG. 2 is a schematic structural diagram of a magnetic memory according to a second embodiment of the present application
  • FIG. 3 is a front view of the structure shown in FIG. 2 .
  • the magnetic memory includes a plurality of unit layers, and the plurality of unit layers are arranged in sequence along a direction perpendicular to the first plane.
  • the magnetic memory includes two unit layers, respectively an upper unit layer 100A and a lower unit layer 100B, and the upper unit layer 100A and the lower unit layer 100B are arranged in sequence along a direction perpendicular to the first plane.
  • the adjacent unit layers are connected to the same wire, and the wire is used as the first wire in the upper unit layer 100A and used as the second wire in the lower unit layer 100B.
  • the upper unit layer 100A and the lower unit layer 100B are adjacent unit layers, and their shared wires are wires 200 .
  • the wire 200 is connected to the magnetic tunnel junction 131 of the storage element 130. Therefore, in the upper unit layer 100A, the wire 200 serves as the first wire, and in the lower unit layer 100B, the The conducting wire 200 is connected to the bidirectional gating device 132 . Therefore, in the lower unit layer 100B, the conducting wire 200 serves as the second conducting wire.
  • the magnetic memory only includes two unit layers, while in other embodiments of the present application, in order to further improve the storage density of the magnetic memory, the magnetic memory may include a plurality of unit layers, and a plurality of the unit layers They are arranged in sequence along the direction perpendicular to the first plane.
  • FIG. 4 is a front view of the magnetic memory according to the third embodiment of the present application.
  • the magnetic memory may include a plurality of unit layers, and the plurality of the unit layers are perpendicular to the first The directions of the planes are set sequentially. 4 schematically illustrates five unit layers, namely unit layer 100A, unit layer 100B, unit layer 100C, unit layer 100D and unit layer 100E, the five unit layers are along the direction perpendicular to the first plane Set in sequence.
  • adjacent unit layers are connected to the same wire, and the wire is used as the first wire in the upper unit layer and used as the second wire in the lower unit layer.
  • the unit layer 100A is adjacent to the unit layer 100B, and the two are connected to the wire 200.
  • the wire 200 is used as the first wire.
  • the The wire 200 is used as the second wire; the unit layer 100B is adjacent to the unit layer 100C, and both are connected to the wire 300, then in the unit layer 100B, the wire 300 is used as the first wire, and in the unit layer 100C, all The wire 300 is used as the second wire; the unit layer 100C is adjacent to the unit layer 100D, and both are connected to the wire 400, then in the unit layer 100C, the wire 400 is used as the first wire, and in the unit layer 100D, all The wire 400 is used as the second wire; the unit layer 100D is adjacent to the unit layer 100E, and both are connected to the wire 500, then in the unit layer 100D, the wire 500 is used as the first wire, and in the unit layer 100E, all The wire 500 is used as the second wire.
  • the bidirectional gate devices 132 of the memory cells 130 of all the unit layers are located above the magnetic tunnel junctions 131, so that the wires that are commonly connected to the adjacent unit layers are in the upper unit layer. It is used as the first wire, and is used as the second wire in the lower unit layer.
  • the bidirectional gate device 132 of the storage unit 130 may also be located below the magnetic tunnel junction 131 , and the principle is the same as that of the second and third embodiments, and will not be repeated here.
  • connection relationship between the wires that are commonly connected to the adjacent unit layers and the storage element 130 is different in the two layers, that is, the wires that are shared by the adjacent unit layers are in the two layers. function is different.
  • Another embodiment of the present application also provides a magnetic memory, which is different from the second embodiment in that the wires that are commonly connected to adjacent cell layers have the same connection relationship with the storage element 130 in the two layers, that is, adjacent cell layers have the same connection relationship with the storage element 130.
  • Wires common to the cell layers function the same in both layers. That is, the wires shared by adjacent unit layers are used as the first wires or the second wires in both the upper unit layer and the lower unit layer.
  • FIG. 5 is a front view of the magnetic memory according to the fourth embodiment of the present application.
  • the magnetic memory includes two unit layers, respectively an upper unit layer 100A and a lower unit layer 100B, and the upper unit layer 100A and the lower unit layer 100B are sequentially arranged along a direction perpendicular to the first plane.
  • the upper unit layer 100A and the lower unit layer 100B are connected to the same wire, and the wire is used as the first wire or the second wire in both the upper unit layer 100A and the lower unit layer 100B.
  • the wires shared by the upper unit layer 100A and the lower unit layer 100B are wires 200 .
  • the wire 200 is connected to the magnetic tunnel junction 131 of the storage element 130. Therefore, in the upper unit layer 100A, the wire 200 is used as the first wire, and in the lower unit layer 100B, The conducting wire 200 is connected to the magnetic tunnel junction 131 of the storage element 130 . Therefore, in the lower cell layer 100B, the conducting wire 200 is also used as a first conducting wire.
  • the storage elements of each layer can also be reversed, so that the wires 200 are respectively connected with the magnetic tunnel junctions 131 of the storage elements of the upper unit layer 100A and the lower unit layer 100B, and the wires 200 serve as all the The second wire is used.
  • the magnetic memory only includes two unit layers, while in other embodiments of the present application, in order to further improve the storage density of the magnetic memory, the magnetic memory may include a plurality of unit layers, and a plurality of the unit layers They are arranged in sequence along the direction perpendicular to the first plane.
  • FIG. 6 is a front view of a magnetic memory according to a fifth embodiment of the present application.
  • the magnetic memory may include a plurality of unit layers, and a plurality of the unit layers are perpendicular to the first The directions of the planes are set sequentially. 6 schematically illustrates five unit layers, namely unit layer 100A, unit layer 100B, unit layer 100C, unit layer 100D and unit layer 100E, the five unit layers are along the direction perpendicular to the first plane Set in sequence.
  • adjacent unit layers are commonly connected to the same wire, and the wire is used as the first wire or the second wire in the upper unit layer and the lower unit layer.
  • the unit layer 100A is adjacent to the unit layer 100B, and the two are connected to the wire 200 together, then in the unit layer 100A, the wire 200 is used as the first wire, and in the unit layer 100B, the The wire 200 is also used as the first wire; the unit layer 100B is adjacent to the unit layer 100C, and both of them are connected to the wire 300.
  • the wire 300 is used as the second wire.
  • the wire 300 is used as the second wire.
  • the wire 300 is also used as the second wire; the unit layer 100C is adjacent to the unit layer 100D, and the two are connected to the wire 400 together, then in the unit layer 100C, the wire 400 is used as the first wire, and in the unit layer 100D , the wire 400 is also used as the first wire; the unit layer 100D is adjacent to the unit layer 100E, and the two are connected to the wire 500 together, then in the unit layer 100D, the wire 500 is used as the second wire. , the wire 500 is also used as a second wire.
  • the direction of the memory cells 130 in each layer can also be reversed, and the connection relationship between the magnetic tunnel junction and the bidirectional gating device and the common wire can be changed.
  • the connection principle is the same as the fifth one. The embodiments are the same and will not be repeated here.
  • the mutual positional relationship between the first wire, the memory cell and the second wire is only schematically shown.
  • the first wire, the memory cell and the second wire are Insulation materials or other structural materials will also be filled in the blanks other than the two conductors, which will not be repeated here.
  • FIG. 7 is a timing diagram of a method for reading and writing a magnetic memory according to a sixth embodiment of the present application.
  • the reading and writing methods of the present application include;
  • Erase operation (Eraser): a first current Ieraser is provided to the magnetic memory, the first current Ieraser flows through the first wire 110 but not through the storage element 130, so that the storage element 130 is in the first storage state.
  • the first current Ieraser only flows through the first wire 110 , and the first current Ieraser acts on the magnetic tunnel junction 131 through the first wire 110 , so that the free layer 131A of the magnetic tunnel junction 131 is
  • the direction of the magnetic moment is changed to the same direction, for example, the same or opposite to the direction of the magnetic moment of the pinned layer 131C.
  • all memory cells connected to the first wire 110 are in the same storage state, that is, the first storage state.
  • the first storage state may store "0" or store "1".
  • the direction of the magnetic moment of the free layer 131A is opposite to the direction of the magnetic moment of the pinned layer 131C, that is, the first storage state is storage "1" , which can make it only need to modify the storage "1" to the storage "0" during the write operation, which greatly reduces the loss of the magnetic tunnel junction.
  • the storage state "1" can also be expressed as the direction of the magnetic moment of the free layer 131A is the same as the direction of the magnetic moment of the pinned layer 131C, which can be designed by those skilled in the art as required.
  • the first selection transistor WWL is controlled by the first control signal, so that the first selection transistor WWL is electrically connected to the first wire 110 in response to the first control signal terminal and the write bit line WBL, the write bit line WBL is at a high level, the source line WSL is at a low level, and the first current Ieraser flows from the write bit line WBL through the The first wire 110 to the source line WSL.
  • the write bit line WBL is at a low level
  • the source line WSL is at a high level
  • the first current Ieraser flows from the source line WSL through the The first wire 110 to the write bit line WBL.
  • Write operation (Write): a second current Iwrite is provided to the magnetic memory, and the second current Iwrite flows through the selected storage element, so that the selected storage element changes from the first storage state to the second storage state .
  • the bidirectional gating device 132 is controlled by the bidirectional gating device 132 as control switches to realize separate control.
  • the selected storage element is configured as the storage element for which the bidirectional gating device 132 is applied with a threshold voltage and/or a threshold current. That is to say, in this step, if a certain storage element 130 needs to be operated, the bidirectional gate device 132 of the storage element 130 is placed in a conducting state, so as to realize the storage element 130 and the first wire 110 and the second wire. 120 electrical connections.
  • the second current Iwrite flows through the storage element 130, the second current Iwrite will change the direction of the magnetic moment of the free layer 131A, so that the direction of the magnetic moment of the free layer 131A is the same as the direction of the magnetic moment of the free layer 131A.
  • the directions of the magnetic moments of the pinned layer 131C are the same or opposite.
  • first current Ieraser and the second current Iwrite make the direction of change of the magnetic moment of the free layer opposite.
  • the first current Ieraser changes the direction of the magnetic moment of the free layer 131A in a direction opposite to the direction of the magnetic moment of the pinned layer 131C
  • the first The second current Iwrite changes the direction of the magnetic moment of the free layer 131A in the same direction as the direction of the magnetic moment of the pinned layer 131C, that is, the first storage state is “1”, and the second storage state is Store "0".
  • the first current Ieraser changes the magnetic moment direction of the free layer 131A to the same direction as the magnetic moment direction of the pinned layer 131C
  • the The second current Iwrite changes the direction of the magnetic moment of the free layer 131A in a direction opposite to the direction of the magnetic moment of the pinned layer 131C, that is, the first storage state is storage “0”, and the second storage state to store "1".
  • storing "0" can also be expressed as the direction of the magnetic moment of the free layer 131A is opposite to the direction of the magnetic moment of the fixed layer 131C, and the same is true for storing "1".
  • the second selection transistor BWL is controlled by a second control signal, so that the second selection transistor BWL is electrically connected to the second wire 120 and the bit line in response to the second control signal BBL, the second current Iwrite flows through the selected storage element 130, so as to achieve the purpose of changing the storage state of the storage element 130 from the first storage state to the second storage state.
  • the second selection transistor BWL is controlled to be turned on by a second control signal, the bit line BBL is at a low level, the source line WSL is at a high level, and the second current Iwrite flows from the source line WSL from The first wire 110 flows to the bit line BBL through the storage element 130 and the second wire 120 .
  • the bit line BBL is at a high level
  • the source line WSL is at a low level
  • the second current Iwrite flows from the bit line BBL from the second wire 120 through the storage element 130
  • the second current Iwrite A wire 110 flows to the source line WSL.
  • the present application also provides a read operation of the magnetic memory.
  • a third current Iread is supplied to the magnetic memory, and the third current Iread flows from the second wire 120 to the first wire 110 through the storage element 130 .
  • the bidirectional gating device 132 As control switches to realize separate control.
  • this read operation step if a certain storage element 130 needs to be read, its bidirectional gate device 132 is placed in a conducting state, and the bidirectional gate devices 132 of other storage elements 130 are placed in a non-conducting state , so as to realize the independent operation of the storage element 130 to prevent other storage elements 130 from affecting the read operation.
  • the third current Iread passes through the storage element 130, a potential difference will be generated across the storage element 130, and the resistance of the storage element 130 can be determined according to the magnitude of the potential difference, thereby obtaining
  • the orientation relationship of the magnetic moment directions of the free layer 131A and the pinned layer 131C of the magnetic tunnel junction can further realize the reading of the storage state of the storage element 130 .
  • the storage state of the storage element 130 can also be determined according to the magnitude of the third current Iread, which can be designed by those skilled in the art as required.
  • the second selection transistor BWL is controlled to be turned on by a third control signal, so that the second selection transistor BWL is electrically connected to the second wire 120 and the bit in response to the third control signal.
  • the line BBL allows the third current I read to flow through the selected storage element 130 , thereby obtaining the storage state of the storage element 130 .
  • the read/write method is the same as that of a single layer, and will not be repeated here.

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Abstract

本申请提供一种磁性存储器及其读写方法，磁性存储器包括至少一单元层，所述单元层包括：若干条平行的第一导线，位于第一平面内；若干条平行的第二导线，位于第二平面内，且所述第一平面与所述第二平面平行，所述第二导线在所述第一平面上的投影与所述第一导线交叉；若干个存储元件，设置在所述第一平面与所述第二平面之间，所述存储元件包括沿垂直所述第一平面方向串联设置的磁隧道结及双向选通器件，所述磁隧道结与所述第一导线连接，所述双向选通器件与所述第二导线连接，所述双向选通器件被配置为在被施加阈值电压和/或阈值电流时导通。本申请磁性存储器改变了传统的磁性存储器设计，大大提高了磁场存储器的存储密度。

Description

磁性存储器及其读写方法
交叉引用
本申请基于申请号为202011596090.7、申请日为2020年12月29日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及集成电路领域，尤其涉及一种磁性存储器及其读写方法。
背景技术
MRAM(Magnetoresistive Random Access Memory)是一种非易失性的磁性存储器，其提供与易失性静态随机存取存储器(SRAM)相当的性能以及与易失性动态随机存取存储器(DRAM)相当的密度和较低的功耗。与非易失性存储器(NVM)闪存相比，MRAM提供了更快的存取时间，并且随着时间的推移经受最小的退化，而闪存只能重写有限的次数。
MRAM元件的核心是磁隧道结(Magnetic tunnel junction；MTJ)，其可包括固定磁性层和自由磁性层，固定磁性层的磁化极性不可改变，自由磁性层的磁化极性可以改变。由于隧道磁电阻效应，在固定磁性层和自由磁性层之间的电阻值随着自由磁性层中的磁化极性切换而变化，从而实现磁性存储器的写入。
但是，内存密度是将MRAM推向主要内存/存储市场的关键限制因素之一，因此，如何提高磁性存储器的密度是目前亟需解决的问题。
发明内容
本申请所要解决的技术问题是，提供一种高密度的磁性存储器及其读写方法。
为了解决上述问题，本申请提供了一种磁性存储器，其包括至少一单元层，所述单元层包括：若干条平行的第一导线，位于第一平面内；若干条平行的第二导线，位于第二平面内，且所述第一平面与所述第二平面平行，所述第二导线在所述第一平面上的投影与所述第一导线交叉；若干个存储元件，设置在所述第一平面与所述第二平面之间，所述存储元件包括沿垂直所述第一平面方向串联设置的磁隧道结及双向选通器件，所述磁隧道结与所述第一导线连接，所述双向选通器件与所述第二导线连接，所述双向选通器件被配置为在被施加阈值电压和/或阈值电流时导通。
进一步，所述磁隧道结包括：连接至所述第一导线的自由层；设置在所述自由层上表面的非磁性绝缘层；设置在所述非磁性绝缘层上表面的固定层，所述自由层的磁矩方向可变，所述固定层的磁矩方向固定；所述双向选通器件的一端与所述固定层连接，另一端与所述第二导线连接。
进一步，所述第一导线包括第一端及第二端，所述磁性存储器还包括若干条写入位线及若干个第一选择晶体管，所述第一选择晶体管被配置为响应于第一控制信号而电连接所述第一导线的第一端和所述写入位线。
进一步，所述磁性存储器还包括源极线，所述源极线与所述第一导线的第二端电连接。
进一步，所述磁性存储器还包括若干条位线及若干个第二选择晶体管，所述第二选择晶体管被配置为响应于第二控制信号而电连接所述第二导线和所述位线。
进一步，所述第二导线在所述第一平面上的投影与所述第一导线垂直交叉。
进一步，所述磁性存储器包括多个所述单元层，多个所述单元层沿垂直所述第一平面的方向依次设置，相邻单元层连接到同一导线， 其中，所述导线在上层单元层中作为所述第一导线使用，在下层单元层中作为所述第二导线使用。
进一步，所述磁性存储器包括多个所述单元层，多个所述单元层沿垂直所述第一平面的方向依次设置，相邻单元层连接到同一导线，其中，所述导线在上层单元层及下层单元层中均作为所述第一导线或所述第二导线使用。
进一步，不同的存储元件通过所述双向选通器件作为控制开关，以实现分别控制。
进一步，所述双向选通器件的材料为掺杂的氧化铪。
本申请还提供一种磁性存储器的读写方法，所述磁性存储器包括至少一单元层，所述单元层包括：若干条平行的第一导线，位于第一平面内；若干条平行的第二导线，位于第二平面内，且所述第一平面与所述第二平面平行，所述第二导线在所述第一平面上的投影与所述第一导线交叉；若干个存储元件，设置在所述第一平面与所述第二平面之间，所述存储元件包括沿垂直所述第一平面方向串联设置的磁隧道结及双向选通器件，所述磁隧道结与所述第一导线连接，所述双向选通器件与所述第二导线连接，所述双向选通器件被配置为在被施加阈值电压和/或阈值电流时导通；
所述读写方法包括：向所述磁性存储器提供第一电流，所述第一电流流经所述第一导线，而不流经所述存储元件，使所述存储元件处于第一存储状态；向所述磁性存储器提供第二电流，所述第二电流流经选定的存储元件，使选定的存储元件由所述第一存储状态变为第二存储状态。
进一步，所述磁隧道结包括：连接至所述第一导线的自由层；设置在所述自由层上表面的非磁性绝缘层；设置在所述非磁性绝缘层上表面的固定层，所述自由层的磁矩方向可变，所述固定层的磁矩方向固定；所述双向选通器件的一端与所述固定层连接，另一端与所述第 二导线连接；所述读写方法包括：所述第一电流及所述第二电流使所述自由层的磁矩方向变化趋势相反。
进一步，所述第一电流使所述自由层的磁矩方向朝向与所述固定层的磁矩方向反向的方向变化，所述第二电流使所述自由层的磁矩方向朝向与所述固定层的磁矩方向同向的方向变化。
进一步，所述第一电流使所述自由层的磁矩方向朝向与所述固定层的磁矩方向同向的方向变化，所述第二电流使所述自由层的磁矩方向朝向与所述固定层的磁矩方向反向的方向变化。
进一步，所述第一导线包括第一端及第二端，所述磁性存储器还包括若干条写入位线及若干个第一选择晶体管，所述第一选择晶体管被配置为响应于第一控制信号而电连接所述第一导线的第一端和所述写入位线；所述读写方法包括：通过所述第一控制信号控制所述第一选择晶体管，使所述第一选择晶体管响应于所述第一控制信号，电连接所述第一导线的第一端和所述写入位线，以使所述第一电流流经所述第一导线。
进一步，所述磁性存储器还包括源极线，所述源极线能够与所述第一导线的第二端电连接，所述读写方法包括：所述第一电流自所述写入位线经所述第一导线至所述源极线，或者所述第一电流自所述源极线经所述第一导线流向所述写入位线。
进一步，所述磁性存储器还包括若干条位线及若干个第二选择晶体管，所述第二选择晶体管被配置为响应于第二控制信号而电连接所述第二导线和所述位线；所述读写方法包括：通过第二控制信号控制所述第二选择晶体管，使所述第二选择晶体管响应于所述第二控制信号，电连接所述第二导线和所述位线，使所述第二电流流经选定的存储元件。
进一步，所述读写方法还包括：在进行读操作时，向所述磁性存储器提供第三电流，所述第三电流从所述第二导线经过所述存储元件 流向所述第一导线。
进一步，不同的存储元件通过所述双向选通器件作为控制开关，以实现分别控制；向所述磁性存储器提供第二电流的步骤中，所述选定的存储元件配置为双向选通器件被施加阈值电压和/或阈值电流时的存储元件。
本申请的优点在于，改变了传统的磁性存储器设计，大大提高了磁场存储器的存储密度。
附图说明
图1是本申请第一实施例的磁性存储器的结构示意图；
图2是本申请第二实施例的磁性存储器的结构示意图；
图3是图2所示结构的前视图；
图4是本申请第三实施例的磁性存储器的前视图；
图5是本申请第四实施例的磁性存储器的前视图；
图6是本申请第五实施例的磁性存储器的前视图；
图7是本申请第六实施例的磁性存储器的读写方法的时序图。
具体实施方式
下面结合附图对本申请提供的磁性存储器及其读写方法的具体实施方式做详细说明。
图1是本申请第一实施例的磁性存储器的结构示意图，请参阅图1，本申请磁性存储器包括至少一单元层100。在本实施例中，所述磁性存储器包括一个单元层100。
所述单元层100包括若干条平行的第一导线110、若干条平行的第二导线120及若干个存储元件130。其中，所述第一导线110、第二导线120及存储元件130的数量可根据所述磁性存储器的存储需求 设置。在图1中仅示意性地绘示两条平行设置的第一导线110、三条平行设置的第二导线120及六个存储元件130，其并不构成对本申请的限制。
所述第一导线110位于第一平面(图中未绘示)内。在本实施例中，所述第一导线110沿X方向延伸，且沿Y方向平行排布，则所述第一平面为XY平面。
所述第二导线120位于第二平面(图中未绘示)内，且所述第一平面与所述第二平面平行。在本实施例中，所述第二导线120沿Y方向延伸，且沿X方向平行排布，则所述第二平面也为XY平面，所述第一平面与所述第二平面为平行的平面。
其中，所述第二导线120在所述第一平面上的投影与所述第一导线110交叉，或者说，所述第一导线110在所述第二平面上的投影与所述第二导线120交叉。具体地说，在垂直所述第一平面的方向上，所述第二导线120在所述第一平面上的投影与所述第一导线110交叉，或者说，在垂直所述第二平面的方向上，所述第一导线110在所述第二平面上的投影与所述第二导线120交叉。由于所述第一平面与所述第二平面平行，所以所述第一导线110与所述第二导线120不会直接交叉，而是两者的投影在某一平面上存在交叉。
进一步，在本实施例中，所述第二导线120在所述第一平面上的投影与所述第一导线110垂直交叉，而在本申请其他实施例中，所述第二导线120在所述第一平面上的投影与所述第一导线110并非是垂直交叉，而是以一锐角或者钝角为夹角而交叉。
进一步，为了提高所述第一导线110及所述第二导线120的导电性能，所述第一导线110及所述第二导线120可采用如下材料：重金属(例如，Pt，Ta等)，半金属(例如，MoTe 2)或硫族化物(例如，Bi xTe 1-x)。
若干个所述存储元件130设置在所述第一平面与所述第二平面 之间。即若干个所述存储元件130设置在所述第一平面与所述第二平面所形成的夹层中。每一个所述存储元件130包括沿垂直所述第一平面方向串联设置的磁隧道结131及双向选通器件132。其中，在本实施例中，所述存储元件130设置在所述第一导线110与所述第二导线120的交叉处，所述磁隧道结131与所述第一导线110连接，所述双向选通器件132与所述第二导线120连接。而在本申请其他实施例中，所述磁隧道结131也可与所述双向选通器件132的位置互换，即所述磁隧道结131与所述第二导线120连接，所述双向选通器件132与所述第一导线110连接。
其中，所述双向选通器件132被配置为在被施加阈值电压和/或阈值电流时导通。所述导通指的是所述双向选通器件132由高阻状态转变为低阻状态。具体地说，当施加在所述双向选通器件132上的电压或者电流为一阈值电压或者电流时，或超过阈值电压或者电流时，所述双向选通器件132由高阻状态转变为低阻状态，从而实现所述磁隧道结131与第二导线120的电连接。其中，所述阈值电压或者电流取决于磁隧道结131的材料性能。例如，在本实施例中，所述双向选通器件132的材料为掺杂的氧化铪，其导通阈值电压为0.25V，当施加在所述双向选通器件132的电压为0.25V或超过0.25V时，所述双向选通器件132导通，当施加在所述双向选通器件132上的电压小于0.25V时，所述双向选通器件132不导通。掺杂的氧化铪具有高的开/关比，低的导通电阻，是双向选通器件比较理想的材料。当然，其他能够实现阈值导通功能的材料也可作为所述双向选通器件132的材料，本申请不限定于此。
由于所述双向选通器件132能够在被施加阈值电压和/或阈值电流时导通，使得不同的存储元件130可通过所述双向选通器件作为控制开关，以实现存储元件130的分别控制。具体地说，若需要对某个或者某些存储元件130进行操作，则可控制该个或者该些存储元件 130对应的所述双向选通器件132导通，而其他非选定的存储元件130对应的所述双向选通器件132不导通，从而实现对存储元件130的选择性操作。
进一步，所述磁隧道结131包括连接至所述第一导线110的自由层131A、设置在所述自由层131A上表面的非磁性绝缘层131B、设置在所述非磁性绝缘层131B上表面的固定层131C。其中，所述自由层131A的磁矩方向可变，所述固定层131c的磁矩方向固定。由于隧道磁电阻效应，固定层31C和自由层131A之间的电阻值随着自由层131A中的磁矩方向切换而变化，从而实现磁性存储器的写入。
所述双向选通器件132的一端与所述固定层131C连接，另一端与所述第二导线120连接。其中，所述双向选通器件132的第一端及第二端仅为了便于描述而设置，对于所述双向选通器件132而言，其第一端及第二端并不存在区别，即所述双向选通器件132的任何一端与所述固定层131C连接均可。
本申请磁性存储器改变了传统的磁性存储器设计，大大提高了磁场存储器的存储密度。
进一步，所述第一导线110包括第一端及第二端。所述磁性存储器还包括若干条写入位线WBL及若干个第一选择晶体管WWL。所述第一选择晶体管WWL被配置为响应于第一控制信号而电连接所述第一导线110的第一端和所述写入位线WBL。
具体地说，在图1中仅示意性地绘示两个写入位线WBL及两个第一选择晶体管WWL，分别为写入位线WBL[00]及写入位线WBL[01]，第一选择晶体管WWL[00]及第一选择晶体管WWL[01]。其中，由于写入位线WBL并非是本申请改进点，因此，在附图中仅用悬挂线段示意。所述第一选择晶体管WWL[00]被配置为响应于第一控制信号而电连接所述第一导线110的第一端和所述写入位线WBL[00]，所述第一选择晶体管WWL[01]被配置为响应于第一控制信号而电连接另一所述第一 导线110的第一端和所述写入位线WBL[01]。
进一步，所述磁性存储器还包括源极线WSL，所述源极线WSL与所述第一导线110的第二端电连接，例如，通过晶体管开关电连接。具体地说，在图1中仅示意性地绘示两个源极线WSL，分别为源极线WSL[00]及源极线WSL[01]。所述源极线WSL[00]与所述第一导线110的第二端电连接，所述源极线WSL[01]与另一所述第一导线110的第二端电连接。
进一步，所述磁性存储器还包括若干条位线BBL及若干个第二选择晶体管BWL，所述第二选择晶体管BWL被配置为响应于第二控制信号而电连接所述第二导线120与所述位线BBL。具体地说，在图1中仅示意性地绘示三条位线BBL及三个第二选择晶体管BWL，分别为位线BBL[00]、位线BBL[01]、位线BBL[02]、第二选择晶体管BWL[00]、第二选择晶体管BWL[01]、第二选择晶体管BWL[02]。所述第二选择晶体管BWL[00]被配置为响应于第二控制信号而电连接所述第二导线120与所述位线BBL[00]、所述第二选择晶体管BWL[01]被配置为响应于第二控制信号而电连接所述第二导线120与所述位线BBL[01]、所述第二选择晶体管BWL[02]被配置为响应于第二控制信号而电连接所述第二导线120与所述位线BBL[02]。
为了进一步提高磁性存储器的存储密度，本申请还提供了一第二实施例。所述第二实施例与第一实施例的区别在于，第二实施例包括多个单元层，所述单元层堆叠设置。具体地说，请参阅图2及图3，其中，图2是本申请第二实施例的磁性存储器的结构示意图，图3是图2所示结构的前视图。在第二实施例中，所述磁性存储器包括多个单元层，多个所述单元层沿垂直所述第一平面的方向依次设置。在本实施例中，所述磁性存储器包括两个单元层，分别为上层单元层100A及下层单元层100B，上层单元层100A及下层单元层100B沿垂直所述第一平面的方向依次设置。
其中，相邻单元层连接到同一导线，所述导线在上层单元层100A中作为所述第一导线使用，在下层单元层100B中作为所述第二导线使用。具体地说，在本实施例中，上层单元层100A与下层单元层100B为相邻的单元层，其共用的导线为导线200。在上层单元层100A中，所述导线200与所述存储元件130的磁隧道结131连接，因此，在上层单元层100A中，所述导线200作为第一导线，在下层单元层100B中，所述导线200与所述双向选通器件132连接，因此，在下层单元层100B中，所述导线200作为第二导线。
上述第二实施例中磁性存储器仅包括两个单元层，而在本申请其他实施例中，为了进一步提高磁性存储器的存储密度，所述磁性存储器可包括多个单元层，多个所述单元层沿垂直所述第一平面的方向依次设置。请参阅图4，其是本申请第三实施例的磁性存储器的前视图，在第三实施例中，所述磁性存储器可包括多个单元层，多个所述单元层沿垂直所述第一平面的方向依次设置。在图4中示意性地绘示了5个单元层，分别为单元层100A、单元层100B、单元层100C、单元层100D及单元层100E，五个单元层沿垂直所述第一平面的方向依次设置。
其中，相邻单元层连接到同一导线，所述导线在上层单元层中作为所述第一导线使用，在下层单元层中作为所述第二导线使用。例如，在第三实施例中，单元层100A与单元层100B相邻，两者连接到导线200，则在单元层100A中，所述导线200作为第一导线使用，在单元层100B中，所述导线200作为第二导线使用；单元层100B与单元层100C相邻，两者连接到导线300，则在单元层100B中，所述导线300作为第一导线使用，在单元层100C中，所述导线300作为第二导线使用；单元层100C与单元层100D相邻，两者连接到导线400，则在单元层100C中，所述导线400作为第一导线使用，在单元层100D中，所述导线400作为第二导线使用；单元层100D与单元层100E相邻， 两者连接到导线500，则在单元层100D中，所述导线500作为第一导线使用，在单元层100E中，所述导线500作为第二导线使用。
其中，在第二实施例及第三实施例中，所有单元层的存储单元130的双向选通器件132均位于磁隧道结131的上方，使得相邻单元层共同连接的导线在上层单元层中作为所述第一导线使用，在下层单元层中作为所述第二导线使用。而在本申请其他实施例中，所述存储单元130的双向选通器件132也可位于磁隧道结131的下方，其原理与第二实施例及第三实施例相同，不再赘述。
在本申请第二实施例或者第三实施例中，相邻的单元层共同连接的导线在两层中与存储元件130的连接关系不同，即相邻的单元层共用的导线在两层中的功能不同。而本申请另一实施例还提供一种磁性存储器，其与第二实施例的区别在于，相邻的单元层共同连接的导线在两层中与存储元件130的连接关系相同，即相邻的单元层共用的导线在两层中的功能相同。即相邻单元层共用的导线在上层单元层及下层单元层中均作为所述第一导线或所述第二导线使用。
具体地说，请参阅图5，其为本申请第四实施例的磁性存储器的前视图。在第四实施例中，所述磁性存储器包括两个单元层，分别为上层单元层100A及下层单元层100B，上层单元层100A及下层单元层100B沿垂直所述第一平面的方向依次设置。
其中，上层单元层100A及下层单元层100B共同连接同一导线，所述导线在上层单元层100A及下层单元层100B中均作为所述第一导线或所述第二导线使用。具体地说，在本实施例中，所述上层单元层100A与下层单元层100B共用的导线为导线200。在上层单元层100A中，所述导线200与所述存储元件130的磁隧道结131连接，因此，在上层单元层100A中，所述导线200作为第一导线使用，在下层单元层100B中，所述导线200与所述存储元件130的磁隧道结131连接，因此，在下层单元层100B中，所述导线200也作为第一导线使 用。在本申请其他实施例中，也可将每一层的存储元件调转，使得所述导线200分别与上层单元层100A与下层单元层100B的存储元件的磁隧道结131，所述导线200作为所述第二导线使用。
上述第四实施例中磁性存储器仅包括两个单元层，而在本申请其他实施例中，为了进一步提高磁性存储器的存储密度，所述磁性存储器可包括多个单元层，多个所述单元层沿垂直所述第一平面的方向依次设置。请参阅图6，其是本申请第五实施例的磁性存储器的前视图，在第五实施例中，所述磁性存储器可包括多个单元层，多个所述单元层沿垂直所述第一平面的方向依次设置。在图6中示意性地绘示了5个单元层，分别为单元层100A、单元层100B、单元层100C、单元层100D及单元层100E，五个单元层沿垂直所述第一平面的方向依次设置。
其中，相邻单元层共同连接同一导线，所述导线在上层单元层及下层单元层中作为所述第一导线或者第二导线使用。例如，在第五实施例中，单元层100A与单元层100B相邻，两者共同连接导线200，则在单元层100A中，所述导线200作为第一导线使用，在单元层100B中，所述导线200也作为第一导线使用；单元层100B与单元层100C相邻，两者共同连接导线300，则在单元层100B中，所述导线300作为第二导线使用，在单元层100C中，所述导线300也作为第二导线使用；单元层100C与单元层100D相邻，两者共同连接导线400，则在单元层100C中，所述导线400作为第一导线使用，在单元层100D中，所述导线400也作为第一导线使用；单元层100D与单元层100E相邻，两者共同连接导线500，则在单元层100D中，所述导线500作为第二导线使用，在单元层100E中，所述导线500也作为第二导线使用。
可以理解的是，在本申请其他实施例中，也可调转每一层中存储单元130的方向，改变所述磁隧道结及双向选通器件与共用导线的连 接关系，其连接原理与第五实施例相同，不再赘述。
进一步，在本申请附图中仅示意性地绘示了第一导线、存储单元及第二导线之间的相互位置关系，在实际的半导体工艺中，在所述第一导线、存储单元及第二导线之外的空白处还会填充绝缘材料或者其他结构材料，在此不再赘述。
本申请还提供了如上所述的磁性存储器的读写方法。请参阅图1及图7，其中，图7是本申请第六实施例的磁性存储器的读写方法的时序图。
本申请读写方法包括；
擦除操作(Eraser)：向所述磁性存储器提供第一电流Ieraser，所述第一电流Ieraser流经所述第一导线110，而不流经所述存储元件130，使所述存储元件130处于第一存储状态。
其中，所述第一电流Ieraser仅流经所述第一导线110，所述第一电流Ieraser通过所述第一导线110作用于磁隧道结131，使得所述磁隧道结131的自由层131A的磁矩方向改变为同一方向，例如，与所述固定层131C的磁矩方向相同或者相反。在所述第一导线110上施加第一电流Ieraser后，与该条第一导线110连接的所有存储单元均处于同一存储状态，即第一存储状态。所述第一存储状态可为存储“0”或者存储“1”。例如，在本实施例中，在第一电流Ieraser的作用下，所述自由层131A的磁矩方向与所述固定层131C的磁矩方向相反，即所述第一存储状态为存储“1”，其可使得在执行写操作中仅需将存储“1”修改为存储“0”，大大降低了磁隧道结的损耗。需要注意的是，存储状态“1”也可表示为所述自由层131A的磁矩方向与所述固定层131C的磁矩方向相同，本领域技术人员可以根据需要自行设计。
在本实施例中，通过所述第一控制信号控制所述第一选择晶体管WWL，使所述第一选择晶体管WWL响应于所述第一控制信号，电连接 所述第一导线110的第一端和所述写入位线WBL，所述写入位线WBL处于高电平，所述源极线WSL处于低电平，所述第一电流Ieraser自所述写入位线WBL经所述第一导线110至所述源极线WSL。或者，在本申请另一实施例中，所述写入位线WBL处于低电平，所述源极线WSL处于高电平，所述第一电流Ieraser自所述源极线WSL经所述第一导线110至写入位线WBL。
写操作(Write)：向所述磁性存储器提供第二电流Iwrite，所述第二电流Iwrite流经选定的存储元件，使选定的存储元件由所述第一存储状态变为第二存储状态。
其中，不同的存储元件通过所述双向选通器件132作为控制开关，以实现分别控制。在该写操作步骤中，所述选定的存储元件配置为双向选通器件132被施加阈值电压和/或阈值电流时的存储元件。也就是说，在该步骤中，若需要对某一个存储元件130进行操作，则将其的双向选通器件132置于导通状态，从而实现该存储元件130与第一导线110及第二导线120的电连接。
在写操作步骤中，所述第二电流Iwrite流经所述存储元件130，则所述第二电流Iwrite会改变所述自由层131A的磁矩方向，使得所述自由层131A的磁矩方向与所述固定层131C的磁矩方向同向或者反向。
进一步，所述第一电流Ieraser及所述第二电流Iwrite使所述自由层的磁矩方向变化趋势相反。
例如，在本实施例中，在擦除操作中，所述第一电流Ieraser使所述自由层131A的磁矩方向朝向与所述固定层131C的磁矩方向反向的方向变化，所述第二电流Iwrite使所述自由层131A的磁矩方向朝向与所述固定层131C的磁矩方向同向的方向变化，即所述第一存储状态为存储“1”，所述第二存储状态为存储“0”。
再例如，在其他实施例中，在擦除操作中，所述第一电流Ieraser 使所述自由层131A的磁矩方向朝向与所述固定层131C的磁矩方向同向的方向变化，所述第二电流Iwrite使所述自由层131A的磁矩方向朝向与所述固定层131C的磁矩方向反向的方向变化，即所述第一存储状态为存储“0”，所述第二存储状态为存储“1”。
需要注意的是，存储“0”也可以表示为自由层131A的磁矩方向与所述固定层131C的磁矩方向反向，存储“1”同理，本领域内技术人员应当理解，这仅仅只是定义的区别，可以根据需要自行定义。
在本实施例中，通过第二控制信号控制所述第二选择晶体管BWL，使所述第二选择晶体管BWL响应于所述第二控制信号，电连接所述第二导线120与所述位线BBL，使所述第二电流Iwrite流经选定的存储元件130，从而实现将所述存储元件130的存储状态由第一存储状态变为第二存储状态的目的。
例如，通过第二控制信号控制所述第二选择晶体管BWL开启，所述位线BBL处于低电平，所述源极线WSL处于高电平，第二电流Iwrite自所述源极线WSL从所述第一导线110经过所述存储元件130、所述第二导线120流向所述位线BBL。或者，所述位线BBL处于高电平，所述源极线WSL处于低电平，第二电流Iwrite自所述位线BBL从所述第二导线120经过所述存储元件130、所述第一导线110流向所述源极线WSL。
进一步，本申请还提供了一种所述磁性存储器的读操作。
读操作(Read)，向所述磁性存储器提供第三电流，所述第三电流Iread从所述第二导线120经过所述存储元件130流向所述第一导线110。
其中，与写操作步骤相同，不同的存储元件通过所述双向选通器件132作为控制开关，以实现分别控制。在该读操作步骤中，若需要对某一个存储元件130进行读操作，则将其的双向选通器件132置于导通状态，其他存储元件130的双向选通器件132置于不导通状态， 从而实现该存储元件130的单独操作，以避免其他存储元件130影响读操作。
在执行读操作时，所述第三电流Iread自所述存储元件130通过，则在存储元件130两端会产生电位差，根据所述电位差的大小可确定存储元件130的电阻，从而可获得所述磁隧道结的自由层131A及固定层131C的磁矩方向的取向关系，进而可实现对存储元件130的存储状态的读取。或者也可根据第三电流Iread的大小来判断存储元件130的存储状态，本领域内技术人员可根据需要自行设计。
在本实施例中，通过第三控制信号控制所述第二选择晶体管BWL开启，使所述第二选择晶体管BWL响应于所述第三控制信号，电连接所述第二导线120与所述位线BBL，使所述第三电流I read流经选定的存储元件130，从而获得所述存储元件130的存储状态。
上述仅描述了一个单元层的读写方法，对于具有多个单元层的磁性存储器而言，其读写方法与单层相同，不再赘述。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (19)

  1. 一种磁性存储器，其特征在于，包括至少一单元层，所述单元层包括：
    若干条平行的第一导线，位于第一平面内；
    若干条平行的第二导线，位于第二平面内，且所述第一平面与所述第二平面平行，所述第二导线在所述第一平面上的投影与所述第一导线交叉；
    若干个存储元件，设置在所述第一平面与所述第二平面之间，所述存储元件包括沿垂直于所述第一平面方向串联设置的磁隧道结及双向选通器件，所述磁隧道结与所述第一导线连接，所述双向选通器件与所述第二导线连接，所述双向选通器件被配置为在被施加阈值电压和/或阈值电流时导通。
  2. 根据权利要求1所述的磁性存储器，其特征在于，所述磁隧道结包括：
    连接至所述第一导线的自由层；
    设置在所述自由层上表面的非磁性绝缘层；
    设置在所述非磁性绝缘层上表面的固定层，所述自由层的磁矩方向可变，所述固定层的磁矩方向固定；
    所述双向选通器件的一端与所述固定层连接，另一端与所述第二导线连接。
  3. 根据权利要求1所述的磁性存储器，其特征在于，所述第一导线包括第一端及第二端，所述磁性存储器还包括若干条写入位线及若干个第一选择晶体管，所述第一选择晶体管被配置为响应于第一控制信号而电连接所述第一导线的第一端和所述写入位线。
  4. 根据权利要求3所述的磁性存储器，其特征在于，所述磁性存储器还包括源极线，所述源极线与所述第一导线的第二端电连接。
  5. 根据权利要求1所述的磁性存储器，其特征在于，所述磁性存 储器还包括若干条位线及若干个第二选择晶体管，所述第二选择晶体管被配置为响应于第二控制信号而电连接所述第二导线和所述位线。
  6. 根据权利要求1所述的磁性存储器，其特征在于，所述第二导线在所述第一平面上的投影与所述第一导线垂直交叉。
  7. 根据权利要求1所述的磁性存储器，其特征在于，所述磁性存储器包括多个所述单元层，多个所述单元层沿垂直所述第一平面的方向依次设置，相邻单元层共同连接同一导线，其中，所述导线在上层单元层中作为所述第一导线使用，在下层单元层中作为所述第二导线使用。
  8. 根据权利要求1所述的磁性存储器，其特征在于，所述磁性存储器包括多个所述单元层，多个所述单元层沿垂直所述第一平面的方向依次设置，相邻单元层共同连接同一导线，其中，所述导线在上层单元层及下层单元层中均作为所述第一导线或所述第二导线使用。
  9. 根据权利要求1所述的磁性存储器，其特征在于，不同的存储元件通过所述双向选通器件作为控制开关，以实现分别控制。
  10. 根据权利要求1所述的磁性存储器，其特征在于，所述双向选通器件的材料为掺杂的氧化铪。
  11. 一种磁性存储器的读写方法，其特征在于，所述磁性存储器包括至少一单元层，所述单元层包括：
    若干条平行的第一导线，位于第一平面内；
    若干条平行的第二导线，位于第二平面内，且所述第一平面与所述第二平面平行，所述第二导线在所述第一平面上的投影与所述第一导线交叉；
    若干个存储元件，设置在所述第一平面与所述第二平面之间，所述存储元件包括沿垂直所述第一平面方向串联设置的磁隧道结及双向选通器件，所述磁隧道结与所述第一导线连接，所述双向选通器件与所述第二导线连接，所述双向选通器件被配置为在被施加阈值电压 和/或阈值电流时导通；
    所述读写方法包括：
    向所述磁性存储器提供第一电流，所述第一电流流经所述第一导线，而不流经所述存储元件，使所述存储元件处于第一存储状态；
    向所述磁性存储器提供第二电流，所述第二电流流经选定的存储元件，使选定的存储元件由所述第一存储状态变为第二存储状态。
  12. 根据权利要求11所述的读写方法，其特征在于，所述磁隧道结包括：
    连接至所述第一导线的自由层；
    设置在所述自由层上表面的非磁性绝缘层；
    设置在所述非磁性绝缘层上表面的固定层，所述自由层的磁矩方向可变，所述固定层的磁矩方向固定；
    所述双向选通器件的一端与所述固定层连接，另一端与所述第二导线连接；
    所述读写方法包括：
    所述第一电流及所述第二电流使所述自由层的磁矩方向变化趋势相反。
  13. 根据权利要求12所述的读写方法，其特征在于，所述第一电流使所述自由层的磁矩方向朝向与所述固定层的磁矩方向反向的方向变化，所述第二电流使所述自由层的磁矩方向朝向与所述固定层的磁矩方向同向的方向变化。
  14. 根据权利要求12所述的读写方法，其特征在于，所述第一电流使所述自由层的磁矩方向朝向与所述固定层的磁矩方向同向的方向变化，所述第二电流使所述自由层的磁矩方向朝向与所述固定层的磁矩方向反向的方向变化。
  15. 根据权利要求11所述的读写方法，其特征在于，所述第一导线包括第一端及第二端，所述磁性存储器还包括若干条写入位线及若 干个第一选择晶体管，所述第一选择晶体管被配置为响应于第一控制信号而电连接所述第一导线的第一端和所述写入位线；
    所述读写方法包括：
    通过所述第一控制信号控制所述第一选择晶体管，使所述第一选择晶体管响应于所述第一控制信号，电连接所述第一导线的第一端和所述写入位线，以使所述第一电流流经所述第一导线。
  16. 根据权利要求15所述的读写方法，其特征在于，所述磁性存储器还包括源极线，所述源极线能够与所述第一导线的第二端电连接，
    所述读写方法包括：所述第一电流自所述写入位线经所述第一导线至所述源极线，或者所述第一电流自所述源极线经所述第一导线流向所述写入位线。
  17. 根据权利要求11所述的读写方法，其特征在于，所述磁性存储器还包括若干条位线及若干个第二选择晶体管，所述第二选择晶体管被配置为响应于第二控制信号而电连接所述第二导线和所述位线；
    所述读写方法包括：
    通过第二控制信号控制所述第二选择晶体管，使所述第二选择晶体管响应于所述第二控制信号，电连接所述第二导线和所述位线，使所述第二电流流经选定的存储元件。
  18. 根据权利要求11所述的读写方法，其特征在于，所述读写方法还包括：在进行读操作时，向所述磁性存储器提供第三电流，所述第三电流从所述第二导线经过所述存储元件流向所述第一导线。
  19. 根据权利要求11所述的读写方法，其特征在于，不同的存储元件通过所述双向选通器件作为控制开关，以实现分别控制；向所述磁性存储器提供第二电流的步骤中，所述选定的存储元件配置为双向选通器件被施加阈值电压和/或阈值电流时的存储元件。
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